3,5c3,5
< sim_seconds 2.824356 # Number of seconds simulated
< sim_ticks 2824356167500 # Number of ticks simulated
< final_tick 2824356167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.824341 # Number of seconds simulated
> sim_ticks 2824340874000 # Number of ticks simulated
> final_tick 2824340874000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 95847 # Simulator instruction rate (inst/s)
< host_op_rate 116283 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2253286315 # Simulator tick rate (ticks/s)
< host_mem_usage 605880 # Number of bytes of host memory used
< host_seconds 1253.44 # Real time elapsed on the host
< sim_insts 120137953 # Number of instructions simulated
< sim_ops 145753814 # Number of ops (including micro ops) simulated
---
> host_inst_rate 96866 # Simulator instruction rate (inst/s)
> host_op_rate 117519 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2277239721 # Simulator tick rate (ticks/s)
> host_mem_usage 609056 # Number of bytes of host memory used
> host_seconds 1240.25 # Real time elapsed on the host
> sim_insts 120137719 # Number of instructions simulated
> sim_ops 145752951 # Number of ops (including micro ops) simulated
16,33d15
< system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory
< system.realview.nvmem.bytes_read::cpu1.inst 208 # Number of bytes read from this memory
< system.realview.nvmem.bytes_read::total 336 # Number of bytes read from this memory
< system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_inst_read::cpu1.inst 208 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_inst_read::total 336 # Number of instructions bytes read from this memory
< system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
< system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory
< system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory
< system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_read::cpu1.inst 74 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_read::total 119 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::cpu1.inst 74 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::total 119 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bw_total::cpu1.inst 74 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bw_total::total 119 # Total bandwidth to/from this memory (bytes/s)
35,49c17,31
< system.physmem.bytes_read::cpu0.dtb.walker 1984 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.inst 286048 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 1048060 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 10518784 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 32848 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 551328 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 1337024 # Number of bytes read from this memory
< system.physmem.bytes_read::total 13777996 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 286048 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 32848 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 318896 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7262976 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 2176 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.itb.walker 512 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.inst 286816 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 1046908 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 10513536 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 31952 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 549344 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 1344384 # Number of bytes read from this memory
> system.physmem.bytes_read::total 13777356 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 286816 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 31952 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 318768 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7262336 # Number of bytes written to this memory
53c35
< system.physmem.bytes_written::total 9599056 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 9598416 # Number of bytes written to this memory
55,66c37,48
< system.physmem.num_reads::cpu0.dtb.walker 31 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.inst 6715 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 16901 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 164356 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 580 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 8638 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 20891 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 218142 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 113484 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu0.dtb.walker 34 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.itb.walker 8 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.inst 6727 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 16883 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 164274 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 566 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 8607 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 21006 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 218132 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 113474 # Number of write requests responded to by this memory
70c52
< system.physmem.num_writes::total 154144 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 154134 # Number of write requests responded to by this memory
72,87c54,69
< system.physmem.bw_read::cpu0.dtb.walker 702 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.inst 101279 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 371079 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 3724312 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 249 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 11630 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 195205 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 473391 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 4878279 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 101279 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 11630 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 112909 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2571551 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::realview.ide 820837 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.dtb.walker 770 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.itb.walker 181 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.inst 101551 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 370673 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 3722474 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 11313 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 194503 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 475999 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 4878078 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 101551 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 11313 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 112865 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2571338 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::realview.ide 820841 # Write bandwidth from this memory (bytes/s)
90,113c72,95
< system.physmem.bw_write::total 3398671 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2571551 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 821177 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 702 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 101279 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 377348 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 3724312 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 249 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 11630 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 195219 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 473391 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 8276949 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 218142 # Number of read requests accepted
< system.physmem.writeReqs 154144 # Number of write requests accepted
< system.physmem.readBursts 218142 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 154144 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 13946624 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 14464 # Total number of bytes read from write queue
< system.physmem.bytesWritten 9613440 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 13777996 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 9599056 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 226 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_write::total 3398462 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2571338 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 821181 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 770 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.itb.walker 181 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 101551 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 376942 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 3722474 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 227 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 11313 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 194518 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 475999 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 8276541 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 218132 # Number of read requests accepted
> system.physmem.writeReqs 154134 # Number of write requests accepted
> system.physmem.readBursts 218132 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 154134 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 13944832 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 15616 # Total number of bytes read from write queue
> system.physmem.bytesWritten 9612032 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 13777356 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 9598416 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 244 # Number of DRAM read bursts serviced by the write queue
115,147c97,129
< system.physmem.neitherReadNorWriteReqs 13812 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 13742 # Per bank write bursts
< system.physmem.perBankRdBursts::1 13629 # Per bank write bursts
< system.physmem.perBankRdBursts::2 14383 # Per bank write bursts
< system.physmem.perBankRdBursts::3 14277 # Per bank write bursts
< system.physmem.perBankRdBursts::4 15951 # Per bank write bursts
< system.physmem.perBankRdBursts::5 13005 # Per bank write bursts
< system.physmem.perBankRdBursts::6 13913 # Per bank write bursts
< system.physmem.perBankRdBursts::7 13901 # Per bank write bursts
< system.physmem.perBankRdBursts::8 13634 # Per bank write bursts
< system.physmem.perBankRdBursts::9 13374 # Per bank write bursts
< system.physmem.perBankRdBursts::10 12813 # Per bank write bursts
< system.physmem.perBankRdBursts::11 11699 # Per bank write bursts
< system.physmem.perBankRdBursts::12 13387 # Per bank write bursts
< system.physmem.perBankRdBursts::13 14173 # Per bank write bursts
< system.physmem.perBankRdBursts::14 13330 # Per bank write bursts
< system.physmem.perBankRdBursts::15 12705 # Per bank write bursts
< system.physmem.perBankWrBursts::0 9697 # Per bank write bursts
< system.physmem.perBankWrBursts::1 9775 # Per bank write bursts
< system.physmem.perBankWrBursts::2 10292 # Per bank write bursts
< system.physmem.perBankWrBursts::3 9920 # Per bank write bursts
< system.physmem.perBankWrBursts::4 9082 # Per bank write bursts
< system.physmem.perBankWrBursts::5 9049 # Per bank write bursts
< system.physmem.perBankWrBursts::6 9470 # Per bank write bursts
< system.physmem.perBankWrBursts::7 9454 # Per bank write bursts
< system.physmem.perBankWrBursts::8 9424 # Per bank write bursts
< system.physmem.perBankWrBursts::9 9315 # Per bank write bursts
< system.physmem.perBankWrBursts::10 9173 # Per bank write bursts
< system.physmem.perBankWrBursts::11 8636 # Per bank write bursts
< system.physmem.perBankWrBursts::12 9486 # Per bank write bursts
< system.physmem.perBankWrBursts::13 9567 # Per bank write bursts
< system.physmem.perBankWrBursts::14 9156 # Per bank write bursts
< system.physmem.perBankWrBursts::15 8714 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 13729 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 13731 # Per bank write bursts
> system.physmem.perBankRdBursts::1 13637 # Per bank write bursts
> system.physmem.perBankRdBursts::2 14382 # Per bank write bursts
> system.physmem.perBankRdBursts::3 14282 # Per bank write bursts
> system.physmem.perBankRdBursts::4 15946 # Per bank write bursts
> system.physmem.perBankRdBursts::5 13017 # Per bank write bursts
> system.physmem.perBankRdBursts::6 13909 # Per bank write bursts
> system.physmem.perBankRdBursts::7 13917 # Per bank write bursts
> system.physmem.perBankRdBursts::8 13612 # Per bank write bursts
> system.physmem.perBankRdBursts::9 13371 # Per bank write bursts
> system.physmem.perBankRdBursts::10 12787 # Per bank write bursts
> system.physmem.perBankRdBursts::11 11726 # Per bank write bursts
> system.physmem.perBankRdBursts::12 13349 # Per bank write bursts
> system.physmem.perBankRdBursts::13 14174 # Per bank write bursts
> system.physmem.perBankRdBursts::14 13344 # Per bank write bursts
> system.physmem.perBankRdBursts::15 12704 # Per bank write bursts
> system.physmem.perBankWrBursts::0 9692 # Per bank write bursts
> system.physmem.perBankWrBursts::1 9790 # Per bank write bursts
> system.physmem.perBankWrBursts::2 10299 # Per bank write bursts
> system.physmem.perBankWrBursts::3 9942 # Per bank write bursts
> system.physmem.perBankWrBursts::4 9060 # Per bank write bursts
> system.physmem.perBankWrBursts::5 9040 # Per bank write bursts
> system.physmem.perBankWrBursts::6 9465 # Per bank write bursts
> system.physmem.perBankWrBursts::7 9428 # Per bank write bursts
> system.physmem.perBankWrBursts::8 9418 # Per bank write bursts
> system.physmem.perBankWrBursts::9 9301 # Per bank write bursts
> system.physmem.perBankWrBursts::10 9150 # Per bank write bursts
> system.physmem.perBankWrBursts::11 8663 # Per bank write bursts
> system.physmem.perBankWrBursts::12 9463 # Per bank write bursts
> system.physmem.perBankWrBursts::13 9594 # Per bank write bursts
> system.physmem.perBankWrBursts::14 9165 # Per bank write bursts
> system.physmem.perBankWrBursts::15 8718 # Per bank write bursts
149,150c131,132
< system.physmem.numWrRetry 9 # Number of times write queue was full causing retry
< system.physmem.totGap 2824354558500 # Total gap between requests
---
> system.physmem.numWrRetry 4 # Number of times write queue was full causing retry
> system.physmem.totGap 2824339295000 # Total gap between requests
157c139
< system.physmem.readPktSize::6 214472 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 214462 # Read request sizes (log2)
164,181c146,163
< system.physmem.writePktSize::6 149708 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 53602 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 76817 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 20742 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 15242 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 11051 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 9710 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 8839 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 8210 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 7163 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 2472 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1433 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 1086 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 621 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 437 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 277 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 206 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 5 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 149698 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 53523 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 76682 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 20695 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 15255 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 11067 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 9733 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 8849 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 8196 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 7196 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 2474 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1465 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 1103 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 647 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 481 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 305 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 208 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see
183c165
< system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
212,214c194,196
< system.physmem.wrQLenPdf::15 2929 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3545 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4158 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 2920 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3538 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4134 # What write queue length does an incoming req see
216,235c198,217
< system.physmem.wrQLenPdf::19 5623 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6990 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7782 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 8751 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 9680 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 10891 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 10789 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 10809 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 10760 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 11318 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 9435 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 9260 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 9292 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 8709 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 893 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 622 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 394 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 295 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 223 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 198 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::19 5600 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6932 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7778 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 8822 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 9717 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 10984 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 10866 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 10869 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 10841 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 11416 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 9525 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 9280 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 9219 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 8573 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 815 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 525 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 368 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 269 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 234 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 200 # What write queue length does an incoming req see
237,249c219,231
< system.physmem.wrQLenPdf::40 192 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 180 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 167 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 165 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 139 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 126 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 85 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 62 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 46 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 40 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::40 181 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 162 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 152 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 161 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 159 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 118 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 104 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 92 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 58 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 39 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 36 # What write queue length does an incoming req see
252,253c234,235
< system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::55 29 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 30 # What write queue length does an incoming req see
255,278c237,260
< system.physmem.wrQLenPdf::58 19 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 14 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 92866 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 253.699567 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 143.705803 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 308.390709 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 46941 50.55% 50.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 18915 20.37% 70.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6813 7.34% 78.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3565 3.84% 82.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3222 3.47% 85.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2153 2.32% 87.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1230 1.32% 89.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1078 1.16% 90.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8949 9.64% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 92866 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 7533 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 28.928183 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 527.934330 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 7532 99.99% 99.99% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 92801 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 253.842782 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 143.815283 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 308.388546 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 46919 50.56% 50.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 18870 20.33% 70.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6768 7.29% 78.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3705 3.99% 82.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3168 3.41% 85.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2103 2.27% 87.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1242 1.34% 89.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1089 1.17% 90.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8937 9.63% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 92801 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 7531 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 28.931483 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 528.461754 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 7530 99.99% 99.99% # Reads before turning the bus around for writes
280,318c262,302
< system.physmem.rdPerTurnAround::total 7533 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 7533 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 19.940263 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.639504 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 10.756386 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 6124 81.30% 81.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 560 7.43% 88.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 110 1.46% 90.19% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 221 2.93% 93.12% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 195 2.59% 95.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 21 0.28% 95.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 17 0.23% 96.22% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 21 0.28% 96.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 30 0.40% 96.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 8 0.11% 97.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 3 0.04% 97.04% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 3 0.04% 97.08% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 162 2.15% 99.23% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 7 0.09% 99.32% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 6 0.08% 99.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 5 0.07% 99.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 13 0.17% 99.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 1 0.01% 99.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 1 0.01% 99.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 7 0.09% 99.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 2 0.03% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 1 0.01% 99.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 1 0.01% 99.81% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 2 0.03% 99.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 3 0.04% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 1 0.01% 99.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 3 0.04% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 3 0.04% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 2 0.03% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 7533 # Writes before turning the bus around for reads
< system.physmem.totQLat 8921648500 # Total ticks spent queuing
< system.physmem.totMemAccLat 13007573500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1089580000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 40940.77 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 7531 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 7531 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 19.942637 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.618581 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 11.035986 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 6139 81.52% 81.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 568 7.54% 89.06% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 91 1.21% 90.27% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 228 3.03% 93.29% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 184 2.44% 95.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 18 0.24% 95.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 26 0.35% 96.32% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 11 0.15% 96.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 33 0.44% 96.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 5 0.07% 96.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 10 0.13% 97.11% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 1 0.01% 97.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 156 2.07% 99.19% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 9 0.12% 99.31% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 4 0.05% 99.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 1 0.01% 99.38% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 13 0.17% 99.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 1 0.01% 99.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 3 0.04% 99.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 4 0.05% 99.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 1 0.01% 99.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 3 0.04% 99.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 2 0.03% 99.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 4 0.05% 99.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 4 0.05% 99.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 1 0.01% 99.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 1 0.01% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 6 0.08% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 2 0.03% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 1 0.01% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::180-183 1 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 7531 # Writes before turning the bus around for reads
> system.physmem.totQLat 8907181250 # Total ticks spent queuing
> system.physmem.totMemAccLat 12992581250 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1089440000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 40879.63 # Average queueing delay per DRAM burst
320c304
< system.physmem.avgMemAccLat 59690.77 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 59629.63 # Average memory access latency per DRAM burst
329,338c313,322
< system.physmem.avgRdQLen 1.74 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 22.17 # Average write queue length when enqueuing
< system.physmem.readRowHits 185257 # Number of row buffer hits during reads
< system.physmem.writeRowHits 90003 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 85.01 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 59.91 # Row buffer hit rate for writes
< system.physmem.avgGap 7586518.32 # Average gap between requests
< system.physmem.pageHitRate 74.77 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 2697281054000 # Time in different power states
< system.physmem.memoryStateTime::REF 94311360000 # Time in different power states
---
> system.physmem.avgRdQLen 1.59 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 21.20 # Average write queue length when enqueuing
> system.physmem.readRowHits 185267 # Number of row buffer hits during reads
> system.physmem.writeRowHits 90008 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 85.03 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 59.92 # Row buffer hit rate for writes
> system.physmem.avgGap 7586884.90 # Average gap between requests
> system.physmem.pageHitRate 74.78 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 2697410352000 # Time in different power states
> system.physmem.memoryStateTime::REF 94310840000 # Time in different power states
340c324
< system.physmem.memoryStateTime::ACT 32761026000 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 32616675500 # Time in different power states
342,364c326,366
< system.physmem.actEnergy::0 364739760 # Energy for activate commands per rank (pJ)
< system.physmem.actEnergy::1 337327200 # Energy for activate commands per rank (pJ)
< system.physmem.preEnergy::0 199014750 # Energy for precharge commands per rank (pJ)
< system.physmem.preEnergy::1 184057500 # Energy for precharge commands per rank (pJ)
< system.physmem.readEnergy::0 879847800 # Energy for read commands per rank (pJ)
< system.physmem.readEnergy::1 819897000 # Energy for read commands per rank (pJ)
< system.physmem.writeEnergy::0 497268720 # Energy for write commands per rank (pJ)
< system.physmem.writeEnergy::1 476092080 # Energy for write commands per rank (pJ)
< system.physmem.refreshEnergy::0 184473020160 # Energy for refresh commands per rank (pJ)
< system.physmem.refreshEnergy::1 184473020160 # Energy for refresh commands per rank (pJ)
< system.physmem.actBackEnergy::0 78882264090 # Energy for active background per rank (pJ)
< system.physmem.actBackEnergy::1 78474830085 # Energy for active background per rank (pJ)
< system.physmem.preBackEnergy::0 1625417087250 # Energy for precharge background per rank (pJ)
< system.physmem.preBackEnergy::1 1625774485500 # Energy for precharge background per rank (pJ)
< system.physmem.totalEnergy::0 1890713242530 # Total energy per rank (pJ)
< system.physmem.totalEnergy::1 1890539709525 # Total energy per rank (pJ)
< system.physmem.averagePower::0 669.432241 # Core power per rank (mW)
< system.physmem.averagePower::1 669.370799 # Core power per rank (mW)
< system.membus.trans_dist::ReadReq 237803 # Transaction distribution
< system.membus.trans_dist::ReadResp 237803 # Transaction distribution
< system.membus.trans_dist::WriteReq 30981 # Transaction distribution
< system.membus.trans_dist::WriteResp 30981 # Transaction distribution
< system.membus.trans_dist::Writeback 113484 # Transaction distribution
---
> system.physmem.actEnergy::0 364754880 # Energy for activate commands per rank (pJ)
> system.physmem.actEnergy::1 336820680 # Energy for activate commands per rank (pJ)
> system.physmem.preEnergy::0 199023000 # Energy for precharge commands per rank (pJ)
> system.physmem.preEnergy::1 183781125 # Energy for precharge commands per rank (pJ)
> system.physmem.readEnergy::0 880003800 # Energy for read commands per rank (pJ)
> system.physmem.readEnergy::1 819522600 # Energy for read commands per rank (pJ)
> system.physmem.writeEnergy::0 497119680 # Energy for write commands per rank (pJ)
> system.physmem.writeEnergy::1 476098560 # Energy for write commands per rank (pJ)
> system.physmem.refreshEnergy::0 184472003040 # Energy for refresh commands per rank (pJ)
> system.physmem.refreshEnergy::1 184472003040 # Energy for refresh commands per rank (pJ)
> system.physmem.actBackEnergy::0 78880301865 # Energy for active background per rank (pJ)
> system.physmem.actBackEnergy::1 78435436815 # Energy for active background per rank (pJ)
> system.physmem.preBackEnergy::0 1625409465000 # Energy for precharge background per rank (pJ)
> system.physmem.preBackEnergy::1 1625799697500 # Energy for precharge background per rank (pJ)
> system.physmem.totalEnergy::0 1890702671265 # Total energy per rank (pJ)
> system.physmem.totalEnergy::1 1890523360320 # Total energy per rank (pJ)
> system.physmem.averagePower::0 669.432189 # Core power per rank (mW)
> system.physmem.averagePower::1 669.368701 # Core power per rank (mW)
> system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory
> system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory
> system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s)
> system.membus.trans_dist::ReadReq 237823 # Transaction distribution
> system.membus.trans_dist::ReadResp 237823 # Transaction distribution
> system.membus.trans_dist::WriteReq 30977 # Transaction distribution
> system.membus.trans_dist::WriteResp 30977 # Transaction distribution
> system.membus.trans_dist::Writeback 113474 # Transaction distribution
367,371c369,373
< system.membus.trans_dist::UpgradeReq 79622 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 40753 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 13812 # Transaction distribution
< system.membus.trans_dist::ReadExReq 31225 # Transaction distribution
< system.membus.trans_dist::ReadExResp 14907 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 79489 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 40661 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 13729 # Transaction distribution
> system.membus.trans_dist::ReadExReq 31194 # Transaction distribution
> system.membus.trans_dist::ReadExResp 14874 # Transaction distribution
373,376c375,378
< system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13750 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 709115 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 830877 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13738 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 708779 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 830527 # Packet count per connected master and slave (bytes)
379c381
< system.membus.pkt_count::total 903587 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 903237 # Packet count per connected master and slave (bytes)
381,384c383,386
< system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 336 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27500 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21057756 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 21248442 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27476 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21056476 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 21247122 # Cumulative packet size per connected master and slave (bytes)
387,389c389,391
< system.membus.pkt_size::total 23567738 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 123113 # Total snoops (count)
< system.membus.snoop_fanout::samples 501114 # Request fanout histogram
---
> system.membus.pkt_size::total 23566418 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 122973 # Total snoops (count)
> system.membus.snoop_fanout::samples 500866 # Request fanout histogram
394c396
< system.membus.snoop_fanout::1 501114 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 500866 100.00% 100.00% # Request fanout histogram
399,400c401,402
< system.membus.snoop_fanout::total 501114 # Request fanout histogram
< system.membus.reqLayer0.occupancy 81319989 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 500866 # Request fanout histogram
> system.membus.reqLayer0.occupancy 81235490 # Layer occupancy (ticks)
402c404
< system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 26500 # Layer occupancy (ticks)
404c406
< system.membus.reqLayer2.occupancy 11512493 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 11626497 # Layer occupancy (ticks)
406c408
< system.membus.reqLayer5.occupancy 1643090249 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 1642596998 # Layer occupancy (ticks)
408c410
< system.membus.respLayer2.occupancy 2114237552 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 2113984385 # Layer occupancy (ticks)
410c412
< system.membus.respLayer3.occupancy 38543657 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 38546403 # Layer occupancy (ticks)
413,417c415,419
< system.l2c.tags.replacements 153338 # number of replacements
< system.l2c.tags.tagsinuse 64407.351795 # Cycle average of tags in use
< system.l2c.tags.total_refs 520948 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 218016 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 2.389494 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 153419 # number of replacements
> system.l2c.tags.tagsinuse 64440.075057 # Cycle average of tags in use
> system.l2c.tags.total_refs 521049 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 218085 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 2.389201 # Average number of references to valid blocks.
419,450c421,452
< system.l2c.tags.occ_blocks::writebacks 14039.109160 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 10.926266 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 1.063683 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 1406.687456 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 2124.369402 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39350.084930 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.463090 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 0.906491 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 305.066680 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 911.182744 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6250.491894 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.214220 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000167 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.021464 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.032415 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.600435 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000114 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.004655 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.013904 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.095375 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.982778 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 44311 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 20347 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 406 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 7760 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 36145 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
---
> system.l2c.tags.occ_blocks::writebacks 14106.989110 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.481706 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 2.879098 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 1413.448081 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 2144.570039 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39278.457251 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.502209 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.itb.walker 0.002709 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 292.869735 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 885.757521 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6295.117598 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.215256 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000221 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.000044 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.021568 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.032724 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.599342 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000084 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.004469 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.013516 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.096056 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.983278 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 44367 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 20280 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 411 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 7792 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 36164 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
452,473c454,475
< system.l2c.tags.age_task_id_blocks_1024::2 348 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 4612 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 15362 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.676132 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.310471 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 6600636 # Number of tag accesses
< system.l2c.tags.data_accesses 6600636 # Number of data accesses
< system.l2c.ReadReq_hits::cpu0.dtb.walker 292 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.itb.walker 154 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.inst 12492 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 39083 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 182457 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.dtb.walker 82 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.itb.walker 48 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 4094 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 11500 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 44186 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 294388 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 252842 # number of Writeback hits
< system.l2c.Writeback_hits::total 252842 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 11706 # number of UpgradeReq hits
---
> system.l2c.tags.age_task_id_blocks_1024::2 342 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 4621 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 15296 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.676987 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.309448 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 6602520 # Number of tag accesses
> system.l2c.tags.data_accesses 6602520 # Number of data accesses
> system.l2c.ReadReq_hits::cpu0.dtb.walker 282 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.itb.walker 122 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.inst 12559 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 39006 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 182592 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.dtb.walker 97 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.itb.walker 55 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 4109 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 11553 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 44326 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 294701 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 252802 # number of Writeback hits
> system.l2c.Writeback_hits::total 252802 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 11705 # number of UpgradeReq hits
475,679c477,681
< system.l2c.UpgradeReq_hits::total 12433 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 197 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 154 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 351 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 3674 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 1157 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 4831 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 292 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 154 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 12492 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 42757 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 182457 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 82 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 48 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 4094 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 12657 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 44186 # number of demand (read+write) hits
< system.l2c.demand_hits::total 299219 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 292 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 154 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 12492 # number of overall hits
< system.l2c.overall_hits::cpu0.data 42757 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 182457 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 82 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 48 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 4094 # number of overall hits
< system.l2c.overall_hits::cpu1.data 12657 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 44186 # number of overall hits
< system.l2c.overall_hits::total 299219 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.dtb.walker 31 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.inst 3722 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 8649 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 164359 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.inst 492 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 1396 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 20906 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 199570 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 8911 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 2815 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 11726 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 768 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 1215 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 1983 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 7775 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 7235 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 15010 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 31 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.inst 3722 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 16424 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 164359 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 492 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 8631 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 20906 # number of demand (read+write) misses
< system.l2c.demand_misses::total 214580 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 31 # number of overall misses
< system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
< system.l2c.overall_misses::cpu0.inst 3722 # number of overall misses
< system.l2c.overall_misses::cpu0.data 16424 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 164359 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses
< system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 492 # number of overall misses
< system.l2c.overall_misses::cpu1.data 8631 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 20906 # number of overall misses
< system.l2c.overall_misses::total 214580 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2653000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.itb.walker 225500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.inst 348764246 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 769947990 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18966096321 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 875000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.itb.walker 75000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 50097250 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 119367500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2549404421 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 22807506228 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.data 7178208 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 2570892 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 9749100 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1432440 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 791466 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 2223906 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 708658416 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 564088479 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 1272746895 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 2653000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 225500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 348764246 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 1478606406 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18966096321 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 875000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 75000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 50097250 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 683455979 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2549404421 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 24080253123 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 2653000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 225500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 348764246 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 1478606406 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18966096321 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 875000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 75000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 50097250 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 683455979 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2549404421 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 24080253123 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.dtb.walker 323 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.itb.walker 157 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.inst 16214 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 47732 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 346816 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.dtb.walker 93 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.itb.walker 49 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 4586 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 12896 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 65092 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 493958 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 252842 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 252842 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 20617 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 3542 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 24159 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 965 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 1369 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 2334 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 11449 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 8392 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 19841 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 323 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 157 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 16214 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 59181 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 346816 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 93 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 49 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 4586 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 21288 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 65092 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 513799 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 323 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 157 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 16214 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 59181 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 346816 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 93 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 49 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 4586 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 21288 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 65092 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 513799 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.095975 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019108 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.229555 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.181199 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.473908 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.118280 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.020408 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.107283 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.108251 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.321176 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.404022 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.432216 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.794749 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.485368 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.795855 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.887509 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.849614 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.679099 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.862131 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.756514 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.095975 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.019108 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.229555 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.277522 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.473908 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.118280 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.020408 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.107283 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.405440 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.321176 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.417634 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.095975 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.019108 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.229555 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.277522 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.473908 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.118280 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.020408 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.107283 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.405440 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.321176 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.417634 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 85580.645161 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75166.666667 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 93703.451370 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 89021.619840 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 115394.327789 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79545.454545 # average ReadReq miss latency
---
> system.l2c.UpgradeReq_hits::total 12432 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 184 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 173 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 357 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 3642 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 1229 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 4871 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 282 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 122 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 12559 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 42648 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 182592 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 97 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 55 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 4109 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 12782 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 44326 # number of demand (read+write) hits
> system.l2c.demand_hits::total 299572 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 282 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 122 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 12559 # number of overall hits
> system.l2c.overall_hits::cpu0.data 42648 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 182592 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 97 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 55 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 4109 # number of overall hits
> system.l2c.overall_hits::cpu1.data 12782 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 44326 # number of overall hits
> system.l2c.overall_hits::total 299572 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.dtb.walker 34 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.itb.walker 8 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.inst 3733 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 8647 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 164277 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.itb.walker 2 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.inst 479 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 1383 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21024 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 199597 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 8851 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 2828 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 11679 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 749 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 1203 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 1952 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 7757 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 7215 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 14972 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 34 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.itb.walker 8 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.inst 3733 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 16404 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 164277 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.itb.walker 2 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 479 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 8598 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 21024 # number of demand (read+write) misses
> system.l2c.demand_misses::total 214569 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 34 # number of overall misses
> system.l2c.overall_misses::cpu0.itb.walker 8 # number of overall misses
> system.l2c.overall_misses::cpu0.inst 3733 # number of overall misses
> system.l2c.overall_misses::cpu0.data 16404 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 164277 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses
> system.l2c.overall_misses::cpu1.itb.walker 2 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 479 # number of overall misses
> system.l2c.overall_misses::cpu1.data 8598 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 21024 # number of overall misses
> system.l2c.overall_misses::total 214569 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2727250 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.itb.walker 613750 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.inst 350075996 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 761569744 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18989592837 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 768250 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.itb.walker 150000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 47537750 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 122331750 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2522463904 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 22797831231 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.data 6376742 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 2877882 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 9254624 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1147452 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1135953 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 2283405 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 711214419 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 562948982 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 1274163401 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 2727250 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 613750 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 350075996 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 1472784163 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18989592837 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 768250 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.itb.walker 150000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 47537750 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 685280732 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2522463904 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 24071994632 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 2727250 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 613750 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 350075996 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 1472784163 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18989592837 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 768250 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.itb.walker 150000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 47537750 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 685280732 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2522463904 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 24071994632 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.dtb.walker 316 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.itb.walker 130 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.inst 16292 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 47653 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 346869 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.dtb.walker 107 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.itb.walker 57 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 4588 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 12936 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 65350 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 494298 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 252802 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 252802 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 20556 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 3555 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 24111 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 933 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 1376 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 2309 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 11399 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 8444 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 19843 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 316 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 130 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 16292 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 59052 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 346869 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 107 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 57 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 4588 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 21380 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 65350 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 514141 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 316 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 130 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 16292 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 59052 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 346869 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 107 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 57 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 4588 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 21380 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 65350 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 514141 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.107595 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.061538 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.229131 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.181458 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.473600 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.093458 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.035088 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.104403 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.106911 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.321714 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.403799 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.430580 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.795499 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.484385 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.802787 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.874273 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.845388 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.680498 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.854453 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.754523 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.107595 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.061538 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.229131 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.277789 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.473600 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.093458 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.035088 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.104403 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.402152 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.321714 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.417335 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.107595 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.061538 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.229131 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.277789 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.473600 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.093458 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.035088 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.104403 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.402152 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.321714 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.417335 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80213.235294 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 76718.750000 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 93778.729172 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 88073.290621 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 115594.957523 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76825 # average ReadReq miss latency
681,699c683,701
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 101823.678862 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 85506.805158 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 121946.064336 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 114283.240106 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 805.544608 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 913.283126 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 831.408835 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1865.156250 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 651.412346 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 1121.485628 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91145.776977 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77966.617692 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 84793.264157 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85580.645161 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75166.666667 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 93703.451370 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 90027.180102 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 115394.327789 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79545.454545 # average overall miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 99243.736952 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 88453.904555 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 119980.208524 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 114219.308061 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 720.454412 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1017.638614 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 792.415789 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1531.978638 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 944.266833 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 1169.777152 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91686.788578 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 78024.806930 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 85103.085827 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80213.235294 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 76718.750000 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 93778.729172 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 89782.014326 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 115594.957523 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 76825 # average overall miss latency
701,710c703,712
< system.l2c.demand_avg_miss_latency::cpu1.inst 101823.678862 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 79186.186884 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 121946.064336 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 112220.398560 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85580.645161 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75166.666667 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 93703.451370 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 90027.180102 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 115394.327789 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79545.454545 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu1.inst 99243.736952 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 79702.341475 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 119980.208524 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 112187.662859 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80213.235294 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 76718.750000 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 93778.729172 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 89782.014326 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 115594.957523 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76825 # average overall miss latency
712,716c714,718
< system.l2c.overall_avg_miss_latency::cpu1.inst 101823.678862 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 79186.186884 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 121946.064336 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 112220.398560 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 435 # number of cycles access was blocked
---
> system.l2c.overall_avg_miss_latency::cpu1.inst 99243.736952 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 79702.341475 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 119980.208524 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 112187.662859 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 168 # number of cycles access was blocked
718c720
< system.l2c.blocked::no_mshrs 26 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 11 # number of cycles access was blocked
720c722
< system.l2c.avg_blocked_cycles::no_mshrs 16.730769 # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs 15.272727 # average number of cycles each access was blocked
724,726c726,728
< system.l2c.writebacks::writebacks 113484 # number of writebacks
< system.l2c.writebacks::total 113484 # number of writebacks
< system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits
---
> system.l2c.writebacks::writebacks 113474 # number of writebacks
> system.l2c.writebacks::total 113474 # number of writebacks
> system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits
728,731c730,733
< system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 15 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
---
> system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 18 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits
733,736c735,738
< system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 15 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
---
> system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 18 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits
738,885c740,887
< system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 15 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits
< system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 31 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.inst 3721 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.data 8649 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 164356 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.inst 491 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.data 1396 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 20891 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 199550 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 8911 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 2815 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 11726 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 768 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1215 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 1983 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 7775 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 7235 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 15010 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 31 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 3721 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 16424 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 164356 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 491 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 8631 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 20891 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 214560 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 31 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 3721 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 16424 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 164356 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 491 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 8631 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 20891 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 214560 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2267000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 187500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 302749246 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 662570490 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16945643071 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 738500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 43998750 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.data 101980500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2293758171 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 20353955728 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 90147824 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 28509296 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 118657120 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7897727 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12233707 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 20131434 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 612435582 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 472780517 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 1085216099 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2267000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 187500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 302749246 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 1275006072 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16945643071 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 738500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 43998750 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 574761017 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2293758171 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 21439171827 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2267000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 187500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 302749246 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 1275006072 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16945643071 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 738500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 43998750 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 574761017 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2293758171 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 21439171827 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 158715000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3685804000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5055250 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919801500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 5769375750 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2713908502 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1535177501 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 4249086003 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 158715000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6399712502 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5055250 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3454979001 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 10018461753 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.095975 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.019108 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.229493 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181199 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473900 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.118280 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.107065 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.108251 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.320946 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.403982 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.432216 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.794749 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.485368 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.795855 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.887509 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.849614 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.679099 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.862131 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.756514 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.095975 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.019108 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.229493 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.277522 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473900 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.118280 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.107065 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.405440 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.320946 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.417595 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.095975 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.019108 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.229493 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.277522 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473900 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.118280 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.107065 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.405440 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.320946 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.417595 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73129.032258 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81362.334319 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 76606.600763 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103103.282332 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67136.363636 # average ReadReq mshr miss latency
---
> system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 18 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 24 # number of overall MSHR hits
> system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 34 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 8 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.inst 3733 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 8646 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 164274 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.inst 477 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.data 1383 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 21006 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::total 199573 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 8851 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 2828 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 11679 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 749 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1203 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 1952 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 7757 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 7215 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 14972 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 34 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.itb.walker 8 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 3733 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 16403 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 164274 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.itb.walker 2 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 477 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 8598 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 21006 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 214545 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 34 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.itb.walker 8 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 3733 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 16403 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 164274 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.itb.walker 2 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 477 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 8598 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 21006 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 214545 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2306250 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 513750 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 303960496 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 654157744 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16970183087 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 643750 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 125000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 41455250 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 105134250 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2264811654 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 20343291231 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 89616766 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 28576308 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 118193074 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7674203 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12103692 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 19777895 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 615195579 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 471924516 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 1087120095 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2306250 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 513750 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 303960496 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 1269353323 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16970183087 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 643750 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 125000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 41455250 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 577058766 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2264811654 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 21430411326 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2306250 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 513750 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 303960496 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 1269353323 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16970183087 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 643750 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 125000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 41455250 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 577058766 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2264811654 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 21430411326 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 159081750 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3686341747 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5350750 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919844500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 5770618747 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2713885499 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1535420500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 4249305999 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 159081750 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6400227246 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5350750 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3455265000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 10019924746 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.107595 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.061538 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181437 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.106911 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.403750 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.430580 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.795499 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.484385 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.802787 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.874273 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.845388 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.680498 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.854453 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.754523 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.107595 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.061538 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.277772 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.402152 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.417288 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.107595 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.061538 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.277772 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.402152 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.417288 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75660.160074 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average ReadReq mshr miss latency
887,905c889,907
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 89610.488798 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73051.934097 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109796.475564 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 101999.277013 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10116.465492 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10127.636234 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10119.147194 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10283.498698 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10068.894650 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10152.009077 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78769.849775 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65346.305045 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 72299.540240 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73129.032258 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81362.334319 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77630.666829 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103103.282332 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67136.363636 # average overall mshr miss latency
---
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76018.980477 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 101934.085427 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10125.044176 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10104.776521 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10120.136484 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10245.931909 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10061.256858 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10132.118340 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79308.441279 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65408.803326 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 72610.212063 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77385.436993 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average overall mshr miss latency
907,916c909,918
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 89610.488798 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66592.633183 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109796.475564 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 99921.568918 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73129.032258 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81362.334319 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77630.666829 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103103.282332 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67136.363636 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67115.464759 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 99887.722044 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77385.436993 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average overall mshr miss latency
918,921c920,923
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 89610.488798 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66592.633183 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109796.475564 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 99921.568918 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67115.464759 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 99887.722044 # average overall mshr miss latency
973,995c975,997
< system.toL2Bus.trans_dist::ReadReq 660507 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 660492 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 30981 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 30981 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 252842 # Transaction distribution
< system.toL2Bus.trans_dist::WriteInvalidateReq 36233 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 91952 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 41104 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 133056 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 40101 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 40101 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1300560 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426210 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 1726770 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 40798474 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8541616 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 49340090 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 291850 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 1084776 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 1.033629 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.180273 # Request fanout histogram
---
> system.toL2Bus.trans_dist::ReadReq 660487 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 660472 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 30977 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 30977 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 252802 # Transaction distribution
> system.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 91823 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 41018 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 132841 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 40090 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 40090 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1299997 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426747 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 1726744 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 40789878 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8569500 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 49359378 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 291335 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 1084475 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 1.033634 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.180285 # Request fanout histogram
998,999c1000,1001
< system.toL2Bus.snoop_fanout::1 1048296 96.64% 96.64% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 36480 3.36% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::1 1048000 96.64% 96.64% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 36475 3.36% 100.00% # Request fanout histogram
1003,1004c1005,1006
< system.toL2Bus.snoop_fanout::total 1084776 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 1587917075 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 1084475 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 1587731325 # Layer occupancy (ticks)
1008c1010
< system.toL2Bus.respLayer0.occupancy 2276216676 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 2275347621 # Layer occupancy (ticks)
1010c1012
< system.toL2Bus.respLayer1.occupancy 846189675 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 846816900 # Layer occupancy (ticks)
1014c1016
< system.iobus.trans_dist::WriteReq 59419 # Transaction distribution
---
> system.iobus.trans_dist::WriteReq 59425 # Transaction distribution
1016c1018
< system.iobus.trans_dist::WriteInvalidateReq 21 # Transaction distribution
---
> system.iobus.trans_dist::WriteInvalidateReq 15 # Transaction distribution
1107c1109
< system.iobus.reqLayer27.occupancy 326647327 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 326640327 # Layer occupancy (ticks)
1113c1115
< system.iobus.respLayer3.occupancy 36834343 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 36831597 # Layer occupancy (ticks)
1115,1119c1117,1121
< system.cpu0.branchPred.lookups 24027935 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 15717476 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 977431 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 14651046 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 10773468 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 24028098 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 15717962 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 977131 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 14655901 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 10773369 # Number of BTB hits
1121,1123c1123,1125
< system.cpu0.branchPred.BTBHitPct 73.533780 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 3878036 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 32430 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 73.508746 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 3877913 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 32441 # Number of incorrect RAS predictions.
1147,1150c1149,1152
< system.cpu0.dtb.read_hits 17722520 # DTB read hits
< system.cpu0.dtb.read_misses 56371 # DTB read misses
< system.cpu0.dtb.write_hits 14647463 # DTB write hits
< system.cpu0.dtb.write_misses 8727 # DTB write misses
---
> system.cpu0.dtb.read_hits 17721911 # DTB read hits
> system.cpu0.dtb.read_misses 56434 # DTB read misses
> system.cpu0.dtb.write_hits 14647364 # DTB write hits
> system.cpu0.dtb.write_misses 8710 # DTB write misses
1155,1157c1157,1159
< system.cpu0.dtb.flush_entries 3522 # Number of entries that have been flushed from TLB
< system.cpu0.dtb.align_faults 304 # Number of TLB faults due to alignment restrictions
< system.cpu0.dtb.prefetch_faults 2355 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB
> system.cpu0.dtb.align_faults 318 # Number of TLB faults due to alignment restrictions
> system.cpu0.dtb.prefetch_faults 2358 # Number of TLB faults due to prefetch
1159,1161c1161,1163
< system.cpu0.dtb.perms_faults 853 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 17778891 # DTB read accesses
< system.cpu0.dtb.write_accesses 14656190 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 855 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 17778345 # DTB read accesses
> system.cpu0.dtb.write_accesses 14656074 # DTB write accesses
1163,1165c1165,1167
< system.cpu0.dtb.hits 32369983 # DTB hits
< system.cpu0.dtb.misses 65098 # DTB misses
< system.cpu0.dtb.accesses 32435081 # DTB accesses
---
> system.cpu0.dtb.hits 32369275 # DTB hits
> system.cpu0.dtb.misses 65144 # DTB misses
> system.cpu0.dtb.accesses 32434419 # DTB accesses
1187,1188c1189,1190
< system.cpu0.itb.inst_hits 37749886 # ITB inst hits
< system.cpu0.itb.inst_misses 10298 # ITB inst misses
---
> system.cpu0.itb.inst_hits 37749203 # ITB inst hits
> system.cpu0.itb.inst_misses 10291 # ITB inst misses
1197c1199
< system.cpu0.itb.flush_entries 2364 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB
1201c1203
< system.cpu0.itb.perms_faults 1942 # Number of TLB faults due to permissions restrictions
---
> system.cpu0.itb.perms_faults 1952 # Number of TLB faults due to permissions restrictions
1204,1208c1206,1210
< system.cpu0.itb.inst_accesses 37760184 # ITB inst accesses
< system.cpu0.itb.hits 37749886 # DTB hits
< system.cpu0.itb.misses 10298 # DTB misses
< system.cpu0.itb.accesses 37760184 # DTB accesses
< system.cpu0.numCycles 126958641 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 37759494 # ITB inst accesses
> system.cpu0.itb.hits 37749203 # DTB hits
> system.cpu0.itb.misses 10291 # DTB misses
> system.cpu0.itb.accesses 37759494 # DTB accesses
> system.cpu0.numCycles 126930318 # number of cpu cycles simulated
1211,1227c1213,1229
< system.cpu0.fetch.icacheStallCycles 18143411 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 112712815 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 24027935 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 14651504 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 104787507 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 2823240 # Number of cycles fetch has spent squashing
< system.cpu0.fetch.TlbCycles 133419 # Number of cycles fetch has spent waiting for tlb
< system.cpu0.fetch.MiscStallCycles 39139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu0.fetch.PendingTrapStallCycles 365906 # Number of stall cycles due to pending traps
< system.cpu0.fetch.PendingQuiesceStallCycles 432078 # Number of stall cycles due to pending quiesce instructions
< system.cpu0.fetch.IcacheWaitRetryStallCycles 38034 # Number of stall cycles due to full MSHR
< system.cpu0.fetch.CacheLines 37750510 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 265510 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.ItlbSquashes 3919 # Number of outstanding ITLB misses that were squashed
< system.cpu0.fetch.rateDist::samples 125351114 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 1.084784 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 1.263056 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.icacheStallCycles 18136746 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 112711782 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 24028098 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 14651282 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 104771989 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 2822564 # Number of cycles fetch has spent squashing
> system.cpu0.fetch.TlbCycles 133376 # Number of cycles fetch has spent waiting for tlb
> system.cpu0.fetch.MiscStallCycles 38789 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu0.fetch.PendingTrapStallCycles 365072 # Number of stall cycles due to pending traps
> system.cpu0.fetch.PendingQuiesceStallCycles 429907 # Number of stall cycles due to pending quiesce instructions
> system.cpu0.fetch.IcacheWaitRetryStallCycles 37570 # Number of stall cycles due to full MSHR
> system.cpu0.fetch.CacheLines 37749815 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 265004 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.ItlbSquashes 3918 # Number of outstanding ITLB misses that were squashed
> system.cpu0.fetch.rateDist::samples 125324731 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 1.084977 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 1.263079 # Number of instructions fetched each cycle (Total)
1229,1232c1231,1234
< system.cpu0.fetch.rateDist::0 62795131 50.10% 50.10% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 21461544 17.12% 67.22% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 8765998 6.99% 74.21% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 32328441 25.79% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 62770441 50.09% 50.09% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 21460959 17.12% 67.21% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 8766539 7.00% 74.21% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 32326792 25.79% 100.00% # Number of instructions fetched each cycle (Total)
1236,1282c1238,1284
< system.cpu0.fetch.rateDist::total 125351114 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.189258 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 0.887792 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 19217150 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 58693987 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 41414238 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 4958351 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 1067388 # Number of cycles decode is squashing
< system.cpu0.decode.BranchResolved 3055751 # Number of times decode resolved a branch
< system.cpu0.decode.BranchMispred 348432 # Number of times decode detected a branch misprediction
< system.cpu0.decode.DecodedInsts 110728193 # Number of instructions handled by decode
< system.cpu0.decode.SquashedInsts 3997819 # Number of squashed instructions handled by decode
< system.cpu0.rename.SquashCycles 1067388 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 24968075 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 11998776 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 36565512 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 40482982 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 10268381 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 105647193 # Number of instructions processed by rename
< system.cpu0.rename.SquashedInsts 1060681 # Number of squashed instructions processed by rename
< system.cpu0.rename.ROBFullEvents 1440352 # Number of times rename has blocked due to ROB full
< system.cpu0.rename.IQFullEvents 161094 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LQFullEvents 60996 # Number of times rename has blocked due to LQ full
< system.cpu0.rename.SQFullEvents 6068574 # Number of times rename has blocked due to SQ full
< system.cpu0.rename.RenamedOperands 109731042 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 482381977 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 120921551 # Number of integer rename lookups
< system.cpu0.rename.fp_rename_lookups 9385 # Number of floating rename lookups
< system.cpu0.rename.CommittedMaps 98136808 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 11594231 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 1228692 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 1087401 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 12320869 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 18735521 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 16202725 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 1699910 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 2282844 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 102687285 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 1694390 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 100670059 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 484670 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 9020348 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 22495673 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 122680 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 125351114 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 0.803105 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.034773 # Number of insts issued each cycle
---
> system.cpu0.fetch.rateDist::total 125324731 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.189301 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 0.887982 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 19209269 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 58676701 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 41413260 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 4958284 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 1067217 # Number of cycles decode is squashing
> system.cpu0.decode.BranchResolved 3055385 # Number of times decode resolved a branch
> system.cpu0.decode.BranchMispred 348256 # Number of times decode detected a branch misprediction
> system.cpu0.decode.DecodedInsts 110724808 # Number of instructions handled by decode
> system.cpu0.decode.SquashedInsts 3997323 # Number of squashed instructions handled by decode
> system.cpu0.rename.SquashCycles 1067217 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 24959463 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 12008700 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 36549302 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 40482992 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 10257057 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 105644030 # Number of instructions processed by rename
> system.cpu0.rename.SquashedInsts 1060860 # Number of squashed instructions processed by rename
> system.cpu0.rename.ROBFullEvents 1434602 # Number of times rename has blocked due to ROB full
> system.cpu0.rename.IQFullEvents 161076 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LQFullEvents 61450 # Number of times rename has blocked due to LQ full
> system.cpu0.rename.SQFullEvents 6058216 # Number of times rename has blocked due to SQ full
> system.cpu0.rename.RenamedOperands 109726611 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 482367040 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 120917485 # Number of integer rename lookups
> system.cpu0.rename.fp_rename_lookups 9389 # Number of floating rename lookups
> system.cpu0.rename.CommittedMaps 98135067 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 11591541 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 1228775 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 1087468 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 12318365 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 18735262 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 16202067 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 1700806 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 2287265 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 102683814 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 1694438 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 100667981 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 483835 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 9019913 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 22488132 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 122848 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 125324731 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 0.803257 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.034844 # Number of insts issued each cycle
1284,1288c1286,1290
< system.cpu0.iq.issued_per_cycle::0 69205207 55.21% 55.21% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 23183333 18.49% 73.70% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 22514733 17.96% 91.67% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 9334141 7.45% 99.11% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 1113663 0.89% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 69182553 55.20% 55.20% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 23178514 18.49% 73.70% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 22516011 17.97% 91.66% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 9333204 7.45% 99.11% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 1114412 0.89% 100.00% # Number of insts issued each cycle
1296c1298
< system.cpu0.iq.issued_per_cycle::total 125351114 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 125324731 # Number of insts issued each cycle
1298,1328c1300,1330
< system.cpu0.iq.fu_full::IntAlu 9379501 40.75% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 82 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.75% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 5582636 24.26% 65.01% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 8053143 34.99% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 9379454 40.76% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 82 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 5581640 24.26% 65.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 8050330 34.98% 100.00% # attempts to use FU when none available
1332,1333c1334,1335
< system.cpu0.iq.FU_type_0::IntAlu 66409608 65.97% 65.97% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 93111 0.09% 66.06% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::IntAlu 66408183 65.97% 65.97% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 93140 0.09% 66.06% # Type of FU issued
1356c1358
< system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.06% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::SimdFloatDiv 2 0.00% 66.06% # Type of FU issued
1361,1362c1363,1364
< system.cpu0.iq.FU_type_0::MemRead 18430675 18.31% 84.38% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 15726281 15.62% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::MemRead 18430252 18.31% 84.38% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 15726021 15.62% 100.00% # Type of FU issued
1365,1376c1367,1378
< system.cpu0.iq.FU_type_0::total 100670059 # Type of FU issued
< system.cpu0.iq.rate 0.792936 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 23015362 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.228622 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 350159403 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 113409879 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 98581657 # Number of integer instruction queue wakeup accesses
< system.cpu0.iq.fp_inst_queue_reads 31861 # Number of floating instruction queue reads
< system.cpu0.iq.fp_inst_queue_writes 11294 # Number of floating instruction queue writes
< system.cpu0.iq.fp_inst_queue_wakeup_accesses 9722 # Number of floating instruction queue wakeup accesses
< system.cpu0.iq.int_alu_accesses 123662544 # Number of integer alu accesses
< system.cpu0.iq.fp_alu_accesses 20604 # Number of floating point alu accesses
---
> system.cpu0.iq.FU_type_0::total 100667981 # Type of FU issued
> system.cpu0.iq.rate 0.793096 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 23011506 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.228588 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 350124170 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 113406012 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 98579580 # Number of integer instruction queue wakeup accesses
> system.cpu0.iq.fp_inst_queue_reads 31864 # Number of floating instruction queue reads
> system.cpu0.iq.fp_inst_queue_writes 11293 # Number of floating instruction queue writes
> system.cpu0.iq.fp_inst_queue_wakeup_accesses 9723 # Number of floating instruction queue wakeup accesses
> system.cpu0.iq.int_alu_accesses 123656622 # Number of integer alu accesses
> system.cpu0.iq.fp_alu_accesses 20592 # Number of floating point alu accesses
1379,1382c1381,1384
< system.cpu0.iew.lsq.thread0.squashedLoads 2006423 # Number of loads squashed
< system.cpu0.iew.lsq.thread0.ignoredResponses 2595 # Number of memory responses ignored because the instruction is squashed
< system.cpu0.iew.lsq.thread0.memOrderViolation 19219 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 1022338 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 2006492 # Number of loads squashed
> system.cpu0.iew.lsq.thread0.ignoredResponses 2605 # Number of memory responses ignored because the instruction is squashed
> system.cpu0.iew.lsq.thread0.memOrderViolation 19209 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 1022192 # Number of stores squashed
1385,1386c1387,1388
< system.cpu0.iew.lsq.thread0.rescheduledLoads 106441 # Number of loads that were rescheduled
< system.cpu0.iew.lsq.thread0.cacheBlocked 337136 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.rescheduledLoads 106472 # Number of loads that were rescheduled
> system.cpu0.iew.lsq.thread0.cacheBlocked 336634 # Number of times an access to memory failed due to the cache being blocked
1388,1391c1390,1393
< system.cpu0.iew.iewSquashCycles 1067388 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 1615648 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 188928 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 104556414 # Number of instructions dispatched to IQ
---
> system.cpu0.iew.iewSquashCycles 1067217 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 1619268 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 191305 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 104552982 # Number of instructions dispatched to IQ
1393,1404c1395,1406
< system.cpu0.iew.iewDispLoadInsts 18735521 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 16202725 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 876047 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 27263 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 138025 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 19219 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 291871 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 400586 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 692457 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 99572602 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 17974009 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 1032494 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewDispLoadInsts 18735262 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 16202067 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 876141 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 27204 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 140421 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 19209 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 291739 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 400527 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 692266 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 99570429 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 17973451 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 1032544 # Number of squashed instructions skipped in execute
1406,1414c1408,1416
< system.cpu0.iew.exec_nop 174739 # number of nop insts executed
< system.cpu0.iew.exec_refs 33508875 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 16843329 # Number of branches executed
< system.cpu0.iew.exec_stores 15534866 # Number of stores executed
< system.cpu0.iew.exec_rate 0.784292 # Inst execution rate
< system.cpu0.iew.wb_sent 99041613 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 98591379 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 51320038 # num instructions producing a value
< system.cpu0.iew.wb_consumers 84796920 # num instructions consuming a value
---
> system.cpu0.iew.exec_nop 174730 # number of nop insts executed
> system.cpu0.iew.exec_refs 33508210 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 16843179 # Number of branches executed
> system.cpu0.iew.exec_stores 15534759 # Number of stores executed
> system.cpu0.iew.exec_rate 0.784450 # Inst execution rate
> system.cpu0.iew.wb_sent 99039643 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 98589303 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 51320532 # num instructions producing a value
> system.cpu0.iew.wb_consumers 84799978 # num instructions consuming a value
1416,1417c1418,1419
< system.cpu0.iew.wb_rate 0.776563 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.605211 # average fanout of values written-back
---
> system.cpu0.iew.wb_rate 0.776720 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.605195 # average fanout of values written-back
1419,1424c1421,1426
< system.cpu0.commit.commitSquashedInsts 8526320 # The number of squashed insts skipped by commit
< system.cpu0.commit.commitNonSpecStalls 1571710 # The number of times commit has been forced to stall to communicate backwards
< system.cpu0.commit.branchMispredicts 633199 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 123596989 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 0.768069 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 1.480980 # Number of insts commited each cycle
---
> system.cpu0.commit.commitSquashedInsts 8525678 # The number of squashed insts skipped by commit
> system.cpu0.commit.commitNonSpecStalls 1571590 # The number of times commit has been forced to stall to communicate backwards
> system.cpu0.commit.branchMispredicts 633066 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 123570875 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 0.768216 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 1.481246 # Number of insts commited each cycle
1426,1434c1428,1436
< system.cpu0.commit.committed_per_cycle::0 79268840 64.13% 64.13% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 24713999 20.00% 84.13% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 8247824 6.67% 90.80% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 3215855 2.60% 93.41% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 3439875 2.78% 96.19% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 1518279 1.23% 97.42% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 1140929 0.92% 98.34% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 533748 0.43% 98.77% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 1517640 1.23% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 79246760 64.13% 64.13% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 24711613 20.00% 84.13% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 8248135 6.67% 90.80% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 3213746 2.60% 93.40% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 3439781 2.78% 96.19% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 1516341 1.23% 97.41% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 1141391 0.92% 98.34% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 534018 0.43% 98.77% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 1519090 1.23% 100.00% # Number of insts commited each cycle
1438,1440c1440,1442
< system.cpu0.commit.committed_per_cycle::total 123596989 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 78900966 # Number of instructions committed
< system.cpu0.commit.committedOps 94931037 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 123570875 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 78899754 # Number of instructions committed
> system.cpu0.commit.committedOps 94929142 # Number of ops (including micro ops) committed
1442,1445c1444,1447
< system.cpu0.commit.refs 31909485 # Number of memory references committed
< system.cpu0.commit.loads 16729098 # Number of loads committed
< system.cpu0.commit.membars 647159 # Number of memory barriers committed
< system.cpu0.commit.branches 16205509 # Number of branches committed
---
> system.cpu0.commit.refs 31908645 # Number of memory references committed
> system.cpu0.commit.loads 16728770 # Number of loads committed
> system.cpu0.commit.membars 647107 # Number of memory barriers committed
> system.cpu0.commit.branches 16205360 # Number of branches committed
1447,1448c1449,1450
< system.cpu0.commit.int_insts 81880566 # Number of committed integer instructions.
< system.cpu0.commit.function_calls 1929583 # Number of function calls committed.
---
> system.cpu0.commit.int_insts 81878721 # Number of committed integer instructions.
> system.cpu0.commit.function_calls 1929507 # Number of function calls committed.
1450,1451c1452,1453
< system.cpu0.commit.op_class_0::IntAlu 62922752 66.28% 66.28% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntMult 90691 0.10% 66.38% # Class of committed instruction
---
> system.cpu0.commit.op_class_0::IntAlu 62921673 66.28% 66.28% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntMult 90715 0.10% 66.38% # Class of committed instruction
1479,1480c1481,1482
< system.cpu0.commit.op_class_0::MemRead 16729098 17.62% 84.01% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemWrite 15180387 15.99% 100.00% # Class of committed instruction
---
> system.cpu0.commit.op_class_0::MemRead 16728770 17.62% 84.01% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemWrite 15179875 15.99% 100.00% # Class of committed instruction
1483,1484c1485,1486
< system.cpu0.commit.op_class_0::total 94931037 # Class of committed instruction
< system.cpu0.commit.bw_lim_events 1517640 # number cycles where commit BW limit reached
---
> system.cpu0.commit.op_class_0::total 94929142 # Class of committed instruction
> system.cpu0.commit.bw_lim_events 1519090 # number cycles where commit BW limit reached
1486,1499c1488,1501
< system.cpu0.rob.rob_reads 221353668 # The number of ROB reads
< system.cpu0.rob.rob_writes 208668086 # The number of ROB writes
< system.cpu0.timesIdled 109562 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 1607527 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.quiesceCycles 5521753720 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.committedInsts 78778915 # Number of Instructions Simulated
< system.cpu0.committedOps 94808986 # Number of Ops (including micro ops) Simulated
< system.cpu0.cpi 1.611581 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 1.611581 # CPI: Total CPI of All Threads
< system.cpu0.ipc 0.620508 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 0.620508 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 110614815 # number of integer regfile reads
< system.cpu0.int_regfile_writes 59737885 # number of integer regfile writes
< system.cpu0.fp_regfile_reads 8165 # number of floating regfile reads
---
> system.cpu0.rob.rob_reads 221323955 # The number of ROB reads
> system.cpu0.rob.rob_writes 208662740 # The number of ROB writes
> system.cpu0.timesIdled 109422 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 1605587 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.quiesceCycles 5521751456 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.committedInsts 78777703 # Number of Instructions Simulated
> system.cpu0.committedOps 94807091 # Number of Ops (including micro ops) Simulated
> system.cpu0.cpi 1.611247 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 1.611247 # CPI: Total CPI of All Threads
> system.cpu0.ipc 0.620637 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 0.620637 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 110612001 # number of integer regfile reads
> system.cpu0.int_regfile_writes 59736021 # number of integer regfile writes
> system.cpu0.fp_regfile_reads 8164 # number of floating regfile reads
1501,1532c1503,1534
< system.cpu0.cc_regfile_reads 350771001 # number of cc regfile reads
< system.cpu0.cc_regfile_writes 41073809 # number of cc regfile writes
< system.cpu0.misc_regfile_reads 245697526 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 1224542 # number of misc regfile writes
< system.cpu0.toL2Bus.trans_dist::ReadReq 2022292 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 1921231 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 19109 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 19109 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::Writeback 512497 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 635775 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36233 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 81120 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43298 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 105236 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 291864 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 281152 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2535030 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2361050 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28910 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120430 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 5045420 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80976096 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86183658 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50232 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 218780 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 167428766 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 1029243 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 3600041 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 5.252406 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.434393 # Request fanout histogram
---
> system.cpu0.cc_regfile_reads 350763374 # number of cc regfile reads
> system.cpu0.cc_regfile_writes 41072426 # number of cc regfile writes
> system.cpu0.misc_regfile_reads 246706358 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 1224463 # number of misc regfile writes
> system.cpu0.toL2Bus.trans_dist::ReadReq 2021709 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 1920443 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 19105 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 19105 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::Writeback 512971 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 647722 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 80908 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43157 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 104918 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 291878 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 281134 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2533809 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2360432 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28914 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120703 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 5043858 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80936864 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86195670 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50328 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 219428 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 167402290 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 1041040 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 3611543 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 5.254928 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.435821 # Request fanout histogram
1539,1540c1541,1542
< system.cpu0.toL2Bus.snoop_fanout::5 2691370 74.76% 74.76% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::6 908671 25.24% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::5 2690859 74.51% 74.51% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::6 920684 25.49% 100.00% # Request fanout histogram
1544,1545c1546,1547
< system.cpu0.toL2Bus.snoop_fanout::total 3600041 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 1889888022 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 3611543 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 1890112247 # Layer occupancy (ticks)
1547c1549
< system.cpu0.toL2Bus.snoopLayer0.occupancy 117489749 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 117326747 # Layer occupancy (ticks)
1549c1551
< system.cpu0.toL2Bus.respLayer0.occupancy 1901826585 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 1900909092 # Layer occupancy (ticks)
1551c1553
< system.cpu0.toL2Bus.respLayer1.occupancy 1220473591 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 1220029643 # Layer occupancy (ticks)
1553c1555
< system.cpu0.toL2Bus.respLayer2.occupancy 16363478 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 16342731 # Layer occupancy (ticks)
1555c1557
< system.cpu0.toL2Bus.respLayer3.occupancy 65772430 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 65878690 # Layer occupancy (ticks)
1557,1563c1559,1565
< system.cpu0.icache.tags.replacements 1263981 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.774384 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 36445999 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 1264493 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 28.822618 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 6310719000 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774384 # Average occupied blocks per requestor
---
> system.cpu0.icache.tags.replacements 1263367 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.774258 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 36446077 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 1263879 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 28.836682 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 6311559000 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774258 # Average occupied blocks per requestor
1568,1569c1570,1571
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 130 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id
1571,1609c1573,1611
< system.cpu0.icache.tags.tag_accesses 76759130 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 76759130 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 36445999 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 36445999 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 36445999 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 36445999 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 36445999 # number of overall hits
< system.cpu0.icache.overall_hits::total 36445999 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 1301304 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 1301304 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 1301304 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 1301304 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 1301304 # number of overall misses
< system.cpu0.icache.overall_misses::total 1301304 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11020664802 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 11020664802 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 11020664802 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 11020664802 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 11020664802 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 11020664802 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 37747303 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 37747303 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 37747303 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 37747303 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 37747303 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 37747303 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034474 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.034474 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034474 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.034474 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034474 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.034474 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8468.939465 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 8468.939465 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8468.939465 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 8468.939465 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8468.939465 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 8468.939465 # average overall miss latency
< system.cpu0.icache.blocked_cycles::no_mshrs 725662 # number of cycles access was blocked
---
> system.cpu0.icache.tags.tag_accesses 76757150 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 76757150 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 36446077 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 36446077 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 36446077 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 36446077 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 36446077 # number of overall hits
> system.cpu0.icache.overall_hits::total 36446077 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 1300540 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 1300540 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 1300540 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 1300540 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 1300540 # number of overall misses
> system.cpu0.icache.overall_misses::total 1300540 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11011983856 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 11011983856 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 11011983856 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 11011983856 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 11011983856 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 11011983856 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 37746617 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 37746617 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 37746617 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 37746617 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 37746617 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 37746617 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034454 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.034454 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034454 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.034454 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034454 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.034454 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8467.239651 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 8467.239651 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8467.239651 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 8467.239651 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8467.239651 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 8467.239651 # average overall miss latency
> system.cpu0.icache.blocked_cycles::no_mshrs 724812 # number of cycles access was blocked
1611c1613
< system.cpu0.icache.blocked::no_mshrs 96193 # number of cycles access was blocked
---
> system.cpu0.icache.blocked::no_mshrs 96016 # number of cycles access was blocked
1613c1615
< system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.543813 # average number of cycles each access was blocked
---
> system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.548867 # average number of cycles each access was blocked
1617,1650c1619,1652
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 36779 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 36779 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 36779 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 36779 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 36779 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 36779 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1264525 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 1264525 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 1264525 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 1264525 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 1264525 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 1264525 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8921757516 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 8921757516 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8921757516 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 8921757516 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8921757516 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 8921757516 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 243776998 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 243776998 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 243776998 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::total 243776998 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033500 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033500 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033500 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.033500 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033500 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.033500 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7055.422009 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7055.422009 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7055.422009 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 7055.422009 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7055.422009 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 7055.422009 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 36623 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 36623 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 36623 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 36623 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 36623 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 36623 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1263917 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 1263917 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 1263917 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 1263917 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 1263917 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 1263917 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8916921322 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 8916921322 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8916921322 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 8916921322 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8916921322 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 8916921322 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 244130748 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 244130748 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 244130748 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::total 244130748 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033484 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033484 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033484 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.033484 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033484 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.033484 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7054.989625 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7054.989625 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7054.989625 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 7054.989625 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7054.989625 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 7054.989625 # average overall mshr miss latency
1656,1659c1658,1661
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 11570902 # number of hwpf identified
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 525454 # number of hwpf that were already in mshr
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 10431616 # number of hwpf that were already in the cache
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 117790 # number of hwpf that were already in the prefetch queue
---
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 11566475 # number of hwpf identified
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 526266 # number of hwpf that were already in mshr
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 10413579 # number of hwpf that were already in the cache
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 118534 # number of hwpf that were already in the prefetch queue
1661,1663c1663,1665
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 25307 # number of hwpf removed because MSHR allocated
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 470730 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 881250 # number of hwpf spanning a virtual page
---
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 25521 # number of hwpf removed because MSHR allocated
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 482570 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 881997 # number of hwpf spanning a virtual page
1665,1824c1667,1828
< system.cpu0.l2cache.tags.replacements 397283 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16205.229139 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 2244912 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 413530 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 5.428656 # Average number of references to valid blocks.
< system.cpu0.l2cache.tags.warmup_cycle 2809069613500 # Cycle when the warmup percentage was hit.
< system.cpu0.l2cache.tags.occ_blocks::writebacks 4639.805304 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 13.151524 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.649414 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 948.692737 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1410.057987 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9191.872173 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.283191 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000803 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000101 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.057904 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.086063 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.561027 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.989089 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8152 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8085 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 51 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 237 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3322 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4084 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 458 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 501 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3682 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3594 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 245 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.497559 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.493469 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 43590224 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 43590224 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54156 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12330 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1242747 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.data 407291 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 1716524 # number of ReadReq hits
< system.cpu0.l2cache.Writeback_hits::writebacks 512497 # number of Writeback hits
< system.cpu0.l2cache.Writeback_hits::total 512497 # number of Writeback hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 15462 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 15462 # number of UpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2188 # number of SCUpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::total 2188 # number of SCUpgradeReq hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 216542 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 216542 # number of ReadExReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54156 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12330 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 1242747 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 623833 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 1933066 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 54156 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12330 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 1242747 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 623833 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 1933066 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 539 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 228 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.inst 21755 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.data 91027 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 113549 # number of ReadReq misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27999 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 27999 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18512 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 18512 # number of SCUpgradeReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 52925 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 52925 # number of ReadExReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 539 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 228 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 21755 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 143952 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 166474 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 539 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 228 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 21755 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 143952 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 166474 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 14141500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 5255000 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 812129434 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2705700107 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 3537226041 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 502587457 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 502587457 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 362338282 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 362338282 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 217500 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 217500 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2594310029 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 2594310029 # number of ReadExReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 14141500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 5255000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 812129434 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 5300010136 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 6131536070 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 14141500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 5255000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 812129434 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 5300010136 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 6131536070 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 54695 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12558 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1264502 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.data 498318 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 1830073 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::writebacks 512497 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::total 512497 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 43461 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 43461 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20700 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 20700 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269467 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 269467 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 54695 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12558 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 1264502 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 767785 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 2099540 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 54695 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12558 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 1264502 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 767785 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 2099540 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009855 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.018156 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.017204 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.182668 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.062046 # miss rate for ReadReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.644233 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.644233 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.894300 # miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.894300 # miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.196406 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.196406 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009855 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.018156 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.017204 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.187490 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.079291 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009855 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.018156 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.017204 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.187490 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.079291 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26236.549165 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23048.245614 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37330.702551 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29724.148956 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31151.538464 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17950.193114 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17950.193114 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19573.156979 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19573.156979 # average SCUpgradeReq miss latency
---
> system.cpu0.l2cache.tags.replacements 397205 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16210.584505 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 2245016 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 413453 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 5.429918 # Average number of references to valid blocks.
> system.cpu0.l2cache.tags.warmup_cycle 2809067534500 # Cycle when the warmup percentage was hit.
> system.cpu0.l2cache.tags.occ_blocks::writebacks 4582.280464 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 7.704235 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.810288 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 954.063900 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1415.763715 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9248.961904 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.279680 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000470 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000110 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.058231 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.086411 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.564512 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.989416 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8114 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8126 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 46 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 255 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3376 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 3995 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 442 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 500 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3733 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3570 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 262 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.495239 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.495972 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 43582923 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 43582923 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54301 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12378 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1242064 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.data 407333 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 1716076 # number of ReadReq hits
> system.cpu0.l2cache.Writeback_hits::writebacks 512970 # number of Writeback hits
> system.cpu0.l2cache.Writeback_hits::total 512970 # number of Writeback hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 15323 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 15323 # number of UpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2128 # number of SCUpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::total 2128 # number of SCUpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 216744 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 216744 # number of ReadExReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54301 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12378 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 1242064 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 624077 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 1932820 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 54301 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12378 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 1242064 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 624077 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 1932820 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 556 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 204 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.inst 21825 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.data 90809 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 113394 # number of ReadReq misses
> system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses
> system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27941 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 27941 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18479 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 18479 # number of SCUpgradeReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 52711 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 52711 # number of ReadExReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 556 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 204 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 21825 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 143520 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 166105 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 556 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 204 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 21825 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 143520 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 166105 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 14566249 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 5056249 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 811526688 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2694555362 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 3525704548 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 501364439 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 501364439 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 362083288 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 362083288 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 361000 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 361000 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2596231534 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 2596231534 # number of ReadExReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 14566249 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 5056249 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 811526688 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 5290786896 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 6121936082 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 14566249 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 5056249 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 811526688 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 5290786896 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 6121936082 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 54857 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12582 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1263889 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.data 498142 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 1829470 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::writebacks 512971 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::total 512971 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 43264 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 43264 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20607 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 20607 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269455 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 269455 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 54857 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12582 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 1263889 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 767597 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 2098925 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 54857 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12582 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 1263889 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 767597 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 2098925 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010135 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.016214 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.017268 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.182295 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.061982 # miss rate for ReadReq accesses
> system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses
> system.cpu0.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.645826 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.645826 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.896734 # miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.896734 # miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.195621 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.195621 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010135 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.016214 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.017268 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.186973 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.079138 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010135 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.016214 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.017268 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.186973 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.079138 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26198.289568 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24785.534314 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37183.353402 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29672.778711 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31092.514137 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17943.682724 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17943.682724 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19594.311813 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19594.311813 # average SCUpgradeReq miss latency
1827,1839c1831,1843
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49018.611790 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49018.611790 # average ReadExReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26236.549165 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23048.245614 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37330.702551 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36817.898577 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 36831.793974 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26236.549165 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23048.245614 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37330.702551 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36817.898577 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 36831.793974 # average overall miss latency
< system.cpu0.l2cache.blocked_cycles::no_mshrs 59871 # number of cycles access was blocked
---
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49254.074747 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49254.074747 # average ReadExReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26198.289568 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24785.534314 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37183.353402 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36864.457191 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 36855.820607 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26198.289568 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24785.534314 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37183.353402 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36864.457191 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 36855.820607 # average overall miss latency
> system.cpu0.l2cache.blocked_cycles::no_mshrs 65022 # number of cycles access was blocked
1841c1845
< system.cpu0.l2cache.blocked::no_mshrs 1464 # number of cycles access was blocked
---
> system.cpu0.l2cache.blocked::no_mshrs 1467 # number of cycles access was blocked
1843c1847
< system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 40.895492 # average number of cycles each access was blocked
---
> system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 44.323108 # average number of cycles each access was blocked
1847,1849c1851,1852
< system.cpu0.l2cache.writebacks::writebacks 212118 # number of writebacks
< system.cpu0.l2cache.writebacks::total 212118 # number of writebacks
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
---
> system.cpu0.l2cache.writebacks::writebacks 212015 # number of writebacks
> system.cpu0.l2cache.writebacks::total 212015 # number of writebacks
1851,1856c1854,1858
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 5582 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 3121 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_hits::total 8705 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8957 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 8957 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
---
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 5576 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 3180 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::total 8757 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8826 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 8826 # number of ReadExReq MSHR hits
1858,1861c1860,1862
< system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 5582 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 12078 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 17662 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
---
> system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 5576 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 12006 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 17583 # number of demand (read+write) MSHR hits
1863,1928c1864,1933
< system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 5582 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 12078 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 17662 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 538 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 227 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 16173 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 87906 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 104844 # number of ReadReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 470726 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 470726 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27999 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27999 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18512 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18512 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43968 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 43968 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 538 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 227 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 16173 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 131874 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 148812 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 538 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 227 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 16173 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 131874 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 470726 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 619538 # number of overall MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10359500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3653000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 584863774 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2018675176 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2617551450 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21918972757 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21918972757 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 483477329 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 483477329 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 250147229 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 250147229 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 175500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 175500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1315007380 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1315007380 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 10359500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3653000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 584863774 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3333682556 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 3932558830 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 10359500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3653000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 584863774 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3333682556 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21918972757 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 25851531587 # number of overall MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 218357500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4053329974 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4271687474 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3040369451 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3040369451 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 218357500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7093699425 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7312056925 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009836 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.018076 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012790 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.176405 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.057290 # mshr miss rate for ReadReq accesses
---
> system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 5576 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 12006 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 17583 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 556 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 203 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 16249 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 87629 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 104637 # number of ReadReq MSHR misses
> system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses
> system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 482567 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 482567 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27941 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27941 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18479 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18479 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43885 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 43885 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 556 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 203 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 16249 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 131514 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 148522 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 556 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 203 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 16249 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 131514 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 482567 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 631089 # number of overall MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10668751 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3620751 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 587001511 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2007365947 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2608656960 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21948496416 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21948496416 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 481784375 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 481784375 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 249254743 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 249254743 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 284000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 284000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1315803854 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1315803854 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 10668751 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3620751 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 587001511 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3323169801 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 3924460814 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 10668751 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3620751 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 587001511 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3323169801 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21948496416 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 25872957230 # number of overall MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 218713750 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4053946738 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4272660488 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3040262957 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3040262957 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 218713750 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7094209695 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7312923445 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010135 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.016134 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012856 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.175912 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.057195 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses
> system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses
1931,1945c1936,1950
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.644233 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.644233 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.894300 # mshr miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.894300 # mshr miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.163167 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163167 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009836 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.018076 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012790 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171759 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.070878 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009836 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.018076 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012790 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171759 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.645826 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.645826 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.896734 # mshr miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.896734 # mshr miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.162866 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.162866 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010135 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.016134 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012856 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171332 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.070761 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010135 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.016134 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012856 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171332 # mshr miss rate for overall accesses
1947,1958c1952,1963
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.295083 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19255.576208 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16092.511013 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36162.973722 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22964.020385 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24966.154000 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46564.185443 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46564.185443 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17267.664167 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17267.664167 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13512.706839 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13512.706839 # average SCUpgradeReq mshr miss latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.300672 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19188.401079 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17836.211823 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36125.393009 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22907.552831 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24930.540440 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45482.795997 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45482.795997 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17242.918113 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17242.918113 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13488.540668 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13488.540668 # average SCUpgradeReq mshr miss latency
1961,1973c1966,1978
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29908.282842 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29908.282842 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19255.576208 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16092.511013 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36162.973722 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25279.301121 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26426.355603 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19255.576208 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16092.511013 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36162.973722 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25279.301121 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46564.185443 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41727.112117 # average overall mshr miss latency
---
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29982.997699 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29982.997699 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19188.401079 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17836.211823 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36125.393009 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25268.563050 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26423.430966 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19188.401079 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17836.211823 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36125.393009 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25268.563050 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45482.795997 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40997.319285 # average overall mshr miss latency
1983,1991c1988,1996
< system.cpu0.dcache.tags.replacements 712949 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 494.466444 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 28841621 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 713461 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 40.424944 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 256469000 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.466444 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965755 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.965755 # Average percentage of cache occupancy
---
> system.cpu0.dcache.tags.replacements 712829 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 493.082766 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 28841671 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 713341 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 40.431815 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 256881000 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.082766 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.963052 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.963052 # Average percentage of cache occupancy
1997,2076c2002,2081
< system.cpu0.dcache.tags.tag_accesses 63482821 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 63482821 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 15588564 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 15588564 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 12071351 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 12071351 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 311001 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 311001 # number of SoftPFReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363214 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 363214 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360561 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 360561 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 27659915 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 27659915 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 27970916 # number of overall hits
< system.cpu0.dcache.overall_hits::total 27970916 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 638335 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 638335 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1832649 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1832649 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 146162 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 146162 # number of SoftPFReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24977 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 24977 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20700 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 20700 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 2470984 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 2470984 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 2617146 # number of overall misses
< system.cpu0.dcache.overall_misses::total 2617146 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8102181310 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 8102181310 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 25003432618 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 25003432618 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 396859499 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 396859499 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 455692776 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 455692776 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 235500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 235500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 33105613928 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 33105613928 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 33105613928 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 33105613928 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 16226899 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 16226899 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 13904000 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 13904000 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457163 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 457163 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388191 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 388191 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381261 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 381261 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 30130899 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 30130899 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 30588062 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 30588062 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039338 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.039338 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.131807 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.131807 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.319715 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.319715 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064342 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064342 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054294 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054294 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082008 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.082008 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085561 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.085561 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12692.679095 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 12692.679095 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13643.328656 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 13643.328656 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15888.997838 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15888.997838 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22014.143768 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22014.143768 # average StoreCondReq miss latency
---
> system.cpu0.dcache.tags.tag_accesses 63481444 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 63481444 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 15588806 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 15588806 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 12071580 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 12071580 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 311031 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 311031 # number of SoftPFReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363190 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 363190 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360636 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 360636 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 27660386 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 27660386 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 27971417 # number of overall hits
> system.cpu0.dcache.overall_hits::total 27971417 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 638107 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 638107 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1831928 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1831928 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 146057 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 146057 # number of SoftPFReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24976 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 24976 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20607 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 20607 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 2470035 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 2470035 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 2616092 # number of overall misses
> system.cpu0.dcache.overall_misses::total 2616092 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8089240805 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 8089240805 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24966494558 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 24966494558 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 395038253 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 395038253 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 453870788 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 453870788 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 394000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 394000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 33055735363 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 33055735363 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 33055735363 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 33055735363 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 16226913 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 16226913 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 13903508 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 13903508 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457088 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 457088 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388166 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 388166 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381243 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 381243 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 30130421 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 30130421 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 30587509 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 30587509 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039324 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.039324 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.131760 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.131760 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.319538 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.319538 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064344 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064344 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054052 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054052 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081978 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.081978 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085528 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.085528 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12676.934754 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 12676.934754 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13628.534832 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 13628.534832 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15816.714166 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15816.714166 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22025.078274 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22025.078274 # average StoreCondReq miss latency
2079,2088c2084,2093
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13397.745161 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 13397.745161 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12649.509782 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 12649.509782 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 1233 # number of cycles access was blocked
< system.cpu0.dcache.blocked_cycles::no_targets 3385599 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_mshrs 70 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_targets 191316 # number of cycles access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.614286 # average number of cycles each access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_targets 17.696371 # average number of cycles each access was blocked
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13382.699178 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 13382.699178 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12635.540097 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 12635.540097 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 1333 # number of cycles access was blocked
> system.cpu0.dcache.blocked_cycles::no_targets 3370028 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_mshrs 68 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_targets 191306 # number of cycles access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.602941 # average number of cycles each access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_targets 17.615903 # average number of cycles each access was blocked
2091,2162c2096,2167
< system.cpu0.dcache.writebacks::writebacks 512498 # number of writebacks
< system.cpu0.dcache.writebacks::total 512498 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 248017 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 248017 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1519903 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 1519903 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18417 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18417 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 1767920 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 1767920 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 1767920 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 1767920 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 390318 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 390318 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312746 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 312746 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101547 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 101547 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6560 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6560 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20700 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 20700 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 703064 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 703064 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 804611 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 804611 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4171307993 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4171307993 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4996022111 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4996022111 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1423316745 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1423316745 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98363500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98363500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 413570224 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 413570224 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 223500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 223500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9167330104 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 9167330104 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10590646849 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 10590646849 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4216535499 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4216535499 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3187175989 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3187175989 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7403711488 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7403711488 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024054 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024054 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.022493 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022493 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222124 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222124 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016899 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016899 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054294 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054294 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023334 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.023334 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026305 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.026305 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10686.947548 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10686.947548 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15974.695475 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15974.695475 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14016.334751 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14016.334751 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14994.435976 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14994.435976 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19979.237874 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19979.237874 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 512971 # number of writebacks
> system.cpu0.dcache.writebacks::total 512971 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 247929 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 247929 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1519381 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 1519381 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18420 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18420 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 1767310 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 1767310 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 1767310 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 1767310 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 390178 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 390178 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312547 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 312547 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101517 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 101517 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6556 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6556 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20607 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 20607 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 702725 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 702725 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 804242 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 804242 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4170870238 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4170870238 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4998082086 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4998082086 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1413907491 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1413907491 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97710498 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97710498 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 411958212 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 411958212 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 372000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 372000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9168952324 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 9168952324 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10582859815 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 10582859815 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4217153741 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4217153741 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3187052487 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3187052487 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7404206228 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7404206228 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024045 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024045 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.022480 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022480 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222095 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222095 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016890 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016890 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054052 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054052 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023323 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.023323 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026293 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.026293 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10689.660201 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10689.660201 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15991.457560 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15991.457560 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13927.790331 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13927.790331 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14903.980781 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14903.980781 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19991.178337 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19991.178337 # average StoreCondReq mshr miss latency
2165,2168c2170,2173
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13039.111808 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13039.111808 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13162.443527 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13162.443527 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13047.710447 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13047.710447 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13158.800231 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13158.800231 # average overall mshr miss latency
2176,2180c2181,2185
< system.cpu1.branchPred.lookups 33913093 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 11564399 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 305039 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 18757536 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 14959019 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 33910931 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 11562938 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 305104 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 18756149 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 14959197 # Number of BTB hits
2182,2184c2187,2189
< system.cpu1.branchPred.BTBHitPct 79.749382 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 12491385 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 7180 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 79.756228 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 12490116 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 7241 # Number of incorrect RAS predictions.
2208,2211c2213,2216
< system.cpu1.dtb.read_hits 10162981 # DTB read hits
< system.cpu1.dtb.read_misses 18754 # DTB read misses
< system.cpu1.dtb.write_hits 6542585 # DTB write hits
< system.cpu1.dtb.write_misses 2848 # DTB write misses
---
> system.cpu1.dtb.read_hits 10163466 # DTB read hits
> system.cpu1.dtb.read_misses 18799 # DTB read misses
> system.cpu1.dtb.write_hits 6542146 # DTB write hits
> system.cpu1.dtb.write_misses 2834 # DTB write misses
2217,2218c2222,2223
< system.cpu1.dtb.align_faults 49 # Number of TLB faults due to alignment restrictions
< system.cpu1.dtb.prefetch_faults 375 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.align_faults 53 # Number of TLB faults due to alignment restrictions
> system.cpu1.dtb.prefetch_faults 373 # Number of TLB faults due to prefetch
2220,2222c2225,2227
< system.cpu1.dtb.perms_faults 394 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 10181735 # DTB read accesses
< system.cpu1.dtb.write_accesses 6545433 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 406 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 10182265 # DTB read accesses
> system.cpu1.dtb.write_accesses 6544980 # DTB write accesses
2224,2226c2229,2231
< system.cpu1.dtb.hits 16705566 # DTB hits
< system.cpu1.dtb.misses 21602 # DTB misses
< system.cpu1.dtb.accesses 16727168 # DTB accesses
---
> system.cpu1.dtb.hits 16705612 # DTB hits
> system.cpu1.dtb.misses 21633 # DTB misses
> system.cpu1.dtb.accesses 16727245 # DTB accesses
2248,2249c2253,2254
< system.cpu1.itb.inst_hits 43643100 # ITB inst hits
< system.cpu1.itb.inst_misses 6996 # ITB inst misses
---
> system.cpu1.itb.inst_hits 43642051 # ITB inst hits
> system.cpu1.itb.inst_misses 6989 # ITB inst misses
2258c2263
< system.cpu1.itb.flush_entries 1201 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_entries 1203 # Number of entries that have been flushed from TLB
2262c2267
< system.cpu1.itb.perms_faults 544 # Number of TLB faults due to permissions restrictions
---
> system.cpu1.itb.perms_faults 541 # Number of TLB faults due to permissions restrictions
2265,2269c2270,2274
< system.cpu1.itb.inst_accesses 43650096 # ITB inst accesses
< system.cpu1.itb.hits 43643100 # DTB hits
< system.cpu1.itb.misses 6996 # DTB misses
< system.cpu1.itb.accesses 43650096 # DTB accesses
< system.cpu1.numCycles 104633766 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 43649040 # ITB inst accesses
> system.cpu1.itb.hits 43642051 # DTB hits
> system.cpu1.itb.misses 6989 # DTB misses
> system.cpu1.itb.accesses 43649040 # DTB accesses
> system.cpu1.numCycles 104614253 # number of cpu cycles simulated
2272,2288c2277,2293
< system.cpu1.fetch.icacheStallCycles 9986103 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 109171918 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 33913093 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 27450404 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 91805384 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 3775592 # Number of cycles fetch has spent squashing
< system.cpu1.fetch.TlbCycles 78970 # Number of cycles fetch has spent waiting for tlb
< system.cpu1.fetch.MiscStallCycles 32292 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu1.fetch.PendingTrapStallCycles 198987 # Number of stall cycles due to pending traps
< system.cpu1.fetch.PendingQuiesceStallCycles 295254 # Number of stall cycles due to pending quiesce instructions
< system.cpu1.fetch.IcacheWaitRetryStallCycles 7461 # Number of stall cycles due to full MSHR
< system.cpu1.fetch.CacheLines 43642483 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 116201 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.ItlbSquashes 2279 # Number of outstanding ITLB misses that were squashed
< system.cpu1.fetch.rateDist::samples 104292247 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 1.296794 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 1.339797 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.icacheStallCycles 9984991 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 109167147 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 33910931 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 27449313 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 91788694 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 3775566 # Number of cycles fetch has spent squashing
> system.cpu1.fetch.TlbCycles 78493 # Number of cycles fetch has spent waiting for tlb
> system.cpu1.fetch.MiscStallCycles 31389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu1.fetch.PendingTrapStallCycles 199715 # Number of stall cycles due to pending traps
> system.cpu1.fetch.PendingQuiesceStallCycles 294230 # Number of stall cycles due to pending quiesce instructions
> system.cpu1.fetch.IcacheWaitRetryStallCycles 7403 # Number of stall cycles due to full MSHR
> system.cpu1.fetch.CacheLines 43641443 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 116254 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.ItlbSquashes 2254 # Number of outstanding ITLB misses that were squashed
> system.cpu1.fetch.rateDist::samples 104272698 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 1.296959 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 1.339784 # Number of instructions fetched each cycle (Total)
2290,2293c2295,2298
< system.cpu1.fetch.rateDist::0 47342099 45.39% 45.39% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 14034599 13.46% 58.85% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 7535653 7.23% 66.08% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 35379896 33.92% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 47324573 45.39% 45.39% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 14035291 13.46% 58.85% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 7536357 7.23% 66.07% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 35376477 33.93% 100.00% # Number of instructions fetched each cycle (Total)
2297,2343c2302,2348
< system.cpu1.fetch.rateDist::total 104292247 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.324112 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 1.043372 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 13023476 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 61678123 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 26726804 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 1110708 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 1753136 # Number of cycles decode is squashing
< system.cpu1.decode.BranchResolved 754254 # Number of times decode resolved a branch
< system.cpu1.decode.BranchMispred 137537 # Number of times decode detected a branch misprediction
< system.cpu1.decode.DecodedInsts 68065454 # Number of instructions handled by decode
< system.cpu1.decode.SquashedInsts 1169726 # Number of squashed instructions handled by decode
< system.cpu1.rename.SquashCycles 1753136 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 17456234 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 2244493 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 56986986 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 23381097 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 2470301 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 55158602 # Number of instructions processed by rename
< system.cpu1.rename.SquashedInsts 230731 # Number of squashed instructions processed by rename
< system.cpu1.rename.ROBFullEvents 262273 # Number of times rename has blocked due to ROB full
< system.cpu1.rename.IQFullEvents 35381 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LQFullEvents 18008 # Number of times rename has blocked due to LQ full
< system.cpu1.rename.SQFullEvents 1443637 # Number of times rename has blocked due to SQ full
< system.cpu1.rename.RenamedOperands 54999686 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 260535269 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 58684549 # Number of integer rename lookups
< system.cpu1.rename.fp_rename_lookups 1692 # Number of floating rename lookups
< system.cpu1.rename.CommittedMaps 52221656 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 2778030 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 1878103 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 1805469 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 13100518 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 10455886 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 6917101 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 629442 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 825387 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 54265513 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 589015 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 53909819 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 113491 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 2298739 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 5813202 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 48820 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 104292247 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 0.516911 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 0.852558 # Number of insts issued each cycle
---
> system.cpu1.fetch.rateDist::total 104272698 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.324152 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 1.043521 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 13017206 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 61665780 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 26725185 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 1111466 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 1753061 # Number of cycles decode is squashing
> system.cpu1.decode.BranchResolved 754244 # Number of times decode resolved a branch
> system.cpu1.decode.BranchMispred 137628 # Number of times decode detected a branch misprediction
> system.cpu1.decode.DecodedInsts 68061507 # Number of instructions handled by decode
> system.cpu1.decode.SquashedInsts 1169291 # Number of squashed instructions handled by decode
> system.cpu1.rename.SquashCycles 1753061 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 17449719 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 2249370 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 56981821 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 23380432 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 2458295 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 55156803 # Number of instructions processed by rename
> system.cpu1.rename.SquashedInsts 230618 # Number of squashed instructions processed by rename
> system.cpu1.rename.ROBFullEvents 263094 # Number of times rename has blocked due to ROB full
> system.cpu1.rename.IQFullEvents 35438 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LQFullEvents 18102 # Number of times rename has blocked due to LQ full
> system.cpu1.rename.SQFullEvents 1431236 # Number of times rename has blocked due to SQ full
> system.cpu1.rename.RenamedOperands 55002903 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 260522537 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 58680311 # Number of integer rename lookups
> system.cpu1.rename.fp_rename_lookups 1689 # Number of floating rename lookups
> system.cpu1.rename.CommittedMaps 52222762 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 2780141 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 1878015 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 1805384 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 13100914 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 10457203 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 6914095 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 629486 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 832023 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 54264845 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 589076 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 53908335 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 111707 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 2293120 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 5811368 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 48776 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 104272698 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 0.516994 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 0.852584 # Number of insts issued each cycle
2345,2350c2350,2355
< system.cpu1.iq.issued_per_cycle::0 71040936 68.12% 68.12% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 16527616 15.85% 83.96% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 13076642 12.54% 96.50% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 3359306 3.22% 99.72% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 287734 0.28% 100.00% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 13 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 71021448 68.11% 68.11% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 16528398 15.85% 83.96% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 13076148 12.54% 96.50% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 3359187 3.22% 99.72% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 287505 0.28% 100.00% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle
2357c2362
< system.cpu1.iq.issued_per_cycle::total 104292247 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 104272698 # Number of insts issued each cycle
2359,2389c2364,2394
< system.cpu1.iq.fu_full::IntAlu 2924694 45.09% 45.09% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 678 0.01% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.10% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 1673523 25.80% 70.90% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 1887909 29.10% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 2925111 45.11% 45.11% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 678 0.01% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 1673253 25.80% 70.93% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 1885198 29.07% 100.00% # attempts to use FU when none available
2393,2417c2398,2422
< system.cpu1.iq.FU_type_0::IntAlu 36727877 68.13% 68.13% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 46567 0.09% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::IntAlu 36727070 68.13% 68.13% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 46542 0.09% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued
2422,2423c2427,2428
< system.cpu1.iq.FU_type_0::MemRead 10379543 19.25% 87.47% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 6752424 12.53% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::MemRead 10379930 19.25% 87.48% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 6751385 12.52% 100.00% # Type of FU issued
2426,2434c2431,2439
< system.cpu1.iq.FU_type_0::total 53909819 # Type of FU issued
< system.cpu1.iq.rate 0.515224 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 6486804 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.120327 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 218706402 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 57161340 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 51920676 # Number of integer instruction queue wakeup accesses
< system.cpu1.iq.fp_inst_queue_reads 5778 # Number of floating instruction queue reads
< system.cpu1.iq.fp_inst_queue_writes 2054 # Number of floating instruction queue writes
---
> system.cpu1.iq.FU_type_0::total 53908335 # Type of FU issued
> system.cpu1.iq.rate 0.515306 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 6484240 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.120283 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 218679535 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 57155155 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 51920155 # Number of integer instruction queue wakeup accesses
> system.cpu1.iq.fp_inst_queue_reads 5780 # Number of floating instruction queue reads
> system.cpu1.iq.fp_inst_queue_writes 2052 # Number of floating instruction queue writes
2436,2438c2441,2443
< system.cpu1.iq.int_alu_accesses 60392866 # Number of integer alu accesses
< system.cpu1.iq.fp_alu_accesses 3691 # Number of floating point alu accesses
< system.cpu1.iew.lsq.thread0.forwLoads 91423 # Number of loads that had data forwarded from stores
---
> system.cpu1.iq.int_alu_accesses 60388817 # Number of integer alu accesses
> system.cpu1.iq.fp_alu_accesses 3692 # Number of floating point alu accesses
> system.cpu1.iew.lsq.thread0.forwLoads 91403 # Number of loads that had data forwarded from stores
2440,2443c2445,2448
< system.cpu1.iew.lsq.thread0.squashedLoads 489842 # Number of loads squashed
< system.cpu1.iew.lsq.thread0.ignoredResponses 678 # Number of memory responses ignored because the instruction is squashed
< system.cpu1.iew.lsq.thread0.memOrderViolation 10158 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 359303 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 490692 # Number of loads squashed
> system.cpu1.iew.lsq.thread0.ignoredResponses 687 # Number of memory responses ignored because the instruction is squashed
> system.cpu1.iew.lsq.thread0.memOrderViolation 10198 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 355978 # Number of stores squashed
2446,2447c2451,2452
< system.cpu1.iew.lsq.thread0.rescheduledLoads 51794 # Number of loads that were rescheduled
< system.cpu1.iew.lsq.thread0.cacheBlocked 70407 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu1.iew.lsq.thread0.rescheduledLoads 51963 # Number of loads that were rescheduled
> system.cpu1.iew.lsq.thread0.cacheBlocked 70332 # Number of times an access to memory failed due to the cache being blocked
2449,2452c2454,2457
< system.cpu1.iew.iewSquashCycles 1753136 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 542605 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 110606 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 54906673 # Number of instructions dispatched to IQ
---
> system.cpu1.iew.iewSquashCycles 1753061 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 546569 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 114085 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 54906076 # Number of instructions dispatched to IQ
2454,2465c2459,2470
< system.cpu1.iew.iewDispLoadInsts 10455886 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 6917101 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 301543 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 9870 # Number of times the IQ has become full, causing a stall
< system.cpu1.iew.iewLSQFullEvents 93230 # Number of times the LSQ has become full, causing a stall
< system.cpu1.iew.memOrderViolationEvents 10158 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 54900 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 127108 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 182008 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 53638957 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 10277477 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 249277 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewDispLoadInsts 10457203 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 6914095 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 301562 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 9838 # Number of times the IQ has become full, causing a stall
> system.cpu1.iew.iewLSQFullEvents 96727 # Number of times the LSQ has become full, causing a stall
> system.cpu1.iew.memOrderViolationEvents 10198 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 54956 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 127310 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 182266 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 53638370 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 10277968 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 248350 # Number of squashed instructions skipped in execute
2467,2475c2472,2480
< system.cpu1.iew.exec_nop 52145 # number of nop insts executed
< system.cpu1.iew.exec_refs 16965020 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 11808497 # Number of branches executed
< system.cpu1.iew.exec_stores 6687543 # Number of stores executed
< system.cpu1.iew.exec_rate 0.512635 # Inst execution rate
< system.cpu1.iew.wb_sent 53498311 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 51922462 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 25227303 # num instructions producing a value
< system.cpu1.iew.wb_consumers 38487680 # num instructions consuming a value
---
> system.cpu1.iew.exec_nop 52155 # number of nop insts executed
> system.cpu1.iew.exec_refs 16965083 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 11807834 # Number of branches executed
> system.cpu1.iew.exec_stores 6687115 # Number of stores executed
> system.cpu1.iew.exec_rate 0.512725 # Inst execution rate
> system.cpu1.iew.wb_sent 53497576 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 51921941 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 25229731 # num instructions producing a value
> system.cpu1.iew.wb_consumers 38490253 # num instructions consuming a value
2477,2478c2482,2483
< system.cpu1.iew.wb_rate 0.496230 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.655464 # average fanout of values written-back
---
> system.cpu1.iew.wb_rate 0.496318 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.655484 # average fanout of values written-back
2480,2485c2485,2490
< system.cpu1.commit.commitSquashedInsts 3659313 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 540195 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 170379 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 102361190 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 0.498018 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.158864 # Number of insts commited each cycle
---
> system.cpu1.commit.commitSquashedInsts 3658728 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 540300 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 170382 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 102340769 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 0.498127 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.159192 # Number of insts commited each cycle
2487,2495c2492,2500
< system.cpu1.commit.committed_per_cycle::0 76777637 75.01% 75.01% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 14293980 13.96% 88.97% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 6079057 5.94% 94.91% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 703860 0.69% 95.60% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 1980599 1.93% 97.53% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 1570719 1.53% 99.07% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 440748 0.43% 99.50% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 123191 0.12% 99.62% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 391399 0.38% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 76762339 75.01% 75.01% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 14287767 13.96% 88.97% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 6080575 5.94% 94.91% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 703802 0.69% 95.60% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 1980023 1.93% 97.53% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 1565125 1.53% 99.06% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 446359 0.44% 99.50% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 123712 0.12% 99.62% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 391067 0.38% 100.00% # Number of insts commited each cycle
2499,2501c2504,2506
< system.cpu1.commit.committed_per_cycle::total 102361190 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 41391892 # Number of instructions committed
< system.cpu1.commit.committedOps 50977682 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 102340769 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 41392870 # Number of instructions committed
> system.cpu1.commit.committedOps 50978714 # Number of ops (including micro ops) committed
2503,2506c2508,2511
< system.cpu1.commit.refs 16523842 # Number of memory references committed
< system.cpu1.commit.loads 9966044 # Number of loads committed
< system.cpu1.commit.membars 209647 # Number of memory barriers committed
< system.cpu1.commit.branches 11639863 # Number of branches committed
---
> system.cpu1.commit.refs 16524628 # Number of memory references committed
> system.cpu1.commit.loads 9966511 # Number of loads committed
> system.cpu1.commit.membars 209715 # Number of memory barriers committed
> system.cpu1.commit.branches 11639820 # Number of branches committed
2508,2509c2513,2514
< system.cpu1.commit.int_insts 45828051 # Number of committed integer instructions.
< system.cpu1.commit.function_calls 3366801 # Number of function calls committed.
---
> system.cpu1.commit.int_insts 45828641 # Number of committed integer instructions.
> system.cpu1.commit.function_calls 3366594 # Number of function calls committed.
2511,2512c2516,2517
< system.cpu1.commit.op_class_0::IntAlu 34404842 67.49% 67.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntMult 45659 0.09% 67.58% # Class of committed instruction
---
> system.cpu1.commit.op_class_0::IntAlu 34405110 67.49% 67.49% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntMult 45637 0.09% 67.58% # Class of committed instruction
2540,2541c2545,2546
< system.cpu1.commit.op_class_0::MemRead 9966044 19.55% 87.14% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemWrite 6557798 12.86% 100.00% # Class of committed instruction
---
> system.cpu1.commit.op_class_0::MemRead 9966511 19.55% 87.14% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemWrite 6558117 12.86% 100.00% # Class of committed instruction
2544,2545c2549,2550
< system.cpu1.commit.op_class_0::total 50977682 # Class of committed instruction
< system.cpu1.commit.bw_lim_events 391399 # number cycles where commit BW limit reached
---
> system.cpu1.commit.op_class_0::total 50978714 # Class of committed instruction
> system.cpu1.commit.bw_lim_events 391067 # number cycles where commit BW limit reached
2547,2559c2552,2564
< system.cpu1.rob.rob_reads 136568898 # The number of ROB reads
< system.cpu1.rob.rob_writes 111201426 # The number of ROB writes
< system.cpu1.timesIdled 53211 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 341519 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 5543537240 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 41359038 # Number of Instructions Simulated
< system.cpu1.committedOps 50944828 # Number of Ops (including micro ops) Simulated
< system.cpu1.cpi 2.529889 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 2.529889 # CPI: Total CPI of All Threads
< system.cpu1.ipc 0.395274 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 0.395274 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 56284416 # number of integer regfile reads
< system.cpu1.int_regfile_writes 35740317 # number of integer regfile writes
---
> system.cpu1.rob.rob_reads 136550879 # The number of ROB reads
> system.cpu1.rob.rob_writes 111203214 # The number of ROB writes
> system.cpu1.timesIdled 53373 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 341555 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 5543525682 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 41360016 # Number of Instructions Simulated
> system.cpu1.committedOps 50945860 # Number of Ops (including micro ops) Simulated
> system.cpu1.cpi 2.529357 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 2.529357 # CPI: Total CPI of All Threads
> system.cpu1.ipc 0.395357 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 0.395357 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 56284604 # number of integer regfile reads
> system.cpu1.int_regfile_writes 35740768 # number of integer regfile writes
2562,2567c2567,2572
< system.cpu1.cc_regfile_reads 191161573 # number of cc regfile reads
< system.cpu1.cc_regfile_writes 15561298 # number of cc regfile writes
< system.cpu1.misc_regfile_reads 205957562 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 388863 # number of misc regfile writes
< system.cpu1.toL2Bus.trans_dist::ReadReq 1295443 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 865390 # Transaction distribution
---
> system.cpu1.cc_regfile_reads 191160889 # number of cc regfile reads
> system.cpu1.cc_regfile_writes 15560745 # number of cc regfile writes
> system.cpu1.misc_regfile_reads 205861724 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 388836 # number of misc regfile writes
> system.cpu1.toL2Bus.trans_dist::ReadReq 1295167 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 865146 # Transaction distribution
2570,2593c2575,2598
< system.cpu1.toL2Bus.trans_dist::Writeback 116918 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 158167 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36233 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 84977 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41950 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 87258 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 79543 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 66388 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215693 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 825104 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17440 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38012 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 2096249 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38897120 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25415568 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 31072 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67528 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 64411288 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 836156 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 1798706 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 5.418986 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.493393 # Request fanout histogram
---
> system.cpu1.toL2Bus.trans_dist::Writeback 117435 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 157667 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 84819 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41863 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 87089 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 79490 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 66369 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215695 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 824924 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17344 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37959 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 2095922 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38897296 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25431436 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30740 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67228 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 64426700 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 835314 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 1798151 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 5.418656 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.493339 # Request fanout histogram
2600,2601c2605,2606
< system.cpu1.toL2Bus.snoop_fanout::5 1045073 58.10% 58.10% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::6 753633 41.90% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::5 1045344 58.13% 58.13% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::6 752807 41.87% 100.00% # Request fanout histogram
2605,2606c2610,2611
< system.cpu1.toL2Bus.snoop_fanout::total 1798706 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 658940429 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 1798151 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 659597923 # Layer occupancy (ticks)
2608c2613
< system.cpu1.toL2Bus.snoopLayer0.occupancy 81408998 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 81215248 # Layer occupancy (ticks)
2610c2615
< system.cpu1.toL2Bus.respLayer0.occupancy 913008604 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 913005612 # Layer occupancy (ticks)
2612c2617
< system.cpu1.toL2Bus.respLayer1.occupancy 404124267 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 403790804 # Layer occupancy (ticks)
2614c2619
< system.cpu1.toL2Bus.respLayer2.occupancy 9811221 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer2.occupancy 9801715 # Layer occupancy (ticks)
2616c2621
< system.cpu1.toL2Bus.respLayer3.occupancy 21199862 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 21218619 # Layer occupancy (ticks)
2618,2624c2623,2629
< system.cpu1.icache.tags.replacements 607230 # number of replacements
< system.cpu1.icache.tags.tagsinuse 499.524831 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 43017967 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 607742 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 70.783272 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 78622263500 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.524831 # Average occupied blocks per requestor
---
> system.cpu1.icache.tags.replacements 607233 # number of replacements
> system.cpu1.icache.tags.tagsinuse 499.524677 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 43016935 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 607745 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 70.781224 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 78589984500 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.524677 # Average occupied blocks per requestor
2631,2669c2636,2674
< system.cpu1.icache.tags.tag_accesses 87892389 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 87892389 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 43017967 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 43017967 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 43017967 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 43017967 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 43017967 # number of overall hits
< system.cpu1.icache.overall_hits::total 43017967 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 624354 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 624354 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 624354 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 624354 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 624354 # number of overall misses
< system.cpu1.icache.overall_misses::total 624354 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5095463294 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 5095463294 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 5095463294 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 5095463294 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 5095463294 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 5095463294 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 43642321 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 43642321 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 43642321 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 43642321 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 43642321 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 43642321 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014306 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.014306 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014306 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.014306 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014306 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.014306 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8161.176663 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 8161.176663 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8161.176663 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 8161.176663 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8161.176663 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 8161.176663 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 277985 # number of cycles access was blocked
---
> system.cpu1.icache.tags.tag_accesses 87890334 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 87890334 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 43016935 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 43016935 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 43016935 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 43016935 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 43016935 # number of overall hits
> system.cpu1.icache.overall_hits::total 43016935 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 624358 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 624358 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 624358 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 624358 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 624358 # number of overall misses
> system.cpu1.icache.overall_misses::total 624358 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5094140300 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 5094140300 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 5094140300 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 5094140300 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 5094140300 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 5094140300 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 43641293 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 43641293 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 43641293 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 43641293 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 43641293 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 43641293 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014307 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.014307 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014307 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.014307 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014307 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.014307 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8159.005410 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 8159.005410 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8159.005410 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 8159.005410 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8159.005410 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 8159.005410 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 274240 # number of cycles access was blocked
2671c2676
< system.cpu1.icache.blocked::no_mshrs 36153 # number of cycles access was blocked
---
> system.cpu1.icache.blocked::no_mshrs 36121 # number of cycles access was blocked
2673c2678
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.689127 # average number of cycles each access was blocked
---
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.592259 # average number of cycles each access was blocked
2677,2698c2682,2703
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16607 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 16607 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 16607 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 16607 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 16607 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 16607 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 607747 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 607747 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 607747 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 607747 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 607747 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 607747 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4104727229 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 4104727229 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4104727229 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 4104727229 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4104727229 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 4104727229 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7919750 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7919750 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7919750 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 7919750 # number of overall MSHR uncacheable cycles
---
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16610 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 16610 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 16610 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 16610 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 16610 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 16610 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 607748 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 607748 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 607748 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 607748 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 607748 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 607748 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4102836710 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 4102836710 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4102836710 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 4102836710 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4102836710 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 4102836710 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8190250 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8190250 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8190250 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 8190250 # number of overall MSHR uncacheable cycles
2705,2710c2710,2715
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6754.006567 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6754.006567 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6754.006567 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 6754.006567 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6754.006567 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 6754.006567 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6750.884758 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6750.884758 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6750.884758 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 6750.884758 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6750.884758 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 6750.884758 # average overall mshr miss latency
2716,2719c2721,2724
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4841798 # number of hwpf identified
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 42982 # number of hwpf that were already in mshr
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4639721 # number of hwpf that were already in the cache
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 43013 # number of hwpf that were already in the prefetch queue
---
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4841881 # number of hwpf identified
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 43251 # number of hwpf that were already in mshr
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4640074 # number of hwpf that were already in the cache
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 42977 # number of hwpf that were already in the prefetch queue
2721,2723c2726,2728
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6040 # number of hwpf removed because MSHR allocated
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 110042 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564522 # number of hwpf spanning a virtual page
---
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6024 # number of hwpf removed because MSHR allocated
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 109555 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564023 # number of hwpf spanning a virtual page
2725,2729c2730,2734
< system.cpu1.l2cache.tags.replacements 85604 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 15613.661542 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 844840 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 100686 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 8.390839 # Average number of references to valid blocks.
---
> system.cpu1.l2cache.tags.replacements 85866 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 15600.635673 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 846675 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 100980 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 8.384581 # Average number of references to valid blocks.
2731,2749c2736,2754
< system.cpu1.l2cache.tags.occ_blocks::writebacks 5991.162043 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 14.384982 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.931077 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 706.431382 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1962.742096 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6937.009962 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.365672 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000878 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000118 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.043117 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.119796 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.423401 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.952982 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9479 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 21 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5582 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 323 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 8003 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1153 # Occupied blocks per task id
---
> system.cpu1.l2cache.tags.occ_blocks::writebacks 6012.739780 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.101116 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.182282 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 726.495477 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1966.711133 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6884.405886 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.366989 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000555 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000072 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.044342 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.120039 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.420191 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.952187 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9526 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 25 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5563 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 306 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 8131 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1089 # Occupied blocks per task id
2751c2756
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id
---
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id
2753,2867c2758,2868
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 418 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4223 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 941 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.578552 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001282 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.340698 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 16875679 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 16875679 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16408 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7497 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.inst 601881 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.data 101311 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 727097 # number of ReadReq hits
< system.cpu1.l2cache.Writeback_hits::writebacks 116917 # number of Writeback hits
< system.cpu1.l2cache.Writeback_hits::total 116917 # number of Writeback hits
< system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2261 # number of UpgradeReq hits
< system.cpu1.l2cache.UpgradeReq_hits::total 2261 # number of UpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 836 # number of SCUpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::total 836 # number of SCUpgradeReq hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28901 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 28901 # number of ReadExReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16408 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7497 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 601881 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 130212 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 755998 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16408 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7497 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 601881 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 130212 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 755998 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 474 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 271 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5861 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.data 72219 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 78825 # number of ReadReq misses
< system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses
< system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28423 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 28423 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22608 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 22608 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32938 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 32938 # number of ReadExReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 474 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 271 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 5861 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 105157 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 111763 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 474 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 271 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 5861 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 105157 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 111763 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10500499 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5483500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 182847956 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1610079123 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 1808911078 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536990378 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 536990378 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 443102047 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 443102047 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 554000 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 554000 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1287438029 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 1287438029 # number of ReadExReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10500499 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5483500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 182847956 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 2897517152 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 3096349107 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10500499 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5483500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 182847956 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 2897517152 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 3096349107 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 16882 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7768 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 607742 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.data 173530 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 805922 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::writebacks 116918 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::total 116918 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30684 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 30684 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23444 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 23444 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61839 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 61839 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 16882 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7768 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 607742 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 235369 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 867761 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 16882 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7768 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 607742 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 235369 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 867761 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.028077 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.034887 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009644 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.416176 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.097807 # miss rate for ReadReq accesses
< system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000009 # miss rate for Writeback accesses
< system.cpu1.l2cache.Writeback_miss_rate::total 0.000009 # miss rate for Writeback accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.926313 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.926313 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.964341 # miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.964341 # miss rate for SCUpgradeReq accesses
---
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 415 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4194 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 954 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.581421 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001526 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.339539 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 16877479 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 16877479 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16335 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7409 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.inst 601802 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.data 101305 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 726851 # number of ReadReq hits
> system.cpu1.l2cache.Writeback_hits::writebacks 117435 # number of Writeback hits
> system.cpu1.l2cache.Writeback_hits::total 117435 # number of Writeback hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2252 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 2252 # number of UpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 837 # number of SCUpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::total 837 # number of SCUpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28910 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 28910 # number of ReadExReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16335 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7409 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 601802 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 130215 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 755761 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16335 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7409 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 601802 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 130215 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 755761 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 472 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 276 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5943 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.data 72078 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 78769 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28388 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 28388 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22558 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 22558 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32913 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 32913 # number of ReadExReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 472 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 276 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 5943 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 104991 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 111682 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 472 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 276 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 5943 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 104991 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 111682 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10433249 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5666498 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 181785702 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1611031625 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 1808917074 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536972883 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 536972883 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 442531028 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 442531028 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 437999 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 437999 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1278690285 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 1278690285 # number of ReadExReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10433249 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5666498 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 181785702 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 2889721910 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 3087607359 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10433249 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5666498 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 181785702 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 2889721910 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 3087607359 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 16807 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7685 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 607745 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.data 173383 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 805620 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::writebacks 117435 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::total 117435 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30640 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 30640 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23395 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 23395 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61823 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 61823 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 16807 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7685 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 607745 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 235206 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 867443 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 16807 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7685 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 607745 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 235206 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 867443 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.028084 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.035914 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009779 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.415715 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.097774 # miss rate for ReadReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.926501 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.926501 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.964223 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.964223 # miss rate for SCUpgradeReq accesses
2870,2905c2871,2906
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532641 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532641 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.028077 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.034887 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009644 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.446775 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.128795 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.028077 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.034887 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009644 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.446775 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.128795 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22152.951477 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20234.317343 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 31197.399079 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22294.397915 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22948.443742 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18892.811385 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18892.811385 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19599.347443 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19599.347443 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 184666.666667 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 184666.666667 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39086.709242 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39086.709242 # average ReadExReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22152.951477 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20234.317343 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 31197.399079 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27554.201356 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 27704.599080 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22152.951477 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20234.317343 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 31197.399079 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27554.201356 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 27704.599080 # average overall miss latency
< system.cpu1.l2cache.blocked_cycles::no_mshrs 23432 # number of cycles access was blocked
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532375 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532375 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.028084 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.035914 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009779 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.446379 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.128749 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.028084 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.035914 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009779 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.446379 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.128749 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22104.341102 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20530.789855 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30588.204947 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22351.225409 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22964.834821 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18915.488340 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18915.488340 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19617.476195 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19617.476195 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 218999.500000 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 218999.500000 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38850.614803 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38850.614803 # average ReadExReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22104.341102 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20530.789855 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30588.204947 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27523.520206 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 27646.418931 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22104.341102 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20530.789855 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30588.204947 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27523.520206 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 27646.418931 # average overall miss latency
> system.cpu1.l2cache.blocked_cycles::no_mshrs 22060 # number of cycles access was blocked
2907c2908
< system.cpu1.l2cache.blocked::no_mshrs 464 # number of cycles access was blocked
---
> system.cpu1.l2cache.blocked::no_mshrs 480 # number of cycles access was blocked
2909c2910
< system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 50.500000 # average number of cycles each access was blocked
---
> system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 45.958333 # average number of cycles each access was blocked
2913,2914c2914,2915
< system.cpu1.l2cache.writebacks::writebacks 40723 # number of writebacks
< system.cpu1.l2cache.writebacks::total 40723 # number of writebacks
---
> system.cpu1.l2cache.writebacks::writebacks 40786 # number of writebacks
> system.cpu1.l2cache.writebacks::total 40786 # number of writebacks
2916,2920c2917,2921
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1292 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 76 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::total 1382 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1310 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 1310 # number of ReadExReq MSHR hits
---
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1367 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 84 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::total 1465 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1237 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 1237 # number of ReadExReq MSHR hits
2922,2924c2923,2925
< system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1292 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1386 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 2692 # number of demand (read+write) MSHR hits
---
> system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1367 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1321 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 2702 # number of demand (read+write) MSHR hits
2926,2997c2927,2994
< system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1292 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1386 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 2692 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 474 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 257 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4569 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 72143 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 77443 # number of ReadReq MSHR misses
< system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses
< system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 110035 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 110035 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28423 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28423 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22608 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22608 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31628 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 31628 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 474 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 257 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4569 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103771 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 109071 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 474 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 257 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4569 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103771 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 110035 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 219106 # number of overall MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7180501 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3513000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 126144777 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1103468683 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1240306961 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3485961286 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3485961286 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 417373575 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 417373575 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 308955268 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308955268 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 463000 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 463000 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 944601401 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 944601401 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7180501 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3513000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 126144777 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2048070084 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 2184908362 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7180501 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3513000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 126144777 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2048070084 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3485961286 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 5670869648 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7061250 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2181994006 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2189055256 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1737322501 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1737322501 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7061250 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3919316507 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3926377757 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028077 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.033084 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.007518 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.415738 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.096092 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000009 # mshr miss rate for Writeback accesses
< system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000009 # mshr miss rate for Writeback accesses
---
> system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1367 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1321 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 2702 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 472 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 262 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4576 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 71994 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 77304 # number of ReadReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 109552 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 109552 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28388 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28388 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22558 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22558 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31676 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 31676 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 472 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 262 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4576 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103670 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 108980 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 472 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 262 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4576 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103670 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 109552 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 218532 # number of overall MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7126751 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3660000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 123437534 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1105460943 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1239685228 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3461172800 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3461172800 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 416881074 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 416881074 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 308366284 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308366284 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 367999 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 367999 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 944446910 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 944446910 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7126751 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3660000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 123437534 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2049907853 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 2184132138 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7126751 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3660000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 123437534 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2049907853 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3461172800 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 5645304938 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7340750 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2182190507 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2189531257 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1737661499 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1737661499 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7340750 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3919852006 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3927192756 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028084 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.034092 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.007529 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.415231 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.095956 # mshr miss rate for ReadReq accesses
3000,3003c2997,3000
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.926313 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.926313 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.964341 # mshr miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.964341 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.926501 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.926501 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.964223 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.964223 # mshr miss rate for SCUpgradeReq accesses
3006,3016c3003,3013
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.511457 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.511457 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028077 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.033084 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.007518 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.440886 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.125692 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028077 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.033084 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.007518 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.440886 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.512366 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.512366 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028084 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.034092 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.007529 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.440763 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.125634 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028084 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.034092 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.007529 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.440763 # mshr miss rate for overall accesses
3018,3044c3015,3041
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.252496 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15148.736287 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13669.260700 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27608.837163 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15295.575219 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16015.740106 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31680.476994 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31680.476994 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14684.360377 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14684.360377 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13665.749646 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13665.749646 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 154333.333333 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 154333.333333 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29865.985867 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29865.985867 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15148.736287 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13669.260700 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27608.837163 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19736.439699 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20031.982488 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15148.736287 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13669.260700 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27608.837163 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19736.439699 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31680.476994 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25881.854664 # average overall mshr miss latency
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.251927 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15099.048729 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13969.465649 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 26974.985577 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15354.903784 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16036.495240 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31593.880532 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31593.880532 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14685.116035 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14685.116035 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13669.930136 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13669.930136 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 183999.500000 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183999.500000 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29815.851433 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29815.851433 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15099.048729 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13969.465649 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26974.985577 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19773.394936 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20041.586878 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15099.048729 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13969.465649 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26974.985577 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19773.394936 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31593.880532 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25832.852571 # average overall mshr miss latency
3054,3062c3051,3059
< system.cpu1.dcache.tags.replacements 191151 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 472.645791 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 15740842 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 191475 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 82.208341 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 102871069000 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.645791 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923136 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.923136 # Average percentage of cache occupancy
---
> system.cpu1.dcache.tags.replacements 191071 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 472.558673 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 15741841 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 191395 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 82.247922 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 102871508500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.558673 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922966 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.922966 # Average percentage of cache occupancy
3067,3146c3064,3143
< system.cpu1.dcache.tags.tag_accesses 32982505 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 32982505 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 9573878 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 9573878 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 5910219 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 5910219 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49544 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 49544 # number of SoftPFReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79107 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 79107 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70933 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 70933 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 15484097 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 15484097 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 15533641 # number of overall hits
< system.cpu1.dcache.overall_hits::total 15533641 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 219762 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 219762 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 398432 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 398432 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30092 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 30092 # number of SoftPFReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18147 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 18147 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23447 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 23447 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 618194 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 618194 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 648286 # number of overall misses
< system.cpu1.dcache.overall_misses::total 648286 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3451433990 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 3451433990 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8738929077 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 8738929077 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362617750 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 362617750 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 543339293 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 543339293 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 593000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 593000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 12190363067 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 12190363067 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 12190363067 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 12190363067 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 9793640 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 9793640 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 6308651 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 6308651 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79636 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 79636 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97254 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 97254 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94380 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 94380 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 16102291 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 16102291 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 16181927 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 16181927 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022439 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.022439 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.063156 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.063156 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377869 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377869 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186594 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186594 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248432 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248432 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038392 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.038392 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040062 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.040062 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15705.326626 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 15705.326626 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21933.301233 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 21933.301233 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19982.242244 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19982.242244 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23173.083678 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23173.083678 # average StoreCondReq miss latency
---
> system.cpu1.dcache.tags.tag_accesses 32983753 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 32983753 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 9574420 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 9574420 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 5910665 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 5910665 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49536 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 49536 # number of SoftPFReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79144 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 79144 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71002 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 71002 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 15485085 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 15485085 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 15534621 # number of overall hits
> system.cpu1.dcache.overall_hits::total 15534621 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 219558 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 219558 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 398300 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 398300 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30127 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 30127 # number of SoftPFReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18119 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 18119 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23397 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 23397 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 617858 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 617858 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 647985 # number of overall misses
> system.cpu1.dcache.overall_misses::total 647985 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3453411003 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 3453411003 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8719629262 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 8719629262 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362936751 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 362936751 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 542268315 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 542268315 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 468000 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 468000 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 12173040265 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 12173040265 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 12173040265 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 12173040265 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 9793978 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 9793978 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 6308965 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 6308965 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79663 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 79663 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97263 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 97263 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94399 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 94399 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 16102943 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 16102943 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 16182606 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 16182606 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022418 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.022418 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.063132 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.063132 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.378181 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.378181 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186289 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186289 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.247852 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.247852 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038369 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.038369 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040042 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.040042 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15728.923578 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15728.923578 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21892.114642 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 21892.114642 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20030.727468 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20030.727468 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23176.831004 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23176.831004 # average StoreCondReq miss latency
3149,3158c3146,3155
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19719.316375 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 19719.316375 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18803.989392 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 18803.989392 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked
< system.cpu1.dcache.blocked_cycles::no_targets 1116254 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_mshrs 47 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_targets 39673 # number of cycles access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.191489 # average number of cycles each access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_targets 28.136365 # average number of cycles each access was blocked
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19702.003154 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 19702.003154 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18785.990825 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 18785.990825 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 358 # number of cycles access was blocked
> system.cpu1.dcache.blocked_cycles::no_targets 1110000 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_mshrs 38 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_targets 39631 # number of cycles access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.421053 # average number of cycles each access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_targets 28.008377 # average number of cycles each access was blocked
3161,3232c3158,3229
< system.cpu1.dcache.writebacks::writebacks 116918 # number of writebacks
< system.cpu1.dcache.writebacks::total 116918 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79804 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 79804 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306588 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 306588 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13195 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13195 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 386392 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 386392 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 386392 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 386392 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139958 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 139958 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91844 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 91844 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28639 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 28639 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4952 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4952 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23447 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 23447 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 231802 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 231802 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 260441 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 260441 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1829576308 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1829576308 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2203829941 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2203829941 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 493924497 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 493924497 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86545750 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86545750 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 495264707 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 495264707 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 567000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 567000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4033406249 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 4033406249 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4527330746 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 4527330746 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298504494 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298504494 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826458496 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826458496 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4124962990 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4124962990 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014291 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014291 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014558 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014558 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359624 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359624 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050918 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050918 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248432 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248432 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014396 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.014396 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016095 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.016095 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13072.323897 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13072.323897 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23995.361058 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23995.361058 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17246.569259 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17246.569259 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17476.928514 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17476.928514 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21122.732418 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21122.732418 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 117436 # number of writebacks
> system.cpu1.dcache.writebacks::total 117436 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79714 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 79714 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306518 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 306518 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13187 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13187 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 386232 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 386232 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 386232 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 386232 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139844 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 139844 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91782 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 91782 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28626 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 28626 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4932 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4932 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23397 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 23397 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 231626 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 231626 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 260252 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 260252 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1827153559 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1827153559 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2193887187 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2193887187 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 494621242 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 494621242 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86939750 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86939750 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 494306685 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 494306685 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 448000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 448000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4021040746 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 4021040746 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4515661988 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 4515661988 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298831492 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298831492 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826840995 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826840995 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4125672487 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4125672487 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014279 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014279 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014548 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014548 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359339 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359339 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050708 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050708 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.247852 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.247852 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014384 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.014384 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016082 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.016082 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13065.655724 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13065.655724 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23903.240145 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23903.240145 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17278.741075 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17278.741075 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17627.686537 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17627.686537 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21126.925888 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21126.925888 # average StoreCondReq mshr miss latency
3235,3238c3232,3235
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17400.221952 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17400.221952 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17383.325767 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17383.325767 # average overall mshr miss latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17360.057791 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17360.057791 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17351.113490 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17351.113490 # average overall mshr miss latency
3247c3244
< system.iocache.tags.tagsinuse 14.560241 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 14.560234 # Cycle average of tags in use
3251,3252c3248,3249
< system.iocache.tags.warmup_cycle 254140751000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 14.560241 # Average occupied blocks per requestor
---
> system.iocache.tags.warmup_cycle 254140674000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 14.560234 # Average occupied blocks per requestor
3258,3259c3255,3256
< system.iocache.tags.tag_accesses 328407 # Number of tag accesses
< system.iocache.tags.data_accesses 328407 # Number of data accesses
---
> system.iocache.tags.tag_accesses 328359 # Number of tag accesses
> system.iocache.tags.data_accesses 328359 # Number of data accesses
3264,3265c3261,3262
< system.iocache.WriteInvalidateReq_misses::realview.ide 21 # number of WriteInvalidateReq misses
< system.iocache.WriteInvalidateReq_misses::total 21 # number of WriteInvalidateReq misses
---
> system.iocache.WriteInvalidateReq_misses::realview.ide 15 # number of WriteInvalidateReq misses
> system.iocache.WriteInvalidateReq_misses::total 15 # number of WriteInvalidateReq misses
3270,3275c3267,3272
< system.iocache.ReadReq_miss_latency::realview.ide 30846377 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 30846377 # number of ReadReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 30846377 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 30846377 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 30846377 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 30846377 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 30832377 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 30832377 # number of ReadReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 30832377 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 30832377 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 30832377 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 30832377 # number of overall miss cycles
3278,3279c3275,3276
< system.iocache.WriteInvalidateReq_accesses::realview.ide 36245 # number of WriteInvalidateReq accesses(hits+misses)
< system.iocache.WriteInvalidateReq_accesses::total 36245 # number of WriteInvalidateReq accesses(hits+misses)
---
> system.iocache.WriteInvalidateReq_accesses::realview.ide 36239 # number of WriteInvalidateReq accesses(hits+misses)
> system.iocache.WriteInvalidateReq_accesses::total 36239 # number of WriteInvalidateReq accesses(hits+misses)
3286,3287c3283,3284
< system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000579 # miss rate for WriteInvalidateReq accesses
< system.iocache.WriteInvalidateReq_miss_rate::total 0.000579 # miss rate for WriteInvalidateReq accesses
---
> system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000414 # miss rate for WriteInvalidateReq accesses
> system.iocache.WriteInvalidateReq_miss_rate::total 0.000414 # miss rate for WriteInvalidateReq accesses
3292,3297c3289,3294
< system.iocache.ReadReq_avg_miss_latency::realview.ide 124884.117409 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 124884.117409 # average ReadReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 124884.117409 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 124884.117409 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 124884.117409 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 124884.117409 # average overall miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 124827.437247 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 124827.437247 # average ReadReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 124827.437247 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 124827.437247 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 124827.437247 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 124827.437247 # average overall miss latency
3312,3319c3309,3316
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 18001377 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 18001377 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2249753293 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2249753293 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 18001377 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 18001377 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 18001377 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 18001377 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 17987377 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 17987377 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2254879547 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2254879547 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 17987377 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 17987377 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 17987377 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 17987377 # number of overall MSHR miss cycles
3326,3327c3323,3324
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72880.068826 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 72880.068826 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72823.388664 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 72823.388664 # average ReadReq mshr miss latency
3330,3333c3327,3330
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 72880.068826 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 72880.068826 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 72880.068826 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 72880.068826 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 72823.388664 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 72823.388664 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 72823.388664 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 72823.388664 # average overall mshr miss latency
3336c3333
< system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed
---
> system.cpu0.kern.inst.quiesce 1856 # number of quiesce instructions executed
3338c3335
< system.cpu1.kern.inst.quiesce 2758 # number of quiesce instructions executed
---
> system.cpu1.kern.inst.quiesce 2744 # number of quiesce instructions executed