3,5c3,5
< sim_seconds 2.605649 # Number of seconds simulated
< sim_ticks 2605649343000 # Number of ticks simulated
< final_tick 2605649343000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.605644 # Number of seconds simulated
> sim_ticks 2605643988500 # Number of ticks simulated
> final_tick 2605643988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 57764 # Simulator instruction rate (inst/s)
< host_op_rate 74374 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2397402056 # Simulator tick rate (ticks/s)
< host_mem_usage 474764 # Number of bytes of host memory used
< host_seconds 1086.86 # Real time elapsed on the host
< sim_insts 62781325 # Number of instructions simulated
< sim_ops 80834116 # Number of ops (including micro ops) simulated
---
> host_inst_rate 56388 # Simulator instruction rate (inst/s)
> host_op_rate 72604 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2339801960 # Simulator tick rate (ticks/s)
> host_mem_usage 475216 # Number of bytes of host memory used
> host_seconds 1113.62 # Real time elapsed on the host
> sim_insts 62794806 # Number of instructions simulated
> sim_ops 80853196 # Number of ops (including micro ops) simulated
17c17
< system.physmem.bytes_read::cpu0.dtb.walker 1024 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory
19,28c19,28
< system.physmem.bytes_read::cpu0.inst 383680 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 5448188 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 438080 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 4125688 # Number of bytes read from this memory
< system.physmem.bytes_read::total 131508276 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 383680 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 438080 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 821760 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 4229952 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu0.inst 394240 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 4377212 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 429184 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 5246712 # Number of bytes read from this memory
> system.physmem.bytes_read::total 131559796 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 394240 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 429184 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 823424 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 4275584 # Number of bytes written to this memory
31c31
< system.physmem.bytes_written::total 7259088 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 7304720 # Number of bytes written to this memory
33c33
< system.physmem.num_reads::cpu0.dtb.walker 16 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory
35,41c35,41
< system.physmem.num_reads::cpu0.inst 5995 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 85202 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 6845 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 64492 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 15301383 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 66093 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu0.inst 6160 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 68468 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 6706 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 82008 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 15302188 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 66806 # Number of write requests responded to by this memory
44,46c44,46
< system.physmem.num_writes::total 823377 # Number of write requests responded to by this memory
< system.physmem.bw_read::realview.clcd 46479979 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.dtb.walker 393 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 824090 # Number of write requests responded to by this memory
> system.physmem.bw_read::realview.clcd 46480075 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.dtb.walker 295 # Total read bandwidth from this memory (bytes/s)
48,57c48,57
< system.physmem.bw_read::cpu0.inst 147249 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 2090914 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 368 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 168127 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 1583363 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 50470443 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 147249 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 168127 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 315376 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1623377 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 151302 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 1679896 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 393 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 164713 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 2013595 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 50490319 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 151302 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 164713 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 316016 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1640893 # Write bandwidth from this memory (bytes/s)
59,63c59,63
< system.physmem.bw_write::cpu1.data 1156002 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 2785904 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1623377 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.clcd 46479979 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::cpu1.data 1156004 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 2803422 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1640893 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.clcd 46480075 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 295 # Total bandwidth to/from this memory (bytes/s)
65,114c65,114
< system.physmem.bw_total::cpu0.inst 147249 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 2097438 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 368 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 168127 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 2739365 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 53256346 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 15301383 # Number of read requests accepted
< system.physmem.writeReqs 823377 # Number of write requests accepted
< system.physmem.readBursts 15301383 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 823377 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 973889408 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 5399104 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7284800 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 131508276 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7259088 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 84361 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 709522 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 14082 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 956098 # Per bank write bursts
< system.physmem.perBankRdBursts::1 950020 # Per bank write bursts
< system.physmem.perBankRdBursts::2 950090 # Per bank write bursts
< system.physmem.perBankRdBursts::3 949980 # Per bank write bursts
< system.physmem.perBankRdBursts::4 956223 # Per bank write bursts
< system.physmem.perBankRdBursts::5 949119 # Per bank write bursts
< system.physmem.perBankRdBursts::6 948884 # Per bank write bursts
< system.physmem.perBankRdBursts::7 948711 # Per bank write bursts
< system.physmem.perBankRdBursts::8 956337 # Per bank write bursts
< system.physmem.perBankRdBursts::9 950158 # Per bank write bursts
< system.physmem.perBankRdBursts::10 948908 # Per bank write bursts
< system.physmem.perBankRdBursts::11 948900 # Per bank write bursts
< system.physmem.perBankRdBursts::12 955944 # Per bank write bursts
< system.physmem.perBankRdBursts::13 949314 # Per bank write bursts
< system.physmem.perBankRdBursts::14 949393 # Per bank write bursts
< system.physmem.perBankRdBursts::15 948943 # Per bank write bursts
< system.physmem.perBankWrBursts::0 7119 # Per bank write bursts
< system.physmem.perBankWrBursts::1 7037 # Per bank write bursts
< system.physmem.perBankWrBursts::2 7071 # Per bank write bursts
< system.physmem.perBankWrBursts::3 7168 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7696 # Per bank write bursts
< system.physmem.perBankWrBursts::5 7220 # Per bank write bursts
< system.physmem.perBankWrBursts::6 7070 # Per bank write bursts
< system.physmem.perBankWrBursts::7 6913 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7415 # Per bank write bursts
< system.physmem.perBankWrBursts::9 7415 # Per bank write bursts
< system.physmem.perBankWrBursts::10 6887 # Per bank write bursts
< system.physmem.perBankWrBursts::11 6788 # Per bank write bursts
< system.physmem.perBankWrBursts::12 7071 # Per bank write bursts
< system.physmem.perBankWrBursts::13 6872 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7197 # Per bank write bursts
< system.physmem.perBankWrBursts::15 6886 # Per bank write bursts
---
> system.physmem.bw_total::cpu0.inst 151302 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 1686421 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 164713 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 3169600 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 53293741 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 15302188 # Number of read requests accepted
> system.physmem.writeReqs 824090 # Number of write requests accepted
> system.physmem.readBursts 15302188 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 824090 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 974626176 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 4713856 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7328128 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 131559796 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7304720 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 73654 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 709569 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 14159 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 956238 # Per bank write bursts
> system.physmem.perBankRdBursts::1 951013 # Per bank write bursts
> system.physmem.perBankRdBursts::2 950196 # Per bank write bursts
> system.physmem.perBankRdBursts::3 950464 # Per bank write bursts
> system.physmem.perBankRdBursts::4 956634 # Per bank write bursts
> system.physmem.perBankRdBursts::5 950822 # Per bank write bursts
> system.physmem.perBankRdBursts::6 949869 # Per bank write bursts
> system.physmem.perBankRdBursts::7 949811 # Per bank write bursts
> system.physmem.perBankRdBursts::8 956681 # Per bank write bursts
> system.physmem.perBankRdBursts::9 951277 # Per bank write bursts
> system.physmem.perBankRdBursts::10 949961 # Per bank write bursts
> system.physmem.perBankRdBursts::11 949024 # Per bank write bursts
> system.physmem.perBankRdBursts::12 956331 # Per bank write bursts
> system.physmem.perBankRdBursts::13 950586 # Per bank write bursts
> system.physmem.perBankRdBursts::14 950041 # Per bank write bursts
> system.physmem.perBankRdBursts::15 949586 # Per bank write bursts
> system.physmem.perBankWrBursts::0 7062 # Per bank write bursts
> system.physmem.perBankWrBursts::1 6963 # Per bank write bursts
> system.physmem.perBankWrBursts::2 7126 # Per bank write bursts
> system.physmem.perBankWrBursts::3 7116 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7811 # Per bank write bursts
> system.physmem.perBankWrBursts::5 7409 # Per bank write bursts
> system.physmem.perBankWrBursts::6 7013 # Per bank write bursts
> system.physmem.perBankWrBursts::7 7004 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7458 # Per bank write bursts
> system.physmem.perBankWrBursts::9 7561 # Per bank write bursts
> system.physmem.perBankWrBursts::10 6914 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6583 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7179 # Per bank write bursts
> system.physmem.perBankWrBursts::13 7101 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7219 # Per bank write bursts
> system.physmem.perBankWrBursts::15 6983 # Per bank write bursts
117c117
< system.physmem.totGap 2605648115500 # Total gap between requests
---
> system.physmem.totGap 2605642823000 # Total gap between requests
124c124
< system.physmem.readPktSize::6 162458 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 163263 # Read request sizes (log2)
131,150c131,150
< system.physmem.writePktSize::6 66093 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 1062706 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 998935 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 950903 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 959607 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 945820 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 946342 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 2754714 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 2746120 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 3637640 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 38272 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 34182 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 34523 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 32360 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 30630 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 22253 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 21644 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 254 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 101 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 66806 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1074226 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 1009957 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 967065 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 1078396 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 970167 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 1034458 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 2664402 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 2566961 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 3342237 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 136100 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 116220 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 107345 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 103465 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 19833 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 18840 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 18525 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 210 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 112 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see
152,153c152,153
< system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
179,219c179,219
< system.physmem.wrQLenPdf::15 1944 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 1998 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 2401 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4700 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5971 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6079 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6148 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 6196 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 6200 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 6189 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 6821 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 6509 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 6365 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 7158 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 6652 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6157 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6118 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6071 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 2256 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 774 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 680 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 711 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 674 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 604 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 634 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 601 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 590 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 593 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 556 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 578 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 550 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 549 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 549 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 543 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 541 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 540 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 543 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 541 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 547 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 3 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 2784 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3035 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4735 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6745 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6909 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6865 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6844 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 7248 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 6920 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 6907 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 6964 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 6850 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 6821 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7229 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 6810 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6824 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6992 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6732 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 139 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 96 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 49 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
228,287c228,272
< system.physmem.bytesPerActivate::samples 965097 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 1010.691593 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 992.992769 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 104.599429 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 5712 0.59% 0.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 4413 0.46% 1.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 2116 0.22% 1.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 1499 0.16% 1.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 1121 0.12% 1.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 815 0.08% 1.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 661 0.07% 1.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 851 0.09% 1.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 947909 98.22% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 965097 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5955 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 2555.332662 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 92927.024688 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-262143 5949 99.90% 99.90% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::262144-524287 1 0.02% 99.92% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::524288-786431 1 0.02% 99.93% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.02% 99.95% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 2 0.03% 99.98% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::6.02931e+06-6.29146e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 5955 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5955 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 19.114190 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.218740 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 7.431880 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 3971 66.68% 66.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 19 0.32% 67.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 175 2.94% 69.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 1141 19.16% 89.10% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 44 0.74% 89.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 19 0.32% 90.16% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 21 0.35% 90.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::23 10 0.17% 90.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24 6 0.10% 90.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::25 3 0.05% 90.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::26 4 0.07% 90.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::27 1 0.02% 90.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::30 1 0.02% 90.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::34 1 0.02% 90.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::39 1 0.02% 90.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40 1 0.02% 90.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::41 146 2.45% 93.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::42 311 5.22% 98.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::43 13 0.22% 98.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44 13 0.22% 99.09% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::45 16 0.27% 99.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::46 22 0.37% 99.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::47 9 0.15% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48 4 0.07% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::49 3 0.05% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5955 # Writes before turning the bus around for reads
< system.physmem.totQLat 579051796250 # Total ticks spent queuing
< system.physmem.totMemAccLat 683715373750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 76085110000 # Total ticks spent in databus transfers
< system.physmem.totBankLat 28578467500 # Total ticks spent accessing banks
< system.physmem.avgQLat 38052.90 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 1878.06 # Average bank access latency per DRAM burst
---
> system.physmem.bytesPerActivate::samples 1012463 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 969.866853 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 900.909804 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 207.662919 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 24967 2.47% 2.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 21104 2.08% 4.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 8681 0.86% 5.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2506 0.25% 5.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2720 0.27% 5.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2029 0.20% 6.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 8638 0.85% 6.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1014 0.10% 7.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 940804 92.92% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1012463 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6706 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 2270.880853 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 84552.226363 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-262143 6700 99.91% 99.91% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::262144-524287 1 0.01% 99.93% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::524288-786431 1 0.01% 99.94% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.01% 99.96% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 1 0.01% 99.97% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::2.88358e+06-3.14573e+06 1 0.01% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::5.24288e+06-5.50502e+06 1 0.01% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 6706 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6706 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.074560 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.020748 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.396636 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 3829 57.10% 57.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 48 0.72% 57.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 1779 26.53% 84.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 878 13.09% 97.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 53 0.79% 98.23% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 31 0.46% 98.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 34 0.51% 99.19% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 40 0.60% 99.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24 12 0.18% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::26 1 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6706 # Writes before turning the bus around for reads
> system.physmem.totQLat 395588666000 # Total ticks spent queuing
> system.physmem.totMemAccLat 681123678500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 76142670000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 25976.81 # Average queueing delay per DRAM burst
289,293c274,278
< system.physmem.avgMemAccLat 44930.96 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 373.76 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 2.80 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 50.47 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 44726.81 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 374.04 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 50.49 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s
298,306c283,295
< system.physmem.avgRdQLen 6.53 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 26.75 # Average write queue length when enqueuing
< system.physmem.readRowHits 14231578 # Number of row buffer hits during reads
< system.physmem.writeRowHits 96073 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 93.52 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 84.38 # Row buffer hit rate for writes
< system.physmem.avgGap 161592.99 # Average gap between requests
< system.physmem.pageHitRate 93.46 # Row buffer hit rate, read and write combined
< system.physmem.prechargeAllPercent 4.22 # Percentage of time for which DRAM has all the banks in precharge state
---
> system.physmem.avgRdQLen 6.23 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 26.05 # Average write queue length when enqueuing
> system.physmem.readRowHits 14234195 # Number of row buffer hits during reads
> system.physmem.writeRowHits 96378 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 93.47 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 84.16 # Row buffer hit rate for writes
> system.physmem.avgGap 161577.45 # Average gap between requests
> system.physmem.pageHitRate 93.40 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 2260536385250 # Time in different power states
> system.physmem.memoryStateTime::REF 87007960000 # Time in different power states
> system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
> system.physmem.memoryStateTime::ACT 258093332250 # Time in different power states
> system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
325,336c314,325
< system.membus.throughput 54186995 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 16352581 # Transaction distribution
< system.membus.trans_dist::ReadResp 16352581 # Transaction distribution
< system.membus.trans_dist::WriteReq 769189 # Transaction distribution
< system.membus.trans_dist::WriteResp 769189 # Transaction distribution
< system.membus.trans_dist::Writeback 66093 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 35785 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 18271 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 14082 # Transaction distribution
< system.membus.trans_dist::ReadExReq 137406 # Transaction distribution
< system.membus.trans_dist::ReadExResp 137045 # Transaction distribution
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384396 # Packet count per connected master and slave (bytes)
---
> system.membus.throughput 54224369 # Throughput (bytes/s)
> system.membus.trans_dist::ReadReq 16352672 # Transaction distribution
> system.membus.trans_dist::ReadResp 16352672 # Transaction distribution
> system.membus.trans_dist::WriteReq 769183 # Transaction distribution
> system.membus.trans_dist::WriteResp 769183 # Transaction distribution
> system.membus.trans_dist::Writeback 66806 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 35949 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 18292 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 14159 # Transaction distribution
> system.membus.trans_dist::ReadExReq 138125 # Transaction distribution
> system.membus.trans_dist::ReadExResp 137746 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384364 # Packet count per connected master and slave (bytes)
338c327
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13840 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13834 # Packet count per connected master and slave (bytes)
341,342c330,331
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1974294 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 4374590 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1976897 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 4377155 # Packet count per connected master and slave (bytes)
345,346c334,335
< system.membus.pkt_count::total 34652222 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392725 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 34654787 # Packet count per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392677 # Cumulative packet size per connected master and slave (bytes)
348c337
< system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27680 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27668 # Cumulative packet size per connected master and slave (bytes)
351,352c340,341
< system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17656836 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::total 20081781 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17753988 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.l2c.mem_side::total 20178873 # Cumulative packet size per connected master and slave (bytes)
355,356c344,345
< system.membus.tot_pkt_size::total 141192309 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 141192309 # Total data (bytes)
---
> system.membus.tot_pkt_size::total 141289401 # Cumulative packet size per connected master and slave (bytes)
> system.membus.data_through_bus 141289401 # Total data (bytes)
358c347
< system.membus.reqLayer0.occupancy 1488242000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 1487962500 # Layer occupancy (ticks)
362c351
< system.membus.reqLayer2.occupancy 11807000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 11808000 # Layer occupancy (ticks)
366c355
< system.membus.reqLayer5.occupancy 1798000 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 1796000 # Layer occupancy (ticks)
368c357
< system.membus.reqLayer6.occupancy 17652470999 # Layer occupancy (ticks)
---
> system.membus.reqLayer6.occupancy 17659548997 # Layer occupancy (ticks)
370c359
< system.membus.respLayer1.occupancy 4843604815 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 4847870095 # Layer occupancy (ticks)
372c361
< system.membus.respLayer2.occupancy 37703679634 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 37379122644 # Layer occupancy (ticks)
375,379c364,368
< system.l2c.tags.replacements 72164 # number of replacements
< system.l2c.tags.tagsinuse 53016.131060 # Cycle average of tags in use
< system.l2c.tags.total_refs 1876966 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 137304 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 13.670148 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 72974 # number of replacements
> system.l2c.tags.tagsinuse 53023.948009 # Cycle average of tags in use
> system.l2c.tags.total_refs 1873330 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 138152 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 13.559920 # Average number of references to valid blocks.
381,390c370,379
< system.l2c.tags.occ_blocks::writebacks 37702.356015 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 7.377107 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000365 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 4186.473555 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 2957.675740 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.683393 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 4035.806716 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 4115.758170 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.575292 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000113 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_blocks::writebacks 37706.296895 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.412172 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000364 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 4169.126027 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 2962.597547 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.621110 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 4061.748879 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 4107.145016 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.575352 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000083 # Average percentage of cache occupancy
392,397c381,386
< system.l2c.tags.occ_percent::cpu0.inst 0.063881 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.045131 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000163 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.061582 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.062801 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.808962 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_percent::cpu0.inst 0.063616 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.045206 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000177 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.061977 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.062670 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.809081 # Average percentage of cache occupancy
399,406c388,394
< system.l2c.tags.occ_task_id_blocks::1024 65136 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 8263 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 53454 # Occupied blocks per task id
---
> system.l2c.tags.occ_task_id_blocks::1024 65174 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 3154 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 9081 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 52631 # Occupied blocks per task id
408,449c396,437
< system.l2c.tags.occ_task_id_percent::1024 0.993896 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 18860644 # Number of tag accesses
< system.l2c.tags.data_accesses 18860644 # Number of data accesses
< system.l2c.ReadReq_hits::cpu0.dtb.walker 23595 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.itb.walker 5577 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.inst 409210 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 169724 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.dtb.walker 33221 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.itb.walker 5824 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 593571 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 196649 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1437371 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 582434 # number of Writeback hits
< system.l2c.Writeback_hits::total 582434 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 737 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 1202 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 1939 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 203 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 149 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 352 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 52746 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 54725 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 107471 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 23595 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 5577 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 409210 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 222470 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 33221 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 5824 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 593571 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 251374 # number of demand (read+write) hits
< system.l2c.demand_hits::total 1544842 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 23595 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 5577 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 409210 # number of overall hits
< system.l2c.overall_hits::cpu0.data 222470 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 33221 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 5824 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 593571 # number of overall hits
< system.l2c.overall_hits::cpu1.data 251374 # number of overall hits
< system.l2c.overall_hits::total 1544842 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.dtb.walker 16 # number of ReadReq misses
---
> system.l2c.tags.occ_task_id_percent::1024 0.994476 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 18850449 # Number of tag accesses
> system.l2c.tags.data_accesses 18850449 # Number of data accesses
> system.l2c.ReadReq_hits::cpu0.dtb.walker 22712 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.itb.walker 4441 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.inst 393676 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 165723 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.dtb.walker 33196 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.itb.walker 5802 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 607870 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 201576 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1434996 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 583128 # number of Writeback hits
> system.l2c.Writeback_hits::total 583128 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 1123 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 727 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 1850 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 207 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 158 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 365 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 47567 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 59393 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 106960 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 22712 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 4441 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 393676 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 213290 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 33196 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 5802 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 607870 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 260969 # number of demand (read+write) hits
> system.l2c.demand_hits::total 1541956 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 22712 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 4441 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 393676 # number of overall hits
> system.l2c.overall_hits::cpu0.data 213290 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 33196 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 5802 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 607870 # number of overall hits
> system.l2c.overall_hits::cpu1.data 260969 # number of overall hits
> system.l2c.overall_hits::total 1541956 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.dtb.walker 12 # number of ReadReq misses
451,466c439,454
< system.l2c.ReadReq_misses::cpu0.inst 5877 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 6190 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.inst 6810 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 6416 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 25326 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 5271 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 4770 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 10041 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 769 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 576 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 1345 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 80429 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 59312 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 139741 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 16 # number of demand (read+write) misses
---
> system.l2c.ReadReq_misses::cpu0.inst 6041 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 6321 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.dtb.walker 16 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.inst 6670 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 6363 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 25425 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 5691 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 4436 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 10127 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 767 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 589 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 1356 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 63545 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 76877 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 140422 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 12 # number of demand (read+write) misses
468,474c456,462
< system.l2c.demand_misses::cpu0.inst 5877 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 86619 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 6810 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 65728 # number of demand (read+write) misses
< system.l2c.demand_misses::total 165067 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 16 # number of overall misses
---
> system.l2c.demand_misses::cpu0.inst 6041 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 69866 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 6670 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 83240 # number of demand (read+write) misses
> system.l2c.demand_misses::total 165847 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 12 # number of overall misses
476,618c464,606
< system.l2c.overall_misses::cpu0.inst 5877 # number of overall misses
< system.l2c.overall_misses::cpu0.data 86619 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 6810 # number of overall misses
< system.l2c.overall_misses::cpu1.data 65728 # number of overall misses
< system.l2c.overall_misses::total 165067 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1263000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.itb.walker 158000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.inst 424519750 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 461015999 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1424250 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 503203750 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 495567749 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 1887152498 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.data 8440130 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 13402927 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 21843057 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 510978 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2957372 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 3468350 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 5751042289 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 4687313508 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 10438355797 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 1263000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 158000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 424519750 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 6212058288 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 1424250 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 503203750 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 5182881257 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 12325508295 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 1263000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 158000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 424519750 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 6212058288 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 1424250 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 503203750 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 5182881257 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 12325508295 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.dtb.walker 23611 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.itb.walker 5579 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.inst 415087 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 175914 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.dtb.walker 33236 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.itb.walker 5824 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 600381 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 203065 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 1462697 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 582434 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 582434 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 6008 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 5972 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 11980 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 972 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 725 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 1697 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 133175 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 114037 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 247212 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 23611 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 5579 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 415087 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 309089 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 33236 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 5824 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 600381 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 317102 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 1709909 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 23611 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 5579 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 415087 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 309089 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 33236 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 5824 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 600381 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 317102 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 1709909 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000678 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000358 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.014158 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.035188 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000451 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.011343 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.031596 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.017315 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.877330 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.798727 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.838147 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.791152 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.794483 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.792575 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.603935 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.520112 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.565268 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000678 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.000358 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.014158 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.280240 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000451 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.011343 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.207277 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.096536 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000678 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.000358 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.014158 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.280240 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000451 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.011343 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.207277 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.096536 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 78937.500000 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 79000 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72234.090522 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 74477.544265 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 94950 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73891.886931 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 77239.362375 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 74514.431730 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1601.238854 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2809.837945 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 2175.386615 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 664.470741 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5134.326389 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 2578.698885 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71504.585274 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 79028.080456 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 74697.875334 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 78937.500000 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 79000 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 72234.090522 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 71717.040003 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 94950 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 73891.886931 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 78853.475794 # average overall miss latency
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< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 78937.500000 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 79000 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 72234.090522 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 71717.040003 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 94950 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 73891.886931 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 78853.475794 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 74669.729837 # average overall miss latency
---
> system.l2c.overall_misses::cpu0.inst 6041 # number of overall misses
> system.l2c.overall_misses::cpu0.data 69866 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 6670 # number of overall misses
> system.l2c.overall_misses::cpu1.data 83240 # number of overall misses
> system.l2c.overall_misses::total 165847 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1149750 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.itb.walker 368000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.inst 435967250 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 468270999 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1231000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 485141500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 483349999 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 1875478498 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.data 9144593 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 12320478 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 21465071 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 441981 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3192363 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 3634344 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 4462150559 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 6003353008 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 10465503567 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 1149750 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 368000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 435967250 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 4930421558 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 1231000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 485141500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 6486703007 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 12340982065 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 1149750 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 368000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 435967250 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 4930421558 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 1231000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 485141500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 6486703007 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 12340982065 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.dtb.walker 22724 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.itb.walker 4443 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.inst 399717 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 172044 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.dtb.walker 33212 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.itb.walker 5802 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 614540 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 207939 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 1460421 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 583128 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 583128 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 6814 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 5163 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 11977 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 974 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 747 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 1721 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 111112 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 136270 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 247382 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 22724 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 4443 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 399717 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 283156 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 33212 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 5802 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 614540 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 344209 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 1707803 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 22724 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 4443 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 399717 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 283156 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 33212 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 5802 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 614540 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 344209 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 1707803 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000528 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000450 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.015113 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.036741 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000482 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.010854 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.030600 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.017409 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.835192 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.859190 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.845537 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.787474 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.788487 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.787914 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.571900 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.564152 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.567632 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000528 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.000450 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.015113 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.246740 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000482 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.010854 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.241830 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.097111 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000528 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.000450 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.015113 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.246740 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000482 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.010854 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.241830 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.097111 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 95812.500000 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 184000 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72168.059924 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 74081.790698 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76937.500000 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72734.857571 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 75962.596102 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 73765.132665 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1606.851696 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2777.384581 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 2119.588328 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 576.246415 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5419.971138 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 2680.194690 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70220.325108 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 78090.365233 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 74528.945372 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 95812.500000 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 184000 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 72168.059924 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 70569.684224 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 76937.500000 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 72734.857571 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 77927.715125 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 74411.849868 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 95812.500000 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 184000 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 72168.059924 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 70569.684224 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76937.500000 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 72734.857571 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 77927.715125 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 74411.849868 # average overall miss latency
627,628c615,616
< system.l2c.writebacks::writebacks 66093 # number of writebacks
< system.l2c.writebacks::total 66093 # number of writebacks
---
> system.l2c.writebacks::writebacks 66806 # number of writebacks
> system.l2c.writebacks::total 66806 # number of writebacks
630,631c618,619
< system.l2c.ReadReq_mshr_hits::cpu0.data 40 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits
---
> system.l2c.ReadReq_mshr_hits::cpu0.data 37 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits
633c621
< system.l2c.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits
---
> system.l2c.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
635,636c623,624
< system.l2c.demand_mshr_hits::cpu0.data 40 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
---
> system.l2c.demand_mshr_hits::cpu0.data 37 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
638c626
< system.l2c.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits
---
> system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
640,641c628,629
< system.l2c.overall_mshr_hits::cpu0.data 40 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
---
> system.l2c.overall_mshr_hits::cpu0.data 37 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
643,644c631,632
< system.l2c.overall_mshr_hits::total 79 # number of overall MSHR hits
< system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 16 # number of ReadReq MSHR misses
---
> system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits
> system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 12 # number of ReadReq MSHR misses
646,661c634,649
< system.l2c.ReadReq_mshr_misses::cpu0.inst 5872 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.data 6150 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 15 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.inst 6802 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.data 6390 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 25247 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 5271 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 4770 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 10041 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 769 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 576 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 1345 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 80429 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 59312 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 139741 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 16 # number of demand (read+write) MSHR misses
---
> system.l2c.ReadReq_mshr_misses::cpu0.inst 6036 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 6284 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 16 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.inst 6663 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.data 6337 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::total 25350 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 5691 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 4436 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 10127 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 767 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 589 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 1356 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 63545 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 76877 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 140422 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 12 # number of demand (read+write) MSHR misses
663,669c651,657
< system.l2c.demand_mshr_misses::cpu0.inst 5872 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 86579 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 15 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 6802 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 65702 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 164988 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 16 # number of overall MSHR misses
---
> system.l2c.demand_mshr_misses::cpu0.inst 6036 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 69829 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 16 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 6663 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 83214 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 165772 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 12 # number of overall MSHR misses
671,788c659,776
< system.l2c.overall_mshr_misses::cpu0.inst 5872 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 86579 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 6802 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 65702 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 164988 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1063000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 133500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 350406250 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 380974999 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1239250 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 417280250 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.data 414218499 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 1565315748 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 52852722 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 48053192 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 100905914 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7702266 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5777069 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 13479335 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4750287699 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3948467988 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 8698755687 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1063000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 133500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 350406250 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 5131262698 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1239250 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 417280250 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 4362686487 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 10264071435 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1063000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 133500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 350406250 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 5131262698 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1239250 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 417280250 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 4362686487 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 10264071435 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6908499 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 110354445727 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2586249 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 56865414992 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 167229355467 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1097294498 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16505203944 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 17602498442 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6908499 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 111451740225 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2586249 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 73370618936 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 184831853909 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000678 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000358 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014146 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.034960 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000451 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011329 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.031468 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.877330 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.798727 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.838147 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.791152 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.794483 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.792575 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.603935 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.520112 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.565268 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000678 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000358 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014146 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.280110 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000451 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011329 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.207195 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.096489 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000678 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000358 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014146 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.280110 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000451 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011329 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.207195 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.096489 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66437.500000 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59674.088896 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61947.154309 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 82616.666667 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61346.699500 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64822.926291 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 62000.069236 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10027.076836 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10074.044444 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10049.388905 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.950585 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10029.633681 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10021.810409 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59061.876923 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66571.148975 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 62249.130084 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66437.500000 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59674.088896 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 59266.827961 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82616.666667 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61346.699500 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66401.121534 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 62211.017983 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66437.500000 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59674.088896 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 59266.827961 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82616.666667 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61346.699500 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66401.121534 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 62211.017983 # average overall mshr miss latency
---
> system.l2c.overall_mshr_misses::cpu0.inst 6036 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 69829 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 16 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 6663 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 83214 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 165772 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1001750 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 343500 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 359682000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 387178249 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1034000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 400959000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 402487249 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 1552685748 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 57050142 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 44722851 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 101772993 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7680764 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5892086 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 13572850 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3668395937 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5048276480 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 8716672417 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1001750 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 343500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 359682000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 4055574186 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1034000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 400959000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 5450763729 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 10269358165 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1001750 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 343500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 359682000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 4055574186 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1034000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 400959000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 5450763729 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 10269358165 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6890749 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12335372988 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2843750 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154881314980 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 167226422467 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1073382998 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16528122341 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 17601505339 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6890749 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13408755986 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2843750 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171409437321 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 184827927806 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000528 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000450 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015101 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036526 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000482 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010842 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030475 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.017358 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.835192 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.859190 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.845537 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787474 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.788487 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.787914 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.571900 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564152 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.567632 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000528 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000450 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015101 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.246610 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000482 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010842 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.241754 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.097067 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000528 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000450 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015101 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.246610 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000482 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010842 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.241754 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.097067 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 83479.166667 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59589.463221 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61613.343253 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64625 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60176.947321 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63513.847089 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 61249.930888 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10024.625198 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10081.796889 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10049.668510 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10014.033898 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.541596 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10009.476401 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57729.104367 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65666.928730 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 62074.834549 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83479.166667 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59589.463221 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58078.651935 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64625 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60176.947321 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65502.964994 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 61948.689556 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83479.166667 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59589.463221 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58078.651935 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64625 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60176.947321 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65502.964994 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 61948.689556 # average overall mshr miss latency
809,840c797,828
< system.toL2Bus.throughput 58721934 # Throughput (bytes/s)
< system.toL2Bus.trans_dist::ReadReq 2742702 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 2742701 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 769189 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 769189 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 582434 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 35028 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 18623 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 53651 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 259025 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 259025 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831060 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2542800 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15169 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 56113 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1201524 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 3348368 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 16175 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 77084 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 8088293 # Packet count per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26573504 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 39205457 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 22316 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 94444 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38427456 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 43600612 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 23296 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132944 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size::total 148080029 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.data_through_bus 148080029 # Total data (bytes)
< system.toL2Bus.snoop_data_through_bus 4928740 # Total snoop data (bytes)
< system.toL2Bus.reqLayer0.occupancy 4918843977 # Layer occupancy (ticks)
---
> system.toL2Bus.throughput 58718575 # Throughput (bytes/s)
> system.toL2Bus.trans_dist::ReadReq 2740966 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 2740965 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 769183 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 769183 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 583128 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 35123 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 18657 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 53780 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 259272 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 259272 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 800244 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073141 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13760 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 56807 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1229764 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4820581 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 15635 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 75586 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 8085518 # Packet count per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25589824 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34686241 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17772 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 90896 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39333696 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 48239320 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 23208 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132848 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size::total 148113805 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.data_through_bus 148113805 # Total data (bytes)
> system.toL2Bus.snoop_data_through_bus 4885896 # Total snoop data (bytes)
> system.toL2Bus.reqLayer0.occupancy 4921313376 # Layer occupancy (ticks)
842c830
< system.toL2Bus.respLayer0.occupancy 1872939397 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 1803473389 # Layer occupancy (ticks)
844c832
< system.toL2Bus.respLayer1.occupancy 2324821689 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 1514355955 # Layer occupancy (ticks)
846c834
< system.toL2Bus.respLayer2.occupancy 9616940 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer2.occupancy 9338456 # Layer occupancy (ticks)
848c836
< system.toL2Bus.respLayer3.occupancy 32646700 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer3.occupancy 34226949 # Layer occupancy (ticks)
850c838
< system.toL2Bus.respLayer6.occupancy 2706859206 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer6.occupancy 2770248418 # Layer occupancy (ticks)
852c840
< system.toL2Bus.respLayer7.occupancy 2444231662 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer7.occupancy 3257977460 # Layer occupancy (ticks)
854c842
< system.toL2Bus.respLayer8.occupancy 10370957 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer8.occupancy 9851958 # Layer occupancy (ticks)
856c844
< system.toL2Bus.respLayer9.occupancy 44131664 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer9.occupancy 42643941 # Layer occupancy (ticks)
858,864c846,852
< system.iobus.throughput 47398263 # Throughput (bytes/s)
< system.iobus.trans_dist::ReadReq 16322928 # Transaction distribution
< system.iobus.trans_dist::ReadResp 16322928 # Transaction distribution
< system.iobus.trans_dist::WriteReq 8086 # Transaction distribution
< system.iobus.trans_dist::WriteResp 8086 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30960 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8852 # Packet count per connected master and slave (bytes)
---
> system.iobus.throughput 47398342 # Throughput (bytes/s)
> system.iobus.trans_dist::ReadReq 16322915 # Transaction distribution
> system.iobus.trans_dist::ReadResp 16322915 # Transaction distribution
> system.iobus.trans_dist::WriteReq 8083 # Transaction distribution
> system.iobus.trans_dist::WriteResp 8083 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30944 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8836 # Packet count per connected master and slave (bytes)
886c874
< system.iobus.pkt_count_system.bridge.master::total 2384396 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 2384364 # Packet count per connected master and slave (bytes)
889,891c877,879
< system.iobus.pkt_count::total 32662028 # Packet count per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40729 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17704 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 32661996 # Packet count per connected master and slave (bytes)
> system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40713 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17672 # Cumulative packet size per connected master and slave (bytes)
913c901
< system.iobus.tot_pkt_size_system.bridge.master::total 2392725 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.tot_pkt_size_system.bridge.master::total 2392677 # Cumulative packet size per connected master and slave (bytes)
916,918c904,906
< system.iobus.tot_pkt_size::total 123503253 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.data_through_bus 123503253 # Total data (bytes)
< system.iobus.reqLayer0.occupancy 21724000 # Layer occupancy (ticks)
---
> system.iobus.tot_pkt_size::total 123503205 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.data_through_bus 123503205 # Total data (bytes)
> system.iobus.reqLayer0.occupancy 21713000 # Layer occupancy (ticks)
920c908
< system.iobus.reqLayer1.occupancy 4432000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 4424000 # Layer occupancy (ticks)
966c954
< system.iobus.respLayer0.occupancy 2376310000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 2376281000 # Layer occupancy (ticks)
968,974c956,962
< system.iobus.respLayer1.occupancy 37739478366 # Layer occupancy (ticks)
< system.iobus.respLayer1.utilization 1.4 # Layer utilization (%)
< system.cpu0.branchPred.lookups 6715650 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 5214611 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 297509 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 4164563 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 3259277 # Number of BTB hits
---
> system.iobus.respLayer1.occupancy 38174483356 # Layer occupancy (ticks)
> system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
> system.cpu0.branchPred.lookups 6117114 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 4670626 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 296157 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 3842728 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 2949969 # Number of BTB hits
976,978c964,966
< system.cpu0.branchPred.BTBHitPct 78.262161 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 722080 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 28659 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 76.767572 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 683314 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 28361 # Number of incorrect RAS predictions.
1002,1005c990,993
< system.cpu0.dtb.read_hits 30314049 # DTB read hits
< system.cpu0.dtb.read_misses 28675 # DTB read misses
< system.cpu0.dtb.write_hits 5612279 # DTB write hits
< system.cpu0.dtb.write_misses 4120 # DTB write misses
---
> system.cpu0.dtb.read_hits 8969403 # DTB read hits
> system.cpu0.dtb.read_misses 29343 # DTB read misses
> system.cpu0.dtb.write_hits 5210557 # DTB write hits
> system.cpu0.dtb.write_misses 5731 # DTB write misses
1010,1012c998,1000
< system.cpu0.dtb.flush_entries 1934 # Number of entries that have been flushed from TLB
< system.cpu0.dtb.align_faults 1024 # Number of TLB faults due to alignment restrictions
< system.cpu0.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.flush_entries 1733 # Number of entries that have been flushed from TLB
> system.cpu0.dtb.align_faults 1050 # Number of TLB faults due to alignment restrictions
> system.cpu0.dtb.prefetch_faults 278 # Number of TLB faults due to prefetch
1014,1016c1002,1004
< system.cpu0.dtb.perms_faults 686 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 30342724 # DTB read accesses
< system.cpu0.dtb.write_accesses 5616399 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 596 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 8998746 # DTB read accesses
> system.cpu0.dtb.write_accesses 5216288 # DTB write accesses
1018,1020c1006,1008
< system.cpu0.dtb.hits 35926328 # DTB hits
< system.cpu0.dtb.misses 32795 # DTB misses
< system.cpu0.dtb.accesses 35959123 # DTB accesses
---
> system.cpu0.dtb.hits 14179960 # DTB hits
> system.cpu0.dtb.misses 35074 # DTB misses
> system.cpu0.dtb.accesses 14215034 # DTB accesses
1042,1043c1030,1031
< system.cpu0.itb.inst_hits 4601822 # ITB inst hits
< system.cpu0.itb.inst_misses 5333 # ITB inst misses
---
> system.cpu0.itb.inst_hits 4277605 # ITB inst hits
> system.cpu0.itb.inst_misses 5145 # ITB inst misses
1052c1040
< system.cpu0.itb.flush_entries 1359 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_entries 1215 # Number of entries that have been flushed from TLB
1056c1044
< system.cpu0.itb.perms_faults 1531 # Number of TLB faults due to permissions restrictions
---
> system.cpu0.itb.perms_faults 1426 # Number of TLB faults due to permissions restrictions
1059,1063c1047,1051
< system.cpu0.itb.inst_accesses 4607155 # ITB inst accesses
< system.cpu0.itb.hits 4601822 # DTB hits
< system.cpu0.itb.misses 5333 # DTB misses
< system.cpu0.itb.accesses 4607155 # DTB accesses
< system.cpu0.numCycles 298758505 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 4282750 # ITB inst accesses
> system.cpu0.itb.hits 4277605 # DTB hits
> system.cpu0.itb.misses 5145 # DTB misses
> system.cpu0.itb.accesses 4282750 # DTB accesses
> system.cpu0.numCycles 70248238 # number of cpu cycles simulated
1066,1083c1054,1071
< system.cpu0.fetch.icacheStallCycles 12556555 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 35349888 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 6715650 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 3981357 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 8343175 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 1485021 # Number of cycles fetch has spent squashing
< system.cpu0.fetch.TlbCycles 73668 # Number of cycles fetch has spent waiting for tlb
< system.cpu0.fetch.BlockedCycles 62934939 # Number of cycles fetch has spent blocked
< system.cpu0.fetch.MiscStallCycles 5979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu0.fetch.PendingTrapStallCycles 43768 # Number of stall cycles due to pending traps
< system.cpu0.fetch.PendingQuiesceStallCycles 1358657 # Number of stall cycles due to pending quiesce instructions
< system.cpu0.fetch.IcacheWaitRetryStallCycles 326 # Number of stall cycles due to full MSHR
< system.cpu0.fetch.CacheLines 4600051 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 159705 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.ItlbSquashes 2319 # Number of outstanding ITLB misses that were squashed
< system.cpu0.fetch.rateDist::samples 86381436 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 0.526874 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 1.794731 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.icacheStallCycles 11931842 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 32451975 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 6117114 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 3633283 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 7612739 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 1460869 # Number of cycles fetch has spent squashing
> system.cpu0.fetch.TlbCycles 60951 # Number of cycles fetch has spent waiting for tlb
> system.cpu0.fetch.BlockedCycles 20309232 # Number of cycles fetch has spent blocked
> system.cpu0.fetch.MiscStallCycles 6063 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu0.fetch.PendingTrapStallCycles 46682 # Number of stall cycles due to pending traps
> system.cpu0.fetch.PendingQuiesceStallCycles 1377400 # Number of stall cycles due to pending quiesce instructions
> system.cpu0.fetch.IcacheWaitRetryStallCycles 299 # Number of stall cycles due to full MSHR
> system.cpu0.fetch.CacheLines 4276074 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 156796 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.ItlbSquashes 2089 # Number of outstanding ITLB misses that were squashed
> system.cpu0.fetch.rateDist::samples 42393450 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 0.988978 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 2.370199 # Number of instructions fetched each cycle (Total)
1085,1093c1073,1081
< system.cpu0.fetch.rateDist::0 78045507 90.35% 90.35% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 675063 0.78% 91.13% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 847046 0.98% 92.11% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 783211 0.91% 93.02% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::4 1013921 1.17% 94.19% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::5 572462 0.66% 94.86% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::6 659407 0.76% 95.62% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::7 359642 0.42% 96.03% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::8 3425177 3.97% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 34788183 82.06% 82.06% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 572054 1.35% 83.41% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 825907 1.95% 85.36% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 686377 1.62% 86.98% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::4 779180 1.84% 88.81% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::5 565083 1.33% 90.15% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::6 677221 1.60% 91.75% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::7 357838 0.84% 92.59% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::8 3141607 7.41% 100.00% # Number of instructions fetched each cycle (Total)
1097,1142c1085,1130
< system.cpu0.fetch.rateDist::total 86381436 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.022479 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 0.118323 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 13622847 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 63604727 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 7412124 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 742617 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 999121 # Number of cycles decode is squashing
< system.cpu0.decode.BranchResolved 974392 # Number of times decode resolved a branch
< system.cpu0.decode.BranchMispred 66422 # Number of times decode detected a branch misprediction
< system.cpu0.decode.DecodedInsts 44125799 # Number of instructions handled by decode
< system.cpu0.decode.SquashedInsts 218867 # Number of squashed instructions handled by decode
< system.cpu0.rename.SquashCycles 999121 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 14363042 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 26099881 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 33731509 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 7356267 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 3831616 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 43013829 # Number of instructions processed by rename
< system.cpu0.rename.ROBFullEvents 321 # Number of times rename has blocked due to ROB full
< system.cpu0.rename.IQFullEvents 629927 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LSQFullEvents 2476084 # Number of times rename has blocked due to LSQ full
< system.cpu0.rename.FullRegisterEvents 94 # Number of times there has been no free registers
< system.cpu0.rename.RenamedOperands 43352703 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 198103413 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 178854732 # Number of integer rename lookups
< system.cpu0.rename.fp_rename_lookups 5396 # Number of floating rename lookups
< system.cpu0.rename.CommittedMaps 34867311 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 8485392 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 643580 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 598183 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 7434614 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 8769305 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 6206849 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 1218439 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 1296110 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 40716219 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 1133567 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 61584494 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 78672 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 6465857 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 13399979 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 300001 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 86381436 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 0.712937 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.420531 # Number of insts issued each cycle
---
> system.cpu0.fetch.rateDist::total 42393450 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.087079 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 0.461961 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 12487890 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 21493629 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 6874468 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 552722 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 984741 # Number of cycles decode is squashing
> system.cpu0.decode.BranchResolved 950951 # Number of times decode resolved a branch
> system.cpu0.decode.BranchMispred 64626 # Number of times decode detected a branch misprediction
> system.cpu0.decode.DecodedInsts 40558878 # Number of instructions handled by decode
> system.cpu0.decode.SquashedInsts 212020 # Number of squashed instructions handled by decode
> system.cpu0.rename.SquashCycles 984741 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 13064503 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 5883311 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 13498743 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 6804692 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 2157460 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 39446559 # Number of instructions processed by rename
> system.cpu0.rename.ROBFullEvents 311 # Number of times rename has blocked due to ROB full
> system.cpu0.rename.IQFullEvents 442642 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LSQFullEvents 1180293 # Number of times rename has blocked due to LSQ full
> system.cpu0.rename.FullRegisterEvents 145 # Number of times there has been no free registers
> system.cpu0.rename.RenamedOperands 39856275 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 180582545 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 163877057 # Number of integer rename lookups
> system.cpu0.rename.fp_rename_lookups 4135 # Number of floating rename lookups
> system.cpu0.rename.CommittedMaps 31488132 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 8368142 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 460013 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 416638 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 5509006 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 7758217 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 5771757 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 1123661 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 1193308 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 37348678 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 906063 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 37718806 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 82800 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 6312476 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 13233696 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 257258 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 42393450 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 0.889732 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.506737 # Number of insts issued each cycle
1144,1152c1132,1140
< system.cpu0.iq.issued_per_cycle::0 63313818 73.30% 73.30% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 8088215 9.36% 82.66% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 3310781 3.83% 86.49% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 2721682 3.15% 89.64% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 7122842 8.25% 97.89% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 1038791 1.20% 99.09% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::6 532976 0.62% 99.71% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::7 192156 0.22% 99.93% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::8 60175 0.07% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 27027469 63.75% 63.75% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 5904750 13.93% 77.68% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 3167008 7.47% 85.15% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 2470651 5.83% 90.98% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 2117188 4.99% 95.97% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 941206 2.22% 98.20% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::6 520081 1.23% 99.42% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::7 187957 0.44% 99.87% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::8 57140 0.13% 100.00% # Number of insts issued each cycle
1156c1144
< system.cpu0.iq.issued_per_cycle::total 86381436 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 42393450 # Number of insts issued each cycle
1158,1188c1146,1176
< system.cpu0.iq.fu_full::IntAlu 26298 0.46% 0.46% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 452 0.01% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 5416194 95.59% 96.06% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 223026 3.94% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 26875 2.51% 2.51% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 458 0.04% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.55% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 836202 77.98% 80.53% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 208765 19.47% 100.00% # attempts to use FU when none available
1191,1222c1179,1210
< system.cpu0.iq.FU_type_0::No_OpClass 15923 0.03% 0.03% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntAlu 24790294 40.25% 40.28% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 50109 0.08% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMisc 806 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 40.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemRead 30788025 49.99% 90.36% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 5939307 9.64% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::No_OpClass 14551 0.04% 0.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntAlu 22694630 60.17% 60.21% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 47979 0.13% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShiftAcc 10 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.33% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.34% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 60.34% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemRead 9430195 25.00% 85.34% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 5530734 14.66% 100.00% # Type of FU issued
1225,1237c1213,1225
< system.cpu0.iq.FU_type_0::total 61584494 # Type of FU issued
< system.cpu0.iq.rate 0.206135 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 5665970 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.092003 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 215315704 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 48322789 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 38367249 # Number of integer instruction queue wakeup accesses
< system.cpu0.iq.fp_inst_queue_reads 11842 # Number of floating instruction queue reads
< system.cpu0.iq.fp_inst_queue_writes 6226 # Number of floating instruction queue writes
< system.cpu0.iq.fp_inst_queue_wakeup_accesses 5089 # Number of floating instruction queue wakeup accesses
< system.cpu0.iq.int_alu_accesses 67228191 # Number of integer alu accesses
< system.cpu0.iq.fp_alu_accesses 6350 # Number of floating point alu accesses
< system.cpu0.iew.lsq.thread0.forwLoads 325894 # Number of loads that had data forwarded from stores
---
> system.cpu0.iq.FU_type_0::total 37718806 # Type of FU issued
> system.cpu0.iq.rate 0.536936 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 1072300 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.028429 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 119012569 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 44575137 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 34852276 # Number of integer instruction queue wakeup accesses
> system.cpu0.iq.fp_inst_queue_reads 8350 # Number of floating instruction queue reads
> system.cpu0.iq.fp_inst_queue_writes 4654 # Number of floating instruction queue writes
> system.cpu0.iq.fp_inst_queue_wakeup_accesses 3869 # Number of floating instruction queue wakeup accesses
> system.cpu0.iq.int_alu_accesses 38772197 # Number of integer alu accesses
> system.cpu0.iq.fp_alu_accesses 4358 # Number of floating point alu accesses
> system.cpu0.iew.lsq.thread0.forwLoads 316382 # Number of loads that had data forwarded from stores
1239,1242c1227,1230
< system.cpu0.iew.lsq.thread0.squashedLoads 1367932 # Number of loads squashed
< system.cpu0.iew.lsq.thread0.ignoredResponses 2587 # Number of memory responses ignored because the instruction is squashed
< system.cpu0.iew.lsq.thread0.memOrderViolation 13911 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 563678 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 1375838 # Number of loads squashed
> system.cpu0.iew.lsq.thread0.ignoredResponses 2694 # Number of memory responses ignored because the instruction is squashed
> system.cpu0.iew.lsq.thread0.memOrderViolation 13105 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 538991 # Number of stores squashed
1245,1246c1233,1234
< system.cpu0.iew.lsq.thread0.rescheduledLoads 22510150 # Number of loads that were rescheduled
< system.cpu0.iew.lsq.thread0.cacheBlocked 5899 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.rescheduledLoads 2149907 # Number of loads that were rescheduled
> system.cpu0.iew.lsq.thread0.cacheBlocked 5937 # Number of times an access to memory failed due to the cache being blocked
1248,1264c1236,1252
< system.cpu0.iew.iewSquashCycles 999121 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 20412775 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 272757 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 41952562 # Number of instructions dispatched to IQ
< system.cpu0.iew.iewDispSquashedInsts 83343 # Number of squashed instructions skipped by dispatch
< system.cpu0.iew.iewDispLoadInsts 8769305 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 6206849 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 796686 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 50755 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 3694 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 13911 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 151015 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 116203 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 267218 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 61206576 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 30649831 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 377918 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewSquashCycles 984741 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 4273547 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 99764 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 38372810 # Number of instructions dispatched to IQ
> system.cpu0.iew.iewDispSquashedInsts 83727 # Number of squashed instructions skipped by dispatch
> system.cpu0.iew.iewDispLoadInsts 7758217 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 5771757 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 578717 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 40350 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 3282 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 13105 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 151036 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 117828 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 268864 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 37337135 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 9286340 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 381671 # Number of squashed instructions skipped in execute
1266,1274c1254,1262
< system.cpu0.iew.exec_nop 102776 # number of nop insts executed
< system.cpu0.iew.exec_refs 36543183 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 5550332 # Number of branches executed
< system.cpu0.iew.exec_stores 5893352 # Number of stores executed
< system.cpu0.iew.exec_rate 0.204870 # Inst execution rate
< system.cpu0.iew.wb_sent 61019070 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 38372338 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 20674113 # num instructions producing a value
< system.cpu0.iew.wb_consumers 38142518 # num instructions consuming a value
---
> system.cpu0.iew.exec_nop 118069 # number of nop insts executed
> system.cpu0.iew.exec_refs 14769450 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 4962843 # Number of branches executed
> system.cpu0.iew.exec_stores 5483110 # Number of stores executed
> system.cpu0.iew.exec_rate 0.531503 # Inst execution rate
> system.cpu0.iew.wb_sent 37142523 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 34856145 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 18592748 # num instructions producing a value
> system.cpu0.iew.wb_consumers 35683758 # num instructions consuming a value
1276,1277c1264,1265
< system.cpu0.iew.wb_rate 0.128439 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.542023 # average fanout of values written-back
---
> system.cpu0.iew.wb_rate 0.496185 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.521042 # average fanout of values written-back
1279,1284c1267,1272
< system.cpu0.commit.commitSquashedInsts 6195680 # The number of squashed insts skipped by commit
< system.cpu0.commit.commitNonSpecStalls 833566 # The number of times commit has been forced to stall to communicate backwards
< system.cpu0.commit.branchMispredicts 232261 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 85382315 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 0.412432 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 1.299663 # Number of insts commited each cycle
---
> system.cpu0.commit.commitSquashedInsts 6125993 # The number of squashed insts skipped by commit
> system.cpu0.commit.commitNonSpecStalls 648805 # The number of times commit has been forced to stall to communicate backwards
> system.cpu0.commit.branchMispredicts 232656 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 41408709 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 0.767702 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 1.726975 # Number of insts commited each cycle
1286,1294c1274,1282
< system.cpu0.commit.committed_per_cycle::0 71262923 83.46% 83.46% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 7740236 9.07% 92.53% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 2004904 2.35% 94.88% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 1114217 1.30% 96.18% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 806577 0.94% 97.13% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 503262 0.59% 97.72% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 497454 0.58% 98.30% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 227564 0.27% 98.57% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 1225178 1.43% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 29445863 71.11% 71.11% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 5939620 14.34% 85.45% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 1940870 4.69% 90.14% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 1013361 2.45% 92.59% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 759448 1.83% 94.42% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 515426 1.24% 95.67% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 408347 0.99% 96.65% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 223076 0.54% 97.19% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 1162698 2.81% 100.00% # Number of insts commited each cycle
1298,1300c1286,1288
< system.cpu0.commit.committed_per_cycle::total 85382315 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 26835114 # Number of instructions committed
< system.cpu0.commit.committedOps 35214409 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 41408709 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 24071577 # Number of instructions committed
> system.cpu0.commit.committedOps 31789563 # Number of ops (including micro ops) committed
1302,1309c1290,1332
< system.cpu0.commit.refs 13044544 # Number of memory references committed
< system.cpu0.commit.loads 7401373 # Number of loads committed
< system.cpu0.commit.membars 236456 # Number of memory barriers committed
< system.cpu0.commit.branches 4918099 # Number of branches committed
< system.cpu0.commit.fp_insts 5062 # Number of committed floating point instructions.
< system.cpu0.commit.int_insts 31243705 # Number of committed integer instructions.
< system.cpu0.commit.function_calls 531450 # Number of function calls committed.
< system.cpu0.commit.bw_lim_events 1225178 # number cycles where commit BW limit reached
---
> system.cpu0.commit.refs 11615145 # Number of memory references committed
> system.cpu0.commit.loads 6382379 # Number of loads committed
> system.cpu0.commit.membars 231812 # Number of memory barriers committed
> system.cpu0.commit.branches 4351457 # Number of branches committed
> system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
> system.cpu0.commit.int_insts 28135168 # Number of committed integer instructions.
> system.cpu0.commit.function_calls 498959 # Number of function calls committed.
> system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntAlu 20133954 63.34% 63.34% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntMult 39784 0.13% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntDiv 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatMult 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMult 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShift 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMisc 680 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemRead 6382379 20.08% 83.54% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemWrite 5232766 16.46% 100.00% # Class of committed instruction
> system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
> system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
> system.cpu0.commit.op_class_0::total 31789563 # Class of committed instruction
> system.cpu0.commit.bw_lim_events 1162698 # number cycles where commit BW limit reached
1311,1337c1334,1360
< system.cpu0.rob.rob_reads 124649951 # The number of ROB reads
< system.cpu0.rob.rob_writes 83821170 # The number of ROB writes
< system.cpu0.timesIdled 1018994 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 212377069 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.quiesceCycles 4911896145 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.committedInsts 26765511 # Number of Instructions Simulated
< system.cpu0.committedOps 35144806 # Number of Ops (including micro ops) Simulated
< system.cpu0.committedInsts_total 26765511 # Number of Instructions Simulated
< system.cpu0.cpi 11.162070 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 11.162070 # CPI: Total CPI of All Threads
< system.cpu0.ipc 0.089589 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 0.089589 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 273626518 # number of integer regfile reads
< system.cpu0.int_regfile_writes 37917674 # number of integer regfile writes
< system.cpu0.fp_regfile_reads 4695 # number of floating regfile reads
< system.cpu0.fp_regfile_writes 986 # number of floating regfile writes
< system.cpu0.misc_regfile_reads 148789996 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 678362 # number of misc regfile writes
< system.cpu0.icache.tags.replacements 415188 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.568306 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 4152259 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 415700 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 9.988595 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 7103550250 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.568306 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999157 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.999157 # Average percentage of cache occupancy
---
> system.cpu0.rob.rob_reads 77292791 # The number of ROB reads
> system.cpu0.rob.rob_writes 76817595 # The number of ROB writes
> system.cpu0.timesIdled 365665 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 27854788 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.quiesceCycles 5140997105 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.committedInsts 23990835 # Number of Instructions Simulated
> system.cpu0.committedOps 31708821 # Number of Ops (including micro ops) Simulated
> system.cpu0.committedInsts_total 23990835 # Number of Instructions Simulated
> system.cpu0.cpi 2.928128 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 2.928128 # CPI: Total CPI of All Threads
> system.cpu0.ipc 0.341515 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 0.341515 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 174285855 # number of integer regfile reads
> system.cpu0.int_regfile_writes 34604955 # number of integer regfile writes
> system.cpu0.fp_regfile_reads 3294 # number of floating regfile reads
> system.cpu0.fp_regfile_writes 912 # number of floating regfile writes
> system.cpu0.misc_regfile_reads 79299010 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 500883 # number of misc regfile writes
> system.cpu0.icache.tags.replacements 399739 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.543627 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 3844274 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 400251 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 9.604658 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 7097393250 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.543627 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999109 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.999109 # Average percentage of cache occupancy
1339c1362,1365
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
1341,1379c1367,1405
< system.cpu0.icache.tags.tag_accesses 5015647 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 5015647 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 4152259 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 4152259 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 4152259 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 4152259 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 4152259 # number of overall hits
< system.cpu0.icache.overall_hits::total 4152259 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 447663 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 447663 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 447663 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 447663 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 447663 # number of overall misses
< system.cpu0.icache.overall_misses::total 447663 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6158685000 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 6158685000 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 6158685000 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 6158685000 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 6158685000 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 6158685000 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 4599922 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 4599922 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 4599922 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 4599922 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 4599922 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 4599922 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097320 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.097320 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097320 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.097320 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097320 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.097320 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13757.413501 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 13757.413501 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13757.413501 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 13757.413501 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13757.413501 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 13757.413501 # average overall miss latency
< system.cpu0.icache.blocked_cycles::no_mshrs 4464 # number of cycles access was blocked
---
> system.cpu0.icache.tags.tag_accesses 4676219 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 4676219 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 3844274 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 3844274 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 3844274 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 3844274 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 3844274 # number of overall hits
> system.cpu0.icache.overall_hits::total 3844274 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 431668 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 431668 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 431668 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 431668 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 431668 # number of overall misses
> system.cpu0.icache.overall_misses::total 431668 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5966691765 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 5966691765 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 5966691765 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 5966691765 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 5966691765 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 5966691765 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 4275942 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 4275942 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 4275942 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 4275942 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 4275942 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 4275942 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100953 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.100953 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100953 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.100953 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100953 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.100953 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13822.409271 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 13822.409271 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13822.409271 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 13822.409271 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13822.409271 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 13822.409271 # average overall miss latency
> system.cpu0.icache.blocked_cycles::no_mshrs 4149 # number of cycles access was blocked
1381c1407
< system.cpu0.icache.blocked::no_mshrs 167 # number of cycles access was blocked
---
> system.cpu0.icache.blocked::no_mshrs 172 # number of cycles access was blocked
1383c1409
< system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.730539 # average number of cycles each access was blocked
---
> system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.122093 # average number of cycles each access was blocked
1387,1420c1413,1446
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31938 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 31938 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 31938 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 31938 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 31938 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 31938 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 415725 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 415725 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 415725 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 415725 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 415725 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 415725 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5022987594 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 5022987594 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5022987594 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 5022987594 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5022987594 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 5022987594 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9487250 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9487250 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9487250 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::total 9487250 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090377 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090377 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090377 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.090377 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090377 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.090377 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12082.476623 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12082.476623 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12082.476623 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 12082.476623 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12082.476623 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 12082.476623 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31390 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 31390 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 31390 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 31390 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 31390 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 31390 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400278 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 400278 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 400278 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 400278 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 400278 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 400278 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4859637603 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 4859637603 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4859637603 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 4859637603 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4859637603 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 4859637603 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9490000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9490000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9490000 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::total 9490000 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093612 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093612 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093612 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.093612 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093612 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.093612 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12140.656251 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12140.656251 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12140.656251 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 12140.656251 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12140.656251 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 12140.656251 # average overall mshr miss latency
1426,1517c1452,1545
< system.cpu0.dcache.tags.replacements 298882 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 483.456705 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 10027143 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 299266 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 33.505787 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 44230250 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 483.456705 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.944251 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.944251 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 384 # Occupied blocks per task id
< system.cpu0.dcache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id
< system.cpu0.dcache.tags.tag_accesses 48541082 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 48541082 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 6144970 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 6144970 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 3563655 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 3563655 # number of WriteReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 144672 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 144672 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 142233 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 142233 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 9708625 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 9708625 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 9708625 # number of overall hits
< system.cpu0.dcache.overall_hits::total 9708625 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 393929 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 393929 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1644577 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1644577 # number of WriteReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9244 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 9244 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7866 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 7866 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 2038506 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 2038506 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 2038506 # number of overall misses
< system.cpu0.dcache.overall_misses::total 2038506 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5542234631 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 5542234631 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 82471404032 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 82471404032 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 94602484 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 94602484 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50293768 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 50293768 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 88013638663 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 88013638663 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 88013638663 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 88013638663 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 6538899 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 6538899 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 5208232 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 5208232 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 153916 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 153916 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 150099 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 150099 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 11747131 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 11747131 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 11747131 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 11747131 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.060244 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.060244 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.315765 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.315765 # miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060059 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.060059 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052405 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052405 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.173532 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.173532 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.173532 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.173532 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14069.120656 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 14069.120656 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50147.487185 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 50147.487185 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10233.933795 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10233.933795 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6393.817442 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6393.817442 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43175.560270 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 43175.560270 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43175.560270 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 43175.560270 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 10878 # number of cycles access was blocked
< system.cpu0.dcache.blocked_cycles::no_targets 5936 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_mshrs 678 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_targets 116 # number of cycles access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.044248 # average number of cycles each access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_targets 51.172414 # average number of cycles each access was blocked
---
> system.cpu0.dcache.tags.replacements 275002 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 479.873805 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 9429051 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 275514 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 34.223491 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 43985250 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.873805 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937254 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.937254 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
> system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu0.dcache.tags.tag_accesses 45805638 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 45805638 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 5875796 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 5875796 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 3229179 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 3229179 # number of WriteReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139566 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 139566 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137212 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 137212 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 9104975 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 9104975 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 9104975 # number of overall hits
> system.cpu0.dcache.overall_hits::total 9104975 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 392540 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 392540 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1582550 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1582550 # number of WriteReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8878 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 8878 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7747 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 7747 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 1975090 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 1975090 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 1975090 # number of overall misses
> system.cpu0.dcache.overall_misses::total 1975090 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5503316358 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 5503316358 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 80403947306 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 80403947306 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91149731 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 91149731 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 49845761 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 49845761 # number of StoreCondReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 85907263664 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 85907263664 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 85907263664 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 85907263664 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 6268336 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 6268336 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 4811729 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 4811729 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148444 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 148444 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144959 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 144959 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 11080065 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 11080065 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 11080065 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 11080065 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062623 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.062623 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.328894 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.328894 # miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059807 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059807 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053443 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053443 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178256 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.178256 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178256 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.178256 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14019.759408 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 14019.759408 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50806.576289 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 50806.576289 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10266.921717 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10266.921717 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6434.201756 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6434.201756 # average StoreCondReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43495.366623 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 43495.366623 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43495.366623 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 43495.366623 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 9513 # number of cycles access was blocked
> system.cpu0.dcache.blocked_cycles::no_targets 7748 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_mshrs 587 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_targets 136 # number of cycles access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.206133 # average number of cycles each access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_targets 56.970588 # average number of cycles each access was blocked
1520,1551c1548,1579
< system.cpu0.dcache.writebacks::writebacks 278268 # number of writebacks
< system.cpu0.dcache.writebacks::total 278268 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 201648 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 201648 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1493557 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 1493557 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 632 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 632 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 1695205 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 1695205 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 1695205 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 1695205 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 192281 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 192281 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 151020 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 151020 # number of WriteReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8612 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8612 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7866 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 7866 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 343301 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 343301 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 343301 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 343301 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2438332267 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2438332267 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6681240000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6681240000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70543016 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70543016 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34562232 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34562232 # number of StoreCondReq MSHR miss cycles
---
> system.cpu0.dcache.writebacks::writebacks 255347 # number of writebacks
> system.cpu0.dcache.writebacks::total 255347 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203411 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 203411 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451593 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 1451593 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 468 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 468 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 1655004 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 1655004 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 1655004 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 1655004 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189129 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 189129 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130957 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 130957 # number of WriteReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8410 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8410 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7747 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 7747 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 320086 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 320086 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 320086 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 320086 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2397985131 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2397985131 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5338215866 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5338215866 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69513767 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69513767 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34349239 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34349239 # number of StoreCondReq MSHR miss cycles
1554,1583c1582,1611
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9119572267 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 9119572267 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9119572267 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 9119572267 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 120538982283 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 120538982283 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1232045382 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1232045382 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 121771027665 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 121771027665 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029406 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029406 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028996 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028996 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055953 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055953 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052405 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052405 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029224 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.029224 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029224 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.029224 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12681.087923 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12681.087923 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44240.762813 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44240.762813 # average WriteReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8191.246633 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8191.246633 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4393.876430 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4393.876430 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7736200997 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 7736200997 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7736200997 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 7736200997 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13434640527 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13434640527 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1206086382 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1206086382 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14640726909 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14640726909 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030172 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030172 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027216 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027216 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056654 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056654 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053443 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053443 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028888 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.028888 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028888 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.028888 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12679.098028 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12679.098028 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40763.119696 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40763.119696 # average WriteReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8265.608442 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8265.608442 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4433.876210 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4433.876210 # average StoreCondReq mshr miss latency
1586,1589c1614,1617
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26564.362664 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26564.362664 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26564.362664 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26564.362664 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24169.132661 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24169.132661 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24169.132661 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24169.132661 # average overall mshr miss latency
1597,1601c1625,1629
< system.cpu1.branchPred.lookups 8689698 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 7082612 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 415349 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 5570453 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 4730059 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 9293378 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 7631598 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 415998 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 5889507 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 5046361 # Number of BTB hits
1603,1605c1631,1633
< system.cpu1.branchPred.BTBHitPct 84.913363 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 759549 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 43595 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 85.683929 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 797302 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 43622 # Number of incorrect RAS predictions.
1629,1632c1657,1660
< system.cpu1.dtb.read_hits 21626734 # DTB read hits
< system.cpu1.dtb.read_misses 38691 # DTB read misses
< system.cpu1.dtb.write_hits 6575784 # DTB write hits
< system.cpu1.dtb.write_misses 12298 # DTB write misses
---
> system.cpu1.dtb.read_hits 42971422 # DTB read hits
> system.cpu1.dtb.read_misses 37905 # DTB read misses
> system.cpu1.dtb.write_hits 6976449 # DTB write hits
> system.cpu1.dtb.write_misses 10883 # DTB write misses
1637,1639c1665,1667
< system.cpu1.dtb.flush_entries 1712 # Number of entries that have been flushed from TLB
< system.cpu1.dtb.align_faults 3023 # Number of TLB faults due to alignment restrictions
< system.cpu1.dtb.prefetch_faults 279 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.flush_entries 1918 # Number of entries that have been flushed from TLB
> system.cpu1.dtb.align_faults 2893 # Number of TLB faults due to alignment restrictions
> system.cpu1.dtb.prefetch_faults 296 # Number of TLB faults due to prefetch
1641,1643c1669,1671
< system.cpu1.dtb.perms_faults 600 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 21665425 # DTB read accesses
< system.cpu1.dtb.write_accesses 6588082 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 686 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 43009327 # DTB read accesses
> system.cpu1.dtb.write_accesses 6987332 # DTB write accesses
1645,1647c1673,1675
< system.cpu1.dtb.hits 28202518 # DTB hits
< system.cpu1.dtb.misses 50989 # DTB misses
< system.cpu1.dtb.accesses 28253507 # DTB accesses
---
> system.cpu1.dtb.hits 49947871 # DTB hits
> system.cpu1.dtb.misses 48788 # DTB misses
> system.cpu1.dtb.accesses 49996659 # DTB accesses
1669,1670c1697,1698
< system.cpu1.itb.inst_hits 7394895 # ITB inst hits
< system.cpu1.itb.inst_misses 5860 # ITB inst misses
---
> system.cpu1.itb.inst_hits 7719787 # ITB inst hits
> system.cpu1.itb.inst_misses 5634 # ITB inst misses
1679c1707
< system.cpu1.itb.flush_entries 1207 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_entries 1369 # Number of entries that have been flushed from TLB
1683c1711
< system.cpu1.itb.perms_faults 1503 # Number of TLB faults due to permissions restrictions
---
> system.cpu1.itb.perms_faults 1538 # Number of TLB faults due to permissions restrictions
1686,1690c1714,1718
< system.cpu1.itb.inst_accesses 7400755 # ITB inst accesses
< system.cpu1.itb.hits 7394895 # DTB hits
< system.cpu1.itb.misses 5860 # DTB misses
< system.cpu1.itb.accesses 7400755 # DTB accesses
< system.cpu1.numCycles 185247782 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 7725421 # ITB inst accesses
> system.cpu1.itb.hits 7719787 # DTB hits
> system.cpu1.itb.misses 5634 # DTB misses
> system.cpu1.itb.accesses 7725421 # DTB accesses
> system.cpu1.numCycles 413693823 # number of cpu cycles simulated
1693,1710c1721,1738
< system.cpu1.fetch.icacheStallCycles 18767441 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 58413381 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 8689698 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 5489608 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 12630025 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 3326163 # Number of cycles fetch has spent squashing
< system.cpu1.fetch.TlbCycles 70879 # Number of cycles fetch has spent waiting for tlb
< system.cpu1.fetch.BlockedCycles 38401480 # Number of cycles fetch has spent blocked
< system.cpu1.fetch.MiscStallCycles 5864 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu1.fetch.PendingTrapStallCycles 46813 # Number of stall cycles due to pending traps
< system.cpu1.fetch.PendingQuiesceStallCycles 1518730 # Number of stall cycles due to pending quiesce instructions
< system.cpu1.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR
< system.cpu1.fetch.CacheLines 7393189 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 549179 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.ItlbSquashes 3073 # Number of outstanding ITLB misses that were squashed
< system.cpu1.fetch.rateDist::samples 73717325 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 0.969397 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 2.351920 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.icacheStallCycles 19372544 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 61318271 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 9293378 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 5843663 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 13362487 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 3346253 # Number of cycles fetch has spent squashing
> system.cpu1.fetch.TlbCycles 69736 # Number of cycles fetch has spent waiting for tlb
> system.cpu1.fetch.BlockedCycles 80999073 # Number of cycles fetch has spent blocked
> system.cpu1.fetch.MiscStallCycles 5941 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu1.fetch.PendingTrapStallCycles 42062 # Number of stall cycles due to pending traps
> system.cpu1.fetch.PendingQuiesceStallCycles 1494344 # Number of stall cycles due to pending quiesce instructions
> system.cpu1.fetch.IcacheWaitRetryStallCycles 284 # Number of stall cycles due to full MSHR
> system.cpu1.fetch.CacheLines 7717920 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 551887 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.ItlbSquashes 2996 # Number of outstanding ITLB misses that were squashed
> system.cpu1.fetch.rateDist::samples 117635394 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 0.638004 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 1.959630 # Number of instructions fetched each cycle (Total)
1712,1720c1740,1748
< system.cpu1.fetch.rateDist::0 61095045 82.88% 82.88% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 712004 0.97% 83.84% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 939814 1.27% 85.12% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 1614257 2.19% 87.31% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::4 1180828 1.60% 88.91% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::5 579149 0.79% 89.70% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::6 1971485 2.67% 92.37% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::7 418985 0.57% 92.94% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::8 5205758 7.06% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 104280280 88.65% 88.65% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 814710 0.69% 89.34% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 961160 0.82% 90.16% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 1713171 1.46% 91.61% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::4 1415249 1.20% 92.82% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::5 586962 0.50% 93.32% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::6 1954597 1.66% 94.98% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::7 422243 0.36% 95.34% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::8 5487022 4.66% 100.00% # Number of instructions fetched each cycle (Total)
1724,1769c1752,1797
< system.cpu1.fetch.rateDist::total 73717325 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.046909 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 0.315326 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 19856835 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 39689565 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 11370888 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 621997 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 2178040 # Number of cycles decode is squashing
< system.cpu1.decode.BranchResolved 1113164 # Number of times decode resolved a branch
< system.cpu1.decode.BranchMispred 99384 # Number of times decode detected a branch misprediction
< system.cpu1.decode.DecodedInsts 67504859 # Number of instructions handled by decode
< system.cpu1.decode.SquashedInsts 329486 # Number of squashed instructions handled by decode
< system.cpu1.rename.SquashCycles 2178040 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 20884497 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 13732674 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 23091492 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 10921071 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 2909551 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 63553177 # Number of instructions processed by rename
< system.cpu1.rename.ROBFullEvents 150 # Number of times rename has blocked due to ROB full
< system.cpu1.rename.IQFullEvents 495727 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LSQFullEvents 1775459 # Number of times rename has blocked due to LSQ full
< system.cpu1.rename.FullRegisterEvents 454 # Number of times there has been no free registers
< system.cpu1.rename.RenamedOperands 67243012 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 295535307 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 271726361 # Number of integer rename lookups
< system.cpu1.rename.fp_rename_lookups 4962 # Number of floating rename lookups
< system.cpu1.rename.CommittedMaps 47019288 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 20223723 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 581683 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 523637 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 6484055 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 11835207 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 7683859 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 982260 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 1485488 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 58475771 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 951228 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 65019700 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 99369 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 13400197 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 36106127 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 236520 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 73717325 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 0.882014 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 1.585621 # Number of insts issued each cycle
---
> system.cpu1.fetch.rateDist::total 117635394 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.022464 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 0.148221 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 20963679 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 81759193 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 11913295 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 809519 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 2189708 # Number of cycles decode is squashing
> system.cpu1.decode.BranchResolved 1137363 # Number of times decode resolved a branch
> system.cpu1.decode.BranchMispred 100954 # Number of times decode detected a branch misprediction
> system.cpu1.decode.DecodedInsts 71089276 # Number of instructions handled by decode
> system.cpu1.decode.SquashedInsts 336011 # Number of squashed instructions handled by decode
> system.cpu1.rename.SquashCycles 2189708 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 22156707 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 33902507 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 43325786 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 11473545 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 4587141 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 67137864 # Number of instructions processed by rename
> system.cpu1.rename.ROBFullEvents 137 # Number of times rename has blocked due to ROB full
> system.cpu1.rename.IQFullEvents 682095 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LSQFullEvents 3075433 # Number of times rename has blocked due to LSQ full
> system.cpu1.rename.FullRegisterEvents 1010 # Number of times there has been no free registers
> system.cpu1.rename.RenamedOperands 70763032 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 313108743 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 286757803 # Number of integer rename lookups
> system.cpu1.rename.fp_rename_lookups 6623 # Number of floating rename lookups
> system.cpu1.rename.CommittedMaps 50416422 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 20346610 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 765987 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 705836 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 8420477 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 12843204 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 8115826 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 1055497 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 1512633 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 61850161 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 1179252 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 88896986 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 93979 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 13548762 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 36246660 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 279849 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 117635394 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 0.755699 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 1.498688 # Number of insts issued each cycle
1771,1779c1799,1807
< system.cpu1.iq.issued_per_cycle::0 50542925 68.56% 68.56% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 7121407 9.66% 78.22% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 4031042 5.47% 83.69% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 3362905 4.56% 88.25% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 5367239 7.28% 95.53% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 1894348 2.57% 98.10% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::6 1048738 1.42% 99.53% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::7 275398 0.37% 99.90% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::8 73323 0.10% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 86772303 73.76% 73.76% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 9298113 7.90% 81.67% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 4175598 3.55% 85.22% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 3594840 3.06% 88.27% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 10374006 8.82% 97.09% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 1994938 1.70% 98.79% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::6 1065613 0.91% 99.69% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::7 281099 0.24% 99.93% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::8 78884 0.07% 100.00% # Number of insts issued each cycle
1783c1811
< system.cpu1.iq.issued_per_cycle::total 73717325 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 117635394 # Number of insts issued each cycle
1785,1815c1813,1843
< system.cpu1.iq.fu_full::IntAlu 33869 1.02% 1.02% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 996 0.03% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.05% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 2994112 90.44% 91.49% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 281623 8.51% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 32152 0.41% 0.41% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 986 0.01% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 7573471 95.70% 96.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 306947 3.88% 100.00% # attempts to use FU when none available
1818,1849c1846,1877
< system.cpu1.iq.FU_type_0::No_OpClass 12895 0.02% 0.02% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntAlu 35505233 54.61% 54.63% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 59031 0.09% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMisc 14 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMisc 1556 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.72% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemRead 22501549 34.61% 89.33% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 6939400 10.67% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::No_OpClass 14268 0.02% 0.02% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntAlu 37614404 42.31% 42.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 61197 0.07% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMisc 1706 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.40% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemRead 43858329 49.34% 91.74% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 7347048 8.26% 100.00% # Type of FU issued
1852,1864c1880,1892
< system.cpu1.iq.FU_type_0::total 65019700 # Type of FU issued
< system.cpu1.iq.rate 0.350988 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 3310600 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.050917 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 207206368 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 72837982 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 50730101 # Number of integer instruction queue wakeup accesses
< system.cpu1.iq.fp_inst_queue_reads 11167 # Number of floating instruction queue reads
< system.cpu1.iq.fp_inst_queue_writes 5978 # Number of floating instruction queue writes
< system.cpu1.iq.fp_inst_queue_wakeup_accesses 5058 # Number of floating instruction queue wakeup accesses
< system.cpu1.iq.int_alu_accesses 68311542 # Number of integer alu accesses
< system.cpu1.iq.fp_alu_accesses 5863 # Number of floating point alu accesses
< system.cpu1.iew.lsq.thread0.forwLoads 343642 # Number of loads that had data forwarded from stores
---
> system.cpu1.iq.FU_type_0::total 88896986 # Type of FU issued
> system.cpu1.iq.rate 0.214886 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 7913556 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.089019 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 303469985 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 76586992 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 54255274 # Number of integer instruction queue wakeup accesses
> system.cpu1.iq.fp_inst_queue_reads 15534 # Number of floating instruction queue reads
> system.cpu1.iq.fp_inst_queue_writes 8108 # Number of floating instruction queue writes
> system.cpu1.iq.fp_inst_queue_wakeup_accesses 6874 # Number of floating instruction queue wakeup accesses
> system.cpu1.iq.int_alu_accesses 96788024 # Number of integer alu accesses
> system.cpu1.iq.fp_alu_accesses 8250 # Number of floating point alu accesses
> system.cpu1.iew.lsq.thread0.forwLoads 355713 # Number of loads that had data forwarded from stores
1866,1869c1894,1897
< system.cpu1.iew.lsq.thread0.squashedLoads 2877094 # Number of loads squashed
< system.cpu1.iew.lsq.thread0.ignoredResponses 3994 # Number of memory responses ignored because the instruction is squashed
< system.cpu1.iew.lsq.thread0.memOrderViolation 17361 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 1094953 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 2862172 # Number of loads squashed
> system.cpu1.iew.lsq.thread0.ignoredResponses 4122 # Number of memory responses ignored because the instruction is squashed
> system.cpu1.iew.lsq.thread0.memOrderViolation 17485 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 1111950 # Number of stores squashed
1872,1873c1900,1901
< system.cpu1.iew.lsq.thread0.rescheduledLoads 11606945 # Number of loads that were rescheduled
< system.cpu1.iew.lsq.thread0.cacheBlocked 675630 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu1.iew.lsq.thread0.rescheduledLoads 31965671 # Number of loads that were rescheduled
> system.cpu1.iew.lsq.thread0.cacheBlocked 675853 # Number of times an access to memory failed due to the cache being blocked
1875,1891c1903,1919
< system.cpu1.iew.iewSquashCycles 2178040 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 10295917 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 191116 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 59545170 # Number of instructions dispatched to IQ
< system.cpu1.iew.iewDispSquashedInsts 114100 # Number of squashed instructions skipped by dispatch
< system.cpu1.iew.iewDispLoadInsts 11835207 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 7683859 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 664311 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 56460 # Number of times the IQ has become full, causing a stall
< system.cpu1.iew.iewLSQFullEvents 4454 # Number of times the LSQ has become full, causing a stall
< system.cpu1.iew.memOrderViolationEvents 17361 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 204103 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 160517 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 364620 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 63283569 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 21990431 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 1736131 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewSquashCycles 2189708 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 26386476 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 363440 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 63133555 # Number of instructions dispatched to IQ
> system.cpu1.iew.iewDispSquashedInsts 115239 # Number of squashed instructions skipped by dispatch
> system.cpu1.iew.iewDispLoadInsts 12843204 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 8115826 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 883054 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 66097 # Number of times the IQ has become full, causing a stall
> system.cpu1.iew.iewLSQFullEvents 4286 # Number of times the LSQ has become full, causing a stall
> system.cpu1.iew.memOrderViolationEvents 17485 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 204520 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 158639 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 363159 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 87164207 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 43354058 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 1732779 # Number of squashed instructions skipped in execute
1893,1901c1921,1929
< system.cpu1.iew.exec_nop 118171 # number of nop insts executed
< system.cpu1.iew.exec_refs 28863200 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 6787528 # Number of branches executed
< system.cpu1.iew.exec_stores 6872769 # Number of stores executed
< system.cpu1.iew.exec_rate 0.341616 # Inst execution rate
< system.cpu1.iew.wb_sent 62514610 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 50735159 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 28199774 # num instructions producing a value
< system.cpu1.iew.wb_consumers 51433237 # num instructions consuming a value
---
> system.cpu1.iew.exec_nop 104142 # number of nop insts executed
> system.cpu1.iew.exec_refs 50636612 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 7376811 # Number of branches executed
> system.cpu1.iew.exec_stores 7282554 # Number of stores executed
> system.cpu1.iew.exec_rate 0.210697 # Inst execution rate
> system.cpu1.iew.wb_sent 86400335 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 54262148 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 30287291 # num instructions producing a value
> system.cpu1.iew.wb_consumers 53873069 # num instructions consuming a value
1903,1904c1931,1932
< system.cpu1.iew.wb_rate 0.273877 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.548279 # average fanout of values written-back
---
> system.cpu1.iew.wb_rate 0.131165 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.562197 # average fanout of values written-back
1906,1911c1934,1939
< system.cpu1.commit.commitSquashedInsts 13377367 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 714708 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 317605 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 71539285 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 0.639790 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.672504 # Number of insts commited each cycle
---
> system.cpu1.commit.commitSquashedInsts 13443206 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 899403 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 316783 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 115445686 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 0.426296 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.378874 # Number of insts commited each cycle
1913,1921c1941,1949
< system.cpu1.commit.committed_per_cycle::0 55665383 77.81% 77.81% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 7811223 10.92% 88.73% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 2101815 2.94% 91.67% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 1189986 1.66% 93.33% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 946066 1.32% 94.65% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 613597 0.86% 95.51% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 912617 1.28% 96.79% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 531458 0.74% 97.53% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 1767140 2.47% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 97421932 84.39% 84.39% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 9594899 8.31% 92.70% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 2172227 1.88% 94.58% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 1301741 1.13% 95.71% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 988993 0.86% 96.56% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 587152 0.51% 97.07% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 1008803 0.87% 97.95% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 534624 0.46% 98.41% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 1835315 1.59% 100.00% # Number of insts commited each cycle
1925,1927c1953,1955
< system.cpu1.commit.committed_per_cycle::total 71539285 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 36096592 # Number of instructions committed
< system.cpu1.commit.committedOps 45770088 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 115445686 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 38873610 # Number of instructions committed
> system.cpu1.commit.committedOps 49214014 # Number of ops (including micro ops) committed
1929,1936c1957,1999
< system.cpu1.commit.refs 15547019 # Number of memory references committed
< system.cpu1.commit.loads 8958113 # Number of loads committed
< system.cpu1.commit.membars 191016 # Number of memory barriers committed
< system.cpu1.commit.branches 5856523 # Number of branches committed
< system.cpu1.commit.fp_insts 5022 # Number of committed floating point instructions.
< system.cpu1.commit.int_insts 40800338 # Number of committed integer instructions.
< system.cpu1.commit.function_calls 520894 # Number of function calls committed.
< system.cpu1.commit.bw_lim_events 1767140 # number cycles where commit BW limit reached
---
> system.cpu1.commit.refs 16984908 # Number of memory references committed
> system.cpu1.commit.loads 9981032 # Number of loads committed
> system.cpu1.commit.membars 195536 # Number of memory barriers committed
> system.cpu1.commit.branches 6424997 # Number of branches committed
> system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions.
> system.cpu1.commit.int_insts 43926362 # Number of committed integer instructions.
> system.cpu1.commit.function_calls 553376 # Number of function calls committed.
> system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntAlu 32169137 65.37% 65.37% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntMult 58263 0.12% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.48% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMisc 1706 0.00% 65.49% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.49% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.49% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.49% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemRead 9981032 20.28% 85.77% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemWrite 7003876 14.23% 100.00% # Class of committed instruction
> system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
> system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
> system.cpu1.commit.op_class_0::total 49214014 # Class of committed instruction
> system.cpu1.commit.bw_lim_events 1835315 # number cycles where commit BW limit reached
1938,1964c2001,2027
< system.cpu1.rob.rob_reads 127901171 # The number of ROB reads
< system.cpu1.rob.rob_writes 120555711 # The number of ROB writes
< system.cpu1.timesIdled 777241 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 111530457 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 5026003021 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 36015814 # Number of Instructions Simulated
< system.cpu1.committedOps 45689310 # Number of Ops (including micro ops) Simulated
< system.cpu1.committedInsts_total 36015814 # Number of Instructions Simulated
< system.cpu1.cpi 5.143512 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 5.143512 # CPI: Total CPI of All Threads
< system.cpu1.ipc 0.194420 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 0.194420 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 292255401 # number of integer regfile reads
< system.cpu1.int_regfile_writes 53047565 # number of integer regfile writes
< system.cpu1.fp_regfile_reads 3797 # number of floating regfile reads
< system.cpu1.fp_regfile_writes 1766 # number of floating regfile writes
< system.cpu1.misc_regfile_reads 133121160 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 545345 # number of misc regfile writes
< system.cpu1.icache.tags.replacements 600500 # number of replacements
< system.cpu1.icache.tags.tagsinuse 498.750005 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 6745926 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 601012 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 11.224278 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 74974413000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.750005 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974121 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.974121 # Average percentage of cache occupancy
---
> system.cpu1.rob.rob_reads 175201017 # The number of ROB reads
> system.cpu1.rob.rob_writes 127586843 # The number of ROB writes
> system.cpu1.timesIdled 1428644 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 296058429 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 4796946974 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 38803971 # Number of Instructions Simulated
> system.cpu1.committedOps 49144375 # Number of Ops (including micro ops) Simulated
> system.cpu1.committedInsts_total 38803971 # Number of Instructions Simulated
> system.cpu1.cpi 10.661121 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 10.661121 # CPI: Total CPI of All Threads
> system.cpu1.ipc 0.093799 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 0.093799 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 391634066 # number of integer regfile reads
> system.cpu1.int_regfile_writes 56368159 # number of integer regfile writes
> system.cpu1.fp_regfile_reads 5144 # number of floating regfile reads
> system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes
> system.cpu1.misc_regfile_reads 202762353 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 723009 # number of misc regfile writes
> system.cpu1.icache.tags.replacements 614589 # number of replacements
> system.cpu1.icache.tags.tagsinuse 498.738252 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 7056364 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 615101 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 11.471879 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 74953244500 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.738252 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974098 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.974098 # Average percentage of cache occupancy
1966,1969c2029
< system.cpu1.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
1971,2014c2031,2074
< system.cpu1.icache.tags.tag_accesses 7994182 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 7994182 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 6745926 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 6745926 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 6745926 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 6745926 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 6745926 # number of overall hits
< system.cpu1.icache.overall_hits::total 6745926 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 647211 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 647211 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 647211 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 647211 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 647211 # number of overall misses
< system.cpu1.icache.overall_misses::total 647211 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8801556837 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 8801556837 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 8801556837 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 8801556837 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 8801556837 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 8801556837 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 7393137 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 7393137 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 7393137 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 7393137 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 7393137 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 7393137 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.087542 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.087542 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.087542 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.087542 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.087542 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.087542 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13599.207734 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 13599.207734 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13599.207734 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 13599.207734 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13599.207734 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 13599.207734 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 3107 # number of cycles access was blocked
< system.cpu1.icache.blocked_cycles::no_targets 341 # number of cycles access was blocked
< system.cpu1.icache.blocked::no_mshrs 199 # number of cycles access was blocked
< system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.613065 # average number of cycles each access was blocked
< system.cpu1.icache.avg_blocked_cycles::no_targets 341 # average number of cycles each access was blocked
---
> system.cpu1.icache.tags.tag_accesses 8332995 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 8332995 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 7056364 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 7056364 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 7056364 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 7056364 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 7056364 # number of overall hits
> system.cpu1.icache.overall_hits::total 7056364 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 661505 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 661505 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 661505 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 661505 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 661505 # number of overall misses
> system.cpu1.icache.overall_misses::total 661505 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8964922762 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 8964922762 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 8964922762 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 8964922762 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 8964922762 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 8964922762 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 7717869 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 7717869 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 7717869 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 7717869 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 7717869 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 7717869 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085711 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.085711 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085711 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.085711 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085711 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.085711 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13552.312926 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 13552.312926 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13552.312926 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 13552.312926 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13552.312926 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 13552.312926 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 3582 # number of cycles access was blocked
> system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu1.icache.blocked::no_mshrs 212 # number of cycles access was blocked
> system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.896226 # average number of cycles each access was blocked
> system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2017,2050c2077,2110
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46165 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 46165 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 46165 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 46165 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 46165 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 46165 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 601046 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 601046 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 601046 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 601046 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 601046 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 601046 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7178040035 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 7178040035 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7178040035 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 7178040035 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7178040035 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 7178040035 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3605250 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3605250 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3605250 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 3605250 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081298 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.081298 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.081298 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.081298 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.081298 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.081298 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11942.580160 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11942.580160 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11942.580160 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 11942.580160 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11942.580160 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 11942.580160 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46379 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 46379 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 46379 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 46379 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 46379 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 46379 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615126 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 615126 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 615126 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 615126 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 615126 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 615126 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7320744820 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 7320744820 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7320744820 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 7320744820 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7320744820 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 7320744820 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3847250 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3847250 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3847250 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 3847250 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079702 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079702 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079702 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.079702 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079702 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.079702 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11901.211817 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11901.211817 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11901.211817 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 11901.211817 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11901.211817 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 11901.211817 # average overall mshr miss latency
2056,2147c2116,2204
< system.cpu1.dcache.tags.replacements 339082 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 482.965075 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 12423447 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 339594 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 36.583235 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 71024759250 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 482.965075 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.943291 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.943291 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 57544569 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 57544569 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 8247311 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 8247311 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 3935666 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 3935666 # number of WriteReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94453 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 94453 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 92037 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 92037 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 12182977 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 12182977 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 12182977 # number of overall hits
< system.cpu1.dcache.overall_hits::total 12182977 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 400036 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 400036 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 1501327 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 1501327 # number of WriteReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13642 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 13642 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10758 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 10758 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 1901363 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 1901363 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 1901363 # number of overall misses
< system.cpu1.dcache.overall_misses::total 1901363 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6052529769 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 6052529769 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 75305143416 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 75305143416 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 124772740 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 124772740 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 57202570 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 57202570 # number of StoreCondReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 81357673185 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 81357673185 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 81357673185 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 81357673185 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 8647347 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 8647347 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 5436993 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 5436993 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 108095 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 108095 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102795 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 102795 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 14084340 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 14084340 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 14084340 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 14084340 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.046261 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.046261 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.276132 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.276132 # miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126204 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126204 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104655 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104655 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134998 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.134998 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134998 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.134998 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15129.962726 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 15129.962726 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 50159.054900 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 50159.054900 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9146.220496 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9146.220496 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5317.212307 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5317.212307 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42789.132420 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 42789.132420 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42789.132420 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 42789.132420 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 27478 # number of cycles access was blocked
< system.cpu1.dcache.blocked_cycles::no_targets 17677 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked
---
> system.cpu1.dcache.tags.replacements 363297 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 486.117445 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 13019165 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 363645 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 35.801853 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 71011321250 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.117445 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949448 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.949448 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 348 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 60291027 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 60291027 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 8513196 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 8513196 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 4271027 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 4271027 # number of WriteReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99804 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 99804 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97081 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 97081 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 12784223 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 12784223 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 12784223 # number of overall hits
> system.cpu1.dcache.overall_hits::total 12784223 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 403038 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 403038 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 1566274 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 1566274 # number of WriteReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14187 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 14187 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10911 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 10911 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 1969312 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 1969312 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 1969312 # number of overall misses
> system.cpu1.dcache.overall_misses::total 1969312 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6108097691 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 6108097691 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 77891341203 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 77891341203 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131130743 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 131130743 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58206088 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 58206088 # number of StoreCondReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 83999438894 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 83999438894 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 83999438894 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 83999438894 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 8916234 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 8916234 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 5837301 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 5837301 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 113991 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 113991 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107992 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 107992 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 14753535 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 14753535 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 14753535 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 14753535 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045203 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.045203 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.268322 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.268322 # miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124457 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124457 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101035 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101035 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.133481 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.133481 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.133481 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.133481 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15155.140932 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15155.140932 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 49730.341692 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 49730.341692 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9243.021287 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9243.021287 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5334.624507 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5334.624507 # average StoreCondReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42654.205577 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 42654.205577 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42654.205577 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 42654.205577 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 29593 # number of cycles access was blocked
> system.cpu1.dcache.blocked_cycles::no_targets 18156 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_mshrs 3287 # number of cycles access was blocked
2149,2150c2206,2207
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.517669 # average number of cycles each access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_targets 101.011429 # average number of cycles each access was blocked
---
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.003042 # average number of cycles each access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_targets 103.748571 # average number of cycles each access was blocked
2153,2218c2210,2275
< system.cpu1.dcache.writebacks::writebacks 304166 # number of writebacks
< system.cpu1.dcache.writebacks::total 304166 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172051 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 172051 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1358464 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 1358464 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1244 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1244 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 1530515 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 1530515 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 1530515 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 1530515 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227985 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 227985 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 142863 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 142863 # number of WriteReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12398 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12398 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10758 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 10758 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 370848 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 370848 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 370848 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 370848 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2835218608 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2835218608 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5632564954 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5632564954 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86730259 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86730259 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 35684430 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 35684430 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8467783562 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 8467783562 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8467783562 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 8467783562 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 62130810008 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 62130810008 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25850406364 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25850406364 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 87981216372 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 87981216372 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026365 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026365 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026276 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026276 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.114695 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.114695 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104655 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104655 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026331 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.026331 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026331 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.026331 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12435.987490 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12435.987490 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39426.338198 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39426.338198 # average WriteReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6995.504033 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6995.504033 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3317.013385 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3317.013385 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22833.569446 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22833.569446 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22833.569446 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22833.569446 # average overall mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 327781 # number of writebacks
> system.cpu1.dcache.writebacks::total 327781 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171674 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 171674 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1403027 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 1403027 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1467 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1467 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 1574701 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 1574701 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 1574701 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 1574701 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231364 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 231364 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163247 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 163247 # number of WriteReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12720 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12720 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10911 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 10911 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 394611 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 394611 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 394611 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 394611 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2878773157 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2878773157 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7001686259 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7001686259 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89753005 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89753005 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36382912 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36382912 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9880459416 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 9880459416 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9880459416 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 9880459416 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231749012 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231749012 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25869959988 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25869959988 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195101709000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195101709000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025949 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025949 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027966 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027966 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111588 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111588 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101035 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101035 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026747 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.026747 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026747 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.026747 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12442.614914 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12442.614914 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42890.137393 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 42890.137393 # average WriteReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7056.053852 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7056.053852 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3334.516726 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3334.516726 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25038.479454 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25038.479454 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25038.479454 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25038.479454 # average overall mshr miss latency
2242,2245c2299,2302
< system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1737834287366 # number of ReadReq MSHR uncacheable cycles
< system.iocache.ReadReq_mshr_uncacheable_latency::total 1737834287366 # number of ReadReq MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1737834287366 # number of overall MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::total 1737834287366 # number of overall MSHR uncacheable cycles
---
> system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1735350782356 # number of ReadReq MSHR uncacheable cycles
> system.iocache.ReadReq_mshr_uncacheable_latency::total 1735350782356 # number of ReadReq MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1735350782356 # number of overall MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::total 1735350782356 # number of overall MSHR uncacheable cycles
2252c2309
< system.cpu0.kern.inst.quiesce 45161 # number of quiesce instructions executed
---
> system.cpu0.kern.inst.quiesce 42636 # number of quiesce instructions executed
2254c2311
< system.cpu1.kern.inst.quiesce 47884 # number of quiesce instructions executed
---
> system.cpu1.kern.inst.quiesce 50408 # number of quiesce instructions executed