Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

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stats.txt (9199:2a5516167688)	stats.txt (9223:be1c1059438b)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.617033 # Number of seconds simulated 4sim_ticks 2617033170500 # Number of ticks simulated 5final_tick 2617033170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 88113 # Simulator instruction rate (inst/s) 8host_op_rate 113402 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3655705591 # Simulator tick rate (ticks/s) 10host_mem_usage 391256 # Number of bytes of host memory used 11host_seconds 715.88 # Real time elapsed on the host 12sim_insts 63077791 # Number of instructions simulated 13sim_ops 81181923 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 395840 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4357428 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 425152 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 5244336 # Number of bytes read from this memory 22system.physmem.bytes_read::total 131535204 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 395840 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 425152 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 820992 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4255104 # Number of bytes written to this memory 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory 29system.physmem.bytes_written::total 7284240 # Number of bytes written to this memory 30system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 6185 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 68157 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 6643 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 81969 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 15301800 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 66486 # Number of write requests responded to by this memory 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 823770 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 46277796 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.dtb.walker 245 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 151255 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 1665026 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.dtb.walker 440 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.inst 162456 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 2003924 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 50261191 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 151255 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 162456 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 313711 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 1625927 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 6496 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 1150974 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 2783396 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 1625927 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 46277796 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.dtb.walker 245 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.inst 151255 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 1671522 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.dtb.walker 440 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.inst 162456 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 3154898 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 53044587 # Total bandwidth to/from this memory (bytes/s) 69system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 70system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory 71system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 72system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 73system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory 74system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 75system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 76system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory 77system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 78system.realview.nvmem.bw_read::cpu0.inst 24 # Total read bandwidth from this memory (bytes/s) 79system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) 80system.realview.nvmem.bw_read::total 171 # Total read bandwidth from this memory (bytes/s) 81system.realview.nvmem.bw_inst_read::cpu0.inst 24 # Instruction read bandwidth from this memory (bytes/s) 82system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) 83system.realview.nvmem.bw_inst_read::total 171 # Instruction read bandwidth from this memory (bytes/s) 84system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s) 85system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) 86system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s) 87system.l2c.replacements 72594 # number of replacements 88system.l2c.tagsinuse 53100.305923 # Cycle average of tags in use 89system.l2c.total_refs 1970249 # Total number of references to valid blocks. 90system.l2c.sampled_refs 137794 # Sample count of references to valid blocks. 91system.l2c.avg_refs 14.298511 # Average number of references to valid blocks. 92system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 93system.l2c.occ_blocks::writebacks 37791.704596 # Average occupied blocks per requestor 94system.l2c.occ_blocks::cpu0.dtb.walker 4.504480 # Average occupied blocks per requestor 95system.l2c.occ_blocks::cpu0.itb.walker 0.004560 # Average occupied blocks per requestor 96system.l2c.occ_blocks::cpu0.inst 4202.741800 # Average occupied blocks per requestor 97system.l2c.occ_blocks::cpu0.data 2939.105076 # Average occupied blocks per requestor 98system.l2c.occ_blocks::cpu1.dtb.walker 13.484693 # Average occupied blocks per requestor 99system.l2c.occ_blocks::cpu1.inst 4025.080355 # Average occupied blocks per requestor 100system.l2c.occ_blocks::cpu1.data 4123.680364 # Average occupied blocks per requestor 101system.l2c.occ_percent::writebacks 0.576656 # Average percentage of cache occupancy 102system.l2c.occ_percent::cpu0.dtb.walker 0.000069 # Average percentage of cache occupancy 103system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 104system.l2c.occ_percent::cpu0.inst 0.064129 # Average percentage of cache occupancy 105system.l2c.occ_percent::cpu0.data 0.044847 # Average percentage of cache occupancy 106system.l2c.occ_percent::cpu1.dtb.walker 0.000206 # Average percentage of cache occupancy 107system.l2c.occ_percent::cpu1.inst 0.061418 # Average percentage of cache occupancy 108system.l2c.occ_percent::cpu1.data 0.062922 # Average percentage of cache occupancy 109system.l2c.occ_percent::total 0.810246 # Average percentage of cache occupancy 110system.l2c.ReadReq_hits::cpu0.dtb.walker 54561 # number of ReadReq hits 111system.l2c.ReadReq_hits::cpu0.itb.walker 5750 # number of ReadReq hits 112system.l2c.ReadReq_hits::cpu0.inst 401038 # number of ReadReq hits 113system.l2c.ReadReq_hits::cpu0.data 165879 # number of ReadReq hits 114system.l2c.ReadReq_hits::cpu1.dtb.walker 78192 # number of ReadReq hits 115system.l2c.ReadReq_hits::cpu1.itb.walker 6577 # number of ReadReq hits 116system.l2c.ReadReq_hits::cpu1.inst 616294 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu1.data 201951 # number of ReadReq hits 118system.l2c.ReadReq_hits::total 1530242 # number of ReadReq hits 119system.l2c.Writeback_hits::writebacks 584193 # number of Writeback hits 120system.l2c.Writeback_hits::total 584193 # number of Writeback hits 121system.l2c.UpgradeReq_hits::cpu0.data 1046 # number of UpgradeReq hits 122system.l2c.UpgradeReq_hits::cpu1.data 814 # number of UpgradeReq hits 123system.l2c.UpgradeReq_hits::total 1860 # number of UpgradeReq hits 124system.l2c.SCUpgradeReq_hits::cpu0.data 204 # number of SCUpgradeReq hits 125system.l2c.SCUpgradeReq_hits::cpu1.data 171 # number of SCUpgradeReq hits 126system.l2c.SCUpgradeReq_hits::total 375 # number of SCUpgradeReq hits 127system.l2c.ReadExReq_hits::cpu0.data 48310 # number of ReadExReq hits 128system.l2c.ReadExReq_hits::cpu1.data 58954 # number of ReadExReq hits 129system.l2c.ReadExReq_hits::total 107264 # number of ReadExReq hits 130system.l2c.demand_hits::cpu0.dtb.walker 54561 # number of demand (read+write) hits 131system.l2c.demand_hits::cpu0.itb.walker 5750 # number of demand (read+write) hits 132system.l2c.demand_hits::cpu0.inst 401038 # number of demand (read+write) hits 133system.l2c.demand_hits::cpu0.data 214189 # number of demand (read+write) hits 134system.l2c.demand_hits::cpu1.dtb.walker 78192 # number of demand (read+write) hits 135system.l2c.demand_hits::cpu1.itb.walker 6577 # number of demand (read+write) hits 136system.l2c.demand_hits::cpu1.inst 616294 # number of demand (read+write) hits 137system.l2c.demand_hits::cpu1.data 260905 # number of demand (read+write) hits 138system.l2c.demand_hits::total 1637506 # number of demand (read+write) hits 139system.l2c.overall_hits::cpu0.dtb.walker 54561 # number of overall hits 140system.l2c.overall_hits::cpu0.itb.walker 5750 # number of overall hits 141system.l2c.overall_hits::cpu0.inst 401038 # number of overall hits 142system.l2c.overall_hits::cpu0.data 214189 # number of overall hits 143system.l2c.overall_hits::cpu1.dtb.walker 78192 # number of overall hits 144system.l2c.overall_hits::cpu1.itb.walker 6577 # number of overall hits 145system.l2c.overall_hits::cpu1.inst 616294 # number of overall hits 146system.l2c.overall_hits::cpu1.data 260905 # number of overall hits 147system.l2c.overall_hits::total 1637506 # number of overall hits 148system.l2c.ReadReq_misses::cpu0.dtb.walker 10 # number of ReadReq misses 149system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 150system.l2c.ReadReq_misses::cpu0.inst 6056 # number of ReadReq misses 151system.l2c.ReadReq_misses::cpu0.data 6316 # number of ReadReq misses 152system.l2c.ReadReq_misses::cpu1.dtb.walker 18 # number of ReadReq misses 153system.l2c.ReadReq_misses::cpu1.inst 6605 # number of ReadReq misses 154system.l2c.ReadReq_misses::cpu1.data 6313 # number of ReadReq misses 155system.l2c.ReadReq_misses::total 25320 # number of ReadReq misses 156system.l2c.UpgradeReq_misses::cpu0.data 5689 # number of UpgradeReq misses 157system.l2c.UpgradeReq_misses::cpu1.data 4311 # number of UpgradeReq misses 158system.l2c.UpgradeReq_misses::total 10000 # number of UpgradeReq misses 159system.l2c.SCUpgradeReq_misses::cpu0.data 783 # number of SCUpgradeReq misses 160system.l2c.SCUpgradeReq_misses::cpu1.data 578 # number of SCUpgradeReq misses 161system.l2c.SCUpgradeReq_misses::total 1361 # number of SCUpgradeReq misses 162system.l2c.ReadExReq_misses::cpu0.data 63204 # number of ReadExReq misses 163system.l2c.ReadExReq_misses::cpu1.data 76879 # number of ReadExReq misses 164system.l2c.ReadExReq_misses::total 140083 # number of ReadExReq misses 165system.l2c.demand_misses::cpu0.dtb.walker 10 # number of demand (read+write) misses 166system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 167system.l2c.demand_misses::cpu0.inst 6056 # number of demand (read+write) misses 168system.l2c.demand_misses::cpu0.data 69520 # number of demand (read+write) misses 169system.l2c.demand_misses::cpu1.dtb.walker 18 # number of demand (read+write) misses 170system.l2c.demand_misses::cpu1.inst 6605 # number of demand (read+write) misses 171system.l2c.demand_misses::cpu1.data 83192 # number of demand (read+write) misses 172system.l2c.demand_misses::total 165403 # number of demand (read+write) misses 173system.l2c.overall_misses::cpu0.dtb.walker 10 # number of overall misses 174system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 175system.l2c.overall_misses::cpu0.inst 6056 # number of overall misses 176system.l2c.overall_misses::cpu0.data 69520 # number of overall misses 177system.l2c.overall_misses::cpu1.dtb.walker 18 # number of overall misses 178system.l2c.overall_misses::cpu1.inst 6605 # number of overall misses 179system.l2c.overall_misses::cpu1.data 83192 # number of overall misses 180system.l2c.overall_misses::total 165403 # number of overall misses 181system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 522500 # number of ReadReq miss cycles 182system.l2c.ReadReq_miss_latency::cpu0.itb.walker 112500 # number of ReadReq miss cycles 183system.l2c.ReadReq_miss_latency::cpu0.inst 322936498 # number of ReadReq miss cycles 184system.l2c.ReadReq_miss_latency::cpu0.data 331707998 # number of ReadReq miss cycles 185system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 952500 # number of ReadReq miss cycles 186system.l2c.ReadReq_miss_latency::cpu1.inst 351349999 # number of ReadReq miss cycles 187system.l2c.ReadReq_miss_latency::cpu1.data 331785500 # number of ReadReq miss cycles 188system.l2c.ReadReq_miss_latency::total 1339367495 # number of ReadReq miss cycles 189system.l2c.UpgradeReq_miss_latency::cpu0.data 20090481 # number of UpgradeReq miss cycles 190system.l2c.UpgradeReq_miss_latency::cpu1.data 27401499 # number of UpgradeReq miss cycles 191system.l2c.UpgradeReq_miss_latency::total 47491980 # number of UpgradeReq miss cycles 192system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1617500 # number of SCUpgradeReq miss cycles 193system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6565000 # number of SCUpgradeReq miss cycles 194system.l2c.SCUpgradeReq_miss_latency::total 8182500 # number of SCUpgradeReq miss cycles 195system.l2c.ReadExReq_miss_latency::cpu0.data 3365710489 # number of ReadExReq miss cycles 196system.l2c.ReadExReq_miss_latency::cpu1.data 4075887489 # number of ReadExReq miss cycles 197system.l2c.ReadExReq_miss_latency::total 7441597978 # number of ReadExReq miss cycles 198system.l2c.demand_miss_latency::cpu0.dtb.walker 522500 # number of demand (read+write) miss cycles 199system.l2c.demand_miss_latency::cpu0.itb.walker 112500 # number of demand (read+write) miss cycles 200system.l2c.demand_miss_latency::cpu0.inst 322936498 # number of demand (read+write) miss cycles 201system.l2c.demand_miss_latency::cpu0.data 3697418487 # number of demand (read+write) miss cycles 202system.l2c.demand_miss_latency::cpu1.dtb.walker 952500 # number of demand (read+write) miss cycles 203system.l2c.demand_miss_latency::cpu1.inst 351349999 # number of demand (read+write) miss cycles 204system.l2c.demand_miss_latency::cpu1.data 4407672989 # number of demand (read+write) miss cycles 205system.l2c.demand_miss_latency::total 8780965473 # number of demand (read+write) miss cycles 206system.l2c.overall_miss_latency::cpu0.dtb.walker 522500 # number of overall miss cycles 207system.l2c.overall_miss_latency::cpu0.itb.walker 112500 # number of overall miss cycles 208system.l2c.overall_miss_latency::cpu0.inst 322936498 # number of overall miss cycles 209system.l2c.overall_miss_latency::cpu0.data 3697418487 # number of overall miss cycles 210system.l2c.overall_miss_latency::cpu1.dtb.walker 952500 # number of overall miss cycles 211system.l2c.overall_miss_latency::cpu1.inst 351349999 # number of overall miss cycles 212system.l2c.overall_miss_latency::cpu1.data 4407672989 # number of overall miss cycles 213system.l2c.overall_miss_latency::total 8780965473 # number of overall miss cycles 214system.l2c.ReadReq_accesses::cpu0.dtb.walker 54571 # number of ReadReq accesses(hits+misses) 215system.l2c.ReadReq_accesses::cpu0.itb.walker 5752 # number of ReadReq accesses(hits+misses) 216system.l2c.ReadReq_accesses::cpu0.inst 407094 # number of ReadReq accesses(hits+misses) 217system.l2c.ReadReq_accesses::cpu0.data 172195 # number of ReadReq accesses(hits+misses) 218system.l2c.ReadReq_accesses::cpu1.dtb.walker 78210 # number of ReadReq accesses(hits+misses) 219system.l2c.ReadReq_accesses::cpu1.itb.walker 6577 # number of ReadReq accesses(hits+misses) 220system.l2c.ReadReq_accesses::cpu1.inst 622899 # number of ReadReq accesses(hits+misses) 221system.l2c.ReadReq_accesses::cpu1.data 208264 # number of ReadReq accesses(hits+misses) 222system.l2c.ReadReq_accesses::total 1555562 # number of ReadReq accesses(hits+misses) 223system.l2c.Writeback_accesses::writebacks 584193 # number of Writeback accesses(hits+misses) 224system.l2c.Writeback_accesses::total 584193 # number of Writeback accesses(hits+misses) 225system.l2c.UpgradeReq_accesses::cpu0.data 6735 # number of UpgradeReq accesses(hits+misses) 226system.l2c.UpgradeReq_accesses::cpu1.data 5125 # number of UpgradeReq accesses(hits+misses) 227system.l2c.UpgradeReq_accesses::total 11860 # number of UpgradeReq accesses(hits+misses) 228system.l2c.SCUpgradeReq_accesses::cpu0.data 987 # number of SCUpgradeReq accesses(hits+misses) 229system.l2c.SCUpgradeReq_accesses::cpu1.data 749 # number of SCUpgradeReq accesses(hits+misses) 230system.l2c.SCUpgradeReq_accesses::total 1736 # number of SCUpgradeReq accesses(hits+misses) 231system.l2c.ReadExReq_accesses::cpu0.data 111514 # number of ReadExReq accesses(hits+misses) 232system.l2c.ReadExReq_accesses::cpu1.data 135833 # number of ReadExReq accesses(hits+misses) 233system.l2c.ReadExReq_accesses::total 247347 # number of ReadExReq accesses(hits+misses) 234system.l2c.demand_accesses::cpu0.dtb.walker 54571 # number of demand (read+write) accesses 235system.l2c.demand_accesses::cpu0.itb.walker 5752 # number of demand (read+write) accesses 236system.l2c.demand_accesses::cpu0.inst 407094 # number of demand (read+write) accesses 237system.l2c.demand_accesses::cpu0.data 283709 # number of demand (read+write) accesses 238system.l2c.demand_accesses::cpu1.dtb.walker 78210 # number of demand (read+write) accesses 239system.l2c.demand_accesses::cpu1.itb.walker 6577 # number of demand (read+write) accesses 240system.l2c.demand_accesses::cpu1.inst 622899 # number of demand (read+write) accesses 241system.l2c.demand_accesses::cpu1.data 344097 # number of demand (read+write) accesses 242system.l2c.demand_accesses::total 1802909 # number of demand (read+write) accesses 243system.l2c.overall_accesses::cpu0.dtb.walker 54571 # number of overall (read+write) accesses 244system.l2c.overall_accesses::cpu0.itb.walker 5752 # number of overall (read+write) accesses 245system.l2c.overall_accesses::cpu0.inst 407094 # number of overall (read+write) accesses 246system.l2c.overall_accesses::cpu0.data 283709 # number of overall (read+write) accesses 247system.l2c.overall_accesses::cpu1.dtb.walker 78210 # number of overall (read+write) accesses 248system.l2c.overall_accesses::cpu1.itb.walker 6577 # number of overall (read+write) accesses 249system.l2c.overall_accesses::cpu1.inst 622899 # number of overall (read+write) accesses 250system.l2c.overall_accesses::cpu1.data 344097 # number of overall (read+write) accesses 251system.l2c.overall_accesses::total 1802909 # number of overall (read+write) accesses 252system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000183 # miss rate for ReadReq accesses 253system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000348 # miss rate for ReadReq accesses 254system.l2c.ReadReq_miss_rate::cpu0.inst 0.014876 # miss rate for ReadReq accesses 255system.l2c.ReadReq_miss_rate::cpu0.data 0.036679 # miss rate for ReadReq accesses 256system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000230 # miss rate for ReadReq accesses 257system.l2c.ReadReq_miss_rate::cpu1.inst 0.010604 # miss rate for ReadReq accesses 258system.l2c.ReadReq_miss_rate::cpu1.data 0.030312 # miss rate for ReadReq accesses 259system.l2c.ReadReq_miss_rate::total 0.016277 # miss rate for ReadReq accesses 260system.l2c.UpgradeReq_miss_rate::cpu0.data 0.844692 # miss rate for UpgradeReq accesses 261system.l2c.UpgradeReq_miss_rate::cpu1.data 0.841171 # miss rate for UpgradeReq accesses 262system.l2c.UpgradeReq_miss_rate::total 0.843170 # miss rate for UpgradeReq accesses 263system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.793313 # miss rate for SCUpgradeReq accesses 264system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.771696 # miss rate for SCUpgradeReq accesses 265system.l2c.SCUpgradeReq_miss_rate::total 0.783986 # miss rate for SCUpgradeReq accesses 266system.l2c.ReadExReq_miss_rate::cpu0.data 0.566781 # miss rate for ReadExReq accesses 267system.l2c.ReadExReq_miss_rate::cpu1.data 0.565982 # miss rate for ReadExReq accesses 268system.l2c.ReadExReq_miss_rate::total 0.566342 # miss rate for ReadExReq accesses 269system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000183 # miss rate for demand accesses 270system.l2c.demand_miss_rate::cpu0.itb.walker 0.000348 # miss rate for demand accesses 271system.l2c.demand_miss_rate::cpu0.inst 0.014876 # miss rate for demand accesses 272system.l2c.demand_miss_rate::cpu0.data 0.245040 # miss rate for demand accesses 273system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000230 # miss rate for demand accesses 274system.l2c.demand_miss_rate::cpu1.inst 0.010604 # miss rate for demand accesses 275system.l2c.demand_miss_rate::cpu1.data 0.241769 # miss rate for demand accesses 276system.l2c.demand_miss_rate::total 0.091742 # miss rate for demand accesses 277system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000183 # miss rate for overall accesses 278system.l2c.overall_miss_rate::cpu0.itb.walker 0.000348 # miss rate for overall accesses 279system.l2c.overall_miss_rate::cpu0.inst 0.014876 # miss rate for overall accesses 280system.l2c.overall_miss_rate::cpu0.data 0.245040 # miss rate for overall accesses 281system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000230 # miss rate for overall accesses 282system.l2c.overall_miss_rate::cpu1.inst 0.010604 # miss rate for overall accesses 283system.l2c.overall_miss_rate::cpu1.data 0.241769 # miss rate for overall accesses 284system.l2c.overall_miss_rate::total 0.091742 # miss rate for overall accesses 285system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52250 # average ReadReq miss latency 286system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 56250 # average ReadReq miss latency 287system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53325.049207 # average ReadReq miss latency 288system.l2c.ReadReq_avg_miss_latency::cpu0.data 52518.682394 # average ReadReq miss latency 289system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52916.666667 # average ReadReq miss latency 290system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53194.549432 # average ReadReq miss latency 291system.l2c.ReadReq_avg_miss_latency::cpu1.data 52555.916363 # average ReadReq miss latency 292system.l2c.ReadReq_avg_miss_latency::total 52897.610387 # average ReadReq miss latency 293system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3531.460889 # average UpgradeReq miss latency 294system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6356.181628 # average UpgradeReq miss latency 295system.l2c.UpgradeReq_avg_miss_latency::total 4749.198000 # average UpgradeReq miss latency 296system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2065.772669 # average SCUpgradeReq miss latency 297system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11358.131488 # average SCUpgradeReq miss latency 298system.l2c.SCUpgradeReq_avg_miss_latency::total 6012.123439 # average SCUpgradeReq miss latency 299system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53251.542450 # average ReadExReq miss latency 300system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53016.916050 # average ReadExReq miss latency 301system.l2c.ReadExReq_avg_miss_latency::total 53122.777054 # average ReadExReq miss latency 302system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52250 # average overall miss latency 303system.l2c.demand_avg_miss_latency::cpu0.itb.walker 56250 # average overall miss latency 304system.l2c.demand_avg_miss_latency::cpu0.inst 53325.049207 # average overall miss latency 305system.l2c.demand_avg_miss_latency::cpu0.data 53184.960975 # average overall miss latency 306system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52916.666667 # average overall miss latency 307system.l2c.demand_avg_miss_latency::cpu1.inst 53194.549432 # average overall miss latency 308system.l2c.demand_avg_miss_latency::cpu1.data 52981.933227 # average overall miss latency 309system.l2c.demand_avg_miss_latency::total 53088.308392 # average overall miss latency 310system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52250 # average overall miss latency 311system.l2c.overall_avg_miss_latency::cpu0.itb.walker 56250 # average overall miss latency 312system.l2c.overall_avg_miss_latency::cpu0.inst 53325.049207 # average overall miss latency 313system.l2c.overall_avg_miss_latency::cpu0.data 53184.960975 # average overall miss latency 314system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52916.666667 # average overall miss latency 315system.l2c.overall_avg_miss_latency::cpu1.inst 53194.549432 # average overall miss latency 316system.l2c.overall_avg_miss_latency::cpu1.data 52981.933227 # average overall miss latency 317system.l2c.overall_avg_miss_latency::total 53088.308392 # average overall miss latency 318system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 319system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 320system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 321system.l2c.blocked::no_targets 0 # number of cycles access was blocked 322system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 323system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 324system.l2c.fast_writes 0 # number of fast writes performed 325system.l2c.cache_copies 0 # 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number of overall MSHR hits 339system.l2c.overall_mshr_hits::cpu0.data 40 # number of overall MSHR hits 340system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits 341system.l2c.overall_mshr_hits::cpu1.data 25 # number of overall MSHR hits 342system.l2c.overall_mshr_hits::total 76 # number of overall MSHR hits 343system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 10 # number of ReadReq MSHR misses 344system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses 345system.l2c.ReadReq_mshr_misses::cpu0.inst 6052 # number of ReadReq MSHR misses 346system.l2c.ReadReq_mshr_misses::cpu0.data 6276 # number of ReadReq MSHR misses 347system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 18 # number of ReadReq MSHR misses 348system.l2c.ReadReq_mshr_misses::cpu1.inst 6598 # number of ReadReq MSHR misses 349system.l2c.ReadReq_mshr_misses::cpu1.data 6288 # number of ReadReq MSHR misses 350system.l2c.ReadReq_mshr_misses::total 25244 # number of ReadReq MSHR misses 351system.l2c.UpgradeReq_mshr_misses::cpu0.data 5689 # number of UpgradeReq MSHR misses 352system.l2c.UpgradeReq_mshr_misses::cpu1.data 4311 # number of UpgradeReq MSHR misses 353system.l2c.UpgradeReq_mshr_misses::total 10000 # number of UpgradeReq MSHR misses 354system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 783 # number of SCUpgradeReq MSHR misses 355system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 578 # number of SCUpgradeReq MSHR misses 356system.l2c.SCUpgradeReq_mshr_misses::total 1361 # number of SCUpgradeReq MSHR misses 357system.l2c.ReadExReq_mshr_misses::cpu0.data 63204 # number of ReadExReq MSHR misses 358system.l2c.ReadExReq_mshr_misses::cpu1.data 76879 # number of ReadExReq MSHR misses 359system.l2c.ReadExReq_mshr_misses::total 140083 # number of ReadExReq MSHR misses 360system.l2c.demand_mshr_misses::cpu0.dtb.walker 10 # number of demand (read+write) MSHR misses 361system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 362system.l2c.demand_mshr_misses::cpu0.inst 6052 # number of demand (read+write) MSHR misses 363system.l2c.demand_mshr_misses::cpu0.data 69480 # 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number of overall MSHR misses 376system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 400000 # number of ReadReq MSHR miss cycles 377system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 88000 # number of ReadReq MSHR miss cycles 378system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 248870498 # number of ReadReq MSHR miss cycles 379system.l2c.ReadReq_mshr_miss_latency::cpu0.data 253621500 # number of ReadReq MSHR miss cycles 380system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 733500 # number of ReadReq MSHR miss cycles 381system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 270526499 # number of ReadReq MSHR miss cycles 382system.l2c.ReadReq_mshr_miss_latency::cpu1.data 254062500 # number of ReadReq MSHR miss cycles 383system.l2c.ReadReq_mshr_miss_latency::total 1028302497 # number of ReadReq MSHR miss cycles 384system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 227738000 # number of UpgradeReq MSHR miss cycles 385system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 172587000 # number of UpgradeReq MSHR miss cycles 386system.l2c.UpgradeReq_mshr_miss_latency::total 400325000 # number of UpgradeReq MSHR miss cycles 387system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31335500 # number of SCUpgradeReq MSHR miss cycles 388system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23126500 # number of SCUpgradeReq MSHR miss cycles 389system.l2c.SCUpgradeReq_mshr_miss_latency::total 54462000 # number of SCUpgradeReq MSHR miss cycles 390system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2597363499 # number of ReadExReq MSHR miss cycles 391system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3131334993 # number of ReadExReq MSHR miss cycles 392system.l2c.ReadExReq_mshr_miss_latency::total 5728698492 # number of ReadExReq MSHR miss cycles 393system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 400000 # number of demand (read+write) MSHR miss cycles 394system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 88000 # number of demand (read+write) MSHR miss cycles 395system.l2c.demand_mshr_miss_latency::cpu0.inst 248870498 # number of demand (read+write) MSHR miss cycles 396system.l2c.demand_mshr_miss_latency::cpu0.data 2850984999 # number of demand (read+write) MSHR miss cycles 397system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 733500 # number of demand (read+write) MSHR miss cycles 398system.l2c.demand_mshr_miss_latency::cpu1.inst 270526499 # number of demand (read+write) MSHR miss cycles 399system.l2c.demand_mshr_miss_latency::cpu1.data 3385397493 # number of demand (read+write) MSHR miss cycles 400system.l2c.demand_mshr_miss_latency::total 6757000989 # number of demand (read+write) MSHR miss cycles 401system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 400000 # number of overall MSHR miss cycles 402system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 88000 # number of overall MSHR miss cycles 403system.l2c.overall_mshr_miss_latency::cpu0.inst 248870498 # number of overall MSHR miss cycles 404system.l2c.overall_mshr_miss_latency::cpu0.data 2850984999 # number of overall MSHR miss cycles 405system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 733500 # number of overall MSHR miss cycles 406system.l2c.overall_mshr_miss_latency::cpu1.inst 270526499 # number of overall MSHR miss cycles 407system.l2c.overall_mshr_miss_latency::cpu1.data 3385397493 # number of overall MSHR miss cycles 408system.l2c.overall_mshr_miss_latency::total 6757000989 # number of overall MSHR miss cycles 409system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5579000 # number of ReadReq MSHR uncacheable cycles 410system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12326324000 # number of ReadReq MSHR uncacheable cycles 411system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2170500 # number of ReadReq MSHR uncacheable cycles 412system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154700128500 # number of ReadReq MSHR uncacheable cycles 413system.l2c.ReadReq_mshr_uncacheable_latency::total 167034202000 # number of ReadReq MSHR uncacheable cycles 414system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1153610999 # number of WriteReq MSHR uncacheable cycles 415system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31143367304 # number of WriteReq MSHR uncacheable cycles 416system.l2c.WriteReq_mshr_uncacheable_latency::total 32296978303 # number of WriteReq MSHR uncacheable cycles 417system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5579000 # number of overall MSHR uncacheable cycles 418system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13479934999 # number of overall MSHR uncacheable cycles 419system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2170500 # number of overall MSHR uncacheable cycles 420system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185843495804 # number of overall MSHR uncacheable cycles 421system.l2c.overall_mshr_uncacheable_latency::total 199331180303 # number of overall MSHR uncacheable cycles 422system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000183 # mshr miss rate for ReadReq accesses 423system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000348 # mshr miss rate for ReadReq accesses 424system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014866 # mshr miss rate for ReadReq accesses 425system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036447 # mshr miss rate for ReadReq accesses 426system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000230 # mshr miss rate for ReadReq accesses 427system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010592 # mshr miss rate for ReadReq accesses 428system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030192 # mshr miss rate for ReadReq accesses 429system.l2c.ReadReq_mshr_miss_rate::total 0.016228 # mshr miss rate for ReadReq accesses 430system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.844692 # mshr miss rate for UpgradeReq accesses 431system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.841171 # mshr miss rate for UpgradeReq accesses 432system.l2c.UpgradeReq_mshr_miss_rate::total 0.843170 # mshr miss rate for UpgradeReq accesses 433system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.793313 # mshr miss rate for SCUpgradeReq accesses 434system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.771696 # mshr miss rate for SCUpgradeReq accesses 435system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.783986 # mshr miss rate for SCUpgradeReq accesses 436system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566781 # mshr miss rate for ReadExReq accesses 437system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.565982 # mshr miss rate for ReadExReq accesses 438system.l2c.ReadExReq_mshr_miss_rate::total 0.566342 # mshr miss rate for ReadExReq accesses 439system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000183 # mshr miss rate for demand accesses 440system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000348 # mshr miss rate for demand accesses 441system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014866 # mshr miss rate for demand accesses 442system.l2c.demand_mshr_miss_rate::cpu0.data 0.244899 # mshr miss rate for demand accesses 443system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000230 # mshr miss rate for demand accesses 444system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010592 # mshr miss rate for demand accesses 445system.l2c.demand_mshr_miss_rate::cpu1.data 0.241696 # mshr miss rate for demand accesses 446system.l2c.demand_mshr_miss_rate::total 0.091700 # mshr miss rate for demand accesses 447system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000183 # mshr miss rate for overall accesses 448system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000348 # mshr miss rate for overall accesses 449system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014866 # mshr miss rate for overall accesses 450system.l2c.overall_mshr_miss_rate::cpu0.data 0.244899 # mshr miss rate for overall accesses 451system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000230 # mshr miss rate for overall accesses 452system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010592 # mshr miss rate for overall accesses 453system.l2c.overall_mshr_miss_rate::cpu1.data 0.241696 # mshr miss rate for overall accesses 454system.l2c.overall_mshr_miss_rate::total 0.091700 # mshr miss rate for overall accesses 455system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency 456system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average ReadReq mshr miss latency 457system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average ReadReq mshr miss latency 458system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40411.328872 # average ReadReq mshr miss latency 459system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average ReadReq mshr miss latency 460system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average ReadReq mshr miss latency 461system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40404.341603 # average ReadReq mshr miss latency 462system.l2c.ReadReq_avg_mshr_miss_latency::total 40734.530859 # average ReadReq mshr miss latency 463system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.288451 # average UpgradeReq mshr miss latency 464system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40034.098817 # average UpgradeReq mshr miss latency 465system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.500000 # average UpgradeReq mshr miss latency 466system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40019.795658 # average SCUpgradeReq mshr miss latency 467system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40011.245675 # average SCUpgradeReq mshr miss latency 468system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40016.164585 # average SCUpgradeReq mshr miss latency 469system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41094.922774 # average ReadExReq mshr miss latency 470system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40730.693596 # average ReadExReq mshr miss latency 471system.l2c.ReadExReq_avg_mshr_miss_latency::total 40895.030032 # average ReadExReq mshr miss latency 472system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 473system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency 474system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average overall mshr miss latency 475system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41033.175000 # average overall mshr miss latency 476system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency 477system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average overall mshr miss latency 478system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40706.019130 # average overall mshr miss latency 479system.l2c.demand_avg_mshr_miss_latency::total 40870.523199 # average overall mshr miss latency 480system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 481system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency 482system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average overall mshr miss latency 483system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41033.175000 # average overall mshr miss latency 484system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency 485system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average overall mshr miss latency 486system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40706.019130 # average overall mshr miss latency 487system.l2c.overall_avg_mshr_miss_latency::total 40870.523199 # average overall mshr miss latency 488system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 489system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 490system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 491system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 492system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 493system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 494system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 495system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 496system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 497system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 498system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 499system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 500system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 501system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 502system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 503system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 504system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 505system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 506system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 507system.cf0.dma_write_txs 0 # Number of DMA write transactions. 508system.cpu0.dtb.inst_hits 0 # ITB inst hits 509system.cpu0.dtb.inst_misses 0 # ITB inst misses 510system.cpu0.dtb.read_hits 9087709 # DTB read hits 511system.cpu0.dtb.read_misses 37707 # DTB read misses 512system.cpu0.dtb.write_hits 5292852 # DTB write hits 513system.cpu0.dtb.write_misses 6797 # DTB write misses 514system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 515system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 516system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 517system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 518system.cpu0.dtb.flush_entries 2252 # Number of entries that have been flushed from TLB 519system.cpu0.dtb.align_faults 1465 # Number of TLB faults due to alignment restrictions 520system.cpu0.dtb.prefetch_faults 402 # Number of TLB faults due to prefetch 521system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 522system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions 523system.cpu0.dtb.read_accesses 9125416 # DTB read accesses 524system.cpu0.dtb.write_accesses 5299649 # DTB write accesses 525system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 526system.cpu0.dtb.hits 14380561 # DTB hits 527system.cpu0.dtb.misses 44504 # DTB misses 528system.cpu0.dtb.accesses 14425065 # DTB accesses 529system.cpu0.itb.inst_hits 4426363 # ITB inst hits 530system.cpu0.itb.inst_misses 5791 # ITB inst misses 531system.cpu0.itb.read_hits 0 # DTB read hits 532system.cpu0.itb.read_misses 0 # DTB read misses 533system.cpu0.itb.write_hits 0 # DTB write hits 534system.cpu0.itb.write_misses 0 # DTB write misses 535system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 536system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 537system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 538system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 539system.cpu0.itb.flush_entries 1409 # Number of entries that have been flushed from TLB 540system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 541system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 542system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 543system.cpu0.itb.perms_faults 1661 # Number of TLB faults due to permissions restrictions 544system.cpu0.itb.read_accesses 0 # DTB read accesses 545system.cpu0.itb.write_accesses 0 # DTB write accesses 546system.cpu0.itb.inst_accesses 4432154 # ITB inst accesses 547system.cpu0.itb.hits 4426363 # DTB hits 548system.cpu0.itb.misses 5791 # DTB misses 549system.cpu0.itb.accesses 4432154 # DTB accesses 550system.cpu0.numCycles 73540541 # number of cpu cycles simulated 551system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 552system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 553system.cpu0.BPredUnit.lookups 6354280 # Number of BP lookups 554system.cpu0.BPredUnit.condPredicted 4863798 # Number of conditional branches predicted 555system.cpu0.BPredUnit.condIncorrect 316535 # Number of conditional branches incorrect 556system.cpu0.BPredUnit.BTBLookups 4079773 # Number of BTB lookups 557system.cpu0.BPredUnit.BTBHits 3047693 # Number of BTB hits 558system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 559system.cpu0.BPredUnit.usedRAS 700511 # Number of times the RAS was used to get a target. 560system.cpu0.BPredUnit.RASInCorrect 30883 # Number of incorrect RAS predictions. 561system.cpu0.fetch.icacheStallCycles 12981968 # Number of cycles fetch is stalled on an Icache miss 562system.cpu0.fetch.Insts 33339853 # Number of instructions fetch has processed 563system.cpu0.fetch.Branches 6354280 # Number of branches that fetch encountered 564system.cpu0.fetch.predictedBranches 3748204 # Number of branches that fetch has predicted taken 565system.cpu0.fetch.Cycles 7827899 # Number of cycles fetch has run and was not squashing or blocked 566system.cpu0.fetch.SquashCycles 1608255 # Number of cycles fetch has spent squashing 567system.cpu0.fetch.TlbCycles 88516 # Number of cycles fetch has spent waiting for tlb 568system.cpu0.fetch.BlockedCycles 23525864 # Number of cycles fetch has spent blocked 569system.cpu0.fetch.MiscStallCycles 5853 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 570system.cpu0.fetch.PendingTrapStallCycles 77679 # Number of stall cycles due to pending traps 571system.cpu0.fetch.PendingQuiesceStallCycles 91798 # Number of stall cycles due to pending quiesce instructions 572system.cpu0.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR 573system.cpu0.fetch.CacheLines 4424514 # Number of cache lines fetched 574system.cpu0.fetch.IcacheSquashes 175463 # Number of outstanding Icache misses that were squashed 575system.cpu0.fetch.ItlbSquashes 2818 # Number of outstanding ITLB misses that were squashed 576system.cpu0.fetch.rateDist::samples 45755598 # Number of instructions fetched each cycle (Total) 577system.cpu0.fetch.rateDist::mean 0.940589 # Number of instructions fetched each cycle (Total) 578system.cpu0.fetch.rateDist::stdev 2.320885 # Number of instructions fetched each cycle (Total) 579system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 580system.cpu0.fetch.rateDist::0 37936221 82.91% 82.91% # Number of instructions fetched each cycle (Total) 581system.cpu0.fetch.rateDist::1 625086 1.37% 84.28% # Number of instructions fetched each cycle (Total) 582system.cpu0.fetch.rateDist::2 819758 1.79% 86.07% # Number of instructions fetched each cycle (Total) 583system.cpu0.fetch.rateDist::3 695394 1.52% 87.59% # Number of instructions fetched each cycle (Total) 584system.cpu0.fetch.rateDist::4 800497 1.75% 89.34% # Number of instructions fetched each cycle (Total) 585system.cpu0.fetch.rateDist::5 578636 1.26% 90.60% # Number of instructions fetched each cycle (Total) 586system.cpu0.fetch.rateDist::6 719119 1.57% 92.17% # Number of instructions fetched each cycle (Total) 587system.cpu0.fetch.rateDist::7 370554 0.81% 92.98% # Number of instructions fetched each cycle (Total) 588system.cpu0.fetch.rateDist::8 3210333 7.02% 100.00% # Number of instructions fetched each cycle (Total) 589system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 590system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 591system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 592system.cpu0.fetch.rateDist::total 45755598 # Number of instructions fetched each cycle (Total) 593system.cpu0.fetch.branchRate 0.086405 # Number of branch fetches per cycle 594system.cpu0.fetch.rate 0.453353 # Number of inst fetches per cycle 595system.cpu0.decode.IdleCycles 13479181 # Number of cycles decode is idle 596system.cpu0.decode.BlockedCycles 23559009 # Number of cycles decode is blocked 597system.cpu0.decode.RunCycles 7020718 # Number of cycles decode is running 598system.cpu0.decode.UnblockCycles 606128 # Number of cycles decode is unblocking 599system.cpu0.decode.SquashCycles 1090562 # Number of cycles decode is squashing 600system.cpu0.decode.BranchResolved 996028 # Number of times decode resolved a branch 601system.cpu0.decode.BranchMispred 66487 # Number of times decode detected a branch misprediction 602system.cpu0.decode.DecodedInsts 41577642 # Number of instructions handled by decode 603system.cpu0.decode.SquashedInsts 218603 # Number of squashed instructions handled by decode 604system.cpu0.rename.SquashCycles 1090562 # Number of cycles rename is squashing 605system.cpu0.rename.IdleCycles 14092626 # Number of cycles rename is idle 606system.cpu0.rename.BlockCycles 6784553 # Number of cycles rename is blocking 607system.cpu0.rename.serializeStallCycles 14469405 # count of cycles rename stalled for serializing inst 608system.cpu0.rename.RunCycles 6963849 # Number of cycles rename is running 609system.cpu0.rename.UnblockCycles 2354603 # Number of cycles rename is unblocking 610system.cpu0.rename.RenamedInsts 40318960 # Number of instructions processed by rename 611system.cpu0.rename.ROBFullEvents 2633 # Number of times rename has blocked due to ROB full 612system.cpu0.rename.IQFullEvents 472928 # Number of times rename has blocked due to IQ full 613system.cpu0.rename.LSQFullEvents 1334672 # Number of times rename has blocked due to LSQ full 614system.cpu0.rename.FullRegisterEvents 351 # Number of times there has been no free registers 615system.cpu0.rename.RenamedOperands 40667832 # Number of destination operands rename has renamed 616system.cpu0.rename.RenameLookups 182121697 # Number of register rename lookups that rename has made 617system.cpu0.rename.int_rename_lookups 182086780 # Number of integer rename lookups 618system.cpu0.rename.fp_rename_lookups 34917 # Number of floating rename lookups 619system.cpu0.rename.CommittedMaps 31702592 # Number of HB maps that are committed 620system.cpu0.rename.UndoneMaps 8965239 # Number of HB maps that are undone due to squashing 621system.cpu0.rename.serializingInsts 463825 # count of serializing insts renamed 622system.cpu0.rename.tempSerializingInsts 419023 # count of temporary serializing insts renamed 623system.cpu0.rename.skidInsts 5696158 # count of insts added to the skid buffer 624system.cpu0.memDep0.insertedLoads 7936117 # Number of loads inserted to the mem dependence unit. 625system.cpu0.memDep0.insertedStores 5894118 # Number of stores inserted to the mem dependence unit. 626system.cpu0.memDep0.conflictingLoads 1139492 # Number of conflicting loads. 627system.cpu0.memDep0.conflictingStores 1233570 # Number of conflicting stores. 628system.cpu0.iq.iqInstsAdded 38069002 # Number of instructions added to the IQ (excludes non-spec) 629system.cpu0.iq.iqNonSpecInstsAdded 950684 # Number of non-speculative instructions added to the IQ 630system.cpu0.iq.iqInstsIssued 38295497 # Number of instructions issued 631system.cpu0.iq.iqSquashedInstsIssued 94171 # Number of squashed instructions issued 632system.cpu0.iq.iqSquashedInstsExamined 6802670 # Number of squashed instructions iterated over during squash; mainly for profiling 633system.cpu0.iq.iqSquashedOperandsExamined 14391567 # Number of squashed operands that are examined and possibly removed from graph 634system.cpu0.iq.iqSquashedNonSpecRemoved 261548 # Number of squashed non-spec instructions that were removed 635system.cpu0.iq.issued_per_cycle::samples 45755598 # Number of insts issued each cycle 636system.cpu0.iq.issued_per_cycle::mean 0.836958 # Number of insts issued each cycle 637system.cpu0.iq.issued_per_cycle::stdev 1.462966 # Number of insts issued each cycle 638system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 639system.cpu0.iq.issued_per_cycle::0 29855724 65.25% 65.25% # Number of insts issued each cycle 640system.cpu0.iq.issued_per_cycle::1 6336412 13.85% 79.10% # Number of insts issued each cycle 641system.cpu0.iq.issued_per_cycle::2 3245721 7.09% 86.19% # Number of insts issued each cycle 642system.cpu0.iq.issued_per_cycle::3 2523061 5.51% 91.71% # Number of insts issued each cycle 643system.cpu0.iq.issued_per_cycle::4 2111675 4.62% 96.32% # Number of insts issued each cycle 644system.cpu0.iq.issued_per_cycle::5 936021 2.05% 98.37% # Number of insts issued each cycle 645system.cpu0.iq.issued_per_cycle::6 511535 1.12% 99.49% # Number of insts issued each cycle 646system.cpu0.iq.issued_per_cycle::7 181147 0.40% 99.88% # Number of insts issued each cycle 647system.cpu0.iq.issued_per_cycle::8 54302 0.12% 100.00% # Number of insts issued each cycle 648system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 649system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 650system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 651system.cpu0.iq.issued_per_cycle::total 45755598 # Number of insts issued each cycle 652system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 653system.cpu0.iq.fu_full::IntAlu 27761 2.59% 2.59% # attempts to use FU when none available 654system.cpu0.iq.fu_full::IntMult 464 0.04% 2.63% # attempts to use FU when none available 655system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available 656system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available 657system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available 658system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available 659system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available 660system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available 661system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available 662system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available 663system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available 664system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available 665system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available 666system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available 667system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available 668system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available 669system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available 670system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available 671system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available 672system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available 673system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available 674system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available 675system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available 676system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available 677system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available 678system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available 679system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available 680system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available 681system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available 682system.cpu0.iq.fu_full::MemRead 835942 77.99% 80.62% # attempts to use FU when none available 683system.cpu0.iq.fu_full::MemWrite 207752 19.38% 100.00% # attempts to use FU when none available 684system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 685system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 686system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued 687system.cpu0.iq.FU_type_0::IntAlu 23003680 60.07% 60.21% # Type of FU issued 688system.cpu0.iq.FU_type_0::IntMult 50163 0.13% 60.34% # Type of FU issued 689system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued 690system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued 691system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued 692system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued 693system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued 694system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued 695system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued 696system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued 697system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued 698system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.34% # Type of FU issued 699system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued 700system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued 701system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 60.34% # Type of FU issued 702system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued 703system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued 704system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 60.34% # Type of FU issued 705system.cpu0.iq.FU_type_0::SimdShiftAcc 10 0.00% 60.34% # Type of FU issued 706system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued 707system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued 708system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued 709system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued 710system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued 711system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued 712system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.34% # Type of FU issued 713system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued 714system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 60.34% # Type of FU issued 715system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued 716system.cpu0.iq.FU_type_0::MemRead 9567598 24.98% 85.32% # Type of FU issued 717system.cpu0.iq.FU_type_0::MemWrite 5620993 14.68% 100.00% # Type of FU issued 718system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 719system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 720system.cpu0.iq.FU_type_0::total 38295497 # Type of FU issued 721system.cpu0.iq.rate 0.520740 # Inst issue rate 722system.cpu0.iq.fu_busy_cnt 1071919 # FU busy when requested 723system.cpu0.iq.fu_busy_rate 0.027991 # FU busy rate (busy events/executed inst) 724system.cpu0.iq.int_inst_queue_reads 123548516 # Number of integer instruction queue reads 725system.cpu0.iq.int_inst_queue_writes 45830842 # Number of integer instruction queue writes 726system.cpu0.iq.int_inst_queue_wakeup_accesses 35351164 # Number of integer instruction queue wakeup accesses 727system.cpu0.iq.fp_inst_queue_reads 8368 # Number of floating instruction queue reads 728system.cpu0.iq.fp_inst_queue_writes 4748 # Number of floating instruction queue writes 729system.cpu0.iq.fp_inst_queue_wakeup_accesses 3893 # Number of floating instruction queue wakeup accesses 730system.cpu0.iq.int_alu_accesses 39310727 # Number of integer alu accesses 731system.cpu0.iq.fp_alu_accesses 4345 # Number of floating point alu accesses 732system.cpu0.iew.lsq.thread0.forwLoads 327037 # Number of loads that had data forwarded from stores 733system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 734system.cpu0.iew.lsq.thread0.squashedLoads 1508258 # Number of loads squashed 735system.cpu0.iew.lsq.thread0.ignoredResponses 3980 # Number of memory responses ignored because the instruction is squashed 736system.cpu0.iew.lsq.thread0.memOrderViolation 13847 # Number of memory ordering violations 737system.cpu0.iew.lsq.thread0.squashedStores 614652 # Number of stores squashed 738system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 739system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 740system.cpu0.iew.lsq.thread0.rescheduledLoads 2149655 # Number of loads that were rescheduled 741system.cpu0.iew.lsq.thread0.cacheBlocked 5288 # Number of times an access to memory failed due to the cache being blocked 742system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 743system.cpu0.iew.iewSquashCycles 1090562 # Number of cycles IEW is squashing 744system.cpu0.iew.iewBlockCycles 4675196 # Number of cycles IEW is blocking 745system.cpu0.iew.iewUnblockCycles 127491 # Number of cycles IEW is unblocking 746system.cpu0.iew.iewDispatchedInsts 39158193 # Number of instructions dispatched to IQ 747system.cpu0.iew.iewDispSquashedInsts 88903 # Number of squashed instructions skipped by dispatch 748system.cpu0.iew.iewDispLoadInsts 7936117 # Number of dispatched load instructions 749system.cpu0.iew.iewDispStoreInsts 5894118 # Number of dispatched store instructions 750system.cpu0.iew.iewDispNonSpecInsts 617815 # Number of dispatched non-speculative instructions 751system.cpu0.iew.iewIQFullEvents 49276 # Number of times the IQ has become full, causing a stall 752system.cpu0.iew.iewLSQFullEvents 17780 # Number of times the LSQ has become full, causing a stall 753system.cpu0.iew.memOrderViolationEvents 13847 # Number of memory order violations 754system.cpu0.iew.predictedTakenIncorrect 160769 # Number of branches that were predicted taken incorrectly 755system.cpu0.iew.predictedNotTakenIncorrect 144529 # Number of branches that were predicted not taken incorrectly 756system.cpu0.iew.branchMispredicts 305298 # Number of branch mispredicts detected at execute 757system.cpu0.iew.iewExecutedInsts 37872918 # Number of executed instructions 758system.cpu0.iew.iewExecLoadInsts 9405503 # Number of load instructions executed 759system.cpu0.iew.iewExecSquashedInsts 422579 # Number of squashed instructions skipped in execute 760system.cpu0.iew.exec_swp 0 # number of swp insts executed 761system.cpu0.iew.exec_nop 138507 # number of nop insts executed 762system.cpu0.iew.exec_refs 14971538 # number of memory reference insts executed 763system.cpu0.iew.exec_branches 5077620 # Number of branches executed 764system.cpu0.iew.exec_stores 5566035 # Number of stores executed 765system.cpu0.iew.exec_rate 0.514994 # Inst execution rate 766system.cpu0.iew.wb_sent 37653849 # cumulative count of insts sent to commit 767system.cpu0.iew.wb_count 35355057 # cumulative count of insts written-back 768system.cpu0.iew.wb_producers 18700837 # num instructions producing a value 769system.cpu0.iew.wb_consumers 35658328 # num instructions consuming a value 770system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 771system.cpu0.iew.wb_rate 0.480756 # insts written-back per cycle 772system.cpu0.iew.wb_fanout 0.524445 # average fanout of values written-back 773system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.617033 # Number of seconds simulated 4sim_ticks 2617033170500 # Number of ticks simulated 5final_tick 2617033170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 88113 # Simulator instruction rate (inst/s) 8host_op_rate 113402 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3655705591 # Simulator tick rate (ticks/s) 10host_mem_usage 391256 # Number of bytes of host memory used 11host_seconds 715.88 # Real time elapsed on the host 12sim_insts 63077791 # Number of instructions simulated 13sim_ops 81181923 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 395840 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4357428 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 425152 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 5244336 # Number of bytes read from this memory 22system.physmem.bytes_read::total 131535204 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 395840 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 425152 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 820992 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4255104 # Number of bytes written to this memory 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory 29system.physmem.bytes_written::total 7284240 # Number of bytes written to this memory 30system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 6185 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 68157 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 6643 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 81969 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 15301800 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 66486 # Number of write requests responded to by this memory 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 823770 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 46277796 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.dtb.walker 245 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 151255 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 1665026 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.dtb.walker 440 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.inst 162456 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 2003924 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 50261191 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 151255 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 162456 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 313711 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 1625927 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 6496 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 1150974 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 2783396 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 1625927 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 46277796 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.dtb.walker 245 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.inst 151255 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 1671522 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.dtb.walker 440 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.inst 162456 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 3154898 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 53044587 # Total bandwidth to/from this memory (bytes/s) 69system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory 70system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory 71system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 72system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory 73system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory 74system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 75system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory 76system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory 77system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 78system.realview.nvmem.bw_read::cpu0.inst 24 # Total read bandwidth from this memory (bytes/s) 79system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) 80system.realview.nvmem.bw_read::total 171 # Total read bandwidth from this memory (bytes/s) 81system.realview.nvmem.bw_inst_read::cpu0.inst 24 # Instruction read bandwidth from this memory (bytes/s) 82system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) 83system.realview.nvmem.bw_inst_read::total 171 # Instruction read bandwidth from this memory (bytes/s) 84system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s) 85system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) 86system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s) 87system.l2c.replacements 72594 # number of replacements 88system.l2c.tagsinuse 53100.305923 # Cycle average of tags in use 89system.l2c.total_refs 1970249 # Total number of references to valid blocks. 90system.l2c.sampled_refs 137794 # Sample count of references to valid blocks. 91system.l2c.avg_refs 14.298511 # Average number of references to valid blocks. 92system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 93system.l2c.occ_blocks::writebacks 37791.704596 # Average occupied blocks per requestor 94system.l2c.occ_blocks::cpu0.dtb.walker 4.504480 # Average occupied blocks per requestor 95system.l2c.occ_blocks::cpu0.itb.walker 0.004560 # Average occupied blocks per requestor 96system.l2c.occ_blocks::cpu0.inst 4202.741800 # Average occupied blocks per requestor 97system.l2c.occ_blocks::cpu0.data 2939.105076 # Average occupied blocks per requestor 98system.l2c.occ_blocks::cpu1.dtb.walker 13.484693 # Average occupied blocks per requestor 99system.l2c.occ_blocks::cpu1.inst 4025.080355 # Average occupied blocks per requestor 100system.l2c.occ_blocks::cpu1.data 4123.680364 # Average occupied blocks per requestor 101system.l2c.occ_percent::writebacks 0.576656 # Average percentage of cache occupancy 102system.l2c.occ_percent::cpu0.dtb.walker 0.000069 # Average percentage of cache occupancy 103system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 104system.l2c.occ_percent::cpu0.inst 0.064129 # Average percentage of cache occupancy 105system.l2c.occ_percent::cpu0.data 0.044847 # Average percentage of cache occupancy 106system.l2c.occ_percent::cpu1.dtb.walker 0.000206 # Average percentage of cache occupancy 107system.l2c.occ_percent::cpu1.inst 0.061418 # Average percentage of cache occupancy 108system.l2c.occ_percent::cpu1.data 0.062922 # Average percentage of cache occupancy 109system.l2c.occ_percent::total 0.810246 # Average percentage of cache occupancy 110system.l2c.ReadReq_hits::cpu0.dtb.walker 54561 # number of ReadReq hits 111system.l2c.ReadReq_hits::cpu0.itb.walker 5750 # number of ReadReq hits 112system.l2c.ReadReq_hits::cpu0.inst 401038 # number of ReadReq hits 113system.l2c.ReadReq_hits::cpu0.data 165879 # number of ReadReq hits 114system.l2c.ReadReq_hits::cpu1.dtb.walker 78192 # number of ReadReq hits 115system.l2c.ReadReq_hits::cpu1.itb.walker 6577 # number of ReadReq hits 116system.l2c.ReadReq_hits::cpu1.inst 616294 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu1.data 201951 # number of ReadReq hits 118system.l2c.ReadReq_hits::total 1530242 # number of ReadReq hits 119system.l2c.Writeback_hits::writebacks 584193 # number of Writeback hits 120system.l2c.Writeback_hits::total 584193 # number of Writeback hits 121system.l2c.UpgradeReq_hits::cpu0.data 1046 # number of UpgradeReq hits 122system.l2c.UpgradeReq_hits::cpu1.data 814 # number of UpgradeReq hits 123system.l2c.UpgradeReq_hits::total 1860 # number of UpgradeReq hits 124system.l2c.SCUpgradeReq_hits::cpu0.data 204 # number of SCUpgradeReq hits 125system.l2c.SCUpgradeReq_hits::cpu1.data 171 # number of SCUpgradeReq hits 126system.l2c.SCUpgradeReq_hits::total 375 # number of SCUpgradeReq hits 127system.l2c.ReadExReq_hits::cpu0.data 48310 # number of ReadExReq hits 128system.l2c.ReadExReq_hits::cpu1.data 58954 # number of ReadExReq hits 129system.l2c.ReadExReq_hits::total 107264 # number of ReadExReq hits 130system.l2c.demand_hits::cpu0.dtb.walker 54561 # number of demand (read+write) hits 131system.l2c.demand_hits::cpu0.itb.walker 5750 # number of demand (read+write) hits 132system.l2c.demand_hits::cpu0.inst 401038 # number of demand (read+write) hits 133system.l2c.demand_hits::cpu0.data 214189 # number of demand (read+write) hits 134system.l2c.demand_hits::cpu1.dtb.walker 78192 # number of demand (read+write) hits 135system.l2c.demand_hits::cpu1.itb.walker 6577 # number of demand (read+write) hits 136system.l2c.demand_hits::cpu1.inst 616294 # number of demand (read+write) hits 137system.l2c.demand_hits::cpu1.data 260905 # number of demand (read+write) hits 138system.l2c.demand_hits::total 1637506 # number of demand (read+write) hits 139system.l2c.overall_hits::cpu0.dtb.walker 54561 # number of overall hits 140system.l2c.overall_hits::cpu0.itb.walker 5750 # number of overall hits 141system.l2c.overall_hits::cpu0.inst 401038 # number of overall hits 142system.l2c.overall_hits::cpu0.data 214189 # number of overall hits 143system.l2c.overall_hits::cpu1.dtb.walker 78192 # number of overall hits 144system.l2c.overall_hits::cpu1.itb.walker 6577 # number of overall hits 145system.l2c.overall_hits::cpu1.inst 616294 # number of overall hits 146system.l2c.overall_hits::cpu1.data 260905 # number of overall hits 147system.l2c.overall_hits::total 1637506 # number of overall hits 148system.l2c.ReadReq_misses::cpu0.dtb.walker 10 # number of ReadReq misses 149system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 150system.l2c.ReadReq_misses::cpu0.inst 6056 # number of ReadReq misses 151system.l2c.ReadReq_misses::cpu0.data 6316 # number of ReadReq misses 152system.l2c.ReadReq_misses::cpu1.dtb.walker 18 # number of ReadReq misses 153system.l2c.ReadReq_misses::cpu1.inst 6605 # number of ReadReq misses 154system.l2c.ReadReq_misses::cpu1.data 6313 # number of ReadReq misses 155system.l2c.ReadReq_misses::total 25320 # number of ReadReq misses 156system.l2c.UpgradeReq_misses::cpu0.data 5689 # number of UpgradeReq misses 157system.l2c.UpgradeReq_misses::cpu1.data 4311 # number of UpgradeReq misses 158system.l2c.UpgradeReq_misses::total 10000 # number of UpgradeReq misses 159system.l2c.SCUpgradeReq_misses::cpu0.data 783 # number of SCUpgradeReq misses 160system.l2c.SCUpgradeReq_misses::cpu1.data 578 # number of SCUpgradeReq misses 161system.l2c.SCUpgradeReq_misses::total 1361 # number of SCUpgradeReq misses 162system.l2c.ReadExReq_misses::cpu0.data 63204 # number of ReadExReq misses 163system.l2c.ReadExReq_misses::cpu1.data 76879 # number of ReadExReq misses 164system.l2c.ReadExReq_misses::total 140083 # number of ReadExReq misses 165system.l2c.demand_misses::cpu0.dtb.walker 10 # number of demand (read+write) misses 166system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 167system.l2c.demand_misses::cpu0.inst 6056 # number of demand (read+write) misses 168system.l2c.demand_misses::cpu0.data 69520 # number of demand (read+write) misses 169system.l2c.demand_misses::cpu1.dtb.walker 18 # number of demand (read+write) misses 170system.l2c.demand_misses::cpu1.inst 6605 # number of demand (read+write) misses 171system.l2c.demand_misses::cpu1.data 83192 # number of demand (read+write) misses 172system.l2c.demand_misses::total 165403 # number of demand (read+write) misses 173system.l2c.overall_misses::cpu0.dtb.walker 10 # number of overall misses 174system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 175system.l2c.overall_misses::cpu0.inst 6056 # number of overall misses 176system.l2c.overall_misses::cpu0.data 69520 # number of overall misses 177system.l2c.overall_misses::cpu1.dtb.walker 18 # number of overall misses 178system.l2c.overall_misses::cpu1.inst 6605 # number of overall misses 179system.l2c.overall_misses::cpu1.data 83192 # number of overall misses 180system.l2c.overall_misses::total 165403 # number of overall misses 181system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 522500 # number of ReadReq miss cycles 182system.l2c.ReadReq_miss_latency::cpu0.itb.walker 112500 # number of ReadReq miss cycles 183system.l2c.ReadReq_miss_latency::cpu0.inst 322936498 # number of ReadReq miss cycles 184system.l2c.ReadReq_miss_latency::cpu0.data 331707998 # number of ReadReq miss cycles 185system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 952500 # number of ReadReq miss cycles 186system.l2c.ReadReq_miss_latency::cpu1.inst 351349999 # number of ReadReq miss cycles 187system.l2c.ReadReq_miss_latency::cpu1.data 331785500 # number of ReadReq miss cycles 188system.l2c.ReadReq_miss_latency::total 1339367495 # number of ReadReq miss cycles 189system.l2c.UpgradeReq_miss_latency::cpu0.data 20090481 # number of UpgradeReq miss cycles 190system.l2c.UpgradeReq_miss_latency::cpu1.data 27401499 # number of UpgradeReq miss cycles 191system.l2c.UpgradeReq_miss_latency::total 47491980 # number of UpgradeReq miss cycles 192system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1617500 # number of SCUpgradeReq miss cycles 193system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6565000 # number of SCUpgradeReq miss cycles 194system.l2c.SCUpgradeReq_miss_latency::total 8182500 # number of SCUpgradeReq miss cycles 195system.l2c.ReadExReq_miss_latency::cpu0.data 3365710489 # number of ReadExReq miss cycles 196system.l2c.ReadExReq_miss_latency::cpu1.data 4075887489 # number of ReadExReq miss cycles 197system.l2c.ReadExReq_miss_latency::total 7441597978 # number of ReadExReq miss cycles 198system.l2c.demand_miss_latency::cpu0.dtb.walker 522500 # number of demand (read+write) miss cycles 199system.l2c.demand_miss_latency::cpu0.itb.walker 112500 # number of demand (read+write) miss cycles 200system.l2c.demand_miss_latency::cpu0.inst 322936498 # number of demand (read+write) miss cycles 201system.l2c.demand_miss_latency::cpu0.data 3697418487 # number of demand (read+write) miss cycles 202system.l2c.demand_miss_latency::cpu1.dtb.walker 952500 # number of demand (read+write) miss cycles 203system.l2c.demand_miss_latency::cpu1.inst 351349999 # number of demand (read+write) miss cycles 204system.l2c.demand_miss_latency::cpu1.data 4407672989 # number of demand (read+write) miss cycles 205system.l2c.demand_miss_latency::total 8780965473 # number of demand (read+write) miss cycles 206system.l2c.overall_miss_latency::cpu0.dtb.walker 522500 # number of overall miss cycles 207system.l2c.overall_miss_latency::cpu0.itb.walker 112500 # number of overall miss cycles 208system.l2c.overall_miss_latency::cpu0.inst 322936498 # number of overall miss cycles 209system.l2c.overall_miss_latency::cpu0.data 3697418487 # number of overall miss cycles 210system.l2c.overall_miss_latency::cpu1.dtb.walker 952500 # number of overall miss cycles 211system.l2c.overall_miss_latency::cpu1.inst 351349999 # number of overall miss cycles 212system.l2c.overall_miss_latency::cpu1.data 4407672989 # number of overall miss cycles 213system.l2c.overall_miss_latency::total 8780965473 # number of overall miss cycles 214system.l2c.ReadReq_accesses::cpu0.dtb.walker 54571 # number of ReadReq accesses(hits+misses) 215system.l2c.ReadReq_accesses::cpu0.itb.walker 5752 # number of ReadReq accesses(hits+misses) 216system.l2c.ReadReq_accesses::cpu0.inst 407094 # number of ReadReq accesses(hits+misses) 217system.l2c.ReadReq_accesses::cpu0.data 172195 # number of ReadReq accesses(hits+misses) 218system.l2c.ReadReq_accesses::cpu1.dtb.walker 78210 # number of ReadReq accesses(hits+misses) 219system.l2c.ReadReq_accesses::cpu1.itb.walker 6577 # number of ReadReq accesses(hits+misses) 220system.l2c.ReadReq_accesses::cpu1.inst 622899 # number of ReadReq accesses(hits+misses) 221system.l2c.ReadReq_accesses::cpu1.data 208264 # number of ReadReq accesses(hits+misses) 222system.l2c.ReadReq_accesses::total 1555562 # number of ReadReq accesses(hits+misses) 223system.l2c.Writeback_accesses::writebacks 584193 # number of Writeback accesses(hits+misses) 224system.l2c.Writeback_accesses::total 584193 # number of Writeback accesses(hits+misses) 225system.l2c.UpgradeReq_accesses::cpu0.data 6735 # number of UpgradeReq accesses(hits+misses) 226system.l2c.UpgradeReq_accesses::cpu1.data 5125 # number of UpgradeReq accesses(hits+misses) 227system.l2c.UpgradeReq_accesses::total 11860 # number of UpgradeReq accesses(hits+misses) 228system.l2c.SCUpgradeReq_accesses::cpu0.data 987 # number of SCUpgradeReq accesses(hits+misses) 229system.l2c.SCUpgradeReq_accesses::cpu1.data 749 # number of SCUpgradeReq accesses(hits+misses) 230system.l2c.SCUpgradeReq_accesses::total 1736 # number of SCUpgradeReq accesses(hits+misses) 231system.l2c.ReadExReq_accesses::cpu0.data 111514 # number of ReadExReq accesses(hits+misses) 232system.l2c.ReadExReq_accesses::cpu1.data 135833 # number of ReadExReq accesses(hits+misses) 233system.l2c.ReadExReq_accesses::total 247347 # number of ReadExReq accesses(hits+misses) 234system.l2c.demand_accesses::cpu0.dtb.walker 54571 # number of demand (read+write) accesses 235system.l2c.demand_accesses::cpu0.itb.walker 5752 # number of demand (read+write) accesses 236system.l2c.demand_accesses::cpu0.inst 407094 # number of demand (read+write) accesses 237system.l2c.demand_accesses::cpu0.data 283709 # number of demand (read+write) accesses 238system.l2c.demand_accesses::cpu1.dtb.walker 78210 # number of demand (read+write) accesses 239system.l2c.demand_accesses::cpu1.itb.walker 6577 # number of demand (read+write) accesses 240system.l2c.demand_accesses::cpu1.inst 622899 # number of demand (read+write) accesses 241system.l2c.demand_accesses::cpu1.data 344097 # number of demand (read+write) accesses 242system.l2c.demand_accesses::total 1802909 # number of demand (read+write) accesses 243system.l2c.overall_accesses::cpu0.dtb.walker 54571 # number of overall (read+write) accesses 244system.l2c.overall_accesses::cpu0.itb.walker 5752 # number of overall (read+write) accesses 245system.l2c.overall_accesses::cpu0.inst 407094 # number of overall (read+write) accesses 246system.l2c.overall_accesses::cpu0.data 283709 # number of overall (read+write) accesses 247system.l2c.overall_accesses::cpu1.dtb.walker 78210 # number of overall (read+write) accesses 248system.l2c.overall_accesses::cpu1.itb.walker 6577 # number of overall (read+write) accesses 249system.l2c.overall_accesses::cpu1.inst 622899 # number of overall (read+write) accesses 250system.l2c.overall_accesses::cpu1.data 344097 # number of overall (read+write) accesses 251system.l2c.overall_accesses::total 1802909 # number of overall (read+write) accesses 252system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000183 # miss rate for ReadReq accesses 253system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000348 # miss rate for ReadReq accesses 254system.l2c.ReadReq_miss_rate::cpu0.inst 0.014876 # miss rate for ReadReq accesses 255system.l2c.ReadReq_miss_rate::cpu0.data 0.036679 # miss rate for ReadReq accesses 256system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000230 # miss rate for ReadReq accesses 257system.l2c.ReadReq_miss_rate::cpu1.inst 0.010604 # miss rate for ReadReq accesses 258system.l2c.ReadReq_miss_rate::cpu1.data 0.030312 # miss rate for ReadReq accesses 259system.l2c.ReadReq_miss_rate::total 0.016277 # miss rate for ReadReq accesses 260system.l2c.UpgradeReq_miss_rate::cpu0.data 0.844692 # miss rate for UpgradeReq accesses 261system.l2c.UpgradeReq_miss_rate::cpu1.data 0.841171 # miss rate for UpgradeReq accesses 262system.l2c.UpgradeReq_miss_rate::total 0.843170 # miss rate for UpgradeReq accesses 263system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.793313 # miss rate for SCUpgradeReq accesses 264system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.771696 # miss rate for SCUpgradeReq accesses 265system.l2c.SCUpgradeReq_miss_rate::total 0.783986 # miss rate for SCUpgradeReq accesses 266system.l2c.ReadExReq_miss_rate::cpu0.data 0.566781 # miss rate for ReadExReq accesses 267system.l2c.ReadExReq_miss_rate::cpu1.data 0.565982 # miss rate for ReadExReq accesses 268system.l2c.ReadExReq_miss_rate::total 0.566342 # miss rate for ReadExReq accesses 269system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000183 # miss rate for demand accesses 270system.l2c.demand_miss_rate::cpu0.itb.walker 0.000348 # miss rate for demand accesses 271system.l2c.demand_miss_rate::cpu0.inst 0.014876 # miss rate for demand accesses 272system.l2c.demand_miss_rate::cpu0.data 0.245040 # miss rate for demand accesses 273system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000230 # miss rate for demand accesses 274system.l2c.demand_miss_rate::cpu1.inst 0.010604 # miss rate for demand accesses 275system.l2c.demand_miss_rate::cpu1.data 0.241769 # miss rate for demand accesses 276system.l2c.demand_miss_rate::total 0.091742 # miss rate for demand accesses 277system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000183 # miss rate for overall accesses 278system.l2c.overall_miss_rate::cpu0.itb.walker 0.000348 # miss rate for overall accesses 279system.l2c.overall_miss_rate::cpu0.inst 0.014876 # miss rate for overall accesses 280system.l2c.overall_miss_rate::cpu0.data 0.245040 # miss rate for overall accesses 281system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000230 # miss rate for overall accesses 282system.l2c.overall_miss_rate::cpu1.inst 0.010604 # miss rate for overall accesses 283system.l2c.overall_miss_rate::cpu1.data 0.241769 # miss rate for overall accesses 284system.l2c.overall_miss_rate::total 0.091742 # miss rate for overall accesses 285system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52250 # average ReadReq miss latency 286system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 56250 # average ReadReq miss latency 287system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53325.049207 # average ReadReq miss latency 288system.l2c.ReadReq_avg_miss_latency::cpu0.data 52518.682394 # average ReadReq miss latency 289system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52916.666667 # average ReadReq miss latency 290system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53194.549432 # average ReadReq miss latency 291system.l2c.ReadReq_avg_miss_latency::cpu1.data 52555.916363 # average ReadReq miss latency 292system.l2c.ReadReq_avg_miss_latency::total 52897.610387 # average ReadReq miss latency 293system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3531.460889 # average UpgradeReq miss latency 294system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6356.181628 # average UpgradeReq miss latency 295system.l2c.UpgradeReq_avg_miss_latency::total 4749.198000 # average UpgradeReq miss latency 296system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2065.772669 # average SCUpgradeReq miss latency 297system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11358.131488 # average SCUpgradeReq miss latency 298system.l2c.SCUpgradeReq_avg_miss_latency::total 6012.123439 # average SCUpgradeReq miss latency 299system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53251.542450 # average ReadExReq miss latency 300system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53016.916050 # average ReadExReq miss latency 301system.l2c.ReadExReq_avg_miss_latency::total 53122.777054 # average ReadExReq miss latency 302system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52250 # average overall miss latency 303system.l2c.demand_avg_miss_latency::cpu0.itb.walker 56250 # average overall miss latency 304system.l2c.demand_avg_miss_latency::cpu0.inst 53325.049207 # average overall miss latency 305system.l2c.demand_avg_miss_latency::cpu0.data 53184.960975 # average overall miss latency 306system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52916.666667 # average overall miss latency 307system.l2c.demand_avg_miss_latency::cpu1.inst 53194.549432 # average overall miss latency 308system.l2c.demand_avg_miss_latency::cpu1.data 52981.933227 # average overall miss latency 309system.l2c.demand_avg_miss_latency::total 53088.308392 # average overall miss latency 310system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52250 # average overall miss latency 311system.l2c.overall_avg_miss_latency::cpu0.itb.walker 56250 # average overall miss latency 312system.l2c.overall_avg_miss_latency::cpu0.inst 53325.049207 # average overall miss latency 313system.l2c.overall_avg_miss_latency::cpu0.data 53184.960975 # average overall miss latency 314system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52916.666667 # average overall miss latency 315system.l2c.overall_avg_miss_latency::cpu1.inst 53194.549432 # average overall miss latency 316system.l2c.overall_avg_miss_latency::cpu1.data 52981.933227 # average overall miss latency 317system.l2c.overall_avg_miss_latency::total 53088.308392 # average overall miss latency 318system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 319system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 320system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 321system.l2c.blocked::no_targets 0 # number of cycles access was blocked 322system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 323system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 324system.l2c.fast_writes 0 # number of fast writes performed 325system.l2c.cache_copies 0 # number of cache copies performed 326system.l2c.writebacks::writebacks 66486 # number of writebacks 327system.l2c.writebacks::total 66486 # number of writebacks 328system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits 329system.l2c.ReadReq_mshr_hits::cpu0.data 40 # number of ReadReq MSHR hits 330system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits 331system.l2c.ReadReq_mshr_hits::cpu1.data 25 # number of ReadReq MSHR hits 332system.l2c.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits 333system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits 334system.l2c.demand_mshr_hits::cpu0.data 40 # number of demand (read+write) MSHR hits 335system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits 336system.l2c.demand_mshr_hits::cpu1.data 25 # number of demand (read+write) MSHR hits 337system.l2c.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits 338system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits 339system.l2c.overall_mshr_hits::cpu0.data 40 # number of overall MSHR hits 340system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits 341system.l2c.overall_mshr_hits::cpu1.data 25 # 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number of SCUpgradeReq MSHR misses 355system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 578 # number of SCUpgradeReq MSHR misses 356system.l2c.SCUpgradeReq_mshr_misses::total 1361 # number of SCUpgradeReq MSHR misses 357system.l2c.ReadExReq_mshr_misses::cpu0.data 63204 # number of ReadExReq MSHR misses 358system.l2c.ReadExReq_mshr_misses::cpu1.data 76879 # number of ReadExReq MSHR misses 359system.l2c.ReadExReq_mshr_misses::total 140083 # number of ReadExReq MSHR misses 360system.l2c.demand_mshr_misses::cpu0.dtb.walker 10 # number of demand (read+write) MSHR misses 361system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 362system.l2c.demand_mshr_misses::cpu0.inst 6052 # number of demand (read+write) MSHR misses 363system.l2c.demand_mshr_misses::cpu0.data 69480 # number of demand (read+write) MSHR misses 364system.l2c.demand_mshr_misses::cpu1.dtb.walker 18 # number of demand (read+write) MSHR misses 365system.l2c.demand_mshr_misses::cpu1.inst 6598 # number of demand (read+write) MSHR misses 366system.l2c.demand_mshr_misses::cpu1.data 83167 # number of demand (read+write) MSHR misses 367system.l2c.demand_mshr_misses::total 165327 # number of demand (read+write) MSHR misses 368system.l2c.overall_mshr_misses::cpu0.dtb.walker 10 # number of overall MSHR misses 369system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 370system.l2c.overall_mshr_misses::cpu0.inst 6052 # number of overall MSHR misses 371system.l2c.overall_mshr_misses::cpu0.data 69480 # number of overall MSHR misses 372system.l2c.overall_mshr_misses::cpu1.dtb.walker 18 # number of overall MSHR misses 373system.l2c.overall_mshr_misses::cpu1.inst 6598 # number of overall MSHR misses 374system.l2c.overall_mshr_misses::cpu1.data 83167 # number of overall MSHR misses 375system.l2c.overall_mshr_misses::total 165327 # number of overall MSHR misses 376system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 400000 # number of ReadReq MSHR miss cycles 377system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 88000 # number of ReadReq MSHR miss cycles 378system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 248870498 # number of ReadReq MSHR miss cycles 379system.l2c.ReadReq_mshr_miss_latency::cpu0.data 253621500 # number of ReadReq MSHR miss cycles 380system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 733500 # number of ReadReq MSHR miss cycles 381system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 270526499 # number of ReadReq MSHR miss cycles 382system.l2c.ReadReq_mshr_miss_latency::cpu1.data 254062500 # number of ReadReq MSHR miss cycles 383system.l2c.ReadReq_mshr_miss_latency::total 1028302497 # number of ReadReq MSHR miss cycles 384system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 227738000 # number of UpgradeReq MSHR miss cycles 385system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 172587000 # number of UpgradeReq MSHR miss cycles 386system.l2c.UpgradeReq_mshr_miss_latency::total 400325000 # number of UpgradeReq MSHR miss cycles 387system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31335500 # number of SCUpgradeReq MSHR miss cycles 388system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23126500 # number of SCUpgradeReq MSHR miss cycles 389system.l2c.SCUpgradeReq_mshr_miss_latency::total 54462000 # number of SCUpgradeReq MSHR miss cycles 390system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2597363499 # number of ReadExReq MSHR miss cycles 391system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3131334993 # number of ReadExReq MSHR miss cycles 392system.l2c.ReadExReq_mshr_miss_latency::total 5728698492 # number of ReadExReq MSHR miss cycles 393system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 400000 # number of demand (read+write) MSHR miss cycles 394system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 88000 # number of demand (read+write) MSHR miss cycles 395system.l2c.demand_mshr_miss_latency::cpu0.inst 248870498 # number of demand (read+write) MSHR miss cycles 396system.l2c.demand_mshr_miss_latency::cpu0.data 2850984999 # number of demand (read+write) MSHR miss cycles 397system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 733500 # number of demand (read+write) MSHR miss cycles 398system.l2c.demand_mshr_miss_latency::cpu1.inst 270526499 # number of demand (read+write) MSHR miss cycles 399system.l2c.demand_mshr_miss_latency::cpu1.data 3385397493 # number of demand (read+write) MSHR miss cycles 400system.l2c.demand_mshr_miss_latency::total 6757000989 # number of demand (read+write) MSHR miss cycles 401system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 400000 # number of overall MSHR miss cycles 402system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 88000 # number of overall MSHR miss cycles 403system.l2c.overall_mshr_miss_latency::cpu0.inst 248870498 # number of overall MSHR miss cycles 404system.l2c.overall_mshr_miss_latency::cpu0.data 2850984999 # number of overall MSHR miss cycles 405system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 733500 # number of overall MSHR miss cycles 406system.l2c.overall_mshr_miss_latency::cpu1.inst 270526499 # number of overall MSHR miss cycles 407system.l2c.overall_mshr_miss_latency::cpu1.data 3385397493 # number of overall MSHR miss cycles 408system.l2c.overall_mshr_miss_latency::total 6757000989 # number of overall MSHR miss cycles 409system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5579000 # number of ReadReq MSHR uncacheable cycles 410system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12326324000 # number of ReadReq MSHR uncacheable cycles 411system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2170500 # number of ReadReq MSHR uncacheable cycles 412system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154700128500 # number of ReadReq MSHR uncacheable cycles 413system.l2c.ReadReq_mshr_uncacheable_latency::total 167034202000 # number of ReadReq MSHR uncacheable cycles 414system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1153610999 # number of WriteReq MSHR uncacheable cycles 415system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31143367304 # number of WriteReq MSHR uncacheable cycles 416system.l2c.WriteReq_mshr_uncacheable_latency::total 32296978303 # number of WriteReq MSHR uncacheable cycles 417system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5579000 # number of overall MSHR uncacheable cycles 418system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13479934999 # number of overall MSHR uncacheable cycles 419system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2170500 # number of overall MSHR uncacheable cycles 420system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185843495804 # number of overall MSHR uncacheable cycles 421system.l2c.overall_mshr_uncacheable_latency::total 199331180303 # number of overall MSHR uncacheable cycles 422system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000183 # mshr miss rate for ReadReq accesses 423system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000348 # mshr miss rate for ReadReq accesses 424system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014866 # mshr miss rate for ReadReq accesses 425system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036447 # mshr miss rate for ReadReq accesses 426system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000230 # mshr miss rate for ReadReq accesses 427system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010592 # mshr miss rate for ReadReq accesses 428system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030192 # mshr miss rate for ReadReq accesses 429system.l2c.ReadReq_mshr_miss_rate::total 0.016228 # mshr miss rate for ReadReq accesses 430system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.844692 # mshr miss rate for UpgradeReq accesses 431system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.841171 # mshr miss rate for UpgradeReq accesses 432system.l2c.UpgradeReq_mshr_miss_rate::total 0.843170 # mshr miss rate for UpgradeReq accesses 433system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.793313 # mshr miss rate for SCUpgradeReq accesses 434system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.771696 # mshr miss rate for SCUpgradeReq accesses 435system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.783986 # mshr miss rate for SCUpgradeReq accesses 436system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566781 # mshr miss rate for ReadExReq accesses 437system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.565982 # mshr miss rate for ReadExReq accesses 438system.l2c.ReadExReq_mshr_miss_rate::total 0.566342 # mshr miss rate for ReadExReq accesses 439system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000183 # mshr miss rate for demand accesses 440system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000348 # mshr miss rate for demand accesses 441system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014866 # mshr miss rate for demand accesses 442system.l2c.demand_mshr_miss_rate::cpu0.data 0.244899 # mshr miss rate for demand accesses 443system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000230 # mshr miss rate for demand accesses 444system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010592 # mshr miss rate for demand accesses 445system.l2c.demand_mshr_miss_rate::cpu1.data 0.241696 # mshr miss rate for demand accesses 446system.l2c.demand_mshr_miss_rate::total 0.091700 # mshr miss rate for demand accesses 447system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000183 # mshr miss rate for overall accesses 448system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000348 # mshr miss rate for overall accesses 449system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014866 # mshr miss rate for overall accesses 450system.l2c.overall_mshr_miss_rate::cpu0.data 0.244899 # mshr miss rate for overall accesses 451system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000230 # mshr miss rate for overall accesses 452system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010592 # mshr miss rate for overall accesses 453system.l2c.overall_mshr_miss_rate::cpu1.data 0.241696 # mshr miss rate for overall accesses 454system.l2c.overall_mshr_miss_rate::total 0.091700 # mshr miss rate for overall accesses 455system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency 456system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average ReadReq mshr miss latency 457system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average ReadReq mshr miss latency 458system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40411.328872 # average ReadReq mshr miss latency 459system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average ReadReq mshr miss latency 460system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average ReadReq mshr miss latency 461system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40404.341603 # average ReadReq mshr miss latency 462system.l2c.ReadReq_avg_mshr_miss_latency::total 40734.530859 # average ReadReq mshr miss latency 463system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.288451 # average UpgradeReq mshr miss latency 464system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40034.098817 # average UpgradeReq mshr miss latency 465system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.500000 # average UpgradeReq mshr miss latency 466system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40019.795658 # average SCUpgradeReq mshr miss latency 467system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40011.245675 # average SCUpgradeReq mshr miss latency 468system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40016.164585 # average SCUpgradeReq mshr miss latency 469system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41094.922774 # average ReadExReq mshr miss latency 470system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40730.693596 # average ReadExReq mshr miss latency 471system.l2c.ReadExReq_avg_mshr_miss_latency::total 40895.030032 # average ReadExReq mshr miss latency 472system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 473system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency 474system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average overall mshr miss latency 475system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41033.175000 # average overall mshr miss latency 476system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency 477system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average overall mshr miss latency 478system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40706.019130 # average overall mshr miss latency 479system.l2c.demand_avg_mshr_miss_latency::total 40870.523199 # average overall mshr miss latency 480system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 481system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency 482system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average overall mshr miss latency 483system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41033.175000 # average overall mshr miss latency 484system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency 485system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average overall mshr miss latency 486system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40706.019130 # average overall mshr miss latency 487system.l2c.overall_avg_mshr_miss_latency::total 40870.523199 # average overall mshr miss latency 488system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 489system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 490system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 491system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 492system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 493system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 494system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 495system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 496system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 497system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 498system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 499system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 500system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 501system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 502system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 503system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 504system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 505system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 506system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 507system.cf0.dma_write_txs 0 # Number of DMA write transactions. 508system.cpu0.dtb.inst_hits 0 # ITB inst hits 509system.cpu0.dtb.inst_misses 0 # ITB inst misses 510system.cpu0.dtb.read_hits 9087709 # DTB read hits 511system.cpu0.dtb.read_misses 37707 # DTB read misses 512system.cpu0.dtb.write_hits 5292852 # DTB write hits 513system.cpu0.dtb.write_misses 6797 # DTB write misses 514system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 515system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 516system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 517system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 518system.cpu0.dtb.flush_entries 2252 # Number of entries that have been flushed from TLB 519system.cpu0.dtb.align_faults 1465 # Number of TLB faults due to alignment restrictions 520system.cpu0.dtb.prefetch_faults 402 # Number of TLB faults due to prefetch 521system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 522system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions 523system.cpu0.dtb.read_accesses 9125416 # DTB read accesses 524system.cpu0.dtb.write_accesses 5299649 # DTB write accesses 525system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 526system.cpu0.dtb.hits 14380561 # DTB hits 527system.cpu0.dtb.misses 44504 # DTB misses 528system.cpu0.dtb.accesses 14425065 # DTB accesses 529system.cpu0.itb.inst_hits 4426363 # ITB inst hits 530system.cpu0.itb.inst_misses 5791 # ITB inst misses 531system.cpu0.itb.read_hits 0 # DTB read hits 532system.cpu0.itb.read_misses 0 # DTB read misses 533system.cpu0.itb.write_hits 0 # DTB write hits 534system.cpu0.itb.write_misses 0 # DTB write misses 535system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 536system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 537system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 538system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 539system.cpu0.itb.flush_entries 1409 # Number of entries that have been flushed from TLB 540system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 541system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 542system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 543system.cpu0.itb.perms_faults 1661 # Number of TLB faults due to permissions restrictions 544system.cpu0.itb.read_accesses 0 # DTB read accesses 545system.cpu0.itb.write_accesses 0 # DTB write accesses 546system.cpu0.itb.inst_accesses 4432154 # ITB inst accesses 547system.cpu0.itb.hits 4426363 # DTB hits 548system.cpu0.itb.misses 5791 # DTB misses 549system.cpu0.itb.accesses 4432154 # DTB accesses 550system.cpu0.numCycles 73540541 # number of cpu cycles simulated 551system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 552system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 553system.cpu0.BPredUnit.lookups 6354280 # Number of BP lookups 554system.cpu0.BPredUnit.condPredicted 4863798 # Number of conditional branches predicted 555system.cpu0.BPredUnit.condIncorrect 316535 # Number of conditional branches incorrect 556system.cpu0.BPredUnit.BTBLookups 4079773 # Number of BTB lookups 557system.cpu0.BPredUnit.BTBHits 3047693 # Number of BTB hits 558system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 559system.cpu0.BPredUnit.usedRAS 700511 # Number of times the RAS was used to get a target. 560system.cpu0.BPredUnit.RASInCorrect 30883 # Number of incorrect RAS predictions. 561system.cpu0.fetch.icacheStallCycles 12981968 # Number of cycles fetch is stalled on an Icache miss 562system.cpu0.fetch.Insts 33339853 # Number of instructions fetch has processed 563system.cpu0.fetch.Branches 6354280 # Number of branches that fetch encountered 564system.cpu0.fetch.predictedBranches 3748204 # Number of branches that fetch has predicted taken 565system.cpu0.fetch.Cycles 7827899 # Number of cycles fetch has run and was not squashing or blocked 566system.cpu0.fetch.SquashCycles 1608255 # Number of cycles fetch has spent squashing 567system.cpu0.fetch.TlbCycles 88516 # Number of cycles fetch has spent waiting for tlb 568system.cpu0.fetch.BlockedCycles 23525864 # Number of cycles fetch has spent blocked 569system.cpu0.fetch.MiscStallCycles 5853 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 570system.cpu0.fetch.PendingTrapStallCycles 77679 # Number of stall cycles due to pending traps 571system.cpu0.fetch.PendingQuiesceStallCycles 91798 # Number of stall cycles due to pending quiesce instructions 572system.cpu0.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR 573system.cpu0.fetch.CacheLines 4424514 # Number of cache lines fetched 574system.cpu0.fetch.IcacheSquashes 175463 # Number of outstanding Icache misses that were squashed 575system.cpu0.fetch.ItlbSquashes 2818 # Number of outstanding ITLB misses that were squashed 576system.cpu0.fetch.rateDist::samples 45755598 # Number of instructions fetched each cycle (Total) 577system.cpu0.fetch.rateDist::mean 0.940589 # Number of instructions fetched each cycle (Total) 578system.cpu0.fetch.rateDist::stdev 2.320885 # Number of instructions fetched each cycle (Total) 579system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 580system.cpu0.fetch.rateDist::0 37936221 82.91% 82.91% # Number of instructions fetched each cycle (Total) 581system.cpu0.fetch.rateDist::1 625086 1.37% 84.28% # Number of instructions fetched each cycle (Total) 582system.cpu0.fetch.rateDist::2 819758 1.79% 86.07% # Number of instructions fetched each cycle (Total) 583system.cpu0.fetch.rateDist::3 695394 1.52% 87.59% # Number of instructions fetched each cycle (Total) 584system.cpu0.fetch.rateDist::4 800497 1.75% 89.34% # Number of instructions fetched each cycle (Total) 585system.cpu0.fetch.rateDist::5 578636 1.26% 90.60% # Number of instructions fetched each cycle (Total) 586system.cpu0.fetch.rateDist::6 719119 1.57% 92.17% # Number of instructions fetched each cycle (Total) 587system.cpu0.fetch.rateDist::7 370554 0.81% 92.98% # Number of instructions fetched each cycle (Total) 588system.cpu0.fetch.rateDist::8 3210333 7.02% 100.00% # Number of instructions fetched each cycle (Total) 589system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 590system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 591system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 592system.cpu0.fetch.rateDist::total 45755598 # Number of instructions fetched each cycle (Total) 593system.cpu0.fetch.branchRate 0.086405 # Number of branch fetches per cycle 594system.cpu0.fetch.rate 0.453353 # Number of inst fetches per cycle 595system.cpu0.decode.IdleCycles 13479181 # Number of cycles decode is idle 596system.cpu0.decode.BlockedCycles 23559009 # Number of cycles decode is blocked 597system.cpu0.decode.RunCycles 7020718 # Number of cycles decode is running 598system.cpu0.decode.UnblockCycles 606128 # Number of cycles decode is unblocking 599system.cpu0.decode.SquashCycles 1090562 # Number of cycles decode is squashing 600system.cpu0.decode.BranchResolved 996028 # Number of times decode resolved a branch 601system.cpu0.decode.BranchMispred 66487 # Number of times decode detected a branch misprediction 602system.cpu0.decode.DecodedInsts 41577642 # Number of instructions handled by decode 603system.cpu0.decode.SquashedInsts 218603 # Number of squashed instructions handled by decode 604system.cpu0.rename.SquashCycles 1090562 # Number of cycles rename is squashing 605system.cpu0.rename.IdleCycles 14092626 # Number of cycles rename is idle 606system.cpu0.rename.BlockCycles 6784553 # Number of cycles rename is blocking 607system.cpu0.rename.serializeStallCycles 14469405 # count of cycles rename stalled for serializing inst 608system.cpu0.rename.RunCycles 6963849 # Number of cycles rename is running 609system.cpu0.rename.UnblockCycles 2354603 # Number of cycles rename is unblocking 610system.cpu0.rename.RenamedInsts 40318960 # Number of instructions processed by rename 611system.cpu0.rename.ROBFullEvents 2633 # Number of times rename has blocked due to ROB full 612system.cpu0.rename.IQFullEvents 472928 # Number of times rename has blocked due to IQ full 613system.cpu0.rename.LSQFullEvents 1334672 # Number of times rename has blocked due to LSQ full 614system.cpu0.rename.FullRegisterEvents 351 # Number of times there has been no free registers 615system.cpu0.rename.RenamedOperands 40667832 # Number of destination operands rename has renamed 616system.cpu0.rename.RenameLookups 182121697 # Number of register rename lookups that rename has made 617system.cpu0.rename.int_rename_lookups 182086780 # Number of integer rename lookups 618system.cpu0.rename.fp_rename_lookups 34917 # Number of floating rename lookups 619system.cpu0.rename.CommittedMaps 31702592 # Number of HB maps that are committed 620system.cpu0.rename.UndoneMaps 8965239 # Number of HB maps that are undone due to squashing 621system.cpu0.rename.serializingInsts 463825 # count of serializing insts renamed 622system.cpu0.rename.tempSerializingInsts 419023 # count of temporary serializing insts renamed 623system.cpu0.rename.skidInsts 5696158 # count of insts added to the skid buffer 624system.cpu0.memDep0.insertedLoads 7936117 # Number of loads inserted to the mem dependence unit. 625system.cpu0.memDep0.insertedStores 5894118 # Number of stores inserted to the mem dependence unit. 626system.cpu0.memDep0.conflictingLoads 1139492 # Number of conflicting loads. 627system.cpu0.memDep0.conflictingStores 1233570 # Number of conflicting stores. 628system.cpu0.iq.iqInstsAdded 38069002 # Number of instructions added to the IQ (excludes non-spec) 629system.cpu0.iq.iqNonSpecInstsAdded 950684 # Number of non-speculative instructions added to the IQ 630system.cpu0.iq.iqInstsIssued 38295497 # Number of instructions issued 631system.cpu0.iq.iqSquashedInstsIssued 94171 # Number of squashed instructions issued 632system.cpu0.iq.iqSquashedInstsExamined 6802670 # Number of squashed instructions iterated over during squash; mainly for profiling 633system.cpu0.iq.iqSquashedOperandsExamined 14391567 # Number of squashed operands that are examined and possibly removed from graph 634system.cpu0.iq.iqSquashedNonSpecRemoved 261548 # Number of squashed non-spec instructions that were removed 635system.cpu0.iq.issued_per_cycle::samples 45755598 # Number of insts issued each cycle 636system.cpu0.iq.issued_per_cycle::mean 0.836958 # Number of insts issued each cycle 637system.cpu0.iq.issued_per_cycle::stdev 1.462966 # Number of insts issued each cycle 638system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 639system.cpu0.iq.issued_per_cycle::0 29855724 65.25% 65.25% # Number of insts issued each cycle 640system.cpu0.iq.issued_per_cycle::1 6336412 13.85% 79.10% # Number of insts issued each cycle 641system.cpu0.iq.issued_per_cycle::2 3245721 7.09% 86.19% # Number of insts issued each cycle 642system.cpu0.iq.issued_per_cycle::3 2523061 5.51% 91.71% # Number of insts issued each cycle 643system.cpu0.iq.issued_per_cycle::4 2111675 4.62% 96.32% # Number of insts issued each cycle 644system.cpu0.iq.issued_per_cycle::5 936021 2.05% 98.37% # Number of insts issued each cycle 645system.cpu0.iq.issued_per_cycle::6 511535 1.12% 99.49% # Number of insts issued each cycle 646system.cpu0.iq.issued_per_cycle::7 181147 0.40% 99.88% # Number of insts issued each cycle 647system.cpu0.iq.issued_per_cycle::8 54302 0.12% 100.00% # Number of insts issued each cycle 648system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 649system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 650system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 651system.cpu0.iq.issued_per_cycle::total 45755598 # Number of insts issued each cycle 652system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 653system.cpu0.iq.fu_full::IntAlu 27761 2.59% 2.59% # attempts to use FU when none available 654system.cpu0.iq.fu_full::IntMult 464 0.04% 2.63% # attempts to use FU when none available 655system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available 656system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available 657system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available 658system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available 659system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available 660system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available 661system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available 662system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available 663system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available 664system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available 665system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available 666system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available 667system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available 668system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available 669system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available 670system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available 671system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available 672system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available 673system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available 674system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available 675system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available 676system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available 677system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available 678system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available 679system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available 680system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available 681system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available 682system.cpu0.iq.fu_full::MemRead 835942 77.99% 80.62% # attempts to use FU when none available 683system.cpu0.iq.fu_full::MemWrite 207752 19.38% 100.00% # attempts to use FU when none available 684system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 685system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 686system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued 687system.cpu0.iq.FU_type_0::IntAlu 23003680 60.07% 60.21% # Type of FU issued 688system.cpu0.iq.FU_type_0::IntMult 50163 0.13% 60.34% # Type of FU issued 689system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued 690system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued 691system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued 692system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued 693system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued 694system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued 695system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued 696system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued 697system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued 698system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.34% # Type of FU issued 699system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued 700system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued 701system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 60.34% # Type of FU issued 702system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued 703system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued 704system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 60.34% # Type of FU issued 705system.cpu0.iq.FU_type_0::SimdShiftAcc 10 0.00% 60.34% # Type of FU issued 706system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued 707system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued 708system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued 709system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued 710system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued 711system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued 712system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.34% # Type of FU issued 713system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued 714system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 60.34% # Type of FU issued 715system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued 716system.cpu0.iq.FU_type_0::MemRead 9567598 24.98% 85.32% # Type of FU issued 717system.cpu0.iq.FU_type_0::MemWrite 5620993 14.68% 100.00% # Type of FU issued 718system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 719system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 720system.cpu0.iq.FU_type_0::total 38295497 # Type of FU issued 721system.cpu0.iq.rate 0.520740 # Inst issue rate 722system.cpu0.iq.fu_busy_cnt 1071919 # FU busy when requested 723system.cpu0.iq.fu_busy_rate 0.027991 # FU busy rate (busy events/executed inst) 724system.cpu0.iq.int_inst_queue_reads 123548516 # Number of integer instruction queue reads 725system.cpu0.iq.int_inst_queue_writes 45830842 # Number of integer instruction queue writes 726system.cpu0.iq.int_inst_queue_wakeup_accesses 35351164 # Number of integer instruction queue wakeup accesses 727system.cpu0.iq.fp_inst_queue_reads 8368 # Number of floating instruction queue reads 728system.cpu0.iq.fp_inst_queue_writes 4748 # Number of floating instruction queue writes 729system.cpu0.iq.fp_inst_queue_wakeup_accesses 3893 # Number of floating instruction queue wakeup accesses 730system.cpu0.iq.int_alu_accesses 39310727 # Number of integer alu accesses 731system.cpu0.iq.fp_alu_accesses 4345 # Number of floating point alu accesses 732system.cpu0.iew.lsq.thread0.forwLoads 327037 # Number of loads that had data forwarded from stores 733system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 734system.cpu0.iew.lsq.thread0.squashedLoads 1508258 # Number of loads squashed 735system.cpu0.iew.lsq.thread0.ignoredResponses 3980 # Number of memory responses ignored because the instruction is squashed 736system.cpu0.iew.lsq.thread0.memOrderViolation 13847 # Number of memory ordering violations 737system.cpu0.iew.lsq.thread0.squashedStores 614652 # Number of stores squashed 738system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 739system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 740system.cpu0.iew.lsq.thread0.rescheduledLoads 2149655 # Number of loads that were rescheduled 741system.cpu0.iew.lsq.thread0.cacheBlocked 5288 # Number of times an access to memory failed due to the cache being blocked 742system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 743system.cpu0.iew.iewSquashCycles 1090562 # Number of cycles IEW is squashing 744system.cpu0.iew.iewBlockCycles 4675196 # Number of cycles IEW is blocking 745system.cpu0.iew.iewUnblockCycles 127491 # Number of cycles IEW is unblocking 746system.cpu0.iew.iewDispatchedInsts 39158193 # Number of instructions dispatched to IQ 747system.cpu0.iew.iewDispSquashedInsts 88903 # Number of squashed instructions skipped by dispatch 748system.cpu0.iew.iewDispLoadInsts 7936117 # Number of dispatched load instructions 749system.cpu0.iew.iewDispStoreInsts 5894118 # Number of dispatched store instructions 750system.cpu0.iew.iewDispNonSpecInsts 617815 # Number of dispatched non-speculative instructions 751system.cpu0.iew.iewIQFullEvents 49276 # Number of times the IQ has become full, causing a stall 752system.cpu0.iew.iewLSQFullEvents 17780 # Number of times the LSQ has become full, causing a stall 753system.cpu0.iew.memOrderViolationEvents 13847 # Number of memory order violations 754system.cpu0.iew.predictedTakenIncorrect 160769 # Number of branches that were predicted taken incorrectly 755system.cpu0.iew.predictedNotTakenIncorrect 144529 # Number of branches that were predicted not taken incorrectly 756system.cpu0.iew.branchMispredicts 305298 # Number of branch mispredicts detected at execute 757system.cpu0.iew.iewExecutedInsts 37872918 # Number of executed instructions 758system.cpu0.iew.iewExecLoadInsts 9405503 # Number of load instructions executed 759system.cpu0.iew.iewExecSquashedInsts 422579 # Number of squashed instructions skipped in execute 760system.cpu0.iew.exec_swp 0 # number of swp insts executed 761system.cpu0.iew.exec_nop 138507 # number of nop insts executed 762system.cpu0.iew.exec_refs 14971538 # number of memory reference insts executed 763system.cpu0.iew.exec_branches 5077620 # Number of branches executed 764system.cpu0.iew.exec_stores 5566035 # Number of stores executed 765system.cpu0.iew.exec_rate 0.514994 # Inst execution rate 766system.cpu0.iew.wb_sent 37653849 # cumulative count of insts sent to commit 767system.cpu0.iew.wb_count 35355057 # cumulative count of insts written-back 768system.cpu0.iew.wb_producers 18700837 # num instructions producing a value 769system.cpu0.iew.wb_consumers 35658328 # num instructions consuming a value 770system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 771system.cpu0.iew.wb_rate 0.480756 # insts written-back per cycle 772system.cpu0.iew.wb_fanout 0.524445 # average fanout of values written-back 773system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
774system.cpu0.commit.commitCommittedInsts 24280608 # The number of committed instructions 775system.cpu0.commit.commitCommittedOps 32020757 # The number of committed instructions
776system.cpu0.commit.commitSquashedInsts 6703968 # The number of squashed insts skipped by commit 777system.cpu0.commit.commitNonSpecStalls 689136 # The number of times commit has been forced to stall to communicate backwards 778system.cpu0.commit.branchMispredicts 267907 # The number of times a branch was mispredicted 779system.cpu0.commit.committed_per_cycle::samples 44701440 # Number of insts commited each cycle 780system.cpu0.commit.committed_per_cycle::mean 0.716325 # Number of insts commited each cycle 781system.cpu0.commit.committed_per_cycle::stdev 1.672707 # Number of insts commited each cycle 782system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 783system.cpu0.commit.committed_per_cycle::0 32554343 72.83% 72.83% # Number of insts commited each cycle 784system.cpu0.commit.committed_per_cycle::1 6077315 13.60% 86.42% # Number of insts commited each cycle 785system.cpu0.commit.committed_per_cycle::2 1947893 4.36% 90.78% # Number of insts commited each cycle 786system.cpu0.commit.committed_per_cycle::3 1038743 2.32% 93.10% # Number of insts commited each cycle 787system.cpu0.commit.committed_per_cycle::4 803562 1.80% 94.90% # Number of insts commited each cycle 788system.cpu0.commit.committed_per_cycle::5 505193 1.13% 96.03% # Number of insts commited each cycle 789system.cpu0.commit.committed_per_cycle::6 401469 0.90% 96.93% # Number of insts commited each cycle 790system.cpu0.commit.committed_per_cycle::7 200976 0.45% 97.38% # Number of insts commited each cycle 791system.cpu0.commit.committed_per_cycle::8 1171946 2.62% 100.00% # Number of insts commited each cycle 792system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 793system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 794system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 795system.cpu0.commit.committed_per_cycle::total 44701440 # Number of insts commited each cycle 796system.cpu0.commit.committedInsts 24280608 # Number of instructions committed 797system.cpu0.commit.committedOps 32020757 # Number of ops (including micro ops) committed 798system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 799system.cpu0.commit.refs 11707325 # Number of memory references committed 800system.cpu0.commit.loads 6427859 # Number of loads committed 801system.cpu0.commit.membars 234599 # Number of memory barriers committed 802system.cpu0.commit.branches 4418672 # Number of branches committed 803system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. 804system.cpu0.commit.int_insts 28286546 # Number of committed integer instructions. 805system.cpu0.commit.function_calls 500309 # Number of function calls committed. 806system.cpu0.commit.bw_lim_events 1171946 # number cycles where commit BW limit reached 807system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 808system.cpu0.rob.rob_reads 81369547 # The number of ROB reads 809system.cpu0.rob.rob_writes 78542452 # The number of ROB writes 810system.cpu0.timesIdled 427204 # Number of times that the entire CPU went into an idle state and unscheduled itself 811system.cpu0.idleCycles 27784943 # Total number of cycles that the CPU has spent unscheduled due to idling 812system.cpu0.quiesceCycles 5160481977 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 813system.cpu0.committedInsts 24199866 # Number of Instructions Simulated 814system.cpu0.committedOps 31940015 # Number of Ops (including micro ops) Simulated 815system.cpu0.committedInsts_total 24199866 # Number of Instructions Simulated 816system.cpu0.cpi 3.038882 # CPI: Cycles Per Instruction 817system.cpu0.cpi_total 3.038882 # CPI: Total CPI of All Threads 818system.cpu0.ipc 0.329068 # IPC: Instructions Per Cycle 819system.cpu0.ipc_total 0.329068 # IPC: Total IPC of All Threads 820system.cpu0.int_regfile_reads 176731885 # number of integer regfile reads 821system.cpu0.int_regfile_writes 35129220 # number of integer regfile writes 822system.cpu0.fp_regfile_reads 3381 # number of floating regfile reads 823system.cpu0.fp_regfile_writes 940 # number of floating regfile writes 824system.cpu0.misc_regfile_reads 47656068 # number of misc regfile reads 825system.cpu0.misc_regfile_writes 527809 # number of misc regfile writes 826system.cpu0.icache.replacements 407270 # number of replacements 827system.cpu0.icache.tagsinuse 511.577657 # Cycle average of tags in use 828system.cpu0.icache.total_refs 3982592 # Total number of references to valid blocks. 829system.cpu0.icache.sampled_refs 407782 # Sample count of references to valid blocks. 830system.cpu0.icache.avg_refs 9.766473 # Average number of references to valid blocks. 831system.cpu0.icache.warmup_cycle 7275068000 # Cycle when the warmup percentage was hit. 832system.cpu0.icache.occ_blocks::cpu0.inst 511.577657 # Average occupied blocks per requestor 833system.cpu0.icache.occ_percent::cpu0.inst 0.999175 # Average percentage of cache occupancy 834system.cpu0.icache.occ_percent::total 0.999175 # Average percentage of cache occupancy 835system.cpu0.icache.ReadReq_hits::cpu0.inst 3982592 # number of ReadReq hits 836system.cpu0.icache.ReadReq_hits::total 3982592 # number of ReadReq hits 837system.cpu0.icache.demand_hits::cpu0.inst 3982592 # number of demand (read+write) hits 838system.cpu0.icache.demand_hits::total 3982592 # number of demand (read+write) hits 839system.cpu0.icache.overall_hits::cpu0.inst 3982592 # number of overall hits 840system.cpu0.icache.overall_hits::total 3982592 # number of overall hits 841system.cpu0.icache.ReadReq_misses::cpu0.inst 441782 # number of ReadReq misses 842system.cpu0.icache.ReadReq_misses::total 441782 # number of ReadReq misses 843system.cpu0.icache.demand_misses::cpu0.inst 441782 # number of demand (read+write) misses 844system.cpu0.icache.demand_misses::total 441782 # number of demand (read+write) misses 845system.cpu0.icache.overall_misses::cpu0.inst 441782 # number of overall misses 846system.cpu0.icache.overall_misses::total 441782 # number of overall misses 847system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7132710997 # number of ReadReq miss cycles 848system.cpu0.icache.ReadReq_miss_latency::total 7132710997 # number of ReadReq miss cycles 849system.cpu0.icache.demand_miss_latency::cpu0.inst 7132710997 # number of demand (read+write) miss cycles 850system.cpu0.icache.demand_miss_latency::total 7132710997 # number of demand (read+write) miss cycles 851system.cpu0.icache.overall_miss_latency::cpu0.inst 7132710997 # number of overall miss cycles 852system.cpu0.icache.overall_miss_latency::total 7132710997 # number of overall miss cycles 853system.cpu0.icache.ReadReq_accesses::cpu0.inst 4424374 # number of ReadReq accesses(hits+misses) 854system.cpu0.icache.ReadReq_accesses::total 4424374 # number of ReadReq accesses(hits+misses) 855system.cpu0.icache.demand_accesses::cpu0.inst 4424374 # number of demand (read+write) accesses 856system.cpu0.icache.demand_accesses::total 4424374 # number of demand (read+write) accesses 857system.cpu0.icache.overall_accesses::cpu0.inst 4424374 # number of overall (read+write) accesses 858system.cpu0.icache.overall_accesses::total 4424374 # number of overall (read+write) accesses 859system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099852 # miss rate for ReadReq accesses 860system.cpu0.icache.ReadReq_miss_rate::total 0.099852 # miss rate for ReadReq accesses 861system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099852 # miss rate for demand accesses 862system.cpu0.icache.demand_miss_rate::total 0.099852 # miss rate for demand accesses 863system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099852 # miss rate for overall accesses 864system.cpu0.icache.overall_miss_rate::total 0.099852 # miss rate for overall accesses 865system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16145.318272 # average ReadReq miss latency 866system.cpu0.icache.ReadReq_avg_miss_latency::total 16145.318272 # average ReadReq miss latency 867system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16145.318272 # average overall miss latency 868system.cpu0.icache.demand_avg_miss_latency::total 16145.318272 # average overall miss latency 869system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16145.318272 # average overall miss latency 870system.cpu0.icache.overall_avg_miss_latency::total 16145.318272 # average overall miss latency 871system.cpu0.icache.blocked_cycles::no_mshrs 1383498 # number of cycles access was blocked 872system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 873system.cpu0.icache.blocked::no_mshrs 169 # number of cycles access was blocked 874system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 875system.cpu0.icache.avg_blocked_cycles::no_mshrs 8186.378698 # average number of cycles each access was blocked 876system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 877system.cpu0.icache.fast_writes 0 # number of fast writes performed 878system.cpu0.icache.cache_copies 0 # number of cache copies performed 879system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33988 # number of ReadReq MSHR hits 880system.cpu0.icache.ReadReq_mshr_hits::total 33988 # number of ReadReq MSHR hits 881system.cpu0.icache.demand_mshr_hits::cpu0.inst 33988 # number of demand (read+write) MSHR hits 882system.cpu0.icache.demand_mshr_hits::total 33988 # number of demand (read+write) MSHR hits 883system.cpu0.icache.overall_mshr_hits::cpu0.inst 33988 # number of overall MSHR hits 884system.cpu0.icache.overall_mshr_hits::total 33988 # number of overall MSHR hits 885system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 407794 # number of ReadReq MSHR misses 886system.cpu0.icache.ReadReq_mshr_misses::total 407794 # number of ReadReq MSHR misses 887system.cpu0.icache.demand_mshr_misses::cpu0.inst 407794 # number of demand (read+write) MSHR misses 888system.cpu0.icache.demand_mshr_misses::total 407794 # number of demand (read+write) MSHR misses 889system.cpu0.icache.overall_mshr_misses::cpu0.inst 407794 # number of overall MSHR misses 890system.cpu0.icache.overall_mshr_misses::total 407794 # number of overall MSHR misses 891system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5471235499 # number of ReadReq MSHR miss cycles 892system.cpu0.icache.ReadReq_mshr_miss_latency::total 5471235499 # number of ReadReq MSHR miss cycles 893system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5471235499 # number of demand (read+write) MSHR miss cycles 894system.cpu0.icache.demand_mshr_miss_latency::total 5471235499 # number of demand (read+write) MSHR miss cycles 895system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5471235499 # number of overall MSHR miss cycles 896system.cpu0.icache.overall_mshr_miss_latency::total 5471235499 # number of overall MSHR miss cycles 897system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8379000 # number of ReadReq MSHR uncacheable cycles 898system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8379000 # number of ReadReq MSHR uncacheable cycles 899system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8379000 # number of overall MSHR uncacheable cycles 900system.cpu0.icache.overall_mshr_uncacheable_latency::total 8379000 # number of overall MSHR uncacheable cycles 901system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for ReadReq accesses 902system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092170 # mshr miss rate for ReadReq accesses 903system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for demand accesses 904system.cpu0.icache.demand_mshr_miss_rate::total 0.092170 # mshr miss rate for demand accesses 905system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for overall accesses 906system.cpu0.icache.overall_mshr_miss_rate::total 0.092170 # mshr miss rate for overall accesses 907system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13416.665029 # average ReadReq mshr miss latency 908system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13416.665029 # average ReadReq mshr miss latency 909system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13416.665029 # average overall mshr miss latency 910system.cpu0.icache.demand_avg_mshr_miss_latency::total 13416.665029 # average overall mshr miss latency 911system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13416.665029 # average overall mshr miss latency 912system.cpu0.icache.overall_avg_mshr_miss_latency::total 13416.665029 # average overall mshr miss latency 913system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 914system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 915system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 916system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 917system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 918system.cpu0.dcache.replacements 275687 # number of replacements 919system.cpu0.dcache.tagsinuse 476.019935 # Cycle average of tags in use 920system.cpu0.dcache.total_refs 9558592 # Total number of references to valid blocks. 921system.cpu0.dcache.sampled_refs 276199 # Sample count of references to valid blocks. 922system.cpu0.dcache.avg_refs 34.607627 # Average number of references to valid blocks. 923system.cpu0.dcache.warmup_cycle 51448000 # Cycle when the warmup percentage was hit. 924system.cpu0.dcache.occ_blocks::cpu0.data 476.019935 # Average occupied blocks per requestor 925system.cpu0.dcache.occ_percent::cpu0.data 0.929726 # Average percentage of cache occupancy 926system.cpu0.dcache.occ_percent::total 0.929726 # Average percentage of cache occupancy 927system.cpu0.dcache.ReadReq_hits::cpu0.data 5937166 # number of ReadReq hits 928system.cpu0.dcache.ReadReq_hits::total 5937166 # number of ReadReq hits 929system.cpu0.dcache.WriteReq_hits::cpu0.data 3229422 # number of WriteReq hits 930system.cpu0.dcache.WriteReq_hits::total 3229422 # number of WriteReq hits 931system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174299 # number of LoadLockedReq hits 932system.cpu0.dcache.LoadLockedReq_hits::total 174299 # number of LoadLockedReq hits 933system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171559 # number of StoreCondReq hits 934system.cpu0.dcache.StoreCondReq_hits::total 171559 # number of StoreCondReq hits 935system.cpu0.dcache.demand_hits::cpu0.data 9166588 # number of demand (read+write) hits 936system.cpu0.dcache.demand_hits::total 9166588 # number of demand (read+write) hits 937system.cpu0.dcache.overall_hits::cpu0.data 9166588 # number of overall hits 938system.cpu0.dcache.overall_hits::total 9166588 # number of overall hits 939system.cpu0.dcache.ReadReq_misses::cpu0.data 401556 # number of ReadReq misses 940system.cpu0.dcache.ReadReq_misses::total 401556 # number of ReadReq misses 941system.cpu0.dcache.WriteReq_misses::cpu0.data 1594295 # number of WriteReq misses 942system.cpu0.dcache.WriteReq_misses::total 1594295 # number of WriteReq misses 943system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9014 # number of LoadLockedReq misses 944system.cpu0.dcache.LoadLockedReq_misses::total 9014 # number of LoadLockedReq misses 945system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7780 # number of StoreCondReq misses 946system.cpu0.dcache.StoreCondReq_misses::total 7780 # number of StoreCondReq misses 947system.cpu0.dcache.demand_misses::cpu0.data 1995851 # number of demand (read+write) misses 948system.cpu0.dcache.demand_misses::total 1995851 # number of demand (read+write) misses 949system.cpu0.dcache.overall_misses::cpu0.data 1995851 # number of overall misses 950system.cpu0.dcache.overall_misses::total 1995851 # number of overall misses 951system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7292954000 # number of ReadReq miss cycles 952system.cpu0.dcache.ReadReq_miss_latency::total 7292954000 # number of ReadReq miss cycles 953system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71657694355 # number of WriteReq miss cycles 954system.cpu0.dcache.WriteReq_miss_latency::total 71657694355 # number of WriteReq miss cycles 955system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 113831500 # number of LoadLockedReq miss cycles 956system.cpu0.dcache.LoadLockedReq_miss_latency::total 113831500 # number of LoadLockedReq miss cycles 957system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 90370500 # number of StoreCondReq miss cycles 958system.cpu0.dcache.StoreCondReq_miss_latency::total 90370500 # number of StoreCondReq miss cycles 959system.cpu0.dcache.demand_miss_latency::cpu0.data 78950648355 # number of demand (read+write) miss cycles 960system.cpu0.dcache.demand_miss_latency::total 78950648355 # number of demand (read+write) miss cycles 961system.cpu0.dcache.overall_miss_latency::cpu0.data 78950648355 # number of overall miss cycles 962system.cpu0.dcache.overall_miss_latency::total 78950648355 # number of overall miss cycles 963system.cpu0.dcache.ReadReq_accesses::cpu0.data 6338722 # number of ReadReq accesses(hits+misses) 964system.cpu0.dcache.ReadReq_accesses::total 6338722 # number of ReadReq accesses(hits+misses) 965system.cpu0.dcache.WriteReq_accesses::cpu0.data 4823717 # number of WriteReq accesses(hits+misses) 966system.cpu0.dcache.WriteReq_accesses::total 4823717 # number of WriteReq accesses(hits+misses) 967system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183313 # number of LoadLockedReq accesses(hits+misses) 968system.cpu0.dcache.LoadLockedReq_accesses::total 183313 # number of LoadLockedReq accesses(hits+misses) 969system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179339 # number of StoreCondReq accesses(hits+misses) 970system.cpu0.dcache.StoreCondReq_accesses::total 179339 # number of StoreCondReq accesses(hits+misses) 971system.cpu0.dcache.demand_accesses::cpu0.data 11162439 # number of demand (read+write) accesses 972system.cpu0.dcache.demand_accesses::total 11162439 # number of demand (read+write) accesses 973system.cpu0.dcache.overall_accesses::cpu0.data 11162439 # number of overall (read+write) accesses 974system.cpu0.dcache.overall_accesses::total 11162439 # number of overall (read+write) accesses 975system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063350 # miss rate for ReadReq accesses 976system.cpu0.dcache.ReadReq_miss_rate::total 0.063350 # miss rate for ReadReq accesses 977system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330512 # miss rate for WriteReq accesses 978system.cpu0.dcache.WriteReq_miss_rate::total 0.330512 # miss rate for WriteReq accesses 979system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.049173 # miss rate for LoadLockedReq accesses 980system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.049173 # miss rate for LoadLockedReq accesses 981system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043382 # miss rate for StoreCondReq accesses 982system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043382 # miss rate for StoreCondReq accesses 983system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178801 # miss rate for demand accesses 984system.cpu0.dcache.demand_miss_rate::total 0.178801 # miss rate for demand accesses 985system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178801 # miss rate for overall accesses 986system.cpu0.dcache.overall_miss_rate::total 0.178801 # miss rate for overall accesses 987system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18161.735848 # average ReadReq miss latency 988system.cpu0.dcache.ReadReq_avg_miss_latency::total 18161.735848 # average ReadReq miss latency 989system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44946.320697 # average WriteReq miss latency 990system.cpu0.dcache.WriteReq_avg_miss_latency::total 44946.320697 # average WriteReq miss latency 991system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12628.300422 # average LoadLockedReq miss latency 992system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12628.300422 # average LoadLockedReq miss latency 993system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11615.745501 # average StoreCondReq miss latency 994system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11615.745501 # average StoreCondReq miss latency 995system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39557.385975 # average overall miss latency 996system.cpu0.dcache.demand_avg_miss_latency::total 39557.385975 # average overall miss latency 997system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39557.385975 # average overall miss latency 998system.cpu0.dcache.overall_avg_miss_latency::total 39557.385975 # average overall miss latency 999system.cpu0.dcache.blocked_cycles::no_mshrs 7317992 # number of cycles access was blocked 1000system.cpu0.dcache.blocked_cycles::no_targets 1712000 # number of cycles access was blocked 1001system.cpu0.dcache.blocked::no_mshrs 1467 # number of cycles access was blocked 1002system.cpu0.dcache.blocked::no_targets 85 # number of cycles access was blocked 1003system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4988.406271 # average number of cycles each access was blocked 1004system.cpu0.dcache.avg_blocked_cycles::no_targets 20141.176471 # average number of cycles each access was blocked 1005system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1006system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1007system.cpu0.dcache.writebacks::writebacks 255942 # number of writebacks 1008system.cpu0.dcache.writebacks::total 255942 # number of writebacks 1009system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 212150 # number of ReadReq MSHR hits 1010system.cpu0.dcache.ReadReq_mshr_hits::total 212150 # number of ReadReq MSHR hits 1011system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1463164 # number of WriteReq MSHR hits 1012system.cpu0.dcache.WriteReq_mshr_hits::total 1463164 # number of WriteReq MSHR hits 1013system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 530 # number of LoadLockedReq MSHR hits 1014system.cpu0.dcache.LoadLockedReq_mshr_hits::total 530 # number of LoadLockedReq MSHR hits 1015system.cpu0.dcache.demand_mshr_hits::cpu0.data 1675314 # number of demand (read+write) MSHR hits 1016system.cpu0.dcache.demand_mshr_hits::total 1675314 # number of demand (read+write) MSHR hits 1017system.cpu0.dcache.overall_mshr_hits::cpu0.data 1675314 # number of overall MSHR hits 1018system.cpu0.dcache.overall_mshr_hits::total 1675314 # number of overall MSHR hits 1019system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189406 # number of ReadReq MSHR misses 1020system.cpu0.dcache.ReadReq_mshr_misses::total 189406 # number of ReadReq MSHR misses 1021system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131131 # number of WriteReq MSHR misses 1022system.cpu0.dcache.WriteReq_mshr_misses::total 131131 # number of WriteReq MSHR misses 1023system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8484 # number of LoadLockedReq MSHR misses 1024system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8484 # number of LoadLockedReq MSHR misses 1025system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7773 # number of StoreCondReq MSHR misses 1026system.cpu0.dcache.StoreCondReq_mshr_misses::total 7773 # number of StoreCondReq MSHR misses 1027system.cpu0.dcache.demand_mshr_misses::cpu0.data 320537 # number of demand (read+write) MSHR misses 1028system.cpu0.dcache.demand_mshr_misses::total 320537 # number of demand (read+write) MSHR misses 1029system.cpu0.dcache.overall_mshr_misses::cpu0.data 320537 # number of overall MSHR misses 1030system.cpu0.dcache.overall_mshr_misses::total 320537 # number of overall MSHR misses 1031system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2811014487 # number of ReadReq MSHR miss cycles 1032system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2811014487 # number of ReadReq MSHR miss cycles 1033system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4674099005 # number of WriteReq MSHR miss cycles 1034system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4674099005 # number of WriteReq MSHR miss cycles 1035system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79244002 # number of LoadLockedReq MSHR miss cycles 1036system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79244002 # number of LoadLockedReq MSHR miss cycles 1037system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 65918035 # number of StoreCondReq MSHR miss cycles 1038system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 65918035 # number of StoreCondReq MSHR miss cycles 1039system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles 1040system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 1041system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7485113492 # number of demand (read+write) MSHR miss cycles 1042system.cpu0.dcache.demand_mshr_miss_latency::total 7485113492 # number of demand (read+write) MSHR miss cycles 1043system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7485113492 # number of overall MSHR miss cycles 1044system.cpu0.dcache.overall_mshr_miss_latency::total 7485113492 # number of overall MSHR miss cycles 1045system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13455989500 # number of ReadReq MSHR uncacheable cycles 1046system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13455989500 # number of ReadReq MSHR uncacheable cycles 1047system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1298746899 # number of WriteReq MSHR uncacheable cycles 1048system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1298746899 # number of WriteReq MSHR uncacheable cycles 1049system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14754736399 # number of overall MSHR uncacheable cycles 1050system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14754736399 # number of overall MSHR uncacheable cycles 1051system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029881 # mshr miss rate for ReadReq accesses 1052system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029881 # mshr miss rate for ReadReq accesses 1053system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027185 # mshr miss rate for WriteReq accesses 1054system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027185 # mshr miss rate for WriteReq accesses 1055system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046281 # mshr miss rate for LoadLockedReq accesses 1056system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046281 # mshr miss rate for LoadLockedReq accesses 1057system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043342 # mshr miss rate for StoreCondReq accesses 1058system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043342 # mshr miss rate for StoreCondReq accesses 1059system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028716 # mshr miss rate for demand accesses 1060system.cpu0.dcache.demand_mshr_miss_rate::total 0.028716 # mshr miss rate for demand accesses 1061system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028716 # mshr miss rate for overall accesses 1062system.cpu0.dcache.overall_mshr_miss_rate::total 0.028716 # mshr miss rate for overall accesses 1063system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14841.211403 # average ReadReq mshr miss latency 1064system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14841.211403 # average ReadReq mshr miss latency 1065system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35644.500576 # average WriteReq mshr miss latency 1066system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35644.500576 # average WriteReq mshr miss latency 1067system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9340.405705 # average LoadLockedReq mshr miss latency 1068system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9340.405705 # average LoadLockedReq mshr miss latency 1069system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8480.385308 # average StoreCondReq mshr miss latency 1070system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8480.385308 # average StoreCondReq mshr miss latency 1071system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1072system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1073system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23351.792436 # average overall mshr miss latency 1074system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23351.792436 # average overall mshr miss latency 1075system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23351.792436 # average overall mshr miss latency 1076system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23351.792436 # average overall mshr miss latency 1077system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1078system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1079system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1080system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1081system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1082system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1083system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1084system.cpu1.dtb.inst_hits 0 # ITB inst hits 1085system.cpu1.dtb.inst_misses 0 # ITB inst misses 1086system.cpu1.dtb.read_hits 43452334 # DTB read hits 1087system.cpu1.dtb.read_misses 46277 # DTB read misses 1088system.cpu1.dtb.write_hits 7091337 # DTB write hits 1089system.cpu1.dtb.write_misses 12150 # DTB write misses 1090system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1091system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1092system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1093system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1094system.cpu1.dtb.flush_entries 2524 # Number of entries that have been flushed from TLB 1095system.cpu1.dtb.align_faults 3762 # Number of TLB faults due to alignment restrictions 1096system.cpu1.dtb.prefetch_faults 371 # Number of TLB faults due to prefetch 1097system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1098system.cpu1.dtb.perms_faults 692 # Number of TLB faults due to permissions restrictions 1099system.cpu1.dtb.read_accesses 43498611 # DTB read accesses 1100system.cpu1.dtb.write_accesses 7103487 # DTB write accesses 1101system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1102system.cpu1.dtb.hits 50543671 # DTB hits 1103system.cpu1.dtb.misses 58427 # DTB misses 1104system.cpu1.dtb.accesses 50602098 # DTB accesses 1105system.cpu1.itb.inst_hits 9232744 # ITB inst hits 1106system.cpu1.itb.inst_misses 6115 # ITB inst misses 1107system.cpu1.itb.read_hits 0 # DTB read hits 1108system.cpu1.itb.read_misses 0 # DTB read misses 1109system.cpu1.itb.write_hits 0 # DTB write hits 1110system.cpu1.itb.write_misses 0 # DTB write misses 1111system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1112system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1113system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1114system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1115system.cpu1.itb.flush_entries 1606 # Number of entries that have been flushed from TLB 1116system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1117system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1118system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1119system.cpu1.itb.perms_faults 1727 # Number of TLB faults due to permissions restrictions 1120system.cpu1.itb.read_accesses 0 # DTB read accesses 1121system.cpu1.itb.write_accesses 0 # DTB write accesses 1122system.cpu1.itb.inst_accesses 9238859 # ITB inst accesses 1123system.cpu1.itb.hits 9232744 # DTB hits 1124system.cpu1.itb.misses 6115 # DTB misses 1125system.cpu1.itb.accesses 9238859 # DTB accesses 1126system.cpu1.numCycles 420389270 # number of cpu cycles simulated 1127system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1128system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1129system.cpu1.BPredUnit.lookups 9847995 # Number of BP lookups 1130system.cpu1.BPredUnit.condPredicted 8081754 # Number of conditional branches predicted 1131system.cpu1.BPredUnit.condIncorrect 448433 # Number of conditional branches incorrect 1132system.cpu1.BPredUnit.BTBLookups 6818773 # Number of BTB lookups 1133system.cpu1.BPredUnit.BTBHits 5657403 # Number of BTB hits 1134system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1135system.cpu1.BPredUnit.usedRAS 833939 # Number of times the RAS was used to get a target. 1136system.cpu1.BPredUnit.RASInCorrect 50420 # Number of incorrect RAS predictions. 1137system.cpu1.fetch.icacheStallCycles 22177481 # Number of cycles fetch is stalled on an Icache miss 1138system.cpu1.fetch.Insts 71987538 # Number of instructions fetch has processed 1139system.cpu1.fetch.Branches 9847995 # Number of branches that fetch encountered 1140system.cpu1.fetch.predictedBranches 6491342 # Number of branches that fetch has predicted taken 1141system.cpu1.fetch.Cycles 15338669 # Number of cycles fetch has run and was not squashing or blocked 1142system.cpu1.fetch.SquashCycles 4640041 # Number of cycles fetch has spent squashing 1143system.cpu1.fetch.TlbCycles 86616 # Number of cycles fetch has spent waiting for tlb 1144system.cpu1.fetch.BlockedCycles 81067805 # Number of cycles fetch has spent blocked 1145system.cpu1.fetch.MiscStallCycles 5869 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1146system.cpu1.fetch.PendingTrapStallCycles 63713 # Number of stall cycles due to pending traps 1147system.cpu1.fetch.PendingQuiesceStallCycles 142087 # Number of stall cycles due to pending quiesce instructions 1148system.cpu1.fetch.IcacheWaitRetryStallCycles 99 # Number of stall cycles due to full MSHR 1149system.cpu1.fetch.CacheLines 9230611 # Number of cache lines fetched 1150system.cpu1.fetch.IcacheSquashes 860735 # Number of outstanding Icache misses that were squashed 1151system.cpu1.fetch.ItlbSquashes 3603 # Number of outstanding ITLB misses that were squashed 1152system.cpu1.fetch.rateDist::samples 122048207 # Number of instructions fetched each cycle (Total) 1153system.cpu1.fetch.rateDist::mean 0.712843 # Number of instructions fetched each cycle (Total) 1154system.cpu1.fetch.rateDist::stdev 2.062128 # Number of instructions fetched each cycle (Total) 1155system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1156system.cpu1.fetch.rateDist::0 106717875 87.44% 87.44% # Number of instructions fetched each cycle (Total) 1157system.cpu1.fetch.rateDist::1 829211 0.68% 88.12% # Number of instructions fetched each cycle (Total) 1158system.cpu1.fetch.rateDist::2 1015415 0.83% 88.95% # Number of instructions fetched each cycle (Total) 1159system.cpu1.fetch.rateDist::3 2063306 1.69% 90.64% # Number of instructions fetched each cycle (Total) 1160system.cpu1.fetch.rateDist::4 1641471 1.34% 91.99% # Number of instructions fetched each cycle (Total) 1161system.cpu1.fetch.rateDist::5 615009 0.50% 92.49% # Number of instructions fetched each cycle (Total) 1162system.cpu1.fetch.rateDist::6 2274741 1.86% 94.35% # Number of instructions fetched each cycle (Total) 1163system.cpu1.fetch.rateDist::7 467540 0.38% 94.74% # Number of instructions fetched each cycle (Total) 1164system.cpu1.fetch.rateDist::8 6423639 5.26% 100.00% # Number of instructions fetched each cycle (Total) 1165system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1166system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1167system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1168system.cpu1.fetch.rateDist::total 122048207 # Number of instructions fetched each cycle (Total) 1169system.cpu1.fetch.branchRate 0.023426 # Number of branch fetches per cycle 1170system.cpu1.fetch.rate 0.171240 # Number of inst fetches per cycle 1171system.cpu1.decode.IdleCycles 23807304 # Number of cycles decode is idle 1172system.cpu1.decode.BlockedCycles 80829213 # Number of cycles decode is blocked 1173system.cpu1.decode.RunCycles 13786228 # Number of cycles decode is running 1174system.cpu1.decode.UnblockCycles 560401 # Number of cycles decode is unblocking 1175system.cpu1.decode.SquashCycles 3065061 # Number of cycles decode is squashing 1176system.cpu1.decode.BranchResolved 1241341 # Number of times decode resolved a branch 1177system.cpu1.decode.BranchMispred 102643 # Number of times decode detected a branch misprediction 1178system.cpu1.decode.DecodedInsts 81234919 # Number of instructions handled by decode 1179system.cpu1.decode.SquashedInsts 343119 # Number of squashed instructions handled by decode 1180system.cpu1.rename.SquashCycles 3065061 # Number of cycles rename is squashing 1181system.cpu1.rename.IdleCycles 25364340 # Number of cycles rename is idle 1182system.cpu1.rename.BlockCycles 34010393 # Number of cycles rename is blocking 1183system.cpu1.rename.serializeStallCycles 42304537 # count of cycles rename stalled for serializing inst 1184system.cpu1.rename.RunCycles 12707018 # Number of cycles rename is running 1185system.cpu1.rename.UnblockCycles 4596858 # Number of cycles rename is unblocking 1186system.cpu1.rename.RenamedInsts 74746383 # Number of instructions processed by rename 1187system.cpu1.rename.ROBFullEvents 20429 # Number of times rename has blocked due to ROB full 1188system.cpu1.rename.IQFullEvents 720817 # Number of times rename has blocked due to IQ full 1189system.cpu1.rename.LSQFullEvents 3279864 # Number of times rename has blocked due to LSQ full 1190system.cpu1.rename.FullRegisterEvents 33412 # Number of times there has been no free registers 1191system.cpu1.rename.RenamedOperands 79106997 # Number of destination operands rename has renamed 1192system.cpu1.rename.RenameLookups 344419030 # Number of register rename lookups that rename has made 1193system.cpu1.rename.int_rename_lookups 344359691 # Number of integer rename lookups 1194system.cpu1.rename.fp_rename_lookups 59339 # Number of floating rename lookups 1195system.cpu1.rename.CommittedMaps 50193146 # Number of HB maps that are committed 1196system.cpu1.rename.UndoneMaps 28913851 # Number of HB maps that are undone due to squashing 1197system.cpu1.rename.serializingInsts 487769 # count of serializing insts renamed 1198system.cpu1.rename.tempSerializingInsts 421850 # count of temporary serializing insts renamed 1199system.cpu1.rename.skidInsts 8399849 # count of insts added to the skid buffer 1200system.cpu1.memDep0.insertedLoads 14034972 # Number of loads inserted to the mem dependence unit. 1201system.cpu1.memDep0.insertedStores 8614706 # Number of stores inserted to the mem dependence unit. 1202system.cpu1.memDep0.conflictingLoads 1072487 # Number of conflicting loads. 1203system.cpu1.memDep0.conflictingStores 1529720 # Number of conflicting stores. 1204system.cpu1.iq.iqInstsAdded 67446295 # Number of instructions added to the IQ (excludes non-spec) 1205system.cpu1.iq.iqNonSpecInstsAdded 1206628 # Number of non-speculative instructions added to the IQ 1206system.cpu1.iq.iqInstsIssued 91979521 # Number of instructions issued 1207system.cpu1.iq.iqSquashedInstsIssued 109681 # Number of squashed instructions issued 1208system.cpu1.iq.iqSquashedInstsExamined 18910261 # Number of squashed instructions iterated over during squash; mainly for profiling 1209system.cpu1.iq.iqSquashedOperandsExamined 53596675 # Number of squashed operands that are examined and possibly removed from graph 1210system.cpu1.iq.iqSquashedNonSpecRemoved 286825 # Number of squashed non-spec instructions that were removed 1211system.cpu1.iq.issued_per_cycle::samples 122048207 # Number of insts issued each cycle 1212system.cpu1.iq.issued_per_cycle::mean 0.753633 # Number of insts issued each cycle 1213system.cpu1.iq.issued_per_cycle::stdev 1.492572 # Number of insts issued each cycle 1214system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1215system.cpu1.iq.issued_per_cycle::0 90230410 73.93% 73.93% # Number of insts issued each cycle 1216system.cpu1.iq.issued_per_cycle::1 9124502 7.48% 81.41% # Number of insts issued each cycle 1217system.cpu1.iq.issued_per_cycle::2 4577298 3.75% 85.16% # Number of insts issued each cycle 1218system.cpu1.iq.issued_per_cycle::3 4017634 3.29% 88.45% # Number of insts issued each cycle 1219system.cpu1.iq.issued_per_cycle::4 10703333 8.77% 97.22% # Number of insts issued each cycle 1220system.cpu1.iq.issued_per_cycle::5 1977632 1.62% 98.84% # Number of insts issued each cycle 1221system.cpu1.iq.issued_per_cycle::6 1055737 0.87% 99.70% # Number of insts issued each cycle 1222system.cpu1.iq.issued_per_cycle::7 281681 0.23% 99.93% # Number of insts issued each cycle 1223system.cpu1.iq.issued_per_cycle::8 79980 0.07% 100.00% # Number of insts issued each cycle 1224system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1225system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1226system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1227system.cpu1.iq.issued_per_cycle::total 122048207 # Number of insts issued each cycle 1228system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1229system.cpu1.iq.fu_full::IntAlu 28913 0.37% 0.37% # attempts to use FU when none available 1230system.cpu1.iq.fu_full::IntMult 998 0.01% 0.38% # attempts to use FU when none available 1231system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available 1232system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available 1233system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available 1234system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available 1235system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available 1236system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available 1237system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available 1238system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available 1239system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available 1240system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available 1241system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available 1242system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available 1243system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available 1244system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available 1245system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available 1246system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available 1247system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available 1248system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available 1249system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available 1250system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available 1251system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available 1252system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available 1253system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available 1254system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available 1255system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available 1256system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available 1257system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available 1258system.cpu1.iq.fu_full::MemRead 7574685 95.84% 96.22% # attempts to use FU when none available 1259system.cpu1.iq.fu_full::MemWrite 298874 3.78% 100.00% # attempts to use FU when none available 1260system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1261system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1262system.cpu1.iq.FU_type_0::No_OpClass 313737 0.34% 0.34% # Type of FU issued 1263system.cpu1.iq.FU_type_0::IntAlu 39479578 42.92% 43.26% # Type of FU issued 1264system.cpu1.iq.FU_type_0::IntMult 61492 0.07% 43.33% # Type of FU issued 1265system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.33% # Type of FU issued 1266system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.33% # Type of FU issued 1267system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.33% # Type of FU issued 1268system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.33% # Type of FU issued 1269system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.33% # Type of FU issued 1270system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.33% # Type of FU issued 1271system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.33% # Type of FU issued 1272system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.33% # Type of FU issued 1273system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.33% # Type of FU issued 1274system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.33% # Type of FU issued 1275system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.33% # Type of FU issued 1276system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.33% # Type of FU issued 1277system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 43.33% # Type of FU issued 1278system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.33% # Type of FU issued 1279system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.33% # Type of FU issued 1280system.cpu1.iq.FU_type_0::SimdShift 6 0.00% 43.33% # Type of FU issued 1281system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 43.33% # Type of FU issued 1282system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.33% # Type of FU issued 1283system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.33% # Type of FU issued 1284system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.33% # Type of FU issued 1285system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.33% # Type of FU issued 1286system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.33% # Type of FU issued 1287system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.33% # Type of FU issued 1288system.cpu1.iq.FU_type_0::SimdFloatMisc 1697 0.00% 43.33% # Type of FU issued 1289system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.33% # Type of FU issued 1290system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 43.33% # Type of FU issued 1291system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.33% # Type of FU issued 1292system.cpu1.iq.FU_type_0::MemRead 44651207 48.54% 91.88% # Type of FU issued 1293system.cpu1.iq.FU_type_0::MemWrite 7471778 8.12% 100.00% # Type of FU issued 1294system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1295system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1296system.cpu1.iq.FU_type_0::total 91979521 # Type of FU issued 1297system.cpu1.iq.rate 0.218796 # Inst issue rate 1298system.cpu1.iq.fu_busy_cnt 7903470 # FU busy when requested 1299system.cpu1.iq.fu_busy_rate 0.085926 # FU busy rate (busy events/executed inst) 1300system.cpu1.iq.int_inst_queue_reads 314063875 # Number of integer instruction queue reads 1301system.cpu1.iq.int_inst_queue_writes 87576510 # Number of integer instruction queue writes 1302system.cpu1.iq.int_inst_queue_wakeup_accesses 55784562 # Number of integer instruction queue wakeup accesses 1303system.cpu1.iq.fp_inst_queue_reads 14814 # Number of floating instruction queue reads 1304system.cpu1.iq.fp_inst_queue_writes 8109 # Number of floating instruction queue writes 1305system.cpu1.iq.fp_inst_queue_wakeup_accesses 6801 # Number of floating instruction queue wakeup accesses 1306system.cpu1.iq.int_alu_accesses 99561488 # Number of integer alu accesses 1307system.cpu1.iq.fp_alu_accesses 7766 # Number of floating point alu accesses 1308system.cpu1.iew.lsq.thread0.forwLoads 369403 # Number of loads that had data forwarded from stores 1309system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1310system.cpu1.iew.lsq.thread0.squashedLoads 4042367 # Number of loads squashed 1311system.cpu1.iew.lsq.thread0.ignoredResponses 6847 # Number of memory responses ignored because the instruction is squashed 1312system.cpu1.iew.lsq.thread0.memOrderViolation 22042 # Number of memory ordering violations 1313system.cpu1.iew.lsq.thread0.squashedStores 1594624 # Number of stores squashed 1314system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1315system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1316system.cpu1.iew.lsq.thread0.rescheduledLoads 31965742 # Number of loads that were rescheduled 1317system.cpu1.iew.lsq.thread0.cacheBlocked 1047944 # Number of times an access to memory failed due to the cache being blocked 1318system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1319system.cpu1.iew.iewSquashCycles 3065061 # Number of cycles IEW is squashing 1320system.cpu1.iew.iewBlockCycles 25634357 # Number of cycles IEW is blocking 1321system.cpu1.iew.iewUnblockCycles 409319 # Number of cycles IEW is unblocking 1322system.cpu1.iew.iewDispatchedInsts 68777683 # Number of instructions dispatched to IQ 1323system.cpu1.iew.iewDispSquashedInsts 134755 # Number of squashed instructions skipped by dispatch 1324system.cpu1.iew.iewDispLoadInsts 14034972 # Number of dispatched load instructions 1325system.cpu1.iew.iewDispStoreInsts 8614706 # Number of dispatched store instructions 1326system.cpu1.iew.iewDispNonSpecInsts 896270 # Number of dispatched non-speculative instructions 1327system.cpu1.iew.iewIQFullEvents 80399 # Number of times the IQ has become full, causing a stall 1328system.cpu1.iew.iewLSQFullEvents 14951 # Number of times the LSQ has become full, causing a stall 1329system.cpu1.iew.memOrderViolationEvents 22042 # Number of memory order violations 1330system.cpu1.iew.predictedTakenIncorrect 226446 # Number of branches that were predicted taken incorrectly 1331system.cpu1.iew.predictedNotTakenIncorrect 198201 # Number of branches that were predicted not taken incorrectly 1332system.cpu1.iew.branchMispredicts 424647 # Number of branch mispredicts detected at execute 1333system.cpu1.iew.iewExecutedInsts 89117462 # Number of executed instructions 1334system.cpu1.iew.iewExecLoadInsts 43838045 # Number of load instructions executed 1335system.cpu1.iew.iewExecSquashedInsts 2862059 # Number of squashed instructions skipped in execute 1336system.cpu1.iew.exec_swp 0 # number of swp insts executed 1337system.cpu1.iew.exec_nop 124760 # number of nop insts executed 1338system.cpu1.iew.exec_refs 51234744 # number of memory reference insts executed 1339system.cpu1.iew.exec_branches 7395685 # Number of branches executed 1340system.cpu1.iew.exec_stores 7396699 # Number of stores executed 1341system.cpu1.iew.exec_rate 0.211988 # Inst execution rate 1342system.cpu1.iew.wb_sent 87946957 # cumulative count of insts sent to commit 1343system.cpu1.iew.wb_count 55791363 # cumulative count of insts written-back 1344system.cpu1.iew.wb_producers 30796912 # num instructions producing a value 1345system.cpu1.iew.wb_consumers 54575062 # num instructions consuming a value 1346system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1347system.cpu1.iew.wb_rate 0.132714 # insts written-back per cycle 1348system.cpu1.iew.wb_fanout 0.564304 # average fanout of values written-back 1349system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ	774system.cpu0.commit.commitSquashedInsts 6703968 # The number of squashed insts skipped by commit 775system.cpu0.commit.commitNonSpecStalls 689136 # The number of times commit has been forced to stall to communicate backwards 776system.cpu0.commit.branchMispredicts 267907 # The number of times a branch was mispredicted 777system.cpu0.commit.committed_per_cycle::samples 44701440 # Number of insts commited each cycle 778system.cpu0.commit.committed_per_cycle::mean 0.716325 # Number of insts commited each cycle 779system.cpu0.commit.committed_per_cycle::stdev 1.672707 # Number of insts commited each cycle 780system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 781system.cpu0.commit.committed_per_cycle::0 32554343 72.83% 72.83% # Number of insts commited each cycle 782system.cpu0.commit.committed_per_cycle::1 6077315 13.60% 86.42% # Number of insts commited each cycle 783system.cpu0.commit.committed_per_cycle::2 1947893 4.36% 90.78% # Number of insts commited each cycle 784system.cpu0.commit.committed_per_cycle::3 1038743 2.32% 93.10% # Number of insts commited each cycle 785system.cpu0.commit.committed_per_cycle::4 803562 1.80% 94.90% # Number of insts commited each cycle 786system.cpu0.commit.committed_per_cycle::5 505193 1.13% 96.03% # Number of insts commited each cycle 787system.cpu0.commit.committed_per_cycle::6 401469 0.90% 96.93% # Number of insts commited each cycle 788system.cpu0.commit.committed_per_cycle::7 200976 0.45% 97.38% # Number of insts commited each cycle 789system.cpu0.commit.committed_per_cycle::8 1171946 2.62% 100.00% # Number of insts commited each cycle 790system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 791system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 792system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 793system.cpu0.commit.committed_per_cycle::total 44701440 # Number of insts commited each cycle 794system.cpu0.commit.committedInsts 24280608 # Number of instructions committed 795system.cpu0.commit.committedOps 32020757 # Number of ops (including micro ops) committed 796system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 797system.cpu0.commit.refs 11707325 # Number of memory references committed 798system.cpu0.commit.loads 6427859 # Number of loads committed 799system.cpu0.commit.membars 234599 # Number of memory barriers committed 800system.cpu0.commit.branches 4418672 # Number of branches committed 801system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. 802system.cpu0.commit.int_insts 28286546 # Number of committed integer instructions. 803system.cpu0.commit.function_calls 500309 # Number of function calls committed. 804system.cpu0.commit.bw_lim_events 1171946 # number cycles where commit BW limit reached 805system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits 806system.cpu0.rob.rob_reads 81369547 # The number of ROB reads 807system.cpu0.rob.rob_writes 78542452 # The number of ROB writes 808system.cpu0.timesIdled 427204 # Number of times that the entire CPU went into an idle state and unscheduled itself 809system.cpu0.idleCycles 27784943 # Total number of cycles that the CPU has spent unscheduled due to idling 810system.cpu0.quiesceCycles 5160481977 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 811system.cpu0.committedInsts 24199866 # Number of Instructions Simulated 812system.cpu0.committedOps 31940015 # Number of Ops (including micro ops) Simulated 813system.cpu0.committedInsts_total 24199866 # Number of Instructions Simulated 814system.cpu0.cpi 3.038882 # CPI: Cycles Per Instruction 815system.cpu0.cpi_total 3.038882 # CPI: Total CPI of All Threads 816system.cpu0.ipc 0.329068 # IPC: Instructions Per Cycle 817system.cpu0.ipc_total 0.329068 # IPC: Total IPC of All Threads 818system.cpu0.int_regfile_reads 176731885 # number of integer regfile reads 819system.cpu0.int_regfile_writes 35129220 # number of integer regfile writes 820system.cpu0.fp_regfile_reads 3381 # number of floating regfile reads 821system.cpu0.fp_regfile_writes 940 # number of floating regfile writes 822system.cpu0.misc_regfile_reads 47656068 # number of misc regfile reads 823system.cpu0.misc_regfile_writes 527809 # number of misc regfile writes 824system.cpu0.icache.replacements 407270 # number of replacements 825system.cpu0.icache.tagsinuse 511.577657 # Cycle average of tags in use 826system.cpu0.icache.total_refs 3982592 # Total number of references to valid blocks. 827system.cpu0.icache.sampled_refs 407782 # Sample count of references to valid blocks. 828system.cpu0.icache.avg_refs 9.766473 # Average number of references to valid blocks. 829system.cpu0.icache.warmup_cycle 7275068000 # Cycle when the warmup percentage was hit. 830system.cpu0.icache.occ_blocks::cpu0.inst 511.577657 # Average occupied blocks per requestor 831system.cpu0.icache.occ_percent::cpu0.inst 0.999175 # Average percentage of cache occupancy 832system.cpu0.icache.occ_percent::total 0.999175 # Average percentage of cache occupancy 833system.cpu0.icache.ReadReq_hits::cpu0.inst 3982592 # number of ReadReq hits 834system.cpu0.icache.ReadReq_hits::total 3982592 # number of ReadReq hits 835system.cpu0.icache.demand_hits::cpu0.inst 3982592 # number of demand (read+write) hits 836system.cpu0.icache.demand_hits::total 3982592 # number of demand (read+write) hits 837system.cpu0.icache.overall_hits::cpu0.inst 3982592 # number of overall hits 838system.cpu0.icache.overall_hits::total 3982592 # number of overall hits 839system.cpu0.icache.ReadReq_misses::cpu0.inst 441782 # number of ReadReq misses 840system.cpu0.icache.ReadReq_misses::total 441782 # number of ReadReq misses 841system.cpu0.icache.demand_misses::cpu0.inst 441782 # number of demand (read+write) misses 842system.cpu0.icache.demand_misses::total 441782 # number of demand (read+write) misses 843system.cpu0.icache.overall_misses::cpu0.inst 441782 # number of overall misses 844system.cpu0.icache.overall_misses::total 441782 # number of overall misses 845system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7132710997 # number of ReadReq miss cycles 846system.cpu0.icache.ReadReq_miss_latency::total 7132710997 # number of ReadReq miss cycles 847system.cpu0.icache.demand_miss_latency::cpu0.inst 7132710997 # number of demand (read+write) miss cycles 848system.cpu0.icache.demand_miss_latency::total 7132710997 # number of demand (read+write) miss cycles 849system.cpu0.icache.overall_miss_latency::cpu0.inst 7132710997 # number of overall miss cycles 850system.cpu0.icache.overall_miss_latency::total 7132710997 # number of overall miss cycles 851system.cpu0.icache.ReadReq_accesses::cpu0.inst 4424374 # number of ReadReq accesses(hits+misses) 852system.cpu0.icache.ReadReq_accesses::total 4424374 # number of ReadReq accesses(hits+misses) 853system.cpu0.icache.demand_accesses::cpu0.inst 4424374 # number of demand (read+write) accesses 854system.cpu0.icache.demand_accesses::total 4424374 # number of demand (read+write) accesses 855system.cpu0.icache.overall_accesses::cpu0.inst 4424374 # number of overall (read+write) accesses 856system.cpu0.icache.overall_accesses::total 4424374 # number of overall (read+write) accesses 857system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099852 # miss rate for ReadReq accesses 858system.cpu0.icache.ReadReq_miss_rate::total 0.099852 # miss rate for ReadReq accesses 859system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099852 # miss rate for demand accesses 860system.cpu0.icache.demand_miss_rate::total 0.099852 # miss rate for demand accesses 861system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099852 # miss rate for overall accesses 862system.cpu0.icache.overall_miss_rate::total 0.099852 # miss rate for overall accesses 863system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16145.318272 # average ReadReq miss latency 864system.cpu0.icache.ReadReq_avg_miss_latency::total 16145.318272 # average ReadReq miss latency 865system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16145.318272 # average overall miss latency 866system.cpu0.icache.demand_avg_miss_latency::total 16145.318272 # average overall miss latency 867system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16145.318272 # average overall miss latency 868system.cpu0.icache.overall_avg_miss_latency::total 16145.318272 # average overall miss latency 869system.cpu0.icache.blocked_cycles::no_mshrs 1383498 # number of cycles access was blocked 870system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 871system.cpu0.icache.blocked::no_mshrs 169 # number of cycles access was blocked 872system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 873system.cpu0.icache.avg_blocked_cycles::no_mshrs 8186.378698 # average number of cycles each access was blocked 874system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 875system.cpu0.icache.fast_writes 0 # number of fast writes performed 876system.cpu0.icache.cache_copies 0 # number of cache copies performed 877system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33988 # number of ReadReq MSHR hits 878system.cpu0.icache.ReadReq_mshr_hits::total 33988 # number of ReadReq MSHR hits 879system.cpu0.icache.demand_mshr_hits::cpu0.inst 33988 # number of demand (read+write) MSHR hits 880system.cpu0.icache.demand_mshr_hits::total 33988 # number of demand (read+write) MSHR hits 881system.cpu0.icache.overall_mshr_hits::cpu0.inst 33988 # number of overall MSHR hits 882system.cpu0.icache.overall_mshr_hits::total 33988 # number of overall MSHR hits 883system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 407794 # number of ReadReq MSHR misses 884system.cpu0.icache.ReadReq_mshr_misses::total 407794 # number of ReadReq MSHR misses 885system.cpu0.icache.demand_mshr_misses::cpu0.inst 407794 # number of demand (read+write) MSHR misses 886system.cpu0.icache.demand_mshr_misses::total 407794 # number of demand (read+write) MSHR misses 887system.cpu0.icache.overall_mshr_misses::cpu0.inst 407794 # number of overall MSHR misses 888system.cpu0.icache.overall_mshr_misses::total 407794 # number of overall MSHR misses 889system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5471235499 # number of ReadReq MSHR miss cycles 890system.cpu0.icache.ReadReq_mshr_miss_latency::total 5471235499 # number of ReadReq MSHR miss cycles 891system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5471235499 # number of demand (read+write) MSHR miss cycles 892system.cpu0.icache.demand_mshr_miss_latency::total 5471235499 # number of demand (read+write) MSHR miss cycles 893system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5471235499 # number of overall MSHR miss cycles 894system.cpu0.icache.overall_mshr_miss_latency::total 5471235499 # number of overall MSHR miss cycles 895system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8379000 # number of ReadReq MSHR uncacheable cycles 896system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8379000 # number of ReadReq MSHR uncacheable cycles 897system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8379000 # number of overall MSHR uncacheable cycles 898system.cpu0.icache.overall_mshr_uncacheable_latency::total 8379000 # number of overall MSHR uncacheable cycles 899system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for ReadReq accesses 900system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092170 # mshr miss rate for ReadReq accesses 901system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for demand accesses 902system.cpu0.icache.demand_mshr_miss_rate::total 0.092170 # mshr miss rate for demand accesses 903system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for overall accesses 904system.cpu0.icache.overall_mshr_miss_rate::total 0.092170 # mshr miss rate for overall accesses 905system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13416.665029 # average ReadReq mshr miss latency 906system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13416.665029 # average ReadReq mshr miss latency 907system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13416.665029 # average overall mshr miss latency 908system.cpu0.icache.demand_avg_mshr_miss_latency::total 13416.665029 # average overall mshr miss latency 909system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13416.665029 # average overall mshr miss latency 910system.cpu0.icache.overall_avg_mshr_miss_latency::total 13416.665029 # average overall mshr miss latency 911system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 912system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 913system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 914system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 915system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 916system.cpu0.dcache.replacements 275687 # number of replacements 917system.cpu0.dcache.tagsinuse 476.019935 # Cycle average of tags in use 918system.cpu0.dcache.total_refs 9558592 # Total number of references to valid blocks. 919system.cpu0.dcache.sampled_refs 276199 # Sample count of references to valid blocks. 920system.cpu0.dcache.avg_refs 34.607627 # Average number of references to valid blocks. 921system.cpu0.dcache.warmup_cycle 51448000 # Cycle when the warmup percentage was hit. 922system.cpu0.dcache.occ_blocks::cpu0.data 476.019935 # Average occupied blocks per requestor 923system.cpu0.dcache.occ_percent::cpu0.data 0.929726 # Average percentage of cache occupancy 924system.cpu0.dcache.occ_percent::total 0.929726 # Average percentage of cache occupancy 925system.cpu0.dcache.ReadReq_hits::cpu0.data 5937166 # number of ReadReq hits 926system.cpu0.dcache.ReadReq_hits::total 5937166 # number of ReadReq hits 927system.cpu0.dcache.WriteReq_hits::cpu0.data 3229422 # number of WriteReq hits 928system.cpu0.dcache.WriteReq_hits::total 3229422 # number of WriteReq hits 929system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174299 # number of LoadLockedReq hits 930system.cpu0.dcache.LoadLockedReq_hits::total 174299 # number of LoadLockedReq hits 931system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171559 # number of StoreCondReq hits 932system.cpu0.dcache.StoreCondReq_hits::total 171559 # number of StoreCondReq hits 933system.cpu0.dcache.demand_hits::cpu0.data 9166588 # number of demand (read+write) hits 934system.cpu0.dcache.demand_hits::total 9166588 # number of demand (read+write) hits 935system.cpu0.dcache.overall_hits::cpu0.data 9166588 # number of overall hits 936system.cpu0.dcache.overall_hits::total 9166588 # number of overall hits 937system.cpu0.dcache.ReadReq_misses::cpu0.data 401556 # number of ReadReq misses 938system.cpu0.dcache.ReadReq_misses::total 401556 # number of ReadReq misses 939system.cpu0.dcache.WriteReq_misses::cpu0.data 1594295 # number of WriteReq misses 940system.cpu0.dcache.WriteReq_misses::total 1594295 # number of WriteReq misses 941system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9014 # number of LoadLockedReq misses 942system.cpu0.dcache.LoadLockedReq_misses::total 9014 # number of LoadLockedReq misses 943system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7780 # number of StoreCondReq misses 944system.cpu0.dcache.StoreCondReq_misses::total 7780 # number of StoreCondReq misses 945system.cpu0.dcache.demand_misses::cpu0.data 1995851 # number of demand (read+write) misses 946system.cpu0.dcache.demand_misses::total 1995851 # number of demand (read+write) misses 947system.cpu0.dcache.overall_misses::cpu0.data 1995851 # number of overall misses 948system.cpu0.dcache.overall_misses::total 1995851 # number of overall misses 949system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7292954000 # number of ReadReq miss cycles 950system.cpu0.dcache.ReadReq_miss_latency::total 7292954000 # number of ReadReq miss cycles 951system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71657694355 # number of WriteReq miss cycles 952system.cpu0.dcache.WriteReq_miss_latency::total 71657694355 # number of WriteReq miss cycles 953system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 113831500 # number of LoadLockedReq miss cycles 954system.cpu0.dcache.LoadLockedReq_miss_latency::total 113831500 # number of LoadLockedReq miss cycles 955system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 90370500 # number of StoreCondReq miss cycles 956system.cpu0.dcache.StoreCondReq_miss_latency::total 90370500 # number of StoreCondReq miss cycles 957system.cpu0.dcache.demand_miss_latency::cpu0.data 78950648355 # number of demand (read+write) miss cycles 958system.cpu0.dcache.demand_miss_latency::total 78950648355 # number of demand (read+write) miss cycles 959system.cpu0.dcache.overall_miss_latency::cpu0.data 78950648355 # number of overall miss cycles 960system.cpu0.dcache.overall_miss_latency::total 78950648355 # number of overall miss cycles 961system.cpu0.dcache.ReadReq_accesses::cpu0.data 6338722 # number of ReadReq accesses(hits+misses) 962system.cpu0.dcache.ReadReq_accesses::total 6338722 # number of ReadReq accesses(hits+misses) 963system.cpu0.dcache.WriteReq_accesses::cpu0.data 4823717 # number of WriteReq accesses(hits+misses) 964system.cpu0.dcache.WriteReq_accesses::total 4823717 # number of WriteReq accesses(hits+misses) 965system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183313 # number of LoadLockedReq accesses(hits+misses) 966system.cpu0.dcache.LoadLockedReq_accesses::total 183313 # number of LoadLockedReq accesses(hits+misses) 967system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179339 # number of StoreCondReq accesses(hits+misses) 968system.cpu0.dcache.StoreCondReq_accesses::total 179339 # number of StoreCondReq accesses(hits+misses) 969system.cpu0.dcache.demand_accesses::cpu0.data 11162439 # number of demand (read+write) accesses 970system.cpu0.dcache.demand_accesses::total 11162439 # number of demand (read+write) accesses 971system.cpu0.dcache.overall_accesses::cpu0.data 11162439 # number of overall (read+write) accesses 972system.cpu0.dcache.overall_accesses::total 11162439 # number of overall (read+write) accesses 973system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063350 # miss rate for ReadReq accesses 974system.cpu0.dcache.ReadReq_miss_rate::total 0.063350 # miss rate for ReadReq accesses 975system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330512 # miss rate for WriteReq accesses 976system.cpu0.dcache.WriteReq_miss_rate::total 0.330512 # miss rate for WriteReq accesses 977system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.049173 # miss rate for LoadLockedReq accesses 978system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.049173 # miss rate for LoadLockedReq accesses 979system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043382 # miss rate for StoreCondReq accesses 980system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043382 # miss rate for StoreCondReq accesses 981system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178801 # miss rate for demand accesses 982system.cpu0.dcache.demand_miss_rate::total 0.178801 # miss rate for demand accesses 983system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178801 # miss rate for overall accesses 984system.cpu0.dcache.overall_miss_rate::total 0.178801 # miss rate for overall accesses 985system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18161.735848 # average ReadReq miss latency 986system.cpu0.dcache.ReadReq_avg_miss_latency::total 18161.735848 # average ReadReq miss latency 987system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44946.320697 # average WriteReq miss latency 988system.cpu0.dcache.WriteReq_avg_miss_latency::total 44946.320697 # average WriteReq miss latency 989system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12628.300422 # average LoadLockedReq miss latency 990system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12628.300422 # average LoadLockedReq miss latency 991system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11615.745501 # average StoreCondReq miss latency 992system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11615.745501 # average StoreCondReq miss latency 993system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39557.385975 # average overall miss latency 994system.cpu0.dcache.demand_avg_miss_latency::total 39557.385975 # average overall miss latency 995system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39557.385975 # average overall miss latency 996system.cpu0.dcache.overall_avg_miss_latency::total 39557.385975 # average overall miss latency 997system.cpu0.dcache.blocked_cycles::no_mshrs 7317992 # number of cycles access was blocked 998system.cpu0.dcache.blocked_cycles::no_targets 1712000 # number of cycles access was blocked 999system.cpu0.dcache.blocked::no_mshrs 1467 # number of cycles access was blocked 1000system.cpu0.dcache.blocked::no_targets 85 # number of cycles access was blocked 1001system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4988.406271 # average number of cycles each access was blocked 1002system.cpu0.dcache.avg_blocked_cycles::no_targets 20141.176471 # average number of cycles each access was blocked 1003system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1004system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1005system.cpu0.dcache.writebacks::writebacks 255942 # number of writebacks 1006system.cpu0.dcache.writebacks::total 255942 # number of writebacks 1007system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 212150 # number of ReadReq MSHR hits 1008system.cpu0.dcache.ReadReq_mshr_hits::total 212150 # number of ReadReq MSHR hits 1009system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1463164 # number of WriteReq MSHR hits 1010system.cpu0.dcache.WriteReq_mshr_hits::total 1463164 # number of WriteReq MSHR hits 1011system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 530 # number of LoadLockedReq MSHR hits 1012system.cpu0.dcache.LoadLockedReq_mshr_hits::total 530 # number of LoadLockedReq MSHR hits 1013system.cpu0.dcache.demand_mshr_hits::cpu0.data 1675314 # number of demand (read+write) MSHR hits 1014system.cpu0.dcache.demand_mshr_hits::total 1675314 # number of demand (read+write) MSHR hits 1015system.cpu0.dcache.overall_mshr_hits::cpu0.data 1675314 # number of overall MSHR hits 1016system.cpu0.dcache.overall_mshr_hits::total 1675314 # number of overall MSHR hits 1017system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189406 # number of ReadReq MSHR misses 1018system.cpu0.dcache.ReadReq_mshr_misses::total 189406 # number of ReadReq MSHR misses 1019system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131131 # number of WriteReq MSHR misses 1020system.cpu0.dcache.WriteReq_mshr_misses::total 131131 # number of WriteReq MSHR misses 1021system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8484 # number of LoadLockedReq MSHR misses 1022system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8484 # number of LoadLockedReq MSHR misses 1023system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7773 # number of StoreCondReq MSHR misses 1024system.cpu0.dcache.StoreCondReq_mshr_misses::total 7773 # number of StoreCondReq MSHR misses 1025system.cpu0.dcache.demand_mshr_misses::cpu0.data 320537 # number of demand (read+write) MSHR misses 1026system.cpu0.dcache.demand_mshr_misses::total 320537 # number of demand (read+write) MSHR misses 1027system.cpu0.dcache.overall_mshr_misses::cpu0.data 320537 # number of overall MSHR misses 1028system.cpu0.dcache.overall_mshr_misses::total 320537 # number of overall MSHR misses 1029system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2811014487 # number of ReadReq MSHR miss cycles 1030system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2811014487 # number of ReadReq MSHR miss cycles 1031system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4674099005 # number of WriteReq MSHR miss cycles 1032system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4674099005 # number of WriteReq MSHR miss cycles 1033system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79244002 # number of LoadLockedReq MSHR miss cycles 1034system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79244002 # number of LoadLockedReq MSHR miss cycles 1035system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 65918035 # number of StoreCondReq MSHR miss cycles 1036system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 65918035 # number of StoreCondReq MSHR miss cycles 1037system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles 1038system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 1039system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7485113492 # number of demand (read+write) MSHR miss cycles 1040system.cpu0.dcache.demand_mshr_miss_latency::total 7485113492 # number of demand (read+write) MSHR miss cycles 1041system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7485113492 # number of overall MSHR miss cycles 1042system.cpu0.dcache.overall_mshr_miss_latency::total 7485113492 # number of overall MSHR miss cycles 1043system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13455989500 # number of ReadReq MSHR uncacheable cycles 1044system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13455989500 # number of ReadReq MSHR uncacheable cycles 1045system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1298746899 # number of WriteReq MSHR uncacheable cycles 1046system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1298746899 # number of WriteReq MSHR uncacheable cycles 1047system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14754736399 # number of overall MSHR uncacheable cycles 1048system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14754736399 # number of overall MSHR uncacheable cycles 1049system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029881 # mshr miss rate for ReadReq accesses 1050system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029881 # mshr miss rate for ReadReq accesses 1051system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027185 # mshr miss rate for WriteReq accesses 1052system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027185 # mshr miss rate for WriteReq accesses 1053system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046281 # mshr miss rate for LoadLockedReq accesses 1054system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046281 # mshr miss rate for LoadLockedReq accesses 1055system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043342 # mshr miss rate for StoreCondReq accesses 1056system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043342 # mshr miss rate for StoreCondReq accesses 1057system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028716 # mshr miss rate for demand accesses 1058system.cpu0.dcache.demand_mshr_miss_rate::total 0.028716 # mshr miss rate for demand accesses 1059system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028716 # mshr miss rate for overall accesses 1060system.cpu0.dcache.overall_mshr_miss_rate::total 0.028716 # mshr miss rate for overall accesses 1061system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14841.211403 # average ReadReq mshr miss latency 1062system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14841.211403 # average ReadReq mshr miss latency 1063system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35644.500576 # average WriteReq mshr miss latency 1064system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35644.500576 # average WriteReq mshr miss latency 1065system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9340.405705 # average LoadLockedReq mshr miss latency 1066system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9340.405705 # average LoadLockedReq mshr miss latency 1067system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8480.385308 # average StoreCondReq mshr miss latency 1068system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8480.385308 # average StoreCondReq mshr miss latency 1069system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1070system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1071system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23351.792436 # average overall mshr miss latency 1072system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23351.792436 # average overall mshr miss latency 1073system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23351.792436 # average overall mshr miss latency 1074system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23351.792436 # average overall mshr miss latency 1075system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1076system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1077system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1078system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1079system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1080system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1081system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1082system.cpu1.dtb.inst_hits 0 # ITB inst hits 1083system.cpu1.dtb.inst_misses 0 # ITB inst misses 1084system.cpu1.dtb.read_hits 43452334 # DTB read hits 1085system.cpu1.dtb.read_misses 46277 # DTB read misses 1086system.cpu1.dtb.write_hits 7091337 # DTB write hits 1087system.cpu1.dtb.write_misses 12150 # DTB write misses 1088system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1089system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1090system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1091system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1092system.cpu1.dtb.flush_entries 2524 # Number of entries that have been flushed from TLB 1093system.cpu1.dtb.align_faults 3762 # Number of TLB faults due to alignment restrictions 1094system.cpu1.dtb.prefetch_faults 371 # Number of TLB faults due to prefetch 1095system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1096system.cpu1.dtb.perms_faults 692 # Number of TLB faults due to permissions restrictions 1097system.cpu1.dtb.read_accesses 43498611 # DTB read accesses 1098system.cpu1.dtb.write_accesses 7103487 # DTB write accesses 1099system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1100system.cpu1.dtb.hits 50543671 # DTB hits 1101system.cpu1.dtb.misses 58427 # DTB misses 1102system.cpu1.dtb.accesses 50602098 # DTB accesses 1103system.cpu1.itb.inst_hits 9232744 # ITB inst hits 1104system.cpu1.itb.inst_misses 6115 # ITB inst misses 1105system.cpu1.itb.read_hits 0 # DTB read hits 1106system.cpu1.itb.read_misses 0 # DTB read misses 1107system.cpu1.itb.write_hits 0 # DTB write hits 1108system.cpu1.itb.write_misses 0 # DTB write misses 1109system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1110system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1111system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1112system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1113system.cpu1.itb.flush_entries 1606 # Number of entries that have been flushed from TLB 1114system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1115system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1116system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1117system.cpu1.itb.perms_faults 1727 # Number of TLB faults due to permissions restrictions 1118system.cpu1.itb.read_accesses 0 # DTB read accesses 1119system.cpu1.itb.write_accesses 0 # DTB write accesses 1120system.cpu1.itb.inst_accesses 9238859 # ITB inst accesses 1121system.cpu1.itb.hits 9232744 # DTB hits 1122system.cpu1.itb.misses 6115 # DTB misses 1123system.cpu1.itb.accesses 9238859 # DTB accesses 1124system.cpu1.numCycles 420389270 # number of cpu cycles simulated 1125system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1126system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1127system.cpu1.BPredUnit.lookups 9847995 # Number of BP lookups 1128system.cpu1.BPredUnit.condPredicted 8081754 # Number of conditional branches predicted 1129system.cpu1.BPredUnit.condIncorrect 448433 # Number of conditional branches incorrect 1130system.cpu1.BPredUnit.BTBLookups 6818773 # Number of BTB lookups 1131system.cpu1.BPredUnit.BTBHits 5657403 # Number of BTB hits 1132system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1133system.cpu1.BPredUnit.usedRAS 833939 # Number of times the RAS was used to get a target. 1134system.cpu1.BPredUnit.RASInCorrect 50420 # Number of incorrect RAS predictions. 1135system.cpu1.fetch.icacheStallCycles 22177481 # Number of cycles fetch is stalled on an Icache miss 1136system.cpu1.fetch.Insts 71987538 # Number of instructions fetch has processed 1137system.cpu1.fetch.Branches 9847995 # Number of branches that fetch encountered 1138system.cpu1.fetch.predictedBranches 6491342 # Number of branches that fetch has predicted taken 1139system.cpu1.fetch.Cycles 15338669 # Number of cycles fetch has run and was not squashing or blocked 1140system.cpu1.fetch.SquashCycles 4640041 # Number of cycles fetch has spent squashing 1141system.cpu1.fetch.TlbCycles 86616 # Number of cycles fetch has spent waiting for tlb 1142system.cpu1.fetch.BlockedCycles 81067805 # Number of cycles fetch has spent blocked 1143system.cpu1.fetch.MiscStallCycles 5869 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1144system.cpu1.fetch.PendingTrapStallCycles 63713 # Number of stall cycles due to pending traps 1145system.cpu1.fetch.PendingQuiesceStallCycles 142087 # Number of stall cycles due to pending quiesce instructions 1146system.cpu1.fetch.IcacheWaitRetryStallCycles 99 # Number of stall cycles due to full MSHR 1147system.cpu1.fetch.CacheLines 9230611 # Number of cache lines fetched 1148system.cpu1.fetch.IcacheSquashes 860735 # Number of outstanding Icache misses that were squashed 1149system.cpu1.fetch.ItlbSquashes 3603 # Number of outstanding ITLB misses that were squashed 1150system.cpu1.fetch.rateDist::samples 122048207 # Number of instructions fetched each cycle (Total) 1151system.cpu1.fetch.rateDist::mean 0.712843 # Number of instructions fetched each cycle (Total) 1152system.cpu1.fetch.rateDist::stdev 2.062128 # Number of instructions fetched each cycle (Total) 1153system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1154system.cpu1.fetch.rateDist::0 106717875 87.44% 87.44% # Number of instructions fetched each cycle (Total) 1155system.cpu1.fetch.rateDist::1 829211 0.68% 88.12% # Number of instructions fetched each cycle (Total) 1156system.cpu1.fetch.rateDist::2 1015415 0.83% 88.95% # Number of instructions fetched each cycle (Total) 1157system.cpu1.fetch.rateDist::3 2063306 1.69% 90.64% # Number of instructions fetched each cycle (Total) 1158system.cpu1.fetch.rateDist::4 1641471 1.34% 91.99% # Number of instructions fetched each cycle (Total) 1159system.cpu1.fetch.rateDist::5 615009 0.50% 92.49% # Number of instructions fetched each cycle (Total) 1160system.cpu1.fetch.rateDist::6 2274741 1.86% 94.35% # Number of instructions fetched each cycle (Total) 1161system.cpu1.fetch.rateDist::7 467540 0.38% 94.74% # Number of instructions fetched each cycle (Total) 1162system.cpu1.fetch.rateDist::8 6423639 5.26% 100.00% # Number of instructions fetched each cycle (Total) 1163system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1164system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1165system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1166system.cpu1.fetch.rateDist::total 122048207 # Number of instructions fetched each cycle (Total) 1167system.cpu1.fetch.branchRate 0.023426 # Number of branch fetches per cycle 1168system.cpu1.fetch.rate 0.171240 # Number of inst fetches per cycle 1169system.cpu1.decode.IdleCycles 23807304 # Number of cycles decode is idle 1170system.cpu1.decode.BlockedCycles 80829213 # Number of cycles decode is blocked 1171system.cpu1.decode.RunCycles 13786228 # Number of cycles decode is running 1172system.cpu1.decode.UnblockCycles 560401 # Number of cycles decode is unblocking 1173system.cpu1.decode.SquashCycles 3065061 # Number of cycles decode is squashing 1174system.cpu1.decode.BranchResolved 1241341 # Number of times decode resolved a branch 1175system.cpu1.decode.BranchMispred 102643 # Number of times decode detected a branch misprediction 1176system.cpu1.decode.DecodedInsts 81234919 # Number of instructions handled by decode 1177system.cpu1.decode.SquashedInsts 343119 # Number of squashed instructions handled by decode 1178system.cpu1.rename.SquashCycles 3065061 # Number of cycles rename is squashing 1179system.cpu1.rename.IdleCycles 25364340 # Number of cycles rename is idle 1180system.cpu1.rename.BlockCycles 34010393 # Number of cycles rename is blocking 1181system.cpu1.rename.serializeStallCycles 42304537 # count of cycles rename stalled for serializing inst 1182system.cpu1.rename.RunCycles 12707018 # Number of cycles rename is running 1183system.cpu1.rename.UnblockCycles 4596858 # Number of cycles rename is unblocking 1184system.cpu1.rename.RenamedInsts 74746383 # Number of instructions processed by rename 1185system.cpu1.rename.ROBFullEvents 20429 # Number of times rename has blocked due to ROB full 1186system.cpu1.rename.IQFullEvents 720817 # Number of times rename has blocked due to IQ full 1187system.cpu1.rename.LSQFullEvents 3279864 # Number of times rename has blocked due to LSQ full 1188system.cpu1.rename.FullRegisterEvents 33412 # Number of times there has been no free registers 1189system.cpu1.rename.RenamedOperands 79106997 # Number of destination operands rename has renamed 1190system.cpu1.rename.RenameLookups 344419030 # Number of register rename lookups that rename has made 1191system.cpu1.rename.int_rename_lookups 344359691 # Number of integer rename lookups 1192system.cpu1.rename.fp_rename_lookups 59339 # Number of floating rename lookups 1193system.cpu1.rename.CommittedMaps 50193146 # Number of HB maps that are committed 1194system.cpu1.rename.UndoneMaps 28913851 # Number of HB maps that are undone due to squashing 1195system.cpu1.rename.serializingInsts 487769 # count of serializing insts renamed 1196system.cpu1.rename.tempSerializingInsts 421850 # count of temporary serializing insts renamed 1197system.cpu1.rename.skidInsts 8399849 # count of insts added to the skid buffer 1198system.cpu1.memDep0.insertedLoads 14034972 # Number of loads inserted to the mem dependence unit. 1199system.cpu1.memDep0.insertedStores 8614706 # Number of stores inserted to the mem dependence unit. 1200system.cpu1.memDep0.conflictingLoads 1072487 # Number of conflicting loads. 1201system.cpu1.memDep0.conflictingStores 1529720 # Number of conflicting stores. 1202system.cpu1.iq.iqInstsAdded 67446295 # Number of instructions added to the IQ (excludes non-spec) 1203system.cpu1.iq.iqNonSpecInstsAdded 1206628 # Number of non-speculative instructions added to the IQ 1204system.cpu1.iq.iqInstsIssued 91979521 # Number of instructions issued 1205system.cpu1.iq.iqSquashedInstsIssued 109681 # Number of squashed instructions issued 1206system.cpu1.iq.iqSquashedInstsExamined 18910261 # Number of squashed instructions iterated over during squash; mainly for profiling 1207system.cpu1.iq.iqSquashedOperandsExamined 53596675 # Number of squashed operands that are examined and possibly removed from graph 1208system.cpu1.iq.iqSquashedNonSpecRemoved 286825 # Number of squashed non-spec instructions that were removed 1209system.cpu1.iq.issued_per_cycle::samples 122048207 # Number of insts issued each cycle 1210system.cpu1.iq.issued_per_cycle::mean 0.753633 # Number of insts issued each cycle 1211system.cpu1.iq.issued_per_cycle::stdev 1.492572 # Number of insts issued each cycle 1212system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1213system.cpu1.iq.issued_per_cycle::0 90230410 73.93% 73.93% # Number of insts issued each cycle 1214system.cpu1.iq.issued_per_cycle::1 9124502 7.48% 81.41% # Number of insts issued each cycle 1215system.cpu1.iq.issued_per_cycle::2 4577298 3.75% 85.16% # Number of insts issued each cycle 1216system.cpu1.iq.issued_per_cycle::3 4017634 3.29% 88.45% # Number of insts issued each cycle 1217system.cpu1.iq.issued_per_cycle::4 10703333 8.77% 97.22% # Number of insts issued each cycle 1218system.cpu1.iq.issued_per_cycle::5 1977632 1.62% 98.84% # Number of insts issued each cycle 1219system.cpu1.iq.issued_per_cycle::6 1055737 0.87% 99.70% # Number of insts issued each cycle 1220system.cpu1.iq.issued_per_cycle::7 281681 0.23% 99.93% # Number of insts issued each cycle 1221system.cpu1.iq.issued_per_cycle::8 79980 0.07% 100.00% # Number of insts issued each cycle 1222system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1223system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1224system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1225system.cpu1.iq.issued_per_cycle::total 122048207 # Number of insts issued each cycle 1226system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1227system.cpu1.iq.fu_full::IntAlu 28913 0.37% 0.37% # attempts to use FU when none available 1228system.cpu1.iq.fu_full::IntMult 998 0.01% 0.38% # attempts to use FU when none available 1229system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available 1230system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available 1231system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available 1232system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available 1233system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available 1234system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available 1235system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available 1236system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available 1237system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available 1238system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available 1239system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available 1240system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available 1241system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available 1242system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available 1243system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available 1244system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available 1245system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available 1246system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available 1247system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available 1248system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available 1249system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available 1250system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available 1251system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available 1252system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available 1253system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available 1254system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available 1255system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available 1256system.cpu1.iq.fu_full::MemRead 7574685 95.84% 96.22% # attempts to use FU when none available 1257system.cpu1.iq.fu_full::MemWrite 298874 3.78% 100.00% # attempts to use FU when none available 1258system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1259system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1260system.cpu1.iq.FU_type_0::No_OpClass 313737 0.34% 0.34% # Type of FU issued 1261system.cpu1.iq.FU_type_0::IntAlu 39479578 42.92% 43.26% # Type of FU issued 1262system.cpu1.iq.FU_type_0::IntMult 61492 0.07% 43.33% # Type of FU issued 1263system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.33% # Type of FU issued 1264system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.33% # Type of FU issued 1265system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.33% # Type of FU issued 1266system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.33% # Type of FU issued 1267system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.33% # Type of FU issued 1268system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.33% # Type of FU issued 1269system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.33% # Type of FU issued 1270system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.33% # Type of FU issued 1271system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.33% # Type of FU issued 1272system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.33% # Type of FU issued 1273system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.33% # Type of FU issued 1274system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.33% # Type of FU issued 1275system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 43.33% # Type of FU issued 1276system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.33% # Type of FU issued 1277system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.33% # Type of FU issued 1278system.cpu1.iq.FU_type_0::SimdShift 6 0.00% 43.33% # Type of FU issued 1279system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 43.33% # Type of FU issued 1280system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.33% # Type of FU issued 1281system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.33% # Type of FU issued 1282system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.33% # Type of FU issued 1283system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.33% # Type of FU issued 1284system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.33% # Type of FU issued 1285system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.33% # Type of FU issued 1286system.cpu1.iq.FU_type_0::SimdFloatMisc 1697 0.00% 43.33% # Type of FU issued 1287system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.33% # Type of FU issued 1288system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 43.33% # Type of FU issued 1289system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.33% # Type of FU issued 1290system.cpu1.iq.FU_type_0::MemRead 44651207 48.54% 91.88% # Type of FU issued 1291system.cpu1.iq.FU_type_0::MemWrite 7471778 8.12% 100.00% # Type of FU issued 1292system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1293system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1294system.cpu1.iq.FU_type_0::total 91979521 # Type of FU issued 1295system.cpu1.iq.rate 0.218796 # Inst issue rate 1296system.cpu1.iq.fu_busy_cnt 7903470 # FU busy when requested 1297system.cpu1.iq.fu_busy_rate 0.085926 # FU busy rate (busy events/executed inst) 1298system.cpu1.iq.int_inst_queue_reads 314063875 # Number of integer instruction queue reads 1299system.cpu1.iq.int_inst_queue_writes 87576510 # Number of integer instruction queue writes 1300system.cpu1.iq.int_inst_queue_wakeup_accesses 55784562 # Number of integer instruction queue wakeup accesses 1301system.cpu1.iq.fp_inst_queue_reads 14814 # Number of floating instruction queue reads 1302system.cpu1.iq.fp_inst_queue_writes 8109 # Number of floating instruction queue writes 1303system.cpu1.iq.fp_inst_queue_wakeup_accesses 6801 # Number of floating instruction queue wakeup accesses 1304system.cpu1.iq.int_alu_accesses 99561488 # Number of integer alu accesses 1305system.cpu1.iq.fp_alu_accesses 7766 # Number of floating point alu accesses 1306system.cpu1.iew.lsq.thread0.forwLoads 369403 # Number of loads that had data forwarded from stores 1307system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1308system.cpu1.iew.lsq.thread0.squashedLoads 4042367 # Number of loads squashed 1309system.cpu1.iew.lsq.thread0.ignoredResponses 6847 # Number of memory responses ignored because the instruction is squashed 1310system.cpu1.iew.lsq.thread0.memOrderViolation 22042 # Number of memory ordering violations 1311system.cpu1.iew.lsq.thread0.squashedStores 1594624 # Number of stores squashed 1312system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1313system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1314system.cpu1.iew.lsq.thread0.rescheduledLoads 31965742 # Number of loads that were rescheduled 1315system.cpu1.iew.lsq.thread0.cacheBlocked 1047944 # Number of times an access to memory failed due to the cache being blocked 1316system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1317system.cpu1.iew.iewSquashCycles 3065061 # Number of cycles IEW is squashing 1318system.cpu1.iew.iewBlockCycles 25634357 # Number of cycles IEW is blocking 1319system.cpu1.iew.iewUnblockCycles 409319 # Number of cycles IEW is unblocking 1320system.cpu1.iew.iewDispatchedInsts 68777683 # Number of instructions dispatched to IQ 1321system.cpu1.iew.iewDispSquashedInsts 134755 # Number of squashed instructions skipped by dispatch 1322system.cpu1.iew.iewDispLoadInsts 14034972 # Number of dispatched load instructions 1323system.cpu1.iew.iewDispStoreInsts 8614706 # Number of dispatched store instructions 1324system.cpu1.iew.iewDispNonSpecInsts 896270 # Number of dispatched non-speculative instructions 1325system.cpu1.iew.iewIQFullEvents 80399 # Number of times the IQ has become full, causing a stall 1326system.cpu1.iew.iewLSQFullEvents 14951 # Number of times the LSQ has become full, causing a stall 1327system.cpu1.iew.memOrderViolationEvents 22042 # Number of memory order violations 1328system.cpu1.iew.predictedTakenIncorrect 226446 # Number of branches that were predicted taken incorrectly 1329system.cpu1.iew.predictedNotTakenIncorrect 198201 # Number of branches that were predicted not taken incorrectly 1330system.cpu1.iew.branchMispredicts 424647 # Number of branch mispredicts detected at execute 1331system.cpu1.iew.iewExecutedInsts 89117462 # Number of executed instructions 1332system.cpu1.iew.iewExecLoadInsts 43838045 # Number of load instructions executed 1333system.cpu1.iew.iewExecSquashedInsts 2862059 # Number of squashed instructions skipped in execute 1334system.cpu1.iew.exec_swp 0 # number of swp insts executed 1335system.cpu1.iew.exec_nop 124760 # number of nop insts executed 1336system.cpu1.iew.exec_refs 51234744 # number of memory reference insts executed 1337system.cpu1.iew.exec_branches 7395685 # Number of branches executed 1338system.cpu1.iew.exec_stores 7396699 # Number of stores executed 1339system.cpu1.iew.exec_rate 0.211988 # Inst execution rate 1340system.cpu1.iew.wb_sent 87946957 # cumulative count of insts sent to commit 1341system.cpu1.iew.wb_count 55791363 # cumulative count of insts written-back 1342system.cpu1.iew.wb_producers 30796912 # num instructions producing a value 1343system.cpu1.iew.wb_consumers 54575062 # num instructions consuming a value 1344system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 1345system.cpu1.iew.wb_rate 0.132714 # insts written-back per cycle 1346system.cpu1.iew.wb_fanout 0.564304 # average fanout of values written-back 1347system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1350system.cpu1.commit.commitCommittedInsts 38947564 # The number of committed instructions 1351system.cpu1.commit.commitCommittedOps 49311547 # The number of committed instructions
1352system.cpu1.commit.commitSquashedInsts 19037243 # The number of squashed insts skipped by commit 1353system.cpu1.commit.commitNonSpecStalls 919803 # The number of times commit has been forced to stall to communicate backwards 1354system.cpu1.commit.branchMispredicts 377326 # The number of times a branch was mispredicted 1355system.cpu1.commit.committed_per_cycle::samples 119031582 # Number of insts commited each cycle 1356system.cpu1.commit.committed_per_cycle::mean 0.414273 # Number of insts commited each cycle 1357system.cpu1.commit.committed_per_cycle::stdev 1.369590 # Number of insts commited each cycle 1358system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1359system.cpu1.commit.committed_per_cycle::0 101746657 85.48% 85.48% # Number of insts commited each cycle 1360system.cpu1.commit.committed_per_cycle::1 8535054 7.17% 92.65% # Number of insts commited each cycle 1361system.cpu1.commit.committed_per_cycle::2 2209116 1.86% 94.51% # Number of insts commited each cycle 1362system.cpu1.commit.committed_per_cycle::3 1312161 1.10% 95.61% # Number of insts commited each cycle 1363system.cpu1.commit.committed_per_cycle::4 1288209 1.08% 96.69% # Number of insts commited each cycle 1364system.cpu1.commit.committed_per_cycle::5 590684 0.50% 97.19% # Number of insts commited each cycle 1365system.cpu1.commit.committed_per_cycle::6 998098 0.84% 98.02% # Number of insts commited each cycle 1366system.cpu1.commit.committed_per_cycle::7 485890 0.41% 98.43% # Number of insts commited each cycle 1367system.cpu1.commit.committed_per_cycle::8 1865713 1.57% 100.00% # Number of insts commited each cycle 1368system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1369system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1370system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1371system.cpu1.commit.committed_per_cycle::total 119031582 # Number of insts commited each cycle 1372system.cpu1.commit.committedInsts 38947564 # Number of instructions committed 1373system.cpu1.commit.committedOps 49311547 # Number of ops (including micro ops) committed 1374system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1375system.cpu1.commit.refs 17012687 # Number of memory references committed 1376system.cpu1.commit.loads 9992605 # Number of loads committed 1377system.cpu1.commit.membars 202357 # Number of memory barriers committed 1378system.cpu1.commit.branches 6222202 # Number of branches committed 1379system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. 1380system.cpu1.commit.int_insts 43701968 # Number of committed integer instructions. 1381system.cpu1.commit.function_calls 556417 # Number of function calls committed. 1382system.cpu1.commit.bw_lim_events 1865713 # number cycles where commit BW limit reached 1383system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1384system.cpu1.rob.rob_reads 184400014 # The number of ROB reads 1385system.cpu1.rob.rob_writes 139856425 # The number of ROB writes 1386system.cpu1.timesIdled 1519588 # Number of times that the entire CPU went into an idle state and unscheduled itself 1387system.cpu1.idleCycles 298341063 # Total number of cycles that the CPU has spent unscheduled due to idling 1388system.cpu1.quiesceCycles 4812976632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1389system.cpu1.committedInsts 38877925 # Number of Instructions Simulated 1390system.cpu1.committedOps 49241908 # Number of Ops (including micro ops) Simulated 1391system.cpu1.committedInsts_total 38877925 # Number of Instructions Simulated 1392system.cpu1.cpi 10.813058 # CPI: Cycles Per Instruction 1393system.cpu1.cpi_total 10.813058 # CPI: Total CPI of All Threads 1394system.cpu1.ipc 0.092481 # IPC: Instructions Per Cycle 1395system.cpu1.ipc_total 0.092481 # IPC: Total IPC of All Threads 1396system.cpu1.int_regfile_reads 398800057 # number of integer regfile reads 1397system.cpu1.int_regfile_writes 58498146 # number of integer regfile writes 1398system.cpu1.fp_regfile_reads 4943 # number of floating regfile reads 1399system.cpu1.fp_regfile_writes 2344 # number of floating regfile writes 1400system.cpu1.misc_regfile_reads 91875872 # number of misc regfile reads 1401system.cpu1.misc_regfile_writes 429758 # number of misc regfile writes 1402system.cpu1.icache.replacements 623101 # number of replacements 1403system.cpu1.icache.tagsinuse 498.730815 # Cycle average of tags in use 1404system.cpu1.icache.total_refs 8556871 # Total number of references to valid blocks. 1405system.cpu1.icache.sampled_refs 623613 # Sample count of references to valid blocks. 1406system.cpu1.icache.avg_refs 13.721444 # Average number of references to valid blocks. 1407system.cpu1.icache.warmup_cycle 75785780000 # Cycle when the warmup percentage was hit. 1408system.cpu1.icache.occ_blocks::cpu1.inst 498.730815 # Average occupied blocks per requestor 1409system.cpu1.icache.occ_percent::cpu1.inst 0.974084 # Average percentage of cache occupancy 1410system.cpu1.icache.occ_percent::total 0.974084 # Average percentage of cache occupancy 1411system.cpu1.icache.ReadReq_hits::cpu1.inst 8556871 # number of ReadReq hits 1412system.cpu1.icache.ReadReq_hits::total 8556871 # number of ReadReq hits 1413system.cpu1.icache.demand_hits::cpu1.inst 8556871 # number of demand (read+write) hits 1414system.cpu1.icache.demand_hits::total 8556871 # number of demand (read+write) hits 1415system.cpu1.icache.overall_hits::cpu1.inst 8556871 # number of overall hits 1416system.cpu1.icache.overall_hits::total 8556871 # number of overall hits 1417system.cpu1.icache.ReadReq_misses::cpu1.inst 673686 # number of ReadReq misses 1418system.cpu1.icache.ReadReq_misses::total 673686 # number of ReadReq misses 1419system.cpu1.icache.demand_misses::cpu1.inst 673686 # number of demand (read+write) misses 1420system.cpu1.icache.demand_misses::total 673686 # number of demand (read+write) misses 1421system.cpu1.icache.overall_misses::cpu1.inst 673686 # number of overall misses 1422system.cpu1.icache.overall_misses::total 673686 # number of overall misses 1423system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10642693998 # number of ReadReq miss cycles 1424system.cpu1.icache.ReadReq_miss_latency::total 10642693998 # number of ReadReq miss cycles 1425system.cpu1.icache.demand_miss_latency::cpu1.inst 10642693998 # number of demand (read+write) miss cycles 1426system.cpu1.icache.demand_miss_latency::total 10642693998 # number of demand (read+write) miss cycles 1427system.cpu1.icache.overall_miss_latency::cpu1.inst 10642693998 # number of overall miss cycles 1428system.cpu1.icache.overall_miss_latency::total 10642693998 # number of overall miss cycles 1429system.cpu1.icache.ReadReq_accesses::cpu1.inst 9230557 # number of ReadReq accesses(hits+misses) 1430system.cpu1.icache.ReadReq_accesses::total 9230557 # number of ReadReq accesses(hits+misses) 1431system.cpu1.icache.demand_accesses::cpu1.inst 9230557 # number of demand (read+write) accesses 1432system.cpu1.icache.demand_accesses::total 9230557 # number of demand (read+write) accesses 1433system.cpu1.icache.overall_accesses::cpu1.inst 9230557 # number of overall (read+write) accesses 1434system.cpu1.icache.overall_accesses::total 9230557 # number of overall (read+write) accesses 1435system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.072984 # miss rate for ReadReq accesses 1436system.cpu1.icache.ReadReq_miss_rate::total 0.072984 # miss rate for ReadReq accesses 1437system.cpu1.icache.demand_miss_rate::cpu1.inst 0.072984 # miss rate for demand accesses 1438system.cpu1.icache.demand_miss_rate::total 0.072984 # miss rate for demand accesses 1439system.cpu1.icache.overall_miss_rate::cpu1.inst 0.072984 # miss rate for overall accesses 1440system.cpu1.icache.overall_miss_rate::total 0.072984 # miss rate for overall accesses 1441system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15797.706941 # average ReadReq miss latency 1442system.cpu1.icache.ReadReq_avg_miss_latency::total 15797.706941 # average ReadReq miss latency 1443system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15797.706941 # average overall miss latency 1444system.cpu1.icache.demand_avg_miss_latency::total 15797.706941 # average overall miss latency 1445system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15797.706941 # average overall miss latency 1446system.cpu1.icache.overall_avg_miss_latency::total 15797.706941 # average overall miss latency 1447system.cpu1.icache.blocked_cycles::no_mshrs 1133998 # number of cycles access was blocked 1448system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1449system.cpu1.icache.blocked::no_mshrs 174 # number of cycles access was blocked 1450system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1451system.cpu1.icache.avg_blocked_cycles::no_mshrs 6517.229885 # average number of cycles each access was blocked 1452system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1453system.cpu1.icache.fast_writes 0 # number of fast writes performed 1454system.cpu1.icache.cache_copies 0 # number of cache copies performed 1455system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50044 # number of ReadReq MSHR hits 1456system.cpu1.icache.ReadReq_mshr_hits::total 50044 # number of ReadReq MSHR hits 1457system.cpu1.icache.demand_mshr_hits::cpu1.inst 50044 # number of demand (read+write) MSHR hits 1458system.cpu1.icache.demand_mshr_hits::total 50044 # number of demand (read+write) MSHR hits 1459system.cpu1.icache.overall_mshr_hits::cpu1.inst 50044 # number of overall MSHR hits 1460system.cpu1.icache.overall_mshr_hits::total 50044 # number of overall MSHR hits 1461system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 623642 # number of ReadReq MSHR misses 1462system.cpu1.icache.ReadReq_mshr_misses::total 623642 # number of ReadReq MSHR misses 1463system.cpu1.icache.demand_mshr_misses::cpu1.inst 623642 # number of demand (read+write) MSHR misses 1464system.cpu1.icache.demand_mshr_misses::total 623642 # number of demand (read+write) MSHR misses 1465system.cpu1.icache.overall_mshr_misses::cpu1.inst 623642 # number of overall MSHR misses 1466system.cpu1.icache.overall_mshr_misses::total 623642 # number of overall MSHR misses 1467system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8149352498 # number of ReadReq MSHR miss cycles 1468system.cpu1.icache.ReadReq_mshr_miss_latency::total 8149352498 # number of ReadReq MSHR miss cycles 1469system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8149352498 # number of demand (read+write) MSHR miss cycles 1470system.cpu1.icache.demand_mshr_miss_latency::total 8149352498 # number of demand (read+write) MSHR miss cycles 1471system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8149352498 # number of overall MSHR miss cycles 1472system.cpu1.icache.overall_mshr_miss_latency::total 8149352498 # number of overall MSHR miss cycles 1473system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3211500 # number of ReadReq MSHR uncacheable cycles 1474system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3211500 # number of ReadReq MSHR uncacheable cycles 1475system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3211500 # number of overall MSHR uncacheable cycles 1476system.cpu1.icache.overall_mshr_uncacheable_latency::total 3211500 # number of overall MSHR uncacheable cycles 1477system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067563 # mshr miss rate for ReadReq accesses 1478system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067563 # mshr miss rate for ReadReq accesses 1479system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067563 # mshr miss rate for demand accesses 1480system.cpu1.icache.demand_mshr_miss_rate::total 0.067563 # mshr miss rate for demand accesses 1481system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067563 # mshr miss rate for overall accesses 1482system.cpu1.icache.overall_mshr_miss_rate::total 0.067563 # mshr miss rate for overall accesses 1483system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13067.356750 # average ReadReq mshr miss latency 1484system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13067.356750 # average ReadReq mshr miss latency 1485system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13067.356750 # average overall mshr miss latency 1486system.cpu1.icache.demand_avg_mshr_miss_latency::total 13067.356750 # average overall mshr miss latency 1487system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13067.356750 # average overall mshr miss latency 1488system.cpu1.icache.overall_avg_mshr_miss_latency::total 13067.356750 # average overall mshr miss latency 1489system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1490system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1491system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1492system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1493system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1494system.cpu1.dcache.replacements 363581 # number of replacements 1495system.cpu1.dcache.tagsinuse 487.223522 # Cycle average of tags in use 1496system.cpu1.dcache.total_refs 13117187 # Total number of references to valid blocks. 1497system.cpu1.dcache.sampled_refs 363929 # Sample count of references to valid blocks. 1498system.cpu1.dcache.avg_refs 36.043258 # Average number of references to valid blocks. 1499system.cpu1.dcache.warmup_cycle 71474573000 # Cycle when the warmup percentage was hit. 1500system.cpu1.dcache.occ_blocks::cpu1.data 487.223522 # Average occupied blocks per requestor 1501system.cpu1.dcache.occ_percent::cpu1.data 0.951608 # Average percentage of cache occupancy 1502system.cpu1.dcache.occ_percent::total 0.951608 # Average percentage of cache occupancy 1503system.cpu1.dcache.ReadReq_hits::cpu1.data 8616147 # number of ReadReq hits 1504system.cpu1.dcache.ReadReq_hits::total 8616147 # number of ReadReq hits 1505system.cpu1.dcache.WriteReq_hits::cpu1.data 4254446 # number of WriteReq hits 1506system.cpu1.dcache.WriteReq_hits::total 4254446 # number of WriteReq hits 1507system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105790 # number of LoadLockedReq hits 1508system.cpu1.dcache.LoadLockedReq_hits::total 105790 # number of LoadLockedReq hits 1509system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100736 # number of StoreCondReq hits 1510system.cpu1.dcache.StoreCondReq_hits::total 100736 # number of StoreCondReq hits 1511system.cpu1.dcache.demand_hits::cpu1.data 12870593 # number of demand (read+write) hits 1512system.cpu1.dcache.demand_hits::total 12870593 # number of demand (read+write) hits 1513system.cpu1.dcache.overall_hits::cpu1.data 12870593 # number of overall hits 1514system.cpu1.dcache.overall_hits::total 12870593 # number of overall hits 1515system.cpu1.dcache.ReadReq_misses::cpu1.data 410065 # number of ReadReq misses 1516system.cpu1.dcache.ReadReq_misses::total 410065 # number of ReadReq misses 1517system.cpu1.dcache.WriteReq_misses::cpu1.data 1595508 # number of WriteReq misses 1518system.cpu1.dcache.WriteReq_misses::total 1595508 # number of WriteReq misses 1519system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14278 # number of LoadLockedReq misses 1520system.cpu1.dcache.LoadLockedReq_misses::total 14278 # number of LoadLockedReq misses 1521system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10912 # number of StoreCondReq misses 1522system.cpu1.dcache.StoreCondReq_misses::total 10912 # number of StoreCondReq misses 1523system.cpu1.dcache.demand_misses::cpu1.data 2005573 # number of demand (read+write) misses 1524system.cpu1.dcache.demand_misses::total 2005573 # number of demand (read+write) misses 1525system.cpu1.dcache.overall_misses::cpu1.data 2005573 # number of overall misses 1526system.cpu1.dcache.overall_misses::total 2005573 # number of overall misses 1527system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8126055000 # number of ReadReq miss cycles 1528system.cpu1.dcache.ReadReq_miss_latency::total 8126055000 # number of ReadReq miss cycles 1529system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66044305227 # number of WriteReq miss cycles 1530system.cpu1.dcache.WriteReq_miss_latency::total 66044305227 # number of WriteReq miss cycles 1531system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 166791500 # number of LoadLockedReq miss cycles 1532system.cpu1.dcache.LoadLockedReq_miss_latency::total 166791500 # number of LoadLockedReq miss cycles 1533system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 95304000 # number of StoreCondReq miss cycles 1534system.cpu1.dcache.StoreCondReq_miss_latency::total 95304000 # number of StoreCondReq miss cycles 1535system.cpu1.dcache.demand_miss_latency::cpu1.data 74170360227 # number of demand (read+write) miss cycles 1536system.cpu1.dcache.demand_miss_latency::total 74170360227 # number of demand (read+write) miss cycles 1537system.cpu1.dcache.overall_miss_latency::cpu1.data 74170360227 # number of overall miss cycles 1538system.cpu1.dcache.overall_miss_latency::total 74170360227 # number of overall miss cycles 1539system.cpu1.dcache.ReadReq_accesses::cpu1.data 9026212 # number of ReadReq accesses(hits+misses) 1540system.cpu1.dcache.ReadReq_accesses::total 9026212 # number of ReadReq accesses(hits+misses) 1541system.cpu1.dcache.WriteReq_accesses::cpu1.data 5849954 # number of WriteReq accesses(hits+misses) 1542system.cpu1.dcache.WriteReq_accesses::total 5849954 # number of WriteReq accesses(hits+misses) 1543system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 120068 # number of LoadLockedReq accesses(hits+misses) 1544system.cpu1.dcache.LoadLockedReq_accesses::total 120068 # number of LoadLockedReq accesses(hits+misses) 1545system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111648 # number of StoreCondReq accesses(hits+misses) 1546system.cpu1.dcache.StoreCondReq_accesses::total 111648 # number of StoreCondReq accesses(hits+misses) 1547system.cpu1.dcache.demand_accesses::cpu1.data 14876166 # number of demand (read+write) accesses 1548system.cpu1.dcache.demand_accesses::total 14876166 # number of demand (read+write) accesses 1549system.cpu1.dcache.overall_accesses::cpu1.data 14876166 # number of overall (read+write) accesses 1550system.cpu1.dcache.overall_accesses::total 14876166 # number of overall (read+write) accesses 1551system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045430 # miss rate for ReadReq accesses 1552system.cpu1.dcache.ReadReq_miss_rate::total 0.045430 # miss rate for ReadReq accesses 1553system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.272739 # miss rate for WriteReq accesses 1554system.cpu1.dcache.WriteReq_miss_rate::total 0.272739 # miss rate for WriteReq accesses 1555system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118916 # miss rate for LoadLockedReq accesses 1556system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118916 # miss rate for LoadLockedReq accesses 1557system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097736 # miss rate for StoreCondReq accesses 1558system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097736 # miss rate for StoreCondReq accesses 1559system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134818 # miss rate for demand accesses 1560system.cpu1.dcache.demand_miss_rate::total 0.134818 # miss rate for demand accesses 1561system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134818 # miss rate for overall accesses 1562system.cpu1.dcache.overall_miss_rate::total 0.134818 # miss rate for overall accesses 1563system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19816.504700 # average ReadReq miss latency 1564system.cpu1.dcache.ReadReq_avg_miss_latency::total 19816.504700 # average ReadReq miss latency 1565system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41393.904153 # average WriteReq miss latency 1566system.cpu1.dcache.WriteReq_avg_miss_latency::total 41393.904153 # average WriteReq miss latency 1567system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11681.713125 # average LoadLockedReq miss latency 1568system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11681.713125 # average LoadLockedReq miss latency 1569system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8733.870968 # average StoreCondReq miss latency 1570system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8733.870968 # average StoreCondReq miss latency 1571system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 36982.129410 # average overall miss latency 1572system.cpu1.dcache.demand_avg_miss_latency::total 36982.129410 # average overall miss latency 1573system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 36982.129410 # average overall miss latency 1574system.cpu1.dcache.overall_avg_miss_latency::total 36982.129410 # average overall miss latency 1575system.cpu1.dcache.blocked_cycles::no_mshrs 29670016 # number of cycles access was blocked 1576system.cpu1.dcache.blocked_cycles::no_targets 5568500 # number of cycles access was blocked 1577system.cpu1.dcache.blocked::no_mshrs 6658 # number of cycles access was blocked 1578system.cpu1.dcache.blocked::no_targets 173 # number of cycles access was blocked 1579system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4456.295584 # average number of cycles each access was blocked 1580system.cpu1.dcache.avg_blocked_cycles::no_targets 32187.861272 # average number of cycles each access was blocked 1581system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1582system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1583system.cpu1.dcache.writebacks::writebacks 328251 # number of writebacks 1584system.cpu1.dcache.writebacks::total 328251 # number of writebacks 1585system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 178277 # number of ReadReq MSHR hits 1586system.cpu1.dcache.ReadReq_mshr_hits::total 178277 # number of ReadReq MSHR hits 1587system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1432587 # number of WriteReq MSHR hits 1588system.cpu1.dcache.WriteReq_mshr_hits::total 1432587 # number of WriteReq MSHR hits 1589system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1464 # number of LoadLockedReq MSHR hits 1590system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1464 # number of LoadLockedReq MSHR hits 1591system.cpu1.dcache.demand_mshr_hits::cpu1.data 1610864 # number of demand (read+write) MSHR hits 1592system.cpu1.dcache.demand_mshr_hits::total 1610864 # number of demand (read+write) MSHR hits 1593system.cpu1.dcache.overall_mshr_hits::cpu1.data 1610864 # number of overall MSHR hits 1594system.cpu1.dcache.overall_mshr_hits::total 1610864 # number of overall MSHR hits 1595system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231788 # number of ReadReq MSHR misses 1596system.cpu1.dcache.ReadReq_mshr_misses::total 231788 # number of ReadReq MSHR misses 1597system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162921 # number of WriteReq MSHR misses 1598system.cpu1.dcache.WriteReq_mshr_misses::total 162921 # number of WriteReq MSHR misses 1599system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12814 # number of LoadLockedReq MSHR misses 1600system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12814 # number of LoadLockedReq MSHR misses 1601system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10909 # number of StoreCondReq MSHR misses 1602system.cpu1.dcache.StoreCondReq_mshr_misses::total 10909 # number of StoreCondReq MSHR misses 1603system.cpu1.dcache.demand_mshr_misses::cpu1.data 394709 # number of demand (read+write) MSHR misses 1604system.cpu1.dcache.demand_mshr_misses::total 394709 # number of demand (read+write) MSHR misses 1605system.cpu1.dcache.overall_mshr_misses::cpu1.data 394709 # number of overall MSHR misses 1606system.cpu1.dcache.overall_mshr_misses::total 394709 # number of overall MSHR misses 1607system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3566201462 # number of ReadReq MSHR miss cycles 1608system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3566201462 # number of ReadReq MSHR miss cycles 1609system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5537603585 # number of WriteReq MSHR miss cycles 1610system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5537603585 # number of WriteReq MSHR miss cycles 1611system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 104573506 # number of LoadLockedReq MSHR miss cycles 1612system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 104573506 # number of LoadLockedReq MSHR miss cycles 1613system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 61265506 # number of StoreCondReq MSHR miss cycles 1614system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 61265506 # number of StoreCondReq MSHR miss cycles 1615system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles 1616system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles 1617system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9103805047 # number of demand (read+write) MSHR miss cycles 1618system.cpu1.dcache.demand_mshr_miss_latency::total 9103805047 # number of demand (read+write) MSHR miss cycles 1619system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9103805047 # number of overall MSHR miss cycles 1620system.cpu1.dcache.overall_mshr_miss_latency::total 9103805047 # number of overall MSHR miss cycles 1621system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169309741500 # number of ReadReq MSHR uncacheable cycles 1622system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169309741500 # number of ReadReq MSHR uncacheable cycles 1623system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40933880282 # number of WriteReq MSHR uncacheable cycles 1624system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40933880282 # number of WriteReq MSHR uncacheable cycles 1625system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210243621782 # number of overall MSHR uncacheable cycles 1626system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210243621782 # number of overall MSHR uncacheable cycles 1627system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025679 # mshr miss rate for ReadReq accesses 1628system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025679 # mshr miss rate for ReadReq accesses 1629system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027850 # mshr miss rate for WriteReq accesses 1630system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027850 # mshr miss rate for WriteReq accesses 1631system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106723 # mshr miss rate for LoadLockedReq accesses 1632system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106723 # mshr miss rate for LoadLockedReq accesses 1633system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097709 # mshr miss rate for StoreCondReq accesses 1634system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097709 # mshr miss rate for StoreCondReq accesses 1635system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026533 # mshr miss rate for demand accesses 1636system.cpu1.dcache.demand_mshr_miss_rate::total 0.026533 # mshr miss rate for demand accesses 1637system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026533 # mshr miss rate for overall accesses 1638system.cpu1.dcache.overall_mshr_miss_rate::total 0.026533 # mshr miss rate for overall accesses 1639system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15385.617297 # average ReadReq mshr miss latency 1640system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15385.617297 # average ReadReq mshr miss latency 1641system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33989.501568 # average WriteReq mshr miss latency 1642system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33989.501568 # average WriteReq mshr miss latency 1643system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8160.879195 # average LoadLockedReq mshr miss latency 1644system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8160.879195 # average LoadLockedReq mshr miss latency 1645system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5616.051517 # average StoreCondReq mshr miss latency 1646system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5616.051517 # average StoreCondReq mshr miss latency 1647system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1648system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1649system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23064.599609 # average overall mshr miss latency 1650system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23064.599609 # average overall mshr miss latency 1651system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23064.599609 # average overall mshr miss latency 1652system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23064.599609 # average overall mshr miss latency 1653system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1654system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1655system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1656system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1657system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1658system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1659system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1660system.iocache.replacements 0 # number of replacements 1661system.iocache.tagsinuse 0 # Cycle average of tags in use 1662system.iocache.total_refs 0 # Total number of references to valid blocks. 1663system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1664system.iocache.avg_refs nan # Average number of references to valid blocks. 1665system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1666system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1667system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1668system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1669system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1670system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1671system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1672system.iocache.fast_writes 0 # number of fast writes performed 1673system.iocache.cache_copies 0 # number of cache copies performed 1674system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323189312111 # number of ReadReq MSHR uncacheable cycles 1675system.iocache.ReadReq_mshr_uncacheable_latency::total 1323189312111 # number of ReadReq MSHR uncacheable cycles 1676system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323189312111 # number of overall MSHR uncacheable cycles 1677system.iocache.overall_mshr_uncacheable_latency::total 1323189312111 # number of overall MSHR uncacheable cycles 1678system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1679system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1680system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1681system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1682system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1683system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1684system.cpu0.kern.inst.quiesce 43824 # number of quiesce instructions executed 1685system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1686system.cpu1.kern.inst.quiesce 53932 # number of quiesce instructions executed 1687 1688---------- End Simulation Statistics ----------	1348system.cpu1.commit.commitSquashedInsts 19037243 # The number of squashed insts skipped by commit 1349system.cpu1.commit.commitNonSpecStalls 919803 # The number of times commit has been forced to stall to communicate backwards 1350system.cpu1.commit.branchMispredicts 377326 # The number of times a branch was mispredicted 1351system.cpu1.commit.committed_per_cycle::samples 119031582 # Number of insts commited each cycle 1352system.cpu1.commit.committed_per_cycle::mean 0.414273 # Number of insts commited each cycle 1353system.cpu1.commit.committed_per_cycle::stdev 1.369590 # Number of insts commited each cycle 1354system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1355system.cpu1.commit.committed_per_cycle::0 101746657 85.48% 85.48% # Number of insts commited each cycle 1356system.cpu1.commit.committed_per_cycle::1 8535054 7.17% 92.65% # Number of insts commited each cycle 1357system.cpu1.commit.committed_per_cycle::2 2209116 1.86% 94.51% # Number of insts commited each cycle 1358system.cpu1.commit.committed_per_cycle::3 1312161 1.10% 95.61% # Number of insts commited each cycle 1359system.cpu1.commit.committed_per_cycle::4 1288209 1.08% 96.69% # Number of insts commited each cycle 1360system.cpu1.commit.committed_per_cycle::5 590684 0.50% 97.19% # Number of insts commited each cycle 1361system.cpu1.commit.committed_per_cycle::6 998098 0.84% 98.02% # Number of insts commited each cycle 1362system.cpu1.commit.committed_per_cycle::7 485890 0.41% 98.43% # Number of insts commited each cycle 1363system.cpu1.commit.committed_per_cycle::8 1865713 1.57% 100.00% # Number of insts commited each cycle 1364system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1365system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1366system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1367system.cpu1.commit.committed_per_cycle::total 119031582 # Number of insts commited each cycle 1368system.cpu1.commit.committedInsts 38947564 # Number of instructions committed 1369system.cpu1.commit.committedOps 49311547 # Number of ops (including micro ops) committed 1370system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1371system.cpu1.commit.refs 17012687 # Number of memory references committed 1372system.cpu1.commit.loads 9992605 # Number of loads committed 1373system.cpu1.commit.membars 202357 # Number of memory barriers committed 1374system.cpu1.commit.branches 6222202 # Number of branches committed 1375system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. 1376system.cpu1.commit.int_insts 43701968 # Number of committed integer instructions. 1377system.cpu1.commit.function_calls 556417 # Number of function calls committed. 1378system.cpu1.commit.bw_lim_events 1865713 # number cycles where commit BW limit reached 1379system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits 1380system.cpu1.rob.rob_reads 184400014 # The number of ROB reads 1381system.cpu1.rob.rob_writes 139856425 # The number of ROB writes 1382system.cpu1.timesIdled 1519588 # Number of times that the entire CPU went into an idle state and unscheduled itself 1383system.cpu1.idleCycles 298341063 # Total number of cycles that the CPU has spent unscheduled due to idling 1384system.cpu1.quiesceCycles 4812976632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1385system.cpu1.committedInsts 38877925 # Number of Instructions Simulated 1386system.cpu1.committedOps 49241908 # Number of Ops (including micro ops) Simulated 1387system.cpu1.committedInsts_total 38877925 # Number of Instructions Simulated 1388system.cpu1.cpi 10.813058 # CPI: Cycles Per Instruction 1389system.cpu1.cpi_total 10.813058 # CPI: Total CPI of All Threads 1390system.cpu1.ipc 0.092481 # IPC: Instructions Per Cycle 1391system.cpu1.ipc_total 0.092481 # IPC: Total IPC of All Threads 1392system.cpu1.int_regfile_reads 398800057 # number of integer regfile reads 1393system.cpu1.int_regfile_writes 58498146 # number of integer regfile writes 1394system.cpu1.fp_regfile_reads 4943 # number of floating regfile reads 1395system.cpu1.fp_regfile_writes 2344 # number of floating regfile writes 1396system.cpu1.misc_regfile_reads 91875872 # number of misc regfile reads 1397system.cpu1.misc_regfile_writes 429758 # number of misc regfile writes 1398system.cpu1.icache.replacements 623101 # number of replacements 1399system.cpu1.icache.tagsinuse 498.730815 # Cycle average of tags in use 1400system.cpu1.icache.total_refs 8556871 # Total number of references to valid blocks. 1401system.cpu1.icache.sampled_refs 623613 # Sample count of references to valid blocks. 1402system.cpu1.icache.avg_refs 13.721444 # Average number of references to valid blocks. 1403system.cpu1.icache.warmup_cycle 75785780000 # Cycle when the warmup percentage was hit. 1404system.cpu1.icache.occ_blocks::cpu1.inst 498.730815 # Average occupied blocks per requestor 1405system.cpu1.icache.occ_percent::cpu1.inst 0.974084 # Average percentage of cache occupancy 1406system.cpu1.icache.occ_percent::total 0.974084 # Average percentage of cache occupancy 1407system.cpu1.icache.ReadReq_hits::cpu1.inst 8556871 # number of ReadReq hits 1408system.cpu1.icache.ReadReq_hits::total 8556871 # number of ReadReq hits 1409system.cpu1.icache.demand_hits::cpu1.inst 8556871 # number of demand (read+write) hits 1410system.cpu1.icache.demand_hits::total 8556871 # number of demand (read+write) hits 1411system.cpu1.icache.overall_hits::cpu1.inst 8556871 # number of overall hits 1412system.cpu1.icache.overall_hits::total 8556871 # number of overall hits 1413system.cpu1.icache.ReadReq_misses::cpu1.inst 673686 # number of ReadReq misses 1414system.cpu1.icache.ReadReq_misses::total 673686 # number of ReadReq misses 1415system.cpu1.icache.demand_misses::cpu1.inst 673686 # number of demand (read+write) misses 1416system.cpu1.icache.demand_misses::total 673686 # number of demand (read+write) misses 1417system.cpu1.icache.overall_misses::cpu1.inst 673686 # number of overall misses 1418system.cpu1.icache.overall_misses::total 673686 # number of overall misses 1419system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10642693998 # number of ReadReq miss cycles 1420system.cpu1.icache.ReadReq_miss_latency::total 10642693998 # number of ReadReq miss cycles 1421system.cpu1.icache.demand_miss_latency::cpu1.inst 10642693998 # number of demand (read+write) miss cycles 1422system.cpu1.icache.demand_miss_latency::total 10642693998 # number of demand (read+write) miss cycles 1423system.cpu1.icache.overall_miss_latency::cpu1.inst 10642693998 # number of overall miss cycles 1424system.cpu1.icache.overall_miss_latency::total 10642693998 # number of overall miss cycles 1425system.cpu1.icache.ReadReq_accesses::cpu1.inst 9230557 # number of ReadReq accesses(hits+misses) 1426system.cpu1.icache.ReadReq_accesses::total 9230557 # number of ReadReq accesses(hits+misses) 1427system.cpu1.icache.demand_accesses::cpu1.inst 9230557 # number of demand (read+write) accesses 1428system.cpu1.icache.demand_accesses::total 9230557 # number of demand (read+write) accesses 1429system.cpu1.icache.overall_accesses::cpu1.inst 9230557 # number of overall (read+write) accesses 1430system.cpu1.icache.overall_accesses::total 9230557 # number of overall (read+write) accesses 1431system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.072984 # miss rate for ReadReq accesses 1432system.cpu1.icache.ReadReq_miss_rate::total 0.072984 # miss rate for ReadReq accesses 1433system.cpu1.icache.demand_miss_rate::cpu1.inst 0.072984 # miss rate for demand accesses 1434system.cpu1.icache.demand_miss_rate::total 0.072984 # miss rate for demand accesses 1435system.cpu1.icache.overall_miss_rate::cpu1.inst 0.072984 # miss rate for overall accesses 1436system.cpu1.icache.overall_miss_rate::total 0.072984 # miss rate for overall accesses 1437system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15797.706941 # average ReadReq miss latency 1438system.cpu1.icache.ReadReq_avg_miss_latency::total 15797.706941 # average ReadReq miss latency 1439system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15797.706941 # average overall miss latency 1440system.cpu1.icache.demand_avg_miss_latency::total 15797.706941 # average overall miss latency 1441system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15797.706941 # average overall miss latency 1442system.cpu1.icache.overall_avg_miss_latency::total 15797.706941 # average overall miss latency 1443system.cpu1.icache.blocked_cycles::no_mshrs 1133998 # number of cycles access was blocked 1444system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1445system.cpu1.icache.blocked::no_mshrs 174 # number of cycles access was blocked 1446system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1447system.cpu1.icache.avg_blocked_cycles::no_mshrs 6517.229885 # average number of cycles each access was blocked 1448system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1449system.cpu1.icache.fast_writes 0 # number of fast writes performed 1450system.cpu1.icache.cache_copies 0 # number of cache copies performed 1451system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50044 # number of ReadReq MSHR hits 1452system.cpu1.icache.ReadReq_mshr_hits::total 50044 # number of ReadReq MSHR hits 1453system.cpu1.icache.demand_mshr_hits::cpu1.inst 50044 # number of demand (read+write) MSHR hits 1454system.cpu1.icache.demand_mshr_hits::total 50044 # number of demand (read+write) MSHR hits 1455system.cpu1.icache.overall_mshr_hits::cpu1.inst 50044 # number of overall MSHR hits 1456system.cpu1.icache.overall_mshr_hits::total 50044 # number of overall MSHR hits 1457system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 623642 # number of ReadReq MSHR misses 1458system.cpu1.icache.ReadReq_mshr_misses::total 623642 # number of ReadReq MSHR misses 1459system.cpu1.icache.demand_mshr_misses::cpu1.inst 623642 # number of demand (read+write) MSHR misses 1460system.cpu1.icache.demand_mshr_misses::total 623642 # number of demand (read+write) MSHR misses 1461system.cpu1.icache.overall_mshr_misses::cpu1.inst 623642 # number of overall MSHR misses 1462system.cpu1.icache.overall_mshr_misses::total 623642 # number of overall MSHR misses 1463system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8149352498 # number of ReadReq MSHR miss cycles 1464system.cpu1.icache.ReadReq_mshr_miss_latency::total 8149352498 # number of ReadReq MSHR miss cycles 1465system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8149352498 # number of demand (read+write) MSHR miss cycles 1466system.cpu1.icache.demand_mshr_miss_latency::total 8149352498 # number of demand (read+write) MSHR miss cycles 1467system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8149352498 # number of overall MSHR miss cycles 1468system.cpu1.icache.overall_mshr_miss_latency::total 8149352498 # number of overall MSHR miss cycles 1469system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3211500 # number of ReadReq MSHR uncacheable cycles 1470system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3211500 # number of ReadReq MSHR uncacheable cycles 1471system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3211500 # number of overall MSHR uncacheable cycles 1472system.cpu1.icache.overall_mshr_uncacheable_latency::total 3211500 # number of overall MSHR uncacheable cycles 1473system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067563 # mshr miss rate for ReadReq accesses 1474system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067563 # mshr miss rate for ReadReq accesses 1475system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067563 # mshr miss rate for demand accesses 1476system.cpu1.icache.demand_mshr_miss_rate::total 0.067563 # mshr miss rate for demand accesses 1477system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067563 # mshr miss rate for overall accesses 1478system.cpu1.icache.overall_mshr_miss_rate::total 0.067563 # mshr miss rate for overall accesses 1479system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13067.356750 # average ReadReq mshr miss latency 1480system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13067.356750 # average ReadReq mshr miss latency 1481system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13067.356750 # average overall mshr miss latency 1482system.cpu1.icache.demand_avg_mshr_miss_latency::total 13067.356750 # average overall mshr miss latency 1483system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13067.356750 # average overall mshr miss latency 1484system.cpu1.icache.overall_avg_mshr_miss_latency::total 13067.356750 # average overall mshr miss latency 1485system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1486system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1487system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1488system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1489system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1490system.cpu1.dcache.replacements 363581 # number of replacements 1491system.cpu1.dcache.tagsinuse 487.223522 # Cycle average of tags in use 1492system.cpu1.dcache.total_refs 13117187 # Total number of references to valid blocks. 1493system.cpu1.dcache.sampled_refs 363929 # Sample count of references to valid blocks. 1494system.cpu1.dcache.avg_refs 36.043258 # Average number of references to valid blocks. 1495system.cpu1.dcache.warmup_cycle 71474573000 # Cycle when the warmup percentage was hit. 1496system.cpu1.dcache.occ_blocks::cpu1.data 487.223522 # Average occupied blocks per requestor 1497system.cpu1.dcache.occ_percent::cpu1.data 0.951608 # Average percentage of cache occupancy 1498system.cpu1.dcache.occ_percent::total 0.951608 # Average percentage of cache occupancy 1499system.cpu1.dcache.ReadReq_hits::cpu1.data 8616147 # number of ReadReq hits 1500system.cpu1.dcache.ReadReq_hits::total 8616147 # number of ReadReq hits 1501system.cpu1.dcache.WriteReq_hits::cpu1.data 4254446 # number of WriteReq hits 1502system.cpu1.dcache.WriteReq_hits::total 4254446 # number of WriteReq hits 1503system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105790 # number of LoadLockedReq hits 1504system.cpu1.dcache.LoadLockedReq_hits::total 105790 # number of LoadLockedReq hits 1505system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100736 # number of StoreCondReq hits 1506system.cpu1.dcache.StoreCondReq_hits::total 100736 # number of StoreCondReq hits 1507system.cpu1.dcache.demand_hits::cpu1.data 12870593 # number of demand (read+write) hits 1508system.cpu1.dcache.demand_hits::total 12870593 # number of demand (read+write) hits 1509system.cpu1.dcache.overall_hits::cpu1.data 12870593 # number of overall hits 1510system.cpu1.dcache.overall_hits::total 12870593 # number of overall hits 1511system.cpu1.dcache.ReadReq_misses::cpu1.data 410065 # number of ReadReq misses 1512system.cpu1.dcache.ReadReq_misses::total 410065 # number of ReadReq misses 1513system.cpu1.dcache.WriteReq_misses::cpu1.data 1595508 # number of WriteReq misses 1514system.cpu1.dcache.WriteReq_misses::total 1595508 # number of WriteReq misses 1515system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14278 # number of LoadLockedReq misses 1516system.cpu1.dcache.LoadLockedReq_misses::total 14278 # number of LoadLockedReq misses 1517system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10912 # number of StoreCondReq misses 1518system.cpu1.dcache.StoreCondReq_misses::total 10912 # number of StoreCondReq misses 1519system.cpu1.dcache.demand_misses::cpu1.data 2005573 # number of demand (read+write) misses 1520system.cpu1.dcache.demand_misses::total 2005573 # number of demand (read+write) misses 1521system.cpu1.dcache.overall_misses::cpu1.data 2005573 # number of overall misses 1522system.cpu1.dcache.overall_misses::total 2005573 # number of overall misses 1523system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8126055000 # number of ReadReq miss cycles 1524system.cpu1.dcache.ReadReq_miss_latency::total 8126055000 # number of ReadReq miss cycles 1525system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66044305227 # number of WriteReq miss cycles 1526system.cpu1.dcache.WriteReq_miss_latency::total 66044305227 # number of WriteReq miss cycles 1527system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 166791500 # number of LoadLockedReq miss cycles 1528system.cpu1.dcache.LoadLockedReq_miss_latency::total 166791500 # number of LoadLockedReq miss cycles 1529system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 95304000 # number of StoreCondReq miss cycles 1530system.cpu1.dcache.StoreCondReq_miss_latency::total 95304000 # number of StoreCondReq miss cycles 1531system.cpu1.dcache.demand_miss_latency::cpu1.data 74170360227 # number of demand (read+write) miss cycles 1532system.cpu1.dcache.demand_miss_latency::total 74170360227 # number of demand (read+write) miss cycles 1533system.cpu1.dcache.overall_miss_latency::cpu1.data 74170360227 # number of overall miss cycles 1534system.cpu1.dcache.overall_miss_latency::total 74170360227 # number of overall miss cycles 1535system.cpu1.dcache.ReadReq_accesses::cpu1.data 9026212 # number of ReadReq accesses(hits+misses) 1536system.cpu1.dcache.ReadReq_accesses::total 9026212 # number of ReadReq accesses(hits+misses) 1537system.cpu1.dcache.WriteReq_accesses::cpu1.data 5849954 # number of WriteReq accesses(hits+misses) 1538system.cpu1.dcache.WriteReq_accesses::total 5849954 # number of WriteReq accesses(hits+misses) 1539system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 120068 # number of LoadLockedReq accesses(hits+misses) 1540system.cpu1.dcache.LoadLockedReq_accesses::total 120068 # number of LoadLockedReq accesses(hits+misses) 1541system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111648 # number of StoreCondReq accesses(hits+misses) 1542system.cpu1.dcache.StoreCondReq_accesses::total 111648 # number of StoreCondReq accesses(hits+misses) 1543system.cpu1.dcache.demand_accesses::cpu1.data 14876166 # number of demand (read+write) accesses 1544system.cpu1.dcache.demand_accesses::total 14876166 # number of demand (read+write) accesses 1545system.cpu1.dcache.overall_accesses::cpu1.data 14876166 # number of overall (read+write) accesses 1546system.cpu1.dcache.overall_accesses::total 14876166 # number of overall (read+write) accesses 1547system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045430 # miss rate for ReadReq accesses 1548system.cpu1.dcache.ReadReq_miss_rate::total 0.045430 # miss rate for ReadReq accesses 1549system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.272739 # miss rate for WriteReq accesses 1550system.cpu1.dcache.WriteReq_miss_rate::total 0.272739 # miss rate for WriteReq accesses 1551system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118916 # miss rate for LoadLockedReq accesses 1552system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118916 # miss rate for LoadLockedReq accesses 1553system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097736 # miss rate for StoreCondReq accesses 1554system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097736 # miss rate for StoreCondReq accesses 1555system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134818 # miss rate for demand accesses 1556system.cpu1.dcache.demand_miss_rate::total 0.134818 # miss rate for demand accesses 1557system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134818 # miss rate for overall accesses 1558system.cpu1.dcache.overall_miss_rate::total 0.134818 # miss rate for overall accesses 1559system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19816.504700 # average ReadReq miss latency 1560system.cpu1.dcache.ReadReq_avg_miss_latency::total 19816.504700 # average ReadReq miss latency 1561system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41393.904153 # average WriteReq miss latency 1562system.cpu1.dcache.WriteReq_avg_miss_latency::total 41393.904153 # average WriteReq miss latency 1563system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11681.713125 # average LoadLockedReq miss latency 1564system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11681.713125 # average LoadLockedReq miss latency 1565system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8733.870968 # average StoreCondReq miss latency 1566system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8733.870968 # average StoreCondReq miss latency 1567system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 36982.129410 # average overall miss latency 1568system.cpu1.dcache.demand_avg_miss_latency::total 36982.129410 # average overall miss latency 1569system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 36982.129410 # average overall miss latency 1570system.cpu1.dcache.overall_avg_miss_latency::total 36982.129410 # average overall miss latency 1571system.cpu1.dcache.blocked_cycles::no_mshrs 29670016 # number of cycles access was blocked 1572system.cpu1.dcache.blocked_cycles::no_targets 5568500 # number of cycles access was blocked 1573system.cpu1.dcache.blocked::no_mshrs 6658 # number of cycles access was blocked 1574system.cpu1.dcache.blocked::no_targets 173 # number of cycles access was blocked 1575system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4456.295584 # average number of cycles each access was blocked 1576system.cpu1.dcache.avg_blocked_cycles::no_targets 32187.861272 # average number of cycles each access was blocked 1577system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1578system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1579system.cpu1.dcache.writebacks::writebacks 328251 # number of writebacks 1580system.cpu1.dcache.writebacks::total 328251 # number of writebacks 1581system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 178277 # number of ReadReq MSHR hits 1582system.cpu1.dcache.ReadReq_mshr_hits::total 178277 # number of ReadReq MSHR hits 1583system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1432587 # number of WriteReq MSHR hits 1584system.cpu1.dcache.WriteReq_mshr_hits::total 1432587 # number of WriteReq MSHR hits 1585system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1464 # number of LoadLockedReq MSHR hits 1586system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1464 # number of LoadLockedReq MSHR hits 1587system.cpu1.dcache.demand_mshr_hits::cpu1.data 1610864 # number of demand (read+write) MSHR hits 1588system.cpu1.dcache.demand_mshr_hits::total 1610864 # number of demand (read+write) MSHR hits 1589system.cpu1.dcache.overall_mshr_hits::cpu1.data 1610864 # number of overall MSHR hits 1590system.cpu1.dcache.overall_mshr_hits::total 1610864 # number of overall MSHR hits 1591system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231788 # number of ReadReq MSHR misses 1592system.cpu1.dcache.ReadReq_mshr_misses::total 231788 # number of ReadReq MSHR misses 1593system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162921 # number of WriteReq MSHR misses 1594system.cpu1.dcache.WriteReq_mshr_misses::total 162921 # number of WriteReq MSHR misses 1595system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12814 # number of LoadLockedReq MSHR misses 1596system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12814 # number of LoadLockedReq MSHR misses 1597system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10909 # number of StoreCondReq MSHR misses 1598system.cpu1.dcache.StoreCondReq_mshr_misses::total 10909 # number of StoreCondReq MSHR misses 1599system.cpu1.dcache.demand_mshr_misses::cpu1.data 394709 # number of demand (read+write) MSHR misses 1600system.cpu1.dcache.demand_mshr_misses::total 394709 # number of demand (read+write) MSHR misses 1601system.cpu1.dcache.overall_mshr_misses::cpu1.data 394709 # number of overall MSHR misses 1602system.cpu1.dcache.overall_mshr_misses::total 394709 # number of overall MSHR misses 1603system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3566201462 # number of ReadReq MSHR miss cycles 1604system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3566201462 # number of ReadReq MSHR miss cycles 1605system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5537603585 # number of WriteReq MSHR miss cycles 1606system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5537603585 # number of WriteReq MSHR miss cycles 1607system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 104573506 # number of LoadLockedReq MSHR miss cycles 1608system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 104573506 # number of LoadLockedReq MSHR miss cycles 1609system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 61265506 # number of StoreCondReq MSHR miss cycles 1610system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 61265506 # number of StoreCondReq MSHR miss cycles 1611system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles 1612system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles 1613system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9103805047 # number of demand (read+write) MSHR miss cycles 1614system.cpu1.dcache.demand_mshr_miss_latency::total 9103805047 # number of demand (read+write) MSHR miss cycles 1615system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9103805047 # number of overall MSHR miss cycles 1616system.cpu1.dcache.overall_mshr_miss_latency::total 9103805047 # number of overall MSHR miss cycles 1617system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169309741500 # number of ReadReq MSHR uncacheable cycles 1618system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169309741500 # number of ReadReq MSHR uncacheable cycles 1619system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40933880282 # number of WriteReq MSHR uncacheable cycles 1620system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40933880282 # number of WriteReq MSHR uncacheable cycles 1621system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210243621782 # number of overall MSHR uncacheable cycles 1622system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210243621782 # number of overall MSHR uncacheable cycles 1623system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025679 # mshr miss rate for ReadReq accesses 1624system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025679 # mshr miss rate for ReadReq accesses 1625system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027850 # mshr miss rate for WriteReq accesses 1626system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027850 # mshr miss rate for WriteReq accesses 1627system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106723 # mshr miss rate for LoadLockedReq accesses 1628system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106723 # mshr miss rate for LoadLockedReq accesses 1629system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097709 # mshr miss rate for StoreCondReq accesses 1630system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097709 # mshr miss rate for StoreCondReq accesses 1631system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026533 # mshr miss rate for demand accesses 1632system.cpu1.dcache.demand_mshr_miss_rate::total 0.026533 # mshr miss rate for demand accesses 1633system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026533 # mshr miss rate for overall accesses 1634system.cpu1.dcache.overall_mshr_miss_rate::total 0.026533 # mshr miss rate for overall accesses 1635system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15385.617297 # average ReadReq mshr miss latency 1636system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15385.617297 # average ReadReq mshr miss latency 1637system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33989.501568 # average WriteReq mshr miss latency 1638system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33989.501568 # average WriteReq mshr miss latency 1639system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8160.879195 # average LoadLockedReq mshr miss latency 1640system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8160.879195 # average LoadLockedReq mshr miss latency 1641system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5616.051517 # average StoreCondReq mshr miss latency 1642system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5616.051517 # average StoreCondReq mshr miss latency 1643system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1644system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1645system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23064.599609 # average overall mshr miss latency 1646system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23064.599609 # average overall mshr miss latency 1647system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23064.599609 # average overall mshr miss latency 1648system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23064.599609 # average overall mshr miss latency 1649system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1650system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1651system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1652system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1653system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1654system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1655system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1656system.iocache.replacements 0 # number of replacements 1657system.iocache.tagsinuse 0 # Cycle average of tags in use 1658system.iocache.total_refs 0 # Total number of references to valid blocks. 1659system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1660system.iocache.avg_refs nan # Average number of references to valid blocks. 1661system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1662system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1663system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1664system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1665system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1666system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1667system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1668system.iocache.fast_writes 0 # number of fast writes performed 1669system.iocache.cache_copies 0 # number of cache copies performed 1670system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323189312111 # number of ReadReq MSHR uncacheable cycles 1671system.iocache.ReadReq_mshr_uncacheable_latency::total 1323189312111 # number of ReadReq MSHR uncacheable cycles 1672system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323189312111 # number of overall MSHR uncacheable cycles 1673system.iocache.overall_mshr_uncacheable_latency::total 1323189312111 # number of overall MSHR uncacheable cycles 1674system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1675system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1676system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1677system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1678system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1679system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1680system.cpu0.kern.inst.quiesce 43824 # number of quiesce instructions executed 1681system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1682system.cpu1.kern.inst.quiesce 53932 # number of quiesce instructions executed 1683 1684---------- End Simulation Statistics ----------