Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.570828 # Number of seconds simulated
4sim_ticks 2570828403500 # Number of ticks simulated
5final_tick 2570828403500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 96885 # Simulator instruction rate (inst/s)
8host_op_rate 125154 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 4026902595 # Simulator tick rate (ticks/s)
10host_mem_usage 385208 # Number of bytes of host memory used
11host_seconds 638.41 # Real time elapsed on the host

7host_inst_rate 36466 # Simulator instruction rate (inst/s)
8host_op_rate 47106 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1515652841 # Simulator tick rate (ticks/s)
10host_mem_usage 392156 # Number of bytes of host memory used
11host_seconds 1696.19 # Real time elapsed on the host

12sim_insts 61852501 # Number of instructions simulated
13sim_ops 79899751 # Number of ops (including micro ops) simulated

14system.realview.nvmem.bytes_read 384 # Number of bytes read from this memory
15system.realview.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory
16system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
17system.realview.nvmem.num_reads 6 # Number of read requests responded to by this memory
18system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
19system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
20system.realview.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s)
21system.realview.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s)
22system.realview.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s)

23system.physmem.bytes_read 131418468 # Number of bytes read from this memory
24system.physmem.bytes_inst_read 1192320 # Number of instructions bytes read from this memory
25system.physmem.bytes_written 10172560 # Number of bytes written to this memory
26system.physmem.num_reads 15127944 # Number of read requests responded to by this memory
27system.physmem.num_writes 868900 # Number of write requests responded to by this memory
28system.physmem.num_other 0 # Number of other requests responded to by this memory
29system.physmem.bw_read 51119113 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read 463788 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write 3956919 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_total 55076032 # Total bandwidth to/from this memory (bytes/s)

14system.physmem.bytes_read 131418468 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 1192320 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 10172560 # Number of bytes written to this memory
17system.physmem.num_reads 15127944 # Number of read requests responded to by this memory
18system.physmem.num_writes 868900 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 51119113 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 463788 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 3956919 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 55076032 # Total bandwidth to/from this memory (bytes/s)

24system.realview.nvmem.bytes_read 384 # Number of bytes read from this memory
25system.realview.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory
26system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
27system.realview.nvmem.num_reads 6 # Number of read requests responded to by this memory
28system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
29system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
30system.realview.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s)
31system.realview.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s)
32system.realview.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s)

33system.l2c.replacements 130877 # number of replacements
34system.l2c.tagsinuse 27573.095607 # Cycle average of tags in use
35system.l2c.total_refs 1846037 # Total number of references to valid blocks.
36system.l2c.sampled_refs 160860 # Sample count of references to valid blocks.
37system.l2c.avg_refs 11.476047 # Average number of references to valid blocks.
38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
39system.l2c.occ_blocks::writebacks 15182.704930 # Average occupied blocks per requestor
40system.l2c.occ_blocks::cpu0.dtb.walker 18.055930 # Average occupied blocks per requestor
41system.l2c.occ_blocks::cpu0.itb.walker 0.023183 # Average occupied blocks per requestor
42system.l2c.occ_blocks::cpu0.inst 2139.633455 # Average occupied blocks per requestor
43system.l2c.occ_blocks::cpu0.data 1078.266225 # Average occupied blocks per requestor
44system.l2c.occ_blocks::cpu1.dtb.walker 23.228189 # Average occupied blocks per requestor
45system.l2c.occ_blocks::cpu1.itb.walker 0.012320 # Average occupied blocks per requestor
46system.l2c.occ_blocks::cpu1.inst 4084.926228 # Average occupied blocks per requestor
47system.l2c.occ_blocks::cpu1.data 5046.245146 # Average occupied blocks per requestor
48system.l2c.occ_percent::writebacks 0.231670 # Average percentage of cache occupancy
49system.l2c.occ_percent::cpu0.dtb.walker 0.000276 # Average percentage of cache occupancy
50system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
51system.l2c.occ_percent::cpu0.inst 0.032648 # Average percentage of cache occupancy
52system.l2c.occ_percent::cpu0.data 0.016453 # Average percentage of cache occupancy
53system.l2c.occ_percent::cpu1.dtb.walker 0.000354 # Average percentage of cache occupancy
54system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
55system.l2c.occ_percent::cpu1.inst 0.062331 # Average percentage of cache occupancy
56system.l2c.occ_percent::cpu1.data 0.077000 # Average percentage of cache occupancy
57system.l2c.occ_percent::total 0.420732 # Average percentage of cache occupancy
58system.l2c.ReadReq_hits::cpu0.dtb.walker 49525 # number of ReadReq hits
59system.l2c.ReadReq_hits::cpu0.itb.walker 7421 # number of ReadReq hits
60system.l2c.ReadReq_hits::cpu0.inst 332040 # number of ReadReq hits
61system.l2c.ReadReq_hits::cpu0.data 132891 # number of ReadReq hits
62system.l2c.ReadReq_hits::cpu1.dtb.walker 112998 # number of ReadReq hits
63system.l2c.ReadReq_hits::cpu1.itb.walker 7553 # number of ReadReq hits
64system.l2c.ReadReq_hits::cpu1.inst 699861 # number of ReadReq hits
65system.l2c.ReadReq_hits::cpu1.data 231630 # number of ReadReq hits
66system.l2c.ReadReq_hits::total 1573919 # number of ReadReq hits
67system.l2c.Writeback_hits::writebacks 605876 # number of Writeback hits
68system.l2c.Writeback_hits::total 605876 # number of Writeback hits
69system.l2c.UpgradeReq_hits::cpu0.data 897 # number of UpgradeReq hits
70system.l2c.UpgradeReq_hits::cpu1.data 1121 # number of UpgradeReq hits
71system.l2c.UpgradeReq_hits::total 2018 # number of UpgradeReq hits
72system.l2c.SCUpgradeReq_hits::cpu0.data 196 # number of SCUpgradeReq hits
73system.l2c.SCUpgradeReq_hits::cpu1.data 382 # number of SCUpgradeReq hits
74system.l2c.SCUpgradeReq_hits::total 578 # number of SCUpgradeReq hits
75system.l2c.ReadExReq_hits::cpu0.data 35379 # number of ReadExReq hits
76system.l2c.ReadExReq_hits::cpu1.data 65973 # number of ReadExReq hits
77system.l2c.ReadExReq_hits::total 101352 # number of ReadExReq hits
78system.l2c.demand_hits::cpu0.dtb.walker 49525 # number of demand (read+write) hits
79system.l2c.demand_hits::cpu0.itb.walker 7421 # number of demand (read+write) hits
80system.l2c.demand_hits::cpu0.inst 332040 # number of demand (read+write) hits
81system.l2c.demand_hits::cpu0.data 168270 # number of demand (read+write) hits
82system.l2c.demand_hits::cpu1.dtb.walker 112998 # number of demand (read+write) hits
83system.l2c.demand_hits::cpu1.itb.walker 7553 # number of demand (read+write) hits
84system.l2c.demand_hits::cpu1.inst 699861 # number of demand (read+write) hits
85system.l2c.demand_hits::cpu1.data 297603 # number of demand (read+write) hits
86system.l2c.demand_hits::total 1675271 # number of demand (read+write) hits
87system.l2c.overall_hits::cpu0.dtb.walker 49525 # number of overall hits
88system.l2c.overall_hits::cpu0.itb.walker 7421 # number of overall hits
89system.l2c.overall_hits::cpu0.inst 332040 # number of overall hits
90system.l2c.overall_hits::cpu0.data 168270 # number of overall hits
91system.l2c.overall_hits::cpu1.dtb.walker 112998 # number of overall hits
92system.l2c.overall_hits::cpu1.itb.walker 7553 # number of overall hits
93system.l2c.overall_hits::cpu1.inst 699861 # number of overall hits
94system.l2c.overall_hits::cpu1.data 297603 # number of overall hits
95system.l2c.overall_hits::total 1675271 # number of overall hits
96system.l2c.ReadReq_misses::cpu0.dtb.walker 81 # number of ReadReq misses
97system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses
98system.l2c.ReadReq_misses::cpu0.inst 8347 # number of ReadReq misses
99system.l2c.ReadReq_misses::cpu0.data 8839 # number of ReadReq misses
100system.l2c.ReadReq_misses::cpu1.dtb.walker 55 # number of ReadReq misses
101system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
102system.l2c.ReadReq_misses::cpu1.inst 10114 # number of ReadReq misses
103system.l2c.ReadReq_misses::cpu1.data 12836 # number of ReadReq misses
104system.l2c.ReadReq_misses::total 40278 # number of ReadReq misses
105system.l2c.UpgradeReq_misses::cpu0.data 5127 # number of UpgradeReq misses
106system.l2c.UpgradeReq_misses::cpu1.data 5687 # number of UpgradeReq misses
107system.l2c.UpgradeReq_misses::total 10814 # number of UpgradeReq misses
108system.l2c.SCUpgradeReq_misses::cpu0.data 762 # number of SCUpgradeReq misses
109system.l2c.SCUpgradeReq_misses::cpu1.data 599 # number of SCUpgradeReq misses
110system.l2c.SCUpgradeReq_misses::total 1361 # number of SCUpgradeReq misses
111system.l2c.ReadExReq_misses::cpu0.data 65841 # number of ReadExReq misses
112system.l2c.ReadExReq_misses::cpu1.data 81581 # number of ReadExReq misses
113system.l2c.ReadExReq_misses::total 147422 # number of ReadExReq misses
114system.l2c.demand_misses::cpu0.dtb.walker 81 # number of demand (read+write) misses
115system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses
116system.l2c.demand_misses::cpu0.inst 8347 # number of demand (read+write) misses
117system.l2c.demand_misses::cpu0.data 74680 # number of demand (read+write) misses
118system.l2c.demand_misses::cpu1.dtb.walker 55 # number of demand (read+write) misses
119system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
120system.l2c.demand_misses::cpu1.inst 10114 # number of demand (read+write) misses
121system.l2c.demand_misses::cpu1.data 94417 # number of demand (read+write) misses
122system.l2c.demand_misses::total 187700 # number of demand (read+write) misses
123system.l2c.overall_misses::cpu0.dtb.walker 81 # number of overall misses
124system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses
125system.l2c.overall_misses::cpu0.inst 8347 # number of overall misses
126system.l2c.overall_misses::cpu0.data 74680 # number of overall misses
127system.l2c.overall_misses::cpu1.dtb.walker 55 # number of overall misses
128system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
129system.l2c.overall_misses::cpu1.inst 10114 # number of overall misses
130system.l2c.overall_misses::cpu1.data 94417 # number of overall misses
131system.l2c.overall_misses::total 187700 # number of overall misses
132system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 4226000 # number of ReadReq miss cycles
133system.l2c.ReadReq_miss_latency::cpu0.itb.walker 261000 # number of ReadReq miss cycles
134system.l2c.ReadReq_miss_latency::cpu0.inst 436472500 # number of ReadReq miss cycles
135system.l2c.ReadReq_miss_latency::cpu0.data 461376000 # number of ReadReq miss cycles
136system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 2870500 # number of ReadReq miss cycles
137system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52000 # number of ReadReq miss cycles
138system.l2c.ReadReq_miss_latency::cpu1.inst 529146500 # number of ReadReq miss cycles
139system.l2c.ReadReq_miss_latency::cpu1.data 670533000 # number of ReadReq miss cycles
140system.l2c.ReadReq_miss_latency::total 2104937500 # number of ReadReq miss cycles
141system.l2c.UpgradeReq_miss_latency::cpu0.data 17145500 # number of UpgradeReq miss cycles
142system.l2c.UpgradeReq_miss_latency::cpu1.data 38360500 # number of UpgradeReq miss cycles
143system.l2c.UpgradeReq_miss_latency::total 55506000 # number of UpgradeReq miss cycles
144system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1985000 # number of SCUpgradeReq miss cycles
145system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5435500 # number of SCUpgradeReq miss cycles
146system.l2c.SCUpgradeReq_miss_latency::total 7420500 # number of SCUpgradeReq miss cycles
147system.l2c.ReadExReq_miss_latency::cpu0.data 3452457999 # number of ReadExReq miss cycles
148system.l2c.ReadExReq_miss_latency::cpu1.data 4285420500 # number of ReadExReq miss cycles
149system.l2c.ReadExReq_miss_latency::total 7737878499 # number of ReadExReq miss cycles
150system.l2c.demand_miss_latency::cpu0.dtb.walker 4226000 # number of demand (read+write) miss cycles
151system.l2c.demand_miss_latency::cpu0.itb.walker 261000 # number of demand (read+write) miss cycles
152system.l2c.demand_miss_latency::cpu0.inst 436472500 # number of demand (read+write) miss cycles
153system.l2c.demand_miss_latency::cpu0.data 3913833999 # number of demand (read+write) miss cycles
154system.l2c.demand_miss_latency::cpu1.dtb.walker 2870500 # number of demand (read+write) miss cycles
155system.l2c.demand_miss_latency::cpu1.itb.walker 52000 # number of demand (read+write) miss cycles
156system.l2c.demand_miss_latency::cpu1.inst 529146500 # number of demand (read+write) miss cycles
157system.l2c.demand_miss_latency::cpu1.data 4955953500 # number of demand (read+write) miss cycles
158system.l2c.demand_miss_latency::total 9842815999 # number of demand (read+write) miss cycles
159system.l2c.overall_miss_latency::cpu0.dtb.walker 4226000 # number of overall miss cycles
160system.l2c.overall_miss_latency::cpu0.itb.walker 261000 # number of overall miss cycles
161system.l2c.overall_miss_latency::cpu0.inst 436472500 # number of overall miss cycles
162system.l2c.overall_miss_latency::cpu0.data 3913833999 # number of overall miss cycles
163system.l2c.overall_miss_latency::cpu1.dtb.walker 2870500 # number of overall miss cycles
164system.l2c.overall_miss_latency::cpu1.itb.walker 52000 # number of overall miss cycles
165system.l2c.overall_miss_latency::cpu1.inst 529146500 # number of overall miss cycles
166system.l2c.overall_miss_latency::cpu1.data 4955953500 # number of overall miss cycles
167system.l2c.overall_miss_latency::total 9842815999 # number of overall miss cycles
168system.l2c.ReadReq_accesses::cpu0.dtb.walker 49606 # number of ReadReq accesses(hits+misses)
169system.l2c.ReadReq_accesses::cpu0.itb.walker 7426 # number of ReadReq accesses(hits+misses)
170system.l2c.ReadReq_accesses::cpu0.inst 340387 # number of ReadReq accesses(hits+misses)
171system.l2c.ReadReq_accesses::cpu0.data 141730 # number of ReadReq accesses(hits+misses)
172system.l2c.ReadReq_accesses::cpu1.dtb.walker 113053 # number of ReadReq accesses(hits+misses)
173system.l2c.ReadReq_accesses::cpu1.itb.walker 7554 # number of ReadReq accesses(hits+misses)
174system.l2c.ReadReq_accesses::cpu1.inst 709975 # number of ReadReq accesses(hits+misses)
175system.l2c.ReadReq_accesses::cpu1.data 244466 # number of ReadReq accesses(hits+misses)
176system.l2c.ReadReq_accesses::total 1614197 # number of ReadReq accesses(hits+misses)
177system.l2c.Writeback_accesses::writebacks 605876 # number of Writeback accesses(hits+misses)
178system.l2c.Writeback_accesses::total 605876 # number of Writeback accesses(hits+misses)
179system.l2c.UpgradeReq_accesses::cpu0.data 6024 # number of UpgradeReq accesses(hits+misses)
180system.l2c.UpgradeReq_accesses::cpu1.data 6808 # number of UpgradeReq accesses(hits+misses)
181system.l2c.UpgradeReq_accesses::total 12832 # number of UpgradeReq accesses(hits+misses)
182system.l2c.SCUpgradeReq_accesses::cpu0.data 958 # number of SCUpgradeReq accesses(hits+misses)
183system.l2c.SCUpgradeReq_accesses::cpu1.data 981 # number of SCUpgradeReq accesses(hits+misses)
184system.l2c.SCUpgradeReq_accesses::total 1939 # number of SCUpgradeReq accesses(hits+misses)
185system.l2c.ReadExReq_accesses::cpu0.data 101220 # number of ReadExReq accesses(hits+misses)
186system.l2c.ReadExReq_accesses::cpu1.data 147554 # number of ReadExReq accesses(hits+misses)
187system.l2c.ReadExReq_accesses::total 248774 # number of ReadExReq accesses(hits+misses)
188system.l2c.demand_accesses::cpu0.dtb.walker 49606 # number of demand (read+write) accesses
189system.l2c.demand_accesses::cpu0.itb.walker 7426 # number of demand (read+write) accesses
190system.l2c.demand_accesses::cpu0.inst 340387 # number of demand (read+write) accesses
191system.l2c.demand_accesses::cpu0.data 242950 # number of demand (read+write) accesses
192system.l2c.demand_accesses::cpu1.dtb.walker 113053 # number of demand (read+write) accesses
193system.l2c.demand_accesses::cpu1.itb.walker 7554 # number of demand (read+write) accesses
194system.l2c.demand_accesses::cpu1.inst 709975 # number of demand (read+write) accesses
195system.l2c.demand_accesses::cpu1.data 392020 # number of demand (read+write) accesses
196system.l2c.demand_accesses::total 1862971 # number of demand (read+write) accesses
197system.l2c.overall_accesses::cpu0.dtb.walker 49606 # number of overall (read+write) accesses
198system.l2c.overall_accesses::cpu0.itb.walker 7426 # number of overall (read+write) accesses
199system.l2c.overall_accesses::cpu0.inst 340387 # number of overall (read+write) accesses
200system.l2c.overall_accesses::cpu0.data 242950 # number of overall (read+write) accesses
201system.l2c.overall_accesses::cpu1.dtb.walker 113053 # number of overall (read+write) accesses
202system.l2c.overall_accesses::cpu1.itb.walker 7554 # number of overall (read+write) accesses
203system.l2c.overall_accesses::cpu1.inst 709975 # number of overall (read+write) accesses
204system.l2c.overall_accesses::cpu1.data 392020 # number of overall (read+write) accesses
205system.l2c.overall_accesses::total 1862971 # number of overall (read+write) accesses
206system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001633 # miss rate for ReadReq accesses
207system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000673 # miss rate for ReadReq accesses
208system.l2c.ReadReq_miss_rate::cpu0.inst 0.024522 # miss rate for ReadReq accesses
209system.l2c.ReadReq_miss_rate::cpu0.data 0.062365 # miss rate for ReadReq accesses
210system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000486 # miss rate for ReadReq accesses
211system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000132 # miss rate for ReadReq accesses
212system.l2c.ReadReq_miss_rate::cpu1.inst 0.014246 # miss rate for ReadReq accesses
213system.l2c.ReadReq_miss_rate::cpu1.data 0.052506 # miss rate for ReadReq accesses
214system.l2c.UpgradeReq_miss_rate::cpu0.data 0.851096 # miss rate for UpgradeReq accesses
215system.l2c.UpgradeReq_miss_rate::cpu1.data 0.835341 # miss rate for UpgradeReq accesses
216system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.795407 # miss rate for SCUpgradeReq accesses
217system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.610601 # miss rate for SCUpgradeReq accesses
218system.l2c.ReadExReq_miss_rate::cpu0.data 0.650474 # miss rate for ReadExReq accesses
219system.l2c.ReadExReq_miss_rate::cpu1.data 0.552889 # miss rate for ReadExReq accesses
220system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001633 # miss rate for demand accesses
221system.l2c.demand_miss_rate::cpu0.itb.walker 0.000673 # miss rate for demand accesses
222system.l2c.demand_miss_rate::cpu0.inst 0.024522 # miss rate for demand accesses
223system.l2c.demand_miss_rate::cpu0.data 0.307388 # miss rate for demand accesses
224system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000486 # miss rate for demand accesses
225system.l2c.demand_miss_rate::cpu1.itb.walker 0.000132 # miss rate for demand accesses
226system.l2c.demand_miss_rate::cpu1.inst 0.014246 # miss rate for demand accesses
227system.l2c.demand_miss_rate::cpu1.data 0.240847 # miss rate for demand accesses
228system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001633 # miss rate for overall accesses
229system.l2c.overall_miss_rate::cpu0.itb.walker 0.000673 # miss rate for overall accesses
230system.l2c.overall_miss_rate::cpu0.inst 0.024522 # miss rate for overall accesses
231system.l2c.overall_miss_rate::cpu0.data 0.307388 # miss rate for overall accesses
232system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000486 # miss rate for overall accesses
233system.l2c.overall_miss_rate::cpu1.itb.walker 0.000132 # miss rate for overall accesses
234system.l2c.overall_miss_rate::cpu1.inst 0.014246 # miss rate for overall accesses
235system.l2c.overall_miss_rate::cpu1.data 0.240847 # miss rate for overall accesses
236system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52172.839506 # average ReadReq miss latency
237system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52200 # average ReadReq miss latency
238system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52290.942854 # average ReadReq miss latency
239system.l2c.ReadReq_avg_miss_latency::cpu0.data 52197.759928 # average ReadReq miss latency
240system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52190.909091 # average ReadReq miss latency
241system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency
242system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52318.222266 # average ReadReq miss latency
243system.l2c.ReadReq_avg_miss_latency::cpu1.data 52238.469928 # average ReadReq miss latency
244system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3344.158377 # average UpgradeReq miss latency
245system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6745.296290 # average UpgradeReq miss latency
246system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2604.986877 # average SCUpgradeReq miss latency
247system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9074.290484 # average SCUpgradeReq miss latency
248system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52436.293480 # average ReadExReq miss latency
249system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52529.639254 # average ReadExReq miss latency
250system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52172.839506 # average overall miss latency
251system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency
252system.l2c.demand_avg_miss_latency::cpu0.inst 52290.942854 # average overall miss latency
253system.l2c.demand_avg_miss_latency::cpu0.data 52408.061047 # average overall miss latency
254system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52190.909091 # average overall miss latency
255system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency
256system.l2c.demand_avg_miss_latency::cpu1.inst 52318.222266 # average overall miss latency
257system.l2c.demand_avg_miss_latency::cpu1.data 52490.054757 # average overall miss latency
258system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52172.839506 # average overall miss latency
259system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency
260system.l2c.overall_avg_miss_latency::cpu0.inst 52290.942854 # average overall miss latency
261system.l2c.overall_avg_miss_latency::cpu0.data 52408.061047 # average overall miss latency
262system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52190.909091 # average overall miss latency
263system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency
264system.l2c.overall_avg_miss_latency::cpu1.inst 52318.222266 # average overall miss latency
265system.l2c.overall_avg_miss_latency::cpu1.data 52490.054757 # average overall miss latency
266system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
267system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
268system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
269system.l2c.blocked::no_targets 0 # number of cycles access was blocked

270system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
271system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked

270system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
271system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

272system.l2c.fast_writes 0 # number of fast writes performed
273system.l2c.cache_copies 0 # number of cache copies performed
274system.l2c.writebacks::writebacks 111616 # number of writebacks
275system.l2c.writebacks::total 111616 # number of writebacks
276system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits
277system.l2c.ReadReq_mshr_hits::cpu0.data 42 # number of ReadReq MSHR hits
278system.l2c.ReadReq_mshr_hits::cpu1.inst 10 # number of ReadReq MSHR hits
279system.l2c.ReadReq_mshr_hits::cpu1.data 35 # number of ReadReq MSHR hits
280system.l2c.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits
281system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits
282system.l2c.demand_mshr_hits::cpu0.data 42 # number of demand (read+write) MSHR hits
283system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits
284system.l2c.demand_mshr_hits::cpu1.data 35 # number of demand (read+write) MSHR hits
285system.l2c.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits
286system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits
287system.l2c.overall_mshr_hits::cpu0.data 42 # number of overall MSHR hits
288system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits
289system.l2c.overall_mshr_hits::cpu1.data 35 # number of overall MSHR hits
290system.l2c.overall_mshr_hits::total 91 # number of overall MSHR hits
291system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 81 # number of ReadReq MSHR misses
292system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 5 # number of ReadReq MSHR misses
293system.l2c.ReadReq_mshr_misses::cpu0.inst 8343 # number of ReadReq MSHR misses
294system.l2c.ReadReq_mshr_misses::cpu0.data 8797 # number of ReadReq MSHR misses
295system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 55 # number of ReadReq MSHR misses
296system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses
297system.l2c.ReadReq_mshr_misses::cpu1.inst 10104 # number of ReadReq MSHR misses
298system.l2c.ReadReq_mshr_misses::cpu1.data 12801 # number of ReadReq MSHR misses
299system.l2c.ReadReq_mshr_misses::total 40187 # number of ReadReq MSHR misses
300system.l2c.UpgradeReq_mshr_misses::cpu0.data 5127 # number of UpgradeReq MSHR misses
301system.l2c.UpgradeReq_mshr_misses::cpu1.data 5687 # number of UpgradeReq MSHR misses
302system.l2c.UpgradeReq_mshr_misses::total 10814 # number of UpgradeReq MSHR misses
303system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 762 # number of SCUpgradeReq MSHR misses
304system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 599 # number of SCUpgradeReq MSHR misses
305system.l2c.SCUpgradeReq_mshr_misses::total 1361 # number of SCUpgradeReq MSHR misses
306system.l2c.ReadExReq_mshr_misses::cpu0.data 65841 # number of ReadExReq MSHR misses
307system.l2c.ReadExReq_mshr_misses::cpu1.data 81581 # number of ReadExReq MSHR misses
308system.l2c.ReadExReq_mshr_misses::total 147422 # number of ReadExReq MSHR misses
309system.l2c.demand_mshr_misses::cpu0.dtb.walker 81 # number of demand (read+write) MSHR misses
310system.l2c.demand_mshr_misses::cpu0.itb.walker 5 # number of demand (read+write) MSHR misses
311system.l2c.demand_mshr_misses::cpu0.inst 8343 # number of demand (read+write) MSHR misses
312system.l2c.demand_mshr_misses::cpu0.data 74638 # number of demand (read+write) MSHR misses
313system.l2c.demand_mshr_misses::cpu1.dtb.walker 55 # number of demand (read+write) MSHR misses
314system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
315system.l2c.demand_mshr_misses::cpu1.inst 10104 # number of demand (read+write) MSHR misses
316system.l2c.demand_mshr_misses::cpu1.data 94382 # number of demand (read+write) MSHR misses
317system.l2c.demand_mshr_misses::total 187609 # number of demand (read+write) MSHR misses
318system.l2c.overall_mshr_misses::cpu0.dtb.walker 81 # number of overall MSHR misses
319system.l2c.overall_mshr_misses::cpu0.itb.walker 5 # number of overall MSHR misses
320system.l2c.overall_mshr_misses::cpu0.inst 8343 # number of overall MSHR misses
321system.l2c.overall_mshr_misses::cpu0.data 74638 # number of overall MSHR misses
322system.l2c.overall_mshr_misses::cpu1.dtb.walker 55 # number of overall MSHR misses
323system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
324system.l2c.overall_mshr_misses::cpu1.inst 10104 # number of overall MSHR misses
325system.l2c.overall_mshr_misses::cpu1.data 94382 # number of overall MSHR misses
326system.l2c.overall_mshr_misses::total 187609 # number of overall MSHR misses
327system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3244000 # number of ReadReq MSHR miss cycles
328system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 201000 # number of ReadReq MSHR miss cycles
329system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 334368500 # number of ReadReq MSHR miss cycles
330system.l2c.ReadReq_mshr_miss_latency::cpu0.data 352448500 # number of ReadReq MSHR miss cycles
331system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 2202500 # number of ReadReq MSHR miss cycles
332system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 40000 # number of ReadReq MSHR miss cycles
333system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 405321000 # number of ReadReq MSHR miss cycles
334system.l2c.ReadReq_mshr_miss_latency::cpu1.data 512811000 # number of ReadReq MSHR miss cycles
335system.l2c.ReadReq_mshr_miss_latency::total 1610636500 # number of ReadReq MSHR miss cycles
336system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 205370000 # number of UpgradeReq MSHR miss cycles
337system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 227611500 # number of UpgradeReq MSHR miss cycles
338system.l2c.UpgradeReq_mshr_miss_latency::total 432981500 # number of UpgradeReq MSHR miss cycles
339system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 30499500 # number of SCUpgradeReq MSHR miss cycles
340system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23997000 # number of SCUpgradeReq MSHR miss cycles
341system.l2c.SCUpgradeReq_mshr_miss_latency::total 54496500 # number of SCUpgradeReq MSHR miss cycles
342system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2635763499 # number of ReadExReq MSHR miss cycles
343system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3271199500 # number of ReadExReq MSHR miss cycles
344system.l2c.ReadExReq_mshr_miss_latency::total 5906962999 # number of ReadExReq MSHR miss cycles
345system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3244000 # number of demand (read+write) MSHR miss cycles
346system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 201000 # number of demand (read+write) MSHR miss cycles
347system.l2c.demand_mshr_miss_latency::cpu0.inst 334368500 # number of demand (read+write) MSHR miss cycles
348system.l2c.demand_mshr_miss_latency::cpu0.data 2988211999 # number of demand (read+write) MSHR miss cycles
349system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 2202500 # number of demand (read+write) MSHR miss cycles
350system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 40000 # number of demand (read+write) MSHR miss cycles
351system.l2c.demand_mshr_miss_latency::cpu1.inst 405321000 # number of demand (read+write) MSHR miss cycles
352system.l2c.demand_mshr_miss_latency::cpu1.data 3784010500 # number of demand (read+write) MSHR miss cycles
353system.l2c.demand_mshr_miss_latency::total 7517599499 # number of demand (read+write) MSHR miss cycles
354system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3244000 # number of overall MSHR miss cycles
355system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 201000 # number of overall MSHR miss cycles
356system.l2c.overall_mshr_miss_latency::cpu0.inst 334368500 # number of overall MSHR miss cycles
357system.l2c.overall_mshr_miss_latency::cpu0.data 2988211999 # number of overall MSHR miss cycles
358system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2202500 # number of overall MSHR miss cycles
359system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 40000 # number of overall MSHR miss cycles
360system.l2c.overall_mshr_miss_latency::cpu1.inst 405321000 # number of overall MSHR miss cycles
361system.l2c.overall_mshr_miss_latency::cpu1.data 3784010500 # number of overall MSHR miss cycles
362system.l2c.overall_mshr_miss_latency::total 7517599499 # number of overall MSHR miss cycles
363system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5668500 # number of ReadReq MSHR uncacheable cycles
364system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 8247511500 # number of ReadReq MSHR uncacheable cycles
365system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1931000 # number of ReadReq MSHR uncacheable cycles
366system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 123718931000 # number of ReadReq MSHR uncacheable cycles
367system.l2c.ReadReq_mshr_uncacheable_latency::total 131974042000 # number of ReadReq MSHR uncacheable cycles
368system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 707206480 # number of WriteReq MSHR uncacheable cycles
369system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31817900108 # number of WriteReq MSHR uncacheable cycles
370system.l2c.WriteReq_mshr_uncacheable_latency::total 32525106588 # number of WriteReq MSHR uncacheable cycles
371system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5668500 # number of overall MSHR uncacheable cycles
372system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8954717980 # number of overall MSHR uncacheable cycles
373system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1931000 # number of overall MSHR uncacheable cycles
374system.l2c.overall_mshr_uncacheable_latency::cpu1.data 155536831108 # number of overall MSHR uncacheable cycles
375system.l2c.overall_mshr_uncacheable_latency::total 164499148588 # number of overall MSHR uncacheable cycles
376system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001633 # mshr miss rate for ReadReq accesses
377system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000673 # mshr miss rate for ReadReq accesses
378system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.024510 # mshr miss rate for ReadReq accesses
379system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.062069 # mshr miss rate for ReadReq accesses
380system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000486 # mshr miss rate for ReadReq accesses
381system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000132 # mshr miss rate for ReadReq accesses
382system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014231 # mshr miss rate for ReadReq accesses
383system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.052363 # mshr miss rate for ReadReq accesses
384system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.851096 # mshr miss rate for UpgradeReq accesses
385system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.835341 # mshr miss rate for UpgradeReq accesses
386system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.795407 # mshr miss rate for SCUpgradeReq accesses
387system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.610601 # mshr miss rate for SCUpgradeReq accesses
388system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.650474 # mshr miss rate for ReadExReq accesses
389system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.552889 # mshr miss rate for ReadExReq accesses
390system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001633 # mshr miss rate for demand accesses
391system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000673 # mshr miss rate for demand accesses
392system.l2c.demand_mshr_miss_rate::cpu0.inst 0.024510 # mshr miss rate for demand accesses
393system.l2c.demand_mshr_miss_rate::cpu0.data 0.307215 # mshr miss rate for demand accesses
394system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000486 # mshr miss rate for demand accesses
395system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000132 # mshr miss rate for demand accesses
396system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014231 # mshr miss rate for demand accesses
397system.l2c.demand_mshr_miss_rate::cpu1.data 0.240758 # mshr miss rate for demand accesses
398system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001633 # mshr miss rate for overall accesses
399system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000673 # mshr miss rate for overall accesses
400system.l2c.overall_mshr_miss_rate::cpu0.inst 0.024510 # mshr miss rate for overall accesses
401system.l2c.overall_mshr_miss_rate::cpu0.data 0.307215 # mshr miss rate for overall accesses
402system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000486 # mshr miss rate for overall accesses
403system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000132 # mshr miss rate for overall accesses
404system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014231 # mshr miss rate for overall accesses
405system.l2c.overall_mshr_miss_rate::cpu1.data 0.240758 # mshr miss rate for overall accesses
406system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40049.382716 # average ReadReq mshr miss latency
407system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average ReadReq mshr miss latency
408system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40077.729833 # average ReadReq mshr miss latency
409system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40064.624304 # average ReadReq mshr miss latency
410system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40045.454545 # average ReadReq mshr miss latency
411system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency
412system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40114.904988 # average ReadReq mshr miss latency
413system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40060.229670 # average ReadReq mshr miss latency
414system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40056.563292 # average UpgradeReq mshr miss latency
415system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40023.122912 # average UpgradeReq mshr miss latency
416system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40025.590551 # average SCUpgradeReq mshr miss latency
417system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40061.769616 # average SCUpgradeReq mshr miss latency
418system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.251925 # average ReadExReq mshr miss latency
419system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40097.565610 # average ReadExReq mshr miss latency
420system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40049.382716 # average overall mshr miss latency
421system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency
422system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40077.729833 # average overall mshr miss latency
423system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40036.067405 # average overall mshr miss latency
424system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40045.454545 # average overall mshr miss latency
425system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
426system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40114.904988 # average overall mshr miss latency
427system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40092.501748 # average overall mshr miss latency
428system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40049.382716 # average overall mshr miss latency
429system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency
430system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40077.729833 # average overall mshr miss latency
431system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40036.067405 # average overall mshr miss latency
432system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40045.454545 # average overall mshr miss latency
433system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
434system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40114.904988 # average overall mshr miss latency
435system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40092.501748 # average overall mshr miss latency
436system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
437system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
438system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
439system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
440system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
441system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
442system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
443system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
444system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
445system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
446system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
447system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
448system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
449system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
450system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
451system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
452system.cf0.dma_write_txs 0 # Number of DMA write transactions.
453system.cpu0.dtb.inst_hits 0 # ITB inst hits
454system.cpu0.dtb.inst_misses 0 # ITB inst misses
455system.cpu0.dtb.read_hits 7527759 # DTB read hits
456system.cpu0.dtb.read_misses 31435 # DTB read misses
457system.cpu0.dtb.write_hits 4435696 # DTB write hits
458system.cpu0.dtb.write_misses 6033 # DTB write misses
459system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
460system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
461system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
462system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
463system.cpu0.dtb.flush_entries 2072 # Number of entries that have been flushed from TLB
464system.cpu0.dtb.align_faults 4328 # Number of TLB faults due to alignment restrictions
465system.cpu0.dtb.prefetch_faults 228 # Number of TLB faults due to prefetch
466system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
467system.cpu0.dtb.perms_faults 803 # Number of TLB faults due to permissions restrictions
468system.cpu0.dtb.read_accesses 7559194 # DTB read accesses
469system.cpu0.dtb.write_accesses 4441729 # DTB write accesses
470system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
471system.cpu0.dtb.hits 11963455 # DTB hits
472system.cpu0.dtb.misses 37468 # DTB misses
473system.cpu0.dtb.accesses 12000923 # DTB accesses
474system.cpu0.itb.inst_hits 3809486 # ITB inst hits
475system.cpu0.itb.inst_misses 6280 # ITB inst misses
476system.cpu0.itb.read_hits 0 # DTB read hits
477system.cpu0.itb.read_misses 0 # DTB read misses
478system.cpu0.itb.write_hits 0 # DTB write hits
479system.cpu0.itb.write_misses 0 # DTB write misses
480system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
481system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
482system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
483system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
484system.cpu0.itb.flush_entries 1380 # Number of entries that have been flushed from TLB
485system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
486system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
487system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
488system.cpu0.itb.perms_faults 1824 # Number of TLB faults due to permissions restrictions
489system.cpu0.itb.read_accesses 0 # DTB read accesses
490system.cpu0.itb.write_accesses 0 # DTB write accesses
491system.cpu0.itb.inst_accesses 3815766 # ITB inst accesses
492system.cpu0.itb.hits 3809486 # DTB hits
493system.cpu0.itb.misses 6280 # DTB misses
494system.cpu0.itb.accesses 3815766 # DTB accesses
495system.cpu0.numCycles 55441069 # number of cpu cycles simulated
496system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
497system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
498system.cpu0.BPredUnit.lookups 5212892 # Number of BP lookups
499system.cpu0.BPredUnit.condPredicted 3951494 # Number of conditional branches predicted
500system.cpu0.BPredUnit.condIncorrect 295394 # Number of conditional branches incorrect
501system.cpu0.BPredUnit.BTBLookups 3415998 # Number of BTB lookups
502system.cpu0.BPredUnit.BTBHits 2549557 # Number of BTB hits
503system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
504system.cpu0.BPredUnit.usedRAS 460779 # Number of times the RAS was used to get a target.
505system.cpu0.BPredUnit.RASInCorrect 62243 # Number of incorrect RAS predictions.
506system.cpu0.fetch.icacheStallCycles 10453565 # Number of cycles fetch is stalled on an Icache miss
507system.cpu0.fetch.Insts 27421447 # Number of instructions fetch has processed
508system.cpu0.fetch.Branches 5212892 # Number of branches that fetch encountered
509system.cpu0.fetch.predictedBranches 3010336 # Number of branches that fetch has predicted taken
510system.cpu0.fetch.Cycles 6440117 # Number of cycles fetch has run and was not squashing or blocked
511system.cpu0.fetch.SquashCycles 1388454 # Number of cycles fetch has spent squashing
512system.cpu0.fetch.TlbCycles 65669 # Number of cycles fetch has spent waiting for tlb
513system.cpu0.fetch.BlockedCycles 17512846 # Number of cycles fetch has spent blocked
514system.cpu0.fetch.MiscStallCycles 6544 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
515system.cpu0.fetch.PendingTrapStallCycles 31892 # Number of stall cycles due to pending traps
516system.cpu0.fetch.PendingQuiesceStallCycles 74131 # Number of stall cycles due to pending quiesce instructions
517system.cpu0.fetch.IcacheWaitRetryStallCycles 256 # Number of stall cycles due to full MSHR
518system.cpu0.fetch.CacheLines 3807333 # Number of cache lines fetched
519system.cpu0.fetch.IcacheSquashes 161414 # Number of outstanding Icache misses that were squashed
520system.cpu0.fetch.ItlbSquashes 4002 # Number of outstanding ITLB misses that were squashed
521system.cpu0.fetch.rateDist::samples 35574590 # Number of instructions fetched each cycle (Total)
522system.cpu0.fetch.rateDist::mean 1.004938 # Number of instructions fetched each cycle (Total)
523system.cpu0.fetch.rateDist::stdev 2.398361 # Number of instructions fetched each cycle (Total)
524system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
525system.cpu0.fetch.rateDist::0 29140690 81.91% 81.91% # Number of instructions fetched each cycle (Total)
526system.cpu0.fetch.rateDist::1 530074 1.49% 83.40% # Number of instructions fetched each cycle (Total)
527system.cpu0.fetch.rateDist::2 686036 1.93% 85.33% # Number of instructions fetched each cycle (Total)
528system.cpu0.fetch.rateDist::3 575113 1.62% 86.95% # Number of instructions fetched each cycle (Total)
529system.cpu0.fetch.rateDist::4 516761 1.45% 88.40% # Number of instructions fetched each cycle (Total)
530system.cpu0.fetch.rateDist::5 484002 1.36% 89.76% # Number of instructions fetched each cycle (Total)
531system.cpu0.fetch.rateDist::6 574923 1.62% 91.38% # Number of instructions fetched each cycle (Total)
532system.cpu0.fetch.rateDist::7 349762 0.98% 92.36% # Number of instructions fetched each cycle (Total)
533system.cpu0.fetch.rateDist::8 2717229 7.64% 100.00% # Number of instructions fetched each cycle (Total)
534system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
535system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
536system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
537system.cpu0.fetch.rateDist::total 35574590 # Number of instructions fetched each cycle (Total)
538system.cpu0.fetch.branchRate 0.094026 # Number of branch fetches per cycle
539system.cpu0.fetch.rate 0.494605 # Number of inst fetches per cycle
540system.cpu0.decode.IdleCycles 10814757 # Number of cycles decode is idle
541system.cpu0.decode.BlockedCycles 17563508 # Number of cycles decode is blocked
542system.cpu0.decode.RunCycles 5782354 # Number of cycles decode is running
543system.cpu0.decode.UnblockCycles 479006 # Number of cycles decode is unblocking
544system.cpu0.decode.SquashCycles 934965 # Number of cycles decode is squashing
545system.cpu0.decode.BranchResolved 835529 # Number of times decode resolved a branch
546system.cpu0.decode.BranchMispred 55823 # Number of times decode detected a branch misprediction
547system.cpu0.decode.DecodedInsts 34470555 # Number of instructions handled by decode
548system.cpu0.decode.SquashedInsts 179479 # Number of squashed instructions handled by decode
549system.cpu0.rename.SquashCycles 934965 # Number of cycles rename is squashing
550system.cpu0.rename.IdleCycles 11326555 # Number of cycles rename is idle
551system.cpu0.rename.BlockCycles 4595002 # Number of cycles rename is blocking
552system.cpu0.rename.serializeStallCycles 11316835 # count of cycles rename stalled for serializing inst
553system.cpu0.rename.RunCycles 5729017 # Number of cycles rename is running
554system.cpu0.rename.UnblockCycles 1672216 # Number of cycles rename is unblocking
555system.cpu0.rename.RenamedInsts 33303546 # Number of instructions processed by rename
556system.cpu0.rename.ROBFullEvents 955 # Number of times rename has blocked due to ROB full
557system.cpu0.rename.IQFullEvents 363738 # Number of times rename has blocked due to IQ full
558system.cpu0.rename.LSQFullEvents 882856 # Number of times rename has blocked due to LSQ full
559system.cpu0.rename.FullRegisterEvents 34 # Number of times there has been no free registers
560system.cpu0.rename.RenamedOperands 33389165 # Number of destination operands rename has renamed
561system.cpu0.rename.RenameLookups 151283000 # Number of register rename lookups that rename has made
562system.cpu0.rename.int_rename_lookups 151242578 # Number of integer rename lookups
563system.cpu0.rename.fp_rename_lookups 40422 # Number of floating rename lookups
564system.cpu0.rename.CommittedMaps 25698465 # Number of HB maps that are committed
565system.cpu0.rename.UndoneMaps 7690700 # Number of HB maps that are undone due to squashing
566system.cpu0.rename.serializingInsts 390539 # count of serializing insts renamed
567system.cpu0.rename.tempSerializingInsts 354252 # count of temporary serializing insts renamed
568system.cpu0.rename.skidInsts 4298434 # count of insts added to the skid buffer
569system.cpu0.memDep0.insertedLoads 6455423 # Number of loads inserted to the mem dependence unit.
570system.cpu0.memDep0.insertedStores 4976732 # Number of stores inserted to the mem dependence unit.
571system.cpu0.memDep0.conflictingLoads 849969 # Number of conflicting loads.
572system.cpu0.memDep0.conflictingStores 853540 # Number of conflicting stores.
573system.cpu0.iq.iqInstsAdded 31433505 # Number of instructions added to the IQ (excludes non-spec)
574system.cpu0.iq.iqNonSpecInstsAdded 659467 # Number of non-speculative instructions added to the IQ
575system.cpu0.iq.iqInstsIssued 31580110 # Number of instructions issued
576system.cpu0.iq.iqSquashedInstsIssued 81056 # Number of squashed instructions issued
577system.cpu0.iq.iqSquashedInstsExamined 5706071 # Number of squashed instructions iterated over during squash; mainly for profiling
578system.cpu0.iq.iqSquashedOperandsExamined 12925708 # Number of squashed operands that are examined and possibly removed from graph
579system.cpu0.iq.iqSquashedNonSpecRemoved 117932 # Number of squashed non-spec instructions that were removed
580system.cpu0.iq.issued_per_cycle::samples 35574590 # Number of insts issued each cycle
581system.cpu0.iq.issued_per_cycle::mean 0.887715 # Number of insts issued each cycle
582system.cpu0.iq.issued_per_cycle::stdev 1.519071 # Number of insts issued each cycle
583system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
584system.cpu0.iq.issued_per_cycle::0 22796169 64.08% 64.08% # Number of insts issued each cycle
585system.cpu0.iq.issued_per_cycle::1 4955890 13.93% 78.01% # Number of insts issued each cycle
586system.cpu0.iq.issued_per_cycle::2 2593205 7.29% 85.30% # Number of insts issued each cycle
587system.cpu0.iq.issued_per_cycle::3 1941493 5.46% 90.76% # Number of insts issued each cycle
588system.cpu0.iq.issued_per_cycle::4 1799462 5.06% 95.82% # Number of insts issued each cycle
589system.cpu0.iq.issued_per_cycle::5 771833 2.17% 97.99% # Number of insts issued each cycle
590system.cpu0.iq.issued_per_cycle::6 508602 1.43% 99.42% # Number of insts issued each cycle
591system.cpu0.iq.issued_per_cycle::7 158782 0.45% 99.86% # Number of insts issued each cycle
592system.cpu0.iq.issued_per_cycle::8 49154 0.14% 100.00% # Number of insts issued each cycle
593system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
594system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
595system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
596system.cpu0.iq.issued_per_cycle::total 35574590 # Number of insts issued each cycle
597system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
598system.cpu0.iq.fu_full::IntAlu 35384 3.74% 3.74% # attempts to use FU when none available
599system.cpu0.iq.fu_full::IntMult 453 0.05% 3.79% # attempts to use FU when none available
600system.cpu0.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available
601system.cpu0.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available
602system.cpu0.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available
603system.cpu0.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available
604system.cpu0.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available
605system.cpu0.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available
606system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available
607system.cpu0.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available
608system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available
609system.cpu0.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available
610system.cpu0.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available
611system.cpu0.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available
612system.cpu0.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available
613system.cpu0.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available
614system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available
615system.cpu0.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available
616system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available
617system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available
618system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available
619system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available
620system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available
621system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available
622system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available
623system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available
624system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available
625system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available
626system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available
627system.cpu0.iq.fu_full::MemRead 728574 76.99% 80.78% # attempts to use FU when none available
628system.cpu0.iq.fu_full::MemWrite 181906 19.22% 100.00% # attempts to use FU when none available
629system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
630system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
631system.cpu0.iq.FU_type_0::No_OpClass 14281 0.05% 0.05% # Type of FU issued
632system.cpu0.iq.FU_type_0::IntAlu 18843805 59.67% 59.72% # Type of FU issued
633system.cpu0.iq.FU_type_0::IntMult 42255 0.13% 59.85% # Type of FU issued
634system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.85% # Type of FU issued
635system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.85% # Type of FU issued
636system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.85% # Type of FU issued
637system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.85% # Type of FU issued
638system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.85% # Type of FU issued
639system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.85% # Type of FU issued
640system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.85% # Type of FU issued
641system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.85% # Type of FU issued
642system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.85% # Type of FU issued
643system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 59.85% # Type of FU issued
644system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.85% # Type of FU issued
645system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.85% # Type of FU issued
646system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 59.85% # Type of FU issued
647system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.85% # Type of FU issued
648system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.85% # Type of FU issued
649system.cpu0.iq.FU_type_0::SimdShift 7 0.00% 59.85% # Type of FU issued
650system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 59.85% # Type of FU issued
651system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.85% # Type of FU issued
652system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.85% # Type of FU issued
653system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.85% # Type of FU issued
654system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.85% # Type of FU issued
655system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.85% # Type of FU issued
656system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.85% # Type of FU issued
657system.cpu0.iq.FU_type_0::SimdFloatMisc 650 0.00% 59.85% # Type of FU issued
658system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.85% # Type of FU issued
659system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 59.85% # Type of FU issued
660system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.85% # Type of FU issued
661system.cpu0.iq.FU_type_0::MemRead 7938571 25.14% 84.99% # Type of FU issued
662system.cpu0.iq.FU_type_0::MemWrite 4740521 15.01% 100.00% # Type of FU issued
663system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
664system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
665system.cpu0.iq.FU_type_0::total 31580110 # Type of FU issued
666system.cpu0.iq.rate 0.569616 # Inst issue rate
667system.cpu0.iq.fu_busy_cnt 946317 # FU busy when requested
668system.cpu0.iq.fu_busy_rate 0.029966 # FU busy rate (busy events/executed inst)
669system.cpu0.iq.int_inst_queue_reads 99788129 # Number of integer instruction queue reads
670system.cpu0.iq.int_inst_queue_writes 37802639 # Number of integer instruction queue writes
671system.cpu0.iq.int_inst_queue_wakeup_accesses 28957807 # Number of integer instruction queue wakeup accesses
672system.cpu0.iq.fp_inst_queue_reads 10678 # Number of floating instruction queue reads
673system.cpu0.iq.fp_inst_queue_writes 5536 # Number of floating instruction queue writes
674system.cpu0.iq.fp_inst_queue_wakeup_accesses 4399 # Number of floating instruction queue wakeup accesses
675system.cpu0.iq.int_alu_accesses 32506335 # Number of integer alu accesses
676system.cpu0.iq.fp_alu_accesses 5811 # Number of floating point alu accesses
677system.cpu0.iew.lsq.thread0.forwLoads 253441 # Number of loads that had data forwarded from stores
678system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
679system.cpu0.iew.lsq.thread0.squashedLoads 1254358 # Number of loads squashed
680system.cpu0.iew.lsq.thread0.ignoredResponses 3684 # Number of memory responses ignored because the instruction is squashed
681system.cpu0.iew.lsq.thread0.memOrderViolation 9621 # Number of memory ordering violations
682system.cpu0.iew.lsq.thread0.squashedStores 525059 # Number of stores squashed
683system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
684system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
685system.cpu0.iew.lsq.thread0.rescheduledLoads 1901492 # Number of loads that were rescheduled
686system.cpu0.iew.lsq.thread0.cacheBlocked 5043 # Number of times an access to memory failed due to the cache being blocked
687system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
688system.cpu0.iew.iewSquashCycles 934965 # Number of cycles IEW is squashing
689system.cpu0.iew.iewBlockCycles 3498549 # Number of cycles IEW is blocking
690system.cpu0.iew.iewUnblockCycles 78984 # Number of cycles IEW is unblocking
691system.cpu0.iew.iewDispatchedInsts 32152208 # Number of instructions dispatched to IQ
692system.cpu0.iew.iewDispSquashedInsts 119958 # Number of squashed instructions skipped by dispatch
693system.cpu0.iew.iewDispLoadInsts 6455423 # Number of dispatched load instructions
694system.cpu0.iew.iewDispStoreInsts 4976732 # Number of dispatched store instructions
695system.cpu0.iew.iewDispNonSpecInsts 398786 # Number of dispatched non-speculative instructions
696system.cpu0.iew.iewIQFullEvents 38665 # Number of times the IQ has become full, causing a stall
697system.cpu0.iew.iewLSQFullEvents 4398 # Number of times the LSQ has become full, causing a stall
698system.cpu0.iew.memOrderViolationEvents 9621 # Number of memory order violations
699system.cpu0.iew.predictedTakenIncorrect 177464 # Number of branches that were predicted taken incorrectly
700system.cpu0.iew.predictedNotTakenIncorrect 119524 # Number of branches that were predicted not taken incorrectly
701system.cpu0.iew.branchMispredicts 296988 # Number of branch mispredicts detected at execute
702system.cpu0.iew.iewExecutedInsts 31195619 # Number of executed instructions
703system.cpu0.iew.iewExecLoadInsts 7789216 # Number of load instructions executed
704system.cpu0.iew.iewExecSquashedInsts 384491 # Number of squashed instructions skipped in execute
705system.cpu0.iew.exec_swp 0 # number of swp insts executed
706system.cpu0.iew.exec_nop 59236 # number of nop insts executed
707system.cpu0.iew.exec_refs 12477007 # number of memory reference insts executed
708system.cpu0.iew.exec_branches 4073990 # Number of branches executed
709system.cpu0.iew.exec_stores 4687791 # Number of stores executed
710system.cpu0.iew.exec_rate 0.562681 # Inst execution rate
711system.cpu0.iew.wb_sent 30989414 # cumulative count of insts sent to commit
712system.cpu0.iew.wb_count 28962206 # cumulative count of insts written-back
713system.cpu0.iew.wb_producers 15536163 # num instructions producing a value
714system.cpu0.iew.wb_consumers 30480637 # num instructions consuming a value
715system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
716system.cpu0.iew.wb_rate 0.522396 # insts written-back per cycle
717system.cpu0.iew.wb_fanout 0.509706 # average fanout of values written-back
718system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
719system.cpu0.commit.commitCommittedInsts 19711221 # The number of committed instructions
720system.cpu0.commit.commitCommittedOps 26183930 # The number of committed instructions
721system.cpu0.commit.commitSquashedInsts 5818378 # The number of squashed insts skipped by commit
722system.cpu0.commit.commitNonSpecStalls 541535 # The number of times commit has been forced to stall to communicate backwards
723system.cpu0.commit.branchMispredicts 256688 # The number of times a branch was mispredicted
724system.cpu0.commit.committed_per_cycle::samples 34668404 # Number of insts commited each cycle
725system.cpu0.commit.committed_per_cycle::mean 0.755268 # Number of insts commited each cycle
726system.cpu0.commit.committed_per_cycle::stdev 1.722296 # Number of insts commited each cycle
727system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
728system.cpu0.commit.committed_per_cycle::0 24842291 71.66% 71.66% # Number of insts commited each cycle
729system.cpu0.commit.committed_per_cycle::1 4903680 14.14% 85.80% # Number of insts commited each cycle
730system.cpu0.commit.committed_per_cycle::2 1598724 4.61% 90.41% # Number of insts commited each cycle
731system.cpu0.commit.committed_per_cycle::3 790644 2.28% 92.69% # Number of insts commited each cycle
732system.cpu0.commit.committed_per_cycle::4 613460 1.77% 94.46% # Number of insts commited each cycle
733system.cpu0.commit.committed_per_cycle::5 370313 1.07% 95.53% # Number of insts commited each cycle
734system.cpu0.commit.committed_per_cycle::6 401864 1.16% 96.69% # Number of insts commited each cycle
735system.cpu0.commit.committed_per_cycle::7 185143 0.53% 97.22% # Number of insts commited each cycle
736system.cpu0.commit.committed_per_cycle::8 962285 2.78% 100.00% # Number of insts commited each cycle
737system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
738system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
739system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
740system.cpu0.commit.committed_per_cycle::total 34668404 # Number of insts commited each cycle
741system.cpu0.commit.committedInsts 19711221 # Number of instructions committed
742system.cpu0.commit.committedOps 26183930 # Number of ops (including micro ops) committed
743system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
744system.cpu0.commit.refs 9652738 # Number of memory references committed
745system.cpu0.commit.loads 5201065 # Number of loads committed
746system.cpu0.commit.membars 194494 # Number of memory barriers committed
747system.cpu0.commit.branches 3582933 # Number of branches committed
748system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions.
749system.cpu0.commit.int_insts 23269679 # Number of committed integer instructions.
750system.cpu0.commit.function_calls 421897 # Number of function calls committed.
751system.cpu0.commit.bw_lim_events 962285 # number cycles where commit BW limit reached
752system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
753system.cpu0.rob.rob_reads 65094034 # The number of ROB reads
754system.cpu0.rob.rob_writes 64941259 # The number of ROB writes
755system.cpu0.timesIdled 360737 # Number of times that the entire CPU went into an idle state and unscheduled itself
756system.cpu0.idleCycles 19866479 # Total number of cycles that the CPU has spent unscheduled due to idling
757system.cpu0.quiesceCycles 5085563503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
758system.cpu0.committedInsts 19686667 # Number of Instructions Simulated
759system.cpu0.committedOps 26159376 # Number of Ops (including micro ops) Simulated
760system.cpu0.committedInsts_total 19686667 # Number of Instructions Simulated
761system.cpu0.cpi 2.816173 # CPI: Cycles Per Instruction
762system.cpu0.cpi_total 2.816173 # CPI: Total CPI of All Threads
763system.cpu0.ipc 0.355092 # IPC: Instructions Per Cycle
764system.cpu0.ipc_total 0.355092 # IPC: Total IPC of All Threads
765system.cpu0.int_regfile_reads 145393582 # number of integer regfile reads
766system.cpu0.int_regfile_writes 28417758 # number of integer regfile writes
767system.cpu0.fp_regfile_reads 4580 # number of floating regfile reads
768system.cpu0.fp_regfile_writes 450 # number of floating regfile writes
769system.cpu0.misc_regfile_reads 38939704 # number of misc regfile reads
770system.cpu0.misc_regfile_writes 443716 # number of misc regfile writes
771system.cpu0.icache.replacements 341473 # number of replacements
772system.cpu0.icache.tagsinuse 511.631456 # Cycle average of tags in use
773system.cpu0.icache.total_refs 3435816 # Total number of references to valid blocks.
774system.cpu0.icache.sampled_refs 341985 # Sample count of references to valid blocks.
775system.cpu0.icache.avg_refs 10.046686 # Average number of references to valid blocks.
776system.cpu0.icache.warmup_cycle 6333594000 # Cycle when the warmup percentage was hit.
777system.cpu0.icache.occ_blocks::cpu0.inst 511.631456 # Average occupied blocks per requestor
778system.cpu0.icache.occ_percent::cpu0.inst 0.999280 # Average percentage of cache occupancy
779system.cpu0.icache.occ_percent::total 0.999280 # Average percentage of cache occupancy
780system.cpu0.icache.ReadReq_hits::cpu0.inst 3435816 # number of ReadReq hits
781system.cpu0.icache.ReadReq_hits::total 3435816 # number of ReadReq hits
782system.cpu0.icache.demand_hits::cpu0.inst 3435816 # number of demand (read+write) hits
783system.cpu0.icache.demand_hits::total 3435816 # number of demand (read+write) hits
784system.cpu0.icache.overall_hits::cpu0.inst 3435816 # number of overall hits
785system.cpu0.icache.overall_hits::total 3435816 # number of overall hits
786system.cpu0.icache.ReadReq_misses::cpu0.inst 371369 # number of ReadReq misses
787system.cpu0.icache.ReadReq_misses::total 371369 # number of ReadReq misses
788system.cpu0.icache.demand_misses::cpu0.inst 371369 # number of demand (read+write) misses
789system.cpu0.icache.demand_misses::total 371369 # number of demand (read+write) misses
790system.cpu0.icache.overall_misses::cpu0.inst 371369 # number of overall misses
791system.cpu0.icache.overall_misses::total 371369 # number of overall misses
792system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5641865987 # number of ReadReq miss cycles
793system.cpu0.icache.ReadReq_miss_latency::total 5641865987 # number of ReadReq miss cycles
794system.cpu0.icache.demand_miss_latency::cpu0.inst 5641865987 # number of demand (read+write) miss cycles
795system.cpu0.icache.demand_miss_latency::total 5641865987 # number of demand (read+write) miss cycles
796system.cpu0.icache.overall_miss_latency::cpu0.inst 5641865987 # number of overall miss cycles
797system.cpu0.icache.overall_miss_latency::total 5641865987 # number of overall miss cycles
798system.cpu0.icache.ReadReq_accesses::cpu0.inst 3807185 # number of ReadReq accesses(hits+misses)
799system.cpu0.icache.ReadReq_accesses::total 3807185 # number of ReadReq accesses(hits+misses)
800system.cpu0.icache.demand_accesses::cpu0.inst 3807185 # number of demand (read+write) accesses
801system.cpu0.icache.demand_accesses::total 3807185 # number of demand (read+write) accesses
802system.cpu0.icache.overall_accesses::cpu0.inst 3807185 # number of overall (read+write) accesses
803system.cpu0.icache.overall_accesses::total 3807185 # number of overall (read+write) accesses
804system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097544 # miss rate for ReadReq accesses
805system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097544 # miss rate for demand accesses
806system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097544 # miss rate for overall accesses
807system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15192.075771 # average ReadReq miss latency
808system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15192.075771 # average overall miss latency
809system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15192.075771 # average overall miss latency
810system.cpu0.icache.blocked_cycles::no_mshrs 1691991 # number of cycles access was blocked
811system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
812system.cpu0.icache.blocked::no_mshrs 206 # number of cycles access was blocked
813system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
814system.cpu0.icache.avg_blocked_cycles::no_mshrs 8213.548544 # average number of cycles each access was blocked

815system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked

815system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

816system.cpu0.icache.fast_writes 0 # number of fast writes performed
817system.cpu0.icache.cache_copies 0 # number of cache copies performed
818system.cpu0.icache.writebacks::writebacks 19233 # number of writebacks
819system.cpu0.icache.writebacks::total 19233 # number of writebacks
820system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 29370 # number of ReadReq MSHR hits
821system.cpu0.icache.ReadReq_mshr_hits::total 29370 # number of ReadReq MSHR hits
822system.cpu0.icache.demand_mshr_hits::cpu0.inst 29370 # number of demand (read+write) MSHR hits
823system.cpu0.icache.demand_mshr_hits::total 29370 # number of demand (read+write) MSHR hits
824system.cpu0.icache.overall_mshr_hits::cpu0.inst 29370 # number of overall MSHR hits
825system.cpu0.icache.overall_mshr_hits::total 29370 # number of overall MSHR hits
826system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 341999 # number of ReadReq MSHR misses
827system.cpu0.icache.ReadReq_mshr_misses::total 341999 # number of ReadReq MSHR misses
828system.cpu0.icache.demand_mshr_misses::cpu0.inst 341999 # number of demand (read+write) MSHR misses
829system.cpu0.icache.demand_mshr_misses::total 341999 # number of demand (read+write) MSHR misses
830system.cpu0.icache.overall_mshr_misses::cpu0.inst 341999 # number of overall MSHR misses
831system.cpu0.icache.overall_mshr_misses::total 341999 # number of overall MSHR misses
832system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4224982491 # number of ReadReq MSHR miss cycles
833system.cpu0.icache.ReadReq_mshr_miss_latency::total 4224982491 # number of ReadReq MSHR miss cycles
834system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4224982491 # number of demand (read+write) MSHR miss cycles
835system.cpu0.icache.demand_mshr_miss_latency::total 4224982491 # number of demand (read+write) MSHR miss cycles
836system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4224982491 # number of overall MSHR miss cycles
837system.cpu0.icache.overall_mshr_miss_latency::total 4224982491 # number of overall MSHR miss cycles
838system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7615500 # number of ReadReq MSHR uncacheable cycles
839system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7615500 # number of ReadReq MSHR uncacheable cycles
840system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7615500 # number of overall MSHR uncacheable cycles
841system.cpu0.icache.overall_mshr_uncacheable_latency::total 7615500 # number of overall MSHR uncacheable cycles
842system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.089830 # mshr miss rate for ReadReq accesses
843system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.089830 # mshr miss rate for demand accesses
844system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.089830 # mshr miss rate for overall accesses
845system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12353.786096 # average ReadReq mshr miss latency
846system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12353.786096 # average overall mshr miss latency
847system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12353.786096 # average overall mshr miss latency
848system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
849system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
850system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
851system.cpu0.dcache.replacements 231957 # number of replacements
852system.cpu0.dcache.tagsinuse 430.483417 # Cycle average of tags in use
853system.cpu0.dcache.total_refs 7734943 # Total number of references to valid blocks.
854system.cpu0.dcache.sampled_refs 232325 # Sample count of references to valid blocks.
855system.cpu0.dcache.avg_refs 33.293632 # Average number of references to valid blocks.
856system.cpu0.dcache.warmup_cycle 49672000 # Cycle when the warmup percentage was hit.
857system.cpu0.dcache.occ_blocks::cpu0.data 430.483417 # Average occupied blocks per requestor
858system.cpu0.dcache.occ_percent::cpu0.data 0.840788 # Average percentage of cache occupancy
859system.cpu0.dcache.occ_percent::total 0.840788 # Average percentage of cache occupancy
860system.cpu0.dcache.ReadReq_hits::cpu0.data 4799900 # number of ReadReq hits
861system.cpu0.dcache.ReadReq_hits::total 4799900 # number of ReadReq hits
862system.cpu0.dcache.WriteReq_hits::cpu0.data 2590245 # number of WriteReq hits
863system.cpu0.dcache.WriteReq_hits::total 2590245 # number of WriteReq hits
864system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 154697 # number of LoadLockedReq hits
865system.cpu0.dcache.LoadLockedReq_hits::total 154697 # number of LoadLockedReq hits
866system.cpu0.dcache.StoreCondReq_hits::cpu0.data 152346 # number of StoreCondReq hits
867system.cpu0.dcache.StoreCondReq_hits::total 152346 # number of StoreCondReq hits
868system.cpu0.dcache.demand_hits::cpu0.data 7390145 # number of demand (read+write) hits
869system.cpu0.dcache.demand_hits::total 7390145 # number of demand (read+write) hits
870system.cpu0.dcache.overall_hits::cpu0.data 7390145 # number of overall hits
871system.cpu0.dcache.overall_hits::total 7390145 # number of overall hits
872system.cpu0.dcache.ReadReq_misses::cpu0.data 331500 # number of ReadReq misses
873system.cpu0.dcache.ReadReq_misses::total 331500 # number of ReadReq misses
874system.cpu0.dcache.WriteReq_misses::cpu0.data 1445399 # number of WriteReq misses
875system.cpu0.dcache.WriteReq_misses::total 1445399 # number of WriteReq misses
876system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8824 # number of LoadLockedReq misses
877system.cpu0.dcache.LoadLockedReq_misses::total 8824 # number of LoadLockedReq misses
878system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7928 # number of StoreCondReq misses
879system.cpu0.dcache.StoreCondReq_misses::total 7928 # number of StoreCondReq misses
880system.cpu0.dcache.demand_misses::cpu0.data 1776899 # number of demand (read+write) misses
881system.cpu0.dcache.demand_misses::total 1776899 # number of demand (read+write) misses
882system.cpu0.dcache.overall_misses::cpu0.data 1776899 # number of overall misses
883system.cpu0.dcache.overall_misses::total 1776899 # number of overall misses
884system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4661132500 # number of ReadReq miss cycles
885system.cpu0.dcache.ReadReq_miss_latency::total 4661132500 # number of ReadReq miss cycles
886system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 59622143898 # number of WriteReq miss cycles
887system.cpu0.dcache.WriteReq_miss_latency::total 59622143898 # number of WriteReq miss cycles
888system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 99172000 # number of LoadLockedReq miss cycles
889system.cpu0.dcache.LoadLockedReq_miss_latency::total 99172000 # number of LoadLockedReq miss cycles
890system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 83748000 # number of StoreCondReq miss cycles
891system.cpu0.dcache.StoreCondReq_miss_latency::total 83748000 # number of StoreCondReq miss cycles
892system.cpu0.dcache.demand_miss_latency::cpu0.data 64283276398 # number of demand (read+write) miss cycles
893system.cpu0.dcache.demand_miss_latency::total 64283276398 # number of demand (read+write) miss cycles
894system.cpu0.dcache.overall_miss_latency::cpu0.data 64283276398 # number of overall miss cycles
895system.cpu0.dcache.overall_miss_latency::total 64283276398 # number of overall miss cycles
896system.cpu0.dcache.ReadReq_accesses::cpu0.data 5131400 # number of ReadReq accesses(hits+misses)
897system.cpu0.dcache.ReadReq_accesses::total 5131400 # number of ReadReq accesses(hits+misses)
898system.cpu0.dcache.WriteReq_accesses::cpu0.data 4035644 # number of WriteReq accesses(hits+misses)
899system.cpu0.dcache.WriteReq_accesses::total 4035644 # number of WriteReq accesses(hits+misses)
900system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 163521 # number of LoadLockedReq accesses(hits+misses)
901system.cpu0.dcache.LoadLockedReq_accesses::total 163521 # number of LoadLockedReq accesses(hits+misses)
902system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160274 # number of StoreCondReq accesses(hits+misses)
903system.cpu0.dcache.StoreCondReq_accesses::total 160274 # number of StoreCondReq accesses(hits+misses)
904system.cpu0.dcache.demand_accesses::cpu0.data 9167044 # number of demand (read+write) accesses
905system.cpu0.dcache.demand_accesses::total 9167044 # number of demand (read+write) accesses
906system.cpu0.dcache.overall_accesses::cpu0.data 9167044 # number of overall (read+write) accesses
907system.cpu0.dcache.overall_accesses::total 9167044 # number of overall (read+write) accesses
908system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.064602 # miss rate for ReadReq accesses
909system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.358158 # miss rate for WriteReq accesses
910system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053962 # miss rate for LoadLockedReq accesses
911system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049465 # miss rate for StoreCondReq accesses
912system.cpu0.dcache.demand_miss_rate::cpu0.data 0.193836 # miss rate for demand accesses
913system.cpu0.dcache.overall_miss_rate::cpu0.data 0.193836 # miss rate for overall accesses
914system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14060.731523 # average ReadReq miss latency
915system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41249.609207 # average WriteReq miss latency
916system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11238.893926 # average LoadLockedReq miss latency
917system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10563.572149 # average StoreCondReq miss latency
918system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36177.225829 # average overall miss latency
919system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36177.225829 # average overall miss latency
920system.cpu0.dcache.blocked_cycles::no_mshrs 3382986 # number of cycles access was blocked
921system.cpu0.dcache.blocked_cycles::no_targets 2017500 # number of cycles access was blocked
922system.cpu0.dcache.blocked::no_mshrs 334 # number of cycles access was blocked
923system.cpu0.dcache.blocked::no_targets 95 # number of cycles access was blocked
924system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10128.700599 # average number of cycles each access was blocked
925system.cpu0.dcache.avg_blocked_cycles::no_targets 21236.842105 # average number of cycles each access was blocked
926system.cpu0.dcache.fast_writes 0 # number of fast writes performed
927system.cpu0.dcache.cache_copies 0 # number of cache copies performed
928system.cpu0.dcache.writebacks::writebacks 207854 # number of writebacks
929system.cpu0.dcache.writebacks::total 207854 # number of writebacks
930system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 173784 # number of ReadReq MSHR hits
931system.cpu0.dcache.ReadReq_mshr_hits::total 173784 # number of ReadReq MSHR hits
932system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1326908 # number of WriteReq MSHR hits
933system.cpu0.dcache.WriteReq_mshr_hits::total 1326908 # number of WriteReq MSHR hits
934system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 637 # number of LoadLockedReq MSHR hits
935system.cpu0.dcache.LoadLockedReq_mshr_hits::total 637 # number of LoadLockedReq MSHR hits
936system.cpu0.dcache.demand_mshr_hits::cpu0.data 1500692 # number of demand (read+write) MSHR hits
937system.cpu0.dcache.demand_mshr_hits::total 1500692 # number of demand (read+write) MSHR hits
938system.cpu0.dcache.overall_mshr_hits::cpu0.data 1500692 # number of overall MSHR hits
939system.cpu0.dcache.overall_mshr_hits::total 1500692 # number of overall MSHR hits
940system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 157716 # number of ReadReq MSHR misses
941system.cpu0.dcache.ReadReq_mshr_misses::total 157716 # number of ReadReq MSHR misses
942system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 118491 # number of WriteReq MSHR misses
943system.cpu0.dcache.WriteReq_mshr_misses::total 118491 # number of WriteReq MSHR misses
944system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8187 # number of LoadLockedReq MSHR misses
945system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8187 # number of LoadLockedReq MSHR misses
946system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7924 # number of StoreCondReq MSHR misses
947system.cpu0.dcache.StoreCondReq_mshr_misses::total 7924 # number of StoreCondReq MSHR misses
948system.cpu0.dcache.demand_mshr_misses::cpu0.data 276207 # number of demand (read+write) MSHR misses
949system.cpu0.dcache.demand_mshr_misses::total 276207 # number of demand (read+write) MSHR misses
950system.cpu0.dcache.overall_mshr_misses::cpu0.data 276207 # number of overall MSHR misses
951system.cpu0.dcache.overall_mshr_misses::total 276207 # number of overall MSHR misses
952system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2028922000 # number of ReadReq MSHR miss cycles
953system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2028922000 # number of ReadReq MSHR miss cycles
954system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4262146485 # number of WriteReq MSHR miss cycles
955system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4262146485 # number of WriteReq MSHR miss cycles
956system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66363000 # number of LoadLockedReq MSHR miss cycles
957system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66363000 # number of LoadLockedReq MSHR miss cycles
958system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 59926500 # number of StoreCondReq MSHR miss cycles
959system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 59926500 # number of StoreCondReq MSHR miss cycles
960system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6291068485 # number of demand (read+write) MSHR miss cycles
961system.cpu0.dcache.demand_mshr_miss_latency::total 6291068485 # number of demand (read+write) MSHR miss cycles
962system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6291068485 # number of overall MSHR miss cycles
963system.cpu0.dcache.overall_mshr_miss_latency::total 6291068485 # number of overall MSHR miss cycles
964system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9234849500 # number of ReadReq MSHR uncacheable cycles
965system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9234849500 # number of ReadReq MSHR uncacheable cycles
966system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 843734891 # number of WriteReq MSHR uncacheable cycles
967system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 843734891 # number of WriteReq MSHR uncacheable cycles
968system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10078584391 # number of overall MSHR uncacheable cycles
969system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10078584391 # number of overall MSHR uncacheable cycles
970system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030735 # mshr miss rate for ReadReq accesses
971system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029361 # mshr miss rate for WriteReq accesses
972system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.050067 # mshr miss rate for LoadLockedReq accesses
973system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049440 # mshr miss rate for StoreCondReq accesses
974system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030130 # mshr miss rate for demand accesses
975system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030130 # mshr miss rate for overall accesses
976system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12864.401836 # average ReadReq mshr miss latency
977system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35970.212801 # average WriteReq mshr miss latency
978system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8105.899597 # average LoadLockedReq mshr miss latency
979system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7562.657749 # average StoreCondReq mshr miss latency
980system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22776.643912 # average overall mshr miss latency
981system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22776.643912 # average overall mshr miss latency
982system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
983system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
984system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
985system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
986system.cpu1.dtb.inst_hits 0 # ITB inst hits
987system.cpu1.dtb.inst_misses 0 # ITB inst misses
988system.cpu1.dtb.read_hits 45296976 # DTB read hits
989system.cpu1.dtb.read_misses 68040 # DTB read misses
990system.cpu1.dtb.write_hits 7958541 # DTB write hits
991system.cpu1.dtb.write_misses 20787 # DTB write misses
992system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
993system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
994system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
995system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
996system.cpu1.dtb.flush_entries 2725 # Number of entries that have been flushed from TLB
997system.cpu1.dtb.align_faults 7868 # Number of TLB faults due to alignment restrictions
998system.cpu1.dtb.prefetch_faults 603 # Number of TLB faults due to prefetch
999system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1000system.cpu1.dtb.perms_faults 1726 # Number of TLB faults due to permissions restrictions
1001system.cpu1.dtb.read_accesses 45365016 # DTB read accesses
1002system.cpu1.dtb.write_accesses 7979328 # DTB write accesses
1003system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1004system.cpu1.dtb.hits 53255517 # DTB hits
1005system.cpu1.dtb.misses 88827 # DTB misses
1006system.cpu1.dtb.accesses 53344344 # DTB accesses
1007system.cpu1.itb.inst_hits 10421118 # ITB inst hits
1008system.cpu1.itb.inst_misses 7923 # ITB inst misses
1009system.cpu1.itb.read_hits 0 # DTB read hits
1010system.cpu1.itb.read_misses 0 # DTB read misses
1011system.cpu1.itb.write_hits 0 # DTB write hits
1012system.cpu1.itb.write_misses 0 # DTB write misses
1013system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
1014system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1015system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1016system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1017system.cpu1.itb.flush_entries 1559 # Number of entries that have been flushed from TLB
1018system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1019system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1020system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1021system.cpu1.itb.perms_faults 4993 # Number of TLB faults due to permissions restrictions
1022system.cpu1.itb.read_accesses 0 # DTB read accesses
1023system.cpu1.itb.write_accesses 0 # DTB write accesses
1024system.cpu1.itb.inst_accesses 10429041 # ITB inst accesses
1025system.cpu1.itb.hits 10421118 # DTB hits
1026system.cpu1.itb.misses 7923 # DTB misses
1027system.cpu1.itb.accesses 10429041 # DTB accesses
1028system.cpu1.numCycles 361284565 # number of cpu cycles simulated
1029system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1030system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1031system.cpu1.BPredUnit.lookups 11160075 # Number of BP lookups
1032system.cpu1.BPredUnit.condPredicted 8957573 # Number of conditional branches predicted
1033system.cpu1.BPredUnit.condIncorrect 655963 # Number of conditional branches incorrect
1034system.cpu1.BPredUnit.BTBLookups 7602711 # Number of BTB lookups
1035system.cpu1.BPredUnit.BTBHits 6100291 # Number of BTB hits
1036system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1037system.cpu1.BPredUnit.usedRAS 909624 # Number of times the RAS was used to get a target.
1038system.cpu1.BPredUnit.RASInCorrect 143125 # Number of incorrect RAS predictions.
1039system.cpu1.fetch.icacheStallCycles 24152579 # Number of cycles fetch is stalled on an Icache miss
1040system.cpu1.fetch.Insts 79243321 # Number of instructions fetch has processed
1041system.cpu1.fetch.Branches 11160075 # Number of branches that fetch encountered
1042system.cpu1.fetch.predictedBranches 7009915 # Number of branches that fetch has predicted taken
1043system.cpu1.fetch.Cycles 17005367 # Number of cycles fetch has run and was not squashing or blocked
1044system.cpu1.fetch.SquashCycles 5503080 # Number of cycles fetch has spent squashing
1045system.cpu1.fetch.TlbCycles 106407 # Number of cycles fetch has spent waiting for tlb
1046system.cpu1.fetch.BlockedCycles 74478012 # Number of cycles fetch has spent blocked
1047system.cpu1.fetch.MiscStallCycles 5575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1048system.cpu1.fetch.PendingTrapStallCycles 116210 # Number of stall cycles due to pending traps
1049system.cpu1.fetch.PendingQuiesceStallCycles 165404 # Number of stall cycles due to pending quiesce instructions
1050system.cpu1.fetch.IcacheWaitRetryStallCycles 287 # Number of stall cycles due to full MSHR
1051system.cpu1.fetch.CacheLines 10415863 # Number of cache lines fetched
1052system.cpu1.fetch.IcacheSquashes 850791 # Number of outstanding Icache misses that were squashed
1053system.cpu1.fetch.ItlbSquashes 4371 # Number of outstanding ITLB misses that were squashed
1054system.cpu1.fetch.rateDist::samples 119805091 # Number of instructions fetched each cycle (Total)
1055system.cpu1.fetch.rateDist::mean 0.807068 # Number of instructions fetched each cycle (Total)
1056system.cpu1.fetch.rateDist::stdev 2.185605 # Number of instructions fetched each cycle (Total)
1057system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1058system.cpu1.fetch.rateDist::0 102809911 85.81% 85.81% # Number of instructions fetched each cycle (Total)
1059system.cpu1.fetch.rateDist::1 1026487 0.86% 86.67% # Number of instructions fetched each cycle (Total)
1060system.cpu1.fetch.rateDist::2 1244623 1.04% 87.71% # Number of instructions fetched each cycle (Total)
1061system.cpu1.fetch.rateDist::3 2220450 1.85% 89.56% # Number of instructions fetched each cycle (Total)
1062system.cpu1.fetch.rateDist::4 1447523 1.21% 90.77% # Number of instructions fetched each cycle (Total)
1063system.cpu1.fetch.rateDist::5 762352 0.64% 91.41% # Number of instructions fetched each cycle (Total)
1064system.cpu1.fetch.rateDist::6 2446430 2.04% 93.45% # Number of instructions fetched each cycle (Total)
1065system.cpu1.fetch.rateDist::7 545220 0.46% 93.91% # Number of instructions fetched each cycle (Total)
1066system.cpu1.fetch.rateDist::8 7302095 6.09% 100.00% # Number of instructions fetched each cycle (Total)
1067system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1068system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1069system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1070system.cpu1.fetch.rateDist::total 119805091 # Number of instructions fetched each cycle (Total)
1071system.cpu1.fetch.branchRate 0.030890 # Number of branch fetches per cycle
1072system.cpu1.fetch.rate 0.219338 # Number of inst fetches per cycle
1073system.cpu1.decode.IdleCycles 25854345 # Number of cycles decode is idle
1074system.cpu1.decode.BlockedCycles 74385490 # Number of cycles decode is blocked
1075system.cpu1.decode.RunCycles 15310008 # Number of cycles decode is running
1076system.cpu1.decode.UnblockCycles 600331 # Number of cycles decode is unblocking
1077system.cpu1.decode.SquashCycles 3654917 # Number of cycles decode is squashing
1078system.cpu1.decode.BranchResolved 1553748 # Number of times decode resolved a branch
1079system.cpu1.decode.BranchMispred 123029 # Number of times decode detected a branch misprediction
1080system.cpu1.decode.DecodedInsts 89962683 # Number of instructions handled by decode
1081system.cpu1.decode.SquashedInsts 400925 # Number of squashed instructions handled by decode
1082system.cpu1.rename.SquashCycles 3654917 # Number of cycles rename is squashing
1083system.cpu1.rename.IdleCycles 27463225 # Number of cycles rename is idle
1084system.cpu1.rename.BlockCycles 32802291 # Number of cycles rename is blocking
1085system.cpu1.rename.serializeStallCycles 37038310 # count of cycles rename stalled for serializing inst
1086system.cpu1.rename.RunCycles 14280523 # Number of cycles rename is running
1087system.cpu1.rename.UnblockCycles 4565825 # Number of cycles rename is unblocking
1088system.cpu1.rename.RenamedInsts 83469542 # Number of instructions processed by rename
1089system.cpu1.rename.ROBFullEvents 3103 # Number of times rename has blocked due to ROB full
1090system.cpu1.rename.IQFullEvents 679234 # Number of times rename has blocked due to IQ full
1091system.cpu1.rename.LSQFullEvents 3297923 # Number of times rename has blocked due to LSQ full
1092system.cpu1.rename.FullRegisterEvents 45820 # Number of times there has been no free registers
1093system.cpu1.rename.RenamedOperands 88189114 # Number of destination operands rename has renamed
1094system.cpu1.rename.RenameLookups 385593776 # Number of register rename lookups that rename has made
1095system.cpu1.rename.int_rename_lookups 385544391 # Number of integer rename lookups
1096system.cpu1.rename.fp_rename_lookups 49385 # Number of floating rename lookups
1097system.cpu1.rename.CommittedMaps 54868386 # Number of HB maps that are committed
1098system.cpu1.rename.UndoneMaps 33320727 # Number of HB maps that are undone due to squashing
1099system.cpu1.rename.serializingInsts 602216 # count of serializing insts renamed
1100system.cpu1.rename.tempSerializingInsts 524905 # count of temporary serializing insts renamed
1101system.cpu1.rename.skidInsts 8650801 # count of insts added to the skid buffer
1102system.cpu1.memDep0.insertedLoads 16023709 # Number of loads inserted to the mem dependence unit.
1103system.cpu1.memDep0.insertedStores 9632090 # Number of stores inserted to the mem dependence unit.
1104system.cpu1.memDep0.conflictingLoads 1276299 # Number of conflicting loads.
1105system.cpu1.memDep0.conflictingStores 1729146 # Number of conflicting stores.
1106system.cpu1.iq.iqInstsAdded 74907136 # Number of instructions added to the IQ (excludes non-spec)
1107system.cpu1.iq.iqNonSpecInstsAdded 1031599 # Number of non-speculative instructions added to the IQ
1108system.cpu1.iq.iqInstsIssued 98321113 # Number of instructions issued
1109system.cpu1.iq.iqSquashedInstsIssued 155877 # Number of squashed instructions issued
1110system.cpu1.iq.iqSquashedInstsExamined 21592981 # Number of squashed instructions iterated over during squash; mainly for profiling
1111system.cpu1.iq.iqSquashedOperandsExamined 61005208 # Number of squashed operands that are examined and possibly removed from graph
1112system.cpu1.iq.iqSquashedNonSpecRemoved 224170 # Number of squashed non-spec instructions that were removed
1113system.cpu1.iq.issued_per_cycle::samples 119805091 # Number of insts issued each cycle
1114system.cpu1.iq.issued_per_cycle::mean 0.820676 # Number of insts issued each cycle
1115system.cpu1.iq.issued_per_cycle::stdev 1.545860 # Number of insts issued each cycle
1116system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1117system.cpu1.iq.issued_per_cycle::0 85906342 71.71% 71.71% # Number of insts issued each cycle
1118system.cpu1.iq.issued_per_cycle::1 9617362 8.03% 79.73% # Number of insts issued each cycle
1119system.cpu1.iq.issued_per_cycle::2 5105765 4.26% 83.99% # Number of insts issued each cycle
1120system.cpu1.iq.issued_per_cycle::3 4221138 3.52% 87.52% # Number of insts issued each cycle
1121system.cpu1.iq.issued_per_cycle::4 11132119 9.29% 96.81% # Number of insts issued each cycle
1122system.cpu1.iq.issued_per_cycle::5 2139642 1.79% 98.60% # Number of insts issued each cycle
1123system.cpu1.iq.issued_per_cycle::6 1275484 1.06% 99.66% # Number of insts issued each cycle
1124system.cpu1.iq.issued_per_cycle::7 308695 0.26% 99.92% # Number of insts issued each cycle
1125system.cpu1.iq.issued_per_cycle::8 98544 0.08% 100.00% # Number of insts issued each cycle
1126system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1127system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1128system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1129system.cpu1.iq.issued_per_cycle::total 119805091 # Number of insts issued each cycle
1130system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1131system.cpu1.iq.fu_full::IntAlu 44454 0.55% 0.55% # attempts to use FU when none available
1132system.cpu1.iq.fu_full::IntMult 993 0.01% 0.56% # attempts to use FU when none available
1133system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.56% # attempts to use FU when none available
1134system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.56% # attempts to use FU when none available
1135system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.56% # attempts to use FU when none available
1136system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.56% # attempts to use FU when none available
1137system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.56% # attempts to use FU when none available
1138system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.56% # attempts to use FU when none available
1139system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.56% # attempts to use FU when none available
1140system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.56% # attempts to use FU when none available
1141system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.56% # attempts to use FU when none available
1142system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.56% # attempts to use FU when none available
1143system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.56% # attempts to use FU when none available
1144system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.56% # attempts to use FU when none available
1145system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.56% # attempts to use FU when none available
1146system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.56% # attempts to use FU when none available
1147system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.56% # attempts to use FU when none available
1148system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.56% # attempts to use FU when none available
1149system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.56% # attempts to use FU when none available
1150system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.56% # attempts to use FU when none available
1151system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.56% # attempts to use FU when none available
1152system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.56% # attempts to use FU when none available
1153system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.56% # attempts to use FU when none available
1154system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.56% # attempts to use FU when none available
1155system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.56% # attempts to use FU when none available
1156system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.56% # attempts to use FU when none available
1157system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.56% # attempts to use FU when none available
1158system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.56% # attempts to use FU when none available
1159system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.56% # attempts to use FU when none available
1160system.cpu1.iq.fu_full::MemRead 7729676 95.36% 95.92% # attempts to use FU when none available
1161system.cpu1.iq.fu_full::MemWrite 330610 4.08% 100.00% # attempts to use FU when none available
1162system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1163system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1164system.cpu1.iq.FU_type_0::No_OpClass 92819 0.09% 0.09% # Type of FU issued
1165system.cpu1.iq.FU_type_0::IntAlu 43197176 43.93% 44.03% # Type of FU issued
1166system.cpu1.iq.FU_type_0::IntMult 69729 0.07% 44.10% # Type of FU issued
1167system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.10% # Type of FU issued
1168system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.10% # Type of FU issued
1169system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.10% # Type of FU issued
1170system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.10% # Type of FU issued
1171system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.10% # Type of FU issued
1172system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.10% # Type of FU issued
1173system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.10% # Type of FU issued
1174system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.10% # Type of FU issued
1175system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.10% # Type of FU issued
1176system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.10% # Type of FU issued
1177system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.10% # Type of FU issued
1178system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.10% # Type of FU issued
1179system.cpu1.iq.FU_type_0::SimdMisc 31 0.00% 44.10% # Type of FU issued
1180system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.10% # Type of FU issued
1181system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.10% # Type of FU issued
1182system.cpu1.iq.FU_type_0::SimdShift 38 0.00% 44.10% # Type of FU issued
1183system.cpu1.iq.FU_type_0::SimdShiftAcc 4 0.00% 44.10% # Type of FU issued
1184system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.10% # Type of FU issued
1185system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.10% # Type of FU issued
1186system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.10% # Type of FU issued
1187system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.10% # Type of FU issued
1188system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.10% # Type of FU issued
1189system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.10% # Type of FU issued
1190system.cpu1.iq.FU_type_0::SimdFloatMisc 1798 0.00% 44.10% # Type of FU issued
1191system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.10% # Type of FU issued
1192system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 44.10% # Type of FU issued
1193system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.10% # Type of FU issued
1194system.cpu1.iq.FU_type_0::MemRead 46580491 47.38% 91.48% # Type of FU issued
1195system.cpu1.iq.FU_type_0::MemWrite 8379023 8.52% 100.00% # Type of FU issued
1196system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1197system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1198system.cpu1.iq.FU_type_0::total 98321113 # Type of FU issued
1199system.cpu1.iq.rate 0.272143 # Inst issue rate
1200system.cpu1.iq.fu_busy_cnt 8105733 # FU busy when requested
1201system.cpu1.iq.fu_busy_rate 0.082441 # FU busy rate (busy events/executed inst)
1202system.cpu1.iq.int_inst_queue_reads 324785513 # Number of integer instruction queue reads
1203system.cpu1.iq.int_inst_queue_writes 97548571 # Number of integer instruction queue writes
1204system.cpu1.iq.int_inst_queue_wakeup_accesses 61562518 # Number of integer instruction queue wakeup accesses
1205system.cpu1.iq.fp_inst_queue_reads 11987 # Number of floating instruction queue reads
1206system.cpu1.iq.fp_inst_queue_writes 6778 # Number of floating instruction queue writes
1207system.cpu1.iq.fp_inst_queue_wakeup_accesses 5521 # Number of floating instruction queue wakeup accesses
1208system.cpu1.iq.int_alu_accesses 106327792 # Number of integer alu accesses
1209system.cpu1.iq.fp_alu_accesses 6235 # Number of floating point alu accesses
1210system.cpu1.iew.lsq.thread0.forwLoads 430499 # Number of loads that had data forwarded from stores
1211system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1212system.cpu1.iew.lsq.thread0.squashedLoads 4865573 # Number of loads squashed
1213system.cpu1.iew.lsq.thread0.ignoredResponses 7656 # Number of memory responses ignored because the instruction is squashed
1214system.cpu1.iew.lsq.thread0.memOrderViolation 24407 # Number of memory ordering violations
1215system.cpu1.iew.lsq.thread0.squashedStores 1834498 # Number of stores squashed
1216system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1217system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1218system.cpu1.iew.lsq.thread0.rescheduledLoads 32207869 # Number of loads that were rescheduled
1219system.cpu1.iew.lsq.thread0.cacheBlocked 1151172 # Number of times an access to memory failed due to the cache being blocked
1220system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1221system.cpu1.iew.iewSquashCycles 3654917 # Number of cycles IEW is squashing
1222system.cpu1.iew.iewBlockCycles 25274079 # Number of cycles IEW is blocking
1223system.cpu1.iew.iewUnblockCycles 368524 # Number of cycles IEW is unblocking
1224system.cpu1.iew.iewDispatchedInsts 76147540 # Number of instructions dispatched to IQ
1225system.cpu1.iew.iewDispSquashedInsts 230680 # Number of squashed instructions skipped by dispatch
1226system.cpu1.iew.iewDispLoadInsts 16023709 # Number of dispatched load instructions
1227system.cpu1.iew.iewDispStoreInsts 9632090 # Number of dispatched store instructions
1228system.cpu1.iew.iewDispNonSpecInsts 636792 # Number of dispatched non-speculative instructions
1229system.cpu1.iew.iewIQFullEvents 64221 # Number of times the IQ has become full, causing a stall
1230system.cpu1.iew.iewLSQFullEvents 8659 # Number of times the LSQ has become full, causing a stall
1231system.cpu1.iew.memOrderViolationEvents 24407 # Number of memory order violations
1232system.cpu1.iew.predictedTakenIncorrect 397735 # Number of branches that were predicted taken incorrectly
1233system.cpu1.iew.predictedNotTakenIncorrect 243587 # Number of branches that were predicted not taken incorrectly
1234system.cpu1.iew.branchMispredicts 641322 # Number of branch mispredicts detected at execute
1235system.cpu1.iew.iewExecutedInsts 95426692 # Number of executed instructions
1236system.cpu1.iew.iewExecLoadInsts 45740593 # Number of load instructions executed
1237system.cpu1.iew.iewExecSquashedInsts 2894421 # Number of squashed instructions skipped in execute
1238system.cpu1.iew.exec_swp 0 # number of swp insts executed
1239system.cpu1.iew.exec_nop 208805 # number of nop insts executed
1240system.cpu1.iew.exec_refs 54014697 # number of memory reference insts executed
1241system.cpu1.iew.exec_branches 8051531 # Number of branches executed
1242system.cpu1.iew.exec_stores 8274104 # Number of stores executed
1243system.cpu1.iew.exec_rate 0.264132 # Inst execution rate
1244system.cpu1.iew.wb_sent 94059839 # cumulative count of insts sent to commit
1245system.cpu1.iew.wb_count 61568039 # cumulative count of insts written-back
1246system.cpu1.iew.wb_producers 33920997 # num instructions producing a value
1247system.cpu1.iew.wb_consumers 61750617 # num instructions consuming a value
1248system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1249system.cpu1.iew.wb_rate 0.170414 # insts written-back per cycle
1250system.cpu1.iew.wb_fanout 0.549322 # average fanout of values written-back
1251system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1252system.cpu1.commit.commitCommittedInsts 42291661 # The number of committed instructions
1253system.cpu1.commit.commitCommittedOps 53866202 # The number of committed instructions
1254system.cpu1.commit.commitSquashedInsts 22216320 # The number of squashed insts skipped by commit
1255system.cpu1.commit.commitNonSpecStalls 807429 # The number of times commit has been forced to stall to communicate backwards
1256system.cpu1.commit.branchMispredicts 565831 # The number of times a branch was mispredicted
1257system.cpu1.commit.committed_per_cycle::samples 116206088 # Number of insts commited each cycle
1258system.cpu1.commit.committed_per_cycle::mean 0.463540 # Number of insts commited each cycle
1259system.cpu1.commit.committed_per_cycle::stdev 1.434749 # Number of insts commited each cycle
1260system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1261system.cpu1.commit.committed_per_cycle::0 97183761 83.63% 83.63% # Number of insts commited each cycle
1262system.cpu1.commit.committed_per_cycle::1 9338835 8.04% 91.67% # Number of insts commited each cycle
1263system.cpu1.commit.committed_per_cycle::2 2558958 2.20% 93.87% # Number of insts commited each cycle
1264system.cpu1.commit.committed_per_cycle::3 1577703 1.36% 95.23% # Number of insts commited each cycle
1265system.cpu1.commit.committed_per_cycle::4 1195507 1.03% 96.26% # Number of insts commited each cycle
1266system.cpu1.commit.committed_per_cycle::5 711645 0.61% 96.87% # Number of insts commited each cycle
1267system.cpu1.commit.committed_per_cycle::6 1133703 0.98% 97.84% # Number of insts commited each cycle
1268system.cpu1.commit.committed_per_cycle::7 513937 0.44% 98.29% # Number of insts commited each cycle
1269system.cpu1.commit.committed_per_cycle::8 1992039 1.71% 100.00% # Number of insts commited each cycle
1270system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1271system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1272system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1273system.cpu1.commit.committed_per_cycle::total 116206088 # Number of insts commited each cycle
1274system.cpu1.commit.committedInsts 42291661 # Number of instructions committed
1275system.cpu1.commit.committedOps 53866202 # Number of ops (including micro ops) committed
1276system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
1277system.cpu1.commit.refs 18955728 # Number of memory references committed
1278system.cpu1.commit.loads 11158136 # Number of loads committed
1279system.cpu1.commit.membars 242500 # Number of memory barriers committed
1280system.cpu1.commit.branches 6770430 # Number of branches committed
1281system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions.
1282system.cpu1.commit.int_insts 47963823 # Number of committed integer instructions.
1283system.cpu1.commit.function_calls 631876 # Number of function calls committed.
1284system.cpu1.commit.bw_lim_events 1992039 # number cycles where commit BW limit reached
1285system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
1286system.cpu1.rob.rob_reads 189074073 # The number of ROB reads
1287system.cpu1.rob.rob_writes 155943577 # The number of ROB writes
1288system.cpu1.timesIdled 1562911 # Number of times that the entire CPU went into an idle state and unscheduled itself
1289system.cpu1.idleCycles 241479474 # Total number of cycles that the CPU has spent unscheduled due to idling
1290system.cpu1.quiesceCycles 4780310719 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1291system.cpu1.committedInsts 42165834 # Number of Instructions Simulated
1292system.cpu1.committedOps 53740375 # Number of Ops (including micro ops) Simulated
1293system.cpu1.committedInsts_total 42165834 # Number of Instructions Simulated
1294system.cpu1.cpi 8.568183 # CPI: Cycles Per Instruction
1295system.cpu1.cpi_total 8.568183 # CPI: Total CPI of All Threads
1296system.cpu1.ipc 0.116711 # IPC: Instructions Per Cycle
1297system.cpu1.ipc_total 0.116711 # IPC: Total IPC of All Threads
1298system.cpu1.int_regfile_reads 429426444 # number of integer regfile reads
1299system.cpu1.int_regfile_writes 64384425 # number of integer regfile writes
1300system.cpu1.fp_regfile_reads 4325 # number of floating regfile reads
1301system.cpu1.fp_regfile_writes 2046 # number of floating regfile writes
1302system.cpu1.misc_regfile_reads 102104658 # number of misc regfile reads
1303system.cpu1.misc_regfile_writes 512737 # number of misc regfile writes
1304system.cpu1.icache.replacements 711552 # number of replacements
1305system.cpu1.icache.tagsinuse 498.766119 # Cycle average of tags in use
1306system.cpu1.icache.total_refs 9643450 # Total number of references to valid blocks.
1307system.cpu1.icache.sampled_refs 712064 # Sample count of references to valid blocks.
1308system.cpu1.icache.avg_refs 13.542954 # Average number of references to valid blocks.
1309system.cpu1.icache.warmup_cycle 74281042000 # Cycle when the warmup percentage was hit.
1310system.cpu1.icache.occ_blocks::cpu1.inst 498.766119 # Average occupied blocks per requestor
1311system.cpu1.icache.occ_percent::cpu1.inst 0.974153 # Average percentage of cache occupancy
1312system.cpu1.icache.occ_percent::total 0.974153 # Average percentage of cache occupancy
1313system.cpu1.icache.ReadReq_hits::cpu1.inst 9643450 # number of ReadReq hits
1314system.cpu1.icache.ReadReq_hits::total 9643450 # number of ReadReq hits
1315system.cpu1.icache.demand_hits::cpu1.inst 9643450 # number of demand (read+write) hits
1316system.cpu1.icache.demand_hits::total 9643450 # number of demand (read+write) hits
1317system.cpu1.icache.overall_hits::cpu1.inst 9643450 # number of overall hits
1318system.cpu1.icache.overall_hits::total 9643450 # number of overall hits
1319system.cpu1.icache.ReadReq_misses::cpu1.inst 772363 # number of ReadReq misses
1320system.cpu1.icache.ReadReq_misses::total 772363 # number of ReadReq misses
1321system.cpu1.icache.demand_misses::cpu1.inst 772363 # number of demand (read+write) misses
1322system.cpu1.icache.demand_misses::total 772363 # number of demand (read+write) misses
1323system.cpu1.icache.overall_misses::cpu1.inst 772363 # number of overall misses
1324system.cpu1.icache.overall_misses::total 772363 # number of overall misses
1325system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11329505492 # number of ReadReq miss cycles
1326system.cpu1.icache.ReadReq_miss_latency::total 11329505492 # number of ReadReq miss cycles
1327system.cpu1.icache.demand_miss_latency::cpu1.inst 11329505492 # number of demand (read+write) miss cycles
1328system.cpu1.icache.demand_miss_latency::total 11329505492 # number of demand (read+write) miss cycles
1329system.cpu1.icache.overall_miss_latency::cpu1.inst 11329505492 # number of overall miss cycles
1330system.cpu1.icache.overall_miss_latency::total 11329505492 # number of overall miss cycles
1331system.cpu1.icache.ReadReq_accesses::cpu1.inst 10415813 # number of ReadReq accesses(hits+misses)
1332system.cpu1.icache.ReadReq_accesses::total 10415813 # number of ReadReq accesses(hits+misses)
1333system.cpu1.icache.demand_accesses::cpu1.inst 10415813 # number of demand (read+write) accesses
1334system.cpu1.icache.demand_accesses::total 10415813 # number of demand (read+write) accesses
1335system.cpu1.icache.overall_accesses::cpu1.inst 10415813 # number of overall (read+write) accesses
1336system.cpu1.icache.overall_accesses::total 10415813 # number of overall (read+write) accesses
1337system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074153 # miss rate for ReadReq accesses
1338system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074153 # miss rate for demand accesses
1339system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074153 # miss rate for overall accesses
1340system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14668.627953 # average ReadReq miss latency
1341system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14668.627953 # average overall miss latency
1342system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14668.627953 # average overall miss latency
1343system.cpu1.icache.blocked_cycles::no_mshrs 1533994 # number of cycles access was blocked
1344system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1345system.cpu1.icache.blocked::no_mshrs 234 # number of cycles access was blocked
1346system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1347system.cpu1.icache.avg_blocked_cycles::no_mshrs 6555.529915 # average number of cycles each access was blocked

1348system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked

1348system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1349system.cpu1.icache.fast_writes 0 # number of fast writes performed
1350system.cpu1.icache.cache_copies 0 # number of cache copies performed
1351system.cpu1.icache.writebacks::writebacks 32964 # number of writebacks
1352system.cpu1.icache.writebacks::total 32964 # number of writebacks
1353system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 60264 # number of ReadReq MSHR hits
1354system.cpu1.icache.ReadReq_mshr_hits::total 60264 # number of ReadReq MSHR hits
1355system.cpu1.icache.demand_mshr_hits::cpu1.inst 60264 # number of demand (read+write) MSHR hits
1356system.cpu1.icache.demand_mshr_hits::total 60264 # number of demand (read+write) MSHR hits
1357system.cpu1.icache.overall_mshr_hits::cpu1.inst 60264 # number of overall MSHR hits
1358system.cpu1.icache.overall_mshr_hits::total 60264 # number of overall MSHR hits
1359system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 712099 # number of ReadReq MSHR misses
1360system.cpu1.icache.ReadReq_mshr_misses::total 712099 # number of ReadReq MSHR misses
1361system.cpu1.icache.demand_mshr_misses::cpu1.inst 712099 # number of demand (read+write) MSHR misses
1362system.cpu1.icache.demand_mshr_misses::total 712099 # number of demand (read+write) MSHR misses
1363system.cpu1.icache.overall_mshr_misses::cpu1.inst 712099 # number of overall MSHR misses
1364system.cpu1.icache.overall_mshr_misses::total 712099 # number of overall MSHR misses
1365system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8466389994 # number of ReadReq MSHR miss cycles
1366system.cpu1.icache.ReadReq_mshr_miss_latency::total 8466389994 # number of ReadReq MSHR miss cycles
1367system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8466389994 # number of demand (read+write) MSHR miss cycles
1368system.cpu1.icache.demand_mshr_miss_latency::total 8466389994 # number of demand (read+write) MSHR miss cycles
1369system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8466389994 # number of overall MSHR miss cycles
1370system.cpu1.icache.overall_mshr_miss_latency::total 8466389994 # number of overall MSHR miss cycles
1371system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2573500 # number of ReadReq MSHR uncacheable cycles
1372system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2573500 # number of ReadReq MSHR uncacheable cycles
1373system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2573500 # number of overall MSHR uncacheable cycles
1374system.cpu1.icache.overall_mshr_uncacheable_latency::total 2573500 # number of overall MSHR uncacheable cycles
1375system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068367 # mshr miss rate for ReadReq accesses
1376system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068367 # mshr miss rate for demand accesses
1377system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068367 # mshr miss rate for overall accesses
1378system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11889.344029 # average ReadReq mshr miss latency
1379system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11889.344029 # average overall mshr miss latency
1380system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11889.344029 # average overall mshr miss latency
1381system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
1382system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
1383system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1384system.cpu1.dcache.replacements 416651 # number of replacements
1385system.cpu1.dcache.tagsinuse 465.227268 # Cycle average of tags in use
1386system.cpu1.dcache.total_refs 15192855 # Total number of references to valid blocks.
1387system.cpu1.dcache.sampled_refs 417163 # Sample count of references to valid blocks.
1388system.cpu1.dcache.avg_refs 36.419469 # Average number of references to valid blocks.
1389system.cpu1.dcache.warmup_cycle 72551040000 # Cycle when the warmup percentage was hit.
1390system.cpu1.dcache.occ_blocks::cpu1.data 465.227268 # Average occupied blocks per requestor
1391system.cpu1.dcache.occ_percent::cpu1.data 0.908647 # Average percentage of cache occupancy
1392system.cpu1.dcache.occ_percent::total 0.908647 # Average percentage of cache occupancy
1393system.cpu1.dcache.ReadReq_hits::cpu1.data 10025124 # number of ReadReq hits
1394system.cpu1.dcache.ReadReq_hits::total 10025124 # number of ReadReq hits
1395system.cpu1.dcache.WriteReq_hits::cpu1.data 4871876 # number of WriteReq hits
1396system.cpu1.dcache.WriteReq_hits::total 4871876 # number of WriteReq hits
1397system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 126729 # number of LoadLockedReq hits
1398system.cpu1.dcache.LoadLockedReq_hits::total 126729 # number of LoadLockedReq hits
1399system.cpu1.dcache.StoreCondReq_hits::cpu1.data 119900 # number of StoreCondReq hits
1400system.cpu1.dcache.StoreCondReq_hits::total 119900 # number of StoreCondReq hits
1401system.cpu1.dcache.demand_hits::cpu1.data 14897000 # number of demand (read+write) hits
1402system.cpu1.dcache.demand_hits::total 14897000 # number of demand (read+write) hits
1403system.cpu1.dcache.overall_hits::cpu1.data 14897000 # number of overall hits
1404system.cpu1.dcache.overall_hits::total 14897000 # number of overall hits
1405system.cpu1.dcache.ReadReq_misses::cpu1.data 473956 # number of ReadReq misses
1406system.cpu1.dcache.ReadReq_misses::total 473956 # number of ReadReq misses
1407system.cpu1.dcache.WriteReq_misses::cpu1.data 1726769 # number of WriteReq misses
1408system.cpu1.dcache.WriteReq_misses::total 1726769 # number of WriteReq misses
1409system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14662 # number of LoadLockedReq misses
1410system.cpu1.dcache.LoadLockedReq_misses::total 14662 # number of LoadLockedReq misses
1411system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10568 # number of StoreCondReq misses
1412system.cpu1.dcache.StoreCondReq_misses::total 10568 # number of StoreCondReq misses
1413system.cpu1.dcache.demand_misses::cpu1.data 2200725 # number of demand (read+write) misses
1414system.cpu1.dcache.demand_misses::total 2200725 # number of demand (read+write) misses
1415system.cpu1.dcache.overall_misses::cpu1.data 2200725 # number of overall misses
1416system.cpu1.dcache.overall_misses::total 2200725 # number of overall misses
1417system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7150775500 # number of ReadReq miss cycles
1418system.cpu1.dcache.ReadReq_miss_latency::total 7150775500 # number of ReadReq miss cycles
1419system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 57296789383 # number of WriteReq miss cycles
1420system.cpu1.dcache.WriteReq_miss_latency::total 57296789383 # number of WriteReq miss cycles
1421system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 176168500 # number of LoadLockedReq miss cycles
1422system.cpu1.dcache.LoadLockedReq_miss_latency::total 176168500 # number of LoadLockedReq miss cycles
1423system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 91818000 # number of StoreCondReq miss cycles
1424system.cpu1.dcache.StoreCondReq_miss_latency::total 91818000 # number of StoreCondReq miss cycles
1425system.cpu1.dcache.demand_miss_latency::cpu1.data 64447564883 # number of demand (read+write) miss cycles
1426system.cpu1.dcache.demand_miss_latency::total 64447564883 # number of demand (read+write) miss cycles
1427system.cpu1.dcache.overall_miss_latency::cpu1.data 64447564883 # number of overall miss cycles
1428system.cpu1.dcache.overall_miss_latency::total 64447564883 # number of overall miss cycles
1429system.cpu1.dcache.ReadReq_accesses::cpu1.data 10499080 # number of ReadReq accesses(hits+misses)
1430system.cpu1.dcache.ReadReq_accesses::total 10499080 # number of ReadReq accesses(hits+misses)
1431system.cpu1.dcache.WriteReq_accesses::cpu1.data 6598645 # number of WriteReq accesses(hits+misses)
1432system.cpu1.dcache.WriteReq_accesses::total 6598645 # number of WriteReq accesses(hits+misses)
1433system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 141391 # number of LoadLockedReq accesses(hits+misses)
1434system.cpu1.dcache.LoadLockedReq_accesses::total 141391 # number of LoadLockedReq accesses(hits+misses)
1435system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 130468 # number of StoreCondReq accesses(hits+misses)
1436system.cpu1.dcache.StoreCondReq_accesses::total 130468 # number of StoreCondReq accesses(hits+misses)
1437system.cpu1.dcache.demand_accesses::cpu1.data 17097725 # number of demand (read+write) accesses
1438system.cpu1.dcache.demand_accesses::total 17097725 # number of demand (read+write) accesses
1439system.cpu1.dcache.overall_accesses::cpu1.data 17097725 # number of overall (read+write) accesses
1440system.cpu1.dcache.overall_accesses::total 17097725 # number of overall (read+write) accesses
1441system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045143 # miss rate for ReadReq accesses
1442system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.261685 # miss rate for WriteReq accesses
1443system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.103698 # miss rate for LoadLockedReq accesses
1444system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081001 # miss rate for StoreCondReq accesses
1445system.cpu1.dcache.demand_miss_rate::cpu1.data 0.128714 # miss rate for demand accesses
1446system.cpu1.dcache.overall_miss_rate::cpu1.data 0.128714 # miss rate for overall accesses
1447system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15087.424782 # average ReadReq miss latency
1448system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33181.502206 # average WriteReq miss latency
1449system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12015.311690 # average LoadLockedReq miss latency
1450system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8688.304315 # average StoreCondReq miss latency
1451system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29284.697035 # average overall miss latency
1452system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29284.697035 # average overall miss latency
1453system.cpu1.dcache.blocked_cycles::no_mshrs 15243046 # number of cycles access was blocked
1454system.cpu1.dcache.blocked_cycles::no_targets 5411000 # number of cycles access was blocked
1455system.cpu1.dcache.blocked::no_mshrs 3282 # number of cycles access was blocked
1456system.cpu1.dcache.blocked::no_targets 148 # number of cycles access was blocked
1457system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4644.438147 # average number of cycles each access was blocked
1458system.cpu1.dcache.avg_blocked_cycles::no_targets 36560.810811 # average number of cycles each access was blocked
1459system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1460system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1461system.cpu1.dcache.writebacks::writebacks 345826 # number of writebacks
1462system.cpu1.dcache.writebacks::total 345826 # number of writebacks
1463system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 203766 # number of ReadReq MSHR hits
1464system.cpu1.dcache.ReadReq_mshr_hits::total 203766 # number of ReadReq MSHR hits
1465system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1549585 # number of WriteReq MSHR hits
1466system.cpu1.dcache.WriteReq_mshr_hits::total 1549585 # number of WriteReq MSHR hits
1467system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1246 # number of LoadLockedReq MSHR hits
1468system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1246 # number of LoadLockedReq MSHR hits
1469system.cpu1.dcache.demand_mshr_hits::cpu1.data 1753351 # number of demand (read+write) MSHR hits
1470system.cpu1.dcache.demand_mshr_hits::total 1753351 # number of demand (read+write) MSHR hits
1471system.cpu1.dcache.overall_mshr_hits::cpu1.data 1753351 # number of overall MSHR hits
1472system.cpu1.dcache.overall_mshr_hits::total 1753351 # number of overall MSHR hits
1473system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 270190 # number of ReadReq MSHR misses
1474system.cpu1.dcache.ReadReq_mshr_misses::total 270190 # number of ReadReq MSHR misses
1475system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 177184 # number of WriteReq MSHR misses
1476system.cpu1.dcache.WriteReq_mshr_misses::total 177184 # number of WriteReq MSHR misses
1477system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13416 # number of LoadLockedReq MSHR misses
1478system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13416 # number of LoadLockedReq MSHR misses
1479system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10560 # number of StoreCondReq MSHR misses
1480system.cpu1.dcache.StoreCondReq_mshr_misses::total 10560 # number of StoreCondReq MSHR misses
1481system.cpu1.dcache.demand_mshr_misses::cpu1.data 447374 # number of demand (read+write) MSHR misses
1482system.cpu1.dcache.demand_mshr_misses::total 447374 # number of demand (read+write) MSHR misses
1483system.cpu1.dcache.overall_mshr_misses::cpu1.data 447374 # number of overall MSHR misses
1484system.cpu1.dcache.overall_mshr_misses::total 447374 # number of overall MSHR misses
1485system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3410102500 # number of ReadReq MSHR miss cycles
1486system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3410102500 # number of ReadReq MSHR miss cycles
1487system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5540518545 # number of WriteReq MSHR miss cycles
1488system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5540518545 # number of WriteReq MSHR miss cycles
1489system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 120430000 # number of LoadLockedReq MSHR miss cycles
1490system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 120430000 # number of LoadLockedReq MSHR miss cycles
1491system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 60079000 # number of StoreCondReq MSHR miss cycles
1492system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 60079000 # number of StoreCondReq MSHR miss cycles
1493system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
1494system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
1495system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8950621045 # number of demand (read+write) MSHR miss cycles
1496system.cpu1.dcache.demand_mshr_miss_latency::total 8950621045 # number of demand (read+write) MSHR miss cycles
1497system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8950621045 # number of overall MSHR miss cycles
1498system.cpu1.dcache.overall_mshr_miss_latency::total 8950621045 # number of overall MSHR miss cycles
1499system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 138186102000 # number of ReadReq MSHR uncacheable cycles
1500system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 138186102000 # number of ReadReq MSHR uncacheable cycles
1501system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41660941677 # number of WriteReq MSHR uncacheable cycles
1502system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41660941677 # number of WriteReq MSHR uncacheable cycles
1503system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179847043677 # number of overall MSHR uncacheable cycles
1504system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179847043677 # number of overall MSHR uncacheable cycles
1505system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025735 # mshr miss rate for ReadReq accesses
1506system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026852 # mshr miss rate for WriteReq accesses
1507system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.094886 # mshr miss rate for LoadLockedReq accesses
1508system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080939 # mshr miss rate for StoreCondReq accesses
1509system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026166 # mshr miss rate for demand accesses
1510system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026166 # mshr miss rate for overall accesses
1511system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12621.127725 # average ReadReq mshr miss latency
1512system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31269.858142 # average WriteReq mshr miss latency
1513system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8976.595110 # average LoadLockedReq mshr miss latency
1514system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5689.299242 # average StoreCondReq mshr miss latency
1515system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1516system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20007.021072 # average overall mshr miss latency
1517system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20007.021072 # average overall mshr miss latency
1518system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1519system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1520system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1521system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1522system.iocache.replacements 0 # number of replacements
1523system.iocache.tagsinuse 0 # Cycle average of tags in use
1524system.iocache.total_refs 0 # Total number of references to valid blocks.
1525system.iocache.sampled_refs 0 # Sample count of references to valid blocks.

1526system.iocache.avg_refs no_value # Average number of references to valid blocks.

1526system.iocache.avg_refs nan # Average number of references to valid blocks.

1527system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1528system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1529system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1530system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1531system.iocache.blocked::no_targets 0 # number of cycles access was blocked

1532system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
1533system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked

1532system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1533system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked