Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

Deleted Added

sdiff udiff text old ( 11530:6e143fd2cabf ) new ( 11547:dd6dfd38b6c2 )

full compact

stats.txt (11530:6e143fd2cabf)	stats.txt (11547:dd6dfd38b6c2)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.825960 # Number of seconds simulated 4sim_ticks 2825959731500 # Number of ticks simulated 5final_tick 2825959731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.825960 # Number of seconds simulated 4sim_ticks 2825959731500 # Number of ticks simulated 5final_tick 2825959731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 153141 # Simulator instruction rate (inst/s) 8host_op_rate 185771 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3602870624 # Simulator tick rate (ticks/s) 10host_mem_usage 666712 # Number of bytes of host memory used 11host_seconds 784.36 # Real time elapsed on the host	7host_inst_rate 99061 # Simulator instruction rate (inst/s) 8host_op_rate 120168 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2330545961 # Simulator tick rate (ticks/s) 10host_mem_usage 626024 # Number of bytes of host memory used 11host_seconds 1212.57 # Real time elapsed on the host
12sim_insts 120118276 # Number of instructions simulated 13sim_ops 145712235 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1306176 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1321704 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8517568 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 181104 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 644308 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 521472 # Number of bytes read from this memory 27system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 28system.physmem.bytes_read::total 12495724 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 1306176 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 181104 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 1487280 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 8956736 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 35system.physmem.bytes_written::total 8974300 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 22656 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 21172 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 133087 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.inst 2898 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 10088 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 8148 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 198102 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 139949 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 51system.physmem.num_writes::total 144340 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 611 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.inst 462206 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 467701 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 3014044 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 159 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.inst 64086 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 227996 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 184529 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::total 4421763 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 462206 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 64086 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 526292 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 3169449 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu0.data 6201 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::total 3175665 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 3169449 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 611 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.inst 462206 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 473902 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 3014044 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 159 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.inst 64086 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 228010 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 184529 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::total 7597427 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 198102 # Number of read requests accepted 85system.physmem.writeReqs 144340 # Number of write requests accepted 86system.physmem.readBursts 198102 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 144340 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 12669056 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue 90system.physmem.bytesWritten 8986944 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 12495724 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 8974300 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue 94system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 96system.physmem.perBankRdBursts::0 12421 # Per bank write bursts 97system.physmem.perBankRdBursts::1 12320 # Per bank write bursts 98system.physmem.perBankRdBursts::2 12949 # Per bank write bursts 99system.physmem.perBankRdBursts::3 12687 # Per bank write bursts 100system.physmem.perBankRdBursts::4 14539 # Per bank write bursts 101system.physmem.perBankRdBursts::5 12136 # Per bank write bursts 102system.physmem.perBankRdBursts::6 12666 # Per bank write bursts 103system.physmem.perBankRdBursts::7 12482 # Per bank write bursts 104system.physmem.perBankRdBursts::8 12195 # Per bank write bursts 105system.physmem.perBankRdBursts::9 12078 # Per bank write bursts 106system.physmem.perBankRdBursts::10 11738 # Per bank write bursts 107system.physmem.perBankRdBursts::11 11022 # Per bank write bursts 108system.physmem.perBankRdBursts::12 11908 # Per bank write bursts 109system.physmem.perBankRdBursts::13 13049 # Per bank write bursts 110system.physmem.perBankRdBursts::14 12095 # Per bank write bursts 111system.physmem.perBankRdBursts::15 11669 # Per bank write bursts 112system.physmem.perBankWrBursts::0 9112 # Per bank write bursts 113system.physmem.perBankWrBursts::1 9127 # Per bank write bursts 114system.physmem.perBankWrBursts::2 9607 # Per bank write bursts 115system.physmem.perBankWrBursts::3 9172 # Per bank write bursts 116system.physmem.perBankWrBursts::4 8420 # Per bank write bursts 117system.physmem.perBankWrBursts::5 8729 # Per bank write bursts 118system.physmem.perBankWrBursts::6 8984 # Per bank write bursts 119system.physmem.perBankWrBursts::7 8803 # Per bank write bursts 120system.physmem.perBankWrBursts::8 8716 # Per bank write bursts 121system.physmem.perBankWrBursts::9 8606 # Per bank write bursts 122system.physmem.perBankWrBursts::10 8527 # Per bank write bursts 123system.physmem.perBankWrBursts::11 8118 # Per bank write bursts 124system.physmem.perBankWrBursts::12 8733 # Per bank write bursts 125system.physmem.perBankWrBursts::13 9183 # Per bank write bursts 126system.physmem.perBankWrBursts::14 8560 # Per bank write bursts 127system.physmem.perBankWrBursts::15 8024 # Per bank write bursts 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 129system.physmem.numWrRetry 19 # Number of times write queue was full causing retry 130system.physmem.totGap 2825959428000 # Total gap between requests 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 551 # Read request sizes (log2) 134system.physmem.readPktSize::3 28 # Read request sizes (log2) 135system.physmem.readPktSize::4 3087 # Read request sizes (log2) 136system.physmem.readPktSize::5 0 # Read request sizes (log2) 137system.physmem.readPktSize::6 194436 # Read request sizes (log2) 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 4391 # Write request sizes (log2) 141system.physmem.writePktSize::3 0 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) 144system.physmem.writePktSize::6 139949 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 60343 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 72005 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 15875 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 12985 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 8721 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 7504 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 6567 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 5357 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 4768 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 1542 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 975 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 736 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 313 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 259 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 177system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::15 2761 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 3720 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 4251 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 4868 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 5700 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 5982 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 6922 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 7546 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 8592 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 8610 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 10123 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 10779 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 9327 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 9570 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 11050 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 9220 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 8388 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 7975 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 747 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 571 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 421 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 246 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 175 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 197 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 177 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 131 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 142 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 155 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 123 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 136 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 123 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 118 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 120 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 141 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 120 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 122 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 109 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 121 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 60 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 41 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 54 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 92433 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 234.287927 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 132.256290 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 299.423161 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 50967 55.14% 55.14% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 17630 19.07% 74.21% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 5955 6.44% 80.66% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 3343 3.62% 84.27% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 2739 2.96% 87.24% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 1518 1.64% 88.88% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 933 1.01% 89.89% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 1042 1.13% 91.01% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 8306 8.99% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 92433 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 6998 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 28.287082 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 556.369682 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-2047 6996 99.97% 99.97% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 6998 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 6998 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 20.065876 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 18.638507 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 11.720707 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 5824 83.22% 83.22% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 388 5.54% 88.77% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 101 1.44% 90.21% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 68 0.97% 91.18% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 286 4.09% 95.27% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 30 0.43% 95.70% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 22 0.31% 96.01% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 18 0.26% 96.27% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 13 0.19% 96.46% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 6 0.09% 96.54% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 8 0.11% 96.66% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 11 0.16% 96.81% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 167 2.39% 99.20% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 8 0.11% 99.31% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 2 0.03% 99.34% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 5 0.07% 99.41% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 8 0.11% 99.53% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::84-87 4 0.06% 99.59% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::88-91 1 0.01% 99.60% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::92-95 2 0.03% 99.63% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::96-99 4 0.06% 99.69% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::100-103 3 0.04% 99.73% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::108-111 1 0.01% 99.74% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::112-115 1 0.01% 99.76% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::128-131 9 0.13% 99.89% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::132-135 1 0.01% 99.90% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::140-143 2 0.03% 99.93% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::156-159 1 0.01% 99.94% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::160-163 2 0.03% 99.97% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::total 6998 # Writes before turning the bus around for reads 298system.physmem.totQLat 6678126737 # Total ticks spent queuing 299system.physmem.totMemAccLat 10389764237 # Total ticks spent from burst creation until serviced by the DRAM 300system.physmem.totBusLat 989770000 # Total ticks spent in databus transfers 301system.physmem.avgQLat 33735.75 # Average queueing delay per DRAM burst 302system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 303system.physmem.avgMemAccLat 52485.75 # Average memory access latency per DRAM burst 304system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s 305system.physmem.avgWrBW 3.18 # Average achieved write bandwidth in MiByte/s 306system.physmem.avgRdBWSys 4.42 # Average system read bandwidth in MiByte/s 307system.physmem.avgWrBWSys 3.18 # Average system write bandwidth in MiByte/s 308system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 309system.physmem.busUtil 0.06 # Data bus utilization in percentage 310system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 311system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 312system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing 313system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing 314system.physmem.readRowHits 165316 # Number of row buffer hits during reads 315system.physmem.writeRowHits 80625 # Number of row buffer hits during writes 316system.physmem.readRowHitRate 83.51 # Row buffer hit rate for reads 317system.physmem.writeRowHitRate 57.41 # Row buffer hit rate for writes 318system.physmem.avgGap 8252373.91 # Average gap between requests 319system.physmem.pageHitRate 72.68 # Row buffer hit rate, read and write combined 320system.physmem_0.actEnergy 362040840 # Energy for activate commands per rank (pJ) 321system.physmem_0.preEnergy 197542125 # Energy for precharge commands per rank (pJ) 322system.physmem_0.readEnergy 797160000 # Energy for read commands per rank (pJ) 323system.physmem_0.writeEnergy 466261920 # Energy for write commands per rank (pJ) 324system.physmem_0.refreshEnergy 184577783520 # Energy for refresh commands per rank (pJ) 325system.physmem_0.actBackEnergy 79687786095 # Energy for active background per rank (pJ) 326system.physmem_0.preBackEnergy 1625672869500 # Energy for precharge background per rank (pJ) 327system.physmem_0.totalEnergy 1891761444000 # Total energy per rank (pJ) 328system.physmem_0.averagePower 669.423201 # Core power per rank (mW) 329system.physmem_0.memoryStateTime::IDLE 2704357113137 # Time in different power states 330system.physmem_0.memoryStateTime::REF 94364920000 # Time in different power states 331system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 332system.physmem_0.memoryStateTime::ACT 27235374363 # Time in different power states 333system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 334system.physmem_1.actEnergy 336752640 # Energy for activate commands per rank (pJ) 335system.physmem_1.preEnergy 183744000 # Energy for precharge commands per rank (pJ) 336system.physmem_1.readEnergy 746873400 # Energy for read commands per rank (pJ) 337system.physmem_1.writeEnergy 443666160 # Energy for write commands per rank (pJ) 338system.physmem_1.refreshEnergy 184577783520 # Energy for refresh commands per rank (pJ) 339system.physmem_1.actBackEnergy 79354368585 # Energy for active background per rank (pJ) 340system.physmem_1.preBackEnergy 1625965341000 # Energy for precharge background per rank (pJ) 341system.physmem_1.totalEnergy 1891608529305 # Total energy per rank (pJ) 342system.physmem_1.averagePower 669.369090 # Core power per rank (mW) 343system.physmem_1.memoryStateTime::IDLE 2704844457298 # Time in different power states 344system.physmem_1.memoryStateTime::REF 94364920000 # Time in different power states 345system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 346system.physmem_1.memoryStateTime::ACT 26750317702 # Time in different power states 347system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 348system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 349system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory 350system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory 351system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory 352system.realview.nvmem.bytes_inst_read::cpu0.inst 112 # Number of instructions bytes read from this memory 353system.realview.nvmem.bytes_inst_read::cpu1.inst 176 # Number of instructions bytes read from this memory 354system.realview.nvmem.bytes_inst_read::total 288 # Number of instructions bytes read from this memory 355system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory 356system.realview.nvmem.num_reads::cpu1.inst 11 # Number of read requests responded to by this memory 357system.realview.nvmem.num_reads::total 18 # Number of read requests responded to by this memory 358system.realview.nvmem.bw_read::cpu0.inst 40 # Total read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_read::cpu1.inst 62 # Total read bandwidth from this memory (bytes/s) 360system.realview.nvmem.bw_read::total 102 # Total read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_inst_read::cpu0.inst 40 # Instruction read bandwidth from this memory (bytes/s) 362system.realview.nvmem.bw_inst_read::cpu1.inst 62 # Instruction read bandwidth from this memory (bytes/s) 363system.realview.nvmem.bw_inst_read::total 102 # Instruction read bandwidth from this memory (bytes/s) 364system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s) 365system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) 366system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) 367system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 368system.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 369system.bridge.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 370system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 371system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 372system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 373system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 374system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 375system.cf0.dma_write_txs 631 # Number of DMA write transactions. 376system.cpu0.branchPred.lookups 53057105 # Number of BP lookups 377system.cpu0.branchPred.condPredicted 24374304 # Number of conditional branches predicted 378system.cpu0.branchPred.condIncorrect 933540 # Number of conditional branches incorrect 379system.cpu0.branchPred.BTBLookups 32092107 # Number of BTB lookups 380system.cpu0.branchPred.BTBHits 13945777 # Number of BTB hits 381system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 382system.cpu0.branchPred.BTBHitPct 43.455473 # BTB Hit Percentage 383system.cpu0.branchPred.usedRAS 15468620 # Number of times the RAS was used to get a target. 384system.cpu0.branchPred.RASInCorrect 33215 # Number of incorrect RAS predictions. 385system.cpu0.branchPred.indirectLookups 10119517 # Number of indirect predictor lookups. 386system.cpu0.branchPred.indirectHits 9964028 # Number of indirect target hits. 387system.cpu0.branchPred.indirectMisses 155489 # Number of indirect misses. 388system.cpu0.branchPredindirectMispredicted 48572 # Number of mispredicted indirect branches. 389system.cpu_clk_domain.clock 500 # Clock period in ticks 390system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 400system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 401system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 402system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 403system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 404system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 405system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 406system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 407system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 408system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 409system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 410system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 411system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 412system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 413system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 414system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 415system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 416system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 417system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 418system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 419system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 420system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 421system.cpu0.dtb.walker.walks 67255 # Table walker walks requested 422system.cpu0.dtb.walker.walksShort 67255 # Table walker walks initiated with short descriptors 423system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25406 # Level at which table walker walks with short descriptors terminate 424system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18986 # Level at which table walker walks with short descriptors terminate 425system.cpu0.dtb.walker.walksSquashedBefore 22863 # Table walks squashed before starting 426system.cpu0.dtb.walker.walkWaitTime::samples 44392 # Table walker wait (enqueue to first request) latency 427system.cpu0.dtb.walker.walkWaitTime::mean 465.320328 # Table walker wait (enqueue to first request) latency 428system.cpu0.dtb.walker.walkWaitTime::stdev 3000.549463 # Table walker wait (enqueue to first request) latency 429system.cpu0.dtb.walker.walkWaitTime::0-8191 43255 97.44% 97.44% # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::8192-16383 874 1.97% 99.41% # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkWaitTime::16384-24575 114 0.26% 99.66% # Table walker wait (enqueue to first request) latency 432system.cpu0.dtb.walker.walkWaitTime::24576-32767 99 0.22% 99.89% # Table walker wait (enqueue to first request) latency 433system.cpu0.dtb.walker.walkWaitTime::32768-40959 12 0.03% 99.91% # Table walker wait (enqueue to first request) latency 434system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.05% 99.96% # Table walker wait (enqueue to first request) latency 435system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.96% # Table walker wait (enqueue to first request) latency 436system.cpu0.dtb.walker.walkWaitTime::57344-65535 13 0.03% 99.99% # Table walker wait (enqueue to first request) latency 437system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 438system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 439system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 440system.cpu0.dtb.walker.walkWaitTime::total 44392 # Table walker wait (enqueue to first request) latency 441system.cpu0.dtb.walker.walkCompletionTime::samples 17098 # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::mean 11190.109954 # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::gmean 9724.852754 # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::stdev 7829.867535 # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::0-16383 15731 92.00% 92.00% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1253 7.33% 99.33% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::32768-49151 72 0.42% 99.75% # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::49152-65535 7 0.04% 99.80% # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.82% # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.82% # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walkCompletionTime::114688-131071 13 0.08% 99.90% # Table walker service (enqueue to completion) latency 452system.cpu0.dtb.walker.walkCompletionTime::147456-163839 16 0.09% 99.99% # Table walker service (enqueue to completion) latency 453system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 454system.cpu0.dtb.walker.walkCompletionTime::total 17098 # Table walker service (enqueue to completion) latency 455system.cpu0.dtb.walker.walksPending::samples 81474776356 # Table walker pending requests distribution 456system.cpu0.dtb.walker.walksPending::mean 0.525392 # Table walker pending requests distribution 457system.cpu0.dtb.walker.walksPending::stdev 0.513017 # Table walker pending requests distribution 458system.cpu0.dtb.walker.walksPending::0-1 81416314856 99.93% 99.93% # Table walker pending requests distribution 459system.cpu0.dtb.walker.walksPending::2-3 41234500 0.05% 99.98% # Table walker pending requests distribution 460system.cpu0.dtb.walker.walksPending::4-5 7083500 0.01% 99.99% # Table walker pending requests distribution 461system.cpu0.dtb.walker.walksPending::6-7 4738000 0.01% 99.99% # Table walker pending requests distribution 462system.cpu0.dtb.walker.walksPending::8-9 1423000 0.00% 100.00% # Table walker pending requests distribution 463system.cpu0.dtb.walker.walksPending::10-11 1004000 0.00% 100.00% # Table walker pending requests distribution 464system.cpu0.dtb.walker.walksPending::12-13 1185500 0.00% 100.00% # Table walker pending requests distribution 465system.cpu0.dtb.walker.walksPending::14-15 1778000 0.00% 100.00% # Table walker pending requests distribution 466system.cpu0.dtb.walker.walksPending::16-17 15000 0.00% 100.00% # Table walker pending requests distribution 467system.cpu0.dtb.walker.walksPending::total 81474776356 # Table walker pending requests distribution 468system.cpu0.dtb.walker.walkPageSizes::4K 5261 77.38% 77.38% # Table walker page sizes translated 469system.cpu0.dtb.walker.walkPageSizes::1M 1538 22.62% 100.00% # Table walker page sizes translated 470system.cpu0.dtb.walker.walkPageSizes::total 6799 # Table walker page sizes translated 471system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67255 # Table walker requests started/completed, data/inst 472system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 473system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67255 # Table walker requests started/completed, data/inst 474system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6799 # Table walker requests started/completed, data/inst 475system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 476system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6799 # Table walker requests started/completed, data/inst 477system.cpu0.dtb.walker.walkRequestOrigin::total 74054 # Table walker requests started/completed, data/inst 478system.cpu0.dtb.inst_hits 0 # ITB inst hits 479system.cpu0.dtb.inst_misses 0 # ITB inst misses 480system.cpu0.dtb.read_hits 23647306 # DTB read hits 481system.cpu0.dtb.read_misses 56401 # DTB read misses 482system.cpu0.dtb.write_hits 17573284 # DTB write hits 483system.cpu0.dtb.write_misses 10854 # DTB write misses 484system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 485system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 486system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 487system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	12sim_insts 120118276 # Number of instructions simulated 13sim_ops 145712235 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1306176 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1321704 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8517568 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 181104 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 644308 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 521472 # Number of bytes read from this memory 27system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 28system.physmem.bytes_read::total 12495724 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 1306176 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 181104 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 1487280 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 8956736 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 35system.physmem.bytes_written::total 8974300 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 22656 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 21172 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 133087 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.inst 2898 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 10088 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 8148 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 198102 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 139949 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 51system.physmem.num_writes::total 144340 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 611 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.inst 462206 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 467701 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 3014044 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 159 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.inst 64086 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 227996 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 184529 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::total 4421763 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 462206 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 64086 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 526292 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 3169449 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu0.data 6201 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::total 3175665 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 3169449 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 611 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.inst 462206 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 473902 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 3014044 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 159 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.inst 64086 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 228010 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 184529 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::total 7597427 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 198102 # Number of read requests accepted 85system.physmem.writeReqs 144340 # Number of write requests accepted 86system.physmem.readBursts 198102 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 144340 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 12669056 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue 90system.physmem.bytesWritten 8986944 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 12495724 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 8974300 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue 94system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 96system.physmem.perBankRdBursts::0 12421 # Per bank write bursts 97system.physmem.perBankRdBursts::1 12320 # Per bank write bursts 98system.physmem.perBankRdBursts::2 12949 # Per bank write bursts 99system.physmem.perBankRdBursts::3 12687 # Per bank write bursts 100system.physmem.perBankRdBursts::4 14539 # Per bank write bursts 101system.physmem.perBankRdBursts::5 12136 # Per bank write bursts 102system.physmem.perBankRdBursts::6 12666 # Per bank write bursts 103system.physmem.perBankRdBursts::7 12482 # Per bank write bursts 104system.physmem.perBankRdBursts::8 12195 # Per bank write bursts 105system.physmem.perBankRdBursts::9 12078 # Per bank write bursts 106system.physmem.perBankRdBursts::10 11738 # Per bank write bursts 107system.physmem.perBankRdBursts::11 11022 # Per bank write bursts 108system.physmem.perBankRdBursts::12 11908 # Per bank write bursts 109system.physmem.perBankRdBursts::13 13049 # Per bank write bursts 110system.physmem.perBankRdBursts::14 12095 # Per bank write bursts 111system.physmem.perBankRdBursts::15 11669 # Per bank write bursts 112system.physmem.perBankWrBursts::0 9112 # Per bank write bursts 113system.physmem.perBankWrBursts::1 9127 # Per bank write bursts 114system.physmem.perBankWrBursts::2 9607 # Per bank write bursts 115system.physmem.perBankWrBursts::3 9172 # Per bank write bursts 116system.physmem.perBankWrBursts::4 8420 # Per bank write bursts 117system.physmem.perBankWrBursts::5 8729 # Per bank write bursts 118system.physmem.perBankWrBursts::6 8984 # Per bank write bursts 119system.physmem.perBankWrBursts::7 8803 # Per bank write bursts 120system.physmem.perBankWrBursts::8 8716 # Per bank write bursts 121system.physmem.perBankWrBursts::9 8606 # Per bank write bursts 122system.physmem.perBankWrBursts::10 8527 # Per bank write bursts 123system.physmem.perBankWrBursts::11 8118 # Per bank write bursts 124system.physmem.perBankWrBursts::12 8733 # Per bank write bursts 125system.physmem.perBankWrBursts::13 9183 # Per bank write bursts 126system.physmem.perBankWrBursts::14 8560 # Per bank write bursts 127system.physmem.perBankWrBursts::15 8024 # Per bank write bursts 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 129system.physmem.numWrRetry 19 # Number of times write queue was full causing retry 130system.physmem.totGap 2825959428000 # Total gap between requests 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 551 # Read request sizes (log2) 134system.physmem.readPktSize::3 28 # Read request sizes (log2) 135system.physmem.readPktSize::4 3087 # Read request sizes (log2) 136system.physmem.readPktSize::5 0 # Read request sizes (log2) 137system.physmem.readPktSize::6 194436 # Read request sizes (log2) 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 4391 # Write request sizes (log2) 141system.physmem.writePktSize::3 0 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) 144system.physmem.writePktSize::6 139949 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 60343 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 72005 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 15875 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 12985 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 8721 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 7504 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 6567 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 5357 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 4768 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 1542 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 975 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 736 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 313 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 259 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 177system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::15 2761 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 3720 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 4251 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 4868 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 5700 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 5982 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 6922 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 7546 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 8592 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 8610 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 10123 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 10779 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 9327 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 9570 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 11050 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 9220 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 8388 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 7975 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 747 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 571 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 421 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 246 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 175 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 197 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 177 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 131 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 142 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 155 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 123 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 136 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 123 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 118 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 120 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 141 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 120 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 122 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 109 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 121 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 60 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 41 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 54 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 92433 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 234.287927 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 132.256290 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 299.423161 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 50967 55.14% 55.14% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 17630 19.07% 74.21% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 5955 6.44% 80.66% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 3343 3.62% 84.27% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 2739 2.96% 87.24% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 1518 1.64% 88.88% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 933 1.01% 89.89% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 1042 1.13% 91.01% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 8306 8.99% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 92433 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 6998 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 28.287082 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 556.369682 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-2047 6996 99.97% 99.97% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 6998 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 6998 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 20.065876 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 18.638507 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 11.720707 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 5824 83.22% 83.22% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 388 5.54% 88.77% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 101 1.44% 90.21% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 68 0.97% 91.18% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 286 4.09% 95.27% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 30 0.43% 95.70% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 22 0.31% 96.01% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 18 0.26% 96.27% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 13 0.19% 96.46% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 6 0.09% 96.54% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 8 0.11% 96.66% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 11 0.16% 96.81% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 167 2.39% 99.20% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 8 0.11% 99.31% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 2 0.03% 99.34% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 5 0.07% 99.41% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 8 0.11% 99.53% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::84-87 4 0.06% 99.59% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::88-91 1 0.01% 99.60% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::92-95 2 0.03% 99.63% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::96-99 4 0.06% 99.69% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::100-103 3 0.04% 99.73% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::108-111 1 0.01% 99.74% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::112-115 1 0.01% 99.76% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::128-131 9 0.13% 99.89% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::132-135 1 0.01% 99.90% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::140-143 2 0.03% 99.93% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::156-159 1 0.01% 99.94% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::160-163 2 0.03% 99.97% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::total 6998 # Writes before turning the bus around for reads 298system.physmem.totQLat 6678126737 # Total ticks spent queuing 299system.physmem.totMemAccLat 10389764237 # Total ticks spent from burst creation until serviced by the DRAM 300system.physmem.totBusLat 989770000 # Total ticks spent in databus transfers 301system.physmem.avgQLat 33735.75 # Average queueing delay per DRAM burst 302system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 303system.physmem.avgMemAccLat 52485.75 # Average memory access latency per DRAM burst 304system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s 305system.physmem.avgWrBW 3.18 # Average achieved write bandwidth in MiByte/s 306system.physmem.avgRdBWSys 4.42 # Average system read bandwidth in MiByte/s 307system.physmem.avgWrBWSys 3.18 # Average system write bandwidth in MiByte/s 308system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 309system.physmem.busUtil 0.06 # Data bus utilization in percentage 310system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 311system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 312system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing 313system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing 314system.physmem.readRowHits 165316 # Number of row buffer hits during reads 315system.physmem.writeRowHits 80625 # Number of row buffer hits during writes 316system.physmem.readRowHitRate 83.51 # Row buffer hit rate for reads 317system.physmem.writeRowHitRate 57.41 # Row buffer hit rate for writes 318system.physmem.avgGap 8252373.91 # Average gap between requests 319system.physmem.pageHitRate 72.68 # Row buffer hit rate, read and write combined 320system.physmem_0.actEnergy 362040840 # Energy for activate commands per rank (pJ) 321system.physmem_0.preEnergy 197542125 # Energy for precharge commands per rank (pJ) 322system.physmem_0.readEnergy 797160000 # Energy for read commands per rank (pJ) 323system.physmem_0.writeEnergy 466261920 # Energy for write commands per rank (pJ) 324system.physmem_0.refreshEnergy 184577783520 # Energy for refresh commands per rank (pJ) 325system.physmem_0.actBackEnergy 79687786095 # Energy for active background per rank (pJ) 326system.physmem_0.preBackEnergy 1625672869500 # Energy for precharge background per rank (pJ) 327system.physmem_0.totalEnergy 1891761444000 # Total energy per rank (pJ) 328system.physmem_0.averagePower 669.423201 # Core power per rank (mW) 329system.physmem_0.memoryStateTime::IDLE 2704357113137 # Time in different power states 330system.physmem_0.memoryStateTime::REF 94364920000 # Time in different power states 331system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 332system.physmem_0.memoryStateTime::ACT 27235374363 # Time in different power states 333system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 334system.physmem_1.actEnergy 336752640 # Energy for activate commands per rank (pJ) 335system.physmem_1.preEnergy 183744000 # Energy for precharge commands per rank (pJ) 336system.physmem_1.readEnergy 746873400 # Energy for read commands per rank (pJ) 337system.physmem_1.writeEnergy 443666160 # Energy for write commands per rank (pJ) 338system.physmem_1.refreshEnergy 184577783520 # Energy for refresh commands per rank (pJ) 339system.physmem_1.actBackEnergy 79354368585 # Energy for active background per rank (pJ) 340system.physmem_1.preBackEnergy 1625965341000 # Energy for precharge background per rank (pJ) 341system.physmem_1.totalEnergy 1891608529305 # Total energy per rank (pJ) 342system.physmem_1.averagePower 669.369090 # Core power per rank (mW) 343system.physmem_1.memoryStateTime::IDLE 2704844457298 # Time in different power states 344system.physmem_1.memoryStateTime::REF 94364920000 # Time in different power states 345system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 346system.physmem_1.memoryStateTime::ACT 26750317702 # Time in different power states 347system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 348system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 349system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory 350system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory 351system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory 352system.realview.nvmem.bytes_inst_read::cpu0.inst 112 # Number of instructions bytes read from this memory 353system.realview.nvmem.bytes_inst_read::cpu1.inst 176 # Number of instructions bytes read from this memory 354system.realview.nvmem.bytes_inst_read::total 288 # Number of instructions bytes read from this memory 355system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory 356system.realview.nvmem.num_reads::cpu1.inst 11 # Number of read requests responded to by this memory 357system.realview.nvmem.num_reads::total 18 # Number of read requests responded to by this memory 358system.realview.nvmem.bw_read::cpu0.inst 40 # Total read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_read::cpu1.inst 62 # Total read bandwidth from this memory (bytes/s) 360system.realview.nvmem.bw_read::total 102 # Total read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_inst_read::cpu0.inst 40 # Instruction read bandwidth from this memory (bytes/s) 362system.realview.nvmem.bw_inst_read::cpu1.inst 62 # Instruction read bandwidth from this memory (bytes/s) 363system.realview.nvmem.bw_inst_read::total 102 # Instruction read bandwidth from this memory (bytes/s) 364system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s) 365system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) 366system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) 367system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 368system.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 369system.bridge.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 370system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 371system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 372system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 373system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 374system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 375system.cf0.dma_write_txs 631 # Number of DMA write transactions. 376system.cpu0.branchPred.lookups 53057105 # Number of BP lookups 377system.cpu0.branchPred.condPredicted 24374304 # Number of conditional branches predicted 378system.cpu0.branchPred.condIncorrect 933540 # Number of conditional branches incorrect 379system.cpu0.branchPred.BTBLookups 32092107 # Number of BTB lookups 380system.cpu0.branchPred.BTBHits 13945777 # Number of BTB hits 381system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 382system.cpu0.branchPred.BTBHitPct 43.455473 # BTB Hit Percentage 383system.cpu0.branchPred.usedRAS 15468620 # Number of times the RAS was used to get a target. 384system.cpu0.branchPred.RASInCorrect 33215 # Number of incorrect RAS predictions. 385system.cpu0.branchPred.indirectLookups 10119517 # Number of indirect predictor lookups. 386system.cpu0.branchPred.indirectHits 9964028 # Number of indirect target hits. 387system.cpu0.branchPred.indirectMisses 155489 # Number of indirect misses. 388system.cpu0.branchPredindirectMispredicted 48572 # Number of mispredicted indirect branches. 389system.cpu_clk_domain.clock 500 # Clock period in ticks 390system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 400system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 401system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 402system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 403system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 404system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 405system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 406system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 407system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 408system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 409system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 410system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 411system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 412system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 413system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 414system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 415system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 416system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 417system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 418system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 419system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 420system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 421system.cpu0.dtb.walker.walks 67255 # Table walker walks requested 422system.cpu0.dtb.walker.walksShort 67255 # Table walker walks initiated with short descriptors 423system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25406 # Level at which table walker walks with short descriptors terminate 424system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18986 # Level at which table walker walks with short descriptors terminate 425system.cpu0.dtb.walker.walksSquashedBefore 22863 # Table walks squashed before starting 426system.cpu0.dtb.walker.walkWaitTime::samples 44392 # Table walker wait (enqueue to first request) latency 427system.cpu0.dtb.walker.walkWaitTime::mean 465.320328 # Table walker wait (enqueue to first request) latency 428system.cpu0.dtb.walker.walkWaitTime::stdev 3000.549463 # Table walker wait (enqueue to first request) latency 429system.cpu0.dtb.walker.walkWaitTime::0-8191 43255 97.44% 97.44% # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::8192-16383 874 1.97% 99.41% # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkWaitTime::16384-24575 114 0.26% 99.66% # Table walker wait (enqueue to first request) latency 432system.cpu0.dtb.walker.walkWaitTime::24576-32767 99 0.22% 99.89% # Table walker wait (enqueue to first request) latency 433system.cpu0.dtb.walker.walkWaitTime::32768-40959 12 0.03% 99.91% # Table walker wait (enqueue to first request) latency 434system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.05% 99.96% # Table walker wait (enqueue to first request) latency 435system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.96% # Table walker wait (enqueue to first request) latency 436system.cpu0.dtb.walker.walkWaitTime::57344-65535 13 0.03% 99.99% # Table walker wait (enqueue to first request) latency 437system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 438system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 439system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 440system.cpu0.dtb.walker.walkWaitTime::total 44392 # Table walker wait (enqueue to first request) latency 441system.cpu0.dtb.walker.walkCompletionTime::samples 17098 # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::mean 11190.109954 # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::gmean 9724.852754 # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::stdev 7829.867535 # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::0-16383 15731 92.00% 92.00% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1253 7.33% 99.33% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::32768-49151 72 0.42% 99.75% # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::49152-65535 7 0.04% 99.80% # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.82% # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.82% # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walkCompletionTime::114688-131071 13 0.08% 99.90% # Table walker service (enqueue to completion) latency 452system.cpu0.dtb.walker.walkCompletionTime::147456-163839 16 0.09% 99.99% # Table walker service (enqueue to completion) latency 453system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 454system.cpu0.dtb.walker.walkCompletionTime::total 17098 # Table walker service (enqueue to completion) latency 455system.cpu0.dtb.walker.walksPending::samples 81474776356 # Table walker pending requests distribution 456system.cpu0.dtb.walker.walksPending::mean 0.525392 # Table walker pending requests distribution 457system.cpu0.dtb.walker.walksPending::stdev 0.513017 # Table walker pending requests distribution 458system.cpu0.dtb.walker.walksPending::0-1 81416314856 99.93% 99.93% # Table walker pending requests distribution 459system.cpu0.dtb.walker.walksPending::2-3 41234500 0.05% 99.98% # Table walker pending requests distribution 460system.cpu0.dtb.walker.walksPending::4-5 7083500 0.01% 99.99% # Table walker pending requests distribution 461system.cpu0.dtb.walker.walksPending::6-7 4738000 0.01% 99.99% # Table walker pending requests distribution 462system.cpu0.dtb.walker.walksPending::8-9 1423000 0.00% 100.00% # Table walker pending requests distribution 463system.cpu0.dtb.walker.walksPending::10-11 1004000 0.00% 100.00% # Table walker pending requests distribution 464system.cpu0.dtb.walker.walksPending::12-13 1185500 0.00% 100.00% # Table walker pending requests distribution 465system.cpu0.dtb.walker.walksPending::14-15 1778000 0.00% 100.00% # Table walker pending requests distribution 466system.cpu0.dtb.walker.walksPending::16-17 15000 0.00% 100.00% # Table walker pending requests distribution 467system.cpu0.dtb.walker.walksPending::total 81474776356 # Table walker pending requests distribution 468system.cpu0.dtb.walker.walkPageSizes::4K 5261 77.38% 77.38% # Table walker page sizes translated 469system.cpu0.dtb.walker.walkPageSizes::1M 1538 22.62% 100.00% # Table walker page sizes translated 470system.cpu0.dtb.walker.walkPageSizes::total 6799 # Table walker page sizes translated 471system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67255 # Table walker requests started/completed, data/inst 472system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 473system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67255 # Table walker requests started/completed, data/inst 474system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6799 # Table walker requests started/completed, data/inst 475system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 476system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6799 # Table walker requests started/completed, data/inst 477system.cpu0.dtb.walker.walkRequestOrigin::total 74054 # Table walker requests started/completed, data/inst 478system.cpu0.dtb.inst_hits 0 # ITB inst hits 479system.cpu0.dtb.inst_misses 0 # ITB inst misses 480system.cpu0.dtb.read_hits 23647306 # DTB read hits 481system.cpu0.dtb.read_misses 56401 # DTB read misses 482system.cpu0.dtb.write_hits 17573284 # DTB write hits 483system.cpu0.dtb.write_misses 10854 # DTB write misses 484system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 485system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 486system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 487system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
488system.cpu0.dtb.flush_entries 3541 # Number of entries that have been flushed from TLB	488system.cpu0.dtb.flush_entries 3477 # Number of entries that have been flushed from TLB
489system.cpu0.dtb.align_faults 219 # Number of TLB faults due to alignment restrictions 490system.cpu0.dtb.prefetch_faults 2242 # Number of TLB faults due to prefetch 491system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 492system.cpu0.dtb.perms_faults 851 # Number of TLB faults due to permissions restrictions 493system.cpu0.dtb.read_accesses 23703707 # DTB read accesses 494system.cpu0.dtb.write_accesses 17584138 # DTB write accesses 495system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 496system.cpu0.dtb.hits 41220590 # DTB hits 497system.cpu0.dtb.misses 67255 # DTB misses 498system.cpu0.dtb.accesses 41287845 # DTB accesses 499system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 500system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 501system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 502system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 503system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 504system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 505system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 506system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 507system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 508system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 509system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 510system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 511system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 512system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 513system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 514system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 515system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 516system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 517system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 518system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 519system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 520system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 521system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 522system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 523system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 524system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 525system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 526system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 527system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 528system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 529system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 530system.cpu0.itb.walker.walks 10944 # Table walker walks requested 531system.cpu0.itb.walker.walksShort 10944 # Table walker walks initiated with short descriptors 532system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3906 # Level at which table walker walks with short descriptors terminate 533system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5976 # Level at which table walker walks with short descriptors terminate 534system.cpu0.itb.walker.walksSquashedBefore 1062 # Table walks squashed before starting 535system.cpu0.itb.walker.walkWaitTime::samples 9882 # Table walker wait (enqueue to first request) latency 536system.cpu0.itb.walker.walkWaitTime::mean 441.003845 # Table walker wait (enqueue to first request) latency 537system.cpu0.itb.walker.walkWaitTime::stdev 2235.176297 # Table walker wait (enqueue to first request) latency 538system.cpu0.itb.walker.walkWaitTime::0-4095 9496 96.09% 96.09% # Table walker wait (enqueue to first request) latency 539system.cpu0.itb.walker.walkWaitTime::4096-8191 178 1.80% 97.90% # Table walker wait (enqueue to first request) latency 540system.cpu0.itb.walker.walkWaitTime::8192-12287 126 1.28% 99.17% # Table walker wait (enqueue to first request) latency 541system.cpu0.itb.walker.walkWaitTime::12288-16383 44 0.45% 99.62% # Table walker wait (enqueue to first request) latency 542system.cpu0.itb.walker.walkWaitTime::16384-20479 8 0.08% 99.70% # Table walker wait (enqueue to first request) latency 543system.cpu0.itb.walker.walkWaitTime::20480-24575 23 0.23% 99.93% # Table walker wait (enqueue to first request) latency 544system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.97% # Table walker wait (enqueue to first request) latency 545system.cpu0.itb.walker.walkWaitTime::28672-32767 2 0.02% 99.99% # Table walker wait (enqueue to first request) latency 546system.cpu0.itb.walker.walkWaitTime::32768-36863 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 547system.cpu0.itb.walker.walkWaitTime::total 9882 # Table walker wait (enqueue to first request) latency 548system.cpu0.itb.walker.walkCompletionTime::samples 3633 # Table walker service (enqueue to completion) latency 549system.cpu0.itb.walker.walkCompletionTime::mean 11938.893476 # Table walker service (enqueue to completion) latency 550system.cpu0.itb.walker.walkCompletionTime::gmean 11121.754202 # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walkCompletionTime::stdev 4829.169649 # Table walker service (enqueue to completion) latency 552system.cpu0.itb.walker.walkCompletionTime::0-8191 620 17.07% 17.07% # Table walker service (enqueue to completion) latency 553system.cpu0.itb.walker.walkCompletionTime::8192-16383 2792 76.85% 93.92% # Table walker service (enqueue to completion) latency 554system.cpu0.itb.walker.walkCompletionTime::16384-24575 142 3.91% 97.83% # Table walker service (enqueue to completion) latency 555system.cpu0.itb.walker.walkCompletionTime::24576-32767 45 1.24% 99.06% # Table walker service (enqueue to completion) latency 556system.cpu0.itb.walker.walkCompletionTime::32768-40959 33 0.91% 99.97% # Table walker service (enqueue to completion) latency 557system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 558system.cpu0.itb.walker.walkCompletionTime::total 3633 # Table walker service (enqueue to completion) latency 559system.cpu0.itb.walker.walksPending::samples 21344293712 # Table walker pending requests distribution 560system.cpu0.itb.walker.walksPending::mean 0.816978 # Table walker pending requests distribution 561system.cpu0.itb.walker.walksPending::stdev 0.386812 # Table walker pending requests distribution 562system.cpu0.itb.walker.walksPending::0 3907509500 18.31% 18.31% # Table walker pending requests distribution 563system.cpu0.itb.walker.walksPending::1 17435777712 81.69% 100.00% # Table walker pending requests distribution 564system.cpu0.itb.walker.walksPending::2 987000 0.00% 100.00% # Table walker pending requests distribution 565system.cpu0.itb.walker.walksPending::3 19500 0.00% 100.00% # Table walker pending requests distribution 566system.cpu0.itb.walker.walksPending::total 21344293712 # Table walker pending requests distribution 567system.cpu0.itb.walker.walkPageSizes::4K 2239 87.09% 87.09% # Table walker page sizes translated 568system.cpu0.itb.walker.walkPageSizes::1M 332 12.91% 100.00% # Table walker page sizes translated 569system.cpu0.itb.walker.walkPageSizes::total 2571 # Table walker page sizes translated 570system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 571system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10944 # Table walker requests started/completed, data/inst 572system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10944 # Table walker requests started/completed, data/inst 573system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 574system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2571 # Table walker requests started/completed, data/inst 575system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2571 # Table walker requests started/completed, data/inst 576system.cpu0.itb.walker.walkRequestOrigin::total 13515 # Table walker requests started/completed, data/inst 577system.cpu0.itb.inst_hits 72708872 # ITB inst hits 578system.cpu0.itb.inst_misses 10944 # ITB inst misses 579system.cpu0.itb.read_hits 0 # DTB read hits 580system.cpu0.itb.read_misses 0 # DTB read misses 581system.cpu0.itb.write_hits 0 # DTB write hits 582system.cpu0.itb.write_misses 0 # DTB write misses 583system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 584system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 585system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 586system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	489system.cpu0.dtb.align_faults 219 # Number of TLB faults due to alignment restrictions 490system.cpu0.dtb.prefetch_faults 2242 # Number of TLB faults due to prefetch 491system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 492system.cpu0.dtb.perms_faults 851 # Number of TLB faults due to permissions restrictions 493system.cpu0.dtb.read_accesses 23703707 # DTB read accesses 494system.cpu0.dtb.write_accesses 17584138 # DTB write accesses 495system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 496system.cpu0.dtb.hits 41220590 # DTB hits 497system.cpu0.dtb.misses 67255 # DTB misses 498system.cpu0.dtb.accesses 41287845 # DTB accesses 499system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 500system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 501system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 502system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 503system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 504system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 505system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 506system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 507system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 508system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 509system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 510system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 511system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 512system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 513system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 514system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 515system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 516system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 517system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 518system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 519system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 520system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 521system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 522system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 523system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 524system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 525system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 526system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 527system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 528system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 529system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 530system.cpu0.itb.walker.walks 10944 # Table walker walks requested 531system.cpu0.itb.walker.walksShort 10944 # Table walker walks initiated with short descriptors 532system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3906 # Level at which table walker walks with short descriptors terminate 533system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5976 # Level at which table walker walks with short descriptors terminate 534system.cpu0.itb.walker.walksSquashedBefore 1062 # Table walks squashed before starting 535system.cpu0.itb.walker.walkWaitTime::samples 9882 # Table walker wait (enqueue to first request) latency 536system.cpu0.itb.walker.walkWaitTime::mean 441.003845 # Table walker wait (enqueue to first request) latency 537system.cpu0.itb.walker.walkWaitTime::stdev 2235.176297 # Table walker wait (enqueue to first request) latency 538system.cpu0.itb.walker.walkWaitTime::0-4095 9496 96.09% 96.09% # Table walker wait (enqueue to first request) latency 539system.cpu0.itb.walker.walkWaitTime::4096-8191 178 1.80% 97.90% # Table walker wait (enqueue to first request) latency 540system.cpu0.itb.walker.walkWaitTime::8192-12287 126 1.28% 99.17% # Table walker wait (enqueue to first request) latency 541system.cpu0.itb.walker.walkWaitTime::12288-16383 44 0.45% 99.62% # Table walker wait (enqueue to first request) latency 542system.cpu0.itb.walker.walkWaitTime::16384-20479 8 0.08% 99.70% # Table walker wait (enqueue to first request) latency 543system.cpu0.itb.walker.walkWaitTime::20480-24575 23 0.23% 99.93% # Table walker wait (enqueue to first request) latency 544system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.97% # Table walker wait (enqueue to first request) latency 545system.cpu0.itb.walker.walkWaitTime::28672-32767 2 0.02% 99.99% # Table walker wait (enqueue to first request) latency 546system.cpu0.itb.walker.walkWaitTime::32768-36863 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 547system.cpu0.itb.walker.walkWaitTime::total 9882 # Table walker wait (enqueue to first request) latency 548system.cpu0.itb.walker.walkCompletionTime::samples 3633 # Table walker service (enqueue to completion) latency 549system.cpu0.itb.walker.walkCompletionTime::mean 11938.893476 # Table walker service (enqueue to completion) latency 550system.cpu0.itb.walker.walkCompletionTime::gmean 11121.754202 # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walkCompletionTime::stdev 4829.169649 # Table walker service (enqueue to completion) latency 552system.cpu0.itb.walker.walkCompletionTime::0-8191 620 17.07% 17.07% # Table walker service (enqueue to completion) latency 553system.cpu0.itb.walker.walkCompletionTime::8192-16383 2792 76.85% 93.92% # Table walker service (enqueue to completion) latency 554system.cpu0.itb.walker.walkCompletionTime::16384-24575 142 3.91% 97.83% # Table walker service (enqueue to completion) latency 555system.cpu0.itb.walker.walkCompletionTime::24576-32767 45 1.24% 99.06% # Table walker service (enqueue to completion) latency 556system.cpu0.itb.walker.walkCompletionTime::32768-40959 33 0.91% 99.97% # Table walker service (enqueue to completion) latency 557system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 558system.cpu0.itb.walker.walkCompletionTime::total 3633 # Table walker service (enqueue to completion) latency 559system.cpu0.itb.walker.walksPending::samples 21344293712 # Table walker pending requests distribution 560system.cpu0.itb.walker.walksPending::mean 0.816978 # Table walker pending requests distribution 561system.cpu0.itb.walker.walksPending::stdev 0.386812 # Table walker pending requests distribution 562system.cpu0.itb.walker.walksPending::0 3907509500 18.31% 18.31% # Table walker pending requests distribution 563system.cpu0.itb.walker.walksPending::1 17435777712 81.69% 100.00% # Table walker pending requests distribution 564system.cpu0.itb.walker.walksPending::2 987000 0.00% 100.00% # Table walker pending requests distribution 565system.cpu0.itb.walker.walksPending::3 19500 0.00% 100.00% # Table walker pending requests distribution 566system.cpu0.itb.walker.walksPending::total 21344293712 # Table walker pending requests distribution 567system.cpu0.itb.walker.walkPageSizes::4K 2239 87.09% 87.09% # Table walker page sizes translated 568system.cpu0.itb.walker.walkPageSizes::1M 332 12.91% 100.00% # Table walker page sizes translated 569system.cpu0.itb.walker.walkPageSizes::total 2571 # Table walker page sizes translated 570system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 571system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10944 # Table walker requests started/completed, data/inst 572system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10944 # Table walker requests started/completed, data/inst 573system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 574system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2571 # Table walker requests started/completed, data/inst 575system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2571 # Table walker requests started/completed, data/inst 576system.cpu0.itb.walker.walkRequestOrigin::total 13515 # Table walker requests started/completed, data/inst 577system.cpu0.itb.inst_hits 72708872 # ITB inst hits 578system.cpu0.itb.inst_misses 10944 # ITB inst misses 579system.cpu0.itb.read_hits 0 # DTB read hits 580system.cpu0.itb.read_misses 0 # DTB read misses 581system.cpu0.itb.write_hits 0 # DTB write hits 582system.cpu0.itb.write_misses 0 # DTB write misses 583system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 584system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 585system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 586system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
587system.cpu0.itb.flush_entries 2345 # Number of entries that have been flushed from TLB	587system.cpu0.itb.flush_entries 2281 # Number of entries that have been flushed from TLB
588system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 589system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 590system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 591system.cpu0.itb.perms_faults 1928 # Number of TLB faults due to permissions restrictions 592system.cpu0.itb.read_accesses 0 # DTB read accesses 593system.cpu0.itb.write_accesses 0 # DTB write accesses 594system.cpu0.itb.inst_accesses 72719816 # ITB inst accesses 595system.cpu0.itb.hits 72708872 # DTB hits 596system.cpu0.itb.misses 10944 # DTB misses 597system.cpu0.itb.accesses 72719816 # DTB accesses 598system.cpu0.numPwrStateTransitions 3656 # Number of power state transitions 599system.cpu0.pwrStateClkGateDist::samples 1828 # Distribution of time spent in the clock gated state 600system.cpu0.pwrStateClkGateDist::mean 1490596475.785011 # Distribution of time spent in the clock gated state 601system.cpu0.pwrStateClkGateDist::stdev 23949118810.105305 # Distribution of time spent in the clock gated state 602system.cpu0.pwrStateClkGateDist::underflows 1055 57.71% 57.71% # Distribution of time spent in the clock gated state 603system.cpu0.pwrStateClkGateDist::1000-5e+10 768 42.01% 99.73% # Distribution of time spent in the clock gated state 604system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state 605system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state 606system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 607system.cpu0.pwrStateClkGateDist::max_value 499973380096 # Distribution of time spent in the clock gated state 608system.cpu0.pwrStateClkGateDist::total 1828 # Distribution of time spent in the clock gated state 609system.cpu0.pwrStateResidencyTicks::ON 101149373765 # Cumulative time (in ticks) in various power states 610system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724810357735 # Cumulative time (in ticks) in various power states 611system.cpu0.numCycles 202299816 # number of cpu cycles simulated 612system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 613system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 614system.cpu0.fetch.icacheStallCycles 20373611 # Number of cycles fetch is stalled on an Icache miss 615system.cpu0.fetch.Insts 195792180 # Number of instructions fetch has processed 616system.cpu0.fetch.Branches 53057105 # Number of branches that fetch encountered 617system.cpu0.fetch.predictedBranches 39378425 # Number of branches that fetch has predicted taken 618system.cpu0.fetch.Cycles 174483712 # Number of cycles fetch has run and was not squashing or blocked 619system.cpu0.fetch.SquashCycles 5690816 # Number of cycles fetch has spent squashing 620system.cpu0.fetch.TlbCycles 148557 # Number of cycles fetch has spent waiting for tlb 621system.cpu0.fetch.MiscStallCycles 57787 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 622system.cpu0.fetch.PendingTrapStallCycles 411894 # Number of stall cycles due to pending traps 623system.cpu0.fetch.PendingQuiesceStallCycles 415808 # Number of stall cycles due to pending quiesce instructions 624system.cpu0.fetch.IcacheWaitRetryStallCycles 91444 # Number of stall cycles due to full MSHR 625system.cpu0.fetch.CacheLines 72708572 # Number of cache lines fetched 626system.cpu0.fetch.IcacheSquashes 259286 # Number of outstanding Icache misses that were squashed 627system.cpu0.fetch.ItlbSquashes 5400 # Number of outstanding ITLB misses that were squashed 628system.cpu0.fetch.rateDist::samples 198828221 # Number of instructions fetched each cycle (Total) 629system.cpu0.fetch.rateDist::mean 1.203592 # Number of instructions fetched each cycle (Total) 630system.cpu0.fetch.rateDist::stdev 1.307832 # Number of instructions fetched each cycle (Total) 631system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 632system.cpu0.fetch.rateDist::0 93975229 47.26% 47.26% # Number of instructions fetched each cycle (Total) 633system.cpu0.fetch.rateDist::1 30343697 15.26% 62.53% # Number of instructions fetched each cycle (Total) 634system.cpu0.fetch.rateDist::2 14563448 7.32% 69.85% # Number of instructions fetched each cycle (Total) 635system.cpu0.fetch.rateDist::3 59945847 30.15% 100.00% # Number of instructions fetched each cycle (Total) 636system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 637system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 638system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 639system.cpu0.fetch.rateDist::total 198828221 # Number of instructions fetched each cycle (Total) 640system.cpu0.fetch.branchRate 0.262270 # Number of branch fetches per cycle 641system.cpu0.fetch.rate 0.967832 # Number of inst fetches per cycle 642system.cpu0.decode.IdleCycles 25603497 # Number of cycles decode is idle 643system.cpu0.decode.BlockedCycles 106945433 # Number of cycles decode is blocked 644system.cpu0.decode.RunCycles 58799621 # Number of cycles decode is running 645system.cpu0.decode.UnblockCycles 4964058 # Number of cycles decode is unblocking 646system.cpu0.decode.SquashCycles 2515612 # Number of cycles decode is squashing 647system.cpu0.decode.BranchResolved 3059417 # Number of times decode resolved a branch 648system.cpu0.decode.BranchMispred 333874 # Number of times decode detected a branch misprediction 649system.cpu0.decode.DecodedInsts 154225745 # Number of instructions handled by decode 650system.cpu0.decode.SquashedInsts 3810952 # Number of squashed instructions handled by decode 651system.cpu0.rename.SquashCycles 2515612 # Number of cycles rename is squashing 652system.cpu0.rename.IdleCycles 34211381 # Number of cycles rename is idle 653system.cpu0.rename.BlockCycles 12457896 # Number of cycles rename is blocking 654system.cpu0.rename.serializeStallCycles 83569478 # count of cycles rename stalled for serializing inst 655system.cpu0.rename.RunCycles 55018547 # Number of cycles rename is running 656system.cpu0.rename.UnblockCycles 11055307 # Number of cycles rename is unblocking 657system.cpu0.rename.RenamedInsts 137550697 # Number of instructions processed by rename 658system.cpu0.rename.SquashedInsts 1033071 # Number of squashed instructions processed by rename 659system.cpu0.rename.ROBFullEvents 1452205 # Number of times rename has blocked due to ROB full 660system.cpu0.rename.IQFullEvents 164556 # Number of times rename has blocked due to IQ full 661system.cpu0.rename.LQFullEvents 58179 # Number of times rename has blocked due to LQ full 662system.cpu0.rename.SQFullEvents 6849429 # Number of times rename has blocked due to SQ full 663system.cpu0.rename.RenamedOperands 141656181 # Number of destination operands rename has renamed 664system.cpu0.rename.RenameLookups 634589847 # Number of register rename lookups that rename has made 665system.cpu0.rename.int_rename_lookups 152645231 # Number of integer rename lookups 666system.cpu0.rename.fp_rename_lookups 9369 # Number of floating rename lookups 667system.cpu0.rename.CommittedMaps 130468277 # Number of HB maps that are committed 668system.cpu0.rename.UndoneMaps 11187893 # Number of HB maps that are undone due to squashing 669system.cpu0.rename.serializingInsts 2697265 # count of serializing insts renamed 670system.cpu0.rename.tempSerializingInsts 2555549 # count of temporary serializing insts renamed 671system.cpu0.rename.skidInsts 22573870 # count of insts added to the skid buffer 672system.cpu0.memDep0.insertedLoads 24578234 # Number of loads inserted to the mem dependence unit. 673system.cpu0.memDep0.insertedStores 19061004 # Number of stores inserted to the mem dependence unit. 674system.cpu0.memDep0.conflictingLoads 1697434 # Number of conflicting loads. 675system.cpu0.memDep0.conflictingStores 2322680 # Number of conflicting stores. 676system.cpu0.iq.iqInstsAdded 134618116 # Number of instructions added to the IQ (excludes non-spec) 677system.cpu0.iq.iqNonSpecInstsAdded 1713414 # Number of non-speculative instructions added to the IQ 678system.cpu0.iq.iqInstsIssued 132756465 # Number of instructions issued 679system.cpu0.iq.iqSquashedInstsIssued 452944 # Number of squashed instructions issued 680system.cpu0.iq.iqSquashedInstsExamined 10581179 # Number of squashed instructions iterated over during squash; mainly for profiling 681system.cpu0.iq.iqSquashedOperandsExamined 21719888 # Number of squashed operands that are examined and possibly removed from graph 682system.cpu0.iq.iqSquashedNonSpecRemoved 120083 # Number of squashed non-spec instructions that were removed 683system.cpu0.iq.issued_per_cycle::samples 198828221 # Number of insts issued each cycle 684system.cpu0.iq.issued_per_cycle::mean 0.667694 # Number of insts issued each cycle 685system.cpu0.iq.issued_per_cycle::stdev 0.963230 # Number of insts issued each cycle 686system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 687system.cpu0.iq.issued_per_cycle::0 122137220 61.43% 61.43% # Number of insts issued each cycle 688system.cpu0.iq.issued_per_cycle::1 33612355 16.91% 78.33% # Number of insts issued each cycle 689system.cpu0.iq.issued_per_cycle::2 31219254 15.70% 94.04% # Number of insts issued each cycle 690system.cpu0.iq.issued_per_cycle::3 10732023 5.40% 99.43% # Number of insts issued each cycle 691system.cpu0.iq.issued_per_cycle::4 1127312 0.57% 100.00% # Number of insts issued each cycle 692system.cpu0.iq.issued_per_cycle::5 57 0.00% 100.00% # Number of insts issued each cycle 693system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 694system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 695system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 696system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 697system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 698system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 699system.cpu0.iq.issued_per_cycle::total 198828221 # Number of insts issued each cycle 700system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 701system.cpu0.iq.fu_full::IntAlu 10787922 43.88% 43.88% # attempts to use FU when none available 702system.cpu0.iq.fu_full::IntMult 67 0.00% 43.88% # attempts to use FU when none available 703system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.88% # attempts to use FU when none available 704system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.88% # attempts to use FU when none available 705system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.88% # attempts to use FU when none available 706system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.88% # attempts to use FU when none available 707system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.88% # attempts to use FU when none available 708system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.88% # attempts to use FU when none available 709system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.88% # attempts to use FU when none available 710system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.88% # attempts to use FU when none available 711system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.88% # attempts to use FU when none available 712system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.88% # attempts to use FU when none available 713system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.88% # attempts to use FU when none available 714system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.88% # attempts to use FU when none available 715system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.88% # attempts to use FU when none available 716system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.88% # attempts to use FU when none available 717system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.88% # attempts to use FU when none available 718system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.88% # attempts to use FU when none available 719system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.88% # attempts to use FU when none available 720system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.88% # attempts to use FU when none available 721system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.88% # attempts to use FU when none available 722system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.88% # attempts to use FU when none available 723system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.88% # attempts to use FU when none available 724system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.88% # attempts to use FU when none available 725system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.88% # attempts to use FU when none available 726system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.88% # attempts to use FU when none available 727system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.88% # attempts to use FU when none available 728system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.88% # attempts to use FU when none available 729system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.88% # attempts to use FU when none available 730system.cpu0.iq.fu_full::MemRead 5632694 22.91% 66.78% # attempts to use FU when none available 731system.cpu0.iq.fu_full::MemWrite 8166758 33.22% 100.00% # attempts to use FU when none available 732system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 733system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 734system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued 735system.cpu0.iq.FU_type_0::IntAlu 89674441 67.55% 67.55% # Type of FU issued 736system.cpu0.iq.FU_type_0::IntMult 111153 0.08% 67.63% # Type of FU issued 737system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.63% # Type of FU issued 738system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.63% # Type of FU issued 739system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.63% # Type of FU issued 740system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.63% # Type of FU issued 741system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.63% # Type of FU issued 742system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.63% # Type of FU issued 743system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.63% # Type of FU issued 744system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.63% # Type of FU issued 745system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.63% # Type of FU issued 746system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.63% # Type of FU issued 747system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.63% # Type of FU issued 748system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.63% # Type of FU issued 749system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.63% # Type of FU issued 750system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.63% # Type of FU issued 751system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.63% # Type of FU issued 752system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.63% # Type of FU issued 753system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.63% # Type of FU issued 754system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.63% # Type of FU issued 755system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.63% # Type of FU issued 756system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.63% # Type of FU issued 757system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.63% # Type of FU issued 758system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.63% # Type of FU issued 759system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 67.63% # Type of FU issued 760system.cpu0.iq.FU_type_0::SimdFloatMisc 8107 0.01% 67.64% # Type of FU issued 761system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.64% # Type of FU issued 762system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.64% # Type of FU issued 763system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.64% # Type of FU issued 764system.cpu0.iq.FU_type_0::MemRead 24338377 18.33% 85.97% # Type of FU issued 765system.cpu0.iq.FU_type_0::MemWrite 18622113 14.03% 100.00% # Type of FU issued 766system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 767system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 768system.cpu0.iq.FU_type_0::total 132756465 # Type of FU issued 769system.cpu0.iq.rate 0.656236 # Inst issue rate 770system.cpu0.iq.fu_busy_cnt 24587441 # FU busy when requested 771system.cpu0.iq.fu_busy_rate 0.185207 # FU busy rate (busy events/executed inst) 772system.cpu0.iq.int_inst_queue_reads 489349072 # Number of integer instruction queue reads 773system.cpu0.iq.int_inst_queue_writes 146920725 # Number of integer instruction queue writes 774system.cpu0.iq.int_inst_queue_wakeup_accesses 129226985 # Number of integer instruction queue wakeup accesses 775system.cpu0.iq.fp_inst_queue_reads 32463 # Number of floating instruction queue reads 776system.cpu0.iq.fp_inst_queue_writes 11252 # Number of floating instruction queue writes 777system.cpu0.iq.fp_inst_queue_wakeup_accesses 9717 # Number of floating instruction queue wakeup accesses 778system.cpu0.iq.int_alu_accesses 157320500 # Number of integer alu accesses 779system.cpu0.iq.fp_alu_accesses 21133 # Number of floating point alu accesses 780system.cpu0.iew.lsq.thread0.forwLoads 365431 # Number of loads that had data forwarded from stores 781system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 782system.cpu0.iew.lsq.thread0.squashedLoads 1915604 # Number of loads squashed 783system.cpu0.iew.lsq.thread0.ignoredResponses 2466 # Number of memory responses ignored because the instruction is squashed 784system.cpu0.iew.lsq.thread0.memOrderViolation 19339 # Number of memory ordering violations 785system.cpu0.iew.lsq.thread0.squashedStores 897405 # Number of stores squashed 786system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 787system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 788system.cpu0.iew.lsq.thread0.rescheduledLoads 120966 # Number of loads that were rescheduled 789system.cpu0.iew.lsq.thread0.cacheBlocked 361642 # Number of times an access to memory failed due to the cache being blocked 790system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 791system.cpu0.iew.iewSquashCycles 2515612 # Number of cycles IEW is squashing 792system.cpu0.iew.iewBlockCycles 1602789 # Number of cycles IEW is blocking 793system.cpu0.iew.iewUnblockCycles 184527 # Number of cycles IEW is unblocking 794system.cpu0.iew.iewDispatchedInsts 136483987 # Number of instructions dispatched to IQ 795system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 796system.cpu0.iew.iewDispLoadInsts 24578234 # Number of dispatched load instructions 797system.cpu0.iew.iewDispStoreInsts 19061004 # Number of dispatched store instructions 798system.cpu0.iew.iewDispNonSpecInsts 875924 # Number of dispatched non-speculative instructions 799system.cpu0.iew.iewIQFullEvents 28511 # Number of times the IQ has become full, causing a stall 800system.cpu0.iew.iewLSQFullEvents 132116 # Number of times the LSQ has become full, causing a stall 801system.cpu0.iew.memOrderViolationEvents 19339 # Number of memory order violations 802system.cpu0.iew.predictedTakenIncorrect 261906 # Number of branches that were predicted taken incorrectly 803system.cpu0.iew.predictedNotTakenIncorrect 398193 # Number of branches that were predicted not taken incorrectly 804system.cpu0.iew.branchMispredicts 660099 # Number of branch mispredicts detected at execute 805system.cpu0.iew.iewExecutedInsts 131724041 # Number of executed instructions 806system.cpu0.iew.iewExecLoadInsts 23895876 # Number of load instructions executed 807system.cpu0.iew.iewExecSquashedInsts 965291 # Number of squashed instructions skipped in execute 808system.cpu0.iew.exec_swp 0 # number of swp insts executed 809system.cpu0.iew.exec_nop 152457 # number of nop insts executed 810system.cpu0.iew.exec_refs 42356949 # number of memory reference insts executed 811system.cpu0.iew.exec_branches 25556056 # Number of branches executed 812system.cpu0.iew.exec_stores 18461073 # Number of stores executed 813system.cpu0.iew.exec_rate 0.651133 # Inst execution rate 814system.cpu0.iew.wb_sent 131168007 # cumulative count of insts sent to commit 815system.cpu0.iew.wb_count 129236702 # cumulative count of insts written-back 816system.cpu0.iew.wb_producers 65950850 # num instructions producing a value 817system.cpu0.iew.wb_consumers 106665798 # num instructions consuming a value 818system.cpu0.iew.wb_rate 0.638837 # insts written-back per cycle 819system.cpu0.iew.wb_fanout 0.618294 # average fanout of values written-back 820system.cpu0.commit.commitSquashedInsts 9550008 # The number of squashed insts skipped by commit 821system.cpu0.commit.commitNonSpecStalls 1593331 # The number of times commit has been forced to stall to communicate backwards 822system.cpu0.commit.branchMispredicts 603744 # The number of times a branch was mispredicted 823system.cpu0.commit.committed_per_cycle::samples 195669003 # Number of insts commited each cycle 824system.cpu0.commit.committed_per_cycle::mean 0.643292 # Number of insts commited each cycle 825system.cpu0.commit.committed_per_cycle::stdev 1.341136 # Number of insts commited each cycle 826system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 827system.cpu0.commit.committed_per_cycle::0 135299612 69.15% 69.15% # Number of insts commited each cycle 828system.cpu0.commit.committed_per_cycle::1 33411311 17.08% 86.22% # Number of insts commited each cycle 829system.cpu0.commit.committed_per_cycle::2 12639941 6.46% 92.68% # Number of insts commited each cycle 830system.cpu0.commit.committed_per_cycle::3 3246105 1.66% 94.34% # Number of insts commited each cycle 831system.cpu0.commit.committed_per_cycle::4 4896411 2.50% 96.84% # Number of insts commited each cycle 832system.cpu0.commit.committed_per_cycle::5 2789558 1.43% 98.27% # Number of insts commited each cycle 833system.cpu0.commit.committed_per_cycle::6 1311154 0.67% 98.94% # Number of insts commited each cycle 834system.cpu0.commit.committed_per_cycle::7 556760 0.28% 99.22% # Number of insts commited each cycle 835system.cpu0.commit.committed_per_cycle::8 1518151 0.78% 100.00% # Number of insts commited each cycle 836system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 837system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 838system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 839system.cpu0.commit.committed_per_cycle::total 195669003 # Number of insts commited each cycle 840system.cpu0.commit.committedInsts 103938440 # Number of instructions committed 841system.cpu0.commit.committedOps 125872394 # Number of ops (including micro ops) committed 842system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 843system.cpu0.commit.refs 40826228 # Number of memory references committed 844system.cpu0.commit.loads 22662629 # Number of loads committed 845system.cpu0.commit.membars 647252 # Number of memory barriers committed 846system.cpu0.commit.branches 24954847 # Number of branches committed 847system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. 848system.cpu0.commit.int_insts 109891295 # Number of committed integer instructions. 849system.cpu0.commit.function_calls 4835454 # Number of function calls committed. 850system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 851system.cpu0.commit.op_class_0::IntAlu 84929206 67.47% 67.47% # Class of committed instruction 852system.cpu0.commit.op_class_0::IntMult 108853 0.09% 67.56% # Class of committed instruction 853system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.56% # Class of committed instruction 854system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.56% # Class of committed instruction 855system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.56% # Class of committed instruction 856system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.56% # Class of committed instruction 857system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.56% # Class of committed instruction 858system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.56% # Class of committed instruction 859system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.56% # Class of committed instruction 860system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.56% # Class of committed instruction 861system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.56% # Class of committed instruction 862system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.56% # Class of committed instruction 863system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.56% # Class of committed instruction 864system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.56% # Class of committed instruction 865system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.56% # Class of committed instruction 866system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.56% # Class of committed instruction 867system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.56% # Class of committed instruction 868system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.56% # Class of committed instruction 869system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.56% # Class of committed instruction 870system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.56% # Class of committed instruction 871system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.56% # Class of committed instruction 872system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.56% # Class of committed instruction 873system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.56% # Class of committed instruction 874system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.56% # Class of committed instruction 875system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.56% # Class of committed instruction 876system.cpu0.commit.op_class_0::SimdFloatMisc 8107 0.01% 67.57% # Class of committed instruction 877system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.57% # Class of committed instruction 878system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.57% # Class of committed instruction 879system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.57% # Class of committed instruction 880system.cpu0.commit.op_class_0::MemRead 22662629 18.00% 85.57% # Class of committed instruction 881system.cpu0.commit.op_class_0::MemWrite 18163599 14.43% 100.00% # Class of committed instruction 882system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 883system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 884system.cpu0.commit.op_class_0::total 125872394 # Class of committed instruction 885system.cpu0.commit.bw_lim_events 1518151 # number cycles where commit BW limit reached 886system.cpu0.rob.rob_reads 306287204 # The number of ROB reads 887system.cpu0.rob.rob_writes 273994781 # The number of ROB writes 888system.cpu0.timesIdled 123974 # Number of times that the entire CPU went into an idle state and unscheduled itself 889system.cpu0.idleCycles 3471595 # Total number of cycles that the CPU has spent unscheduled due to idling 890system.cpu0.quiesceCycles 5449619957 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 891system.cpu0.committedInsts 103816388 # Number of Instructions Simulated 892system.cpu0.committedOps 125750342 # Number of Ops (including micro ops) Simulated 893system.cpu0.cpi 1.948631 # CPI: Cycles Per Instruction 894system.cpu0.cpi_total 1.948631 # CPI: Total CPI of All Threads 895system.cpu0.ipc 0.513181 # IPC: Instructions Per Cycle 896system.cpu0.ipc_total 0.513181 # IPC: Total IPC of All Threads 897system.cpu0.int_regfile_reads 142719808 # number of integer regfile reads 898system.cpu0.int_regfile_writes 81679098 # number of integer regfile writes 899system.cpu0.fp_regfile_reads 8185 # number of floating regfile reads 900system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes 901system.cpu0.cc_regfile_reads 464897652 # number of cc regfile reads 902system.cpu0.cc_regfile_writes 49725456 # number of cc regfile writes 903system.cpu0.misc_regfile_reads 388373326 # number of misc regfile reads 904system.cpu0.misc_regfile_writes 1224889 # number of misc regfile writes 905system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 906system.cpu0.dcache.tags.replacements 709828 # number of replacements 907system.cpu0.dcache.tags.tagsinuse 497.174198 # Cycle average of tags in use 908system.cpu0.dcache.tags.total_refs 37665141 # Total number of references to valid blocks. 909system.cpu0.dcache.tags.sampled_refs 710340 # Sample count of references to valid blocks. 910system.cpu0.dcache.tags.avg_refs 53.024103 # Average number of references to valid blocks. 911system.cpu0.dcache.tags.warmup_cycle 278078500 # Cycle when the warmup percentage was hit. 912system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.174198 # Average occupied blocks per requestor 913system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971043 # Average percentage of cache occupancy 914system.cpu0.dcache.tags.occ_percent::total 0.971043 # Average percentage of cache occupancy 915system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 916system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id 917system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id 918system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id 919system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 920system.cpu0.dcache.tags.tag_accesses 81170296 # Number of tag accesses 921system.cpu0.dcache.tags.data_accesses 81170296 # Number of data accesses 922system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 923system.cpu0.dcache.ReadReq_hits::cpu0.data 21454849 # number of ReadReq hits 924system.cpu0.dcache.ReadReq_hits::total 21454849 # number of ReadReq hits 925system.cpu0.dcache.WriteReq_hits::cpu0.data 14988122 # number of WriteReq hits 926system.cpu0.dcache.WriteReq_hits::total 14988122 # number of WriteReq hits 927system.cpu0.dcache.SoftPFReq_hits::cpu0.data 308527 # number of SoftPFReq hits 928system.cpu0.dcache.SoftPFReq_hits::total 308527 # number of SoftPFReq hits 929system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363066 # number of LoadLockedReq hits 930system.cpu0.dcache.LoadLockedReq_hits::total 363066 # number of LoadLockedReq hits 931system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361109 # number of StoreCondReq hits 932system.cpu0.dcache.StoreCondReq_hits::total 361109 # number of StoreCondReq hits 933system.cpu0.dcache.demand_hits::cpu0.data 36442971 # number of demand (read+write) hits 934system.cpu0.dcache.demand_hits::total 36442971 # number of demand (read+write) hits 935system.cpu0.dcache.overall_hits::cpu0.data 36751498 # number of overall hits 936system.cpu0.dcache.overall_hits::total 36751498 # number of overall hits 937system.cpu0.dcache.ReadReq_misses::cpu0.data 646522 # number of ReadReq misses 938system.cpu0.dcache.ReadReq_misses::total 646522 # number of ReadReq misses 939system.cpu0.dcache.WriteReq_misses::cpu0.data 1887777 # number of WriteReq misses 940system.cpu0.dcache.WriteReq_misses::total 1887777 # number of WriteReq misses 941system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147802 # number of SoftPFReq misses 942system.cpu0.dcache.SoftPFReq_misses::total 147802 # number of SoftPFReq misses 943system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25065 # number of LoadLockedReq misses 944system.cpu0.dcache.LoadLockedReq_misses::total 25065 # number of LoadLockedReq misses 945system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20108 # number of StoreCondReq misses 946system.cpu0.dcache.StoreCondReq_misses::total 20108 # number of StoreCondReq misses 947system.cpu0.dcache.demand_misses::cpu0.data 2534299 # number of demand (read+write) misses 948system.cpu0.dcache.demand_misses::total 2534299 # number of demand (read+write) misses 949system.cpu0.dcache.overall_misses::cpu0.data 2682101 # number of overall misses 950system.cpu0.dcache.overall_misses::total 2682101 # number of overall misses 951system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8646662000 # number of ReadReq miss cycles 952system.cpu0.dcache.ReadReq_miss_latency::total 8646662000 # number of ReadReq miss cycles 953system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29876871349 # number of WriteReq miss cycles 954system.cpu0.dcache.WriteReq_miss_latency::total 29876871349 # number of WriteReq miss cycles 955system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 399690500 # number of LoadLockedReq miss cycles 956system.cpu0.dcache.LoadLockedReq_miss_latency::total 399690500 # number of LoadLockedReq miss cycles 957system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 484891000 # number of StoreCondReq miss cycles 958system.cpu0.dcache.StoreCondReq_miss_latency::total 484891000 # number of StoreCondReq miss cycles 959system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 240000 # number of StoreCondFailReq miss cycles 960system.cpu0.dcache.StoreCondFailReq_miss_latency::total 240000 # number of StoreCondFailReq miss cycles 961system.cpu0.dcache.demand_miss_latency::cpu0.data 38523533349 # number of demand (read+write) miss cycles 962system.cpu0.dcache.demand_miss_latency::total 38523533349 # number of demand (read+write) miss cycles 963system.cpu0.dcache.overall_miss_latency::cpu0.data 38523533349 # number of overall miss cycles 964system.cpu0.dcache.overall_miss_latency::total 38523533349 # number of overall miss cycles 965system.cpu0.dcache.ReadReq_accesses::cpu0.data 22101371 # number of ReadReq accesses(hits+misses) 966system.cpu0.dcache.ReadReq_accesses::total 22101371 # number of ReadReq accesses(hits+misses) 967system.cpu0.dcache.WriteReq_accesses::cpu0.data 16875899 # number of WriteReq accesses(hits+misses) 968system.cpu0.dcache.WriteReq_accesses::total 16875899 # number of WriteReq accesses(hits+misses) 969system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456329 # number of SoftPFReq accesses(hits+misses) 970system.cpu0.dcache.SoftPFReq_accesses::total 456329 # number of SoftPFReq accesses(hits+misses) 971system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388131 # number of LoadLockedReq accesses(hits+misses) 972system.cpu0.dcache.LoadLockedReq_accesses::total 388131 # number of LoadLockedReq accesses(hits+misses) 973system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381217 # number of StoreCondReq accesses(hits+misses) 974system.cpu0.dcache.StoreCondReq_accesses::total 381217 # number of StoreCondReq accesses(hits+misses) 975system.cpu0.dcache.demand_accesses::cpu0.data 38977270 # number of demand (read+write) accesses 976system.cpu0.dcache.demand_accesses::total 38977270 # number of demand (read+write) accesses 977system.cpu0.dcache.overall_accesses::cpu0.data 39433599 # number of overall (read+write) accesses 978system.cpu0.dcache.overall_accesses::total 39433599 # number of overall (read+write) accesses 979system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029253 # miss rate for ReadReq accesses 980system.cpu0.dcache.ReadReq_miss_rate::total 0.029253 # miss rate for ReadReq accesses 981system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.111862 # miss rate for WriteReq accesses 982system.cpu0.dcache.WriteReq_miss_rate::total 0.111862 # miss rate for WriteReq accesses 983system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323894 # miss rate for SoftPFReq accesses 984system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323894 # miss rate for SoftPFReq accesses 985system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064579 # miss rate for LoadLockedReq accesses 986system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064579 # miss rate for LoadLockedReq accesses 987system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052747 # miss rate for StoreCondReq accesses 988system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052747 # miss rate for StoreCondReq accesses 989system.cpu0.dcache.demand_miss_rate::cpu0.data 0.065020 # miss rate for demand accesses 990system.cpu0.dcache.demand_miss_rate::total 0.065020 # miss rate for demand accesses 991system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068016 # miss rate for overall accesses 992system.cpu0.dcache.overall_miss_rate::total 0.068016 # miss rate for overall accesses 993system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13374.118746 # average ReadReq miss latency 994system.cpu0.dcache.ReadReq_avg_miss_latency::total 13374.118746 # average ReadReq miss latency 995system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15826.483398 # average WriteReq miss latency 996system.cpu0.dcache.WriteReq_avg_miss_latency::total 15826.483398 # average WriteReq miss latency 997system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15946.159984 # average LoadLockedReq miss latency 998system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15946.159984 # average LoadLockedReq miss latency 999system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24114.332604 # average StoreCondReq miss latency 1000system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24114.332604 # average StoreCondReq miss latency 1001system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1002system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1003system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15200.863572 # average overall miss latency 1004system.cpu0.dcache.demand_avg_miss_latency::total 15200.863572 # average overall miss latency 1005system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14363.192642 # average overall miss latency 1006system.cpu0.dcache.overall_avg_miss_latency::total 14363.192642 # average overall miss latency 1007system.cpu0.dcache.blocked_cycles::no_mshrs 1028 # number of cycles access was blocked 1008system.cpu0.dcache.blocked_cycles::no_targets 4276317 # number of cycles access was blocked 1009system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked 1010system.cpu0.dcache.blocked::no_targets 201917 # number of cycles access was blocked 1011system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.416667 # average number of cycles each access was blocked 1012system.cpu0.dcache.avg_blocked_cycles::no_targets 21.178588 # average number of cycles each access was blocked 1013system.cpu0.dcache.writebacks::writebacks 709828 # number of writebacks 1014system.cpu0.dcache.writebacks::total 709828 # number of writebacks 1015system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 259036 # number of ReadReq MSHR hits 1016system.cpu0.dcache.ReadReq_mshr_hits::total 259036 # number of ReadReq MSHR hits 1017system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1563852 # number of WriteReq MSHR hits 1018system.cpu0.dcache.WriteReq_mshr_hits::total 1563852 # number of WriteReq MSHR hits 1019system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18553 # number of LoadLockedReq MSHR hits 1020system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18553 # number of LoadLockedReq MSHR hits 1021system.cpu0.dcache.demand_mshr_hits::cpu0.data 1822888 # number of demand (read+write) MSHR hits 1022system.cpu0.dcache.demand_mshr_hits::total 1822888 # number of demand (read+write) MSHR hits 1023system.cpu0.dcache.overall_mshr_hits::cpu0.data 1822888 # number of overall MSHR hits 1024system.cpu0.dcache.overall_mshr_hits::total 1822888 # number of overall MSHR hits 1025system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 387486 # number of ReadReq MSHR misses 1026system.cpu0.dcache.ReadReq_mshr_misses::total 387486 # number of ReadReq MSHR misses 1027system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323925 # number of WriteReq MSHR misses 1028system.cpu0.dcache.WriteReq_mshr_misses::total 323925 # number of WriteReq MSHR misses 1029system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101400 # number of SoftPFReq MSHR misses 1030system.cpu0.dcache.SoftPFReq_mshr_misses::total 101400 # number of SoftPFReq MSHR misses 1031system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6512 # number of LoadLockedReq MSHR misses 1032system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6512 # number of LoadLockedReq MSHR misses 1033system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20108 # number of StoreCondReq MSHR misses 1034system.cpu0.dcache.StoreCondReq_mshr_misses::total 20108 # number of StoreCondReq MSHR misses 1035system.cpu0.dcache.demand_mshr_misses::cpu0.data 711411 # number of demand (read+write) MSHR misses 1036system.cpu0.dcache.demand_mshr_misses::total 711411 # number of demand (read+write) MSHR misses 1037system.cpu0.dcache.overall_mshr_misses::cpu0.data 812811 # number of overall MSHR misses 1038system.cpu0.dcache.overall_mshr_misses::total 812811 # number of overall MSHR misses 1039system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31771 # number of ReadReq MSHR uncacheable 1040system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31771 # number of ReadReq MSHR uncacheable 1041system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28450 # number of WriteReq MSHR uncacheable 1042system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28450 # number of WriteReq MSHR uncacheable 1043system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60221 # number of overall MSHR uncacheable misses 1044system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60221 # number of overall MSHR uncacheable misses 1045system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4570691500 # number of ReadReq MSHR miss cycles 1046system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4570691500 # number of ReadReq MSHR miss cycles 1047system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6113916381 # number of WriteReq MSHR miss cycles 1048system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6113916381 # number of WriteReq MSHR miss cycles 1049system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1664414000 # number of SoftPFReq MSHR miss cycles 1050system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1664414000 # number of SoftPFReq MSHR miss cycles 1051system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102380000 # number of LoadLockedReq MSHR miss cycles 1052system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102380000 # number of LoadLockedReq MSHR miss cycles 1053system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 464790000 # number of StoreCondReq MSHR miss cycles 1054system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 464790000 # number of StoreCondReq MSHR miss cycles 1055system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 233000 # number of StoreCondFailReq MSHR miss cycles 1056system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 233000 # number of StoreCondFailReq MSHR miss cycles 1057system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10684607881 # number of demand (read+write) MSHR miss cycles 1058system.cpu0.dcache.demand_mshr_miss_latency::total 10684607881 # number of demand (read+write) MSHR miss cycles 1059system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12349021881 # number of overall MSHR miss cycles 1060system.cpu0.dcache.overall_mshr_miss_latency::total 12349021881 # number of overall MSHR miss cycles 1061system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6621026500 # number of ReadReq MSHR uncacheable cycles 1062system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6621026500 # number of ReadReq MSHR uncacheable cycles 1063system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6621026500 # number of overall MSHR uncacheable cycles 1064system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6621026500 # number of overall MSHR uncacheable cycles 1065system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017532 # mshr miss rate for ReadReq accesses 1066system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017532 # mshr miss rate for ReadReq accesses 1067system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019195 # mshr miss rate for WriteReq accesses 1068system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019195 # mshr miss rate for WriteReq accesses 1069system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222208 # mshr miss rate for SoftPFReq accesses 1070system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222208 # mshr miss rate for SoftPFReq accesses 1071system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016778 # mshr miss rate for LoadLockedReq accesses 1072system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016778 # mshr miss rate for LoadLockedReq accesses 1073system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052747 # mshr miss rate for StoreCondReq accesses 1074system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052747 # mshr miss rate for StoreCondReq accesses 1075system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018252 # mshr miss rate for demand accesses 1076system.cpu0.dcache.demand_mshr_miss_rate::total 0.018252 # mshr miss rate for demand accesses 1077system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020612 # mshr miss rate for overall accesses 1078system.cpu0.dcache.overall_mshr_miss_rate::total 0.020612 # mshr miss rate for overall accesses 1079system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11795.759073 # average ReadReq mshr miss latency 1080system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11795.759073 # average ReadReq mshr miss latency 1081system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18874.481380 # average WriteReq mshr miss latency 1082system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18874.481380 # average WriteReq mshr miss latency 1083system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16414.339250 # average SoftPFReq mshr miss latency 1084system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16414.339250 # average SoftPFReq mshr miss latency 1085system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15721.744472 # average LoadLockedReq mshr miss latency 1086system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15721.744472 # average LoadLockedReq mshr miss latency 1087system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23114.680724 # average StoreCondReq mshr miss latency 1088system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23114.680724 # average StoreCondReq mshr miss latency 1089system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1090system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1091system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15018.896083 # average overall mshr miss latency 1092system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15018.896083 # average overall mshr miss latency 1093system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15192.980756 # average overall mshr miss latency 1094system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15192.980756 # average overall mshr miss latency 1095system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208398.429385 # average ReadReq mshr uncacheable latency 1096system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208398.429385 # average ReadReq mshr uncacheable latency 1097system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109945.475831 # average overall mshr uncacheable latency 1098system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109945.475831 # average overall mshr uncacheable latency 1099system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 1100system.cpu0.icache.tags.replacements 1253795 # number of replacements 1101system.cpu0.icache.tags.tagsinuse 511.762128 # Cycle average of tags in use 1102system.cpu0.icache.tags.total_refs 71396857 # Total number of references to valid blocks. 1103system.cpu0.icache.tags.sampled_refs 1254307 # Sample count of references to valid blocks. 1104system.cpu0.icache.tags.avg_refs 56.921357 # Average number of references to valid blocks. 1105system.cpu0.icache.tags.warmup_cycle 7880422000 # Cycle when the warmup percentage was hit. 1106system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762128 # Average occupied blocks per requestor 1107system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999535 # Average percentage of cache occupancy 1108system.cpu0.icache.tags.occ_percent::total 0.999535 # Average percentage of cache occupancy 1109system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1110system.cpu0.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id 1111system.cpu0.icache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id 1112system.cpu0.icache.tags.age_task_id_blocks_1024::2 122 # Occupied blocks per task id 1113system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1114system.cpu0.icache.tags.tag_accesses 146664376 # Number of tag accesses 1115system.cpu0.icache.tags.data_accesses 146664376 # Number of data accesses 1116system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 1117system.cpu0.icache.ReadReq_hits::cpu0.inst 71396857 # number of ReadReq hits 1118system.cpu0.icache.ReadReq_hits::total 71396857 # number of ReadReq hits 1119system.cpu0.icache.demand_hits::cpu0.inst 71396857 # number of demand (read+write) hits 1120system.cpu0.icache.demand_hits::total 71396857 # number of demand (read+write) hits 1121system.cpu0.icache.overall_hits::cpu0.inst 71396857 # number of overall hits 1122system.cpu0.icache.overall_hits::total 71396857 # number of overall hits 1123system.cpu0.icache.ReadReq_misses::cpu0.inst 1308156 # number of ReadReq misses 1124system.cpu0.icache.ReadReq_misses::total 1308156 # number of ReadReq misses 1125system.cpu0.icache.demand_misses::cpu0.inst 1308156 # number of demand (read+write) misses 1126system.cpu0.icache.demand_misses::total 1308156 # number of demand (read+write) misses 1127system.cpu0.icache.overall_misses::cpu0.inst 1308156 # number of overall misses 1128system.cpu0.icache.overall_misses::total 1308156 # number of overall misses 1129system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13216802476 # number of ReadReq miss cycles 1130system.cpu0.icache.ReadReq_miss_latency::total 13216802476 # number of ReadReq miss cycles 1131system.cpu0.icache.demand_miss_latency::cpu0.inst 13216802476 # number of demand (read+write) miss cycles 1132system.cpu0.icache.demand_miss_latency::total 13216802476 # number of demand (read+write) miss cycles 1133system.cpu0.icache.overall_miss_latency::cpu0.inst 13216802476 # number of overall miss cycles 1134system.cpu0.icache.overall_miss_latency::total 13216802476 # number of overall miss cycles 1135system.cpu0.icache.ReadReq_accesses::cpu0.inst 72705013 # number of ReadReq accesses(hits+misses) 1136system.cpu0.icache.ReadReq_accesses::total 72705013 # number of ReadReq accesses(hits+misses) 1137system.cpu0.icache.demand_accesses::cpu0.inst 72705013 # number of demand (read+write) accesses 1138system.cpu0.icache.demand_accesses::total 72705013 # number of demand (read+write) accesses 1139system.cpu0.icache.overall_accesses::cpu0.inst 72705013 # number of overall (read+write) accesses 1140system.cpu0.icache.overall_accesses::total 72705013 # number of overall (read+write) accesses 1141system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017993 # miss rate for ReadReq accesses 1142system.cpu0.icache.ReadReq_miss_rate::total 0.017993 # miss rate for ReadReq accesses 1143system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017993 # miss rate for demand accesses 1144system.cpu0.icache.demand_miss_rate::total 0.017993 # miss rate for demand accesses 1145system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017993 # miss rate for overall accesses 1146system.cpu0.icache.overall_miss_rate::total 0.017993 # miss rate for overall accesses 1147system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10103.384058 # average ReadReq miss latency 1148system.cpu0.icache.ReadReq_avg_miss_latency::total 10103.384058 # average ReadReq miss latency 1149system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10103.384058 # average overall miss latency 1150system.cpu0.icache.demand_avg_miss_latency::total 10103.384058 # average overall miss latency 1151system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10103.384058 # average overall miss latency 1152system.cpu0.icache.overall_avg_miss_latency::total 10103.384058 # average overall miss latency 1153system.cpu0.icache.blocked_cycles::no_mshrs 1586454 # number of cycles access was blocked 1154system.cpu0.icache.blocked_cycles::no_targets 443 # number of cycles access was blocked 1155system.cpu0.icache.blocked::no_mshrs 112621 # number of cycles access was blocked 1156system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked 1157system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.086662 # average number of cycles each access was blocked 1158system.cpu0.icache.avg_blocked_cycles::no_targets 44.300000 # average number of cycles each access was blocked 1159system.cpu0.icache.writebacks::writebacks 1253795 # number of writebacks 1160system.cpu0.icache.writebacks::total 1253795 # number of writebacks 1161system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53805 # number of ReadReq MSHR hits 1162system.cpu0.icache.ReadReq_mshr_hits::total 53805 # number of ReadReq MSHR hits 1163system.cpu0.icache.demand_mshr_hits::cpu0.inst 53805 # number of demand (read+write) MSHR hits 1164system.cpu0.icache.demand_mshr_hits::total 53805 # number of demand (read+write) MSHR hits 1165system.cpu0.icache.overall_mshr_hits::cpu0.inst 53805 # number of overall MSHR hits 1166system.cpu0.icache.overall_mshr_hits::total 53805 # number of overall MSHR hits 1167system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1254351 # number of ReadReq MSHR misses 1168system.cpu0.icache.ReadReq_mshr_misses::total 1254351 # number of ReadReq MSHR misses 1169system.cpu0.icache.demand_mshr_misses::cpu0.inst 1254351 # number of demand (read+write) MSHR misses 1170system.cpu0.icache.demand_mshr_misses::total 1254351 # number of demand (read+write) MSHR misses 1171system.cpu0.icache.overall_mshr_misses::cpu0.inst 1254351 # number of overall MSHR misses 1172system.cpu0.icache.overall_mshr_misses::total 1254351 # number of overall MSHR misses 1173system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable 1174system.cpu0.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable 1175system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses 1176system.cpu0.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses 1177system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11994065954 # number of ReadReq MSHR miss cycles 1178system.cpu0.icache.ReadReq_mshr_miss_latency::total 11994065954 # number of ReadReq MSHR miss cycles 1179system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11994065954 # number of demand (read+write) MSHR miss cycles 1180system.cpu0.icache.demand_mshr_miss_latency::total 11994065954 # number of demand (read+write) MSHR miss cycles 1181system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11994065954 # number of overall MSHR miss cycles 1182system.cpu0.icache.overall_mshr_miss_latency::total 11994065954 # number of overall MSHR miss cycles 1183system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 269145498 # number of ReadReq MSHR uncacheable cycles 1184system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 269145498 # number of ReadReq MSHR uncacheable cycles 1185system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 269145498 # number of overall MSHR uncacheable cycles 1186system.cpu0.icache.overall_mshr_uncacheable_latency::total 269145498 # number of overall MSHR uncacheable cycles 1187system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017253 # mshr miss rate for ReadReq accesses 1188system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017253 # mshr miss rate for ReadReq accesses 1189system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017253 # mshr miss rate for demand accesses 1190system.cpu0.icache.demand_mshr_miss_rate::total 0.017253 # mshr miss rate for demand accesses 1191system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017253 # mshr miss rate for overall accesses 1192system.cpu0.icache.overall_mshr_miss_rate::total 0.017253 # mshr miss rate for overall accesses 1193system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average ReadReq mshr miss latency 1194system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9561.969460 # average ReadReq mshr miss latency 1195system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average overall mshr miss latency 1196system.cpu0.icache.demand_avg_mshr_miss_latency::total 9561.969460 # average overall mshr miss latency 1197system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average overall mshr miss latency 1198system.cpu0.icache.overall_avg_mshr_miss_latency::total 9561.969460 # average overall mshr miss latency 1199system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average ReadReq mshr uncacheable latency 1200system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460 # average ReadReq mshr uncacheable latency 1201system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average overall mshr uncacheable latency 1202system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460 # average overall mshr uncacheable latency 1203system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 1204system.cpu0.l2cache.prefetcher.num_hwpf_issued 1837870 # number of hwpf issued 1205system.cpu0.l2cache.prefetcher.pfIdentified 1840472 # number of prefetch candidates identified 1206system.cpu0.l2cache.prefetcher.pfBufferHit 2353 # number of redundant prefetches already in prefetch queue 1207system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1208system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1209system.cpu0.l2cache.prefetcher.pfSpanPage 236752 # number of prefetches not generated due to page crossing 1210system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 1211system.cpu0.l2cache.tags.replacements 276743 # number of replacements 1212system.cpu0.l2cache.tags.tagsinuse 16098.325627 # Cycle average of tags in use 1213system.cpu0.l2cache.tags.total_refs 3280707 # Total number of references to valid blocks. 1214system.cpu0.l2cache.tags.sampled_refs 292864 # Sample count of references to valid blocks. 1215system.cpu0.l2cache.tags.avg_refs 11.202152 # Average number of references to valid blocks. 1216system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1217system.cpu0.l2cache.tags.occ_blocks::writebacks 14667.103561 # Average occupied blocks per requestor 1218system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 16.169259 # Average occupied blocks per requestor 1219system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.382075 # Average occupied blocks per requestor 1220system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1413.670732 # Average occupied blocks per requestor 1221system.cpu0.l2cache.tags.occ_percent::writebacks 0.895209 # Average percentage of cache occupancy 1222system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000987 # Average percentage of cache occupancy 1223system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000084 # Average percentage of cache occupancy 1224system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.086284 # Average percentage of cache occupancy 1225system.cpu0.l2cache.tags.occ_percent::total 0.982564 # Average percentage of cache occupancy 1226system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1008 # Occupied blocks per task id 1227system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id 1228system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15101 # Occupied blocks per task id 1229system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 35 # Occupied blocks per task id 1230system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 303 # Occupied blocks per task id 1231system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 375 # Occupied blocks per task id 1232system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 295 # Occupied blocks per task id 1233system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 1234system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 1235system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id 1236system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 1237system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id 1238system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 469 # Occupied blocks per task id 1239system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4669 # Occupied blocks per task id 1240system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6979 # Occupied blocks per task id 1241system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2875 # Occupied blocks per task id 1242system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061523 # Percentage of cache occupancy per task id 1243system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id 1244system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921692 # Percentage of cache occupancy per task id 1245system.cpu0.l2cache.tags.tag_accesses 66287217 # Number of tag accesses 1246system.cpu0.l2cache.tags.data_accesses 66287217 # Number of data accesses 1247system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 1248system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55484 # number of ReadReq hits 1249system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13243 # number of ReadReq hits 1250system.cpu0.l2cache.ReadReq_hits::total 68727 # number of ReadReq hits 1251system.cpu0.l2cache.WritebackDirty_hits::writebacks 481730 # number of WritebackDirty hits 1252system.cpu0.l2cache.WritebackDirty_hits::total 481730 # number of WritebackDirty hits 1253system.cpu0.l2cache.WritebackClean_hits::writebacks 1450652 # number of WritebackClean hits 1254system.cpu0.l2cache.WritebackClean_hits::total 1450652 # number of WritebackClean hits 1255system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 1256system.cpu0.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits 1257system.cpu0.l2cache.ReadExReq_hits::cpu0.data 221301 # number of ReadExReq hits 1258system.cpu0.l2cache.ReadExReq_hits::total 221301 # number of ReadExReq hits 1259system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1201423 # number of ReadCleanReq hits 1260system.cpu0.l2cache.ReadCleanReq_hits::total 1201423 # number of ReadCleanReq hits 1261system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 398814 # number of ReadSharedReq hits 1262system.cpu0.l2cache.ReadSharedReq_hits::total 398814 # number of ReadSharedReq hits 1263system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55484 # number of demand (read+write) hits 1264system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13243 # number of demand (read+write) hits 1265system.cpu0.l2cache.demand_hits::cpu0.inst 1201423 # number of demand (read+write) hits 1266system.cpu0.l2cache.demand_hits::cpu0.data 620115 # number of demand (read+write) hits 1267system.cpu0.l2cache.demand_hits::total 1890265 # number of demand (read+write) hits 1268system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55484 # number of overall hits 1269system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13243 # number of overall hits 1270system.cpu0.l2cache.overall_hits::cpu0.inst 1201423 # number of overall hits 1271system.cpu0.l2cache.overall_hits::cpu0.data 620115 # number of overall hits 1272system.cpu0.l2cache.overall_hits::total 1890265 # number of overall hits 1273system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 413 # number of ReadReq misses 1274system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 141 # number of ReadReq misses 1275system.cpu0.l2cache.ReadReq_misses::total 554 # number of ReadReq misses 1276system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 54992 # number of UpgradeReq misses 1277system.cpu0.l2cache.UpgradeReq_misses::total 54992 # number of UpgradeReq misses 1278system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20107 # number of SCUpgradeReq misses 1279system.cpu0.l2cache.SCUpgradeReq_misses::total 20107 # number of SCUpgradeReq misses 1280system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses 1281system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 1282system.cpu0.l2cache.ReadExReq_misses::cpu0.data 47807 # number of ReadExReq misses 1283system.cpu0.l2cache.ReadExReq_misses::total 47807 # number of ReadExReq misses 1284system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 52895 # number of ReadCleanReq misses 1285system.cpu0.l2cache.ReadCleanReq_misses::total 52895 # number of ReadCleanReq misses 1286system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 96473 # number of ReadSharedReq misses 1287system.cpu0.l2cache.ReadSharedReq_misses::total 96473 # number of ReadSharedReq misses 1288system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 413 # number of demand (read+write) misses 1289system.cpu0.l2cache.demand_misses::cpu0.itb.walker 141 # number of demand (read+write) misses 1290system.cpu0.l2cache.demand_misses::cpu0.inst 52895 # number of demand (read+write) misses 1291system.cpu0.l2cache.demand_misses::cpu0.data 144280 # number of demand (read+write) misses 1292system.cpu0.l2cache.demand_misses::total 197729 # number of demand (read+write) misses 1293system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 413 # number of overall misses 1294system.cpu0.l2cache.overall_misses::cpu0.itb.walker 141 # number of overall misses 1295system.cpu0.l2cache.overall_misses::cpu0.inst 52895 # number of overall misses 1296system.cpu0.l2cache.overall_misses::cpu0.data 144280 # number of overall misses 1297system.cpu0.l2cache.overall_misses::total 197729 # number of overall misses 1298system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11587500 # number of ReadReq miss cycles 1299system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3409000 # number of ReadReq miss cycles 1300system.cpu0.l2cache.ReadReq_miss_latency::total 14996500 # number of ReadReq miss cycles 1301system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 108889500 # number of UpgradeReq miss cycles 1302system.cpu0.l2cache.UpgradeReq_miss_latency::total 108889500 # number of UpgradeReq miss cycles 1303system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 23948500 # number of SCUpgradeReq miss cycles 1304system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 23948500 # number of SCUpgradeReq miss cycles 1305system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 220499 # number of SCUpgradeFailReq miss cycles 1306system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 220499 # number of SCUpgradeFailReq miss cycles 1307system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2771311500 # number of ReadExReq miss cycles 1308system.cpu0.l2cache.ReadExReq_miss_latency::total 2771311500 # number of ReadExReq miss cycles 1309system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2784395500 # number of ReadCleanReq miss cycles 1310system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2784395500 # number of ReadCleanReq miss cycles 1311system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2944676496 # number of ReadSharedReq miss cycles 1312system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2944676496 # number of ReadSharedReq miss cycles 1313system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11587500 # number of demand (read+write) miss cycles 1314system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3409000 # number of demand (read+write) miss cycles 1315system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2784395500 # number of demand (read+write) miss cycles 1316system.cpu0.l2cache.demand_miss_latency::cpu0.data 5715987996 # number of demand (read+write) miss cycles 1317system.cpu0.l2cache.demand_miss_latency::total 8515379996 # number of demand (read+write) miss cycles 1318system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11587500 # number of overall miss cycles 1319system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3409000 # number of overall miss cycles 1320system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2784395500 # number of overall miss cycles 1321system.cpu0.l2cache.overall_miss_latency::cpu0.data 5715987996 # number of overall miss cycles 1322system.cpu0.l2cache.overall_miss_latency::total 8515379996 # number of overall miss cycles 1323system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 55897 # number of ReadReq accesses(hits+misses) 1324system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 13384 # number of ReadReq accesses(hits+misses) 1325system.cpu0.l2cache.ReadReq_accesses::total 69281 # number of ReadReq accesses(hits+misses) 1326system.cpu0.l2cache.WritebackDirty_accesses::writebacks 481730 # number of WritebackDirty accesses(hits+misses) 1327system.cpu0.l2cache.WritebackDirty_accesses::total 481730 # number of WritebackDirty accesses(hits+misses) 1328system.cpu0.l2cache.WritebackClean_accesses::writebacks 1450652 # number of WritebackClean accesses(hits+misses) 1329system.cpu0.l2cache.WritebackClean_accesses::total 1450652 # number of WritebackClean accesses(hits+misses) 1330system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54994 # number of UpgradeReq accesses(hits+misses) 1331system.cpu0.l2cache.UpgradeReq_accesses::total 54994 # number of UpgradeReq accesses(hits+misses) 1332system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20107 # number of SCUpgradeReq accesses(hits+misses) 1333system.cpu0.l2cache.SCUpgradeReq_accesses::total 20107 # number of SCUpgradeReq accesses(hits+misses) 1334system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 1335system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 1336system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269108 # number of ReadExReq accesses(hits+misses) 1337system.cpu0.l2cache.ReadExReq_accesses::total 269108 # number of ReadExReq accesses(hits+misses) 1338system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1254318 # number of ReadCleanReq accesses(hits+misses) 1339system.cpu0.l2cache.ReadCleanReq_accesses::total 1254318 # number of ReadCleanReq accesses(hits+misses) 1340system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 495287 # number of ReadSharedReq accesses(hits+misses) 1341system.cpu0.l2cache.ReadSharedReq_accesses::total 495287 # number of ReadSharedReq accesses(hits+misses) 1342system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 55897 # number of demand (read+write) accesses 1343system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 13384 # number of demand (read+write) accesses 1344system.cpu0.l2cache.demand_accesses::cpu0.inst 1254318 # number of demand (read+write) accesses 1345system.cpu0.l2cache.demand_accesses::cpu0.data 764395 # number of demand (read+write) accesses 1346system.cpu0.l2cache.demand_accesses::total 2087994 # number of demand (read+write) accesses 1347system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 55897 # number of overall (read+write) accesses 1348system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 13384 # number of overall (read+write) accesses 1349system.cpu0.l2cache.overall_accesses::cpu0.inst 1254318 # number of overall (read+write) accesses 1350system.cpu0.l2cache.overall_accesses::cpu0.data 764395 # number of overall (read+write) accesses 1351system.cpu0.l2cache.overall_accesses::total 2087994 # number of overall (read+write) accesses 1352system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007389 # miss rate for ReadReq accesses 1353system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.010535 # miss rate for ReadReq accesses 1354system.cpu0.l2cache.ReadReq_miss_rate::total 0.007996 # miss rate for ReadReq accesses 1355system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999964 # miss rate for UpgradeReq accesses 1356system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999964 # miss rate for UpgradeReq accesses 1357system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1358system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1359system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1360system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1361system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.177650 # miss rate for ReadExReq accesses 1362system.cpu0.l2cache.ReadExReq_miss_rate::total 0.177650 # miss rate for ReadExReq accesses 1363system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.042170 # miss rate for ReadCleanReq accesses 1364system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.042170 # miss rate for ReadCleanReq accesses 1365system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.194782 # miss rate for ReadSharedReq accesses 1366system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.194782 # miss rate for ReadSharedReq accesses 1367system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007389 # miss rate for demand accesses 1368system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.010535 # miss rate for demand accesses 1369system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042170 # miss rate for demand accesses 1370system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.188751 # miss rate for demand accesses 1371system.cpu0.l2cache.demand_miss_rate::total 0.094698 # miss rate for demand accesses 1372system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007389 # miss rate for overall accesses 1373system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.010535 # miss rate for overall accesses 1374system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042170 # miss rate for overall accesses 1375system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.188751 # miss rate for overall accesses 1376system.cpu0.l2cache.overall_miss_rate::total 0.094698 # miss rate for overall accesses 1377system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 28056.900726 # average ReadReq miss latency 1378system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24177.304965 # average ReadReq miss latency 1379system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27069.494585 # average ReadReq miss latency 1380system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 1980.097105 # average UpgradeReq miss latency 1381system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 1980.097105 # average UpgradeReq miss latency 1382system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1191.052867 # average SCUpgradeReq miss latency 1383system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1191.052867 # average SCUpgradeReq miss latency 1384system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 220499 # average SCUpgradeFailReq miss latency 1385system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 220499 # average SCUpgradeFailReq miss latency 1386system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 57968.738888 # average ReadExReq miss latency 1387system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 57968.738888 # average ReadExReq miss latency 1388system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 52640.051045 # average ReadCleanReq miss latency 1389system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 52640.051045 # average ReadCleanReq miss latency 1390system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 30523.322546 # average ReadSharedReq miss latency 1391system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 30523.322546 # average ReadSharedReq miss latency 1392system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 28056.900726 # average overall miss latency 1393system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24177.304965 # average overall miss latency 1394system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 52640.051045 # average overall miss latency 1395system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39617.327391 # average overall miss latency 1396system.cpu0.l2cache.demand_avg_miss_latency::total 43065.913427 # average overall miss latency 1397system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 28056.900726 # average overall miss latency 1398system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24177.304965 # average overall miss latency 1399system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 52640.051045 # average overall miss latency 1400system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 39617.327391 # average overall miss latency 1401system.cpu0.l2cache.overall_avg_miss_latency::total 43065.913427 # average overall miss latency 1402system.cpu0.l2cache.blocked_cycles::no_mshrs 136 # number of cycles access was blocked 1403system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1404system.cpu0.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked 1405system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1406system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked 1407system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1408system.cpu0.l2cache.unused_prefetches 10266 # number of HardPF blocks evicted w/o reference 1409system.cpu0.l2cache.writebacks::writebacks 229575 # number of writebacks 1410system.cpu0.l2cache.writebacks::total 229575 # number of writebacks 1411system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 1412system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1413system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5846 # number of ReadExReq MSHR hits 1414system.cpu0.l2cache.ReadExReq_mshr_hits::total 5846 # number of ReadExReq MSHR hits 1415system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 35 # number of ReadCleanReq MSHR hits 1416system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 35 # number of ReadCleanReq MSHR hits 1417system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 765 # number of ReadSharedReq MSHR hits 1418system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 765 # number of ReadSharedReq MSHR hits 1419system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 1420system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 35 # number of demand (read+write) MSHR hits 1421system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6611 # number of demand (read+write) MSHR hits 1422system.cpu0.l2cache.demand_mshr_hits::total 6647 # number of demand (read+write) MSHR hits 1423system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 1424system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 35 # number of overall MSHR hits 1425system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6611 # number of overall MSHR hits 1426system.cpu0.l2cache.overall_mshr_hits::total 6647 # number of overall MSHR hits 1427system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 412 # number of ReadReq MSHR misses 1428system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 141 # number of ReadReq MSHR misses 1429system.cpu0.l2cache.ReadReq_mshr_misses::total 553 # number of ReadReq MSHR misses 1430system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 257570 # number of HardPFReq MSHR misses 1431system.cpu0.l2cache.HardPFReq_mshr_misses::total 257570 # number of HardPFReq MSHR misses 1432system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 54992 # number of UpgradeReq MSHR misses 1433system.cpu0.l2cache.UpgradeReq_mshr_misses::total 54992 # number of UpgradeReq MSHR misses 1434system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20107 # number of SCUpgradeReq MSHR misses 1435system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20107 # number of SCUpgradeReq MSHR misses 1436system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses 1437system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 1438system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41961 # number of ReadExReq MSHR misses 1439system.cpu0.l2cache.ReadExReq_mshr_misses::total 41961 # number of ReadExReq MSHR misses 1440system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 52860 # number of ReadCleanReq MSHR misses 1441system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 52860 # number of ReadCleanReq MSHR misses 1442system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 95708 # number of ReadSharedReq MSHR misses 1443system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 95708 # number of ReadSharedReq MSHR misses 1444system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 412 # number of demand (read+write) MSHR misses 1445system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 141 # number of demand (read+write) MSHR misses 1446system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 52860 # number of demand (read+write) MSHR misses 1447system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137669 # number of demand (read+write) MSHR misses 1448system.cpu0.l2cache.demand_mshr_misses::total 191082 # number of demand (read+write) MSHR misses 1449system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 412 # number of overall MSHR misses 1450system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 141 # number of overall MSHR misses 1451system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 52860 # number of overall MSHR misses 1452system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137669 # number of overall MSHR misses 1453system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 257570 # number of overall MSHR misses 1454system.cpu0.l2cache.overall_mshr_misses::total 448652 # number of overall MSHR misses 1455system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable 1456system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31771 # number of ReadReq MSHR uncacheable 1457system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 34774 # number of ReadReq MSHR uncacheable 1458system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28450 # number of WriteReq MSHR uncacheable 1459system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28450 # number of WriteReq MSHR uncacheable 1460system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses 1461system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60221 # number of overall MSHR uncacheable misses 1462system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63224 # number of overall MSHR uncacheable misses 1463system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 9106500 # number of ReadReq MSHR miss cycles 1464system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2563000 # number of ReadReq MSHR miss cycles 1465system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 11669500 # number of ReadReq MSHR miss cycles 1466system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15404483231 # number of HardPFReq MSHR miss cycles 1467system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15404483231 # number of HardPFReq MSHR miss cycles 1468system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1067197500 # number of UpgradeReq MSHR miss cycles 1469system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1067197500 # number of UpgradeReq MSHR miss cycles 1470system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 312794500 # number of SCUpgradeReq MSHR miss cycles 1471system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 312794500 # number of SCUpgradeReq MSHR miss cycles 1472system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 178499 # number of SCUpgradeFailReq MSHR miss cycles 1473system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 178499 # number of SCUpgradeFailReq MSHR miss cycles 1474system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1799957000 # number of ReadExReq MSHR miss cycles 1475system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1799957000 # number of ReadExReq MSHR miss cycles 1476system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2466178500 # number of ReadCleanReq MSHR miss cycles 1477system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2466178500 # number of ReadCleanReq MSHR miss cycles 1478system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2327314996 # number of ReadSharedReq MSHR miss cycles 1479system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2327314996 # number of ReadSharedReq MSHR miss cycles 1480system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 9106500 # number of demand (read+write) MSHR miss cycles 1481system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2563000 # number of demand (read+write) MSHR miss cycles 1482system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2466178500 # number of demand (read+write) MSHR miss cycles 1483system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4127271996 # number of demand (read+write) MSHR miss cycles 1484system.cpu0.l2cache.demand_mshr_miss_latency::total 6605119996 # number of demand (read+write) MSHR miss cycles 1485system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 9106500 # number of overall MSHR miss cycles 1486system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2563000 # number of overall MSHR miss cycles 1487system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2466178500 # number of overall MSHR miss cycles 1488system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4127271996 # number of overall MSHR miss cycles 1489system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15404483231 # number of overall MSHR miss cycles 1490system.cpu0.l2cache.overall_mshr_miss_latency::total 22009603227 # number of overall MSHR miss cycles 1491system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 246621000 # number of ReadReq MSHR uncacheable cycles 1492system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6366568000 # number of ReadReq MSHR uncacheable cycles 1493system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6613189000 # number of ReadReq MSHR uncacheable cycles 1494system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 246621000 # number of overall MSHR uncacheable cycles 1495system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6366568000 # number of overall MSHR uncacheable cycles 1496system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6613189000 # number of overall MSHR uncacheable cycles 1497system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007371 # mshr miss rate for ReadReq accesses 1498system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.010535 # mshr miss rate for ReadReq accesses 1499system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.007982 # mshr miss rate for ReadReq accesses 1500system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1501system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1502system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999964 # mshr miss rate for UpgradeReq accesses 1503system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999964 # mshr miss rate for UpgradeReq accesses 1504system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1505system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1506system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1507system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1508system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155926 # mshr miss rate for ReadExReq accesses 1509system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155926 # mshr miss rate for ReadExReq accesses 1510system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042142 # mshr miss rate for ReadCleanReq accesses 1511system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042142 # mshr miss rate for ReadCleanReq accesses 1512system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.193237 # mshr miss rate for ReadSharedReq accesses 1513system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.193237 # mshr miss rate for ReadSharedReq accesses 1514system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007371 # mshr miss rate for demand accesses 1515system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.010535 # mshr miss rate for demand accesses 1516system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042142 # mshr miss rate for demand accesses 1517system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.180102 # mshr miss rate for demand accesses 1518system.cpu0.l2cache.demand_mshr_miss_rate::total 0.091515 # mshr miss rate for demand accesses 1519system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007371 # mshr miss rate for overall accesses 1520system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.010535 # mshr miss rate for overall accesses 1521system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042142 # mshr miss rate for overall accesses 1522system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.180102 # mshr miss rate for overall accesses 1523system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1524system.cpu0.l2cache.overall_mshr_miss_rate::total 0.214872 # mshr miss rate for overall accesses 1525system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22103.155340 # average ReadReq mshr miss latency 1526system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18177.304965 # average ReadReq mshr miss latency 1527system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21102.169982 # average ReadReq mshr miss latency 1528system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59806.977641 # average HardPFReq mshr miss latency 1529system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59806.977641 # average HardPFReq mshr miss latency 1530system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19406.413660 # average UpgradeReq mshr miss latency 1531system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19406.413660 # average UpgradeReq mshr miss latency 1532system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15556.497737 # average SCUpgradeReq mshr miss latency 1533system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15556.497737 # average SCUpgradeReq mshr miss latency 1534system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 178499 # average SCUpgradeFailReq mshr miss latency 1535system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 178499 # average SCUpgradeFailReq mshr miss latency 1536system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42895.951002 # average ReadExReq mshr miss latency 1537system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42895.951002 # average ReadExReq mshr miss latency 1538system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 46654.909194 # average ReadCleanReq mshr miss latency 1539system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 46654.909194 # average ReadCleanReq mshr miss latency 1540system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24316.828228 # average ReadSharedReq mshr miss latency 1541system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24316.828228 # average ReadSharedReq mshr miss latency 1542system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22103.155340 # average overall mshr miss latency 1543system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18177.304965 # average overall mshr miss latency 1544system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 46654.909194 # average overall mshr miss latency 1545system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29979.675860 # average overall mshr miss latency 1546system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34566.939827 # average overall mshr miss latency 1547system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22103.155340 # average overall mshr miss latency 1548system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18177.304965 # average overall mshr miss latency 1549system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 46654.909194 # average overall mshr miss latency 1550system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29979.675860 # average overall mshr miss latency 1551system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59806.977641 # average overall mshr miss latency 1552system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49057.182910 # average overall mshr miss latency 1553system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average ReadReq mshr uncacheable latency 1554system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200389.285827 # average ReadReq mshr uncacheable latency 1555system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 190176.252372 # average ReadReq mshr uncacheable latency 1556system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average overall mshr uncacheable latency 1557system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105720.064429 # average overall mshr uncacheable latency 1558system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104599.345185 # average overall mshr uncacheable latency 1559system.cpu0.toL2Bus.snoop_filter.tot_requests 4078191 # Total number of requests made to the snoop filter. 1560system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2059480 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1561system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31273 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1562system.cpu0.toL2Bus.snoop_filter.tot_snoops 323545 # Total number of snoops made to the snoop filter. 1563system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 318913 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1564system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4632 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1565system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 1566system.cpu0.toL2Bus.trans_dist::ReadReq 114042 # Transaction distribution 1567system.cpu0.toL2Bus.trans_dist::ReadResp 1911688 # Transaction distribution 1568system.cpu0.toL2Bus.trans_dist::WriteReq 28450 # Transaction distribution 1569system.cpu0.toL2Bus.trans_dist::WriteResp 28450 # Transaction distribution 1570system.cpu0.toL2Bus.trans_dist::WritebackDirty 711578 # Transaction distribution 1571system.cpu0.toL2Bus.trans_dist::WritebackClean 1481889 # Transaction distribution 1572system.cpu0.toL2Bus.trans_dist::CleanEvict 203573 # Transaction distribution 1573system.cpu0.toL2Bus.trans_dist::HardPFReq 327784 # Transaction distribution 1574system.cpu0.toL2Bus.trans_dist::UpgradeReq 86629 # Transaction distribution 1575system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42593 # Transaction distribution 1576system.cpu0.toL2Bus.trans_dist::UpgradeResp 112544 # Transaction distribution 1577system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution 1578system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution 1579system.cpu0.toL2Bus.trans_dist::ReadExReq 287566 # Transaction distribution 1580system.cpu0.toL2Bus.trans_dist::ReadExResp 284127 # Transaction distribution 1581system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1254351 # Transaction distribution 1582system.cpu0.toL2Bus.trans_dist::ReadSharedReq 576083 # Transaction distribution 1583system.cpu0.toL2Bus.trans_dist::InvalidateReq 3239 # Transaction distribution 1584system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3768469 # Packet count per connected master and slave (bytes) 1585system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2609794 # Packet count per connected master and slave (bytes) 1586system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29242 # Packet count per connected master and slave (bytes) 1587system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119275 # Packet count per connected master and slave (bytes) 1588system.cpu0.toL2Bus.pkt_count::total 6526780 # Packet count per connected master and slave (bytes) 1589system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160567216 # Cumulative packet size per connected master and slave (bytes) 1590system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98579420 # Cumulative packet size per connected master and slave (bytes) 1591system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53536 # Cumulative packet size per connected master and slave (bytes) 1592system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 223588 # Cumulative packet size per connected master and slave (bytes) 1593system.cpu0.toL2Bus.pkt_size::total 259423760 # Cumulative packet size per connected master and slave (bytes) 1594system.cpu0.toL2Bus.snoops 1028398 # Total snoops (count) 1595system.cpu0.toL2Bus.snoop_fanout::samples 3154188 # Request fanout histogram 1596system.cpu0.toL2Bus.snoop_fanout::mean 0.120549 # Request fanout histogram 1597system.cpu0.toL2Bus.snoop_fanout::stdev 0.330082 # Request fanout histogram 1598system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1599system.cpu0.toL2Bus.snoop_fanout::0 2778586 88.09% 88.09% # Request fanout histogram 1600system.cpu0.toL2Bus.snoop_fanout::1 370970 11.76% 99.85% # Request fanout histogram 1601system.cpu0.toL2Bus.snoop_fanout::2 4632 0.15% 100.00% # Request fanout histogram 1602system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1603system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1604system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1605system.cpu0.toL2Bus.snoop_fanout::total 3154188 # Request fanout histogram 1606system.cpu0.toL2Bus.reqLayer0.occupancy 4077816986 # Layer occupancy (ticks) 1607system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1608system.cpu0.toL2Bus.snoopLayer0.occupancy 113410626 # Layer occupancy (ticks) 1609system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1610system.cpu0.toL2Bus.respLayer0.occupancy 1885067918 # Layer occupancy (ticks) 1611system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1612system.cpu0.toL2Bus.respLayer1.occupancy 1231542700 # Layer occupancy (ticks) 1613system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1614system.cpu0.toL2Bus.respLayer2.occupancy 15872970 # Layer occupancy (ticks) 1615system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1616system.cpu0.toL2Bus.respLayer3.occupancy 63417420 # Layer occupancy (ticks) 1617system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1618system.cpu1.branchPred.lookups 4689327 # Number of BP lookups 1619system.cpu1.branchPred.condPredicted 2779312 # Number of conditional branches predicted 1620system.cpu1.branchPred.condIncorrect 269179 # Number of conditional branches incorrect 1621system.cpu1.branchPred.BTBLookups 2466051 # Number of BTB lookups 1622system.cpu1.branchPred.BTBHits 1570212 # Number of BTB hits 1623system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1624system.cpu1.branchPred.BTBHitPct 63.673136 # BTB Hit Percentage 1625system.cpu1.branchPred.usedRAS 878603 # Number of times the RAS was used to get a target. 1626system.cpu1.branchPred.RASInCorrect 7046 # Number of incorrect RAS predictions. 1627system.cpu1.branchPred.indirectLookups 249142 # Number of indirect predictor lookups. 1628system.cpu1.branchPred.indirectHits 213575 # Number of indirect target hits. 1629system.cpu1.branchPred.indirectMisses 35567 # Number of indirect misses. 1630system.cpu1.branchPredindirectMispredicted 10613 # Number of mispredicted indirect branches. 1631system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 1632system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1633system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1634system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1635system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1636system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1637system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1638system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1639system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1640system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1641system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1642system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1643system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1644system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1645system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1646system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1647system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1648system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1649system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1650system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1651system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1652system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1653system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1654system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1655system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1656system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1657system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1658system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1659system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1660system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1661system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 1662system.cpu1.dtb.walker.walks 21410 # Table walker walks requested 1663system.cpu1.dtb.walker.walksShort 21410 # Table walker walks initiated with short descriptors 1664system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8641 # Level at which table walker walks with short descriptors terminate 1665system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5914 # Level at which table walker walks with short descriptors terminate 1666system.cpu1.dtb.walker.walksSquashedBefore 6855 # Table walks squashed before starting 1667system.cpu1.dtb.walker.walkWaitTime::samples 14555 # Table walker wait (enqueue to first request) latency 1668system.cpu1.dtb.walker.walkWaitTime::mean 598.110615 # Table walker wait (enqueue to first request) latency 1669system.cpu1.dtb.walker.walkWaitTime::stdev 3237.595624 # Table walker wait (enqueue to first request) latency 1670system.cpu1.dtb.walker.walkWaitTime::0-4095 13903 95.52% 95.52% # Table walker wait (enqueue to first request) latency 1671system.cpu1.dtb.walker.walkWaitTime::4096-8191 193 1.33% 96.85% # Table walker wait (enqueue to first request) latency 1672system.cpu1.dtb.walker.walkWaitTime::8192-12287 240 1.65% 98.50% # Table walker wait (enqueue to first request) latency 1673system.cpu1.dtb.walker.walkWaitTime::12288-16383 97 0.67% 99.16% # Table walker wait (enqueue to first request) latency 1674system.cpu1.dtb.walker.walkWaitTime::16384-20479 26 0.18% 99.34% # Table walker wait (enqueue to first request) latency 1675system.cpu1.dtb.walker.walkWaitTime::20480-24575 15 0.10% 99.44% # Table walker wait (enqueue to first request) latency 1676system.cpu1.dtb.walker.walkWaitTime::24576-28671 4 0.03% 99.47% # Table walker wait (enqueue to first request) latency 1677system.cpu1.dtb.walker.walkWaitTime::28672-32767 64 0.44% 99.91% # Table walker wait (enqueue to first request) latency 1678system.cpu1.dtb.walker.walkWaitTime::32768-36863 5 0.03% 99.95% # Table walker wait (enqueue to first request) latency 1679system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency 1680system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency 1681system.cpu1.dtb.walker.walkWaitTime::45056-49151 4 0.03% 99.99% # Table walker wait (enqueue to first request) latency 1682system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1683system.cpu1.dtb.walker.walkWaitTime::total 14555 # Table walker wait (enqueue to first request) latency 1684system.cpu1.dtb.walker.walkCompletionTime::samples 5693 # Table walker service (enqueue to completion) latency 1685system.cpu1.dtb.walker.walkCompletionTime::mean 11275.601616 # Table walker service (enqueue to completion) latency 1686system.cpu1.dtb.walker.walkCompletionTime::gmean 9954.937359 # Table walker service (enqueue to completion) latency 1687system.cpu1.dtb.walker.walkCompletionTime::stdev 6246.075100 # Table walker service (enqueue to completion) latency 1688system.cpu1.dtb.walker.walkCompletionTime::0-8191 1927 33.85% 33.85% # Table walker service (enqueue to completion) latency 1689system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3145 55.24% 89.09% # Table walker service (enqueue to completion) latency 1690system.cpu1.dtb.walker.walkCompletionTime::16384-24575 429 7.54% 96.63% # Table walker service (enqueue to completion) latency 1691system.cpu1.dtb.walker.walkCompletionTime::24576-32767 137 2.41% 99.03% # Table walker service (enqueue to completion) latency 1692system.cpu1.dtb.walker.walkCompletionTime::32768-40959 17 0.30% 99.33% # Table walker service (enqueue to completion) latency 1693system.cpu1.dtb.walker.walkCompletionTime::40960-49151 31 0.54% 99.88% # Table walker service (enqueue to completion) latency 1694system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.04% 99.91% # Table walker service (enqueue to completion) latency 1695system.cpu1.dtb.walker.walkCompletionTime::57344-65535 3 0.05% 99.96% # Table walker service (enqueue to completion) latency 1696system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 99.98% # Table walker service (enqueue to completion) latency 1697system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 1698system.cpu1.dtb.walker.walkCompletionTime::total 5693 # Table walker service (enqueue to completion) latency 1699system.cpu1.dtb.walker.walksPending::samples 72606451764 # Table walker pending requests distribution 1700system.cpu1.dtb.walker.walksPending::mean 0.284045 # Table walker pending requests distribution 1701system.cpu1.dtb.walker.walksPending::stdev 0.454557 # Table walker pending requests distribution 1702system.cpu1.dtb.walker.walksPending::0-1 72584974764 99.97% 99.97% # Table walker pending requests distribution 1703system.cpu1.dtb.walker.walksPending::2-3 16673000 0.02% 99.99% # Table walker pending requests distribution 1704system.cpu1.dtb.walker.walksPending::4-5 2243500 0.00% 100.00% # Table walker pending requests distribution 1705system.cpu1.dtb.walker.walksPending::6-7 1638500 0.00% 100.00% # Table walker pending requests distribution 1706system.cpu1.dtb.walker.walksPending::8-9 418000 0.00% 100.00% # Table walker pending requests distribution 1707system.cpu1.dtb.walker.walksPending::10-11 173000 0.00% 100.00% # Table walker pending requests distribution 1708system.cpu1.dtb.walker.walksPending::12-13 183000 0.00% 100.00% # Table walker pending requests distribution 1709system.cpu1.dtb.walker.walksPending::14-15 118000 0.00% 100.00% # Table walker pending requests distribution 1710system.cpu1.dtb.walker.walksPending::16-17 30000 0.00% 100.00% # Table walker pending requests distribution 1711system.cpu1.dtb.walker.walksPending::total 72606451764 # Table walker pending requests distribution 1712system.cpu1.dtb.walker.walkPageSizes::4K 1957 73.85% 73.85% # Table walker page sizes translated 1713system.cpu1.dtb.walker.walkPageSizes::1M 693 26.15% 100.00% # Table walker page sizes translated 1714system.cpu1.dtb.walker.walkPageSizes::total 2650 # Table walker page sizes translated 1715system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21410 # Table walker requests started/completed, data/inst 1716system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1717system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21410 # Table walker requests started/completed, data/inst 1718system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2650 # Table walker requests started/completed, data/inst 1719system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1720system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2650 # Table walker requests started/completed, data/inst 1721system.cpu1.dtb.walker.walkRequestOrigin::total 24060 # Table walker requests started/completed, data/inst 1722system.cpu1.dtb.inst_hits 0 # ITB inst hits 1723system.cpu1.dtb.inst_misses 0 # ITB inst misses 1724system.cpu1.dtb.read_hits 4195760 # DTB read hits 1725system.cpu1.dtb.read_misses 18440 # DTB read misses 1726system.cpu1.dtb.write_hits 3493575 # DTB write hits 1727system.cpu1.dtb.write_misses 2970 # DTB write misses 1728system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1729system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1730system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1731system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	588system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 589system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 590system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 591system.cpu0.itb.perms_faults 1928 # Number of TLB faults due to permissions restrictions 592system.cpu0.itb.read_accesses 0 # DTB read accesses 593system.cpu0.itb.write_accesses 0 # DTB write accesses 594system.cpu0.itb.inst_accesses 72719816 # ITB inst accesses 595system.cpu0.itb.hits 72708872 # DTB hits 596system.cpu0.itb.misses 10944 # DTB misses 597system.cpu0.itb.accesses 72719816 # DTB accesses 598system.cpu0.numPwrStateTransitions 3656 # Number of power state transitions 599system.cpu0.pwrStateClkGateDist::samples 1828 # Distribution of time spent in the clock gated state 600system.cpu0.pwrStateClkGateDist::mean 1490596475.785011 # Distribution of time spent in the clock gated state 601system.cpu0.pwrStateClkGateDist::stdev 23949118810.105305 # Distribution of time spent in the clock gated state 602system.cpu0.pwrStateClkGateDist::underflows 1055 57.71% 57.71% # Distribution of time spent in the clock gated state 603system.cpu0.pwrStateClkGateDist::1000-5e+10 768 42.01% 99.73% # Distribution of time spent in the clock gated state 604system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state 605system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state 606system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 607system.cpu0.pwrStateClkGateDist::max_value 499973380096 # Distribution of time spent in the clock gated state 608system.cpu0.pwrStateClkGateDist::total 1828 # Distribution of time spent in the clock gated state 609system.cpu0.pwrStateResidencyTicks::ON 101149373765 # Cumulative time (in ticks) in various power states 610system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724810357735 # Cumulative time (in ticks) in various power states 611system.cpu0.numCycles 202299816 # number of cpu cycles simulated 612system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 613system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 614system.cpu0.fetch.icacheStallCycles 20373611 # Number of cycles fetch is stalled on an Icache miss 615system.cpu0.fetch.Insts 195792180 # Number of instructions fetch has processed 616system.cpu0.fetch.Branches 53057105 # Number of branches that fetch encountered 617system.cpu0.fetch.predictedBranches 39378425 # Number of branches that fetch has predicted taken 618system.cpu0.fetch.Cycles 174483712 # Number of cycles fetch has run and was not squashing or blocked 619system.cpu0.fetch.SquashCycles 5690816 # Number of cycles fetch has spent squashing 620system.cpu0.fetch.TlbCycles 148557 # Number of cycles fetch has spent waiting for tlb 621system.cpu0.fetch.MiscStallCycles 57787 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 622system.cpu0.fetch.PendingTrapStallCycles 411894 # Number of stall cycles due to pending traps 623system.cpu0.fetch.PendingQuiesceStallCycles 415808 # Number of stall cycles due to pending quiesce instructions 624system.cpu0.fetch.IcacheWaitRetryStallCycles 91444 # Number of stall cycles due to full MSHR 625system.cpu0.fetch.CacheLines 72708572 # Number of cache lines fetched 626system.cpu0.fetch.IcacheSquashes 259286 # Number of outstanding Icache misses that were squashed 627system.cpu0.fetch.ItlbSquashes 5400 # Number of outstanding ITLB misses that were squashed 628system.cpu0.fetch.rateDist::samples 198828221 # Number of instructions fetched each cycle (Total) 629system.cpu0.fetch.rateDist::mean 1.203592 # Number of instructions fetched each cycle (Total) 630system.cpu0.fetch.rateDist::stdev 1.307832 # Number of instructions fetched each cycle (Total) 631system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 632system.cpu0.fetch.rateDist::0 93975229 47.26% 47.26% # Number of instructions fetched each cycle (Total) 633system.cpu0.fetch.rateDist::1 30343697 15.26% 62.53% # Number of instructions fetched each cycle (Total) 634system.cpu0.fetch.rateDist::2 14563448 7.32% 69.85% # Number of instructions fetched each cycle (Total) 635system.cpu0.fetch.rateDist::3 59945847 30.15% 100.00% # Number of instructions fetched each cycle (Total) 636system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 637system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 638system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 639system.cpu0.fetch.rateDist::total 198828221 # Number of instructions fetched each cycle (Total) 640system.cpu0.fetch.branchRate 0.262270 # Number of branch fetches per cycle 641system.cpu0.fetch.rate 0.967832 # Number of inst fetches per cycle 642system.cpu0.decode.IdleCycles 25603497 # Number of cycles decode is idle 643system.cpu0.decode.BlockedCycles 106945433 # Number of cycles decode is blocked 644system.cpu0.decode.RunCycles 58799621 # Number of cycles decode is running 645system.cpu0.decode.UnblockCycles 4964058 # Number of cycles decode is unblocking 646system.cpu0.decode.SquashCycles 2515612 # Number of cycles decode is squashing 647system.cpu0.decode.BranchResolved 3059417 # Number of times decode resolved a branch 648system.cpu0.decode.BranchMispred 333874 # Number of times decode detected a branch misprediction 649system.cpu0.decode.DecodedInsts 154225745 # Number of instructions handled by decode 650system.cpu0.decode.SquashedInsts 3810952 # Number of squashed instructions handled by decode 651system.cpu0.rename.SquashCycles 2515612 # Number of cycles rename is squashing 652system.cpu0.rename.IdleCycles 34211381 # Number of cycles rename is idle 653system.cpu0.rename.BlockCycles 12457896 # Number of cycles rename is blocking 654system.cpu0.rename.serializeStallCycles 83569478 # count of cycles rename stalled for serializing inst 655system.cpu0.rename.RunCycles 55018547 # Number of cycles rename is running 656system.cpu0.rename.UnblockCycles 11055307 # Number of cycles rename is unblocking 657system.cpu0.rename.RenamedInsts 137550697 # Number of instructions processed by rename 658system.cpu0.rename.SquashedInsts 1033071 # Number of squashed instructions processed by rename 659system.cpu0.rename.ROBFullEvents 1452205 # Number of times rename has blocked due to ROB full 660system.cpu0.rename.IQFullEvents 164556 # Number of times rename has blocked due to IQ full 661system.cpu0.rename.LQFullEvents 58179 # Number of times rename has blocked due to LQ full 662system.cpu0.rename.SQFullEvents 6849429 # Number of times rename has blocked due to SQ full 663system.cpu0.rename.RenamedOperands 141656181 # Number of destination operands rename has renamed 664system.cpu0.rename.RenameLookups 634589847 # Number of register rename lookups that rename has made 665system.cpu0.rename.int_rename_lookups 152645231 # Number of integer rename lookups 666system.cpu0.rename.fp_rename_lookups 9369 # Number of floating rename lookups 667system.cpu0.rename.CommittedMaps 130468277 # Number of HB maps that are committed 668system.cpu0.rename.UndoneMaps 11187893 # Number of HB maps that are undone due to squashing 669system.cpu0.rename.serializingInsts 2697265 # count of serializing insts renamed 670system.cpu0.rename.tempSerializingInsts 2555549 # count of temporary serializing insts renamed 671system.cpu0.rename.skidInsts 22573870 # count of insts added to the skid buffer 672system.cpu0.memDep0.insertedLoads 24578234 # Number of loads inserted to the mem dependence unit. 673system.cpu0.memDep0.insertedStores 19061004 # Number of stores inserted to the mem dependence unit. 674system.cpu0.memDep0.conflictingLoads 1697434 # Number of conflicting loads. 675system.cpu0.memDep0.conflictingStores 2322680 # Number of conflicting stores. 676system.cpu0.iq.iqInstsAdded 134618116 # Number of instructions added to the IQ (excludes non-spec) 677system.cpu0.iq.iqNonSpecInstsAdded 1713414 # Number of non-speculative instructions added to the IQ 678system.cpu0.iq.iqInstsIssued 132756465 # Number of instructions issued 679system.cpu0.iq.iqSquashedInstsIssued 452944 # Number of squashed instructions issued 680system.cpu0.iq.iqSquashedInstsExamined 10581179 # Number of squashed instructions iterated over during squash; mainly for profiling 681system.cpu0.iq.iqSquashedOperandsExamined 21719888 # Number of squashed operands that are examined and possibly removed from graph 682system.cpu0.iq.iqSquashedNonSpecRemoved 120083 # Number of squashed non-spec instructions that were removed 683system.cpu0.iq.issued_per_cycle::samples 198828221 # Number of insts issued each cycle 684system.cpu0.iq.issued_per_cycle::mean 0.667694 # Number of insts issued each cycle 685system.cpu0.iq.issued_per_cycle::stdev 0.963230 # Number of insts issued each cycle 686system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 687system.cpu0.iq.issued_per_cycle::0 122137220 61.43% 61.43% # Number of insts issued each cycle 688system.cpu0.iq.issued_per_cycle::1 33612355 16.91% 78.33% # Number of insts issued each cycle 689system.cpu0.iq.issued_per_cycle::2 31219254 15.70% 94.04% # Number of insts issued each cycle 690system.cpu0.iq.issued_per_cycle::3 10732023 5.40% 99.43% # Number of insts issued each cycle 691system.cpu0.iq.issued_per_cycle::4 1127312 0.57% 100.00% # Number of insts issued each cycle 692system.cpu0.iq.issued_per_cycle::5 57 0.00% 100.00% # Number of insts issued each cycle 693system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 694system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 695system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 696system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 697system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 698system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 699system.cpu0.iq.issued_per_cycle::total 198828221 # Number of insts issued each cycle 700system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 701system.cpu0.iq.fu_full::IntAlu 10787922 43.88% 43.88% # attempts to use FU when none available 702system.cpu0.iq.fu_full::IntMult 67 0.00% 43.88% # attempts to use FU when none available 703system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.88% # attempts to use FU when none available 704system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.88% # attempts to use FU when none available 705system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.88% # attempts to use FU when none available 706system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.88% # attempts to use FU when none available 707system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.88% # attempts to use FU when none available 708system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.88% # attempts to use FU when none available 709system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.88% # attempts to use FU when none available 710system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.88% # attempts to use FU when none available 711system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.88% # attempts to use FU when none available 712system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.88% # attempts to use FU when none available 713system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.88% # attempts to use FU when none available 714system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.88% # attempts to use FU when none available 715system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.88% # attempts to use FU when none available 716system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.88% # attempts to use FU when none available 717system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.88% # attempts to use FU when none available 718system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.88% # attempts to use FU when none available 719system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.88% # attempts to use FU when none available 720system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.88% # attempts to use FU when none available 721system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.88% # attempts to use FU when none available 722system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.88% # attempts to use FU when none available 723system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.88% # attempts to use FU when none available 724system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.88% # attempts to use FU when none available 725system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.88% # attempts to use FU when none available 726system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.88% # attempts to use FU when none available 727system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.88% # attempts to use FU when none available 728system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.88% # attempts to use FU when none available 729system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.88% # attempts to use FU when none available 730system.cpu0.iq.fu_full::MemRead 5632694 22.91% 66.78% # attempts to use FU when none available 731system.cpu0.iq.fu_full::MemWrite 8166758 33.22% 100.00% # attempts to use FU when none available 732system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 733system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 734system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued 735system.cpu0.iq.FU_type_0::IntAlu 89674441 67.55% 67.55% # Type of FU issued 736system.cpu0.iq.FU_type_0::IntMult 111153 0.08% 67.63% # Type of FU issued 737system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.63% # Type of FU issued 738system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.63% # Type of FU issued 739system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.63% # Type of FU issued 740system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.63% # Type of FU issued 741system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.63% # Type of FU issued 742system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.63% # Type of FU issued 743system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.63% # Type of FU issued 744system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.63% # Type of FU issued 745system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.63% # Type of FU issued 746system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.63% # Type of FU issued 747system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.63% # Type of FU issued 748system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.63% # Type of FU issued 749system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.63% # Type of FU issued 750system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.63% # Type of FU issued 751system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.63% # Type of FU issued 752system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.63% # Type of FU issued 753system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.63% # Type of FU issued 754system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.63% # Type of FU issued 755system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.63% # Type of FU issued 756system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.63% # Type of FU issued 757system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.63% # Type of FU issued 758system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.63% # Type of FU issued 759system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 67.63% # Type of FU issued 760system.cpu0.iq.FU_type_0::SimdFloatMisc 8107 0.01% 67.64% # Type of FU issued 761system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.64% # Type of FU issued 762system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.64% # Type of FU issued 763system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.64% # Type of FU issued 764system.cpu0.iq.FU_type_0::MemRead 24338377 18.33% 85.97% # Type of FU issued 765system.cpu0.iq.FU_type_0::MemWrite 18622113 14.03% 100.00% # Type of FU issued 766system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 767system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 768system.cpu0.iq.FU_type_0::total 132756465 # Type of FU issued 769system.cpu0.iq.rate 0.656236 # Inst issue rate 770system.cpu0.iq.fu_busy_cnt 24587441 # FU busy when requested 771system.cpu0.iq.fu_busy_rate 0.185207 # FU busy rate (busy events/executed inst) 772system.cpu0.iq.int_inst_queue_reads 489349072 # Number of integer instruction queue reads 773system.cpu0.iq.int_inst_queue_writes 146920725 # Number of integer instruction queue writes 774system.cpu0.iq.int_inst_queue_wakeup_accesses 129226985 # Number of integer instruction queue wakeup accesses 775system.cpu0.iq.fp_inst_queue_reads 32463 # Number of floating instruction queue reads 776system.cpu0.iq.fp_inst_queue_writes 11252 # Number of floating instruction queue writes 777system.cpu0.iq.fp_inst_queue_wakeup_accesses 9717 # Number of floating instruction queue wakeup accesses 778system.cpu0.iq.int_alu_accesses 157320500 # Number of integer alu accesses 779system.cpu0.iq.fp_alu_accesses 21133 # Number of floating point alu accesses 780system.cpu0.iew.lsq.thread0.forwLoads 365431 # Number of loads that had data forwarded from stores 781system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 782system.cpu0.iew.lsq.thread0.squashedLoads 1915604 # Number of loads squashed 783system.cpu0.iew.lsq.thread0.ignoredResponses 2466 # Number of memory responses ignored because the instruction is squashed 784system.cpu0.iew.lsq.thread0.memOrderViolation 19339 # Number of memory ordering violations 785system.cpu0.iew.lsq.thread0.squashedStores 897405 # Number of stores squashed 786system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 787system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 788system.cpu0.iew.lsq.thread0.rescheduledLoads 120966 # Number of loads that were rescheduled 789system.cpu0.iew.lsq.thread0.cacheBlocked 361642 # Number of times an access to memory failed due to the cache being blocked 790system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 791system.cpu0.iew.iewSquashCycles 2515612 # Number of cycles IEW is squashing 792system.cpu0.iew.iewBlockCycles 1602789 # Number of cycles IEW is blocking 793system.cpu0.iew.iewUnblockCycles 184527 # Number of cycles IEW is unblocking 794system.cpu0.iew.iewDispatchedInsts 136483987 # Number of instructions dispatched to IQ 795system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 796system.cpu0.iew.iewDispLoadInsts 24578234 # Number of dispatched load instructions 797system.cpu0.iew.iewDispStoreInsts 19061004 # Number of dispatched store instructions 798system.cpu0.iew.iewDispNonSpecInsts 875924 # Number of dispatched non-speculative instructions 799system.cpu0.iew.iewIQFullEvents 28511 # Number of times the IQ has become full, causing a stall 800system.cpu0.iew.iewLSQFullEvents 132116 # Number of times the LSQ has become full, causing a stall 801system.cpu0.iew.memOrderViolationEvents 19339 # Number of memory order violations 802system.cpu0.iew.predictedTakenIncorrect 261906 # Number of branches that were predicted taken incorrectly 803system.cpu0.iew.predictedNotTakenIncorrect 398193 # Number of branches that were predicted not taken incorrectly 804system.cpu0.iew.branchMispredicts 660099 # Number of branch mispredicts detected at execute 805system.cpu0.iew.iewExecutedInsts 131724041 # Number of executed instructions 806system.cpu0.iew.iewExecLoadInsts 23895876 # Number of load instructions executed 807system.cpu0.iew.iewExecSquashedInsts 965291 # Number of squashed instructions skipped in execute 808system.cpu0.iew.exec_swp 0 # number of swp insts executed 809system.cpu0.iew.exec_nop 152457 # number of nop insts executed 810system.cpu0.iew.exec_refs 42356949 # number of memory reference insts executed 811system.cpu0.iew.exec_branches 25556056 # Number of branches executed 812system.cpu0.iew.exec_stores 18461073 # Number of stores executed 813system.cpu0.iew.exec_rate 0.651133 # Inst execution rate 814system.cpu0.iew.wb_sent 131168007 # cumulative count of insts sent to commit 815system.cpu0.iew.wb_count 129236702 # cumulative count of insts written-back 816system.cpu0.iew.wb_producers 65950850 # num instructions producing a value 817system.cpu0.iew.wb_consumers 106665798 # num instructions consuming a value 818system.cpu0.iew.wb_rate 0.638837 # insts written-back per cycle 819system.cpu0.iew.wb_fanout 0.618294 # average fanout of values written-back 820system.cpu0.commit.commitSquashedInsts 9550008 # The number of squashed insts skipped by commit 821system.cpu0.commit.commitNonSpecStalls 1593331 # The number of times commit has been forced to stall to communicate backwards 822system.cpu0.commit.branchMispredicts 603744 # The number of times a branch was mispredicted 823system.cpu0.commit.committed_per_cycle::samples 195669003 # Number of insts commited each cycle 824system.cpu0.commit.committed_per_cycle::mean 0.643292 # Number of insts commited each cycle 825system.cpu0.commit.committed_per_cycle::stdev 1.341136 # Number of insts commited each cycle 826system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 827system.cpu0.commit.committed_per_cycle::0 135299612 69.15% 69.15% # Number of insts commited each cycle 828system.cpu0.commit.committed_per_cycle::1 33411311 17.08% 86.22% # Number of insts commited each cycle 829system.cpu0.commit.committed_per_cycle::2 12639941 6.46% 92.68% # Number of insts commited each cycle 830system.cpu0.commit.committed_per_cycle::3 3246105 1.66% 94.34% # Number of insts commited each cycle 831system.cpu0.commit.committed_per_cycle::4 4896411 2.50% 96.84% # Number of insts commited each cycle 832system.cpu0.commit.committed_per_cycle::5 2789558 1.43% 98.27% # Number of insts commited each cycle 833system.cpu0.commit.committed_per_cycle::6 1311154 0.67% 98.94% # Number of insts commited each cycle 834system.cpu0.commit.committed_per_cycle::7 556760 0.28% 99.22% # Number of insts commited each cycle 835system.cpu0.commit.committed_per_cycle::8 1518151 0.78% 100.00% # Number of insts commited each cycle 836system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 837system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 838system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 839system.cpu0.commit.committed_per_cycle::total 195669003 # Number of insts commited each cycle 840system.cpu0.commit.committedInsts 103938440 # Number of instructions committed 841system.cpu0.commit.committedOps 125872394 # Number of ops (including micro ops) committed 842system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 843system.cpu0.commit.refs 40826228 # Number of memory references committed 844system.cpu0.commit.loads 22662629 # Number of loads committed 845system.cpu0.commit.membars 647252 # Number of memory barriers committed 846system.cpu0.commit.branches 24954847 # Number of branches committed 847system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. 848system.cpu0.commit.int_insts 109891295 # Number of committed integer instructions. 849system.cpu0.commit.function_calls 4835454 # Number of function calls committed. 850system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 851system.cpu0.commit.op_class_0::IntAlu 84929206 67.47% 67.47% # Class of committed instruction 852system.cpu0.commit.op_class_0::IntMult 108853 0.09% 67.56% # Class of committed instruction 853system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.56% # Class of committed instruction 854system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.56% # Class of committed instruction 855system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.56% # Class of committed instruction 856system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.56% # Class of committed instruction 857system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.56% # Class of committed instruction 858system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.56% # Class of committed instruction 859system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.56% # Class of committed instruction 860system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.56% # Class of committed instruction 861system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.56% # Class of committed instruction 862system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.56% # Class of committed instruction 863system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.56% # Class of committed instruction 864system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.56% # Class of committed instruction 865system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.56% # Class of committed instruction 866system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.56% # Class of committed instruction 867system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.56% # Class of committed instruction 868system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.56% # Class of committed instruction 869system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.56% # Class of committed instruction 870system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.56% # Class of committed instruction 871system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.56% # Class of committed instruction 872system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.56% # Class of committed instruction 873system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.56% # Class of committed instruction 874system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.56% # Class of committed instruction 875system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.56% # Class of committed instruction 876system.cpu0.commit.op_class_0::SimdFloatMisc 8107 0.01% 67.57% # Class of committed instruction 877system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.57% # Class of committed instruction 878system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.57% # Class of committed instruction 879system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.57% # Class of committed instruction 880system.cpu0.commit.op_class_0::MemRead 22662629 18.00% 85.57% # Class of committed instruction 881system.cpu0.commit.op_class_0::MemWrite 18163599 14.43% 100.00% # Class of committed instruction 882system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 883system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 884system.cpu0.commit.op_class_0::total 125872394 # Class of committed instruction 885system.cpu0.commit.bw_lim_events 1518151 # number cycles where commit BW limit reached 886system.cpu0.rob.rob_reads 306287204 # The number of ROB reads 887system.cpu0.rob.rob_writes 273994781 # The number of ROB writes 888system.cpu0.timesIdled 123974 # Number of times that the entire CPU went into an idle state and unscheduled itself 889system.cpu0.idleCycles 3471595 # Total number of cycles that the CPU has spent unscheduled due to idling 890system.cpu0.quiesceCycles 5449619957 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 891system.cpu0.committedInsts 103816388 # Number of Instructions Simulated 892system.cpu0.committedOps 125750342 # Number of Ops (including micro ops) Simulated 893system.cpu0.cpi 1.948631 # CPI: Cycles Per Instruction 894system.cpu0.cpi_total 1.948631 # CPI: Total CPI of All Threads 895system.cpu0.ipc 0.513181 # IPC: Instructions Per Cycle 896system.cpu0.ipc_total 0.513181 # IPC: Total IPC of All Threads 897system.cpu0.int_regfile_reads 142719808 # number of integer regfile reads 898system.cpu0.int_regfile_writes 81679098 # number of integer regfile writes 899system.cpu0.fp_regfile_reads 8185 # number of floating regfile reads 900system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes 901system.cpu0.cc_regfile_reads 464897652 # number of cc regfile reads 902system.cpu0.cc_regfile_writes 49725456 # number of cc regfile writes 903system.cpu0.misc_regfile_reads 388373326 # number of misc regfile reads 904system.cpu0.misc_regfile_writes 1224889 # number of misc regfile writes 905system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 906system.cpu0.dcache.tags.replacements 709828 # number of replacements 907system.cpu0.dcache.tags.tagsinuse 497.174198 # Cycle average of tags in use 908system.cpu0.dcache.tags.total_refs 37665141 # Total number of references to valid blocks. 909system.cpu0.dcache.tags.sampled_refs 710340 # Sample count of references to valid blocks. 910system.cpu0.dcache.tags.avg_refs 53.024103 # Average number of references to valid blocks. 911system.cpu0.dcache.tags.warmup_cycle 278078500 # Cycle when the warmup percentage was hit. 912system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.174198 # Average occupied blocks per requestor 913system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971043 # Average percentage of cache occupancy 914system.cpu0.dcache.tags.occ_percent::total 0.971043 # Average percentage of cache occupancy 915system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 916system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id 917system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id 918system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id 919system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 920system.cpu0.dcache.tags.tag_accesses 81170296 # Number of tag accesses 921system.cpu0.dcache.tags.data_accesses 81170296 # Number of data accesses 922system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 923system.cpu0.dcache.ReadReq_hits::cpu0.data 21454849 # number of ReadReq hits 924system.cpu0.dcache.ReadReq_hits::total 21454849 # number of ReadReq hits 925system.cpu0.dcache.WriteReq_hits::cpu0.data 14988122 # number of WriteReq hits 926system.cpu0.dcache.WriteReq_hits::total 14988122 # number of WriteReq hits 927system.cpu0.dcache.SoftPFReq_hits::cpu0.data 308527 # number of SoftPFReq hits 928system.cpu0.dcache.SoftPFReq_hits::total 308527 # number of SoftPFReq hits 929system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363066 # number of LoadLockedReq hits 930system.cpu0.dcache.LoadLockedReq_hits::total 363066 # number of LoadLockedReq hits 931system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361109 # number of StoreCondReq hits 932system.cpu0.dcache.StoreCondReq_hits::total 361109 # number of StoreCondReq hits 933system.cpu0.dcache.demand_hits::cpu0.data 36442971 # number of demand (read+write) hits 934system.cpu0.dcache.demand_hits::total 36442971 # number of demand (read+write) hits 935system.cpu0.dcache.overall_hits::cpu0.data 36751498 # number of overall hits 936system.cpu0.dcache.overall_hits::total 36751498 # number of overall hits 937system.cpu0.dcache.ReadReq_misses::cpu0.data 646522 # number of ReadReq misses 938system.cpu0.dcache.ReadReq_misses::total 646522 # number of ReadReq misses 939system.cpu0.dcache.WriteReq_misses::cpu0.data 1887777 # number of WriteReq misses 940system.cpu0.dcache.WriteReq_misses::total 1887777 # number of WriteReq misses 941system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147802 # number of SoftPFReq misses 942system.cpu0.dcache.SoftPFReq_misses::total 147802 # number of SoftPFReq misses 943system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25065 # number of LoadLockedReq misses 944system.cpu0.dcache.LoadLockedReq_misses::total 25065 # number of LoadLockedReq misses 945system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20108 # number of StoreCondReq misses 946system.cpu0.dcache.StoreCondReq_misses::total 20108 # number of StoreCondReq misses 947system.cpu0.dcache.demand_misses::cpu0.data 2534299 # number of demand (read+write) misses 948system.cpu0.dcache.demand_misses::total 2534299 # number of demand (read+write) misses 949system.cpu0.dcache.overall_misses::cpu0.data 2682101 # number of overall misses 950system.cpu0.dcache.overall_misses::total 2682101 # number of overall misses 951system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8646662000 # number of ReadReq miss cycles 952system.cpu0.dcache.ReadReq_miss_latency::total 8646662000 # number of ReadReq miss cycles 953system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29876871349 # number of WriteReq miss cycles 954system.cpu0.dcache.WriteReq_miss_latency::total 29876871349 # number of WriteReq miss cycles 955system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 399690500 # number of LoadLockedReq miss cycles 956system.cpu0.dcache.LoadLockedReq_miss_latency::total 399690500 # number of LoadLockedReq miss cycles 957system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 484891000 # number of StoreCondReq miss cycles 958system.cpu0.dcache.StoreCondReq_miss_latency::total 484891000 # number of StoreCondReq miss cycles 959system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 240000 # number of StoreCondFailReq miss cycles 960system.cpu0.dcache.StoreCondFailReq_miss_latency::total 240000 # number of StoreCondFailReq miss cycles 961system.cpu0.dcache.demand_miss_latency::cpu0.data 38523533349 # number of demand (read+write) miss cycles 962system.cpu0.dcache.demand_miss_latency::total 38523533349 # number of demand (read+write) miss cycles 963system.cpu0.dcache.overall_miss_latency::cpu0.data 38523533349 # number of overall miss cycles 964system.cpu0.dcache.overall_miss_latency::total 38523533349 # number of overall miss cycles 965system.cpu0.dcache.ReadReq_accesses::cpu0.data 22101371 # number of ReadReq accesses(hits+misses) 966system.cpu0.dcache.ReadReq_accesses::total 22101371 # number of ReadReq accesses(hits+misses) 967system.cpu0.dcache.WriteReq_accesses::cpu0.data 16875899 # number of WriteReq accesses(hits+misses) 968system.cpu0.dcache.WriteReq_accesses::total 16875899 # number of WriteReq accesses(hits+misses) 969system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456329 # number of SoftPFReq accesses(hits+misses) 970system.cpu0.dcache.SoftPFReq_accesses::total 456329 # number of SoftPFReq accesses(hits+misses) 971system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388131 # number of LoadLockedReq accesses(hits+misses) 972system.cpu0.dcache.LoadLockedReq_accesses::total 388131 # number of LoadLockedReq accesses(hits+misses) 973system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381217 # number of StoreCondReq accesses(hits+misses) 974system.cpu0.dcache.StoreCondReq_accesses::total 381217 # number of StoreCondReq accesses(hits+misses) 975system.cpu0.dcache.demand_accesses::cpu0.data 38977270 # number of demand (read+write) accesses 976system.cpu0.dcache.demand_accesses::total 38977270 # number of demand (read+write) accesses 977system.cpu0.dcache.overall_accesses::cpu0.data 39433599 # number of overall (read+write) accesses 978system.cpu0.dcache.overall_accesses::total 39433599 # number of overall (read+write) accesses 979system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029253 # miss rate for ReadReq accesses 980system.cpu0.dcache.ReadReq_miss_rate::total 0.029253 # miss rate for ReadReq accesses 981system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.111862 # miss rate for WriteReq accesses 982system.cpu0.dcache.WriteReq_miss_rate::total 0.111862 # miss rate for WriteReq accesses 983system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323894 # miss rate for SoftPFReq accesses 984system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323894 # miss rate for SoftPFReq accesses 985system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064579 # miss rate for LoadLockedReq accesses 986system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064579 # miss rate for LoadLockedReq accesses 987system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052747 # miss rate for StoreCondReq accesses 988system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052747 # miss rate for StoreCondReq accesses 989system.cpu0.dcache.demand_miss_rate::cpu0.data 0.065020 # miss rate for demand accesses 990system.cpu0.dcache.demand_miss_rate::total 0.065020 # miss rate for demand accesses 991system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068016 # miss rate for overall accesses 992system.cpu0.dcache.overall_miss_rate::total 0.068016 # miss rate for overall accesses 993system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13374.118746 # average ReadReq miss latency 994system.cpu0.dcache.ReadReq_avg_miss_latency::total 13374.118746 # average ReadReq miss latency 995system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15826.483398 # average WriteReq miss latency 996system.cpu0.dcache.WriteReq_avg_miss_latency::total 15826.483398 # average WriteReq miss latency 997system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15946.159984 # average LoadLockedReq miss latency 998system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15946.159984 # average LoadLockedReq miss latency 999system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24114.332604 # average StoreCondReq miss latency 1000system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24114.332604 # average StoreCondReq miss latency 1001system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1002system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1003system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15200.863572 # average overall miss latency 1004system.cpu0.dcache.demand_avg_miss_latency::total 15200.863572 # average overall miss latency 1005system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14363.192642 # average overall miss latency 1006system.cpu0.dcache.overall_avg_miss_latency::total 14363.192642 # average overall miss latency 1007system.cpu0.dcache.blocked_cycles::no_mshrs 1028 # number of cycles access was blocked 1008system.cpu0.dcache.blocked_cycles::no_targets 4276317 # number of cycles access was blocked 1009system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked 1010system.cpu0.dcache.blocked::no_targets 201917 # number of cycles access was blocked 1011system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.416667 # average number of cycles each access was blocked 1012system.cpu0.dcache.avg_blocked_cycles::no_targets 21.178588 # average number of cycles each access was blocked 1013system.cpu0.dcache.writebacks::writebacks 709828 # number of writebacks 1014system.cpu0.dcache.writebacks::total 709828 # number of writebacks 1015system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 259036 # number of ReadReq MSHR hits 1016system.cpu0.dcache.ReadReq_mshr_hits::total 259036 # number of ReadReq MSHR hits 1017system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1563852 # number of WriteReq MSHR hits 1018system.cpu0.dcache.WriteReq_mshr_hits::total 1563852 # number of WriteReq MSHR hits 1019system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18553 # number of LoadLockedReq MSHR hits 1020system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18553 # number of LoadLockedReq MSHR hits 1021system.cpu0.dcache.demand_mshr_hits::cpu0.data 1822888 # number of demand (read+write) MSHR hits 1022system.cpu0.dcache.demand_mshr_hits::total 1822888 # number of demand (read+write) MSHR hits 1023system.cpu0.dcache.overall_mshr_hits::cpu0.data 1822888 # number of overall MSHR hits 1024system.cpu0.dcache.overall_mshr_hits::total 1822888 # number of overall MSHR hits 1025system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 387486 # number of ReadReq MSHR misses 1026system.cpu0.dcache.ReadReq_mshr_misses::total 387486 # number of ReadReq MSHR misses 1027system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323925 # number of WriteReq MSHR misses 1028system.cpu0.dcache.WriteReq_mshr_misses::total 323925 # number of WriteReq MSHR misses 1029system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101400 # number of SoftPFReq MSHR misses 1030system.cpu0.dcache.SoftPFReq_mshr_misses::total 101400 # number of SoftPFReq MSHR misses 1031system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6512 # number of LoadLockedReq MSHR misses 1032system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6512 # number of LoadLockedReq MSHR misses 1033system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20108 # number of StoreCondReq MSHR misses 1034system.cpu0.dcache.StoreCondReq_mshr_misses::total 20108 # number of StoreCondReq MSHR misses 1035system.cpu0.dcache.demand_mshr_misses::cpu0.data 711411 # number of demand (read+write) MSHR misses 1036system.cpu0.dcache.demand_mshr_misses::total 711411 # number of demand (read+write) MSHR misses 1037system.cpu0.dcache.overall_mshr_misses::cpu0.data 812811 # number of overall MSHR misses 1038system.cpu0.dcache.overall_mshr_misses::total 812811 # number of overall MSHR misses 1039system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31771 # number of ReadReq MSHR uncacheable 1040system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31771 # number of ReadReq MSHR uncacheable 1041system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28450 # number of WriteReq MSHR uncacheable 1042system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28450 # number of WriteReq MSHR uncacheable 1043system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60221 # number of overall MSHR uncacheable misses 1044system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60221 # number of overall MSHR uncacheable misses 1045system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4570691500 # number of ReadReq MSHR miss cycles 1046system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4570691500 # number of ReadReq MSHR miss cycles 1047system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6113916381 # number of WriteReq MSHR miss cycles 1048system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6113916381 # number of WriteReq MSHR miss cycles 1049system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1664414000 # number of SoftPFReq MSHR miss cycles 1050system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1664414000 # number of SoftPFReq MSHR miss cycles 1051system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102380000 # number of LoadLockedReq MSHR miss cycles 1052system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102380000 # number of LoadLockedReq MSHR miss cycles 1053system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 464790000 # number of StoreCondReq MSHR miss cycles 1054system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 464790000 # number of StoreCondReq MSHR miss cycles 1055system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 233000 # number of StoreCondFailReq MSHR miss cycles 1056system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 233000 # number of StoreCondFailReq MSHR miss cycles 1057system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10684607881 # number of demand (read+write) MSHR miss cycles 1058system.cpu0.dcache.demand_mshr_miss_latency::total 10684607881 # number of demand (read+write) MSHR miss cycles 1059system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12349021881 # number of overall MSHR miss cycles 1060system.cpu0.dcache.overall_mshr_miss_latency::total 12349021881 # number of overall MSHR miss cycles 1061system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6621026500 # number of ReadReq MSHR uncacheable cycles 1062system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6621026500 # number of ReadReq MSHR uncacheable cycles 1063system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6621026500 # number of overall MSHR uncacheable cycles 1064system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6621026500 # number of overall MSHR uncacheable cycles 1065system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017532 # mshr miss rate for ReadReq accesses 1066system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017532 # mshr miss rate for ReadReq accesses 1067system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019195 # mshr miss rate for WriteReq accesses 1068system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019195 # mshr miss rate for WriteReq accesses 1069system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222208 # mshr miss rate for SoftPFReq accesses 1070system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222208 # mshr miss rate for SoftPFReq accesses 1071system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016778 # mshr miss rate for LoadLockedReq accesses 1072system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016778 # mshr miss rate for LoadLockedReq accesses 1073system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052747 # mshr miss rate for StoreCondReq accesses 1074system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052747 # mshr miss rate for StoreCondReq accesses 1075system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018252 # mshr miss rate for demand accesses 1076system.cpu0.dcache.demand_mshr_miss_rate::total 0.018252 # mshr miss rate for demand accesses 1077system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020612 # mshr miss rate for overall accesses 1078system.cpu0.dcache.overall_mshr_miss_rate::total 0.020612 # mshr miss rate for overall accesses 1079system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11795.759073 # average ReadReq mshr miss latency 1080system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11795.759073 # average ReadReq mshr miss latency 1081system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18874.481380 # average WriteReq mshr miss latency 1082system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18874.481380 # average WriteReq mshr miss latency 1083system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16414.339250 # average SoftPFReq mshr miss latency 1084system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16414.339250 # average SoftPFReq mshr miss latency 1085system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15721.744472 # average LoadLockedReq mshr miss latency 1086system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15721.744472 # average LoadLockedReq mshr miss latency 1087system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23114.680724 # average StoreCondReq mshr miss latency 1088system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23114.680724 # average StoreCondReq mshr miss latency 1089system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1090system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1091system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15018.896083 # average overall mshr miss latency 1092system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15018.896083 # average overall mshr miss latency 1093system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15192.980756 # average overall mshr miss latency 1094system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15192.980756 # average overall mshr miss latency 1095system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208398.429385 # average ReadReq mshr uncacheable latency 1096system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208398.429385 # average ReadReq mshr uncacheable latency 1097system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109945.475831 # average overall mshr uncacheable latency 1098system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109945.475831 # average overall mshr uncacheable latency 1099system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 1100system.cpu0.icache.tags.replacements 1253795 # number of replacements 1101system.cpu0.icache.tags.tagsinuse 511.762128 # Cycle average of tags in use 1102system.cpu0.icache.tags.total_refs 71396857 # Total number of references to valid blocks. 1103system.cpu0.icache.tags.sampled_refs 1254307 # Sample count of references to valid blocks. 1104system.cpu0.icache.tags.avg_refs 56.921357 # Average number of references to valid blocks. 1105system.cpu0.icache.tags.warmup_cycle 7880422000 # Cycle when the warmup percentage was hit. 1106system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762128 # Average occupied blocks per requestor 1107system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999535 # Average percentage of cache occupancy 1108system.cpu0.icache.tags.occ_percent::total 0.999535 # Average percentage of cache occupancy 1109system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1110system.cpu0.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id 1111system.cpu0.icache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id 1112system.cpu0.icache.tags.age_task_id_blocks_1024::2 122 # Occupied blocks per task id 1113system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1114system.cpu0.icache.tags.tag_accesses 146664376 # Number of tag accesses 1115system.cpu0.icache.tags.data_accesses 146664376 # Number of data accesses 1116system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 1117system.cpu0.icache.ReadReq_hits::cpu0.inst 71396857 # number of ReadReq hits 1118system.cpu0.icache.ReadReq_hits::total 71396857 # number of ReadReq hits 1119system.cpu0.icache.demand_hits::cpu0.inst 71396857 # number of demand (read+write) hits 1120system.cpu0.icache.demand_hits::total 71396857 # number of demand (read+write) hits 1121system.cpu0.icache.overall_hits::cpu0.inst 71396857 # number of overall hits 1122system.cpu0.icache.overall_hits::total 71396857 # number of overall hits 1123system.cpu0.icache.ReadReq_misses::cpu0.inst 1308156 # number of ReadReq misses 1124system.cpu0.icache.ReadReq_misses::total 1308156 # number of ReadReq misses 1125system.cpu0.icache.demand_misses::cpu0.inst 1308156 # number of demand (read+write) misses 1126system.cpu0.icache.demand_misses::total 1308156 # number of demand (read+write) misses 1127system.cpu0.icache.overall_misses::cpu0.inst 1308156 # number of overall misses 1128system.cpu0.icache.overall_misses::total 1308156 # number of overall misses 1129system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13216802476 # number of ReadReq miss cycles 1130system.cpu0.icache.ReadReq_miss_latency::total 13216802476 # number of ReadReq miss cycles 1131system.cpu0.icache.demand_miss_latency::cpu0.inst 13216802476 # number of demand (read+write) miss cycles 1132system.cpu0.icache.demand_miss_latency::total 13216802476 # number of demand (read+write) miss cycles 1133system.cpu0.icache.overall_miss_latency::cpu0.inst 13216802476 # number of overall miss cycles 1134system.cpu0.icache.overall_miss_latency::total 13216802476 # number of overall miss cycles 1135system.cpu0.icache.ReadReq_accesses::cpu0.inst 72705013 # number of ReadReq accesses(hits+misses) 1136system.cpu0.icache.ReadReq_accesses::total 72705013 # number of ReadReq accesses(hits+misses) 1137system.cpu0.icache.demand_accesses::cpu0.inst 72705013 # number of demand (read+write) accesses 1138system.cpu0.icache.demand_accesses::total 72705013 # number of demand (read+write) accesses 1139system.cpu0.icache.overall_accesses::cpu0.inst 72705013 # number of overall (read+write) accesses 1140system.cpu0.icache.overall_accesses::total 72705013 # number of overall (read+write) accesses 1141system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017993 # miss rate for ReadReq accesses 1142system.cpu0.icache.ReadReq_miss_rate::total 0.017993 # miss rate for ReadReq accesses 1143system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017993 # miss rate for demand accesses 1144system.cpu0.icache.demand_miss_rate::total 0.017993 # miss rate for demand accesses 1145system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017993 # miss rate for overall accesses 1146system.cpu0.icache.overall_miss_rate::total 0.017993 # miss rate for overall accesses 1147system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10103.384058 # average ReadReq miss latency 1148system.cpu0.icache.ReadReq_avg_miss_latency::total 10103.384058 # average ReadReq miss latency 1149system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10103.384058 # average overall miss latency 1150system.cpu0.icache.demand_avg_miss_latency::total 10103.384058 # average overall miss latency 1151system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10103.384058 # average overall miss latency 1152system.cpu0.icache.overall_avg_miss_latency::total 10103.384058 # average overall miss latency 1153system.cpu0.icache.blocked_cycles::no_mshrs 1586454 # number of cycles access was blocked 1154system.cpu0.icache.blocked_cycles::no_targets 443 # number of cycles access was blocked 1155system.cpu0.icache.blocked::no_mshrs 112621 # number of cycles access was blocked 1156system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked 1157system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.086662 # average number of cycles each access was blocked 1158system.cpu0.icache.avg_blocked_cycles::no_targets 44.300000 # average number of cycles each access was blocked 1159system.cpu0.icache.writebacks::writebacks 1253795 # number of writebacks 1160system.cpu0.icache.writebacks::total 1253795 # number of writebacks 1161system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53805 # number of ReadReq MSHR hits 1162system.cpu0.icache.ReadReq_mshr_hits::total 53805 # number of ReadReq MSHR hits 1163system.cpu0.icache.demand_mshr_hits::cpu0.inst 53805 # number of demand (read+write) MSHR hits 1164system.cpu0.icache.demand_mshr_hits::total 53805 # number of demand (read+write) MSHR hits 1165system.cpu0.icache.overall_mshr_hits::cpu0.inst 53805 # number of overall MSHR hits 1166system.cpu0.icache.overall_mshr_hits::total 53805 # number of overall MSHR hits 1167system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1254351 # number of ReadReq MSHR misses 1168system.cpu0.icache.ReadReq_mshr_misses::total 1254351 # number of ReadReq MSHR misses 1169system.cpu0.icache.demand_mshr_misses::cpu0.inst 1254351 # number of demand (read+write) MSHR misses 1170system.cpu0.icache.demand_mshr_misses::total 1254351 # number of demand (read+write) MSHR misses 1171system.cpu0.icache.overall_mshr_misses::cpu0.inst 1254351 # number of overall MSHR misses 1172system.cpu0.icache.overall_mshr_misses::total 1254351 # number of overall MSHR misses 1173system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable 1174system.cpu0.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable 1175system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses 1176system.cpu0.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses 1177system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11994065954 # number of ReadReq MSHR miss cycles 1178system.cpu0.icache.ReadReq_mshr_miss_latency::total 11994065954 # number of ReadReq MSHR miss cycles 1179system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11994065954 # number of demand (read+write) MSHR miss cycles 1180system.cpu0.icache.demand_mshr_miss_latency::total 11994065954 # number of demand (read+write) MSHR miss cycles 1181system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11994065954 # number of overall MSHR miss cycles 1182system.cpu0.icache.overall_mshr_miss_latency::total 11994065954 # number of overall MSHR miss cycles 1183system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 269145498 # number of ReadReq MSHR uncacheable cycles 1184system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 269145498 # number of ReadReq MSHR uncacheable cycles 1185system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 269145498 # number of overall MSHR uncacheable cycles 1186system.cpu0.icache.overall_mshr_uncacheable_latency::total 269145498 # number of overall MSHR uncacheable cycles 1187system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017253 # mshr miss rate for ReadReq accesses 1188system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017253 # mshr miss rate for ReadReq accesses 1189system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017253 # mshr miss rate for demand accesses 1190system.cpu0.icache.demand_mshr_miss_rate::total 0.017253 # mshr miss rate for demand accesses 1191system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017253 # mshr miss rate for overall accesses 1192system.cpu0.icache.overall_mshr_miss_rate::total 0.017253 # mshr miss rate for overall accesses 1193system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average ReadReq mshr miss latency 1194system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9561.969460 # average ReadReq mshr miss latency 1195system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average overall mshr miss latency 1196system.cpu0.icache.demand_avg_mshr_miss_latency::total 9561.969460 # average overall mshr miss latency 1197system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average overall mshr miss latency 1198system.cpu0.icache.overall_avg_mshr_miss_latency::total 9561.969460 # average overall mshr miss latency 1199system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average ReadReq mshr uncacheable latency 1200system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460 # average ReadReq mshr uncacheable latency 1201system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average overall mshr uncacheable latency 1202system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460 # average overall mshr uncacheable latency 1203system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 1204system.cpu0.l2cache.prefetcher.num_hwpf_issued 1837870 # number of hwpf issued 1205system.cpu0.l2cache.prefetcher.pfIdentified 1840472 # number of prefetch candidates identified 1206system.cpu0.l2cache.prefetcher.pfBufferHit 2353 # number of redundant prefetches already in prefetch queue 1207system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1208system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1209system.cpu0.l2cache.prefetcher.pfSpanPage 236752 # number of prefetches not generated due to page crossing 1210system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 1211system.cpu0.l2cache.tags.replacements 276743 # number of replacements 1212system.cpu0.l2cache.tags.tagsinuse 16098.325627 # Cycle average of tags in use 1213system.cpu0.l2cache.tags.total_refs 3280707 # Total number of references to valid blocks. 1214system.cpu0.l2cache.tags.sampled_refs 292864 # Sample count of references to valid blocks. 1215system.cpu0.l2cache.tags.avg_refs 11.202152 # Average number of references to valid blocks. 1216system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1217system.cpu0.l2cache.tags.occ_blocks::writebacks 14667.103561 # Average occupied blocks per requestor 1218system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 16.169259 # Average occupied blocks per requestor 1219system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.382075 # Average occupied blocks per requestor 1220system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1413.670732 # Average occupied blocks per requestor 1221system.cpu0.l2cache.tags.occ_percent::writebacks 0.895209 # Average percentage of cache occupancy 1222system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000987 # Average percentage of cache occupancy 1223system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000084 # Average percentage of cache occupancy 1224system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.086284 # Average percentage of cache occupancy 1225system.cpu0.l2cache.tags.occ_percent::total 0.982564 # Average percentage of cache occupancy 1226system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1008 # Occupied blocks per task id 1227system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id 1228system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15101 # Occupied blocks per task id 1229system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 35 # Occupied blocks per task id 1230system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 303 # Occupied blocks per task id 1231system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 375 # Occupied blocks per task id 1232system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 295 # Occupied blocks per task id 1233system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 1234system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 1235system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id 1236system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 1237system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id 1238system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 469 # Occupied blocks per task id 1239system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4669 # Occupied blocks per task id 1240system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6979 # Occupied blocks per task id 1241system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2875 # Occupied blocks per task id 1242system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061523 # Percentage of cache occupancy per task id 1243system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id 1244system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921692 # Percentage of cache occupancy per task id 1245system.cpu0.l2cache.tags.tag_accesses 66287217 # Number of tag accesses 1246system.cpu0.l2cache.tags.data_accesses 66287217 # Number of data accesses 1247system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 1248system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55484 # number of ReadReq hits 1249system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13243 # number of ReadReq hits 1250system.cpu0.l2cache.ReadReq_hits::total 68727 # number of ReadReq hits 1251system.cpu0.l2cache.WritebackDirty_hits::writebacks 481730 # number of WritebackDirty hits 1252system.cpu0.l2cache.WritebackDirty_hits::total 481730 # number of WritebackDirty hits 1253system.cpu0.l2cache.WritebackClean_hits::writebacks 1450652 # number of WritebackClean hits 1254system.cpu0.l2cache.WritebackClean_hits::total 1450652 # number of WritebackClean hits 1255system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 1256system.cpu0.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits 1257system.cpu0.l2cache.ReadExReq_hits::cpu0.data 221301 # number of ReadExReq hits 1258system.cpu0.l2cache.ReadExReq_hits::total 221301 # number of ReadExReq hits 1259system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1201423 # number of ReadCleanReq hits 1260system.cpu0.l2cache.ReadCleanReq_hits::total 1201423 # number of ReadCleanReq hits 1261system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 398814 # number of ReadSharedReq hits 1262system.cpu0.l2cache.ReadSharedReq_hits::total 398814 # number of ReadSharedReq hits 1263system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55484 # number of demand (read+write) hits 1264system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13243 # number of demand (read+write) hits 1265system.cpu0.l2cache.demand_hits::cpu0.inst 1201423 # number of demand (read+write) hits 1266system.cpu0.l2cache.demand_hits::cpu0.data 620115 # number of demand (read+write) hits 1267system.cpu0.l2cache.demand_hits::total 1890265 # number of demand (read+write) hits 1268system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55484 # number of overall hits 1269system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13243 # number of overall hits 1270system.cpu0.l2cache.overall_hits::cpu0.inst 1201423 # number of overall hits 1271system.cpu0.l2cache.overall_hits::cpu0.data 620115 # number of overall hits 1272system.cpu0.l2cache.overall_hits::total 1890265 # number of overall hits 1273system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 413 # number of ReadReq misses 1274system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 141 # number of ReadReq misses 1275system.cpu0.l2cache.ReadReq_misses::total 554 # number of ReadReq misses 1276system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 54992 # number of UpgradeReq misses 1277system.cpu0.l2cache.UpgradeReq_misses::total 54992 # number of UpgradeReq misses 1278system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20107 # number of SCUpgradeReq misses 1279system.cpu0.l2cache.SCUpgradeReq_misses::total 20107 # number of SCUpgradeReq misses 1280system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses 1281system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 1282system.cpu0.l2cache.ReadExReq_misses::cpu0.data 47807 # number of ReadExReq misses 1283system.cpu0.l2cache.ReadExReq_misses::total 47807 # number of ReadExReq misses 1284system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 52895 # number of ReadCleanReq misses 1285system.cpu0.l2cache.ReadCleanReq_misses::total 52895 # number of ReadCleanReq misses 1286system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 96473 # number of ReadSharedReq misses 1287system.cpu0.l2cache.ReadSharedReq_misses::total 96473 # number of ReadSharedReq misses 1288system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 413 # number of demand (read+write) misses 1289system.cpu0.l2cache.demand_misses::cpu0.itb.walker 141 # number of demand (read+write) misses 1290system.cpu0.l2cache.demand_misses::cpu0.inst 52895 # number of demand (read+write) misses 1291system.cpu0.l2cache.demand_misses::cpu0.data 144280 # number of demand (read+write) misses 1292system.cpu0.l2cache.demand_misses::total 197729 # number of demand (read+write) misses 1293system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 413 # number of overall misses 1294system.cpu0.l2cache.overall_misses::cpu0.itb.walker 141 # number of overall misses 1295system.cpu0.l2cache.overall_misses::cpu0.inst 52895 # number of overall misses 1296system.cpu0.l2cache.overall_misses::cpu0.data 144280 # number of overall misses 1297system.cpu0.l2cache.overall_misses::total 197729 # number of overall misses 1298system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11587500 # number of ReadReq miss cycles 1299system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3409000 # number of ReadReq miss cycles 1300system.cpu0.l2cache.ReadReq_miss_latency::total 14996500 # number of ReadReq miss cycles 1301system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 108889500 # number of UpgradeReq miss cycles 1302system.cpu0.l2cache.UpgradeReq_miss_latency::total 108889500 # number of UpgradeReq miss cycles 1303system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 23948500 # number of SCUpgradeReq miss cycles 1304system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 23948500 # number of SCUpgradeReq miss cycles 1305system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 220499 # number of SCUpgradeFailReq miss cycles 1306system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 220499 # number of SCUpgradeFailReq miss cycles 1307system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2771311500 # number of ReadExReq miss cycles 1308system.cpu0.l2cache.ReadExReq_miss_latency::total 2771311500 # number of ReadExReq miss cycles 1309system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2784395500 # number of ReadCleanReq miss cycles 1310system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2784395500 # number of ReadCleanReq miss cycles 1311system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2944676496 # number of ReadSharedReq miss cycles 1312system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2944676496 # number of ReadSharedReq miss cycles 1313system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11587500 # number of demand (read+write) miss cycles 1314system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3409000 # number of demand (read+write) miss cycles 1315system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2784395500 # number of demand (read+write) miss cycles 1316system.cpu0.l2cache.demand_miss_latency::cpu0.data 5715987996 # number of demand (read+write) miss cycles 1317system.cpu0.l2cache.demand_miss_latency::total 8515379996 # number of demand (read+write) miss cycles 1318system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11587500 # number of overall miss cycles 1319system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3409000 # number of overall miss cycles 1320system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2784395500 # number of overall miss cycles 1321system.cpu0.l2cache.overall_miss_latency::cpu0.data 5715987996 # number of overall miss cycles 1322system.cpu0.l2cache.overall_miss_latency::total 8515379996 # number of overall miss cycles 1323system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 55897 # number of ReadReq accesses(hits+misses) 1324system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 13384 # number of ReadReq accesses(hits+misses) 1325system.cpu0.l2cache.ReadReq_accesses::total 69281 # number of ReadReq accesses(hits+misses) 1326system.cpu0.l2cache.WritebackDirty_accesses::writebacks 481730 # number of WritebackDirty accesses(hits+misses) 1327system.cpu0.l2cache.WritebackDirty_accesses::total 481730 # number of WritebackDirty accesses(hits+misses) 1328system.cpu0.l2cache.WritebackClean_accesses::writebacks 1450652 # number of WritebackClean accesses(hits+misses) 1329system.cpu0.l2cache.WritebackClean_accesses::total 1450652 # number of WritebackClean accesses(hits+misses) 1330system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54994 # number of UpgradeReq accesses(hits+misses) 1331system.cpu0.l2cache.UpgradeReq_accesses::total 54994 # number of UpgradeReq accesses(hits+misses) 1332system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20107 # number of SCUpgradeReq accesses(hits+misses) 1333system.cpu0.l2cache.SCUpgradeReq_accesses::total 20107 # number of SCUpgradeReq accesses(hits+misses) 1334system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 1335system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 1336system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269108 # number of ReadExReq accesses(hits+misses) 1337system.cpu0.l2cache.ReadExReq_accesses::total 269108 # number of ReadExReq accesses(hits+misses) 1338system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1254318 # number of ReadCleanReq accesses(hits+misses) 1339system.cpu0.l2cache.ReadCleanReq_accesses::total 1254318 # number of ReadCleanReq accesses(hits+misses) 1340system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 495287 # number of ReadSharedReq accesses(hits+misses) 1341system.cpu0.l2cache.ReadSharedReq_accesses::total 495287 # number of ReadSharedReq accesses(hits+misses) 1342system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 55897 # number of demand (read+write) accesses 1343system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 13384 # number of demand (read+write) accesses 1344system.cpu0.l2cache.demand_accesses::cpu0.inst 1254318 # number of demand (read+write) accesses 1345system.cpu0.l2cache.demand_accesses::cpu0.data 764395 # number of demand (read+write) accesses 1346system.cpu0.l2cache.demand_accesses::total 2087994 # number of demand (read+write) accesses 1347system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 55897 # number of overall (read+write) accesses 1348system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 13384 # number of overall (read+write) accesses 1349system.cpu0.l2cache.overall_accesses::cpu0.inst 1254318 # number of overall (read+write) accesses 1350system.cpu0.l2cache.overall_accesses::cpu0.data 764395 # number of overall (read+write) accesses 1351system.cpu0.l2cache.overall_accesses::total 2087994 # number of overall (read+write) accesses 1352system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007389 # miss rate for ReadReq accesses 1353system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.010535 # miss rate for ReadReq accesses 1354system.cpu0.l2cache.ReadReq_miss_rate::total 0.007996 # miss rate for ReadReq accesses 1355system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999964 # miss rate for UpgradeReq accesses 1356system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999964 # miss rate for UpgradeReq accesses 1357system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1358system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1359system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1360system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1361system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.177650 # miss rate for ReadExReq accesses 1362system.cpu0.l2cache.ReadExReq_miss_rate::total 0.177650 # miss rate for ReadExReq accesses 1363system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.042170 # miss rate for ReadCleanReq accesses 1364system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.042170 # miss rate for ReadCleanReq accesses 1365system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.194782 # miss rate for ReadSharedReq accesses 1366system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.194782 # miss rate for ReadSharedReq accesses 1367system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007389 # miss rate for demand accesses 1368system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.010535 # miss rate for demand accesses 1369system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042170 # miss rate for demand accesses 1370system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.188751 # miss rate for demand accesses 1371system.cpu0.l2cache.demand_miss_rate::total 0.094698 # miss rate for demand accesses 1372system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007389 # miss rate for overall accesses 1373system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.010535 # miss rate for overall accesses 1374system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042170 # miss rate for overall accesses 1375system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.188751 # miss rate for overall accesses 1376system.cpu0.l2cache.overall_miss_rate::total 0.094698 # miss rate for overall accesses 1377system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 28056.900726 # average ReadReq miss latency 1378system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24177.304965 # average ReadReq miss latency 1379system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27069.494585 # average ReadReq miss latency 1380system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 1980.097105 # average UpgradeReq miss latency 1381system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 1980.097105 # average UpgradeReq miss latency 1382system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1191.052867 # average SCUpgradeReq miss latency 1383system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1191.052867 # average SCUpgradeReq miss latency 1384system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 220499 # average SCUpgradeFailReq miss latency 1385system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 220499 # average SCUpgradeFailReq miss latency 1386system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 57968.738888 # average ReadExReq miss latency 1387system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 57968.738888 # average ReadExReq miss latency 1388system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 52640.051045 # average ReadCleanReq miss latency 1389system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 52640.051045 # average ReadCleanReq miss latency 1390system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 30523.322546 # average ReadSharedReq miss latency 1391system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 30523.322546 # average ReadSharedReq miss latency 1392system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 28056.900726 # average overall miss latency 1393system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24177.304965 # average overall miss latency 1394system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 52640.051045 # average overall miss latency 1395system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39617.327391 # average overall miss latency 1396system.cpu0.l2cache.demand_avg_miss_latency::total 43065.913427 # average overall miss latency 1397system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 28056.900726 # average overall miss latency 1398system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24177.304965 # average overall miss latency 1399system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 52640.051045 # average overall miss latency 1400system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 39617.327391 # average overall miss latency 1401system.cpu0.l2cache.overall_avg_miss_latency::total 43065.913427 # average overall miss latency 1402system.cpu0.l2cache.blocked_cycles::no_mshrs 136 # number of cycles access was blocked 1403system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1404system.cpu0.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked 1405system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1406system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked 1407system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1408system.cpu0.l2cache.unused_prefetches 10266 # number of HardPF blocks evicted w/o reference 1409system.cpu0.l2cache.writebacks::writebacks 229575 # number of writebacks 1410system.cpu0.l2cache.writebacks::total 229575 # number of writebacks 1411system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 1412system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1413system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5846 # number of ReadExReq MSHR hits 1414system.cpu0.l2cache.ReadExReq_mshr_hits::total 5846 # number of ReadExReq MSHR hits 1415system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 35 # number of ReadCleanReq MSHR hits 1416system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 35 # number of ReadCleanReq MSHR hits 1417system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 765 # number of ReadSharedReq MSHR hits 1418system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 765 # number of ReadSharedReq MSHR hits 1419system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 1420system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 35 # number of demand (read+write) MSHR hits 1421system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6611 # number of demand (read+write) MSHR hits 1422system.cpu0.l2cache.demand_mshr_hits::total 6647 # number of demand (read+write) MSHR hits 1423system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 1424system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 35 # number of overall MSHR hits 1425system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6611 # number of overall MSHR hits 1426system.cpu0.l2cache.overall_mshr_hits::total 6647 # number of overall MSHR hits 1427system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 412 # number of ReadReq MSHR misses 1428system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 141 # number of ReadReq MSHR misses 1429system.cpu0.l2cache.ReadReq_mshr_misses::total 553 # number of ReadReq MSHR misses 1430system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 257570 # number of HardPFReq MSHR misses 1431system.cpu0.l2cache.HardPFReq_mshr_misses::total 257570 # number of HardPFReq MSHR misses 1432system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 54992 # number of UpgradeReq MSHR misses 1433system.cpu0.l2cache.UpgradeReq_mshr_misses::total 54992 # number of UpgradeReq MSHR misses 1434system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20107 # number of SCUpgradeReq MSHR misses 1435system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20107 # number of SCUpgradeReq MSHR misses 1436system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses 1437system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 1438system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41961 # number of ReadExReq MSHR misses 1439system.cpu0.l2cache.ReadExReq_mshr_misses::total 41961 # number of ReadExReq MSHR misses 1440system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 52860 # number of ReadCleanReq MSHR misses 1441system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 52860 # number of ReadCleanReq MSHR misses 1442system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 95708 # number of ReadSharedReq MSHR misses 1443system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 95708 # number of ReadSharedReq MSHR misses 1444system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 412 # number of demand (read+write) MSHR misses 1445system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 141 # number of demand (read+write) MSHR misses 1446system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 52860 # number of demand (read+write) MSHR misses 1447system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137669 # number of demand (read+write) MSHR misses 1448system.cpu0.l2cache.demand_mshr_misses::total 191082 # number of demand (read+write) MSHR misses 1449system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 412 # number of overall MSHR misses 1450system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 141 # number of overall MSHR misses 1451system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 52860 # number of overall MSHR misses 1452system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137669 # number of overall MSHR misses 1453system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 257570 # number of overall MSHR misses 1454system.cpu0.l2cache.overall_mshr_misses::total 448652 # number of overall MSHR misses 1455system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable 1456system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31771 # number of ReadReq MSHR uncacheable 1457system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 34774 # number of ReadReq MSHR uncacheable 1458system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28450 # number of WriteReq MSHR uncacheable 1459system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28450 # number of WriteReq MSHR uncacheable 1460system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses 1461system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60221 # number of overall MSHR uncacheable misses 1462system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63224 # number of overall MSHR uncacheable misses 1463system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 9106500 # number of ReadReq MSHR miss cycles 1464system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2563000 # number of ReadReq MSHR miss cycles 1465system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 11669500 # number of ReadReq MSHR miss cycles 1466system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15404483231 # number of HardPFReq MSHR miss cycles 1467system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15404483231 # number of HardPFReq MSHR miss cycles 1468system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1067197500 # number of UpgradeReq MSHR miss cycles 1469system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1067197500 # number of UpgradeReq MSHR miss cycles 1470system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 312794500 # number of SCUpgradeReq MSHR miss cycles 1471system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 312794500 # number of SCUpgradeReq MSHR miss cycles 1472system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 178499 # number of SCUpgradeFailReq MSHR miss cycles 1473system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 178499 # number of SCUpgradeFailReq MSHR miss cycles 1474system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1799957000 # number of ReadExReq MSHR miss cycles 1475system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1799957000 # number of ReadExReq MSHR miss cycles 1476system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2466178500 # number of ReadCleanReq MSHR miss cycles 1477system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2466178500 # number of ReadCleanReq MSHR miss cycles 1478system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2327314996 # number of ReadSharedReq MSHR miss cycles 1479system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2327314996 # number of ReadSharedReq MSHR miss cycles 1480system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 9106500 # number of demand (read+write) MSHR miss cycles 1481system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2563000 # number of demand (read+write) MSHR miss cycles 1482system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2466178500 # number of demand (read+write) MSHR miss cycles 1483system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4127271996 # number of demand (read+write) MSHR miss cycles 1484system.cpu0.l2cache.demand_mshr_miss_latency::total 6605119996 # number of demand (read+write) MSHR miss cycles 1485system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 9106500 # number of overall MSHR miss cycles 1486system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2563000 # number of overall MSHR miss cycles 1487system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2466178500 # number of overall MSHR miss cycles 1488system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4127271996 # number of overall MSHR miss cycles 1489system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15404483231 # number of overall MSHR miss cycles 1490system.cpu0.l2cache.overall_mshr_miss_latency::total 22009603227 # number of overall MSHR miss cycles 1491system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 246621000 # number of ReadReq MSHR uncacheable cycles 1492system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6366568000 # number of ReadReq MSHR uncacheable cycles 1493system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6613189000 # number of ReadReq MSHR uncacheable cycles 1494system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 246621000 # number of overall MSHR uncacheable cycles 1495system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6366568000 # number of overall MSHR uncacheable cycles 1496system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6613189000 # number of overall MSHR uncacheable cycles 1497system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007371 # mshr miss rate for ReadReq accesses 1498system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.010535 # mshr miss rate for ReadReq accesses 1499system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.007982 # mshr miss rate for ReadReq accesses 1500system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1501system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1502system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999964 # mshr miss rate for UpgradeReq accesses 1503system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999964 # mshr miss rate for UpgradeReq accesses 1504system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1505system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1506system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1507system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1508system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155926 # mshr miss rate for ReadExReq accesses 1509system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155926 # mshr miss rate for ReadExReq accesses 1510system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042142 # mshr miss rate for ReadCleanReq accesses 1511system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042142 # mshr miss rate for ReadCleanReq accesses 1512system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.193237 # mshr miss rate for ReadSharedReq accesses 1513system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.193237 # mshr miss rate for ReadSharedReq accesses 1514system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007371 # mshr miss rate for demand accesses 1515system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.010535 # mshr miss rate for demand accesses 1516system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042142 # mshr miss rate for demand accesses 1517system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.180102 # mshr miss rate for demand accesses 1518system.cpu0.l2cache.demand_mshr_miss_rate::total 0.091515 # mshr miss rate for demand accesses 1519system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007371 # mshr miss rate for overall accesses 1520system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.010535 # mshr miss rate for overall accesses 1521system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042142 # mshr miss rate for overall accesses 1522system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.180102 # mshr miss rate for overall accesses 1523system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1524system.cpu0.l2cache.overall_mshr_miss_rate::total 0.214872 # mshr miss rate for overall accesses 1525system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22103.155340 # average ReadReq mshr miss latency 1526system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18177.304965 # average ReadReq mshr miss latency 1527system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21102.169982 # average ReadReq mshr miss latency 1528system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59806.977641 # average HardPFReq mshr miss latency 1529system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59806.977641 # average HardPFReq mshr miss latency 1530system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19406.413660 # average UpgradeReq mshr miss latency 1531system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19406.413660 # average UpgradeReq mshr miss latency 1532system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15556.497737 # average SCUpgradeReq mshr miss latency 1533system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15556.497737 # average SCUpgradeReq mshr miss latency 1534system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 178499 # average SCUpgradeFailReq mshr miss latency 1535system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 178499 # average SCUpgradeFailReq mshr miss latency 1536system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42895.951002 # average ReadExReq mshr miss latency 1537system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42895.951002 # average ReadExReq mshr miss latency 1538system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 46654.909194 # average ReadCleanReq mshr miss latency 1539system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 46654.909194 # average ReadCleanReq mshr miss latency 1540system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24316.828228 # average ReadSharedReq mshr miss latency 1541system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24316.828228 # average ReadSharedReq mshr miss latency 1542system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22103.155340 # average overall mshr miss latency 1543system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18177.304965 # average overall mshr miss latency 1544system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 46654.909194 # average overall mshr miss latency 1545system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29979.675860 # average overall mshr miss latency 1546system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34566.939827 # average overall mshr miss latency 1547system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22103.155340 # average overall mshr miss latency 1548system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18177.304965 # average overall mshr miss latency 1549system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 46654.909194 # average overall mshr miss latency 1550system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29979.675860 # average overall mshr miss latency 1551system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59806.977641 # average overall mshr miss latency 1552system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49057.182910 # average overall mshr miss latency 1553system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average ReadReq mshr uncacheable latency 1554system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200389.285827 # average ReadReq mshr uncacheable latency 1555system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 190176.252372 # average ReadReq mshr uncacheable latency 1556system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average overall mshr uncacheable latency 1557system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105720.064429 # average overall mshr uncacheable latency 1558system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104599.345185 # average overall mshr uncacheable latency 1559system.cpu0.toL2Bus.snoop_filter.tot_requests 4078191 # Total number of requests made to the snoop filter. 1560system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2059480 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1561system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31273 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1562system.cpu0.toL2Bus.snoop_filter.tot_snoops 323545 # Total number of snoops made to the snoop filter. 1563system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 318913 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1564system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4632 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1565system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 1566system.cpu0.toL2Bus.trans_dist::ReadReq 114042 # Transaction distribution 1567system.cpu0.toL2Bus.trans_dist::ReadResp 1911688 # Transaction distribution 1568system.cpu0.toL2Bus.trans_dist::WriteReq 28450 # Transaction distribution 1569system.cpu0.toL2Bus.trans_dist::WriteResp 28450 # Transaction distribution 1570system.cpu0.toL2Bus.trans_dist::WritebackDirty 711578 # Transaction distribution 1571system.cpu0.toL2Bus.trans_dist::WritebackClean 1481889 # Transaction distribution 1572system.cpu0.toL2Bus.trans_dist::CleanEvict 203573 # Transaction distribution 1573system.cpu0.toL2Bus.trans_dist::HardPFReq 327784 # Transaction distribution 1574system.cpu0.toL2Bus.trans_dist::UpgradeReq 86629 # Transaction distribution 1575system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42593 # Transaction distribution 1576system.cpu0.toL2Bus.trans_dist::UpgradeResp 112544 # Transaction distribution 1577system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution 1578system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution 1579system.cpu0.toL2Bus.trans_dist::ReadExReq 287566 # Transaction distribution 1580system.cpu0.toL2Bus.trans_dist::ReadExResp 284127 # Transaction distribution 1581system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1254351 # Transaction distribution 1582system.cpu0.toL2Bus.trans_dist::ReadSharedReq 576083 # Transaction distribution 1583system.cpu0.toL2Bus.trans_dist::InvalidateReq 3239 # Transaction distribution 1584system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3768469 # Packet count per connected master and slave (bytes) 1585system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2609794 # Packet count per connected master and slave (bytes) 1586system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29242 # Packet count per connected master and slave (bytes) 1587system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119275 # Packet count per connected master and slave (bytes) 1588system.cpu0.toL2Bus.pkt_count::total 6526780 # Packet count per connected master and slave (bytes) 1589system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160567216 # Cumulative packet size per connected master and slave (bytes) 1590system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98579420 # Cumulative packet size per connected master and slave (bytes) 1591system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53536 # Cumulative packet size per connected master and slave (bytes) 1592system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 223588 # Cumulative packet size per connected master and slave (bytes) 1593system.cpu0.toL2Bus.pkt_size::total 259423760 # Cumulative packet size per connected master and slave (bytes) 1594system.cpu0.toL2Bus.snoops 1028398 # Total snoops (count) 1595system.cpu0.toL2Bus.snoop_fanout::samples 3154188 # Request fanout histogram 1596system.cpu0.toL2Bus.snoop_fanout::mean 0.120549 # Request fanout histogram 1597system.cpu0.toL2Bus.snoop_fanout::stdev 0.330082 # Request fanout histogram 1598system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1599system.cpu0.toL2Bus.snoop_fanout::0 2778586 88.09% 88.09% # Request fanout histogram 1600system.cpu0.toL2Bus.snoop_fanout::1 370970 11.76% 99.85% # Request fanout histogram 1601system.cpu0.toL2Bus.snoop_fanout::2 4632 0.15% 100.00% # Request fanout histogram 1602system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1603system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1604system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1605system.cpu0.toL2Bus.snoop_fanout::total 3154188 # Request fanout histogram 1606system.cpu0.toL2Bus.reqLayer0.occupancy 4077816986 # Layer occupancy (ticks) 1607system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1608system.cpu0.toL2Bus.snoopLayer0.occupancy 113410626 # Layer occupancy (ticks) 1609system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1610system.cpu0.toL2Bus.respLayer0.occupancy 1885067918 # Layer occupancy (ticks) 1611system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1612system.cpu0.toL2Bus.respLayer1.occupancy 1231542700 # Layer occupancy (ticks) 1613system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1614system.cpu0.toL2Bus.respLayer2.occupancy 15872970 # Layer occupancy (ticks) 1615system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1616system.cpu0.toL2Bus.respLayer3.occupancy 63417420 # Layer occupancy (ticks) 1617system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1618system.cpu1.branchPred.lookups 4689327 # Number of BP lookups 1619system.cpu1.branchPred.condPredicted 2779312 # Number of conditional branches predicted 1620system.cpu1.branchPred.condIncorrect 269179 # Number of conditional branches incorrect 1621system.cpu1.branchPred.BTBLookups 2466051 # Number of BTB lookups 1622system.cpu1.branchPred.BTBHits 1570212 # Number of BTB hits 1623system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1624system.cpu1.branchPred.BTBHitPct 63.673136 # BTB Hit Percentage 1625system.cpu1.branchPred.usedRAS 878603 # Number of times the RAS was used to get a target. 1626system.cpu1.branchPred.RASInCorrect 7046 # Number of incorrect RAS predictions. 1627system.cpu1.branchPred.indirectLookups 249142 # Number of indirect predictor lookups. 1628system.cpu1.branchPred.indirectHits 213575 # Number of indirect target hits. 1629system.cpu1.branchPred.indirectMisses 35567 # Number of indirect misses. 1630system.cpu1.branchPredindirectMispredicted 10613 # Number of mispredicted indirect branches. 1631system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 1632system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1633system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1634system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1635system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1636system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1637system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1638system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1639system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1640system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1641system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1642system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1643system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1644system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1645system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1646system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1647system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1648system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1649system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1650system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1651system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1652system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1653system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1654system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1655system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1656system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1657system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1658system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1659system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1660system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1661system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 1662system.cpu1.dtb.walker.walks 21410 # Table walker walks requested 1663system.cpu1.dtb.walker.walksShort 21410 # Table walker walks initiated with short descriptors 1664system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8641 # Level at which table walker walks with short descriptors terminate 1665system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5914 # Level at which table walker walks with short descriptors terminate 1666system.cpu1.dtb.walker.walksSquashedBefore 6855 # Table walks squashed before starting 1667system.cpu1.dtb.walker.walkWaitTime::samples 14555 # Table walker wait (enqueue to first request) latency 1668system.cpu1.dtb.walker.walkWaitTime::mean 598.110615 # Table walker wait (enqueue to first request) latency 1669system.cpu1.dtb.walker.walkWaitTime::stdev 3237.595624 # Table walker wait (enqueue to first request) latency 1670system.cpu1.dtb.walker.walkWaitTime::0-4095 13903 95.52% 95.52% # Table walker wait (enqueue to first request) latency 1671system.cpu1.dtb.walker.walkWaitTime::4096-8191 193 1.33% 96.85% # Table walker wait (enqueue to first request) latency 1672system.cpu1.dtb.walker.walkWaitTime::8192-12287 240 1.65% 98.50% # Table walker wait (enqueue to first request) latency 1673system.cpu1.dtb.walker.walkWaitTime::12288-16383 97 0.67% 99.16% # Table walker wait (enqueue to first request) latency 1674system.cpu1.dtb.walker.walkWaitTime::16384-20479 26 0.18% 99.34% # Table walker wait (enqueue to first request) latency 1675system.cpu1.dtb.walker.walkWaitTime::20480-24575 15 0.10% 99.44% # Table walker wait (enqueue to first request) latency 1676system.cpu1.dtb.walker.walkWaitTime::24576-28671 4 0.03% 99.47% # Table walker wait (enqueue to first request) latency 1677system.cpu1.dtb.walker.walkWaitTime::28672-32767 64 0.44% 99.91% # Table walker wait (enqueue to first request) latency 1678system.cpu1.dtb.walker.walkWaitTime::32768-36863 5 0.03% 99.95% # Table walker wait (enqueue to first request) latency 1679system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency 1680system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency 1681system.cpu1.dtb.walker.walkWaitTime::45056-49151 4 0.03% 99.99% # Table walker wait (enqueue to first request) latency 1682system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1683system.cpu1.dtb.walker.walkWaitTime::total 14555 # Table walker wait (enqueue to first request) latency 1684system.cpu1.dtb.walker.walkCompletionTime::samples 5693 # Table walker service (enqueue to completion) latency 1685system.cpu1.dtb.walker.walkCompletionTime::mean 11275.601616 # Table walker service (enqueue to completion) latency 1686system.cpu1.dtb.walker.walkCompletionTime::gmean 9954.937359 # Table walker service (enqueue to completion) latency 1687system.cpu1.dtb.walker.walkCompletionTime::stdev 6246.075100 # Table walker service (enqueue to completion) latency 1688system.cpu1.dtb.walker.walkCompletionTime::0-8191 1927 33.85% 33.85% # Table walker service (enqueue to completion) latency 1689system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3145 55.24% 89.09% # Table walker service (enqueue to completion) latency 1690system.cpu1.dtb.walker.walkCompletionTime::16384-24575 429 7.54% 96.63% # Table walker service (enqueue to completion) latency 1691system.cpu1.dtb.walker.walkCompletionTime::24576-32767 137 2.41% 99.03% # Table walker service (enqueue to completion) latency 1692system.cpu1.dtb.walker.walkCompletionTime::32768-40959 17 0.30% 99.33% # Table walker service (enqueue to completion) latency 1693system.cpu1.dtb.walker.walkCompletionTime::40960-49151 31 0.54% 99.88% # Table walker service (enqueue to completion) latency 1694system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.04% 99.91% # Table walker service (enqueue to completion) latency 1695system.cpu1.dtb.walker.walkCompletionTime::57344-65535 3 0.05% 99.96% # Table walker service (enqueue to completion) latency 1696system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 99.98% # Table walker service (enqueue to completion) latency 1697system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 1698system.cpu1.dtb.walker.walkCompletionTime::total 5693 # Table walker service (enqueue to completion) latency 1699system.cpu1.dtb.walker.walksPending::samples 72606451764 # Table walker pending requests distribution 1700system.cpu1.dtb.walker.walksPending::mean 0.284045 # Table walker pending requests distribution 1701system.cpu1.dtb.walker.walksPending::stdev 0.454557 # Table walker pending requests distribution 1702system.cpu1.dtb.walker.walksPending::0-1 72584974764 99.97% 99.97% # Table walker pending requests distribution 1703system.cpu1.dtb.walker.walksPending::2-3 16673000 0.02% 99.99% # Table walker pending requests distribution 1704system.cpu1.dtb.walker.walksPending::4-5 2243500 0.00% 100.00% # Table walker pending requests distribution 1705system.cpu1.dtb.walker.walksPending::6-7 1638500 0.00% 100.00% # Table walker pending requests distribution 1706system.cpu1.dtb.walker.walksPending::8-9 418000 0.00% 100.00% # Table walker pending requests distribution 1707system.cpu1.dtb.walker.walksPending::10-11 173000 0.00% 100.00% # Table walker pending requests distribution 1708system.cpu1.dtb.walker.walksPending::12-13 183000 0.00% 100.00% # Table walker pending requests distribution 1709system.cpu1.dtb.walker.walksPending::14-15 118000 0.00% 100.00% # Table walker pending requests distribution 1710system.cpu1.dtb.walker.walksPending::16-17 30000 0.00% 100.00% # Table walker pending requests distribution 1711system.cpu1.dtb.walker.walksPending::total 72606451764 # Table walker pending requests distribution 1712system.cpu1.dtb.walker.walkPageSizes::4K 1957 73.85% 73.85% # Table walker page sizes translated 1713system.cpu1.dtb.walker.walkPageSizes::1M 693 26.15% 100.00% # Table walker page sizes translated 1714system.cpu1.dtb.walker.walkPageSizes::total 2650 # Table walker page sizes translated 1715system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21410 # Table walker requests started/completed, data/inst 1716system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1717system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21410 # Table walker requests started/completed, data/inst 1718system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2650 # Table walker requests started/completed, data/inst 1719system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1720system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2650 # Table walker requests started/completed, data/inst 1721system.cpu1.dtb.walker.walkRequestOrigin::total 24060 # Table walker requests started/completed, data/inst 1722system.cpu1.dtb.inst_hits 0 # ITB inst hits 1723system.cpu1.dtb.inst_misses 0 # ITB inst misses 1724system.cpu1.dtb.read_hits 4195760 # DTB read hits 1725system.cpu1.dtb.read_misses 18440 # DTB read misses 1726system.cpu1.dtb.write_hits 3493575 # DTB write hits 1727system.cpu1.dtb.write_misses 2970 # DTB write misses 1728system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1729system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1730system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1731system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1732system.cpu1.dtb.flush_entries 2051 # Number of entries that have been flushed from TLB	1732system.cpu1.dtb.flush_entries 1987 # Number of entries that have been flushed from TLB
1733system.cpu1.dtb.align_faults 47 # Number of TLB faults due to alignment restrictions 1734system.cpu1.dtb.prefetch_faults 392 # Number of TLB faults due to prefetch 1735system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1736system.cpu1.dtb.perms_faults 375 # Number of TLB faults due to permissions restrictions 1737system.cpu1.dtb.read_accesses 4214200 # DTB read accesses 1738system.cpu1.dtb.write_accesses 3496545 # DTB write accesses 1739system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1740system.cpu1.dtb.hits 7689335 # DTB hits 1741system.cpu1.dtb.misses 21410 # DTB misses 1742system.cpu1.dtb.accesses 7710745 # DTB accesses 1743system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 1744system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1745system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1746system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1747system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1748system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1749system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1750system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1751system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1752system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1753system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1754system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1755system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1756system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1757system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1758system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1759system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1760system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1761system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1762system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1763system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1764system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1765system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1766system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1767system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1768system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1769system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1770system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1771system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1772system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1773system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 1774system.cpu1.itb.walker.walks 5994 # Table walker walks requested 1775system.cpu1.itb.walker.walksShort 5994 # Table walker walks initiated with short descriptors 1776system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2734 # Level at which table walker walks with short descriptors terminate 1777system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2643 # Level at which table walker walks with short descriptors terminate 1778system.cpu1.itb.walker.walksSquashedBefore 617 # Table walks squashed before starting 1779system.cpu1.itb.walker.walkWaitTime::samples 5377 # Table walker wait (enqueue to first request) latency 1780system.cpu1.itb.walker.walkWaitTime::mean 333.364330 # Table walker wait (enqueue to first request) latency 1781system.cpu1.itb.walker.walkWaitTime::stdev 2161.417395 # Table walker wait (enqueue to first request) latency 1782system.cpu1.itb.walker.walkWaitTime::0-4095 5231 97.28% 97.28% # Table walker wait (enqueue to first request) latency 1783system.cpu1.itb.walker.walkWaitTime::4096-8191 63 1.17% 98.46% # Table walker wait (enqueue to first request) latency 1784system.cpu1.itb.walker.walkWaitTime::8192-12287 36 0.67% 99.13% # Table walker wait (enqueue to first request) latency 1785system.cpu1.itb.walker.walkWaitTime::12288-16383 24 0.45% 99.57% # Table walker wait (enqueue to first request) latency 1786system.cpu1.itb.walker.walkWaitTime::16384-20479 7 0.13% 99.70% # Table walker wait (enqueue to first request) latency 1787system.cpu1.itb.walker.walkWaitTime::20480-24575 4 0.07% 99.78% # Table walker wait (enqueue to first request) latency 1788system.cpu1.itb.walker.walkWaitTime::24576-28671 7 0.13% 99.91% # Table walker wait (enqueue to first request) latency 1789system.cpu1.itb.walker.walkWaitTime::28672-32767 3 0.06% 99.96% # Table walker wait (enqueue to first request) latency 1790system.cpu1.itb.walker.walkWaitTime::32768-36863 2 0.04% 100.00% # Table walker wait (enqueue to first request) latency 1791system.cpu1.itb.walker.walkWaitTime::total 5377 # Table walker wait (enqueue to first request) latency 1792system.cpu1.itb.walker.walkCompletionTime::samples 1782 # Table walker service (enqueue to completion) latency 1793system.cpu1.itb.walker.walkCompletionTime::mean 11592.031425 # Table walker service (enqueue to completion) latency 1794system.cpu1.itb.walker.walkCompletionTime::gmean 10629.889069 # Table walker service (enqueue to completion) latency 1795system.cpu1.itb.walker.walkCompletionTime::stdev 5561.428024 # Table walker service (enqueue to completion) latency 1796system.cpu1.itb.walker.walkCompletionTime::0-8191 316 17.73% 17.73% # Table walker service (enqueue to completion) latency 1797system.cpu1.itb.walker.walkCompletionTime::8192-16383 1349 75.70% 93.43% # Table walker service (enqueue to completion) latency 1798system.cpu1.itb.walker.walkCompletionTime::16384-24575 63 3.54% 96.97% # Table walker service (enqueue to completion) latency 1799system.cpu1.itb.walker.walkCompletionTime::24576-32767 25 1.40% 98.37% # Table walker service (enqueue to completion) latency 1800system.cpu1.itb.walker.walkCompletionTime::32768-40959 19 1.07% 99.44% # Table walker service (enqueue to completion) latency 1801system.cpu1.itb.walker.walkCompletionTime::40960-49151 3 0.17% 99.61% # Table walker service (enqueue to completion) latency 1802system.cpu1.itb.walker.walkCompletionTime::49152-57343 4 0.22% 99.83% # Table walker service (enqueue to completion) latency 1803system.cpu1.itb.walker.walkCompletionTime::57344-65535 2 0.11% 99.94% # Table walker service (enqueue to completion) latency 1804system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency 1805system.cpu1.itb.walker.walkCompletionTime::total 1782 # Table walker service (enqueue to completion) latency 1806system.cpu1.itb.walker.walksPending::samples 16752128416 # Table walker pending requests distribution 1807system.cpu1.itb.walker.walksPending::mean 0.862615 # Table walker pending requests distribution 1808system.cpu1.itb.walker.walksPending::stdev 0.344368 # Table walker pending requests distribution 1809system.cpu1.itb.walker.walksPending::0 2302152764 13.74% 13.74% # Table walker pending requests distribution 1810system.cpu1.itb.walker.walksPending::1 14449314652 86.25% 100.00% # Table walker pending requests distribution 1811system.cpu1.itb.walker.walksPending::2 661000 0.00% 100.00% # Table walker pending requests distribution 1812system.cpu1.itb.walker.walksPending::total 16752128416 # Table walker pending requests distribution 1813system.cpu1.itb.walker.walkPageSizes::4K 990 84.98% 84.98% # Table walker page sizes translated 1814system.cpu1.itb.walker.walkPageSizes::1M 175 15.02% 100.00% # Table walker page sizes translated 1815system.cpu1.itb.walker.walkPageSizes::total 1165 # Table walker page sizes translated 1816system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1817system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5994 # Table walker requests started/completed, data/inst 1818system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5994 # Table walker requests started/completed, data/inst 1819system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1820system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1165 # Table walker requests started/completed, data/inst 1821system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1165 # Table walker requests started/completed, data/inst 1822system.cpu1.itb.walker.walkRequestOrigin::total 7159 # Table walker requests started/completed, data/inst 1823system.cpu1.itb.inst_hits 8253439 # ITB inst hits 1824system.cpu1.itb.inst_misses 5994 # ITB inst misses 1825system.cpu1.itb.read_hits 0 # DTB read hits 1826system.cpu1.itb.read_misses 0 # DTB read misses 1827system.cpu1.itb.write_hits 0 # DTB write hits 1828system.cpu1.itb.write_misses 0 # DTB write misses 1829system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1830system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1831system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1832system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	1733system.cpu1.dtb.align_faults 47 # Number of TLB faults due to alignment restrictions 1734system.cpu1.dtb.prefetch_faults 392 # Number of TLB faults due to prefetch 1735system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1736system.cpu1.dtb.perms_faults 375 # Number of TLB faults due to permissions restrictions 1737system.cpu1.dtb.read_accesses 4214200 # DTB read accesses 1738system.cpu1.dtb.write_accesses 3496545 # DTB write accesses 1739system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1740system.cpu1.dtb.hits 7689335 # DTB hits 1741system.cpu1.dtb.misses 21410 # DTB misses 1742system.cpu1.dtb.accesses 7710745 # DTB accesses 1743system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 1744system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1745system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1746system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1747system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1748system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1749system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1750system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1751system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1752system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1753system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1754system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1755system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1756system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1757system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1758system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1759system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1760system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1761system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1762system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1763system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1764system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1765system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1766system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1767system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1768system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1769system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1770system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1771system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1772system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1773system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 1774system.cpu1.itb.walker.walks 5994 # Table walker walks requested 1775system.cpu1.itb.walker.walksShort 5994 # Table walker walks initiated with short descriptors 1776system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2734 # Level at which table walker walks with short descriptors terminate 1777system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2643 # Level at which table walker walks with short descriptors terminate 1778system.cpu1.itb.walker.walksSquashedBefore 617 # Table walks squashed before starting 1779system.cpu1.itb.walker.walkWaitTime::samples 5377 # Table walker wait (enqueue to first request) latency 1780system.cpu1.itb.walker.walkWaitTime::mean 333.364330 # Table walker wait (enqueue to first request) latency 1781system.cpu1.itb.walker.walkWaitTime::stdev 2161.417395 # Table walker wait (enqueue to first request) latency 1782system.cpu1.itb.walker.walkWaitTime::0-4095 5231 97.28% 97.28% # Table walker wait (enqueue to first request) latency 1783system.cpu1.itb.walker.walkWaitTime::4096-8191 63 1.17% 98.46% # Table walker wait (enqueue to first request) latency 1784system.cpu1.itb.walker.walkWaitTime::8192-12287 36 0.67% 99.13% # Table walker wait (enqueue to first request) latency 1785system.cpu1.itb.walker.walkWaitTime::12288-16383 24 0.45% 99.57% # Table walker wait (enqueue to first request) latency 1786system.cpu1.itb.walker.walkWaitTime::16384-20479 7 0.13% 99.70% # Table walker wait (enqueue to first request) latency 1787system.cpu1.itb.walker.walkWaitTime::20480-24575 4 0.07% 99.78% # Table walker wait (enqueue to first request) latency 1788system.cpu1.itb.walker.walkWaitTime::24576-28671 7 0.13% 99.91% # Table walker wait (enqueue to first request) latency 1789system.cpu1.itb.walker.walkWaitTime::28672-32767 3 0.06% 99.96% # Table walker wait (enqueue to first request) latency 1790system.cpu1.itb.walker.walkWaitTime::32768-36863 2 0.04% 100.00% # Table walker wait (enqueue to first request) latency 1791system.cpu1.itb.walker.walkWaitTime::total 5377 # Table walker wait (enqueue to first request) latency 1792system.cpu1.itb.walker.walkCompletionTime::samples 1782 # Table walker service (enqueue to completion) latency 1793system.cpu1.itb.walker.walkCompletionTime::mean 11592.031425 # Table walker service (enqueue to completion) latency 1794system.cpu1.itb.walker.walkCompletionTime::gmean 10629.889069 # Table walker service (enqueue to completion) latency 1795system.cpu1.itb.walker.walkCompletionTime::stdev 5561.428024 # Table walker service (enqueue to completion) latency 1796system.cpu1.itb.walker.walkCompletionTime::0-8191 316 17.73% 17.73% # Table walker service (enqueue to completion) latency 1797system.cpu1.itb.walker.walkCompletionTime::8192-16383 1349 75.70% 93.43% # Table walker service (enqueue to completion) latency 1798system.cpu1.itb.walker.walkCompletionTime::16384-24575 63 3.54% 96.97% # Table walker service (enqueue to completion) latency 1799system.cpu1.itb.walker.walkCompletionTime::24576-32767 25 1.40% 98.37% # Table walker service (enqueue to completion) latency 1800system.cpu1.itb.walker.walkCompletionTime::32768-40959 19 1.07% 99.44% # Table walker service (enqueue to completion) latency 1801system.cpu1.itb.walker.walkCompletionTime::40960-49151 3 0.17% 99.61% # Table walker service (enqueue to completion) latency 1802system.cpu1.itb.walker.walkCompletionTime::49152-57343 4 0.22% 99.83% # Table walker service (enqueue to completion) latency 1803system.cpu1.itb.walker.walkCompletionTime::57344-65535 2 0.11% 99.94% # Table walker service (enqueue to completion) latency 1804system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency 1805system.cpu1.itb.walker.walkCompletionTime::total 1782 # Table walker service (enqueue to completion) latency 1806system.cpu1.itb.walker.walksPending::samples 16752128416 # Table walker pending requests distribution 1807system.cpu1.itb.walker.walksPending::mean 0.862615 # Table walker pending requests distribution 1808system.cpu1.itb.walker.walksPending::stdev 0.344368 # Table walker pending requests distribution 1809system.cpu1.itb.walker.walksPending::0 2302152764 13.74% 13.74% # Table walker pending requests distribution 1810system.cpu1.itb.walker.walksPending::1 14449314652 86.25% 100.00% # Table walker pending requests distribution 1811system.cpu1.itb.walker.walksPending::2 661000 0.00% 100.00% # Table walker pending requests distribution 1812system.cpu1.itb.walker.walksPending::total 16752128416 # Table walker pending requests distribution 1813system.cpu1.itb.walker.walkPageSizes::4K 990 84.98% 84.98% # Table walker page sizes translated 1814system.cpu1.itb.walker.walkPageSizes::1M 175 15.02% 100.00% # Table walker page sizes translated 1815system.cpu1.itb.walker.walkPageSizes::total 1165 # Table walker page sizes translated 1816system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1817system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5994 # Table walker requests started/completed, data/inst 1818system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5994 # Table walker requests started/completed, data/inst 1819system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1820system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1165 # Table walker requests started/completed, data/inst 1821system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1165 # Table walker requests started/completed, data/inst 1822system.cpu1.itb.walker.walkRequestOrigin::total 7159 # Table walker requests started/completed, data/inst 1823system.cpu1.itb.inst_hits 8253439 # ITB inst hits 1824system.cpu1.itb.inst_misses 5994 # ITB inst misses 1825system.cpu1.itb.read_hits 0 # DTB read hits 1826system.cpu1.itb.read_misses 0 # DTB read misses 1827system.cpu1.itb.write_hits 0 # DTB write hits 1828system.cpu1.itb.write_misses 0 # DTB write misses 1829system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1830system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1831system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1832system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1833system.cpu1.itb.flush_entries 1194 # Number of entries that have been flushed from TLB	1833system.cpu1.itb.flush_entries 1130 # Number of entries that have been flushed from TLB
1834system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1835system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1836system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1837system.cpu1.itb.perms_faults 578 # Number of TLB faults due to permissions restrictions 1838system.cpu1.itb.read_accesses 0 # DTB read accesses 1839system.cpu1.itb.write_accesses 0 # DTB write accesses 1840system.cpu1.itb.inst_accesses 8259433 # ITB inst accesses 1841system.cpu1.itb.hits 8253439 # DTB hits 1842system.cpu1.itb.misses 5994 # DTB misses 1843system.cpu1.itb.accesses 8259433 # DTB accesses 1844system.cpu1.numPwrStateTransitions 5525 # Number of power state transitions 1845system.cpu1.pwrStateClkGateDist::samples 2763 # Distribution of time spent in the clock gated state 1846system.cpu1.pwrStateClkGateDist::mean 1016473602.620702 # Distribution of time spent in the clock gated state 1847system.cpu1.pwrStateClkGateDist::stdev 25821981878.711128 # Distribution of time spent in the clock gated state 1848system.cpu1.pwrStateClkGateDist::underflows 1969 71.26% 71.26% # Distribution of time spent in the clock gated state 1849system.cpu1.pwrStateClkGateDist::1000-5e+10 788 28.52% 99.78% # Distribution of time spent in the clock gated state 1850system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.86% # Distribution of time spent in the clock gated state 1851system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state 1852system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 1853system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 1854system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state 1855system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 1856system.cpu1.pwrStateClkGateDist::max_value 959984667908 # Distribution of time spent in the clock gated state 1857system.cpu1.pwrStateClkGateDist::total 2763 # Distribution of time spent in the clock gated state 1858system.cpu1.pwrStateResidencyTicks::ON 17443167459 # Cumulative time (in ticks) in various power states 1859system.cpu1.pwrStateResidencyTicks::CLK_GATED 2808516564041 # Cumulative time (in ticks) in various power states 1860system.cpu1.numCycles 34887121 # number of cpu cycles simulated 1861system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1862system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1863system.cpu1.fetch.icacheStallCycles 8560607 # Number of cycles fetch is stalled on an Icache miss 1864system.cpu1.fetch.Insts 24821804 # Number of instructions fetch has processed 1865system.cpu1.fetch.Branches 4689327 # Number of branches that fetch encountered 1866system.cpu1.fetch.predictedBranches 2662390 # Number of branches that fetch has predicted taken 1867system.cpu1.fetch.Cycles 24583766 # Number of cycles fetch has run and was not squashing or blocked 1868system.cpu1.fetch.SquashCycles 780426 # Number of cycles fetch has spent squashing 1869system.cpu1.fetch.TlbCycles 78816 # Number of cycles fetch has spent waiting for tlb 1870system.cpu1.fetch.MiscStallCycles 28892 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1871system.cpu1.fetch.PendingTrapStallCycles 168872 # Number of stall cycles due to pending traps 1872system.cpu1.fetch.PendingQuiesceStallCycles 301988 # Number of stall cycles due to pending quiesce instructions 1873system.cpu1.fetch.IcacheWaitRetryStallCycles 23027 # Number of stall cycles due to full MSHR 1874system.cpu1.fetch.CacheLines 8252257 # Number of cache lines fetched 1875system.cpu1.fetch.IcacheSquashes 107887 # Number of outstanding Icache misses that were squashed 1876system.cpu1.fetch.ItlbSquashes 2262 # Number of outstanding ITLB misses that were squashed 1877system.cpu1.fetch.rateDist::samples 34136181 # Number of instructions fetched each cycle (Total) 1878system.cpu1.fetch.rateDist::mean 0.885084 # Number of instructions fetched each cycle (Total) 1879system.cpu1.fetch.rateDist::stdev 1.219625 # Number of instructions fetched each cycle (Total) 1880system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1881system.cpu1.fetch.rateDist::0 20248194 59.32% 59.32% # Number of instructions fetched each cycle (Total) 1882system.cpu1.fetch.rateDist::1 4889749 14.32% 73.64% # Number of instructions fetched each cycle (Total) 1883system.cpu1.fetch.rateDist::2 1671087 4.90% 78.54% # Number of instructions fetched each cycle (Total) 1884system.cpu1.fetch.rateDist::3 7327151 21.46% 100.00% # Number of instructions fetched each cycle (Total) 1885system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1886system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1887system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1888system.cpu1.fetch.rateDist::total 34136181 # Number of instructions fetched each cycle (Total) 1889system.cpu1.fetch.branchRate 0.134414 # Number of branch fetches per cycle 1890system.cpu1.fetch.rate 0.711489 # Number of inst fetches per cycle 1891system.cpu1.decode.IdleCycles 7136711 # Number of cycles decode is idle 1892system.cpu1.decode.BlockedCycles 16890873 # Number of cycles decode is blocked 1893system.cpu1.decode.RunCycles 8747772 # Number of cycles decode is running 1894system.cpu1.decode.UnblockCycles 1097057 # Number of cycles decode is unblocking 1895system.cpu1.decode.SquashCycles 263768 # Number of cycles decode is squashing 1896system.cpu1.decode.BranchResolved 709532 # Number of times decode resolved a branch 1897system.cpu1.decode.BranchMispred 129045 # Number of times decode detected a branch misprediction 1898system.cpu1.decode.DecodedInsts 23428697 # Number of instructions handled by decode 1899system.cpu1.decode.SquashedInsts 1046505 # Number of squashed instructions handled by decode 1900system.cpu1.rename.SquashCycles 263768 # Number of cycles rename is squashing 1901system.cpu1.rename.IdleCycles 8558773 # Number of cycles rename is idle 1902system.cpu1.rename.BlockCycles 2377328 # Number of cycles rename is blocking 1903system.cpu1.rename.serializeStallCycles 11841982 # count of cycles rename stalled for serializing inst 1904system.cpu1.rename.RunCycles 8401624 # Number of cycles rename is running 1905system.cpu1.rename.UnblockCycles 2692706 # Number of cycles rename is unblocking 1906system.cpu1.rename.RenamedInsts 22261726 # Number of instructions processed by rename 1907system.cpu1.rename.SquashedInsts 187544 # Number of squashed instructions processed by rename 1908system.cpu1.rename.ROBFullEvents 264330 # Number of times rename has blocked due to ROB full 1909system.cpu1.rename.IQFullEvents 36982 # Number of times rename has blocked due to IQ full 1910system.cpu1.rename.LQFullEvents 15461 # Number of times rename has blocked due to LQ full 1911system.cpu1.rename.SQFullEvents 1675349 # Number of times rename has blocked due to SQ full 1912system.cpu1.rename.RenamedOperands 22265644 # Number of destination operands rename has renamed 1913system.cpu1.rename.RenameLookups 103648875 # Number of register rename lookups that rename has made 1914system.cpu1.rename.int_rename_lookups 25648399 # Number of integer rename lookups 1915system.cpu1.rename.fp_rename_lookups 1667 # Number of floating rename lookups 1916system.cpu1.rename.CommittedMaps 19867778 # Number of HB maps that are committed 1917system.cpu1.rename.UndoneMaps 2397866 # Number of HB maps that are undone due to squashing 1918system.cpu1.rename.serializingInsts 407377 # count of serializing insts renamed 1919system.cpu1.rename.tempSerializingInsts 334219 # count of temporary serializing insts renamed 1920system.cpu1.rename.skidInsts 2894111 # count of insts added to the skid buffer 1921system.cpu1.memDep0.insertedLoads 4447920 # Number of loads inserted to the mem dependence unit. 1922system.cpu1.memDep0.insertedStores 3797613 # Number of stores inserted to the mem dependence unit. 1923system.cpu1.memDep0.conflictingLoads 625649 # Number of conflicting loads. 1924system.cpu1.memDep0.conflictingStores 631175 # Number of conflicting stores. 1925system.cpu1.iq.iqInstsAdded 21446441 # Number of instructions added to the IQ (excludes non-spec) 1926system.cpu1.iq.iqNonSpecInstsAdded 559995 # Number of non-speculative instructions added to the IQ 1927system.cpu1.iq.iqInstsIssued 21251983 # Number of instructions issued 1928system.cpu1.iq.iqSquashedInstsIssued 91992 # Number of squashed instructions issued 1929system.cpu1.iq.iqSquashedInstsExamined 2044542 # Number of squashed instructions iterated over during squash; mainly for profiling 1930system.cpu1.iq.iqSquashedOperandsExamined 4726903 # Number of squashed operands that are examined and possibly removed from graph 1931system.cpu1.iq.iqSquashedNonSpecRemoved 43295 # Number of squashed non-spec instructions that were removed 1932system.cpu1.iq.issued_per_cycle::samples 34136181 # Number of insts issued each cycle 1933system.cpu1.iq.issued_per_cycle::mean 0.622565 # Number of insts issued each cycle 1934system.cpu1.iq.issued_per_cycle::stdev 0.949324 # Number of insts issued each cycle 1935system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1936system.cpu1.iq.issued_per_cycle::0 21624116 63.35% 63.35% # Number of insts issued each cycle 1937system.cpu1.iq.issued_per_cycle::1 6146372 18.01% 81.35% # Number of insts issued each cycle 1938system.cpu1.iq.issued_per_cycle::2 4248735 12.45% 93.80% # Number of insts issued each cycle 1939system.cpu1.iq.issued_per_cycle::3 1859698 5.45% 99.25% # Number of insts issued each cycle 1940system.cpu1.iq.issued_per_cycle::4 257253 0.75% 100.00% # Number of insts issued each cycle 1941system.cpu1.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle 1942system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1943system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1944system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1945system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1946system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1947system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 1948system.cpu1.iq.issued_per_cycle::total 34136181 # Number of insts issued each cycle 1949system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1950system.cpu1.iq.fu_full::IntAlu 1435935 29.89% 29.89% # attempts to use FU when none available 1951system.cpu1.iq.fu_full::IntMult 668 0.01% 29.90% # attempts to use FU when none available 1952system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.90% # attempts to use FU when none available 1953system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.90% # attempts to use FU when none available 1954system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.90% # attempts to use FU when none available 1955system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.90% # attempts to use FU when none available 1956system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.90% # attempts to use FU when none available 1957system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.90% # attempts to use FU when none available 1958system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.90% # attempts to use FU when none available 1959system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.90% # attempts to use FU when none available 1960system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.90% # attempts to use FU when none available 1961system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.90% # attempts to use FU when none available 1962system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.90% # attempts to use FU when none available 1963system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.90% # attempts to use FU when none available 1964system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.90% # attempts to use FU when none available 1965system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.90% # attempts to use FU when none available 1966system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.90% # attempts to use FU when none available 1967system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.90% # attempts to use FU when none available 1968system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.90% # attempts to use FU when none available 1969system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.90% # attempts to use FU when none available 1970system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.90% # attempts to use FU when none available 1971system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.90% # attempts to use FU when none available 1972system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.90% # attempts to use FU when none available 1973system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.90% # attempts to use FU when none available 1974system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.90% # attempts to use FU when none available 1975system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.90% # attempts to use FU when none available 1976system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.90% # attempts to use FU when none available 1977system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.90% # attempts to use FU when none available 1978system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.90% # attempts to use FU when none available 1979system.cpu1.iq.fu_full::MemRead 1614233 33.60% 63.50% # attempts to use FU when none available 1980system.cpu1.iq.fu_full::MemWrite 1753849 36.50% 100.00% # attempts to use FU when none available 1981system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1982system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1983system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued 1984system.cpu1.iq.FU_type_0::IntAlu 13143313 61.85% 61.85% # Type of FU issued 1985system.cpu1.iq.FU_type_0::IntMult 28154 0.13% 61.98% # Type of FU issued 1986system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.98% # Type of FU issued 1987system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.98% # Type of FU issued 1988system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.98% # Type of FU issued 1989system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.98% # Type of FU issued 1990system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.98% # Type of FU issued 1991system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.98% # Type of FU issued 1992system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.98% # Type of FU issued 1993system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.98% # Type of FU issued 1994system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.98% # Type of FU issued 1995system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.98% # Type of FU issued 1996system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.98% # Type of FU issued 1997system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.98% # Type of FU issued 1998system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.98% # Type of FU issued 1999system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.98% # Type of FU issued 2000system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.98% # Type of FU issued 2001system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.98% # Type of FU issued 2002system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.98% # Type of FU issued 2003system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.98% # Type of FU issued 2004system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.98% # Type of FU issued 2005system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.98% # Type of FU issued 2006system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.98% # Type of FU issued 2007system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.98% # Type of FU issued 2008system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.98% # Type of FU issued 2009system.cpu1.iq.FU_type_0::SimdFloatMisc 3291 0.02% 61.99% # Type of FU issued 2010system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.99% # Type of FU issued 2011system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.99% # Type of FU issued 2012system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.99% # Type of FU issued 2013system.cpu1.iq.FU_type_0::MemRead 4401591 20.71% 82.70% # Type of FU issued 2014system.cpu1.iq.FU_type_0::MemWrite 3675568 17.30% 100.00% # Type of FU issued 2015system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2016system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2017system.cpu1.iq.FU_type_0::total 21251983 # Type of FU issued 2018system.cpu1.iq.rate 0.609164 # Inst issue rate 2019system.cpu1.iq.fu_busy_cnt 4804685 # FU busy when requested 2020system.cpu1.iq.fu_busy_rate 0.226082 # FU busy rate (busy events/executed inst) 2021system.cpu1.iq.int_inst_queue_reads 81530573 # Number of integer instruction queue reads 2022system.cpu1.iq.int_inst_queue_writes 24059081 # Number of integer instruction queue writes 2023system.cpu1.iq.int_inst_queue_wakeup_accesses 20789563 # Number of integer instruction queue wakeup accesses 2024system.cpu1.iq.fp_inst_queue_reads 6251 # Number of floating instruction queue reads 2025system.cpu1.iq.fp_inst_queue_writes 2056 # Number of floating instruction queue writes 2026system.cpu1.iq.fp_inst_queue_wakeup_accesses 1789 # Number of floating instruction queue wakeup accesses 2027system.cpu1.iq.int_alu_accesses 26052476 # Number of integer alu accesses 2028system.cpu1.iq.fp_alu_accesses 4126 # Number of floating point alu accesses 2029system.cpu1.iew.lsq.thread0.forwLoads 87608 # Number of loads that had data forwarded from stores 2030system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2031system.cpu1.iew.lsq.thread0.squashedLoads 411817 # Number of loads squashed 2032system.cpu1.iew.lsq.thread0.ignoredResponses 594 # Number of memory responses ignored because the instruction is squashed 2033system.cpu1.iew.lsq.thread0.memOrderViolation 10183 # Number of memory ordering violations 2034system.cpu1.iew.lsq.thread0.squashedStores 255647 # Number of stores squashed 2035system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2036system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2037system.cpu1.iew.lsq.thread0.rescheduledLoads 40342 # Number of loads that were rescheduled 2038system.cpu1.iew.lsq.thread0.cacheBlocked 77877 # Number of times an access to memory failed due to the cache being blocked 2039system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2040system.cpu1.iew.iewSquashCycles 263768 # Number of cycles IEW is squashing 2041system.cpu1.iew.iewBlockCycles 542908 # Number of cycles IEW is blocking 2042system.cpu1.iew.iewUnblockCycles 100291 # Number of cycles IEW is unblocking 2043system.cpu1.iew.iewDispatchedInsts 22047493 # Number of instructions dispatched to IQ 2044system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 2045system.cpu1.iew.iewDispLoadInsts 4447920 # Number of dispatched load instructions 2046system.cpu1.iew.iewDispStoreInsts 3797613 # Number of dispatched store instructions 2047system.cpu1.iew.iewDispNonSpecInsts 296998 # Number of dispatched non-speculative instructions 2048system.cpu1.iew.iewIQFullEvents 7633 # Number of times the IQ has become full, causing a stall 2049system.cpu1.iew.iewLSQFullEvents 86238 # Number of times the LSQ has become full, causing a stall 2050system.cpu1.iew.memOrderViolationEvents 10183 # Number of memory order violations 2051system.cpu1.iew.predictedTakenIncorrect 34861 # Number of branches that were predicted taken incorrectly 2052system.cpu1.iew.predictedNotTakenIncorrect 119032 # Number of branches that were predicted not taken incorrectly 2053system.cpu1.iew.branchMispredicts 153893 # Number of branch mispredicts detected at execute 2054system.cpu1.iew.iewExecutedInsts 21020629 # Number of executed instructions 2055system.cpu1.iew.iewExecLoadInsts 4306114 # Number of load instructions executed 2056system.cpu1.iew.iewExecSquashedInsts 209967 # Number of squashed instructions skipped in execute 2057system.cpu1.iew.exec_swp 0 # number of swp insts executed 2058system.cpu1.iew.exec_nop 41057 # number of nop insts executed 2059system.cpu1.iew.exec_refs 7931495 # number of memory reference insts executed 2060system.cpu1.iew.exec_branches 3060021 # Number of branches executed 2061system.cpu1.iew.exec_stores 3625381 # Number of stores executed 2062system.cpu1.iew.exec_rate 0.602533 # Inst execution rate 2063system.cpu1.iew.wb_sent 20889464 # cumulative count of insts sent to commit 2064system.cpu1.iew.wb_count 20791352 # cumulative count of insts written-back 2065system.cpu1.iew.wb_producers 10424214 # num instructions producing a value 2066system.cpu1.iew.wb_consumers 16342751 # num instructions consuming a value 2067system.cpu1.iew.wb_rate 0.595961 # insts written-back per cycle 2068system.cpu1.iew.wb_fanout 0.637849 # average fanout of values written-back 2069system.cpu1.commit.commitSquashedInsts 1830942 # The number of squashed insts skipped by commit 2070system.cpu1.commit.commitNonSpecStalls 516700 # The number of times commit has been forced to stall to communicate backwards 2071system.cpu1.commit.branchMispredicts 142734 # The number of times a branch was mispredicted 2072system.cpu1.commit.committed_per_cycle::samples 33726190 # Number of insts commited each cycle 2073system.cpu1.commit.committed_per_cycle::mean 0.592855 # Number of insts commited each cycle 2074system.cpu1.commit.committed_per_cycle::stdev 1.351829 # Number of insts commited each cycle 2075system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2076system.cpu1.commit.committed_per_cycle::0 24181138 71.70% 71.70% # Number of insts commited each cycle 2077system.cpu1.commit.committed_per_cycle::1 5602280 16.61% 88.31% # Number of insts commited each cycle 2078system.cpu1.commit.committed_per_cycle::2 1689893 5.01% 93.32% # Number of insts commited each cycle 2079system.cpu1.commit.committed_per_cycle::3 666101 1.98% 95.30% # Number of insts commited each cycle 2080system.cpu1.commit.committed_per_cycle::4 523339 1.55% 96.85% # Number of insts commited each cycle 2081system.cpu1.commit.committed_per_cycle::5 342031 1.01% 97.86% # Number of insts commited each cycle 2082system.cpu1.commit.committed_per_cycle::6 220744 0.65% 98.52% # Number of insts commited each cycle 2083system.cpu1.commit.committed_per_cycle::7 118908 0.35% 98.87% # Number of insts commited each cycle 2084system.cpu1.commit.committed_per_cycle::8 381756 1.13% 100.00% # Number of insts commited each cycle 2085system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2086system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2087system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2088system.cpu1.commit.committed_per_cycle::total 33726190 # Number of insts commited each cycle 2089system.cpu1.commit.committedInsts 16334743 # Number of instructions committed 2090system.cpu1.commit.committedOps 19994748 # Number of ops (including micro ops) committed 2091system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 2092system.cpu1.commit.refs 7578069 # Number of memory references committed 2093system.cpu1.commit.loads 4036103 # Number of loads committed 2094system.cpu1.commit.membars 208295 # Number of memory barriers committed 2095system.cpu1.commit.branches 2905369 # Number of branches committed 2096system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. 2097system.cpu1.commit.int_insts 17763800 # Number of committed integer instructions. 2098system.cpu1.commit.function_calls 462325 # Number of function calls committed. 2099system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 2100system.cpu1.commit.op_class_0::IntAlu 12386323 61.95% 61.95% # Class of committed instruction 2101system.cpu1.commit.op_class_0::IntMult 27065 0.14% 62.08% # Class of committed instruction 2102system.cpu1.commit.op_class_0::IntDiv 0 0.00% 62.08% # Class of committed instruction 2103system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 62.08% # Class of committed instruction 2104system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 62.08% # Class of committed instruction 2105system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 62.08% # Class of committed instruction 2106system.cpu1.commit.op_class_0::FloatMult 0 0.00% 62.08% # Class of committed instruction 2107system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 62.08% # Class of committed instruction 2108system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 62.08% # Class of committed instruction 2109system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 62.08% # Class of committed instruction 2110system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 62.08% # Class of committed instruction 2111system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 62.08% # Class of committed instruction 2112system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 62.08% # Class of committed instruction 2113system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 62.08% # Class of committed instruction 2114system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 62.08% # Class of committed instruction 2115system.cpu1.commit.op_class_0::SimdMult 0 0.00% 62.08% # Class of committed instruction 2116system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 62.08% # Class of committed instruction 2117system.cpu1.commit.op_class_0::SimdShift 0 0.00% 62.08% # Class of committed instruction 2118system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 62.08% # Class of committed instruction 2119system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 62.08% # Class of committed instruction 2120system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 62.08% # Class of committed instruction 2121system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 62.08% # Class of committed instruction 2122system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 62.08% # Class of committed instruction 2123system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 62.08% # Class of committed instruction 2124system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 62.08% # Class of committed instruction 2125system.cpu1.commit.op_class_0::SimdFloatMisc 3291 0.02% 62.10% # Class of committed instruction 2126system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 62.10% # Class of committed instruction 2127system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.10% # Class of committed instruction 2128system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.10% # Class of committed instruction 2129system.cpu1.commit.op_class_0::MemRead 4036103 20.19% 82.29% # Class of committed instruction 2130system.cpu1.commit.op_class_0::MemWrite 3541966 17.71% 100.00% # Class of committed instruction 2131system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2132system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2133system.cpu1.commit.op_class_0::total 19994748 # Class of committed instruction 2134system.cpu1.commit.bw_lim_events 381756 # number cycles where commit BW limit reached 2135system.cpu1.rob.rob_reads 54190677 # The number of ROB reads 2136system.cpu1.rob.rob_writes 44052640 # The number of ROB writes 2137system.cpu1.timesIdled 55343 # Number of times that the entire CPU went into an idle state and unscheduled itself 2138system.cpu1.idleCycles 750940 # Total number of cycles that the CPU has spent unscheduled due to idling 2139system.cpu1.quiesceCycles 5616474700 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2140system.cpu1.committedInsts 16301888 # Number of Instructions Simulated 2141system.cpu1.committedOps 19961893 # Number of Ops (including micro ops) Simulated 2142system.cpu1.cpi 2.140066 # CPI: Cycles Per Instruction 2143system.cpu1.cpi_total 2.140066 # CPI: Total CPI of All Threads 2144system.cpu1.ipc 0.467275 # IPC: Instructions Per Cycle 2145system.cpu1.ipc_total 0.467275 # IPC: Total IPC of All Threads 2146system.cpu1.int_regfile_reads 23580432 # number of integer regfile reads 2147system.cpu1.int_regfile_writes 13478394 # number of integer regfile writes 2148system.cpu1.fp_regfile_reads 1401 # number of floating regfile reads 2149system.cpu1.fp_regfile_writes 516 # number of floating regfile writes 2150system.cpu1.cc_regfile_reads 75464831 # number of cc regfile reads 2151system.cpu1.cc_regfile_writes 6816973 # number of cc regfile writes 2152system.cpu1.misc_regfile_reads 66091366 # number of misc regfile reads 2153system.cpu1.misc_regfile_writes 387254 # number of misc regfile writes 2154system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2155system.cpu1.dcache.tags.replacements 189214 # number of replacements 2156system.cpu1.dcache.tags.tagsinuse 472.223119 # Cycle average of tags in use 2157system.cpu1.dcache.tags.total_refs 6799121 # Total number of references to valid blocks. 2158system.cpu1.dcache.tags.sampled_refs 189549 # Sample count of references to valid blocks. 2159system.cpu1.dcache.tags.avg_refs 35.869991 # Average number of references to valid blocks. 2160system.cpu1.dcache.tags.warmup_cycle 103707030000 # Cycle when the warmup percentage was hit. 2161system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.223119 # Average occupied blocks per requestor 2162system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922311 # Average percentage of cache occupancy 2163system.cpu1.dcache.tags.occ_percent::total 0.922311 # Average percentage of cache occupancy 2164system.cpu1.dcache.tags.occ_task_id_blocks::1024 335 # Occupied blocks per task id 2165system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id 2166system.cpu1.dcache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id 2167system.cpu1.dcache.tags.occ_task_id_percent::1024 0.654297 # Percentage of cache occupancy per task id 2168system.cpu1.dcache.tags.tag_accesses 15096738 # Number of tag accesses 2169system.cpu1.dcache.tags.data_accesses 15096738 # Number of data accesses 2170system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2171system.cpu1.dcache.ReadReq_hits::cpu1.data 3630827 # number of ReadReq hits 2172system.cpu1.dcache.ReadReq_hits::total 3630827 # number of ReadReq hits 2173system.cpu1.dcache.WriteReq_hits::cpu1.data 2915447 # number of WriteReq hits 2174system.cpu1.dcache.WriteReq_hits::total 2915447 # number of WriteReq hits 2175system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48893 # number of SoftPFReq hits 2176system.cpu1.dcache.SoftPFReq_hits::total 48893 # number of SoftPFReq hits 2177system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78128 # number of LoadLockedReq hits 2178system.cpu1.dcache.LoadLockedReq_hits::total 78128 # number of LoadLockedReq hits 2179system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70537 # number of StoreCondReq hits 2180system.cpu1.dcache.StoreCondReq_hits::total 70537 # number of StoreCondReq hits 2181system.cpu1.dcache.demand_hits::cpu1.data 6546274 # number of demand (read+write) hits 2182system.cpu1.dcache.demand_hits::total 6546274 # number of demand (read+write) hits 2183system.cpu1.dcache.overall_hits::cpu1.data 6595167 # number of overall hits 2184system.cpu1.dcache.overall_hits::total 6595167 # number of overall hits 2185system.cpu1.dcache.ReadReq_misses::cpu1.data 215923 # number of ReadReq misses 2186system.cpu1.dcache.ReadReq_misses::total 215923 # number of ReadReq misses 2187system.cpu1.dcache.WriteReq_misses::cpu1.data 399880 # number of WriteReq misses 2188system.cpu1.dcache.WriteReq_misses::total 399880 # number of WriteReq misses 2189system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30250 # number of SoftPFReq misses 2190system.cpu1.dcache.SoftPFReq_misses::total 30250 # number of SoftPFReq misses 2191system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18610 # number of LoadLockedReq misses 2192system.cpu1.dcache.LoadLockedReq_misses::total 18610 # number of LoadLockedReq misses 2193system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23458 # number of StoreCondReq misses 2194system.cpu1.dcache.StoreCondReq_misses::total 23458 # number of StoreCondReq misses 2195system.cpu1.dcache.demand_misses::cpu1.data 615803 # number of demand (read+write) misses 2196system.cpu1.dcache.demand_misses::total 615803 # number of demand (read+write) misses 2197system.cpu1.dcache.overall_misses::cpu1.data 646053 # number of overall misses 2198system.cpu1.dcache.overall_misses::total 646053 # number of overall misses 2199system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3499498000 # number of ReadReq miss cycles 2200system.cpu1.dcache.ReadReq_miss_latency::total 3499498000 # number of ReadReq miss cycles 2201system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10163021954 # number of WriteReq miss cycles 2202system.cpu1.dcache.WriteReq_miss_latency::total 10163021954 # number of WriteReq miss cycles 2203system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 366635500 # number of LoadLockedReq miss cycles 2204system.cpu1.dcache.LoadLockedReq_miss_latency::total 366635500 # number of LoadLockedReq miss cycles 2205system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 572131000 # number of StoreCondReq miss cycles 2206system.cpu1.dcache.StoreCondReq_miss_latency::total 572131000 # number of StoreCondReq miss cycles 2207system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1270000 # number of StoreCondFailReq miss cycles 2208system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1270000 # number of StoreCondFailReq miss cycles 2209system.cpu1.dcache.demand_miss_latency::cpu1.data 13662519954 # number of demand (read+write) miss cycles 2210system.cpu1.dcache.demand_miss_latency::total 13662519954 # number of demand (read+write) miss cycles 2211system.cpu1.dcache.overall_miss_latency::cpu1.data 13662519954 # number of overall miss cycles 2212system.cpu1.dcache.overall_miss_latency::total 13662519954 # number of overall miss cycles 2213system.cpu1.dcache.ReadReq_accesses::cpu1.data 3846750 # number of ReadReq accesses(hits+misses) 2214system.cpu1.dcache.ReadReq_accesses::total 3846750 # number of ReadReq accesses(hits+misses) 2215system.cpu1.dcache.WriteReq_accesses::cpu1.data 3315327 # number of WriteReq accesses(hits+misses) 2216system.cpu1.dcache.WriteReq_accesses::total 3315327 # number of WriteReq accesses(hits+misses) 2217system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79143 # number of SoftPFReq accesses(hits+misses) 2218system.cpu1.dcache.SoftPFReq_accesses::total 79143 # number of SoftPFReq accesses(hits+misses) 2219system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96738 # number of LoadLockedReq accesses(hits+misses) 2220system.cpu1.dcache.LoadLockedReq_accesses::total 96738 # number of LoadLockedReq accesses(hits+misses) 2221system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93995 # number of StoreCondReq accesses(hits+misses) 2222system.cpu1.dcache.StoreCondReq_accesses::total 93995 # number of StoreCondReq accesses(hits+misses) 2223system.cpu1.dcache.demand_accesses::cpu1.data 7162077 # number of demand (read+write) accesses 2224system.cpu1.dcache.demand_accesses::total 7162077 # number of demand (read+write) accesses 2225system.cpu1.dcache.overall_accesses::cpu1.data 7241220 # number of overall (read+write) accesses 2226system.cpu1.dcache.overall_accesses::total 7241220 # number of overall (read+write) accesses 2227system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.056131 # miss rate for ReadReq accesses 2228system.cpu1.dcache.ReadReq_miss_rate::total 0.056131 # miss rate for ReadReq accesses 2229system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.120616 # miss rate for WriteReq accesses 2230system.cpu1.dcache.WriteReq_miss_rate::total 0.120616 # miss rate for WriteReq accesses 2231system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382220 # miss rate for SoftPFReq accesses 2232system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382220 # miss rate for SoftPFReq accesses 2233system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.192375 # miss rate for LoadLockedReq accesses 2234system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.192375 # miss rate for LoadLockedReq accesses 2235system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249566 # miss rate for StoreCondReq accesses 2236system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249566 # miss rate for StoreCondReq accesses 2237system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085981 # miss rate for demand accesses 2238system.cpu1.dcache.demand_miss_rate::total 0.085981 # miss rate for demand accesses 2239system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089219 # miss rate for overall accesses 2240system.cpu1.dcache.overall_miss_rate::total 0.089219 # miss rate for overall accesses 2241system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16207.157181 # average ReadReq miss latency 2242system.cpu1.dcache.ReadReq_avg_miss_latency::total 16207.157181 # average ReadReq miss latency 2243system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25415.179439 # average WriteReq miss latency 2244system.cpu1.dcache.WriteReq_avg_miss_latency::total 25415.179439 # average WriteReq miss latency 2245system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19700.994089 # average LoadLockedReq miss latency 2246system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19700.994089 # average LoadLockedReq miss latency 2247system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24389.589905 # average StoreCondReq miss latency 2248system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24389.589905 # average StoreCondReq miss latency 2249system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2250system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2251system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22186.510871 # average overall miss latency 2252system.cpu1.dcache.demand_avg_miss_latency::total 22186.510871 # average overall miss latency 2253system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21147.676667 # average overall miss latency 2254system.cpu1.dcache.overall_avg_miss_latency::total 21147.676667 # average overall miss latency 2255system.cpu1.dcache.blocked_cycles::no_mshrs 397 # number of cycles access was blocked 2256system.cpu1.dcache.blocked_cycles::no_targets 1522509 # number of cycles access was blocked 2257system.cpu1.dcache.blocked::no_mshrs 39 # number of cycles access was blocked 2258system.cpu1.dcache.blocked::no_targets 40277 # number of cycles access was blocked 2259system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10.179487 # average number of cycles each access was blocked 2260system.cpu1.dcache.avg_blocked_cycles::no_targets 37.800953 # average number of cycles each access was blocked 2261system.cpu1.dcache.writebacks::writebacks 189214 # number of writebacks 2262system.cpu1.dcache.writebacks::total 189214 # number of writebacks 2263system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79118 # number of ReadReq MSHR hits 2264system.cpu1.dcache.ReadReq_mshr_hits::total 79118 # number of ReadReq MSHR hits 2265system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 308913 # number of WriteReq MSHR hits 2266system.cpu1.dcache.WriteReq_mshr_hits::total 308913 # number of WriteReq MSHR hits 2267system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13245 # number of LoadLockedReq MSHR hits 2268system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13245 # number of LoadLockedReq MSHR hits 2269system.cpu1.dcache.demand_mshr_hits::cpu1.data 388031 # number of demand (read+write) MSHR hits 2270system.cpu1.dcache.demand_mshr_hits::total 388031 # number of demand (read+write) MSHR hits 2271system.cpu1.dcache.overall_mshr_hits::cpu1.data 388031 # number of overall MSHR hits 2272system.cpu1.dcache.overall_mshr_hits::total 388031 # number of overall MSHR hits 2273system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 136805 # number of ReadReq MSHR misses 2274system.cpu1.dcache.ReadReq_mshr_misses::total 136805 # number of ReadReq MSHR misses 2275system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90967 # number of WriteReq MSHR misses 2276system.cpu1.dcache.WriteReq_mshr_misses::total 90967 # number of WriteReq MSHR misses 2277system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28906 # number of SoftPFReq MSHR misses 2278system.cpu1.dcache.SoftPFReq_mshr_misses::total 28906 # number of SoftPFReq MSHR misses 2279system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5365 # number of LoadLockedReq MSHR misses 2280system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5365 # number of LoadLockedReq MSHR misses 2281system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23458 # number of StoreCondReq MSHR misses 2282system.cpu1.dcache.StoreCondReq_mshr_misses::total 23458 # number of StoreCondReq MSHR misses 2283system.cpu1.dcache.demand_mshr_misses::cpu1.data 227772 # number of demand (read+write) MSHR misses 2284system.cpu1.dcache.demand_mshr_misses::total 227772 # number of demand (read+write) MSHR misses 2285system.cpu1.dcache.overall_mshr_misses::cpu1.data 256678 # number of overall MSHR misses 2286system.cpu1.dcache.overall_mshr_misses::total 256678 # number of overall MSHR misses 2287system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3078 # number of ReadReq MSHR uncacheable 2288system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3078 # number of ReadReq MSHR uncacheable 2289system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2435 # number of WriteReq MSHR uncacheable 2290system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2435 # number of WriteReq MSHR uncacheable 2291system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5513 # number of overall MSHR uncacheable misses 2292system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5513 # number of overall MSHR uncacheable misses 2293system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1918091000 # number of ReadReq MSHR miss cycles 2294system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1918091000 # number of ReadReq MSHR miss cycles 2295system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2479606465 # number of WriteReq MSHR miss cycles 2296system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2479606465 # number of WriteReq MSHR miss cycles 2297system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 495967500 # number of SoftPFReq MSHR miss cycles 2298system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 495967500 # number of SoftPFReq MSHR miss cycles 2299system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 96498000 # number of LoadLockedReq MSHR miss cycles 2300system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 96498000 # number of LoadLockedReq MSHR miss cycles 2301system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 548698000 # number of StoreCondReq MSHR miss cycles 2302system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 548698000 # number of StoreCondReq MSHR miss cycles 2303system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1245000 # number of StoreCondFailReq MSHR miss cycles 2304system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1245000 # number of StoreCondFailReq MSHR miss cycles 2305system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4397697465 # number of demand (read+write) MSHR miss cycles 2306system.cpu1.dcache.demand_mshr_miss_latency::total 4397697465 # number of demand (read+write) MSHR miss cycles 2307system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4893664965 # number of overall MSHR miss cycles 2308system.cpu1.dcache.overall_mshr_miss_latency::total 4893664965 # number of overall MSHR miss cycles 2309system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 441985000 # number of ReadReq MSHR uncacheable cycles 2310system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 441985000 # number of ReadReq MSHR uncacheable cycles 2311system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 441985000 # number of overall MSHR uncacheable cycles 2312system.cpu1.dcache.overall_mshr_uncacheable_latency::total 441985000 # number of overall MSHR uncacheable cycles 2313system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035564 # mshr miss rate for ReadReq accesses 2314system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035564 # mshr miss rate for ReadReq accesses 2315system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027438 # mshr miss rate for WriteReq accesses 2316system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027438 # mshr miss rate for WriteReq accesses 2317system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.365238 # mshr miss rate for SoftPFReq accesses 2318system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.365238 # mshr miss rate for SoftPFReq accesses 2319system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055459 # mshr miss rate for LoadLockedReq accesses 2320system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055459 # mshr miss rate for LoadLockedReq accesses 2321system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249566 # mshr miss rate for StoreCondReq accesses 2322system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249566 # mshr miss rate for StoreCondReq accesses 2323system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031803 # mshr miss rate for demand accesses 2324system.cpu1.dcache.demand_mshr_miss_rate::total 0.031803 # mshr miss rate for demand accesses 2325system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035447 # mshr miss rate for overall accesses 2326system.cpu1.dcache.overall_mshr_miss_rate::total 0.035447 # mshr miss rate for overall accesses 2327system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14020.620591 # average ReadReq mshr miss latency 2328system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14020.620591 # average ReadReq mshr miss latency 2329system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27258.307573 # average WriteReq mshr miss latency 2330system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27258.307573 # average WriteReq mshr miss latency 2331system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17157.942988 # average SoftPFReq mshr miss latency 2332system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17157.942988 # average SoftPFReq mshr miss latency 2333system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17986.579683 # average LoadLockedReq mshr miss latency 2334system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17986.579683 # average LoadLockedReq mshr miss latency 2335system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23390.655640 # average StoreCondReq mshr miss latency 2336system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23390.655640 # average StoreCondReq mshr miss latency 2337system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2338system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2339system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19307.454231 # average overall mshr miss latency 2340system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19307.454231 # average overall mshr miss latency 2341system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19065.385288 # average overall mshr miss latency 2342system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19065.385288 # average overall mshr miss latency 2343system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143594.866797 # average ReadReq mshr uncacheable latency 2344system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143594.866797 # average ReadReq mshr uncacheable latency 2345system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80171.413024 # average overall mshr uncacheable latency 2346system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80171.413024 # average overall mshr uncacheable latency 2347system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2348system.cpu1.icache.tags.replacements 585593 # number of replacements 2349system.cpu1.icache.tags.tagsinuse 499.448296 # Cycle average of tags in use 2350system.cpu1.icache.tags.total_refs 7643805 # Total number of references to valid blocks. 2351system.cpu1.icache.tags.sampled_refs 586105 # Sample count of references to valid blocks. 2352system.cpu1.icache.tags.avg_refs 13.041699 # Average number of references to valid blocks. 2353system.cpu1.icache.tags.warmup_cycle 79061349000 # Cycle when the warmup percentage was hit. 2354system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.448296 # Average occupied blocks per requestor 2355system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975485 # Average percentage of cache occupancy 2356system.cpu1.icache.tags.occ_percent::total 0.975485 # Average percentage of cache occupancy 2357system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2358system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id 2359system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id 2360system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2361system.cpu1.icache.tags.tag_accesses 17090093 # Number of tag accesses 2362system.cpu1.icache.tags.data_accesses 17090093 # Number of data accesses 2363system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2364system.cpu1.icache.ReadReq_hits::cpu1.inst 7643805 # number of ReadReq hits 2365system.cpu1.icache.ReadReq_hits::total 7643805 # number of ReadReq hits 2366system.cpu1.icache.demand_hits::cpu1.inst 7643805 # number of demand (read+write) hits 2367system.cpu1.icache.demand_hits::total 7643805 # number of demand (read+write) hits 2368system.cpu1.icache.overall_hits::cpu1.inst 7643805 # number of overall hits 2369system.cpu1.icache.overall_hits::total 7643805 # number of overall hits 2370system.cpu1.icache.ReadReq_misses::cpu1.inst 608184 # number of ReadReq misses 2371system.cpu1.icache.ReadReq_misses::total 608184 # number of ReadReq misses 2372system.cpu1.icache.demand_misses::cpu1.inst 608184 # number of demand (read+write) misses 2373system.cpu1.icache.demand_misses::total 608184 # number of demand (read+write) misses 2374system.cpu1.icache.overall_misses::cpu1.inst 608184 # number of overall misses 2375system.cpu1.icache.overall_misses::total 608184 # number of overall misses 2376system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5475305711 # number of ReadReq miss cycles 2377system.cpu1.icache.ReadReq_miss_latency::total 5475305711 # number of ReadReq miss cycles 2378system.cpu1.icache.demand_miss_latency::cpu1.inst 5475305711 # number of demand (read+write) miss cycles 2379system.cpu1.icache.demand_miss_latency::total 5475305711 # number of demand (read+write) miss cycles 2380system.cpu1.icache.overall_miss_latency::cpu1.inst 5475305711 # number of overall miss cycles 2381system.cpu1.icache.overall_miss_latency::total 5475305711 # number of overall miss cycles 2382system.cpu1.icache.ReadReq_accesses::cpu1.inst 8251989 # number of ReadReq accesses(hits+misses) 2383system.cpu1.icache.ReadReq_accesses::total 8251989 # number of ReadReq accesses(hits+misses) 2384system.cpu1.icache.demand_accesses::cpu1.inst 8251989 # number of demand (read+write) accesses 2385system.cpu1.icache.demand_accesses::total 8251989 # number of demand (read+write) accesses 2386system.cpu1.icache.overall_accesses::cpu1.inst 8251989 # number of overall (read+write) accesses 2387system.cpu1.icache.overall_accesses::total 8251989 # number of overall (read+write) accesses 2388system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073702 # miss rate for ReadReq accesses 2389system.cpu1.icache.ReadReq_miss_rate::total 0.073702 # miss rate for ReadReq accesses 2390system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073702 # miss rate for demand accesses 2391system.cpu1.icache.demand_miss_rate::total 0.073702 # miss rate for demand accesses 2392system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073702 # miss rate for overall accesses 2393system.cpu1.icache.overall_miss_rate::total 0.073702 # miss rate for overall accesses 2394system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9002.712520 # average ReadReq miss latency 2395system.cpu1.icache.ReadReq_avg_miss_latency::total 9002.712520 # average ReadReq miss latency 2396system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9002.712520 # average overall miss latency 2397system.cpu1.icache.demand_avg_miss_latency::total 9002.712520 # average overall miss latency 2398system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9002.712520 # average overall miss latency 2399system.cpu1.icache.overall_avg_miss_latency::total 9002.712520 # average overall miss latency 2400system.cpu1.icache.blocked_cycles::no_mshrs 487413 # number of cycles access was blocked 2401system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2402system.cpu1.icache.blocked::no_mshrs 41153 # number of cycles access was blocked 2403system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 2404system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.843924 # average number of cycles each access was blocked 2405system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2406system.cpu1.icache.writebacks::writebacks 585593 # number of writebacks 2407system.cpu1.icache.writebacks::total 585593 # number of writebacks 2408system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22069 # number of ReadReq MSHR hits 2409system.cpu1.icache.ReadReq_mshr_hits::total 22069 # number of ReadReq MSHR hits 2410system.cpu1.icache.demand_mshr_hits::cpu1.inst 22069 # number of demand (read+write) MSHR hits 2411system.cpu1.icache.demand_mshr_hits::total 22069 # number of demand (read+write) MSHR hits 2412system.cpu1.icache.overall_mshr_hits::cpu1.inst 22069 # number of overall MSHR hits 2413system.cpu1.icache.overall_mshr_hits::total 22069 # number of overall MSHR hits 2414system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 586115 # number of ReadReq MSHR misses 2415system.cpu1.icache.ReadReq_mshr_misses::total 586115 # number of ReadReq MSHR misses 2416system.cpu1.icache.demand_mshr_misses::cpu1.inst 586115 # number of demand (read+write) MSHR misses 2417system.cpu1.icache.demand_mshr_misses::total 586115 # number of demand (read+write) MSHR misses 2418system.cpu1.icache.overall_mshr_misses::cpu1.inst 586115 # number of overall MSHR misses 2419system.cpu1.icache.overall_mshr_misses::total 586115 # number of overall MSHR misses 2420system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable 2421system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable 2422system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses 2423system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses 2424system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5018314097 # number of ReadReq MSHR miss cycles 2425system.cpu1.icache.ReadReq_mshr_miss_latency::total 5018314097 # number of ReadReq MSHR miss cycles 2426system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5018314097 # number of demand (read+write) MSHR miss cycles 2427system.cpu1.icache.demand_mshr_miss_latency::total 5018314097 # number of demand (read+write) MSHR miss cycles 2428system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5018314097 # number of overall MSHR miss cycles 2429system.cpu1.icache.overall_mshr_miss_latency::total 5018314097 # number of overall MSHR miss cycles 2430system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9229000 # number of ReadReq MSHR uncacheable cycles 2431system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9229000 # number of ReadReq MSHR uncacheable cycles 2432system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9229000 # number of overall MSHR uncacheable cycles 2433system.cpu1.icache.overall_mshr_uncacheable_latency::total 9229000 # number of overall MSHR uncacheable cycles 2434system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071027 # mshr miss rate for ReadReq accesses 2435system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071027 # mshr miss rate for ReadReq accesses 2436system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071027 # mshr miss rate for demand accesses 2437system.cpu1.icache.demand_mshr_miss_rate::total 0.071027 # mshr miss rate for demand accesses 2438system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071027 # mshr miss rate for overall accesses 2439system.cpu1.icache.overall_mshr_miss_rate::total 0.071027 # mshr miss rate for overall accesses 2440system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8561.995678 # average ReadReq mshr miss latency 2441system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8561.995678 # average ReadReq mshr miss latency 2442system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8561.995678 # average overall mshr miss latency 2443system.cpu1.icache.demand_avg_mshr_miss_latency::total 8561.995678 # average overall mshr miss latency 2444system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8561.995678 # average overall mshr miss latency 2445system.cpu1.icache.overall_avg_mshr_miss_latency::total 8561.995678 # average overall mshr miss latency 2446system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90480.392157 # average ReadReq mshr uncacheable latency 2447system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90480.392157 # average ReadReq mshr uncacheable latency 2448system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90480.392157 # average overall mshr uncacheable latency 2449system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90480.392157 # average overall mshr uncacheable latency 2450system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2451system.cpu1.l2cache.prefetcher.num_hwpf_issued 204984 # number of hwpf issued 2452system.cpu1.l2cache.prefetcher.pfIdentified 205710 # number of prefetch candidates identified 2453system.cpu1.l2cache.prefetcher.pfBufferHit 651 # number of redundant prefetches already in prefetch queue 2454system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2455system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2456system.cpu1.l2cache.prefetcher.pfSpanPage 59802 # number of prefetches not generated due to page crossing 2457system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2458system.cpu1.l2cache.tags.replacements 51951 # number of replacements 2459system.cpu1.l2cache.tags.tagsinuse 15270.218898 # Cycle average of tags in use 2460system.cpu1.l2cache.tags.total_refs 1330892 # Total number of references to valid blocks. 2461system.cpu1.l2cache.tags.sampled_refs 66549 # Sample count of references to valid blocks. 2462system.cpu1.l2cache.tags.avg_refs 19.998678 # Average number of references to valid blocks. 2463system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2464system.cpu1.l2cache.tags.occ_blocks::writebacks 14780.960176 # Average occupied blocks per requestor 2465system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 15.872611 # Average occupied blocks per requestor 2466system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.970486 # Average occupied blocks per requestor 2467system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 470.415625 # Average occupied blocks per requestor 2468system.cpu1.l2cache.tags.occ_percent::writebacks 0.902158 # Average percentage of cache occupancy 2469system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000969 # Average percentage of cache occupancy 2470system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000181 # Average percentage of cache occupancy 2471system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.028712 # Average percentage of cache occupancy 2472system.cpu1.l2cache.tags.occ_percent::total 0.932020 # Average percentage of cache occupancy 2473system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1023 # Occupied blocks per task id 2474system.cpu1.l2cache.tags.occ_task_id_blocks::1023 34 # Occupied blocks per task id 2475system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13541 # Occupied blocks per task id 2476system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 11 # Occupied blocks per task id 2477system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 870 # Occupied blocks per task id 2478system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 142 # Occupied blocks per task id 2479system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id 2480system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id 2481system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id 2482system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id 2483system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8705 # Occupied blocks per task id 2484system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4388 # Occupied blocks per task id 2485system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.062439 # Percentage of cache occupancy per task id 2486system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002075 # Percentage of cache occupancy per task id 2487system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.826477 # Percentage of cache occupancy per task id 2488system.cpu1.l2cache.tags.tag_accesses 26699823 # Number of tag accesses 2489system.cpu1.l2cache.tags.data_accesses 26699823 # Number of data accesses 2490system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2491system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16755 # number of ReadReq hits 2492system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6229 # number of ReadReq hits 2493system.cpu1.l2cache.ReadReq_hits::total 22984 # number of ReadReq hits 2494system.cpu1.l2cache.WritebackDirty_hits::writebacks 115107 # number of WritebackDirty hits 2495system.cpu1.l2cache.WritebackDirty_hits::total 115107 # number of WritebackDirty hits 2496system.cpu1.l2cache.WritebackClean_hits::writebacks 647294 # number of WritebackClean hits 2497system.cpu1.l2cache.WritebackClean_hits::total 647294 # number of WritebackClean hits 2498system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27150 # number of ReadExReq hits 2499system.cpu1.l2cache.ReadExReq_hits::total 27150 # number of ReadExReq hits 2500system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 570057 # number of ReadCleanReq hits 2501system.cpu1.l2cache.ReadCleanReq_hits::total 570057 # number of ReadCleanReq hits 2502system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 101740 # number of ReadSharedReq hits 2503system.cpu1.l2cache.ReadSharedReq_hits::total 101740 # number of ReadSharedReq hits 2504system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16755 # number of demand (read+write) hits 2505system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6229 # number of demand (read+write) hits 2506system.cpu1.l2cache.demand_hits::cpu1.inst 570057 # number of demand (read+write) hits 2507system.cpu1.l2cache.demand_hits::cpu1.data 128890 # number of demand (read+write) hits 2508system.cpu1.l2cache.demand_hits::total 721931 # number of demand (read+write) hits 2509system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16755 # number of overall hits 2510system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6229 # number of overall hits 2511system.cpu1.l2cache.overall_hits::cpu1.inst 570057 # number of overall hits 2512system.cpu1.l2cache.overall_hits::cpu1.data 128890 # number of overall hits 2513system.cpu1.l2cache.overall_hits::total 721931 # number of overall hits 2514system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 448 # number of ReadReq misses 2515system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 243 # number of ReadReq misses 2516system.cpu1.l2cache.ReadReq_misses::total 691 # number of ReadReq misses 2517system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29892 # number of UpgradeReq misses 2518system.cpu1.l2cache.UpgradeReq_misses::total 29892 # number of UpgradeReq misses 2519system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23453 # number of SCUpgradeReq misses 2520system.cpu1.l2cache.SCUpgradeReq_misses::total 23453 # number of SCUpgradeReq misses 2521system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses 2522system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 2523system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34596 # number of ReadExReq misses 2524system.cpu1.l2cache.ReadExReq_misses::total 34596 # number of ReadExReq misses 2525system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 16047 # number of ReadCleanReq misses 2526system.cpu1.l2cache.ReadCleanReq_misses::total 16047 # number of ReadCleanReq misses 2527system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69320 # number of ReadSharedReq misses 2528system.cpu1.l2cache.ReadSharedReq_misses::total 69320 # number of ReadSharedReq misses 2529system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 448 # number of demand (read+write) misses 2530system.cpu1.l2cache.demand_misses::cpu1.itb.walker 243 # number of demand (read+write) misses 2531system.cpu1.l2cache.demand_misses::cpu1.inst 16047 # number of demand (read+write) misses 2532system.cpu1.l2cache.demand_misses::cpu1.data 103916 # number of demand (read+write) misses 2533system.cpu1.l2cache.demand_misses::total 120654 # number of demand (read+write) misses 2534system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 448 # number of overall misses 2535system.cpu1.l2cache.overall_misses::cpu1.itb.walker 243 # number of overall misses 2536system.cpu1.l2cache.overall_misses::cpu1.inst 16047 # number of overall misses 2537system.cpu1.l2cache.overall_misses::cpu1.data 103916 # number of overall misses 2538system.cpu1.l2cache.overall_misses::total 120654 # number of overall misses 2539system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9860500 # number of ReadReq miss cycles 2540system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5063000 # number of ReadReq miss cycles 2541system.cpu1.l2cache.ReadReq_miss_latency::total 14923500 # number of ReadReq miss cycles 2542system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 63584500 # number of UpgradeReq miss cycles 2543system.cpu1.l2cache.UpgradeReq_miss_latency::total 63584500 # number of UpgradeReq miss cycles 2544system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 34923000 # number of SCUpgradeReq miss cycles 2545system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 34923000 # number of SCUpgradeReq miss cycles 2546system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1206498 # number of SCUpgradeFailReq miss cycles 2547system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1206498 # number of SCUpgradeFailReq miss cycles 2548system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1459821998 # number of ReadExReq miss cycles 2549system.cpu1.l2cache.ReadExReq_miss_latency::total 1459821998 # number of ReadExReq miss cycles 2550system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 658205000 # number of ReadCleanReq miss cycles 2551system.cpu1.l2cache.ReadCleanReq_miss_latency::total 658205000 # number of ReadCleanReq miss cycles 2552system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1571289999 # number of ReadSharedReq miss cycles 2553system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1571289999 # number of ReadSharedReq miss cycles 2554system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9860500 # number of demand (read+write) miss cycles 2555system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5063000 # number of demand (read+write) miss cycles 2556system.cpu1.l2cache.demand_miss_latency::cpu1.inst 658205000 # number of demand (read+write) miss cycles 2557system.cpu1.l2cache.demand_miss_latency::cpu1.data 3031111997 # number of demand (read+write) miss cycles 2558system.cpu1.l2cache.demand_miss_latency::total 3704240497 # number of demand (read+write) miss cycles 2559system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9860500 # number of overall miss cycles 2560system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5063000 # number of overall miss cycles 2561system.cpu1.l2cache.overall_miss_latency::cpu1.inst 658205000 # number of overall miss cycles 2562system.cpu1.l2cache.overall_miss_latency::cpu1.data 3031111997 # number of overall miss cycles 2563system.cpu1.l2cache.overall_miss_latency::total 3704240497 # number of overall miss cycles 2564system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17203 # number of ReadReq accesses(hits+misses) 2565system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 6472 # number of ReadReq accesses(hits+misses) 2566system.cpu1.l2cache.ReadReq_accesses::total 23675 # number of ReadReq accesses(hits+misses) 2567system.cpu1.l2cache.WritebackDirty_accesses::writebacks 115107 # number of WritebackDirty accesses(hits+misses) 2568system.cpu1.l2cache.WritebackDirty_accesses::total 115107 # number of WritebackDirty accesses(hits+misses) 2569system.cpu1.l2cache.WritebackClean_accesses::writebacks 647294 # number of WritebackClean accesses(hits+misses) 2570system.cpu1.l2cache.WritebackClean_accesses::total 647294 # number of WritebackClean accesses(hits+misses) 2571system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29892 # number of UpgradeReq accesses(hits+misses) 2572system.cpu1.l2cache.UpgradeReq_accesses::total 29892 # number of UpgradeReq accesses(hits+misses) 2573system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23453 # number of SCUpgradeReq accesses(hits+misses) 2574system.cpu1.l2cache.SCUpgradeReq_accesses::total 23453 # number of SCUpgradeReq accesses(hits+misses) 2575system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 2576system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 2577system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61746 # number of ReadExReq accesses(hits+misses) 2578system.cpu1.l2cache.ReadExReq_accesses::total 61746 # number of ReadExReq accesses(hits+misses) 2579system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 586104 # number of ReadCleanReq accesses(hits+misses) 2580system.cpu1.l2cache.ReadCleanReq_accesses::total 586104 # number of ReadCleanReq accesses(hits+misses) 2581system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 171060 # number of ReadSharedReq accesses(hits+misses) 2582system.cpu1.l2cache.ReadSharedReq_accesses::total 171060 # number of ReadSharedReq accesses(hits+misses) 2583system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17203 # number of demand (read+write) accesses 2584system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 6472 # number of demand (read+write) accesses 2585system.cpu1.l2cache.demand_accesses::cpu1.inst 586104 # number of demand (read+write) accesses 2586system.cpu1.l2cache.demand_accesses::cpu1.data 232806 # number of demand (read+write) accesses 2587system.cpu1.l2cache.demand_accesses::total 842585 # number of demand (read+write) accesses 2588system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17203 # number of overall (read+write) accesses 2589system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 6472 # number of overall (read+write) accesses 2590system.cpu1.l2cache.overall_accesses::cpu1.inst 586104 # number of overall (read+write) accesses 2591system.cpu1.l2cache.overall_accesses::cpu1.data 232806 # number of overall (read+write) accesses 2592system.cpu1.l2cache.overall_accesses::total 842585 # number of overall (read+write) accesses 2593system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026042 # miss rate for ReadReq accesses 2594system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.037546 # miss rate for ReadReq accesses 2595system.cpu1.l2cache.ReadReq_miss_rate::total 0.029187 # miss rate for ReadReq accesses 2596system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2597system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2598system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2599system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2600system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2601system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2602system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.560295 # miss rate for ReadExReq accesses 2603system.cpu1.l2cache.ReadExReq_miss_rate::total 0.560295 # miss rate for ReadExReq accesses 2604system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.027379 # miss rate for ReadCleanReq accesses 2605system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.027379 # miss rate for ReadCleanReq accesses 2606system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.405238 # miss rate for ReadSharedReq accesses 2607system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.405238 # miss rate for ReadSharedReq accesses 2608system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.026042 # miss rate for demand accesses 2609system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.037546 # miss rate for demand accesses 2610system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.027379 # miss rate for demand accesses 2611system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.446363 # miss rate for demand accesses 2612system.cpu1.l2cache.demand_miss_rate::total 0.143195 # miss rate for demand accesses 2613system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.026042 # miss rate for overall accesses 2614system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.037546 # miss rate for overall accesses 2615system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.027379 # miss rate for overall accesses 2616system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.446363 # miss rate for overall accesses 2617system.cpu1.l2cache.overall_miss_rate::total 0.143195 # miss rate for overall accesses 2618system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22010.044643 # average ReadReq miss latency 2619system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20835.390947 # average ReadReq miss latency 2620system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21596.960926 # average ReadReq miss latency 2621system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2127.141041 # average UpgradeReq miss latency 2622system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2127.141041 # average UpgradeReq miss latency 2623system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1489.063233 # average SCUpgradeReq miss latency 2624system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1489.063233 # average SCUpgradeReq miss latency 2625system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 241299.600000 # average SCUpgradeFailReq miss latency 2626system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 241299.600000 # average SCUpgradeFailReq miss latency 2627system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42196.265406 # average ReadExReq miss latency 2628system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42196.265406 # average ReadExReq miss latency 2629system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 41017.324110 # average ReadCleanReq miss latency 2630system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 41017.324110 # average ReadCleanReq miss latency 2631system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22667.195600 # average ReadSharedReq miss latency 2632system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22667.195600 # average ReadSharedReq miss latency 2633system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22010.044643 # average overall miss latency 2634system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20835.390947 # average overall miss latency 2635system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 41017.324110 # average overall miss latency 2636system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29168.867133 # average overall miss latency 2637system.cpu1.l2cache.demand_avg_miss_latency::total 30701.348459 # average overall miss latency 2638system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22010.044643 # average overall miss latency 2639system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20835.390947 # average overall miss latency 2640system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 41017.324110 # average overall miss latency 2641system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29168.867133 # average overall miss latency 2642system.cpu1.l2cache.overall_avg_miss_latency::total 30701.348459 # average overall miss latency 2643system.cpu1.l2cache.blocked_cycles::no_mshrs 235 # number of cycles access was blocked 2644system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2645system.cpu1.l2cache.blocked::no_mshrs 9 # number of cycles access was blocked 2646system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2647system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 26.111111 # average number of cycles each access was blocked 2648system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2649system.cpu1.l2cache.unused_prefetches 821 # number of HardPF blocks evicted w/o reference 2650system.cpu1.l2cache.writebacks::writebacks 37285 # number of writebacks 2651system.cpu1.l2cache.writebacks::total 37285 # number of writebacks 2652system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 573 # number of ReadExReq MSHR hits 2653system.cpu1.l2cache.ReadExReq_mshr_hits::total 573 # number of ReadExReq MSHR hits 2654system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits 2655system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits 2656system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 74 # number of ReadSharedReq MSHR hits 2657system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 74 # number of ReadSharedReq MSHR hits 2658system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits 2659system.cpu1.l2cache.demand_mshr_hits::cpu1.data 647 # number of demand (read+write) MSHR hits 2660system.cpu1.l2cache.demand_mshr_hits::total 651 # number of demand (read+write) MSHR hits 2661system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits 2662system.cpu1.l2cache.overall_mshr_hits::cpu1.data 647 # number of overall MSHR hits 2663system.cpu1.l2cache.overall_mshr_hits::total 651 # number of overall MSHR hits 2664system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 448 # number of ReadReq MSHR misses 2665system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 243 # number of ReadReq MSHR misses 2666system.cpu1.l2cache.ReadReq_mshr_misses::total 691 # number of ReadReq MSHR misses 2667system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 27204 # number of HardPFReq MSHR misses 2668system.cpu1.l2cache.HardPFReq_mshr_misses::total 27204 # number of HardPFReq MSHR misses 2669system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29892 # number of UpgradeReq MSHR misses 2670system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29892 # number of UpgradeReq MSHR misses 2671system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23453 # number of SCUpgradeReq MSHR misses 2672system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23453 # number of SCUpgradeReq MSHR misses 2673system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses 2674system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 2675system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34023 # number of ReadExReq MSHR misses 2676system.cpu1.l2cache.ReadExReq_mshr_misses::total 34023 # number of ReadExReq MSHR misses 2677system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 16043 # number of ReadCleanReq MSHR misses 2678system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 16043 # number of ReadCleanReq MSHR misses 2679system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69246 # number of ReadSharedReq MSHR misses 2680system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69246 # number of ReadSharedReq MSHR misses 2681system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 448 # number of demand (read+write) MSHR misses 2682system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 243 # number of demand (read+write) MSHR misses 2683system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 16043 # number of demand (read+write) MSHR misses 2684system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103269 # number of demand (read+write) MSHR misses 2685system.cpu1.l2cache.demand_mshr_misses::total 120003 # number of demand (read+write) MSHR misses 2686system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 448 # number of overall MSHR misses 2687system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 243 # number of overall MSHR misses 2688system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 16043 # number of overall MSHR misses 2689system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103269 # number of overall MSHR misses 2690system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 27204 # number of overall MSHR misses 2691system.cpu1.l2cache.overall_mshr_misses::total 147207 # number of overall MSHR misses 2692system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable 2693system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3078 # number of ReadReq MSHR uncacheable 2694system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3180 # number of ReadReq MSHR uncacheable 2695system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2435 # number of WriteReq MSHR uncacheable 2696system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2435 # number of WriteReq MSHR uncacheable 2697system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses 2698system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5513 # number of overall MSHR uncacheable misses 2699system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5615 # number of overall MSHR uncacheable misses 2700system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7172500 # number of ReadReq MSHR miss cycles 2701system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3605000 # number of ReadReq MSHR miss cycles 2702system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10777500 # number of ReadReq MSHR miss cycles 2703system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1221222561 # number of HardPFReq MSHR miss cycles 2704system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1221222561 # number of HardPFReq MSHR miss cycles 2705system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 499462500 # number of UpgradeReq MSHR miss cycles 2706system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 499462500 # number of UpgradeReq MSHR miss cycles 2707system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 372532500 # number of SCUpgradeReq MSHR miss cycles 2708system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 372532500 # number of SCUpgradeReq MSHR miss cycles 2709system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1056498 # number of SCUpgradeFailReq MSHR miss cycles 2710system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1056498 # number of SCUpgradeFailReq MSHR miss cycles 2711system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1184971500 # number of ReadExReq MSHR miss cycles 2712system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1184971500 # number of ReadExReq MSHR miss cycles 2713system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 561881000 # number of ReadCleanReq MSHR miss cycles 2714system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 561881000 # number of ReadCleanReq MSHR miss cycles 2715system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1153728499 # number of ReadSharedReq MSHR miss cycles 2716system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1153728499 # number of ReadSharedReq MSHR miss cycles 2717system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7172500 # number of demand (read+write) MSHR miss cycles 2718system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3605000 # number of demand (read+write) MSHR miss cycles 2719system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 561881000 # number of demand (read+write) MSHR miss cycles 2720system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2338699999 # number of demand (read+write) MSHR miss cycles 2721system.cpu1.l2cache.demand_mshr_miss_latency::total 2911358499 # number of demand (read+write) MSHR miss cycles 2722system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7172500 # number of overall MSHR miss cycles 2723system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3605000 # number of overall MSHR miss cycles 2724system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 561881000 # number of overall MSHR miss cycles 2725system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2338699999 # number of overall MSHR miss cycles 2726system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1221222561 # number of overall MSHR miss cycles 2727system.cpu1.l2cache.overall_mshr_miss_latency::total 4132581060 # number of overall MSHR miss cycles 2728system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8464000 # number of ReadReq MSHR uncacheable cycles 2729system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 417313000 # number of ReadReq MSHR uncacheable cycles 2730system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 425777000 # number of ReadReq MSHR uncacheable cycles 2731system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8464000 # number of overall MSHR uncacheable cycles 2732system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 417313000 # number of overall MSHR uncacheable cycles 2733system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 425777000 # number of overall MSHR uncacheable cycles 2734system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026042 # mshr miss rate for ReadReq accesses 2735system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.037546 # mshr miss rate for ReadReq accesses 2736system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029187 # mshr miss rate for ReadReq accesses 2737system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2738system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2739system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2740system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2741system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2742system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2743system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2744system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2745system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.551015 # mshr miss rate for ReadExReq accesses 2746system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.551015 # mshr miss rate for ReadExReq accesses 2747system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027372 # mshr miss rate for ReadCleanReq accesses 2748system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.027372 # mshr miss rate for ReadCleanReq accesses 2749system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.404805 # mshr miss rate for ReadSharedReq accesses 2750system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.404805 # mshr miss rate for ReadSharedReq accesses 2751system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026042 # mshr miss rate for demand accesses 2752system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.037546 # mshr miss rate for demand accesses 2753system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.027372 # mshr miss rate for demand accesses 2754system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443584 # mshr miss rate for demand accesses 2755system.cpu1.l2cache.demand_mshr_miss_rate::total 0.142422 # mshr miss rate for demand accesses 2756system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026042 # mshr miss rate for overall accesses 2757system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.037546 # mshr miss rate for overall accesses 2758system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.027372 # mshr miss rate for overall accesses 2759system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443584 # mshr miss rate for overall accesses 2760system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2761system.cpu1.l2cache.overall_mshr_miss_rate::total 0.174709 # mshr miss rate for overall accesses 2762system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16010.044643 # average ReadReq mshr miss latency 2763system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14835.390947 # average ReadReq mshr miss latency 2764system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15596.960926 # average ReadReq mshr miss latency 2765system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44891.286612 # average HardPFReq mshr miss latency 2766system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44891.286612 # average HardPFReq mshr miss latency 2767system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16708.902047 # average UpgradeReq mshr miss latency 2768system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16708.902047 # average UpgradeReq mshr miss latency 2769system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15884.215239 # average SCUpgradeReq mshr miss latency 2770system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15884.215239 # average SCUpgradeReq mshr miss latency 2771system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 211299.600000 # average SCUpgradeFailReq mshr miss latency 2772system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 211299.600000 # average SCUpgradeFailReq mshr miss latency 2773system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34828.542457 # average ReadExReq mshr miss latency 2774system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34828.542457 # average ReadExReq mshr miss latency 2775system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 35023.437013 # average ReadCleanReq mshr miss latency 2776system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 35023.437013 # average ReadCleanReq mshr miss latency 2777system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16661.301721 # average ReadSharedReq mshr miss latency 2778system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16661.301721 # average ReadSharedReq mshr miss latency 2779system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16010.044643 # average overall mshr miss latency 2780system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14835.390947 # average overall mshr miss latency 2781system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 35023.437013 # average overall mshr miss latency 2782system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22646.680020 # average overall mshr miss latency 2783system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24260.714307 # average overall mshr miss latency 2784system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16010.044643 # average overall mshr miss latency 2785system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14835.390947 # average overall mshr miss latency 2786system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 35023.437013 # average overall mshr miss latency 2787system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22646.680020 # average overall mshr miss latency 2788system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44891.286612 # average overall mshr miss latency 2789system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28073.264587 # average overall mshr miss latency 2790system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82980.392157 # average ReadReq mshr uncacheable latency 2791system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135579.272255 # average ReadReq mshr uncacheable latency 2792system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133892.138365 # average ReadReq mshr uncacheable latency 2793system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82980.392157 # average overall mshr uncacheable latency 2794system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75696.172683 # average overall mshr uncacheable latency 2795system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75828.495102 # average overall mshr uncacheable latency 2796system.cpu1.toL2Bus.snoop_filter.tot_requests 1657712 # Total number of requests made to the snoop filter. 2797system.cpu1.toL2Bus.snoop_filter.hit_single_requests 838800 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2798system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12415 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2799system.cpu1.toL2Bus.snoop_filter.tot_snoops 183176 # Total number of snoops made to the snoop filter. 2800system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 180762 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2801system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2414 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2802system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2803system.cpu1.toL2Bus.trans_dist::ReadReq 31669 # Transaction distribution 2804system.cpu1.toL2Bus.trans_dist::ReadResp 826741 # Transaction distribution 2805system.cpu1.toL2Bus.trans_dist::WriteReq 2435 # Transaction distribution 2806system.cpu1.toL2Bus.trans_dist::WriteResp 2435 # Transaction distribution 2807system.cpu1.toL2Bus.trans_dist::WritebackDirty 153550 # Transaction distribution 2808system.cpu1.toL2Bus.trans_dist::WritebackClean 659699 # Transaction distribution 2809system.cpu1.toL2Bus.trans_dist::CleanEvict 108887 # Transaction distribution 2810system.cpu1.toL2Bus.trans_dist::HardPFReq 33537 # Transaction distribution 2811system.cpu1.toL2Bus.trans_dist::UpgradeReq 71200 # Transaction distribution 2812system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41639 # Transaction distribution 2813system.cpu1.toL2Bus.trans_dist::UpgradeResp 86222 # Transaction distribution 2814system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution 2815system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution 2816system.cpu1.toL2Bus.trans_dist::ReadExReq 68548 # Transaction distribution 2817system.cpu1.toL2Bus.trans_dist::ReadExResp 66385 # Transaction distribution 2818system.cpu1.toL2Bus.trans_dist::ReadCleanReq 586115 # Transaction distribution 2819system.cpu1.toL2Bus.trans_dist::ReadSharedReq 251518 # Transaction distribution 2820system.cpu1.toL2Bus.trans_dist::InvalidateReq 256 # Transaction distribution 2821system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1758016 # Packet count per connected master and slave (bytes) 2822system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 847991 # Packet count per connected master and slave (bytes) 2823system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14492 # Packet count per connected master and slave (bytes) 2824system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37672 # Packet count per connected master and slave (bytes) 2825system.cpu1.toL2Bus.pkt_count::total 2658171 # Packet count per connected master and slave (bytes) 2826system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 74990240 # Cumulative packet size per connected master and slave (bytes) 2827system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29751886 # Cumulative packet size per connected master and slave (bytes) 2828system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25888 # Cumulative packet size per connected master and slave (bytes) 2829system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 68812 # Cumulative packet size per connected master and slave (bytes) 2830system.cpu1.toL2Bus.pkt_size::total 104836826 # Cumulative packet size per connected master and slave (bytes) 2831system.cpu1.toL2Bus.snoops 408149 # Total snoops (count) 2832system.cpu1.toL2Bus.snoop_fanout::samples 1234265 # Request fanout histogram 2833system.cpu1.toL2Bus.snoop_fanout::mean 0.169046 # Request fanout histogram 2834system.cpu1.toL2Bus.snoop_fanout::stdev 0.379975 # Request fanout histogram 2835system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2836system.cpu1.toL2Bus.snoop_fanout::0 1028032 83.29% 83.29% # Request fanout histogram 2837system.cpu1.toL2Bus.snoop_fanout::1 203819 16.51% 99.80% # Request fanout histogram 2838system.cpu1.toL2Bus.snoop_fanout::2 2414 0.20% 100.00% # Request fanout histogram 2839system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2840system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2841system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2842system.cpu1.toL2Bus.snoop_fanout::total 1234265 # Request fanout histogram 2843system.cpu1.toL2Bus.reqLayer0.occupancy 1616622989 # Layer occupancy (ticks) 2844system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2845system.cpu1.toL2Bus.snoopLayer0.occupancy 80296887 # Layer occupancy (ticks) 2846system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2847system.cpu1.toL2Bus.respLayer0.occupancy 879411723 # Layer occupancy (ticks) 2848system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2849system.cpu1.toL2Bus.respLayer1.occupancy 381445015 # Layer occupancy (ticks) 2850system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2851system.cpu1.toL2Bus.respLayer2.occupancy 8027984 # Layer occupancy (ticks) 2852system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2853system.cpu1.toL2Bus.respLayer3.occupancy 20485966 # Layer occupancy (ticks) 2854system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2855system.iobus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2856system.iobus.trans_dist::ReadReq 31012 # Transaction distribution 2857system.iobus.trans_dist::ReadResp 31012 # Transaction distribution 2858system.iobus.trans_dist::WriteReq 59421 # Transaction distribution 2859system.iobus.trans_dist::WriteResp 59421 # Transaction distribution 2860system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) 2861system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2862system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2863system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2864system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2865system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2866system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2867system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2868system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2869system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2870system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2871system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2872system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2873system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2874system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2875system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2876system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2877system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2878system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2879system.iobus.pkt_count_system.bridge.master::total 107914 # Packet count per connected master and slave (bytes) 2880system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 2881system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 2882system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) 2883system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes) 2884system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2885system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2886system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2887system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2888system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2889system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2890system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2891system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2892system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2893system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2894system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2895system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2896system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2897system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2898system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2899system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2900system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2901system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2902system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) 2903system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 2904system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 2905system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes) 2906system.iobus.reqLayer0.occupancy 40382501 # Layer occupancy (ticks) 2907system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2908system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) 2909system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2910system.iobus.reqLayer2.occupancy 327500 # Layer occupancy (ticks) 2911system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2912system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks) 2913system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2914system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks) 2915system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2916system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks) 2917system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2918system.iobus.reqLayer8.occupancy 582000 # Layer occupancy (ticks) 2919system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2920system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks) 2921system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2922system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) 2923system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2924system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) 2925system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2926system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) 2927system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2928system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks) 2929system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2930system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) 2931system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2932system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 2933system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2934system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2935system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2936system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2937system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2938system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) 2939system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2940system.iobus.reqLayer23.occupancy 6099000 # Layer occupancy (ticks) 2941system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2942system.iobus.reqLayer24.occupancy 33797500 # Layer occupancy (ticks) 2943system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2944system.iobus.reqLayer25.occupancy 187673606 # Layer occupancy (ticks) 2945system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2946system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) 2947system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2948system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) 2949system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2950system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2951system.iocache.tags.replacements 36458 # number of replacements 2952system.iocache.tags.tagsinuse 14.555465 # Cycle average of tags in use 2953system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2954system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. 2955system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2956system.iocache.tags.warmup_cycle 255128019000 # Cycle when the warmup percentage was hit. 2957system.iocache.tags.occ_blocks::realview.ide 14.555465 # Average occupied blocks per requestor 2958system.iocache.tags.occ_percent::realview.ide 0.909717 # Average percentage of cache occupancy 2959system.iocache.tags.occ_percent::total 0.909717 # Average percentage of cache occupancy 2960system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2961system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2962system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2963system.iocache.tags.tag_accesses 328284 # Number of tag accesses 2964system.iocache.tags.data_accesses 328284 # Number of data accesses 2965system.iocache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2966system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 2967system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 2968system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2969system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2970system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 2971system.iocache.demand_misses::total 36476 # number of demand (read+write) misses 2972system.iocache.overall_misses::realview.ide 36476 # number of overall misses 2973system.iocache.overall_misses::total 36476 # number of overall misses 2974system.iocache.ReadReq_miss_latency::realview.ide 32586377 # number of ReadReq miss cycles 2975system.iocache.ReadReq_miss_latency::total 32586377 # number of ReadReq miss cycles 2976system.iocache.WriteLineReq_miss_latency::realview.ide 4303595229 # number of WriteLineReq miss cycles 2977system.iocache.WriteLineReq_miss_latency::total 4303595229 # number of WriteLineReq miss cycles 2978system.iocache.demand_miss_latency::realview.ide 4336181606 # number of demand (read+write) miss cycles 2979system.iocache.demand_miss_latency::total 4336181606 # number of demand (read+write) miss cycles 2980system.iocache.overall_miss_latency::realview.ide 4336181606 # number of overall miss cycles 2981system.iocache.overall_miss_latency::total 4336181606 # number of overall miss cycles 2982system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 2983system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 2984system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2985system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2986system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses 2987system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses 2988system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses 2989system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses 2990system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2991system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2992system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2993system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2994system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2995system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2996system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2997system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2998system.iocache.ReadReq_avg_miss_latency::realview.ide 129311.019841 # average ReadReq miss latency 2999system.iocache.ReadReq_avg_miss_latency::total 129311.019841 # average ReadReq miss latency 3000system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118805.080306 # average WriteLineReq miss latency 3001system.iocache.WriteLineReq_avg_miss_latency::total 118805.080306 # average WriteLineReq miss latency 3002system.iocache.demand_avg_miss_latency::realview.ide 118877.662189 # average overall miss latency 3003system.iocache.demand_avg_miss_latency::total 118877.662189 # average overall miss latency 3004system.iocache.overall_avg_miss_latency::realview.ide 118877.662189 # average overall miss latency 3005system.iocache.overall_avg_miss_latency::total 118877.662189 # average overall miss latency 3006system.iocache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked 3007system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3008system.iocache.blocked::no_mshrs 5 # number of cycles access was blocked 3009system.iocache.blocked::no_targets 0 # number of cycles access was blocked 3010system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked 3011system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3012system.iocache.writebacks::writebacks 36206 # number of writebacks 3013system.iocache.writebacks::total 36206 # number of writebacks 3014system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses 3015system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses 3016system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 3017system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 3018system.iocache.demand_mshr_misses::realview.ide 36476 # number of demand (read+write) MSHR misses 3019system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses 3020system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses 3021system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses 3022system.iocache.ReadReq_mshr_miss_latency::realview.ide 19986377 # number of ReadReq MSHR miss cycles 3023system.iocache.ReadReq_mshr_miss_latency::total 19986377 # number of ReadReq MSHR miss cycles 3024system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2490041664 # number of WriteLineReq MSHR miss cycles 3025system.iocache.WriteLineReq_mshr_miss_latency::total 2490041664 # number of WriteLineReq MSHR miss cycles 3026system.iocache.demand_mshr_miss_latency::realview.ide 2510028041 # number of demand (read+write) MSHR miss cycles 3027system.iocache.demand_mshr_miss_latency::total 2510028041 # number of demand (read+write) MSHR miss cycles 3028system.iocache.overall_mshr_miss_latency::realview.ide 2510028041 # number of overall MSHR miss cycles 3029system.iocache.overall_mshr_miss_latency::total 2510028041 # number of overall MSHR miss cycles 3030system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3031system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3032system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 3033system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 3034system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3035system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3036system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3037system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 3038system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79311.019841 # average ReadReq mshr miss latency 3039system.iocache.ReadReq_avg_mshr_miss_latency::total 79311.019841 # average ReadReq mshr miss latency 3040system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68740.107774 # average WriteLineReq mshr miss latency 3041system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68740.107774 # average WriteLineReq mshr miss latency 3042system.iocache.demand_avg_mshr_miss_latency::realview.ide 68813.138529 # average overall mshr miss latency 3043system.iocache.demand_avg_mshr_miss_latency::total 68813.138529 # average overall mshr miss latency 3044system.iocache.overall_avg_mshr_miss_latency::realview.ide 68813.138529 # average overall mshr miss latency 3045system.iocache.overall_avg_mshr_miss_latency::total 68813.138529 # average overall mshr miss latency 3046system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3047system.l2c.tags.replacements 132778 # number of replacements 3048system.l2c.tags.tagsinuse 63203.828730 # Cycle average of tags in use 3049system.l2c.tags.total_refs 444088 # Total number of references to valid blocks. 3050system.l2c.tags.sampled_refs 196669 # Sample count of references to valid blocks. 3051system.l2c.tags.avg_refs 2.258048 # Average number of references to valid blocks. 3052system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3053system.l2c.tags.occ_blocks::writebacks 13685.490361 # Average occupied blocks per requestor 3054system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.358726 # Average occupied blocks per requestor 3055system.l2c.tags.occ_blocks::cpu0.itb.walker 1.065836 # Average occupied blocks per requestor 3056system.l2c.tags.occ_blocks::cpu0.inst 8064.380543 # Average occupied blocks per requestor 3057system.l2c.tags.occ_blocks::cpu0.data 2772.729395 # Average occupied blocks per requestor 3058system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33768.581689 # Average occupied blocks per requestor 3059system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.679196 # Average occupied blocks per requestor 3060system.l2c.tags.occ_blocks::cpu1.itb.walker 0.910017 # Average occupied blocks per requestor 3061system.l2c.tags.occ_blocks::cpu1.inst 1783.108864 # Average occupied blocks per requestor 3062system.l2c.tags.occ_blocks::cpu1.data 674.072360 # Average occupied blocks per requestor 3063system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2431.451744 # Average occupied blocks per requestor 3064system.l2c.tags.occ_percent::writebacks 0.208824 # Average percentage of cache occupancy 3065system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000250 # Average percentage of cache occupancy 3066system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy 3067system.l2c.tags.occ_percent::cpu0.inst 0.123053 # Average percentage of cache occupancy 3068system.l2c.tags.occ_percent::cpu0.data 0.042308 # Average percentage of cache occupancy 3069system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.515268 # Average percentage of cache occupancy 3070system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000087 # Average percentage of cache occupancy 3071system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy 3072system.l2c.tags.occ_percent::cpu1.inst 0.027208 # Average percentage of cache occupancy 3073system.l2c.tags.occ_percent::cpu1.data 0.010286 # Average percentage of cache occupancy 3074system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.037101 # Average percentage of cache occupancy 3075system.l2c.tags.occ_percent::total 0.964414 # Average percentage of cache occupancy 3076system.l2c.tags.occ_task_id_blocks::1022 29279 # Occupied blocks per task id 3077system.l2c.tags.occ_task_id_blocks::1023 30 # Occupied blocks per task id 3078system.l2c.tags.occ_task_id_blocks::1024 34582 # Occupied blocks per task id 3079system.l2c.tags.age_task_id_blocks_1022::2 180 # Occupied blocks per task id 3080system.l2c.tags.age_task_id_blocks_1022::3 5628 # Occupied blocks per task id 3081system.l2c.tags.age_task_id_blocks_1022::4 23471 # Occupied blocks per task id 3082system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 3083system.l2c.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id 3084system.l2c.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 3085system.l2c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id 3086system.l2c.tags.age_task_id_blocks_1024::2 579 # Occupied blocks per task id 3087system.l2c.tags.age_task_id_blocks_1024::3 6711 # Occupied blocks per task id 3088system.l2c.tags.age_task_id_blocks_1024::4 27249 # Occupied blocks per task id 3089system.l2c.tags.occ_task_id_percent::1022 0.446762 # Percentage of cache occupancy per task id 3090system.l2c.tags.occ_task_id_percent::1023 0.000458 # Percentage of cache occupancy per task id 3091system.l2c.tags.occ_task_id_percent::1024 0.527679 # Percentage of cache occupancy per task id 3092system.l2c.tags.tag_accesses 6131058 # Number of tag accesses 3093system.l2c.tags.data_accesses 6131058 # Number of data accesses 3094system.l2c.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3095system.l2c.WritebackDirty_hits::writebacks 266860 # number of WritebackDirty hits 3096system.l2c.WritebackDirty_hits::total 266860 # number of WritebackDirty hits 3097system.l2c.UpgradeReq_hits::cpu0.data 32430 # number of UpgradeReq hits 3098system.l2c.UpgradeReq_hits::cpu1.data 2686 # number of UpgradeReq hits 3099system.l2c.UpgradeReq_hits::total 35116 # number of UpgradeReq hits 3100system.l2c.SCUpgradeReq_hits::cpu0.data 2009 # number of SCUpgradeReq hits 3101system.l2c.SCUpgradeReq_hits::cpu1.data 933 # number of SCUpgradeReq hits 3102system.l2c.SCUpgradeReq_hits::total 2942 # number of SCUpgradeReq hits 3103system.l2c.ReadExReq_hits::cpu0.data 4036 # number of ReadExReq hits 3104system.l2c.ReadExReq_hits::cpu1.data 1379 # number of ReadExReq hits 3105system.l2c.ReadExReq_hits::total 5415 # number of ReadExReq hits 3106system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 163 # number of ReadSharedReq hits 3107system.l2c.ReadSharedReq_hits::cpu0.itb.walker 75 # number of ReadSharedReq hits 3108system.l2c.ReadSharedReq_hits::cpu0.inst 33190 # number of ReadSharedReq hits 3109system.l2c.ReadSharedReq_hits::cpu0.data 46982 # number of ReadSharedReq hits 3110system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46066 # number of ReadSharedReq hits 3111system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 73 # number of ReadSharedReq hits 3112system.l2c.ReadSharedReq_hits::cpu1.itb.walker 29 # number of ReadSharedReq hits 3113system.l2c.ReadSharedReq_hits::cpu1.inst 13227 # number of ReadSharedReq hits 3114system.l2c.ReadSharedReq_hits::cpu1.data 9835 # number of ReadSharedReq hits 3115system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5456 # number of ReadSharedReq hits 3116system.l2c.ReadSharedReq_hits::total 155096 # number of ReadSharedReq hits 3117system.l2c.demand_hits::cpu0.dtb.walker 163 # number of demand (read+write) hits 3118system.l2c.demand_hits::cpu0.itb.walker 75 # number of demand (read+write) hits 3119system.l2c.demand_hits::cpu0.inst 33190 # number of demand (read+write) hits 3120system.l2c.demand_hits::cpu0.data 51018 # number of demand (read+write) hits 3121system.l2c.demand_hits::cpu0.l2cache.prefetcher 46066 # number of demand (read+write) hits 3122system.l2c.demand_hits::cpu1.dtb.walker 73 # number of demand (read+write) hits 3123system.l2c.demand_hits::cpu1.itb.walker 29 # number of demand (read+write) hits 3124system.l2c.demand_hits::cpu1.inst 13227 # number of demand (read+write) hits 3125system.l2c.demand_hits::cpu1.data 11214 # number of demand (read+write) hits 3126system.l2c.demand_hits::cpu1.l2cache.prefetcher 5456 # number of demand (read+write) hits 3127system.l2c.demand_hits::total 160511 # number of demand (read+write) hits 3128system.l2c.overall_hits::cpu0.dtb.walker 163 # number of overall hits 3129system.l2c.overall_hits::cpu0.itb.walker 75 # number of overall hits 3130system.l2c.overall_hits::cpu0.inst 33190 # number of overall hits 3131system.l2c.overall_hits::cpu0.data 51018 # number of overall hits 3132system.l2c.overall_hits::cpu0.l2cache.prefetcher 46066 # number of overall hits 3133system.l2c.overall_hits::cpu1.dtb.walker 73 # number of overall hits 3134system.l2c.overall_hits::cpu1.itb.walker 29 # number of overall hits 3135system.l2c.overall_hits::cpu1.inst 13227 # number of overall hits 3136system.l2c.overall_hits::cpu1.data 11214 # number of overall hits 3137system.l2c.overall_hits::cpu1.l2cache.prefetcher 5456 # number of overall hits 3138system.l2c.overall_hits::total 160511 # number of overall hits 3139system.l2c.UpgradeReq_misses::cpu0.data 8984 # number of UpgradeReq misses 3140system.l2c.UpgradeReq_misses::cpu1.data 2771 # number of UpgradeReq misses 3141system.l2c.UpgradeReq_misses::total 11755 # number of UpgradeReq misses 3142system.l2c.SCUpgradeReq_misses::cpu0.data 655 # number of SCUpgradeReq misses 3143system.l2c.SCUpgradeReq_misses::cpu1.data 1290 # number of SCUpgradeReq misses 3144system.l2c.SCUpgradeReq_misses::total 1945 # number of SCUpgradeReq misses 3145system.l2c.ReadExReq_misses::cpu0.data 11642 # number of ReadExReq misses 3146system.l2c.ReadExReq_misses::cpu1.data 8933 # number of ReadExReq misses 3147system.l2c.ReadExReq_misses::total 20575 # number of ReadExReq misses 3148system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 27 # number of ReadSharedReq misses 3149system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses 3150system.l2c.ReadSharedReq_misses::cpu0.inst 19670 # number of ReadSharedReq misses 3151system.l2c.ReadSharedReq_misses::cpu0.data 9220 # number of ReadSharedReq misses 3152system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133244 # number of ReadSharedReq misses 3153system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 7 # number of ReadSharedReq misses 3154system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses 3155system.l2c.ReadSharedReq_misses::cpu1.inst 2815 # number of ReadSharedReq misses 3156system.l2c.ReadSharedReq_misses::cpu1.data 1145 # number of ReadSharedReq misses 3157system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 8148 # number of ReadSharedReq misses 3158system.l2c.ReadSharedReq_misses::total 174280 # number of ReadSharedReq misses 3159system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses 3160system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 3161system.l2c.demand_misses::cpu0.inst 19670 # number of demand (read+write) misses 3162system.l2c.demand_misses::cpu0.data 20862 # number of demand (read+write) misses 3163system.l2c.demand_misses::cpu0.l2cache.prefetcher 133244 # number of demand (read+write) misses 3164system.l2c.demand_misses::cpu1.dtb.walker 7 # number of demand (read+write) misses 3165system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 3166system.l2c.demand_misses::cpu1.inst 2815 # number of demand (read+write) misses 3167system.l2c.demand_misses::cpu1.data 10078 # number of demand (read+write) misses 3168system.l2c.demand_misses::cpu1.l2cache.prefetcher 8148 # number of demand (read+write) misses 3169system.l2c.demand_misses::total 194855 # number of demand (read+write) misses 3170system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses 3171system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 3172system.l2c.overall_misses::cpu0.inst 19670 # number of overall misses 3173system.l2c.overall_misses::cpu0.data 20862 # number of overall misses 3174system.l2c.overall_misses::cpu0.l2cache.prefetcher 133244 # number of overall misses 3175system.l2c.overall_misses::cpu1.dtb.walker 7 # number of overall misses 3176system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 3177system.l2c.overall_misses::cpu1.inst 2815 # number of overall misses 3178system.l2c.overall_misses::cpu1.data 10078 # number of overall misses 3179system.l2c.overall_misses::cpu1.l2cache.prefetcher 8148 # number of overall misses 3180system.l2c.overall_misses::total 194855 # number of overall misses 3181system.l2c.UpgradeReq_miss_latency::cpu0.data 8725000 # number of UpgradeReq miss cycles 3182system.l2c.UpgradeReq_miss_latency::cpu1.data 2891500 # number of UpgradeReq miss cycles 3183system.l2c.UpgradeReq_miss_latency::total 11616500 # number of UpgradeReq miss cycles 3184system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1430000 # number of SCUpgradeReq miss cycles 3185system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1143000 # number of SCUpgradeReq miss cycles 3186system.l2c.SCUpgradeReq_miss_latency::total 2573000 # number of SCUpgradeReq miss cycles 3187system.l2c.ReadExReq_miss_latency::cpu0.data 1196035499 # number of ReadExReq miss cycles 3188system.l2c.ReadExReq_miss_latency::cpu1.data 747656500 # number of ReadExReq miss cycles 3189system.l2c.ReadExReq_miss_latency::total 1943691999 # number of ReadExReq miss cycles 3190system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 2599000 # number of ReadSharedReq miss cycles 3191system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 241000 # number of ReadSharedReq miss cycles 3192system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1635002000 # number of ReadSharedReq miss cycles 3193system.l2c.ReadSharedReq_miss_latency::cpu0.data 838941000 # number of ReadSharedReq miss cycles 3194system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 14574955860 # number of ReadSharedReq miss cycles 3195system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 652000 # number of ReadSharedReq miss cycles 3196system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 97500 # number of ReadSharedReq miss cycles 3197system.l2c.ReadSharedReq_miss_latency::cpu1.inst 242297000 # number of ReadSharedReq miss cycles 3198system.l2c.ReadSharedReq_miss_latency::cpu1.data 106324000 # number of ReadSharedReq miss cycles 3199system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1101582147 # number of ReadSharedReq miss cycles 3200system.l2c.ReadSharedReq_miss_latency::total 18502691507 # number of ReadSharedReq miss cycles 3201system.l2c.demand_miss_latency::cpu0.dtb.walker 2599000 # number of demand (read+write) miss cycles 3202system.l2c.demand_miss_latency::cpu0.itb.walker 241000 # number of demand (read+write) miss cycles 3203system.l2c.demand_miss_latency::cpu0.inst 1635002000 # number of demand (read+write) miss cycles 3204system.l2c.demand_miss_latency::cpu0.data 2034976499 # number of demand (read+write) miss cycles 3205system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14574955860 # number of demand (read+write) miss cycles 3206system.l2c.demand_miss_latency::cpu1.dtb.walker 652000 # number of demand (read+write) miss cycles 3207system.l2c.demand_miss_latency::cpu1.itb.walker 97500 # number of demand (read+write) miss cycles 3208system.l2c.demand_miss_latency::cpu1.inst 242297000 # number of demand (read+write) miss cycles 3209system.l2c.demand_miss_latency::cpu1.data 853980500 # number of demand (read+write) miss cycles 3210system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1101582147 # number of demand (read+write) miss cycles 3211system.l2c.demand_miss_latency::total 20446383506 # number of demand (read+write) miss cycles 3212system.l2c.overall_miss_latency::cpu0.dtb.walker 2599000 # number of overall miss cycles 3213system.l2c.overall_miss_latency::cpu0.itb.walker 241000 # number of overall miss cycles 3214system.l2c.overall_miss_latency::cpu0.inst 1635002000 # number of overall miss cycles 3215system.l2c.overall_miss_latency::cpu0.data 2034976499 # number of overall miss cycles 3216system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14574955860 # number of overall miss cycles 3217system.l2c.overall_miss_latency::cpu1.dtb.walker 652000 # number of overall miss cycles 3218system.l2c.overall_miss_latency::cpu1.itb.walker 97500 # number of overall miss cycles 3219system.l2c.overall_miss_latency::cpu1.inst 242297000 # number of overall miss cycles 3220system.l2c.overall_miss_latency::cpu1.data 853980500 # number of overall miss cycles 3221system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1101582147 # number of overall miss cycles 3222system.l2c.overall_miss_latency::total 20446383506 # number of overall miss cycles 3223system.l2c.WritebackDirty_accesses::writebacks 266860 # number of WritebackDirty accesses(hits+misses) 3224system.l2c.WritebackDirty_accesses::total 266860 # number of WritebackDirty accesses(hits+misses) 3225system.l2c.UpgradeReq_accesses::cpu0.data 41414 # number of UpgradeReq accesses(hits+misses) 3226system.l2c.UpgradeReq_accesses::cpu1.data 5457 # number of UpgradeReq accesses(hits+misses) 3227system.l2c.UpgradeReq_accesses::total 46871 # number of UpgradeReq accesses(hits+misses) 3228system.l2c.SCUpgradeReq_accesses::cpu0.data 2664 # number of SCUpgradeReq accesses(hits+misses) 3229system.l2c.SCUpgradeReq_accesses::cpu1.data 2223 # number of SCUpgradeReq accesses(hits+misses) 3230system.l2c.SCUpgradeReq_accesses::total 4887 # number of SCUpgradeReq accesses(hits+misses) 3231system.l2c.ReadExReq_accesses::cpu0.data 15678 # number of ReadExReq accesses(hits+misses) 3232system.l2c.ReadExReq_accesses::cpu1.data 10312 # number of ReadExReq accesses(hits+misses) 3233system.l2c.ReadExReq_accesses::total 25990 # number of ReadExReq accesses(hits+misses) 3234system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 190 # number of ReadSharedReq accesses(hits+misses) 3235system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 78 # number of ReadSharedReq accesses(hits+misses) 3236system.l2c.ReadSharedReq_accesses::cpu0.inst 52860 # number of ReadSharedReq accesses(hits+misses) 3237system.l2c.ReadSharedReq_accesses::cpu0.data 56202 # number of ReadSharedReq accesses(hits+misses) 3238system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179310 # number of ReadSharedReq accesses(hits+misses) 3239system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 80 # number of ReadSharedReq accesses(hits+misses) 3240system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 30 # number of ReadSharedReq accesses(hits+misses) 3241system.l2c.ReadSharedReq_accesses::cpu1.inst 16042 # number of ReadSharedReq accesses(hits+misses) 3242system.l2c.ReadSharedReq_accesses::cpu1.data 10980 # number of ReadSharedReq accesses(hits+misses) 3243system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 13604 # number of ReadSharedReq accesses(hits+misses) 3244system.l2c.ReadSharedReq_accesses::total 329376 # number of ReadSharedReq accesses(hits+misses) 3245system.l2c.demand_accesses::cpu0.dtb.walker 190 # number of demand (read+write) accesses 3246system.l2c.demand_accesses::cpu0.itb.walker 78 # number of demand (read+write) accesses 3247system.l2c.demand_accesses::cpu0.inst 52860 # number of demand (read+write) accesses 3248system.l2c.demand_accesses::cpu0.data 71880 # number of demand (read+write) accesses 3249system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179310 # number of demand (read+write) accesses 3250system.l2c.demand_accesses::cpu1.dtb.walker 80 # number of demand (read+write) accesses 3251system.l2c.demand_accesses::cpu1.itb.walker 30 # number of demand (read+write) accesses 3252system.l2c.demand_accesses::cpu1.inst 16042 # number of demand (read+write) accesses 3253system.l2c.demand_accesses::cpu1.data 21292 # number of demand (read+write) accesses 3254system.l2c.demand_accesses::cpu1.l2cache.prefetcher 13604 # number of demand (read+write) accesses 3255system.l2c.demand_accesses::total 355366 # number of demand (read+write) accesses 3256system.l2c.overall_accesses::cpu0.dtb.walker 190 # number of overall (read+write) accesses 3257system.l2c.overall_accesses::cpu0.itb.walker 78 # number of overall (read+write) accesses 3258system.l2c.overall_accesses::cpu0.inst 52860 # number of overall (read+write) accesses 3259system.l2c.overall_accesses::cpu0.data 71880 # number of overall (read+write) accesses 3260system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179310 # number of overall (read+write) accesses 3261system.l2c.overall_accesses::cpu1.dtb.walker 80 # number of overall (read+write) accesses 3262system.l2c.overall_accesses::cpu1.itb.walker 30 # number of overall (read+write) accesses 3263system.l2c.overall_accesses::cpu1.inst 16042 # number of overall (read+write) accesses 3264system.l2c.overall_accesses::cpu1.data 21292 # number of overall (read+write) accesses 3265system.l2c.overall_accesses::cpu1.l2cache.prefetcher 13604 # number of overall (read+write) accesses 3266system.l2c.overall_accesses::total 355366 # number of overall (read+write) accesses 3267system.l2c.UpgradeReq_miss_rate::cpu0.data 0.216931 # miss rate for UpgradeReq accesses 3268system.l2c.UpgradeReq_miss_rate::cpu1.data 0.507788 # miss rate for UpgradeReq accesses 3269system.l2c.UpgradeReq_miss_rate::total 0.250795 # miss rate for UpgradeReq accesses 3270system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.245871 # miss rate for SCUpgradeReq accesses 3271system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.580297 # miss rate for SCUpgradeReq accesses 3272system.l2c.SCUpgradeReq_miss_rate::total 0.397995 # miss rate for SCUpgradeReq accesses 3273system.l2c.ReadExReq_miss_rate::cpu0.data 0.742569 # miss rate for ReadExReq accesses 3274system.l2c.ReadExReq_miss_rate::cpu1.data 0.866272 # miss rate for ReadExReq accesses 3275system.l2c.ReadExReq_miss_rate::total 0.791651 # miss rate for ReadExReq accesses 3276system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.142105 # miss rate for ReadSharedReq accesses 3277system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.038462 # miss rate for ReadSharedReq accesses 3278system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.372115 # miss rate for ReadSharedReq accesses 3279system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.164051 # miss rate for ReadSharedReq accesses 3280system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.743093 # miss rate for ReadSharedReq accesses 3281system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.087500 # miss rate for ReadSharedReq accesses 3282system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.033333 # miss rate for ReadSharedReq accesses 3283system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.175477 # miss rate for ReadSharedReq accesses 3284system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.104281 # miss rate for ReadSharedReq accesses 3285system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.598941 # miss rate for ReadSharedReq accesses 3286system.l2c.ReadSharedReq_miss_rate::total 0.529122 # miss rate for ReadSharedReq accesses 3287system.l2c.demand_miss_rate::cpu0.dtb.walker 0.142105 # miss rate for demand accesses 3288system.l2c.demand_miss_rate::cpu0.itb.walker 0.038462 # miss rate for demand accesses 3289system.l2c.demand_miss_rate::cpu0.inst 0.372115 # miss rate for demand accesses 3290system.l2c.demand_miss_rate::cpu0.data 0.290234 # miss rate for demand accesses 3291system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.743093 # miss rate for demand accesses 3292system.l2c.demand_miss_rate::cpu1.dtb.walker 0.087500 # miss rate for demand accesses 3293system.l2c.demand_miss_rate::cpu1.itb.walker 0.033333 # miss rate for demand accesses 3294system.l2c.demand_miss_rate::cpu1.inst 0.175477 # miss rate for demand accesses 3295system.l2c.demand_miss_rate::cpu1.data 0.473323 # miss rate for demand accesses 3296system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.598941 # miss rate for demand accesses 3297system.l2c.demand_miss_rate::total 0.548322 # miss rate for demand accesses 3298system.l2c.overall_miss_rate::cpu0.dtb.walker 0.142105 # miss rate for overall accesses 3299system.l2c.overall_miss_rate::cpu0.itb.walker 0.038462 # miss rate for overall accesses 3300system.l2c.overall_miss_rate::cpu0.inst 0.372115 # miss rate for overall accesses 3301system.l2c.overall_miss_rate::cpu0.data 0.290234 # miss rate for overall accesses 3302system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.743093 # miss rate for overall accesses 3303system.l2c.overall_miss_rate::cpu1.dtb.walker 0.087500 # miss rate for overall accesses 3304system.l2c.overall_miss_rate::cpu1.itb.walker 0.033333 # miss rate for overall accesses 3305system.l2c.overall_miss_rate::cpu1.inst 0.175477 # miss rate for overall accesses 3306system.l2c.overall_miss_rate::cpu1.data 0.473323 # miss rate for overall accesses 3307system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.598941 # miss rate for overall accesses 3308system.l2c.overall_miss_rate::total 0.548322 # miss rate for overall accesses 3309system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 971.170971 # average UpgradeReq miss latency 3310system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1043.486106 # average UpgradeReq miss latency 3311system.l2c.UpgradeReq_avg_miss_latency::total 988.217780 # average UpgradeReq miss latency 3312system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2183.206107 # average SCUpgradeReq miss latency 3313system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 886.046512 # average SCUpgradeReq miss latency 3314system.l2c.SCUpgradeReq_avg_miss_latency::total 1322.879177 # average SCUpgradeReq miss latency 3315system.l2c.ReadExReq_avg_miss_latency::cpu0.data 102734.538653 # average ReadExReq miss latency 3316system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83696.014777 # average ReadExReq miss latency 3317system.l2c.ReadExReq_avg_miss_latency::total 94468.626926 # average ReadExReq miss latency 3318system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 96259.259259 # average ReadSharedReq miss latency 3319system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 80333.333333 # average ReadSharedReq miss latency 3320system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83121.606507 # average ReadSharedReq miss latency 3321system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90991.431670 # average ReadSharedReq miss latency 3322system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 109385.457206 # average ReadSharedReq miss latency 3323system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 93142.857143 # average ReadSharedReq miss latency 3324system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 97500 # average ReadSharedReq miss latency 3325system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86073.534636 # average ReadSharedReq miss latency 3326system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 92859.388646 # average ReadSharedReq miss latency 3327system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 135196.630707 # average ReadSharedReq miss latency 3328system.l2c.ReadSharedReq_avg_miss_latency::total 106166.464924 # average ReadSharedReq miss latency 3329system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 96259.259259 # average overall miss latency 3330system.l2c.demand_avg_miss_latency::cpu0.itb.walker 80333.333333 # average overall miss latency 3331system.l2c.demand_avg_miss_latency::cpu0.inst 83121.606507 # average overall miss latency 3332system.l2c.demand_avg_miss_latency::cpu0.data 97544.650513 # average overall miss latency 3333system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 109385.457206 # average overall miss latency 3334system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 93142.857143 # average overall miss latency 3335system.l2c.demand_avg_miss_latency::cpu1.itb.walker 97500 # average overall miss latency 3336system.l2c.demand_avg_miss_latency::cpu1.inst 86073.534636 # average overall miss latency 3337system.l2c.demand_avg_miss_latency::cpu1.data 84737.100615 # average overall miss latency 3338system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 135196.630707 # average overall miss latency 3339system.l2c.demand_avg_miss_latency::total 104931.274568 # average overall miss latency 3340system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 96259.259259 # average overall miss latency 3341system.l2c.overall_avg_miss_latency::cpu0.itb.walker 80333.333333 # average overall miss latency 3342system.l2c.overall_avg_miss_latency::cpu0.inst 83121.606507 # average overall miss latency 3343system.l2c.overall_avg_miss_latency::cpu0.data 97544.650513 # average overall miss latency 3344system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 109385.457206 # average overall miss latency 3345system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 93142.857143 # average overall miss latency 3346system.l2c.overall_avg_miss_latency::cpu1.itb.walker 97500 # average overall miss latency 3347system.l2c.overall_avg_miss_latency::cpu1.inst 86073.534636 # average overall miss latency 3348system.l2c.overall_avg_miss_latency::cpu1.data 84737.100615 # average overall miss latency 3349system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 135196.630707 # average overall miss latency 3350system.l2c.overall_avg_miss_latency::total 104931.274568 # average overall miss latency 3351system.l2c.blocked_cycles::no_mshrs 21 # number of cycles access was blocked 3352system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3353system.l2c.blocked::no_mshrs 3 # number of cycles access was blocked 3354system.l2c.blocked::no_targets 0 # number of cycles access was blocked 3355system.l2c.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked 3356system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3357system.l2c.writebacks::writebacks 103743 # number of writebacks 3358system.l2c.writebacks::total 103743 # number of writebacks 3359system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 8 # number of ReadSharedReq MSHR hits 3360system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 8 # number of ReadSharedReq MSHR hits 3361system.l2c.ReadSharedReq_mshr_hits::total 16 # number of ReadSharedReq MSHR hits 3362system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits 3363system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits 3364system.l2c.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 3365system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits 3366system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits 3367system.l2c.overall_mshr_hits::total 16 # number of overall MSHR hits 3368system.l2c.CleanEvict_mshr_misses::writebacks 3708 # number of CleanEvict MSHR misses 3369system.l2c.CleanEvict_mshr_misses::total 3708 # number of CleanEvict MSHR misses 3370system.l2c.UpgradeReq_mshr_misses::cpu0.data 8984 # number of UpgradeReq MSHR misses 3371system.l2c.UpgradeReq_mshr_misses::cpu1.data 2771 # number of UpgradeReq MSHR misses 3372system.l2c.UpgradeReq_mshr_misses::total 11755 # number of UpgradeReq MSHR misses 3373system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 655 # number of SCUpgradeReq MSHR misses 3374system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1290 # number of SCUpgradeReq MSHR misses 3375system.l2c.SCUpgradeReq_mshr_misses::total 1945 # number of SCUpgradeReq MSHR misses 3376system.l2c.ReadExReq_mshr_misses::cpu0.data 11642 # number of ReadExReq MSHR misses 3377system.l2c.ReadExReq_mshr_misses::cpu1.data 8933 # number of ReadExReq MSHR misses 3378system.l2c.ReadExReq_mshr_misses::total 20575 # number of ReadExReq MSHR misses 3379system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 27 # number of ReadSharedReq MSHR misses 3380system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3 # number of ReadSharedReq MSHR misses 3381system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19662 # number of ReadSharedReq MSHR misses 3382system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9220 # number of ReadSharedReq MSHR misses 3383system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133244 # number of ReadSharedReq MSHR misses 3384system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 7 # number of ReadSharedReq MSHR misses 3385system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses 3386system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2807 # number of ReadSharedReq MSHR misses 3387system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1145 # number of ReadSharedReq MSHR misses 3388system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 8148 # number of ReadSharedReq MSHR misses 3389system.l2c.ReadSharedReq_mshr_misses::total 174264 # number of ReadSharedReq MSHR misses 3390system.l2c.demand_mshr_misses::cpu0.dtb.walker 27 # number of demand (read+write) MSHR misses 3391system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses 3392system.l2c.demand_mshr_misses::cpu0.inst 19662 # number of demand (read+write) MSHR misses 3393system.l2c.demand_mshr_misses::cpu0.data 20862 # number of demand (read+write) MSHR misses 3394system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133244 # number of demand (read+write) MSHR misses 3395system.l2c.demand_mshr_misses::cpu1.dtb.walker 7 # number of demand (read+write) MSHR misses 3396system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses 3397system.l2c.demand_mshr_misses::cpu1.inst 2807 # number of demand (read+write) MSHR misses 3398system.l2c.demand_mshr_misses::cpu1.data 10078 # number of demand (read+write) MSHR misses 3399system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 8148 # number of demand (read+write) MSHR misses 3400system.l2c.demand_mshr_misses::total 194839 # number of demand (read+write) MSHR misses 3401system.l2c.overall_mshr_misses::cpu0.dtb.walker 27 # number of overall MSHR misses 3402system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses 3403system.l2c.overall_mshr_misses::cpu0.inst 19662 # number of overall MSHR misses 3404system.l2c.overall_mshr_misses::cpu0.data 20862 # number of overall MSHR misses 3405system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133244 # number of overall MSHR misses 3406system.l2c.overall_mshr_misses::cpu1.dtb.walker 7 # number of overall MSHR misses 3407system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 3408system.l2c.overall_mshr_misses::cpu1.inst 2807 # number of overall MSHR misses 3409system.l2c.overall_mshr_misses::cpu1.data 10078 # number of overall MSHR misses 3410system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 8148 # number of overall MSHR misses 3411system.l2c.overall_mshr_misses::total 194839 # number of overall MSHR misses 3412system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable 3413system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31771 # number of ReadReq MSHR uncacheable 3414system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable 3415system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3075 # number of ReadReq MSHR uncacheable 3416system.l2c.ReadReq_mshr_uncacheable::total 37951 # number of ReadReq MSHR uncacheable 3417system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28450 # number of WriteReq MSHR uncacheable 3418system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2435 # number of WriteReq MSHR uncacheable 3419system.l2c.WriteReq_mshr_uncacheable::total 30885 # number of WriteReq MSHR uncacheable 3420system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses 3421system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60221 # number of overall MSHR uncacheable misses 3422system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses 3423system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5510 # number of overall MSHR uncacheable misses 3424system.l2c.overall_mshr_uncacheable_misses::total 68836 # number of overall MSHR uncacheable misses 3425system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 213623000 # number of UpgradeReq MSHR miss cycles 3426system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 63075000 # number of UpgradeReq MSHR miss cycles 3427system.l2c.UpgradeReq_mshr_miss_latency::total 276698000 # number of UpgradeReq MSHR miss cycles 3428system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16864000 # number of SCUpgradeReq MSHR miss cycles 3429system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 32149500 # number of SCUpgradeReq MSHR miss cycles 3430system.l2c.SCUpgradeReq_mshr_miss_latency::total 49013500 # number of SCUpgradeReq MSHR miss cycles 3431system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1079614502 # number of ReadExReq MSHR miss cycles 3432system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 658325502 # number of ReadExReq MSHR miss cycles 3433system.l2c.ReadExReq_mshr_miss_latency::total 1737940004 # number of ReadExReq MSHR miss cycles 3434system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 2329000 # number of ReadSharedReq MSHR miss cycles 3435system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 211000 # number of ReadSharedReq MSHR miss cycles 3436system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1437895505 # number of ReadSharedReq MSHR miss cycles 3437system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 746740501 # number of ReadSharedReq MSHR miss cycles 3438system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13242511370 # number of ReadSharedReq MSHR miss cycles 3439system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 582000 # number of ReadSharedReq MSHR miss cycles 3440system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 87500 # number of ReadSharedReq MSHR miss cycles 3441system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 213731003 # number of ReadSharedReq MSHR miss cycles 3442system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 94873501 # number of ReadSharedReq MSHR miss cycles 3443system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1020101648 # number of ReadSharedReq MSHR miss cycles 3444system.l2c.ReadSharedReq_mshr_miss_latency::total 16759063028 # number of ReadSharedReq MSHR miss cycles 3445system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2329000 # number of demand (read+write) MSHR miss cycles 3446system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 211000 # number of demand (read+write) MSHR miss cycles 3447system.l2c.demand_mshr_miss_latency::cpu0.inst 1437895505 # number of demand (read+write) MSHR miss cycles 3448system.l2c.demand_mshr_miss_latency::cpu0.data 1826355003 # number of demand (read+write) MSHR miss cycles 3449system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13242511370 # number of demand (read+write) MSHR miss cycles 3450system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 582000 # number of demand (read+write) MSHR miss cycles 3451system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 87500 # number of demand (read+write) MSHR miss cycles 3452system.l2c.demand_mshr_miss_latency::cpu1.inst 213731003 # number of demand (read+write) MSHR miss cycles 3453system.l2c.demand_mshr_miss_latency::cpu1.data 753199003 # number of demand (read+write) MSHR miss cycles 3454system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1020101648 # number of demand (read+write) MSHR miss cycles 3455system.l2c.demand_mshr_miss_latency::total 18497003032 # number of demand (read+write) MSHR miss cycles 3456system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2329000 # number of overall MSHR miss cycles 3457system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 211000 # number of overall MSHR miss cycles 3458system.l2c.overall_mshr_miss_latency::cpu0.inst 1437895505 # number of overall MSHR miss cycles 3459system.l2c.overall_mshr_miss_latency::cpu0.data 1826355003 # number of overall MSHR miss cycles 3460system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13242511370 # number of overall MSHR miss cycles 3461system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 582000 # number of overall MSHR miss cycles 3462system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 87500 # number of overall MSHR miss cycles 3463system.l2c.overall_mshr_miss_latency::cpu1.inst 213731003 # number of overall MSHR miss cycles 3464system.l2c.overall_mshr_miss_latency::cpu1.data 753199003 # number of overall MSHR miss cycles 3465system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1020101648 # number of overall MSHR miss cycles 3466system.l2c.overall_mshr_miss_latency::total 18497003032 # number of overall MSHR miss cycles 3467system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 192566500 # number of ReadReq MSHR uncacheable cycles 3468system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5794669001 # number of ReadReq MSHR uncacheable cycles 3469system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6627000 # number of ReadReq MSHR uncacheable cycles 3470system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 361914000 # number of ReadReq MSHR uncacheable cycles 3471system.l2c.ReadReq_mshr_uncacheable_latency::total 6355776501 # number of ReadReq MSHR uncacheable cycles 3472system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 192566500 # number of overall MSHR uncacheable cycles 3473system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5794669001 # number of overall MSHR uncacheable cycles 3474system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6627000 # number of overall MSHR uncacheable cycles 3475system.l2c.overall_mshr_uncacheable_latency::cpu1.data 361914000 # number of overall MSHR uncacheable cycles 3476system.l2c.overall_mshr_uncacheable_latency::total 6355776501 # number of overall MSHR uncacheable cycles 3477system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3478system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3479system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.216931 # mshr miss rate for UpgradeReq accesses 3480system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.507788 # mshr miss rate for UpgradeReq accesses 3481system.l2c.UpgradeReq_mshr_miss_rate::total 0.250795 # mshr miss rate for UpgradeReq accesses 3482system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.245871 # mshr miss rate for SCUpgradeReq accesses 3483system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.580297 # mshr miss rate for SCUpgradeReq accesses 3484system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.397995 # mshr miss rate for SCUpgradeReq accesses 3485system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.742569 # mshr miss rate for ReadExReq accesses 3486system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.866272 # mshr miss rate for ReadExReq accesses 3487system.l2c.ReadExReq_mshr_miss_rate::total 0.791651 # mshr miss rate for ReadExReq accesses 3488system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.142105 # mshr miss rate for ReadSharedReq accesses 3489system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.038462 # mshr miss rate for ReadSharedReq accesses 3490system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.371964 # mshr miss rate for ReadSharedReq accesses 3491system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.164051 # mshr miss rate for ReadSharedReq accesses 3492system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743093 # mshr miss rate for ReadSharedReq accesses 3493system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.087500 # mshr miss rate for ReadSharedReq accesses 3494system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for ReadSharedReq accesses 3495system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.174978 # mshr miss rate for ReadSharedReq accesses 3496system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.104281 # mshr miss rate for ReadSharedReq accesses 3497system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.598941 # mshr miss rate for ReadSharedReq accesses 3498system.l2c.ReadSharedReq_mshr_miss_rate::total 0.529073 # mshr miss rate for ReadSharedReq accesses 3499system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.142105 # mshr miss rate for demand accesses 3500system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.038462 # mshr miss rate for demand accesses 3501system.l2c.demand_mshr_miss_rate::cpu0.inst 0.371964 # mshr miss rate for demand accesses 3502system.l2c.demand_mshr_miss_rate::cpu0.data 0.290234 # mshr miss rate for demand accesses 3503system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743093 # mshr miss rate for demand accesses 3504system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.087500 # mshr miss rate for demand accesses 3505system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for demand accesses 3506system.l2c.demand_mshr_miss_rate::cpu1.inst 0.174978 # mshr miss rate for demand accesses 3507system.l2c.demand_mshr_miss_rate::cpu1.data 0.473323 # mshr miss rate for demand accesses 3508system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.598941 # mshr miss rate for demand accesses 3509system.l2c.demand_mshr_miss_rate::total 0.548277 # mshr miss rate for demand accesses 3510system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.142105 # mshr miss rate for overall accesses 3511system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.038462 # mshr miss rate for overall accesses 3512system.l2c.overall_mshr_miss_rate::cpu0.inst 0.371964 # mshr miss rate for overall accesses 3513system.l2c.overall_mshr_miss_rate::cpu0.data 0.290234 # mshr miss rate for overall accesses 3514system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743093 # mshr miss rate for overall accesses 3515system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.087500 # mshr miss rate for overall accesses 3516system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for overall accesses 3517system.l2c.overall_mshr_miss_rate::cpu1.inst 0.174978 # mshr miss rate for overall accesses 3518system.l2c.overall_mshr_miss_rate::cpu1.data 0.473323 # mshr miss rate for overall accesses 3519system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.598941 # mshr miss rate for overall accesses 3520system.l2c.overall_mshr_miss_rate::total 0.548277 # mshr miss rate for overall accesses 3521system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23778.161175 # average UpgradeReq mshr miss latency 3522system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22762.540599 # average UpgradeReq mshr miss latency 3523system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23538.749468 # average UpgradeReq mshr miss latency 3524system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25746.564885 # average SCUpgradeReq mshr miss latency 3525system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24922.093023 # average SCUpgradeReq mshr miss latency 3526system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25199.742931 # average SCUpgradeReq mshr miss latency 3527system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92734.453015 # average ReadExReq mshr miss latency 3528system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73695.903056 # average ReadExReq mshr miss latency 3529system.l2c.ReadExReq_avg_mshr_miss_latency::total 84468.529964 # average ReadExReq mshr miss latency 3530system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 86259.259259 # average ReadSharedReq mshr miss latency 3531system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average ReadSharedReq mshr miss latency 3532system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73130.683806 # average ReadSharedReq mshr miss latency 3533system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80991.377549 # average ReadSharedReq mshr miss latency 3534system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99385.423509 # average ReadSharedReq mshr miss latency 3535system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 83142.857143 # average ReadSharedReq mshr miss latency 3536system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 87500 # average ReadSharedReq mshr miss latency 3537system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76142.145707 # average ReadSharedReq mshr miss latency 3538system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82858.952838 # average ReadSharedReq mshr miss latency 3539system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125196.569465 # average ReadSharedReq mshr miss latency 3540system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96170.540261 # average ReadSharedReq mshr miss latency 3541system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86259.259259 # average overall mshr miss latency 3542system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency 3543system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73130.683806 # average overall mshr miss latency 3544system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87544.578804 # average overall mshr miss latency 3545system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99385.423509 # average overall mshr miss latency 3546system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 83142.857143 # average overall mshr miss latency 3547system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 87500 # average overall mshr miss latency 3548system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76142.145707 # average overall mshr miss latency 3549system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74736.952074 # average overall mshr miss latency 3550system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125196.569465 # average overall mshr miss latency 3551system.l2c.demand_avg_mshr_miss_latency::total 94934.807877 # average overall mshr miss latency 3552system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86259.259259 # average overall mshr miss latency 3553system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency 3554system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73130.683806 # average overall mshr miss latency 3555system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87544.578804 # average overall mshr miss latency 3556system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99385.423509 # average overall mshr miss latency 3557system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83142.857143 # average overall mshr miss latency 3558system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 87500 # average overall mshr miss latency 3559system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76142.145707 # average overall mshr miss latency 3560system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74736.952074 # average overall mshr miss latency 3561system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125196.569465 # average overall mshr miss latency 3562system.l2c.overall_avg_mshr_miss_latency::total 94934.807877 # average overall mshr miss latency 3563system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average ReadReq mshr uncacheable latency 3564system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182388.624878 # average ReadReq mshr uncacheable latency 3565system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64970.588235 # average ReadReq mshr uncacheable latency 3566system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117695.609756 # average ReadReq mshr uncacheable latency 3567system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167473.228663 # average ReadReq mshr uncacheable latency 3568system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average overall mshr uncacheable latency 3569system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96223.393849 # average overall mshr uncacheable latency 3570system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64970.588235 # average overall mshr uncacheable latency 3571system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65683.121597 # average overall mshr uncacheable latency 3572system.l2c.overall_avg_mshr_uncacheable_latency::total 92332.159059 # average overall mshr uncacheable latency 3573system.membus.snoop_filter.tot_requests 523609 # Total number of requests made to the snoop filter. 3574system.membus.snoop_filter.hit_single_requests 298426 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3575system.membus.snoop_filter.hit_multi_requests 572 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3576system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3577system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3578system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3579system.membus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3580system.membus.trans_dist::ReadReq 37951 # Transaction distribution 3581system.membus.trans_dist::ReadResp 212466 # Transaction distribution 3582system.membus.trans_dist::WriteReq 30885 # Transaction distribution 3583system.membus.trans_dist::WriteResp 30885 # Transaction distribution 3584system.membus.trans_dist::WritebackDirty 139949 # Transaction distribution 3585system.membus.trans_dist::CleanEvict 17155 # Transaction distribution 3586system.membus.trans_dist::UpgradeReq 74789 # Transaction distribution 3587system.membus.trans_dist::SCUpgradeReq 40592 # Transaction distribution 3588system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 3589system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 3590system.membus.trans_dist::ReadExReq 40333 # Transaction distribution 3591system.membus.trans_dist::ReadExResp 20490 # Transaction distribution 3592system.membus.trans_dist::ReadSharedReq 174516 # Transaction distribution 3593system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 3594system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes) 3595system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes) 3596system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13608 # Packet count per connected master and slave (bytes) 3597system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661161 # Packet count per connected master and slave (bytes) 3598system.membus.pkt_count_system.l2c.mem_side::total 782719 # Packet count per connected master and slave (bytes) 3599system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) 3600system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) 3601system.membus.pkt_count::total 855668 # Packet count per connected master and slave (bytes) 3602system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) 3603system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes) 3604system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27216 # Cumulative packet size per connected master and slave (bytes) 3605system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19151816 # Cumulative packet size per connected master and slave (bytes) 3606system.membus.pkt_size_system.l2c.mem_side::total 19342114 # Cumulative packet size per connected master and slave (bytes) 3607system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 3608system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) 3609system.membus.pkt_size::total 21660258 # Cumulative packet size per connected master and slave (bytes) 3610system.membus.snoops 122014 # Total snoops (count) 3611system.membus.snoop_fanout::samples 435296 # Request fanout histogram 3612system.membus.snoop_fanout::mean 0.011884 # Request fanout histogram 3613system.membus.snoop_fanout::stdev 0.108364 # Request fanout histogram 3614system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3615system.membus.snoop_fanout::0 430123 98.81% 98.81% # Request fanout histogram 3616system.membus.snoop_fanout::1 5173 1.19% 100.00% # Request fanout histogram 3617system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3618system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3619system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3620system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3621system.membus.snoop_fanout::total 435296 # Request fanout histogram 3622system.membus.reqLayer0.occupancy 81593499 # Layer occupancy (ticks) 3623system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3624system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks) 3625system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3626system.membus.reqLayer2.occupancy 11516500 # Layer occupancy (ticks) 3627system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3628system.membus.reqLayer5.occupancy 1022226685 # Layer occupancy (ticks) 3629system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3630system.membus.respLayer2.occupancy 1121401156 # Layer occupancy (ticks) 3631system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3632system.membus.respLayer3.occupancy 1360881 # Layer occupancy (ticks) 3633system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3634system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3635system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3636system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3637system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3638system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3639system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3640system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3641system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3642system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3643system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3644system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3645system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3646system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3647system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3648system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3649system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3650system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3651system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3652system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3653system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3654system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3655system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3656system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3657system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3658system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3659system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3660system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3661system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3662system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3663system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3664system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3665system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3666system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3667system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3668system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3669system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3670system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3671system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3672system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3673system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3674system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3675system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3676system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3677system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3678system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3679system.realview.ethernet.droppedPackets 0 # number of packets dropped 3680system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3681system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3682system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3683system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3684system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3685system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3686system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3687system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3688system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3689system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3690system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3691system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3692system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3693system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3694system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3695system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3696system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3697system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3698system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3699system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3700system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3701system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3702system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3703system.toL2Bus.snoop_filter.tot_requests 1012829 # Total number of requests made to the snoop filter. 3704system.toL2Bus.snoop_filter.hit_single_requests 548493 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3705system.toL2Bus.snoop_filter.hit_multi_requests 154614 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3706system.toL2Bus.snoop_filter.tot_snoops 20965 # Total number of snoops made to the snoop filter. 3707system.toL2Bus.snoop_filter.hit_single_snoops 19995 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3708system.toL2Bus.snoop_filter.hit_multi_snoops 970 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3709system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3710system.toL2Bus.trans_dist::ReadReq 37954 # Transaction distribution 3711system.toL2Bus.trans_dist::ReadResp 485832 # Transaction distribution 3712system.toL2Bus.trans_dist::WriteReq 30885 # Transaction distribution 3713system.toL2Bus.trans_dist::WriteResp 30885 # Transaction distribution 3714system.toL2Bus.trans_dist::WritebackDirty 370603 # Transaction distribution 3715system.toL2Bus.trans_dist::CleanEvict 122893 # Transaction distribution 3716system.toL2Bus.trans_dist::UpgradeReq 109820 # Transaction distribution 3717system.toL2Bus.trans_dist::SCUpgradeReq 43534 # Transaction distribution 3718system.toL2Bus.trans_dist::UpgradeResp 153354 # Transaction distribution 3719system.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution 3720system.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution 3721system.toL2Bus.trans_dist::ReadExReq 51065 # Transaction distribution 3722system.toL2Bus.trans_dist::ReadExResp 51065 # Transaction distribution 3723system.toL2Bus.trans_dist::ReadSharedReq 447881 # Transaction distribution 3724system.toL2Bus.trans_dist::InvalidateReq 4599 # Transaction distribution 3725system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1241884 # Packet count per connected master and slave (bytes) 3726system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 315944 # Packet count per connected master and slave (bytes) 3727system.toL2Bus.pkt_count::total 1557828 # Packet count per connected master and slave (bytes) 3728system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34423168 # Cumulative packet size per connected master and slave (bytes) 3729system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5674082 # Cumulative packet size per connected master and slave (bytes) 3730system.toL2Bus.pkt_size::total 40097250 # Cumulative packet size per connected master and slave (bytes) 3731system.toL2Bus.snoops 382843 # Total snoops (count) 3732system.toL2Bus.snoop_fanout::samples 858573 # Request fanout histogram 3733system.toL2Bus.snoop_fanout::mean 0.374933 # Request fanout histogram 3734system.toL2Bus.snoop_fanout::stdev 0.486434 # Request fanout histogram 3735system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3736system.toL2Bus.snoop_fanout::0 537636 62.62% 62.62% # Request fanout histogram 3737system.toL2Bus.snoop_fanout::1 319967 37.27% 99.89% # Request fanout histogram 3738system.toL2Bus.snoop_fanout::2 970 0.11% 100.00% # Request fanout histogram 3739system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3740system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3741system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3742system.toL2Bus.snoop_fanout::total 858573 # Request fanout histogram 3743system.toL2Bus.reqLayer0.occupancy 885446562 # Layer occupancy (ticks) 3744system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3745system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks) 3746system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3747system.toL2Bus.respLayer0.occupancy 647873032 # Layer occupancy (ticks) 3748system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3749system.toL2Bus.respLayer1.occupancy 232753441 # Layer occupancy (ticks) 3750system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3751system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3752system.cpu0.kern.inst.quiesce 1828 # number of quiesce instructions executed 3753system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3754system.cpu1.kern.inst.quiesce 2763 # number of quiesce instructions executed 3755 3756---------- End Simulation Statistics ----------	1834system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1835system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1836system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1837system.cpu1.itb.perms_faults 578 # Number of TLB faults due to permissions restrictions 1838system.cpu1.itb.read_accesses 0 # DTB read accesses 1839system.cpu1.itb.write_accesses 0 # DTB write accesses 1840system.cpu1.itb.inst_accesses 8259433 # ITB inst accesses 1841system.cpu1.itb.hits 8253439 # DTB hits 1842system.cpu1.itb.misses 5994 # DTB misses 1843system.cpu1.itb.accesses 8259433 # DTB accesses 1844system.cpu1.numPwrStateTransitions 5525 # Number of power state transitions 1845system.cpu1.pwrStateClkGateDist::samples 2763 # Distribution of time spent in the clock gated state 1846system.cpu1.pwrStateClkGateDist::mean 1016473602.620702 # Distribution of time spent in the clock gated state 1847system.cpu1.pwrStateClkGateDist::stdev 25821981878.711128 # Distribution of time spent in the clock gated state 1848system.cpu1.pwrStateClkGateDist::underflows 1969 71.26% 71.26% # Distribution of time spent in the clock gated state 1849system.cpu1.pwrStateClkGateDist::1000-5e+10 788 28.52% 99.78% # Distribution of time spent in the clock gated state 1850system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.86% # Distribution of time spent in the clock gated state 1851system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state 1852system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 1853system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 1854system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state 1855system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 1856system.cpu1.pwrStateClkGateDist::max_value 959984667908 # Distribution of time spent in the clock gated state 1857system.cpu1.pwrStateClkGateDist::total 2763 # Distribution of time spent in the clock gated state 1858system.cpu1.pwrStateResidencyTicks::ON 17443167459 # Cumulative time (in ticks) in various power states 1859system.cpu1.pwrStateResidencyTicks::CLK_GATED 2808516564041 # Cumulative time (in ticks) in various power states 1860system.cpu1.numCycles 34887121 # number of cpu cycles simulated 1861system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1862system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1863system.cpu1.fetch.icacheStallCycles 8560607 # Number of cycles fetch is stalled on an Icache miss 1864system.cpu1.fetch.Insts 24821804 # Number of instructions fetch has processed 1865system.cpu1.fetch.Branches 4689327 # Number of branches that fetch encountered 1866system.cpu1.fetch.predictedBranches 2662390 # Number of branches that fetch has predicted taken 1867system.cpu1.fetch.Cycles 24583766 # Number of cycles fetch has run and was not squashing or blocked 1868system.cpu1.fetch.SquashCycles 780426 # Number of cycles fetch has spent squashing 1869system.cpu1.fetch.TlbCycles 78816 # Number of cycles fetch has spent waiting for tlb 1870system.cpu1.fetch.MiscStallCycles 28892 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1871system.cpu1.fetch.PendingTrapStallCycles 168872 # Number of stall cycles due to pending traps 1872system.cpu1.fetch.PendingQuiesceStallCycles 301988 # Number of stall cycles due to pending quiesce instructions 1873system.cpu1.fetch.IcacheWaitRetryStallCycles 23027 # Number of stall cycles due to full MSHR 1874system.cpu1.fetch.CacheLines 8252257 # Number of cache lines fetched 1875system.cpu1.fetch.IcacheSquashes 107887 # Number of outstanding Icache misses that were squashed 1876system.cpu1.fetch.ItlbSquashes 2262 # Number of outstanding ITLB misses that were squashed 1877system.cpu1.fetch.rateDist::samples 34136181 # Number of instructions fetched each cycle (Total) 1878system.cpu1.fetch.rateDist::mean 0.885084 # Number of instructions fetched each cycle (Total) 1879system.cpu1.fetch.rateDist::stdev 1.219625 # Number of instructions fetched each cycle (Total) 1880system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1881system.cpu1.fetch.rateDist::0 20248194 59.32% 59.32% # Number of instructions fetched each cycle (Total) 1882system.cpu1.fetch.rateDist::1 4889749 14.32% 73.64% # Number of instructions fetched each cycle (Total) 1883system.cpu1.fetch.rateDist::2 1671087 4.90% 78.54% # Number of instructions fetched each cycle (Total) 1884system.cpu1.fetch.rateDist::3 7327151 21.46% 100.00% # Number of instructions fetched each cycle (Total) 1885system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1886system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1887system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1888system.cpu1.fetch.rateDist::total 34136181 # Number of instructions fetched each cycle (Total) 1889system.cpu1.fetch.branchRate 0.134414 # Number of branch fetches per cycle 1890system.cpu1.fetch.rate 0.711489 # Number of inst fetches per cycle 1891system.cpu1.decode.IdleCycles 7136711 # Number of cycles decode is idle 1892system.cpu1.decode.BlockedCycles 16890873 # Number of cycles decode is blocked 1893system.cpu1.decode.RunCycles 8747772 # Number of cycles decode is running 1894system.cpu1.decode.UnblockCycles 1097057 # Number of cycles decode is unblocking 1895system.cpu1.decode.SquashCycles 263768 # Number of cycles decode is squashing 1896system.cpu1.decode.BranchResolved 709532 # Number of times decode resolved a branch 1897system.cpu1.decode.BranchMispred 129045 # Number of times decode detected a branch misprediction 1898system.cpu1.decode.DecodedInsts 23428697 # Number of instructions handled by decode 1899system.cpu1.decode.SquashedInsts 1046505 # Number of squashed instructions handled by decode 1900system.cpu1.rename.SquashCycles 263768 # Number of cycles rename is squashing 1901system.cpu1.rename.IdleCycles 8558773 # Number of cycles rename is idle 1902system.cpu1.rename.BlockCycles 2377328 # Number of cycles rename is blocking 1903system.cpu1.rename.serializeStallCycles 11841982 # count of cycles rename stalled for serializing inst 1904system.cpu1.rename.RunCycles 8401624 # Number of cycles rename is running 1905system.cpu1.rename.UnblockCycles 2692706 # Number of cycles rename is unblocking 1906system.cpu1.rename.RenamedInsts 22261726 # Number of instructions processed by rename 1907system.cpu1.rename.SquashedInsts 187544 # Number of squashed instructions processed by rename 1908system.cpu1.rename.ROBFullEvents 264330 # Number of times rename has blocked due to ROB full 1909system.cpu1.rename.IQFullEvents 36982 # Number of times rename has blocked due to IQ full 1910system.cpu1.rename.LQFullEvents 15461 # Number of times rename has blocked due to LQ full 1911system.cpu1.rename.SQFullEvents 1675349 # Number of times rename has blocked due to SQ full 1912system.cpu1.rename.RenamedOperands 22265644 # Number of destination operands rename has renamed 1913system.cpu1.rename.RenameLookups 103648875 # Number of register rename lookups that rename has made 1914system.cpu1.rename.int_rename_lookups 25648399 # Number of integer rename lookups 1915system.cpu1.rename.fp_rename_lookups 1667 # Number of floating rename lookups 1916system.cpu1.rename.CommittedMaps 19867778 # Number of HB maps that are committed 1917system.cpu1.rename.UndoneMaps 2397866 # Number of HB maps that are undone due to squashing 1918system.cpu1.rename.serializingInsts 407377 # count of serializing insts renamed 1919system.cpu1.rename.tempSerializingInsts 334219 # count of temporary serializing insts renamed 1920system.cpu1.rename.skidInsts 2894111 # count of insts added to the skid buffer 1921system.cpu1.memDep0.insertedLoads 4447920 # Number of loads inserted to the mem dependence unit. 1922system.cpu1.memDep0.insertedStores 3797613 # Number of stores inserted to the mem dependence unit. 1923system.cpu1.memDep0.conflictingLoads 625649 # Number of conflicting loads. 1924system.cpu1.memDep0.conflictingStores 631175 # Number of conflicting stores. 1925system.cpu1.iq.iqInstsAdded 21446441 # Number of instructions added to the IQ (excludes non-spec) 1926system.cpu1.iq.iqNonSpecInstsAdded 559995 # Number of non-speculative instructions added to the IQ 1927system.cpu1.iq.iqInstsIssued 21251983 # Number of instructions issued 1928system.cpu1.iq.iqSquashedInstsIssued 91992 # Number of squashed instructions issued 1929system.cpu1.iq.iqSquashedInstsExamined 2044542 # Number of squashed instructions iterated over during squash; mainly for profiling 1930system.cpu1.iq.iqSquashedOperandsExamined 4726903 # Number of squashed operands that are examined and possibly removed from graph 1931system.cpu1.iq.iqSquashedNonSpecRemoved 43295 # Number of squashed non-spec instructions that were removed 1932system.cpu1.iq.issued_per_cycle::samples 34136181 # Number of insts issued each cycle 1933system.cpu1.iq.issued_per_cycle::mean 0.622565 # Number of insts issued each cycle 1934system.cpu1.iq.issued_per_cycle::stdev 0.949324 # Number of insts issued each cycle 1935system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1936system.cpu1.iq.issued_per_cycle::0 21624116 63.35% 63.35% # Number of insts issued each cycle 1937system.cpu1.iq.issued_per_cycle::1 6146372 18.01% 81.35% # Number of insts issued each cycle 1938system.cpu1.iq.issued_per_cycle::2 4248735 12.45% 93.80% # Number of insts issued each cycle 1939system.cpu1.iq.issued_per_cycle::3 1859698 5.45% 99.25% # Number of insts issued each cycle 1940system.cpu1.iq.issued_per_cycle::4 257253 0.75% 100.00% # Number of insts issued each cycle 1941system.cpu1.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle 1942system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1943system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1944system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1945system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1946system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1947system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 1948system.cpu1.iq.issued_per_cycle::total 34136181 # Number of insts issued each cycle 1949system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1950system.cpu1.iq.fu_full::IntAlu 1435935 29.89% 29.89% # attempts to use FU when none available 1951system.cpu1.iq.fu_full::IntMult 668 0.01% 29.90% # attempts to use FU when none available 1952system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.90% # attempts to use FU when none available 1953system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.90% # attempts to use FU when none available 1954system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.90% # attempts to use FU when none available 1955system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.90% # attempts to use FU when none available 1956system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.90% # attempts to use FU when none available 1957system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.90% # attempts to use FU when none available 1958system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.90% # attempts to use FU when none available 1959system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.90% # attempts to use FU when none available 1960system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.90% # attempts to use FU when none available 1961system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.90% # attempts to use FU when none available 1962system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.90% # attempts to use FU when none available 1963system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.90% # attempts to use FU when none available 1964system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.90% # attempts to use FU when none available 1965system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.90% # attempts to use FU when none available 1966system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.90% # attempts to use FU when none available 1967system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.90% # attempts to use FU when none available 1968system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.90% # attempts to use FU when none available 1969system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.90% # attempts to use FU when none available 1970system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.90% # attempts to use FU when none available 1971system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.90% # attempts to use FU when none available 1972system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.90% # attempts to use FU when none available 1973system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.90% # attempts to use FU when none available 1974system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.90% # attempts to use FU when none available 1975system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.90% # attempts to use FU when none available 1976system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.90% # attempts to use FU when none available 1977system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.90% # attempts to use FU when none available 1978system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.90% # attempts to use FU when none available 1979system.cpu1.iq.fu_full::MemRead 1614233 33.60% 63.50% # attempts to use FU when none available 1980system.cpu1.iq.fu_full::MemWrite 1753849 36.50% 100.00% # attempts to use FU when none available 1981system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1982system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1983system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued 1984system.cpu1.iq.FU_type_0::IntAlu 13143313 61.85% 61.85% # Type of FU issued 1985system.cpu1.iq.FU_type_0::IntMult 28154 0.13% 61.98% # Type of FU issued 1986system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.98% # Type of FU issued 1987system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.98% # Type of FU issued 1988system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.98% # Type of FU issued 1989system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.98% # Type of FU issued 1990system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.98% # Type of FU issued 1991system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.98% # Type of FU issued 1992system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.98% # Type of FU issued 1993system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.98% # Type of FU issued 1994system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.98% # Type of FU issued 1995system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.98% # Type of FU issued 1996system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.98% # Type of FU issued 1997system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.98% # Type of FU issued 1998system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.98% # Type of FU issued 1999system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.98% # Type of FU issued 2000system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.98% # Type of FU issued 2001system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.98% # Type of FU issued 2002system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.98% # Type of FU issued 2003system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.98% # Type of FU issued 2004system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.98% # Type of FU issued 2005system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.98% # Type of FU issued 2006system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.98% # Type of FU issued 2007system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.98% # Type of FU issued 2008system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.98% # Type of FU issued 2009system.cpu1.iq.FU_type_0::SimdFloatMisc 3291 0.02% 61.99% # Type of FU issued 2010system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.99% # Type of FU issued 2011system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.99% # Type of FU issued 2012system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.99% # Type of FU issued 2013system.cpu1.iq.FU_type_0::MemRead 4401591 20.71% 82.70% # Type of FU issued 2014system.cpu1.iq.FU_type_0::MemWrite 3675568 17.30% 100.00% # Type of FU issued 2015system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2016system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2017system.cpu1.iq.FU_type_0::total 21251983 # Type of FU issued 2018system.cpu1.iq.rate 0.609164 # Inst issue rate 2019system.cpu1.iq.fu_busy_cnt 4804685 # FU busy when requested 2020system.cpu1.iq.fu_busy_rate 0.226082 # FU busy rate (busy events/executed inst) 2021system.cpu1.iq.int_inst_queue_reads 81530573 # Number of integer instruction queue reads 2022system.cpu1.iq.int_inst_queue_writes 24059081 # Number of integer instruction queue writes 2023system.cpu1.iq.int_inst_queue_wakeup_accesses 20789563 # Number of integer instruction queue wakeup accesses 2024system.cpu1.iq.fp_inst_queue_reads 6251 # Number of floating instruction queue reads 2025system.cpu1.iq.fp_inst_queue_writes 2056 # Number of floating instruction queue writes 2026system.cpu1.iq.fp_inst_queue_wakeup_accesses 1789 # Number of floating instruction queue wakeup accesses 2027system.cpu1.iq.int_alu_accesses 26052476 # Number of integer alu accesses 2028system.cpu1.iq.fp_alu_accesses 4126 # Number of floating point alu accesses 2029system.cpu1.iew.lsq.thread0.forwLoads 87608 # Number of loads that had data forwarded from stores 2030system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2031system.cpu1.iew.lsq.thread0.squashedLoads 411817 # Number of loads squashed 2032system.cpu1.iew.lsq.thread0.ignoredResponses 594 # Number of memory responses ignored because the instruction is squashed 2033system.cpu1.iew.lsq.thread0.memOrderViolation 10183 # Number of memory ordering violations 2034system.cpu1.iew.lsq.thread0.squashedStores 255647 # Number of stores squashed 2035system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2036system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2037system.cpu1.iew.lsq.thread0.rescheduledLoads 40342 # Number of loads that were rescheduled 2038system.cpu1.iew.lsq.thread0.cacheBlocked 77877 # Number of times an access to memory failed due to the cache being blocked 2039system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2040system.cpu1.iew.iewSquashCycles 263768 # Number of cycles IEW is squashing 2041system.cpu1.iew.iewBlockCycles 542908 # Number of cycles IEW is blocking 2042system.cpu1.iew.iewUnblockCycles 100291 # Number of cycles IEW is unblocking 2043system.cpu1.iew.iewDispatchedInsts 22047493 # Number of instructions dispatched to IQ 2044system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 2045system.cpu1.iew.iewDispLoadInsts 4447920 # Number of dispatched load instructions 2046system.cpu1.iew.iewDispStoreInsts 3797613 # Number of dispatched store instructions 2047system.cpu1.iew.iewDispNonSpecInsts 296998 # Number of dispatched non-speculative instructions 2048system.cpu1.iew.iewIQFullEvents 7633 # Number of times the IQ has become full, causing a stall 2049system.cpu1.iew.iewLSQFullEvents 86238 # Number of times the LSQ has become full, causing a stall 2050system.cpu1.iew.memOrderViolationEvents 10183 # Number of memory order violations 2051system.cpu1.iew.predictedTakenIncorrect 34861 # Number of branches that were predicted taken incorrectly 2052system.cpu1.iew.predictedNotTakenIncorrect 119032 # Number of branches that were predicted not taken incorrectly 2053system.cpu1.iew.branchMispredicts 153893 # Number of branch mispredicts detected at execute 2054system.cpu1.iew.iewExecutedInsts 21020629 # Number of executed instructions 2055system.cpu1.iew.iewExecLoadInsts 4306114 # Number of load instructions executed 2056system.cpu1.iew.iewExecSquashedInsts 209967 # Number of squashed instructions skipped in execute 2057system.cpu1.iew.exec_swp 0 # number of swp insts executed 2058system.cpu1.iew.exec_nop 41057 # number of nop insts executed 2059system.cpu1.iew.exec_refs 7931495 # number of memory reference insts executed 2060system.cpu1.iew.exec_branches 3060021 # Number of branches executed 2061system.cpu1.iew.exec_stores 3625381 # Number of stores executed 2062system.cpu1.iew.exec_rate 0.602533 # Inst execution rate 2063system.cpu1.iew.wb_sent 20889464 # cumulative count of insts sent to commit 2064system.cpu1.iew.wb_count 20791352 # cumulative count of insts written-back 2065system.cpu1.iew.wb_producers 10424214 # num instructions producing a value 2066system.cpu1.iew.wb_consumers 16342751 # num instructions consuming a value 2067system.cpu1.iew.wb_rate 0.595961 # insts written-back per cycle 2068system.cpu1.iew.wb_fanout 0.637849 # average fanout of values written-back 2069system.cpu1.commit.commitSquashedInsts 1830942 # The number of squashed insts skipped by commit 2070system.cpu1.commit.commitNonSpecStalls 516700 # The number of times commit has been forced to stall to communicate backwards 2071system.cpu1.commit.branchMispredicts 142734 # The number of times a branch was mispredicted 2072system.cpu1.commit.committed_per_cycle::samples 33726190 # Number of insts commited each cycle 2073system.cpu1.commit.committed_per_cycle::mean 0.592855 # Number of insts commited each cycle 2074system.cpu1.commit.committed_per_cycle::stdev 1.351829 # Number of insts commited each cycle 2075system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2076system.cpu1.commit.committed_per_cycle::0 24181138 71.70% 71.70% # Number of insts commited each cycle 2077system.cpu1.commit.committed_per_cycle::1 5602280 16.61% 88.31% # Number of insts commited each cycle 2078system.cpu1.commit.committed_per_cycle::2 1689893 5.01% 93.32% # Number of insts commited each cycle 2079system.cpu1.commit.committed_per_cycle::3 666101 1.98% 95.30% # Number of insts commited each cycle 2080system.cpu1.commit.committed_per_cycle::4 523339 1.55% 96.85% # Number of insts commited each cycle 2081system.cpu1.commit.committed_per_cycle::5 342031 1.01% 97.86% # Number of insts commited each cycle 2082system.cpu1.commit.committed_per_cycle::6 220744 0.65% 98.52% # Number of insts commited each cycle 2083system.cpu1.commit.committed_per_cycle::7 118908 0.35% 98.87% # Number of insts commited each cycle 2084system.cpu1.commit.committed_per_cycle::8 381756 1.13% 100.00% # Number of insts commited each cycle 2085system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2086system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2087system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2088system.cpu1.commit.committed_per_cycle::total 33726190 # Number of insts commited each cycle 2089system.cpu1.commit.committedInsts 16334743 # Number of instructions committed 2090system.cpu1.commit.committedOps 19994748 # Number of ops (including micro ops) committed 2091system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 2092system.cpu1.commit.refs 7578069 # Number of memory references committed 2093system.cpu1.commit.loads 4036103 # Number of loads committed 2094system.cpu1.commit.membars 208295 # Number of memory barriers committed 2095system.cpu1.commit.branches 2905369 # Number of branches committed 2096system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. 2097system.cpu1.commit.int_insts 17763800 # Number of committed integer instructions. 2098system.cpu1.commit.function_calls 462325 # Number of function calls committed. 2099system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 2100system.cpu1.commit.op_class_0::IntAlu 12386323 61.95% 61.95% # Class of committed instruction 2101system.cpu1.commit.op_class_0::IntMult 27065 0.14% 62.08% # Class of committed instruction 2102system.cpu1.commit.op_class_0::IntDiv 0 0.00% 62.08% # Class of committed instruction 2103system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 62.08% # Class of committed instruction 2104system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 62.08% # Class of committed instruction 2105system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 62.08% # Class of committed instruction 2106system.cpu1.commit.op_class_0::FloatMult 0 0.00% 62.08% # Class of committed instruction 2107system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 62.08% # Class of committed instruction 2108system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 62.08% # Class of committed instruction 2109system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 62.08% # Class of committed instruction 2110system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 62.08% # Class of committed instruction 2111system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 62.08% # Class of committed instruction 2112system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 62.08% # Class of committed instruction 2113system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 62.08% # Class of committed instruction 2114system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 62.08% # Class of committed instruction 2115system.cpu1.commit.op_class_0::SimdMult 0 0.00% 62.08% # Class of committed instruction 2116system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 62.08% # Class of committed instruction 2117system.cpu1.commit.op_class_0::SimdShift 0 0.00% 62.08% # Class of committed instruction 2118system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 62.08% # Class of committed instruction 2119system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 62.08% # Class of committed instruction 2120system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 62.08% # Class of committed instruction 2121system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 62.08% # Class of committed instruction 2122system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 62.08% # Class of committed instruction 2123system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 62.08% # Class of committed instruction 2124system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 62.08% # Class of committed instruction 2125system.cpu1.commit.op_class_0::SimdFloatMisc 3291 0.02% 62.10% # Class of committed instruction 2126system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 62.10% # Class of committed instruction 2127system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.10% # Class of committed instruction 2128system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.10% # Class of committed instruction 2129system.cpu1.commit.op_class_0::MemRead 4036103 20.19% 82.29% # Class of committed instruction 2130system.cpu1.commit.op_class_0::MemWrite 3541966 17.71% 100.00% # Class of committed instruction 2131system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2132system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2133system.cpu1.commit.op_class_0::total 19994748 # Class of committed instruction 2134system.cpu1.commit.bw_lim_events 381756 # number cycles where commit BW limit reached 2135system.cpu1.rob.rob_reads 54190677 # The number of ROB reads 2136system.cpu1.rob.rob_writes 44052640 # The number of ROB writes 2137system.cpu1.timesIdled 55343 # Number of times that the entire CPU went into an idle state and unscheduled itself 2138system.cpu1.idleCycles 750940 # Total number of cycles that the CPU has spent unscheduled due to idling 2139system.cpu1.quiesceCycles 5616474700 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2140system.cpu1.committedInsts 16301888 # Number of Instructions Simulated 2141system.cpu1.committedOps 19961893 # Number of Ops (including micro ops) Simulated 2142system.cpu1.cpi 2.140066 # CPI: Cycles Per Instruction 2143system.cpu1.cpi_total 2.140066 # CPI: Total CPI of All Threads 2144system.cpu1.ipc 0.467275 # IPC: Instructions Per Cycle 2145system.cpu1.ipc_total 0.467275 # IPC: Total IPC of All Threads 2146system.cpu1.int_regfile_reads 23580432 # number of integer regfile reads 2147system.cpu1.int_regfile_writes 13478394 # number of integer regfile writes 2148system.cpu1.fp_regfile_reads 1401 # number of floating regfile reads 2149system.cpu1.fp_regfile_writes 516 # number of floating regfile writes 2150system.cpu1.cc_regfile_reads 75464831 # number of cc regfile reads 2151system.cpu1.cc_regfile_writes 6816973 # number of cc regfile writes 2152system.cpu1.misc_regfile_reads 66091366 # number of misc regfile reads 2153system.cpu1.misc_regfile_writes 387254 # number of misc regfile writes 2154system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2155system.cpu1.dcache.tags.replacements 189214 # number of replacements 2156system.cpu1.dcache.tags.tagsinuse 472.223119 # Cycle average of tags in use 2157system.cpu1.dcache.tags.total_refs 6799121 # Total number of references to valid blocks. 2158system.cpu1.dcache.tags.sampled_refs 189549 # Sample count of references to valid blocks. 2159system.cpu1.dcache.tags.avg_refs 35.869991 # Average number of references to valid blocks. 2160system.cpu1.dcache.tags.warmup_cycle 103707030000 # Cycle when the warmup percentage was hit. 2161system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.223119 # Average occupied blocks per requestor 2162system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922311 # Average percentage of cache occupancy 2163system.cpu1.dcache.tags.occ_percent::total 0.922311 # Average percentage of cache occupancy 2164system.cpu1.dcache.tags.occ_task_id_blocks::1024 335 # Occupied blocks per task id 2165system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id 2166system.cpu1.dcache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id 2167system.cpu1.dcache.tags.occ_task_id_percent::1024 0.654297 # Percentage of cache occupancy per task id 2168system.cpu1.dcache.tags.tag_accesses 15096738 # Number of tag accesses 2169system.cpu1.dcache.tags.data_accesses 15096738 # Number of data accesses 2170system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2171system.cpu1.dcache.ReadReq_hits::cpu1.data 3630827 # number of ReadReq hits 2172system.cpu1.dcache.ReadReq_hits::total 3630827 # number of ReadReq hits 2173system.cpu1.dcache.WriteReq_hits::cpu1.data 2915447 # number of WriteReq hits 2174system.cpu1.dcache.WriteReq_hits::total 2915447 # number of WriteReq hits 2175system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48893 # number of SoftPFReq hits 2176system.cpu1.dcache.SoftPFReq_hits::total 48893 # number of SoftPFReq hits 2177system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78128 # number of LoadLockedReq hits 2178system.cpu1.dcache.LoadLockedReq_hits::total 78128 # number of LoadLockedReq hits 2179system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70537 # number of StoreCondReq hits 2180system.cpu1.dcache.StoreCondReq_hits::total 70537 # number of StoreCondReq hits 2181system.cpu1.dcache.demand_hits::cpu1.data 6546274 # number of demand (read+write) hits 2182system.cpu1.dcache.demand_hits::total 6546274 # number of demand (read+write) hits 2183system.cpu1.dcache.overall_hits::cpu1.data 6595167 # number of overall hits 2184system.cpu1.dcache.overall_hits::total 6595167 # number of overall hits 2185system.cpu1.dcache.ReadReq_misses::cpu1.data 215923 # number of ReadReq misses 2186system.cpu1.dcache.ReadReq_misses::total 215923 # number of ReadReq misses 2187system.cpu1.dcache.WriteReq_misses::cpu1.data 399880 # number of WriteReq misses 2188system.cpu1.dcache.WriteReq_misses::total 399880 # number of WriteReq misses 2189system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30250 # number of SoftPFReq misses 2190system.cpu1.dcache.SoftPFReq_misses::total 30250 # number of SoftPFReq misses 2191system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18610 # number of LoadLockedReq misses 2192system.cpu1.dcache.LoadLockedReq_misses::total 18610 # number of LoadLockedReq misses 2193system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23458 # number of StoreCondReq misses 2194system.cpu1.dcache.StoreCondReq_misses::total 23458 # number of StoreCondReq misses 2195system.cpu1.dcache.demand_misses::cpu1.data 615803 # number of demand (read+write) misses 2196system.cpu1.dcache.demand_misses::total 615803 # number of demand (read+write) misses 2197system.cpu1.dcache.overall_misses::cpu1.data 646053 # number of overall misses 2198system.cpu1.dcache.overall_misses::total 646053 # number of overall misses 2199system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3499498000 # number of ReadReq miss cycles 2200system.cpu1.dcache.ReadReq_miss_latency::total 3499498000 # number of ReadReq miss cycles 2201system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10163021954 # number of WriteReq miss cycles 2202system.cpu1.dcache.WriteReq_miss_latency::total 10163021954 # number of WriteReq miss cycles 2203system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 366635500 # number of LoadLockedReq miss cycles 2204system.cpu1.dcache.LoadLockedReq_miss_latency::total 366635500 # number of LoadLockedReq miss cycles 2205system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 572131000 # number of StoreCondReq miss cycles 2206system.cpu1.dcache.StoreCondReq_miss_latency::total 572131000 # number of StoreCondReq miss cycles 2207system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1270000 # number of StoreCondFailReq miss cycles 2208system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1270000 # number of StoreCondFailReq miss cycles 2209system.cpu1.dcache.demand_miss_latency::cpu1.data 13662519954 # number of demand (read+write) miss cycles 2210system.cpu1.dcache.demand_miss_latency::total 13662519954 # number of demand (read+write) miss cycles 2211system.cpu1.dcache.overall_miss_latency::cpu1.data 13662519954 # number of overall miss cycles 2212system.cpu1.dcache.overall_miss_latency::total 13662519954 # number of overall miss cycles 2213system.cpu1.dcache.ReadReq_accesses::cpu1.data 3846750 # number of ReadReq accesses(hits+misses) 2214system.cpu1.dcache.ReadReq_accesses::total 3846750 # number of ReadReq accesses(hits+misses) 2215system.cpu1.dcache.WriteReq_accesses::cpu1.data 3315327 # number of WriteReq accesses(hits+misses) 2216system.cpu1.dcache.WriteReq_accesses::total 3315327 # number of WriteReq accesses(hits+misses) 2217system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79143 # number of SoftPFReq accesses(hits+misses) 2218system.cpu1.dcache.SoftPFReq_accesses::total 79143 # number of SoftPFReq accesses(hits+misses) 2219system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96738 # number of LoadLockedReq accesses(hits+misses) 2220system.cpu1.dcache.LoadLockedReq_accesses::total 96738 # number of LoadLockedReq accesses(hits+misses) 2221system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93995 # number of StoreCondReq accesses(hits+misses) 2222system.cpu1.dcache.StoreCondReq_accesses::total 93995 # number of StoreCondReq accesses(hits+misses) 2223system.cpu1.dcache.demand_accesses::cpu1.data 7162077 # number of demand (read+write) accesses 2224system.cpu1.dcache.demand_accesses::total 7162077 # number of demand (read+write) accesses 2225system.cpu1.dcache.overall_accesses::cpu1.data 7241220 # number of overall (read+write) accesses 2226system.cpu1.dcache.overall_accesses::total 7241220 # number of overall (read+write) accesses 2227system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.056131 # miss rate for ReadReq accesses 2228system.cpu1.dcache.ReadReq_miss_rate::total 0.056131 # miss rate for ReadReq accesses 2229system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.120616 # miss rate for WriteReq accesses 2230system.cpu1.dcache.WriteReq_miss_rate::total 0.120616 # miss rate for WriteReq accesses 2231system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382220 # miss rate for SoftPFReq accesses 2232system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382220 # miss rate for SoftPFReq accesses 2233system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.192375 # miss rate for LoadLockedReq accesses 2234system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.192375 # miss rate for LoadLockedReq accesses 2235system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249566 # miss rate for StoreCondReq accesses 2236system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249566 # miss rate for StoreCondReq accesses 2237system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085981 # miss rate for demand accesses 2238system.cpu1.dcache.demand_miss_rate::total 0.085981 # miss rate for demand accesses 2239system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089219 # miss rate for overall accesses 2240system.cpu1.dcache.overall_miss_rate::total 0.089219 # miss rate for overall accesses 2241system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16207.157181 # average ReadReq miss latency 2242system.cpu1.dcache.ReadReq_avg_miss_latency::total 16207.157181 # average ReadReq miss latency 2243system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25415.179439 # average WriteReq miss latency 2244system.cpu1.dcache.WriteReq_avg_miss_latency::total 25415.179439 # average WriteReq miss latency 2245system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19700.994089 # average LoadLockedReq miss latency 2246system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19700.994089 # average LoadLockedReq miss latency 2247system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24389.589905 # average StoreCondReq miss latency 2248system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24389.589905 # average StoreCondReq miss latency 2249system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2250system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2251system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22186.510871 # average overall miss latency 2252system.cpu1.dcache.demand_avg_miss_latency::total 22186.510871 # average overall miss latency 2253system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21147.676667 # average overall miss latency 2254system.cpu1.dcache.overall_avg_miss_latency::total 21147.676667 # average overall miss latency 2255system.cpu1.dcache.blocked_cycles::no_mshrs 397 # number of cycles access was blocked 2256system.cpu1.dcache.blocked_cycles::no_targets 1522509 # number of cycles access was blocked 2257system.cpu1.dcache.blocked::no_mshrs 39 # number of cycles access was blocked 2258system.cpu1.dcache.blocked::no_targets 40277 # number of cycles access was blocked 2259system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10.179487 # average number of cycles each access was blocked 2260system.cpu1.dcache.avg_blocked_cycles::no_targets 37.800953 # average number of cycles each access was blocked 2261system.cpu1.dcache.writebacks::writebacks 189214 # number of writebacks 2262system.cpu1.dcache.writebacks::total 189214 # number of writebacks 2263system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79118 # number of ReadReq MSHR hits 2264system.cpu1.dcache.ReadReq_mshr_hits::total 79118 # number of ReadReq MSHR hits 2265system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 308913 # number of WriteReq MSHR hits 2266system.cpu1.dcache.WriteReq_mshr_hits::total 308913 # number of WriteReq MSHR hits 2267system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13245 # number of LoadLockedReq MSHR hits 2268system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13245 # number of LoadLockedReq MSHR hits 2269system.cpu1.dcache.demand_mshr_hits::cpu1.data 388031 # number of demand (read+write) MSHR hits 2270system.cpu1.dcache.demand_mshr_hits::total 388031 # number of demand (read+write) MSHR hits 2271system.cpu1.dcache.overall_mshr_hits::cpu1.data 388031 # number of overall MSHR hits 2272system.cpu1.dcache.overall_mshr_hits::total 388031 # number of overall MSHR hits 2273system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 136805 # number of ReadReq MSHR misses 2274system.cpu1.dcache.ReadReq_mshr_misses::total 136805 # number of ReadReq MSHR misses 2275system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90967 # number of WriteReq MSHR misses 2276system.cpu1.dcache.WriteReq_mshr_misses::total 90967 # number of WriteReq MSHR misses 2277system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28906 # number of SoftPFReq MSHR misses 2278system.cpu1.dcache.SoftPFReq_mshr_misses::total 28906 # number of SoftPFReq MSHR misses 2279system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5365 # number of LoadLockedReq MSHR misses 2280system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5365 # number of LoadLockedReq MSHR misses 2281system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23458 # number of StoreCondReq MSHR misses 2282system.cpu1.dcache.StoreCondReq_mshr_misses::total 23458 # number of StoreCondReq MSHR misses 2283system.cpu1.dcache.demand_mshr_misses::cpu1.data 227772 # number of demand (read+write) MSHR misses 2284system.cpu1.dcache.demand_mshr_misses::total 227772 # number of demand (read+write) MSHR misses 2285system.cpu1.dcache.overall_mshr_misses::cpu1.data 256678 # number of overall MSHR misses 2286system.cpu1.dcache.overall_mshr_misses::total 256678 # number of overall MSHR misses 2287system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3078 # number of ReadReq MSHR uncacheable 2288system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3078 # number of ReadReq MSHR uncacheable 2289system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2435 # number of WriteReq MSHR uncacheable 2290system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2435 # number of WriteReq MSHR uncacheable 2291system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5513 # number of overall MSHR uncacheable misses 2292system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5513 # number of overall MSHR uncacheable misses 2293system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1918091000 # number of ReadReq MSHR miss cycles 2294system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1918091000 # number of ReadReq MSHR miss cycles 2295system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2479606465 # number of WriteReq MSHR miss cycles 2296system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2479606465 # number of WriteReq MSHR miss cycles 2297system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 495967500 # number of SoftPFReq MSHR miss cycles 2298system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 495967500 # number of SoftPFReq MSHR miss cycles 2299system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 96498000 # number of LoadLockedReq MSHR miss cycles 2300system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 96498000 # number of LoadLockedReq MSHR miss cycles 2301system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 548698000 # number of StoreCondReq MSHR miss cycles 2302system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 548698000 # number of StoreCondReq MSHR miss cycles 2303system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1245000 # number of StoreCondFailReq MSHR miss cycles 2304system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1245000 # number of StoreCondFailReq MSHR miss cycles 2305system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4397697465 # number of demand (read+write) MSHR miss cycles 2306system.cpu1.dcache.demand_mshr_miss_latency::total 4397697465 # number of demand (read+write) MSHR miss cycles 2307system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4893664965 # number of overall MSHR miss cycles 2308system.cpu1.dcache.overall_mshr_miss_latency::total 4893664965 # number of overall MSHR miss cycles 2309system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 441985000 # number of ReadReq MSHR uncacheable cycles 2310system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 441985000 # number of ReadReq MSHR uncacheable cycles 2311system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 441985000 # number of overall MSHR uncacheable cycles 2312system.cpu1.dcache.overall_mshr_uncacheable_latency::total 441985000 # number of overall MSHR uncacheable cycles 2313system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035564 # mshr miss rate for ReadReq accesses 2314system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035564 # mshr miss rate for ReadReq accesses 2315system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027438 # mshr miss rate for WriteReq accesses 2316system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027438 # mshr miss rate for WriteReq accesses 2317system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.365238 # mshr miss rate for SoftPFReq accesses 2318system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.365238 # mshr miss rate for SoftPFReq accesses 2319system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055459 # mshr miss rate for LoadLockedReq accesses 2320system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055459 # mshr miss rate for LoadLockedReq accesses 2321system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249566 # mshr miss rate for StoreCondReq accesses 2322system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249566 # mshr miss rate for StoreCondReq accesses 2323system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031803 # mshr miss rate for demand accesses 2324system.cpu1.dcache.demand_mshr_miss_rate::total 0.031803 # mshr miss rate for demand accesses 2325system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035447 # mshr miss rate for overall accesses 2326system.cpu1.dcache.overall_mshr_miss_rate::total 0.035447 # mshr miss rate for overall accesses 2327system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14020.620591 # average ReadReq mshr miss latency 2328system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14020.620591 # average ReadReq mshr miss latency 2329system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27258.307573 # average WriteReq mshr miss latency 2330system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27258.307573 # average WriteReq mshr miss latency 2331system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17157.942988 # average SoftPFReq mshr miss latency 2332system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17157.942988 # average SoftPFReq mshr miss latency 2333system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17986.579683 # average LoadLockedReq mshr miss latency 2334system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17986.579683 # average LoadLockedReq mshr miss latency 2335system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23390.655640 # average StoreCondReq mshr miss latency 2336system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23390.655640 # average StoreCondReq mshr miss latency 2337system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2338system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2339system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19307.454231 # average overall mshr miss latency 2340system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19307.454231 # average overall mshr miss latency 2341system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19065.385288 # average overall mshr miss latency 2342system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19065.385288 # average overall mshr miss latency 2343system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143594.866797 # average ReadReq mshr uncacheable latency 2344system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143594.866797 # average ReadReq mshr uncacheable latency 2345system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80171.413024 # average overall mshr uncacheable latency 2346system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80171.413024 # average overall mshr uncacheable latency 2347system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2348system.cpu1.icache.tags.replacements 585593 # number of replacements 2349system.cpu1.icache.tags.tagsinuse 499.448296 # Cycle average of tags in use 2350system.cpu1.icache.tags.total_refs 7643805 # Total number of references to valid blocks. 2351system.cpu1.icache.tags.sampled_refs 586105 # Sample count of references to valid blocks. 2352system.cpu1.icache.tags.avg_refs 13.041699 # Average number of references to valid blocks. 2353system.cpu1.icache.tags.warmup_cycle 79061349000 # Cycle when the warmup percentage was hit. 2354system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.448296 # Average occupied blocks per requestor 2355system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975485 # Average percentage of cache occupancy 2356system.cpu1.icache.tags.occ_percent::total 0.975485 # Average percentage of cache occupancy 2357system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2358system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id 2359system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id 2360system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2361system.cpu1.icache.tags.tag_accesses 17090093 # Number of tag accesses 2362system.cpu1.icache.tags.data_accesses 17090093 # Number of data accesses 2363system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2364system.cpu1.icache.ReadReq_hits::cpu1.inst 7643805 # number of ReadReq hits 2365system.cpu1.icache.ReadReq_hits::total 7643805 # number of ReadReq hits 2366system.cpu1.icache.demand_hits::cpu1.inst 7643805 # number of demand (read+write) hits 2367system.cpu1.icache.demand_hits::total 7643805 # number of demand (read+write) hits 2368system.cpu1.icache.overall_hits::cpu1.inst 7643805 # number of overall hits 2369system.cpu1.icache.overall_hits::total 7643805 # number of overall hits 2370system.cpu1.icache.ReadReq_misses::cpu1.inst 608184 # number of ReadReq misses 2371system.cpu1.icache.ReadReq_misses::total 608184 # number of ReadReq misses 2372system.cpu1.icache.demand_misses::cpu1.inst 608184 # number of demand (read+write) misses 2373system.cpu1.icache.demand_misses::total 608184 # number of demand (read+write) misses 2374system.cpu1.icache.overall_misses::cpu1.inst 608184 # number of overall misses 2375system.cpu1.icache.overall_misses::total 608184 # number of overall misses 2376system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5475305711 # number of ReadReq miss cycles 2377system.cpu1.icache.ReadReq_miss_latency::total 5475305711 # number of ReadReq miss cycles 2378system.cpu1.icache.demand_miss_latency::cpu1.inst 5475305711 # number of demand (read+write) miss cycles 2379system.cpu1.icache.demand_miss_latency::total 5475305711 # number of demand (read+write) miss cycles 2380system.cpu1.icache.overall_miss_latency::cpu1.inst 5475305711 # number of overall miss cycles 2381system.cpu1.icache.overall_miss_latency::total 5475305711 # number of overall miss cycles 2382system.cpu1.icache.ReadReq_accesses::cpu1.inst 8251989 # number of ReadReq accesses(hits+misses) 2383system.cpu1.icache.ReadReq_accesses::total 8251989 # number of ReadReq accesses(hits+misses) 2384system.cpu1.icache.demand_accesses::cpu1.inst 8251989 # number of demand (read+write) accesses 2385system.cpu1.icache.demand_accesses::total 8251989 # number of demand (read+write) accesses 2386system.cpu1.icache.overall_accesses::cpu1.inst 8251989 # number of overall (read+write) accesses 2387system.cpu1.icache.overall_accesses::total 8251989 # number of overall (read+write) accesses 2388system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073702 # miss rate for ReadReq accesses 2389system.cpu1.icache.ReadReq_miss_rate::total 0.073702 # miss rate for ReadReq accesses 2390system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073702 # miss rate for demand accesses 2391system.cpu1.icache.demand_miss_rate::total 0.073702 # miss rate for demand accesses 2392system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073702 # miss rate for overall accesses 2393system.cpu1.icache.overall_miss_rate::total 0.073702 # miss rate for overall accesses 2394system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9002.712520 # average ReadReq miss latency 2395system.cpu1.icache.ReadReq_avg_miss_latency::total 9002.712520 # average ReadReq miss latency 2396system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9002.712520 # average overall miss latency 2397system.cpu1.icache.demand_avg_miss_latency::total 9002.712520 # average overall miss latency 2398system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9002.712520 # average overall miss latency 2399system.cpu1.icache.overall_avg_miss_latency::total 9002.712520 # average overall miss latency 2400system.cpu1.icache.blocked_cycles::no_mshrs 487413 # number of cycles access was blocked 2401system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2402system.cpu1.icache.blocked::no_mshrs 41153 # number of cycles access was blocked 2403system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 2404system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.843924 # average number of cycles each access was blocked 2405system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2406system.cpu1.icache.writebacks::writebacks 585593 # number of writebacks 2407system.cpu1.icache.writebacks::total 585593 # number of writebacks 2408system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22069 # number of ReadReq MSHR hits 2409system.cpu1.icache.ReadReq_mshr_hits::total 22069 # number of ReadReq MSHR hits 2410system.cpu1.icache.demand_mshr_hits::cpu1.inst 22069 # number of demand (read+write) MSHR hits 2411system.cpu1.icache.demand_mshr_hits::total 22069 # number of demand (read+write) MSHR hits 2412system.cpu1.icache.overall_mshr_hits::cpu1.inst 22069 # number of overall MSHR hits 2413system.cpu1.icache.overall_mshr_hits::total 22069 # number of overall MSHR hits 2414system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 586115 # number of ReadReq MSHR misses 2415system.cpu1.icache.ReadReq_mshr_misses::total 586115 # number of ReadReq MSHR misses 2416system.cpu1.icache.demand_mshr_misses::cpu1.inst 586115 # number of demand (read+write) MSHR misses 2417system.cpu1.icache.demand_mshr_misses::total 586115 # number of demand (read+write) MSHR misses 2418system.cpu1.icache.overall_mshr_misses::cpu1.inst 586115 # number of overall MSHR misses 2419system.cpu1.icache.overall_mshr_misses::total 586115 # number of overall MSHR misses 2420system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable 2421system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable 2422system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses 2423system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses 2424system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5018314097 # number of ReadReq MSHR miss cycles 2425system.cpu1.icache.ReadReq_mshr_miss_latency::total 5018314097 # number of ReadReq MSHR miss cycles 2426system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5018314097 # number of demand (read+write) MSHR miss cycles 2427system.cpu1.icache.demand_mshr_miss_latency::total 5018314097 # number of demand (read+write) MSHR miss cycles 2428system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5018314097 # number of overall MSHR miss cycles 2429system.cpu1.icache.overall_mshr_miss_latency::total 5018314097 # number of overall MSHR miss cycles 2430system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9229000 # number of ReadReq MSHR uncacheable cycles 2431system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9229000 # number of ReadReq MSHR uncacheable cycles 2432system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9229000 # number of overall MSHR uncacheable cycles 2433system.cpu1.icache.overall_mshr_uncacheable_latency::total 9229000 # number of overall MSHR uncacheable cycles 2434system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071027 # mshr miss rate for ReadReq accesses 2435system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071027 # mshr miss rate for ReadReq accesses 2436system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071027 # mshr miss rate for demand accesses 2437system.cpu1.icache.demand_mshr_miss_rate::total 0.071027 # mshr miss rate for demand accesses 2438system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071027 # mshr miss rate for overall accesses 2439system.cpu1.icache.overall_mshr_miss_rate::total 0.071027 # mshr miss rate for overall accesses 2440system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8561.995678 # average ReadReq mshr miss latency 2441system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8561.995678 # average ReadReq mshr miss latency 2442system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8561.995678 # average overall mshr miss latency 2443system.cpu1.icache.demand_avg_mshr_miss_latency::total 8561.995678 # average overall mshr miss latency 2444system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8561.995678 # average overall mshr miss latency 2445system.cpu1.icache.overall_avg_mshr_miss_latency::total 8561.995678 # average overall mshr miss latency 2446system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90480.392157 # average ReadReq mshr uncacheable latency 2447system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90480.392157 # average ReadReq mshr uncacheable latency 2448system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90480.392157 # average overall mshr uncacheable latency 2449system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90480.392157 # average overall mshr uncacheable latency 2450system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2451system.cpu1.l2cache.prefetcher.num_hwpf_issued 204984 # number of hwpf issued 2452system.cpu1.l2cache.prefetcher.pfIdentified 205710 # number of prefetch candidates identified 2453system.cpu1.l2cache.prefetcher.pfBufferHit 651 # number of redundant prefetches already in prefetch queue 2454system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2455system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2456system.cpu1.l2cache.prefetcher.pfSpanPage 59802 # number of prefetches not generated due to page crossing 2457system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2458system.cpu1.l2cache.tags.replacements 51951 # number of replacements 2459system.cpu1.l2cache.tags.tagsinuse 15270.218898 # Cycle average of tags in use 2460system.cpu1.l2cache.tags.total_refs 1330892 # Total number of references to valid blocks. 2461system.cpu1.l2cache.tags.sampled_refs 66549 # Sample count of references to valid blocks. 2462system.cpu1.l2cache.tags.avg_refs 19.998678 # Average number of references to valid blocks. 2463system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2464system.cpu1.l2cache.tags.occ_blocks::writebacks 14780.960176 # Average occupied blocks per requestor 2465system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 15.872611 # Average occupied blocks per requestor 2466system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.970486 # Average occupied blocks per requestor 2467system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 470.415625 # Average occupied blocks per requestor 2468system.cpu1.l2cache.tags.occ_percent::writebacks 0.902158 # Average percentage of cache occupancy 2469system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000969 # Average percentage of cache occupancy 2470system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000181 # Average percentage of cache occupancy 2471system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.028712 # Average percentage of cache occupancy 2472system.cpu1.l2cache.tags.occ_percent::total 0.932020 # Average percentage of cache occupancy 2473system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1023 # Occupied blocks per task id 2474system.cpu1.l2cache.tags.occ_task_id_blocks::1023 34 # Occupied blocks per task id 2475system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13541 # Occupied blocks per task id 2476system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 11 # Occupied blocks per task id 2477system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 870 # Occupied blocks per task id 2478system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 142 # Occupied blocks per task id 2479system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id 2480system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id 2481system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id 2482system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id 2483system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8705 # Occupied blocks per task id 2484system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4388 # Occupied blocks per task id 2485system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.062439 # Percentage of cache occupancy per task id 2486system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002075 # Percentage of cache occupancy per task id 2487system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.826477 # Percentage of cache occupancy per task id 2488system.cpu1.l2cache.tags.tag_accesses 26699823 # Number of tag accesses 2489system.cpu1.l2cache.tags.data_accesses 26699823 # Number of data accesses 2490system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2491system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16755 # number of ReadReq hits 2492system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6229 # number of ReadReq hits 2493system.cpu1.l2cache.ReadReq_hits::total 22984 # number of ReadReq hits 2494system.cpu1.l2cache.WritebackDirty_hits::writebacks 115107 # number of WritebackDirty hits 2495system.cpu1.l2cache.WritebackDirty_hits::total 115107 # number of WritebackDirty hits 2496system.cpu1.l2cache.WritebackClean_hits::writebacks 647294 # number of WritebackClean hits 2497system.cpu1.l2cache.WritebackClean_hits::total 647294 # number of WritebackClean hits 2498system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27150 # number of ReadExReq hits 2499system.cpu1.l2cache.ReadExReq_hits::total 27150 # number of ReadExReq hits 2500system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 570057 # number of ReadCleanReq hits 2501system.cpu1.l2cache.ReadCleanReq_hits::total 570057 # number of ReadCleanReq hits 2502system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 101740 # number of ReadSharedReq hits 2503system.cpu1.l2cache.ReadSharedReq_hits::total 101740 # number of ReadSharedReq hits 2504system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16755 # number of demand (read+write) hits 2505system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6229 # number of demand (read+write) hits 2506system.cpu1.l2cache.demand_hits::cpu1.inst 570057 # number of demand (read+write) hits 2507system.cpu1.l2cache.demand_hits::cpu1.data 128890 # number of demand (read+write) hits 2508system.cpu1.l2cache.demand_hits::total 721931 # number of demand (read+write) hits 2509system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16755 # number of overall hits 2510system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6229 # number of overall hits 2511system.cpu1.l2cache.overall_hits::cpu1.inst 570057 # number of overall hits 2512system.cpu1.l2cache.overall_hits::cpu1.data 128890 # number of overall hits 2513system.cpu1.l2cache.overall_hits::total 721931 # number of overall hits 2514system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 448 # number of ReadReq misses 2515system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 243 # number of ReadReq misses 2516system.cpu1.l2cache.ReadReq_misses::total 691 # number of ReadReq misses 2517system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29892 # number of UpgradeReq misses 2518system.cpu1.l2cache.UpgradeReq_misses::total 29892 # number of UpgradeReq misses 2519system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23453 # number of SCUpgradeReq misses 2520system.cpu1.l2cache.SCUpgradeReq_misses::total 23453 # number of SCUpgradeReq misses 2521system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses 2522system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 2523system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34596 # number of ReadExReq misses 2524system.cpu1.l2cache.ReadExReq_misses::total 34596 # number of ReadExReq misses 2525system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 16047 # number of ReadCleanReq misses 2526system.cpu1.l2cache.ReadCleanReq_misses::total 16047 # number of ReadCleanReq misses 2527system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69320 # number of ReadSharedReq misses 2528system.cpu1.l2cache.ReadSharedReq_misses::total 69320 # number of ReadSharedReq misses 2529system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 448 # number of demand (read+write) misses 2530system.cpu1.l2cache.demand_misses::cpu1.itb.walker 243 # number of demand (read+write) misses 2531system.cpu1.l2cache.demand_misses::cpu1.inst 16047 # number of demand (read+write) misses 2532system.cpu1.l2cache.demand_misses::cpu1.data 103916 # number of demand (read+write) misses 2533system.cpu1.l2cache.demand_misses::total 120654 # number of demand (read+write) misses 2534system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 448 # number of overall misses 2535system.cpu1.l2cache.overall_misses::cpu1.itb.walker 243 # number of overall misses 2536system.cpu1.l2cache.overall_misses::cpu1.inst 16047 # number of overall misses 2537system.cpu1.l2cache.overall_misses::cpu1.data 103916 # number of overall misses 2538system.cpu1.l2cache.overall_misses::total 120654 # number of overall misses 2539system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9860500 # number of ReadReq miss cycles 2540system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5063000 # number of ReadReq miss cycles 2541system.cpu1.l2cache.ReadReq_miss_latency::total 14923500 # number of ReadReq miss cycles 2542system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 63584500 # number of UpgradeReq miss cycles 2543system.cpu1.l2cache.UpgradeReq_miss_latency::total 63584500 # number of UpgradeReq miss cycles 2544system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 34923000 # number of SCUpgradeReq miss cycles 2545system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 34923000 # number of SCUpgradeReq miss cycles 2546system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1206498 # number of SCUpgradeFailReq miss cycles 2547system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1206498 # number of SCUpgradeFailReq miss cycles 2548system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1459821998 # number of ReadExReq miss cycles 2549system.cpu1.l2cache.ReadExReq_miss_latency::total 1459821998 # number of ReadExReq miss cycles 2550system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 658205000 # number of ReadCleanReq miss cycles 2551system.cpu1.l2cache.ReadCleanReq_miss_latency::total 658205000 # number of ReadCleanReq miss cycles 2552system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1571289999 # number of ReadSharedReq miss cycles 2553system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1571289999 # number of ReadSharedReq miss cycles 2554system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9860500 # number of demand (read+write) miss cycles 2555system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5063000 # number of demand (read+write) miss cycles 2556system.cpu1.l2cache.demand_miss_latency::cpu1.inst 658205000 # number of demand (read+write) miss cycles 2557system.cpu1.l2cache.demand_miss_latency::cpu1.data 3031111997 # number of demand (read+write) miss cycles 2558system.cpu1.l2cache.demand_miss_latency::total 3704240497 # number of demand (read+write) miss cycles 2559system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9860500 # number of overall miss cycles 2560system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5063000 # number of overall miss cycles 2561system.cpu1.l2cache.overall_miss_latency::cpu1.inst 658205000 # number of overall miss cycles 2562system.cpu1.l2cache.overall_miss_latency::cpu1.data 3031111997 # number of overall miss cycles 2563system.cpu1.l2cache.overall_miss_latency::total 3704240497 # number of overall miss cycles 2564system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17203 # number of ReadReq accesses(hits+misses) 2565system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 6472 # number of ReadReq accesses(hits+misses) 2566system.cpu1.l2cache.ReadReq_accesses::total 23675 # number of ReadReq accesses(hits+misses) 2567system.cpu1.l2cache.WritebackDirty_accesses::writebacks 115107 # number of WritebackDirty accesses(hits+misses) 2568system.cpu1.l2cache.WritebackDirty_accesses::total 115107 # number of WritebackDirty accesses(hits+misses) 2569system.cpu1.l2cache.WritebackClean_accesses::writebacks 647294 # number of WritebackClean accesses(hits+misses) 2570system.cpu1.l2cache.WritebackClean_accesses::total 647294 # number of WritebackClean accesses(hits+misses) 2571system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29892 # number of UpgradeReq accesses(hits+misses) 2572system.cpu1.l2cache.UpgradeReq_accesses::total 29892 # number of UpgradeReq accesses(hits+misses) 2573system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23453 # number of SCUpgradeReq accesses(hits+misses) 2574system.cpu1.l2cache.SCUpgradeReq_accesses::total 23453 # number of SCUpgradeReq accesses(hits+misses) 2575system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 2576system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 2577system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61746 # number of ReadExReq accesses(hits+misses) 2578system.cpu1.l2cache.ReadExReq_accesses::total 61746 # number of ReadExReq accesses(hits+misses) 2579system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 586104 # number of ReadCleanReq accesses(hits+misses) 2580system.cpu1.l2cache.ReadCleanReq_accesses::total 586104 # number of ReadCleanReq accesses(hits+misses) 2581system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 171060 # number of ReadSharedReq accesses(hits+misses) 2582system.cpu1.l2cache.ReadSharedReq_accesses::total 171060 # number of ReadSharedReq accesses(hits+misses) 2583system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17203 # number of demand (read+write) accesses 2584system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 6472 # number of demand (read+write) accesses 2585system.cpu1.l2cache.demand_accesses::cpu1.inst 586104 # number of demand (read+write) accesses 2586system.cpu1.l2cache.demand_accesses::cpu1.data 232806 # number of demand (read+write) accesses 2587system.cpu1.l2cache.demand_accesses::total 842585 # number of demand (read+write) accesses 2588system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17203 # number of overall (read+write) accesses 2589system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 6472 # number of overall (read+write) accesses 2590system.cpu1.l2cache.overall_accesses::cpu1.inst 586104 # number of overall (read+write) accesses 2591system.cpu1.l2cache.overall_accesses::cpu1.data 232806 # number of overall (read+write) accesses 2592system.cpu1.l2cache.overall_accesses::total 842585 # number of overall (read+write) accesses 2593system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026042 # miss rate for ReadReq accesses 2594system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.037546 # miss rate for ReadReq accesses 2595system.cpu1.l2cache.ReadReq_miss_rate::total 0.029187 # miss rate for ReadReq accesses 2596system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2597system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2598system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2599system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2600system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2601system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2602system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.560295 # miss rate for ReadExReq accesses 2603system.cpu1.l2cache.ReadExReq_miss_rate::total 0.560295 # miss rate for ReadExReq accesses 2604system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.027379 # miss rate for ReadCleanReq accesses 2605system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.027379 # miss rate for ReadCleanReq accesses 2606system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.405238 # miss rate for ReadSharedReq accesses 2607system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.405238 # miss rate for ReadSharedReq accesses 2608system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.026042 # miss rate for demand accesses 2609system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.037546 # miss rate for demand accesses 2610system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.027379 # miss rate for demand accesses 2611system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.446363 # miss rate for demand accesses 2612system.cpu1.l2cache.demand_miss_rate::total 0.143195 # miss rate for demand accesses 2613system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.026042 # miss rate for overall accesses 2614system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.037546 # miss rate for overall accesses 2615system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.027379 # miss rate for overall accesses 2616system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.446363 # miss rate for overall accesses 2617system.cpu1.l2cache.overall_miss_rate::total 0.143195 # miss rate for overall accesses 2618system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22010.044643 # average ReadReq miss latency 2619system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20835.390947 # average ReadReq miss latency 2620system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21596.960926 # average ReadReq miss latency 2621system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2127.141041 # average UpgradeReq miss latency 2622system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2127.141041 # average UpgradeReq miss latency 2623system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1489.063233 # average SCUpgradeReq miss latency 2624system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1489.063233 # average SCUpgradeReq miss latency 2625system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 241299.600000 # average SCUpgradeFailReq miss latency 2626system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 241299.600000 # average SCUpgradeFailReq miss latency 2627system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42196.265406 # average ReadExReq miss latency 2628system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42196.265406 # average ReadExReq miss latency 2629system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 41017.324110 # average ReadCleanReq miss latency 2630system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 41017.324110 # average ReadCleanReq miss latency 2631system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22667.195600 # average ReadSharedReq miss latency 2632system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22667.195600 # average ReadSharedReq miss latency 2633system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22010.044643 # average overall miss latency 2634system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20835.390947 # average overall miss latency 2635system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 41017.324110 # average overall miss latency 2636system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29168.867133 # average overall miss latency 2637system.cpu1.l2cache.demand_avg_miss_latency::total 30701.348459 # average overall miss latency 2638system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22010.044643 # average overall miss latency 2639system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20835.390947 # average overall miss latency 2640system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 41017.324110 # average overall miss latency 2641system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29168.867133 # average overall miss latency 2642system.cpu1.l2cache.overall_avg_miss_latency::total 30701.348459 # average overall miss latency 2643system.cpu1.l2cache.blocked_cycles::no_mshrs 235 # number of cycles access was blocked 2644system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2645system.cpu1.l2cache.blocked::no_mshrs 9 # number of cycles access was blocked 2646system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2647system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 26.111111 # average number of cycles each access was blocked 2648system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2649system.cpu1.l2cache.unused_prefetches 821 # number of HardPF blocks evicted w/o reference 2650system.cpu1.l2cache.writebacks::writebacks 37285 # number of writebacks 2651system.cpu1.l2cache.writebacks::total 37285 # number of writebacks 2652system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 573 # number of ReadExReq MSHR hits 2653system.cpu1.l2cache.ReadExReq_mshr_hits::total 573 # number of ReadExReq MSHR hits 2654system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits 2655system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits 2656system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 74 # number of ReadSharedReq MSHR hits 2657system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 74 # number of ReadSharedReq MSHR hits 2658system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits 2659system.cpu1.l2cache.demand_mshr_hits::cpu1.data 647 # number of demand (read+write) MSHR hits 2660system.cpu1.l2cache.demand_mshr_hits::total 651 # number of demand (read+write) MSHR hits 2661system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits 2662system.cpu1.l2cache.overall_mshr_hits::cpu1.data 647 # number of overall MSHR hits 2663system.cpu1.l2cache.overall_mshr_hits::total 651 # number of overall MSHR hits 2664system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 448 # number of ReadReq MSHR misses 2665system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 243 # number of ReadReq MSHR misses 2666system.cpu1.l2cache.ReadReq_mshr_misses::total 691 # number of ReadReq MSHR misses 2667system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 27204 # number of HardPFReq MSHR misses 2668system.cpu1.l2cache.HardPFReq_mshr_misses::total 27204 # number of HardPFReq MSHR misses 2669system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29892 # number of UpgradeReq MSHR misses 2670system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29892 # number of UpgradeReq MSHR misses 2671system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23453 # number of SCUpgradeReq MSHR misses 2672system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23453 # number of SCUpgradeReq MSHR misses 2673system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses 2674system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 2675system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34023 # number of ReadExReq MSHR misses 2676system.cpu1.l2cache.ReadExReq_mshr_misses::total 34023 # number of ReadExReq MSHR misses 2677system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 16043 # number of ReadCleanReq MSHR misses 2678system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 16043 # number of ReadCleanReq MSHR misses 2679system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69246 # number of ReadSharedReq MSHR misses 2680system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69246 # number of ReadSharedReq MSHR misses 2681system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 448 # number of demand (read+write) MSHR misses 2682system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 243 # number of demand (read+write) MSHR misses 2683system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 16043 # number of demand (read+write) MSHR misses 2684system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103269 # number of demand (read+write) MSHR misses 2685system.cpu1.l2cache.demand_mshr_misses::total 120003 # number of demand (read+write) MSHR misses 2686system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 448 # number of overall MSHR misses 2687system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 243 # number of overall MSHR misses 2688system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 16043 # number of overall MSHR misses 2689system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103269 # number of overall MSHR misses 2690system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 27204 # number of overall MSHR misses 2691system.cpu1.l2cache.overall_mshr_misses::total 147207 # number of overall MSHR misses 2692system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable 2693system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3078 # number of ReadReq MSHR uncacheable 2694system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3180 # number of ReadReq MSHR uncacheable 2695system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2435 # number of WriteReq MSHR uncacheable 2696system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2435 # number of WriteReq MSHR uncacheable 2697system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses 2698system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5513 # number of overall MSHR uncacheable misses 2699system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5615 # number of overall MSHR uncacheable misses 2700system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7172500 # number of ReadReq MSHR miss cycles 2701system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3605000 # number of ReadReq MSHR miss cycles 2702system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10777500 # number of ReadReq MSHR miss cycles 2703system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1221222561 # number of HardPFReq MSHR miss cycles 2704system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1221222561 # number of HardPFReq MSHR miss cycles 2705system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 499462500 # number of UpgradeReq MSHR miss cycles 2706system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 499462500 # number of UpgradeReq MSHR miss cycles 2707system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 372532500 # number of SCUpgradeReq MSHR miss cycles 2708system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 372532500 # number of SCUpgradeReq MSHR miss cycles 2709system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1056498 # number of SCUpgradeFailReq MSHR miss cycles 2710system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1056498 # number of SCUpgradeFailReq MSHR miss cycles 2711system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1184971500 # number of ReadExReq MSHR miss cycles 2712system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1184971500 # number of ReadExReq MSHR miss cycles 2713system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 561881000 # number of ReadCleanReq MSHR miss cycles 2714system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 561881000 # number of ReadCleanReq MSHR miss cycles 2715system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1153728499 # number of ReadSharedReq MSHR miss cycles 2716system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1153728499 # number of ReadSharedReq MSHR miss cycles 2717system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7172500 # number of demand (read+write) MSHR miss cycles 2718system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3605000 # number of demand (read+write) MSHR miss cycles 2719system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 561881000 # number of demand (read+write) MSHR miss cycles 2720system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2338699999 # number of demand (read+write) MSHR miss cycles 2721system.cpu1.l2cache.demand_mshr_miss_latency::total 2911358499 # number of demand (read+write) MSHR miss cycles 2722system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7172500 # number of overall MSHR miss cycles 2723system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3605000 # number of overall MSHR miss cycles 2724system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 561881000 # number of overall MSHR miss cycles 2725system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2338699999 # number of overall MSHR miss cycles 2726system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1221222561 # number of overall MSHR miss cycles 2727system.cpu1.l2cache.overall_mshr_miss_latency::total 4132581060 # number of overall MSHR miss cycles 2728system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8464000 # number of ReadReq MSHR uncacheable cycles 2729system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 417313000 # number of ReadReq MSHR uncacheable cycles 2730system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 425777000 # number of ReadReq MSHR uncacheable cycles 2731system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8464000 # number of overall MSHR uncacheable cycles 2732system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 417313000 # number of overall MSHR uncacheable cycles 2733system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 425777000 # number of overall MSHR uncacheable cycles 2734system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026042 # mshr miss rate for ReadReq accesses 2735system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.037546 # mshr miss rate for ReadReq accesses 2736system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029187 # mshr miss rate for ReadReq accesses 2737system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2738system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2739system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2740system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2741system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2742system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2743system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2744system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2745system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.551015 # mshr miss rate for ReadExReq accesses 2746system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.551015 # mshr miss rate for ReadExReq accesses 2747system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027372 # mshr miss rate for ReadCleanReq accesses 2748system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.027372 # mshr miss rate for ReadCleanReq accesses 2749system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.404805 # mshr miss rate for ReadSharedReq accesses 2750system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.404805 # mshr miss rate for ReadSharedReq accesses 2751system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026042 # mshr miss rate for demand accesses 2752system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.037546 # mshr miss rate for demand accesses 2753system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.027372 # mshr miss rate for demand accesses 2754system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443584 # mshr miss rate for demand accesses 2755system.cpu1.l2cache.demand_mshr_miss_rate::total 0.142422 # mshr miss rate for demand accesses 2756system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026042 # mshr miss rate for overall accesses 2757system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.037546 # mshr miss rate for overall accesses 2758system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.027372 # mshr miss rate for overall accesses 2759system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443584 # mshr miss rate for overall accesses 2760system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2761system.cpu1.l2cache.overall_mshr_miss_rate::total 0.174709 # mshr miss rate for overall accesses 2762system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16010.044643 # average ReadReq mshr miss latency 2763system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14835.390947 # average ReadReq mshr miss latency 2764system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15596.960926 # average ReadReq mshr miss latency 2765system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44891.286612 # average HardPFReq mshr miss latency 2766system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44891.286612 # average HardPFReq mshr miss latency 2767system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16708.902047 # average UpgradeReq mshr miss latency 2768system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16708.902047 # average UpgradeReq mshr miss latency 2769system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15884.215239 # average SCUpgradeReq mshr miss latency 2770system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15884.215239 # average SCUpgradeReq mshr miss latency 2771system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 211299.600000 # average SCUpgradeFailReq mshr miss latency 2772system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 211299.600000 # average SCUpgradeFailReq mshr miss latency 2773system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34828.542457 # average ReadExReq mshr miss latency 2774system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34828.542457 # average ReadExReq mshr miss latency 2775system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 35023.437013 # average ReadCleanReq mshr miss latency 2776system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 35023.437013 # average ReadCleanReq mshr miss latency 2777system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16661.301721 # average ReadSharedReq mshr miss latency 2778system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16661.301721 # average ReadSharedReq mshr miss latency 2779system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16010.044643 # average overall mshr miss latency 2780system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14835.390947 # average overall mshr miss latency 2781system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 35023.437013 # average overall mshr miss latency 2782system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22646.680020 # average overall mshr miss latency 2783system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24260.714307 # average overall mshr miss latency 2784system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16010.044643 # average overall mshr miss latency 2785system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14835.390947 # average overall mshr miss latency 2786system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 35023.437013 # average overall mshr miss latency 2787system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22646.680020 # average overall mshr miss latency 2788system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44891.286612 # average overall mshr miss latency 2789system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28073.264587 # average overall mshr miss latency 2790system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82980.392157 # average ReadReq mshr uncacheable latency 2791system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135579.272255 # average ReadReq mshr uncacheable latency 2792system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133892.138365 # average ReadReq mshr uncacheable latency 2793system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82980.392157 # average overall mshr uncacheable latency 2794system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75696.172683 # average overall mshr uncacheable latency 2795system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75828.495102 # average overall mshr uncacheable latency 2796system.cpu1.toL2Bus.snoop_filter.tot_requests 1657712 # Total number of requests made to the snoop filter. 2797system.cpu1.toL2Bus.snoop_filter.hit_single_requests 838800 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2798system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12415 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2799system.cpu1.toL2Bus.snoop_filter.tot_snoops 183176 # Total number of snoops made to the snoop filter. 2800system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 180762 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2801system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2414 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2802system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2803system.cpu1.toL2Bus.trans_dist::ReadReq 31669 # Transaction distribution 2804system.cpu1.toL2Bus.trans_dist::ReadResp 826741 # Transaction distribution 2805system.cpu1.toL2Bus.trans_dist::WriteReq 2435 # Transaction distribution 2806system.cpu1.toL2Bus.trans_dist::WriteResp 2435 # Transaction distribution 2807system.cpu1.toL2Bus.trans_dist::WritebackDirty 153550 # Transaction distribution 2808system.cpu1.toL2Bus.trans_dist::WritebackClean 659699 # Transaction distribution 2809system.cpu1.toL2Bus.trans_dist::CleanEvict 108887 # Transaction distribution 2810system.cpu1.toL2Bus.trans_dist::HardPFReq 33537 # Transaction distribution 2811system.cpu1.toL2Bus.trans_dist::UpgradeReq 71200 # Transaction distribution 2812system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41639 # Transaction distribution 2813system.cpu1.toL2Bus.trans_dist::UpgradeResp 86222 # Transaction distribution 2814system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution 2815system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution 2816system.cpu1.toL2Bus.trans_dist::ReadExReq 68548 # Transaction distribution 2817system.cpu1.toL2Bus.trans_dist::ReadExResp 66385 # Transaction distribution 2818system.cpu1.toL2Bus.trans_dist::ReadCleanReq 586115 # Transaction distribution 2819system.cpu1.toL2Bus.trans_dist::ReadSharedReq 251518 # Transaction distribution 2820system.cpu1.toL2Bus.trans_dist::InvalidateReq 256 # Transaction distribution 2821system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1758016 # Packet count per connected master and slave (bytes) 2822system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 847991 # Packet count per connected master and slave (bytes) 2823system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14492 # Packet count per connected master and slave (bytes) 2824system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37672 # Packet count per connected master and slave (bytes) 2825system.cpu1.toL2Bus.pkt_count::total 2658171 # Packet count per connected master and slave (bytes) 2826system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 74990240 # Cumulative packet size per connected master and slave (bytes) 2827system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29751886 # Cumulative packet size per connected master and slave (bytes) 2828system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25888 # Cumulative packet size per connected master and slave (bytes) 2829system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 68812 # Cumulative packet size per connected master and slave (bytes) 2830system.cpu1.toL2Bus.pkt_size::total 104836826 # Cumulative packet size per connected master and slave (bytes) 2831system.cpu1.toL2Bus.snoops 408149 # Total snoops (count) 2832system.cpu1.toL2Bus.snoop_fanout::samples 1234265 # Request fanout histogram 2833system.cpu1.toL2Bus.snoop_fanout::mean 0.169046 # Request fanout histogram 2834system.cpu1.toL2Bus.snoop_fanout::stdev 0.379975 # Request fanout histogram 2835system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2836system.cpu1.toL2Bus.snoop_fanout::0 1028032 83.29% 83.29% # Request fanout histogram 2837system.cpu1.toL2Bus.snoop_fanout::1 203819 16.51% 99.80% # Request fanout histogram 2838system.cpu1.toL2Bus.snoop_fanout::2 2414 0.20% 100.00% # Request fanout histogram 2839system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2840system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2841system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2842system.cpu1.toL2Bus.snoop_fanout::total 1234265 # Request fanout histogram 2843system.cpu1.toL2Bus.reqLayer0.occupancy 1616622989 # Layer occupancy (ticks) 2844system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2845system.cpu1.toL2Bus.snoopLayer0.occupancy 80296887 # Layer occupancy (ticks) 2846system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2847system.cpu1.toL2Bus.respLayer0.occupancy 879411723 # Layer occupancy (ticks) 2848system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2849system.cpu1.toL2Bus.respLayer1.occupancy 381445015 # Layer occupancy (ticks) 2850system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2851system.cpu1.toL2Bus.respLayer2.occupancy 8027984 # Layer occupancy (ticks) 2852system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2853system.cpu1.toL2Bus.respLayer3.occupancy 20485966 # Layer occupancy (ticks) 2854system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2855system.iobus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2856system.iobus.trans_dist::ReadReq 31012 # Transaction distribution 2857system.iobus.trans_dist::ReadResp 31012 # Transaction distribution 2858system.iobus.trans_dist::WriteReq 59421 # Transaction distribution 2859system.iobus.trans_dist::WriteResp 59421 # Transaction distribution 2860system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) 2861system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2862system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2863system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2864system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2865system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2866system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2867system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2868system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2869system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2870system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2871system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2872system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2873system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2874system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2875system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2876system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2877system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2878system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2879system.iobus.pkt_count_system.bridge.master::total 107914 # Packet count per connected master and slave (bytes) 2880system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 2881system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 2882system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) 2883system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes) 2884system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2885system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2886system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2887system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2888system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2889system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2890system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2891system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2892system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2893system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2894system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2895system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2896system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2897system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2898system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2899system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2900system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2901system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2902system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) 2903system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 2904system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 2905system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes) 2906system.iobus.reqLayer0.occupancy 40382501 # Layer occupancy (ticks) 2907system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2908system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) 2909system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2910system.iobus.reqLayer2.occupancy 327500 # Layer occupancy (ticks) 2911system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2912system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks) 2913system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2914system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks) 2915system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2916system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks) 2917system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2918system.iobus.reqLayer8.occupancy 582000 # Layer occupancy (ticks) 2919system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2920system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks) 2921system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2922system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) 2923system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2924system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) 2925system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2926system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) 2927system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2928system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks) 2929system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2930system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) 2931system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2932system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 2933system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2934system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2935system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2936system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2937system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2938system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) 2939system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2940system.iobus.reqLayer23.occupancy 6099000 # Layer occupancy (ticks) 2941system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2942system.iobus.reqLayer24.occupancy 33797500 # Layer occupancy (ticks) 2943system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2944system.iobus.reqLayer25.occupancy 187673606 # Layer occupancy (ticks) 2945system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2946system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) 2947system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2948system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) 2949system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2950system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2951system.iocache.tags.replacements 36458 # number of replacements 2952system.iocache.tags.tagsinuse 14.555465 # Cycle average of tags in use 2953system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2954system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. 2955system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2956system.iocache.tags.warmup_cycle 255128019000 # Cycle when the warmup percentage was hit. 2957system.iocache.tags.occ_blocks::realview.ide 14.555465 # Average occupied blocks per requestor 2958system.iocache.tags.occ_percent::realview.ide 0.909717 # Average percentage of cache occupancy 2959system.iocache.tags.occ_percent::total 0.909717 # Average percentage of cache occupancy 2960system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2961system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2962system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2963system.iocache.tags.tag_accesses 328284 # Number of tag accesses 2964system.iocache.tags.data_accesses 328284 # Number of data accesses 2965system.iocache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 2966system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 2967system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 2968system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2969system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2970system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 2971system.iocache.demand_misses::total 36476 # number of demand (read+write) misses 2972system.iocache.overall_misses::realview.ide 36476 # number of overall misses 2973system.iocache.overall_misses::total 36476 # number of overall misses 2974system.iocache.ReadReq_miss_latency::realview.ide 32586377 # number of ReadReq miss cycles 2975system.iocache.ReadReq_miss_latency::total 32586377 # number of ReadReq miss cycles 2976system.iocache.WriteLineReq_miss_latency::realview.ide 4303595229 # number of WriteLineReq miss cycles 2977system.iocache.WriteLineReq_miss_latency::total 4303595229 # number of WriteLineReq miss cycles 2978system.iocache.demand_miss_latency::realview.ide 4336181606 # number of demand (read+write) miss cycles 2979system.iocache.demand_miss_latency::total 4336181606 # number of demand (read+write) miss cycles 2980system.iocache.overall_miss_latency::realview.ide 4336181606 # number of overall miss cycles 2981system.iocache.overall_miss_latency::total 4336181606 # number of overall miss cycles 2982system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 2983system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 2984system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2985system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2986system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses 2987system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses 2988system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses 2989system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses 2990system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2991system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2992system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2993system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2994system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2995system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2996system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2997system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2998system.iocache.ReadReq_avg_miss_latency::realview.ide 129311.019841 # average ReadReq miss latency 2999system.iocache.ReadReq_avg_miss_latency::total 129311.019841 # average ReadReq miss latency 3000system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118805.080306 # average WriteLineReq miss latency 3001system.iocache.WriteLineReq_avg_miss_latency::total 118805.080306 # average WriteLineReq miss latency 3002system.iocache.demand_avg_miss_latency::realview.ide 118877.662189 # average overall miss latency 3003system.iocache.demand_avg_miss_latency::total 118877.662189 # average overall miss latency 3004system.iocache.overall_avg_miss_latency::realview.ide 118877.662189 # average overall miss latency 3005system.iocache.overall_avg_miss_latency::total 118877.662189 # average overall miss latency 3006system.iocache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked 3007system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3008system.iocache.blocked::no_mshrs 5 # number of cycles access was blocked 3009system.iocache.blocked::no_targets 0 # number of cycles access was blocked 3010system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked 3011system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3012system.iocache.writebacks::writebacks 36206 # number of writebacks 3013system.iocache.writebacks::total 36206 # number of writebacks 3014system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses 3015system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses 3016system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 3017system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 3018system.iocache.demand_mshr_misses::realview.ide 36476 # number of demand (read+write) MSHR misses 3019system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses 3020system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses 3021system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses 3022system.iocache.ReadReq_mshr_miss_latency::realview.ide 19986377 # number of ReadReq MSHR miss cycles 3023system.iocache.ReadReq_mshr_miss_latency::total 19986377 # number of ReadReq MSHR miss cycles 3024system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2490041664 # number of WriteLineReq MSHR miss cycles 3025system.iocache.WriteLineReq_mshr_miss_latency::total 2490041664 # number of WriteLineReq MSHR miss cycles 3026system.iocache.demand_mshr_miss_latency::realview.ide 2510028041 # number of demand (read+write) MSHR miss cycles 3027system.iocache.demand_mshr_miss_latency::total 2510028041 # number of demand (read+write) MSHR miss cycles 3028system.iocache.overall_mshr_miss_latency::realview.ide 2510028041 # number of overall MSHR miss cycles 3029system.iocache.overall_mshr_miss_latency::total 2510028041 # number of overall MSHR miss cycles 3030system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3031system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3032system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 3033system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 3034system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3035system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3036system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3037system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 3038system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79311.019841 # average ReadReq mshr miss latency 3039system.iocache.ReadReq_avg_mshr_miss_latency::total 79311.019841 # average ReadReq mshr miss latency 3040system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68740.107774 # average WriteLineReq mshr miss latency 3041system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68740.107774 # average WriteLineReq mshr miss latency 3042system.iocache.demand_avg_mshr_miss_latency::realview.ide 68813.138529 # average overall mshr miss latency 3043system.iocache.demand_avg_mshr_miss_latency::total 68813.138529 # average overall mshr miss latency 3044system.iocache.overall_avg_mshr_miss_latency::realview.ide 68813.138529 # average overall mshr miss latency 3045system.iocache.overall_avg_mshr_miss_latency::total 68813.138529 # average overall mshr miss latency 3046system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3047system.l2c.tags.replacements 132778 # number of replacements 3048system.l2c.tags.tagsinuse 63203.828730 # Cycle average of tags in use 3049system.l2c.tags.total_refs 444088 # Total number of references to valid blocks. 3050system.l2c.tags.sampled_refs 196669 # Sample count of references to valid blocks. 3051system.l2c.tags.avg_refs 2.258048 # Average number of references to valid blocks. 3052system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3053system.l2c.tags.occ_blocks::writebacks 13685.490361 # Average occupied blocks per requestor 3054system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.358726 # Average occupied blocks per requestor 3055system.l2c.tags.occ_blocks::cpu0.itb.walker 1.065836 # Average occupied blocks per requestor 3056system.l2c.tags.occ_blocks::cpu0.inst 8064.380543 # Average occupied blocks per requestor 3057system.l2c.tags.occ_blocks::cpu0.data 2772.729395 # Average occupied blocks per requestor 3058system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33768.581689 # Average occupied blocks per requestor 3059system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.679196 # Average occupied blocks per requestor 3060system.l2c.tags.occ_blocks::cpu1.itb.walker 0.910017 # Average occupied blocks per requestor 3061system.l2c.tags.occ_blocks::cpu1.inst 1783.108864 # Average occupied blocks per requestor 3062system.l2c.tags.occ_blocks::cpu1.data 674.072360 # Average occupied blocks per requestor 3063system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2431.451744 # Average occupied blocks per requestor 3064system.l2c.tags.occ_percent::writebacks 0.208824 # Average percentage of cache occupancy 3065system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000250 # Average percentage of cache occupancy 3066system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy 3067system.l2c.tags.occ_percent::cpu0.inst 0.123053 # Average percentage of cache occupancy 3068system.l2c.tags.occ_percent::cpu0.data 0.042308 # Average percentage of cache occupancy 3069system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.515268 # Average percentage of cache occupancy 3070system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000087 # Average percentage of cache occupancy 3071system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy 3072system.l2c.tags.occ_percent::cpu1.inst 0.027208 # Average percentage of cache occupancy 3073system.l2c.tags.occ_percent::cpu1.data 0.010286 # Average percentage of cache occupancy 3074system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.037101 # Average percentage of cache occupancy 3075system.l2c.tags.occ_percent::total 0.964414 # Average percentage of cache occupancy 3076system.l2c.tags.occ_task_id_blocks::1022 29279 # Occupied blocks per task id 3077system.l2c.tags.occ_task_id_blocks::1023 30 # Occupied blocks per task id 3078system.l2c.tags.occ_task_id_blocks::1024 34582 # Occupied blocks per task id 3079system.l2c.tags.age_task_id_blocks_1022::2 180 # Occupied blocks per task id 3080system.l2c.tags.age_task_id_blocks_1022::3 5628 # Occupied blocks per task id 3081system.l2c.tags.age_task_id_blocks_1022::4 23471 # Occupied blocks per task id 3082system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 3083system.l2c.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id 3084system.l2c.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 3085system.l2c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id 3086system.l2c.tags.age_task_id_blocks_1024::2 579 # Occupied blocks per task id 3087system.l2c.tags.age_task_id_blocks_1024::3 6711 # Occupied blocks per task id 3088system.l2c.tags.age_task_id_blocks_1024::4 27249 # Occupied blocks per task id 3089system.l2c.tags.occ_task_id_percent::1022 0.446762 # Percentage of cache occupancy per task id 3090system.l2c.tags.occ_task_id_percent::1023 0.000458 # Percentage of cache occupancy per task id 3091system.l2c.tags.occ_task_id_percent::1024 0.527679 # Percentage of cache occupancy per task id 3092system.l2c.tags.tag_accesses 6131058 # Number of tag accesses 3093system.l2c.tags.data_accesses 6131058 # Number of data accesses 3094system.l2c.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3095system.l2c.WritebackDirty_hits::writebacks 266860 # number of WritebackDirty hits 3096system.l2c.WritebackDirty_hits::total 266860 # number of WritebackDirty hits 3097system.l2c.UpgradeReq_hits::cpu0.data 32430 # number of UpgradeReq hits 3098system.l2c.UpgradeReq_hits::cpu1.data 2686 # number of UpgradeReq hits 3099system.l2c.UpgradeReq_hits::total 35116 # number of UpgradeReq hits 3100system.l2c.SCUpgradeReq_hits::cpu0.data 2009 # number of SCUpgradeReq hits 3101system.l2c.SCUpgradeReq_hits::cpu1.data 933 # number of SCUpgradeReq hits 3102system.l2c.SCUpgradeReq_hits::total 2942 # number of SCUpgradeReq hits 3103system.l2c.ReadExReq_hits::cpu0.data 4036 # number of ReadExReq hits 3104system.l2c.ReadExReq_hits::cpu1.data 1379 # number of ReadExReq hits 3105system.l2c.ReadExReq_hits::total 5415 # number of ReadExReq hits 3106system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 163 # number of ReadSharedReq hits 3107system.l2c.ReadSharedReq_hits::cpu0.itb.walker 75 # number of ReadSharedReq hits 3108system.l2c.ReadSharedReq_hits::cpu0.inst 33190 # number of ReadSharedReq hits 3109system.l2c.ReadSharedReq_hits::cpu0.data 46982 # number of ReadSharedReq hits 3110system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46066 # number of ReadSharedReq hits 3111system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 73 # number of ReadSharedReq hits 3112system.l2c.ReadSharedReq_hits::cpu1.itb.walker 29 # number of ReadSharedReq hits 3113system.l2c.ReadSharedReq_hits::cpu1.inst 13227 # number of ReadSharedReq hits 3114system.l2c.ReadSharedReq_hits::cpu1.data 9835 # number of ReadSharedReq hits 3115system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5456 # number of ReadSharedReq hits 3116system.l2c.ReadSharedReq_hits::total 155096 # number of ReadSharedReq hits 3117system.l2c.demand_hits::cpu0.dtb.walker 163 # number of demand (read+write) hits 3118system.l2c.demand_hits::cpu0.itb.walker 75 # number of demand (read+write) hits 3119system.l2c.demand_hits::cpu0.inst 33190 # number of demand (read+write) hits 3120system.l2c.demand_hits::cpu0.data 51018 # number of demand (read+write) hits 3121system.l2c.demand_hits::cpu0.l2cache.prefetcher 46066 # number of demand (read+write) hits 3122system.l2c.demand_hits::cpu1.dtb.walker 73 # number of demand (read+write) hits 3123system.l2c.demand_hits::cpu1.itb.walker 29 # number of demand (read+write) hits 3124system.l2c.demand_hits::cpu1.inst 13227 # number of demand (read+write) hits 3125system.l2c.demand_hits::cpu1.data 11214 # number of demand (read+write) hits 3126system.l2c.demand_hits::cpu1.l2cache.prefetcher 5456 # number of demand (read+write) hits 3127system.l2c.demand_hits::total 160511 # number of demand (read+write) hits 3128system.l2c.overall_hits::cpu0.dtb.walker 163 # number of overall hits 3129system.l2c.overall_hits::cpu0.itb.walker 75 # number of overall hits 3130system.l2c.overall_hits::cpu0.inst 33190 # number of overall hits 3131system.l2c.overall_hits::cpu0.data 51018 # number of overall hits 3132system.l2c.overall_hits::cpu0.l2cache.prefetcher 46066 # number of overall hits 3133system.l2c.overall_hits::cpu1.dtb.walker 73 # number of overall hits 3134system.l2c.overall_hits::cpu1.itb.walker 29 # number of overall hits 3135system.l2c.overall_hits::cpu1.inst 13227 # number of overall hits 3136system.l2c.overall_hits::cpu1.data 11214 # number of overall hits 3137system.l2c.overall_hits::cpu1.l2cache.prefetcher 5456 # number of overall hits 3138system.l2c.overall_hits::total 160511 # number of overall hits 3139system.l2c.UpgradeReq_misses::cpu0.data 8984 # number of UpgradeReq misses 3140system.l2c.UpgradeReq_misses::cpu1.data 2771 # number of UpgradeReq misses 3141system.l2c.UpgradeReq_misses::total 11755 # number of UpgradeReq misses 3142system.l2c.SCUpgradeReq_misses::cpu0.data 655 # number of SCUpgradeReq misses 3143system.l2c.SCUpgradeReq_misses::cpu1.data 1290 # number of SCUpgradeReq misses 3144system.l2c.SCUpgradeReq_misses::total 1945 # number of SCUpgradeReq misses 3145system.l2c.ReadExReq_misses::cpu0.data 11642 # number of ReadExReq misses 3146system.l2c.ReadExReq_misses::cpu1.data 8933 # number of ReadExReq misses 3147system.l2c.ReadExReq_misses::total 20575 # number of ReadExReq misses 3148system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 27 # number of ReadSharedReq misses 3149system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses 3150system.l2c.ReadSharedReq_misses::cpu0.inst 19670 # number of ReadSharedReq misses 3151system.l2c.ReadSharedReq_misses::cpu0.data 9220 # number of ReadSharedReq misses 3152system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133244 # number of ReadSharedReq misses 3153system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 7 # number of ReadSharedReq misses 3154system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses 3155system.l2c.ReadSharedReq_misses::cpu1.inst 2815 # number of ReadSharedReq misses 3156system.l2c.ReadSharedReq_misses::cpu1.data 1145 # number of ReadSharedReq misses 3157system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 8148 # number of ReadSharedReq misses 3158system.l2c.ReadSharedReq_misses::total 174280 # number of ReadSharedReq misses 3159system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses 3160system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 3161system.l2c.demand_misses::cpu0.inst 19670 # number of demand (read+write) misses 3162system.l2c.demand_misses::cpu0.data 20862 # number of demand (read+write) misses 3163system.l2c.demand_misses::cpu0.l2cache.prefetcher 133244 # number of demand (read+write) misses 3164system.l2c.demand_misses::cpu1.dtb.walker 7 # number of demand (read+write) misses 3165system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 3166system.l2c.demand_misses::cpu1.inst 2815 # number of demand (read+write) misses 3167system.l2c.demand_misses::cpu1.data 10078 # number of demand (read+write) misses 3168system.l2c.demand_misses::cpu1.l2cache.prefetcher 8148 # number of demand (read+write) misses 3169system.l2c.demand_misses::total 194855 # number of demand (read+write) misses 3170system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses 3171system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 3172system.l2c.overall_misses::cpu0.inst 19670 # number of overall misses 3173system.l2c.overall_misses::cpu0.data 20862 # number of overall misses 3174system.l2c.overall_misses::cpu0.l2cache.prefetcher 133244 # number of overall misses 3175system.l2c.overall_misses::cpu1.dtb.walker 7 # number of overall misses 3176system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 3177system.l2c.overall_misses::cpu1.inst 2815 # number of overall misses 3178system.l2c.overall_misses::cpu1.data 10078 # number of overall misses 3179system.l2c.overall_misses::cpu1.l2cache.prefetcher 8148 # number of overall misses 3180system.l2c.overall_misses::total 194855 # number of overall misses 3181system.l2c.UpgradeReq_miss_latency::cpu0.data 8725000 # number of UpgradeReq miss cycles 3182system.l2c.UpgradeReq_miss_latency::cpu1.data 2891500 # number of UpgradeReq miss cycles 3183system.l2c.UpgradeReq_miss_latency::total 11616500 # number of UpgradeReq miss cycles 3184system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1430000 # number of SCUpgradeReq miss cycles 3185system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1143000 # number of SCUpgradeReq miss cycles 3186system.l2c.SCUpgradeReq_miss_latency::total 2573000 # number of SCUpgradeReq miss cycles 3187system.l2c.ReadExReq_miss_latency::cpu0.data 1196035499 # number of ReadExReq miss cycles 3188system.l2c.ReadExReq_miss_latency::cpu1.data 747656500 # number of ReadExReq miss cycles 3189system.l2c.ReadExReq_miss_latency::total 1943691999 # number of ReadExReq miss cycles 3190system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 2599000 # number of ReadSharedReq miss cycles 3191system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 241000 # number of ReadSharedReq miss cycles 3192system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1635002000 # number of ReadSharedReq miss cycles 3193system.l2c.ReadSharedReq_miss_latency::cpu0.data 838941000 # number of ReadSharedReq miss cycles 3194system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 14574955860 # number of ReadSharedReq miss cycles 3195system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 652000 # number of ReadSharedReq miss cycles 3196system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 97500 # number of ReadSharedReq miss cycles 3197system.l2c.ReadSharedReq_miss_latency::cpu1.inst 242297000 # number of ReadSharedReq miss cycles 3198system.l2c.ReadSharedReq_miss_latency::cpu1.data 106324000 # number of ReadSharedReq miss cycles 3199system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1101582147 # number of ReadSharedReq miss cycles 3200system.l2c.ReadSharedReq_miss_latency::total 18502691507 # number of ReadSharedReq miss cycles 3201system.l2c.demand_miss_latency::cpu0.dtb.walker 2599000 # number of demand (read+write) miss cycles 3202system.l2c.demand_miss_latency::cpu0.itb.walker 241000 # number of demand (read+write) miss cycles 3203system.l2c.demand_miss_latency::cpu0.inst 1635002000 # number of demand (read+write) miss cycles 3204system.l2c.demand_miss_latency::cpu0.data 2034976499 # number of demand (read+write) miss cycles 3205system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14574955860 # number of demand (read+write) miss cycles 3206system.l2c.demand_miss_latency::cpu1.dtb.walker 652000 # number of demand (read+write) miss cycles 3207system.l2c.demand_miss_latency::cpu1.itb.walker 97500 # number of demand (read+write) miss cycles 3208system.l2c.demand_miss_latency::cpu1.inst 242297000 # number of demand (read+write) miss cycles 3209system.l2c.demand_miss_latency::cpu1.data 853980500 # number of demand (read+write) miss cycles 3210system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1101582147 # number of demand (read+write) miss cycles 3211system.l2c.demand_miss_latency::total 20446383506 # number of demand (read+write) miss cycles 3212system.l2c.overall_miss_latency::cpu0.dtb.walker 2599000 # number of overall miss cycles 3213system.l2c.overall_miss_latency::cpu0.itb.walker 241000 # number of overall miss cycles 3214system.l2c.overall_miss_latency::cpu0.inst 1635002000 # number of overall miss cycles 3215system.l2c.overall_miss_latency::cpu0.data 2034976499 # number of overall miss cycles 3216system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14574955860 # number of overall miss cycles 3217system.l2c.overall_miss_latency::cpu1.dtb.walker 652000 # number of overall miss cycles 3218system.l2c.overall_miss_latency::cpu1.itb.walker 97500 # number of overall miss cycles 3219system.l2c.overall_miss_latency::cpu1.inst 242297000 # number of overall miss cycles 3220system.l2c.overall_miss_latency::cpu1.data 853980500 # number of overall miss cycles 3221system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1101582147 # number of overall miss cycles 3222system.l2c.overall_miss_latency::total 20446383506 # number of overall miss cycles 3223system.l2c.WritebackDirty_accesses::writebacks 266860 # number of WritebackDirty accesses(hits+misses) 3224system.l2c.WritebackDirty_accesses::total 266860 # number of WritebackDirty accesses(hits+misses) 3225system.l2c.UpgradeReq_accesses::cpu0.data 41414 # number of UpgradeReq accesses(hits+misses) 3226system.l2c.UpgradeReq_accesses::cpu1.data 5457 # number of UpgradeReq accesses(hits+misses) 3227system.l2c.UpgradeReq_accesses::total 46871 # number of UpgradeReq accesses(hits+misses) 3228system.l2c.SCUpgradeReq_accesses::cpu0.data 2664 # number of SCUpgradeReq accesses(hits+misses) 3229system.l2c.SCUpgradeReq_accesses::cpu1.data 2223 # number of SCUpgradeReq accesses(hits+misses) 3230system.l2c.SCUpgradeReq_accesses::total 4887 # number of SCUpgradeReq accesses(hits+misses) 3231system.l2c.ReadExReq_accesses::cpu0.data 15678 # number of ReadExReq accesses(hits+misses) 3232system.l2c.ReadExReq_accesses::cpu1.data 10312 # number of ReadExReq accesses(hits+misses) 3233system.l2c.ReadExReq_accesses::total 25990 # number of ReadExReq accesses(hits+misses) 3234system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 190 # number of ReadSharedReq accesses(hits+misses) 3235system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 78 # number of ReadSharedReq accesses(hits+misses) 3236system.l2c.ReadSharedReq_accesses::cpu0.inst 52860 # number of ReadSharedReq accesses(hits+misses) 3237system.l2c.ReadSharedReq_accesses::cpu0.data 56202 # number of ReadSharedReq accesses(hits+misses) 3238system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179310 # number of ReadSharedReq accesses(hits+misses) 3239system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 80 # number of ReadSharedReq accesses(hits+misses) 3240system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 30 # number of ReadSharedReq accesses(hits+misses) 3241system.l2c.ReadSharedReq_accesses::cpu1.inst 16042 # number of ReadSharedReq accesses(hits+misses) 3242system.l2c.ReadSharedReq_accesses::cpu1.data 10980 # number of ReadSharedReq accesses(hits+misses) 3243system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 13604 # number of ReadSharedReq accesses(hits+misses) 3244system.l2c.ReadSharedReq_accesses::total 329376 # number of ReadSharedReq accesses(hits+misses) 3245system.l2c.demand_accesses::cpu0.dtb.walker 190 # number of demand (read+write) accesses 3246system.l2c.demand_accesses::cpu0.itb.walker 78 # number of demand (read+write) accesses 3247system.l2c.demand_accesses::cpu0.inst 52860 # number of demand (read+write) accesses 3248system.l2c.demand_accesses::cpu0.data 71880 # number of demand (read+write) accesses 3249system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179310 # number of demand (read+write) accesses 3250system.l2c.demand_accesses::cpu1.dtb.walker 80 # number of demand (read+write) accesses 3251system.l2c.demand_accesses::cpu1.itb.walker 30 # number of demand (read+write) accesses 3252system.l2c.demand_accesses::cpu1.inst 16042 # number of demand (read+write) accesses 3253system.l2c.demand_accesses::cpu1.data 21292 # number of demand (read+write) accesses 3254system.l2c.demand_accesses::cpu1.l2cache.prefetcher 13604 # number of demand (read+write) accesses 3255system.l2c.demand_accesses::total 355366 # number of demand (read+write) accesses 3256system.l2c.overall_accesses::cpu0.dtb.walker 190 # number of overall (read+write) accesses 3257system.l2c.overall_accesses::cpu0.itb.walker 78 # number of overall (read+write) accesses 3258system.l2c.overall_accesses::cpu0.inst 52860 # number of overall (read+write) accesses 3259system.l2c.overall_accesses::cpu0.data 71880 # number of overall (read+write) accesses 3260system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179310 # number of overall (read+write) accesses 3261system.l2c.overall_accesses::cpu1.dtb.walker 80 # number of overall (read+write) accesses 3262system.l2c.overall_accesses::cpu1.itb.walker 30 # number of overall (read+write) accesses 3263system.l2c.overall_accesses::cpu1.inst 16042 # number of overall (read+write) accesses 3264system.l2c.overall_accesses::cpu1.data 21292 # number of overall (read+write) accesses 3265system.l2c.overall_accesses::cpu1.l2cache.prefetcher 13604 # number of overall (read+write) accesses 3266system.l2c.overall_accesses::total 355366 # number of overall (read+write) accesses 3267system.l2c.UpgradeReq_miss_rate::cpu0.data 0.216931 # miss rate for UpgradeReq accesses 3268system.l2c.UpgradeReq_miss_rate::cpu1.data 0.507788 # miss rate for UpgradeReq accesses 3269system.l2c.UpgradeReq_miss_rate::total 0.250795 # miss rate for UpgradeReq accesses 3270system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.245871 # miss rate for SCUpgradeReq accesses 3271system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.580297 # miss rate for SCUpgradeReq accesses 3272system.l2c.SCUpgradeReq_miss_rate::total 0.397995 # miss rate for SCUpgradeReq accesses 3273system.l2c.ReadExReq_miss_rate::cpu0.data 0.742569 # miss rate for ReadExReq accesses 3274system.l2c.ReadExReq_miss_rate::cpu1.data 0.866272 # miss rate for ReadExReq accesses 3275system.l2c.ReadExReq_miss_rate::total 0.791651 # miss rate for ReadExReq accesses 3276system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.142105 # miss rate for ReadSharedReq accesses 3277system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.038462 # miss rate for ReadSharedReq accesses 3278system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.372115 # miss rate for ReadSharedReq accesses 3279system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.164051 # miss rate for ReadSharedReq accesses 3280system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.743093 # miss rate for ReadSharedReq accesses 3281system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.087500 # miss rate for ReadSharedReq accesses 3282system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.033333 # miss rate for ReadSharedReq accesses 3283system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.175477 # miss rate for ReadSharedReq accesses 3284system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.104281 # miss rate for ReadSharedReq accesses 3285system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.598941 # miss rate for ReadSharedReq accesses 3286system.l2c.ReadSharedReq_miss_rate::total 0.529122 # miss rate for ReadSharedReq accesses 3287system.l2c.demand_miss_rate::cpu0.dtb.walker 0.142105 # miss rate for demand accesses 3288system.l2c.demand_miss_rate::cpu0.itb.walker 0.038462 # miss rate for demand accesses 3289system.l2c.demand_miss_rate::cpu0.inst 0.372115 # miss rate for demand accesses 3290system.l2c.demand_miss_rate::cpu0.data 0.290234 # miss rate for demand accesses 3291system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.743093 # miss rate for demand accesses 3292system.l2c.demand_miss_rate::cpu1.dtb.walker 0.087500 # miss rate for demand accesses 3293system.l2c.demand_miss_rate::cpu1.itb.walker 0.033333 # miss rate for demand accesses 3294system.l2c.demand_miss_rate::cpu1.inst 0.175477 # miss rate for demand accesses 3295system.l2c.demand_miss_rate::cpu1.data 0.473323 # miss rate for demand accesses 3296system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.598941 # miss rate for demand accesses 3297system.l2c.demand_miss_rate::total 0.548322 # miss rate for demand accesses 3298system.l2c.overall_miss_rate::cpu0.dtb.walker 0.142105 # miss rate for overall accesses 3299system.l2c.overall_miss_rate::cpu0.itb.walker 0.038462 # miss rate for overall accesses 3300system.l2c.overall_miss_rate::cpu0.inst 0.372115 # miss rate for overall accesses 3301system.l2c.overall_miss_rate::cpu0.data 0.290234 # miss rate for overall accesses 3302system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.743093 # miss rate for overall accesses 3303system.l2c.overall_miss_rate::cpu1.dtb.walker 0.087500 # miss rate for overall accesses 3304system.l2c.overall_miss_rate::cpu1.itb.walker 0.033333 # miss rate for overall accesses 3305system.l2c.overall_miss_rate::cpu1.inst 0.175477 # miss rate for overall accesses 3306system.l2c.overall_miss_rate::cpu1.data 0.473323 # miss rate for overall accesses 3307system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.598941 # miss rate for overall accesses 3308system.l2c.overall_miss_rate::total 0.548322 # miss rate for overall accesses 3309system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 971.170971 # average UpgradeReq miss latency 3310system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1043.486106 # average UpgradeReq miss latency 3311system.l2c.UpgradeReq_avg_miss_latency::total 988.217780 # average UpgradeReq miss latency 3312system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2183.206107 # average SCUpgradeReq miss latency 3313system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 886.046512 # average SCUpgradeReq miss latency 3314system.l2c.SCUpgradeReq_avg_miss_latency::total 1322.879177 # average SCUpgradeReq miss latency 3315system.l2c.ReadExReq_avg_miss_latency::cpu0.data 102734.538653 # average ReadExReq miss latency 3316system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83696.014777 # average ReadExReq miss latency 3317system.l2c.ReadExReq_avg_miss_latency::total 94468.626926 # average ReadExReq miss latency 3318system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 96259.259259 # average ReadSharedReq miss latency 3319system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 80333.333333 # average ReadSharedReq miss latency 3320system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83121.606507 # average ReadSharedReq miss latency 3321system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90991.431670 # average ReadSharedReq miss latency 3322system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 109385.457206 # average ReadSharedReq miss latency 3323system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 93142.857143 # average ReadSharedReq miss latency 3324system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 97500 # average ReadSharedReq miss latency 3325system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86073.534636 # average ReadSharedReq miss latency 3326system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 92859.388646 # average ReadSharedReq miss latency 3327system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 135196.630707 # average ReadSharedReq miss latency 3328system.l2c.ReadSharedReq_avg_miss_latency::total 106166.464924 # average ReadSharedReq miss latency 3329system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 96259.259259 # average overall miss latency 3330system.l2c.demand_avg_miss_latency::cpu0.itb.walker 80333.333333 # average overall miss latency 3331system.l2c.demand_avg_miss_latency::cpu0.inst 83121.606507 # average overall miss latency 3332system.l2c.demand_avg_miss_latency::cpu0.data 97544.650513 # average overall miss latency 3333system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 109385.457206 # average overall miss latency 3334system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 93142.857143 # average overall miss latency 3335system.l2c.demand_avg_miss_latency::cpu1.itb.walker 97500 # average overall miss latency 3336system.l2c.demand_avg_miss_latency::cpu1.inst 86073.534636 # average overall miss latency 3337system.l2c.demand_avg_miss_latency::cpu1.data 84737.100615 # average overall miss latency 3338system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 135196.630707 # average overall miss latency 3339system.l2c.demand_avg_miss_latency::total 104931.274568 # average overall miss latency 3340system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 96259.259259 # average overall miss latency 3341system.l2c.overall_avg_miss_latency::cpu0.itb.walker 80333.333333 # average overall miss latency 3342system.l2c.overall_avg_miss_latency::cpu0.inst 83121.606507 # average overall miss latency 3343system.l2c.overall_avg_miss_latency::cpu0.data 97544.650513 # average overall miss latency 3344system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 109385.457206 # average overall miss latency 3345system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 93142.857143 # average overall miss latency 3346system.l2c.overall_avg_miss_latency::cpu1.itb.walker 97500 # average overall miss latency 3347system.l2c.overall_avg_miss_latency::cpu1.inst 86073.534636 # average overall miss latency 3348system.l2c.overall_avg_miss_latency::cpu1.data 84737.100615 # average overall miss latency 3349system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 135196.630707 # average overall miss latency 3350system.l2c.overall_avg_miss_latency::total 104931.274568 # average overall miss latency 3351system.l2c.blocked_cycles::no_mshrs 21 # number of cycles access was blocked 3352system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3353system.l2c.blocked::no_mshrs 3 # number of cycles access was blocked 3354system.l2c.blocked::no_targets 0 # number of cycles access was blocked 3355system.l2c.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked 3356system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3357system.l2c.writebacks::writebacks 103743 # number of writebacks 3358system.l2c.writebacks::total 103743 # number of writebacks 3359system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 8 # number of ReadSharedReq MSHR hits 3360system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 8 # number of ReadSharedReq MSHR hits 3361system.l2c.ReadSharedReq_mshr_hits::total 16 # number of ReadSharedReq MSHR hits 3362system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits 3363system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits 3364system.l2c.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 3365system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits 3366system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits 3367system.l2c.overall_mshr_hits::total 16 # number of overall MSHR hits 3368system.l2c.CleanEvict_mshr_misses::writebacks 3708 # number of CleanEvict MSHR misses 3369system.l2c.CleanEvict_mshr_misses::total 3708 # number of CleanEvict MSHR misses 3370system.l2c.UpgradeReq_mshr_misses::cpu0.data 8984 # number of UpgradeReq MSHR misses 3371system.l2c.UpgradeReq_mshr_misses::cpu1.data 2771 # number of UpgradeReq MSHR misses 3372system.l2c.UpgradeReq_mshr_misses::total 11755 # number of UpgradeReq MSHR misses 3373system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 655 # number of SCUpgradeReq MSHR misses 3374system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1290 # number of SCUpgradeReq MSHR misses 3375system.l2c.SCUpgradeReq_mshr_misses::total 1945 # number of SCUpgradeReq MSHR misses 3376system.l2c.ReadExReq_mshr_misses::cpu0.data 11642 # number of ReadExReq MSHR misses 3377system.l2c.ReadExReq_mshr_misses::cpu1.data 8933 # number of ReadExReq MSHR misses 3378system.l2c.ReadExReq_mshr_misses::total 20575 # number of ReadExReq MSHR misses 3379system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 27 # number of ReadSharedReq MSHR misses 3380system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3 # number of ReadSharedReq MSHR misses 3381system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19662 # number of ReadSharedReq MSHR misses 3382system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9220 # number of ReadSharedReq MSHR misses 3383system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133244 # number of ReadSharedReq MSHR misses 3384system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 7 # number of ReadSharedReq MSHR misses 3385system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses 3386system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2807 # number of ReadSharedReq MSHR misses 3387system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1145 # number of ReadSharedReq MSHR misses 3388system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 8148 # number of ReadSharedReq MSHR misses 3389system.l2c.ReadSharedReq_mshr_misses::total 174264 # number of ReadSharedReq MSHR misses 3390system.l2c.demand_mshr_misses::cpu0.dtb.walker 27 # number of demand (read+write) MSHR misses 3391system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses 3392system.l2c.demand_mshr_misses::cpu0.inst 19662 # number of demand (read+write) MSHR misses 3393system.l2c.demand_mshr_misses::cpu0.data 20862 # number of demand (read+write) MSHR misses 3394system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133244 # number of demand (read+write) MSHR misses 3395system.l2c.demand_mshr_misses::cpu1.dtb.walker 7 # number of demand (read+write) MSHR misses 3396system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses 3397system.l2c.demand_mshr_misses::cpu1.inst 2807 # number of demand (read+write) MSHR misses 3398system.l2c.demand_mshr_misses::cpu1.data 10078 # number of demand (read+write) MSHR misses 3399system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 8148 # number of demand (read+write) MSHR misses 3400system.l2c.demand_mshr_misses::total 194839 # number of demand (read+write) MSHR misses 3401system.l2c.overall_mshr_misses::cpu0.dtb.walker 27 # number of overall MSHR misses 3402system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses 3403system.l2c.overall_mshr_misses::cpu0.inst 19662 # number of overall MSHR misses 3404system.l2c.overall_mshr_misses::cpu0.data 20862 # number of overall MSHR misses 3405system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133244 # number of overall MSHR misses 3406system.l2c.overall_mshr_misses::cpu1.dtb.walker 7 # number of overall MSHR misses 3407system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 3408system.l2c.overall_mshr_misses::cpu1.inst 2807 # number of overall MSHR misses 3409system.l2c.overall_mshr_misses::cpu1.data 10078 # number of overall MSHR misses 3410system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 8148 # number of overall MSHR misses 3411system.l2c.overall_mshr_misses::total 194839 # number of overall MSHR misses 3412system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable 3413system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31771 # number of ReadReq MSHR uncacheable 3414system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable 3415system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3075 # number of ReadReq MSHR uncacheable 3416system.l2c.ReadReq_mshr_uncacheable::total 37951 # number of ReadReq MSHR uncacheable 3417system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28450 # number of WriteReq MSHR uncacheable 3418system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2435 # number of WriteReq MSHR uncacheable 3419system.l2c.WriteReq_mshr_uncacheable::total 30885 # number of WriteReq MSHR uncacheable 3420system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses 3421system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60221 # number of overall MSHR uncacheable misses 3422system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses 3423system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5510 # number of overall MSHR uncacheable misses 3424system.l2c.overall_mshr_uncacheable_misses::total 68836 # number of overall MSHR uncacheable misses 3425system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 213623000 # number of UpgradeReq MSHR miss cycles 3426system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 63075000 # number of UpgradeReq MSHR miss cycles 3427system.l2c.UpgradeReq_mshr_miss_latency::total 276698000 # number of UpgradeReq MSHR miss cycles 3428system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16864000 # number of SCUpgradeReq MSHR miss cycles 3429system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 32149500 # number of SCUpgradeReq MSHR miss cycles 3430system.l2c.SCUpgradeReq_mshr_miss_latency::total 49013500 # number of SCUpgradeReq MSHR miss cycles 3431system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1079614502 # number of ReadExReq MSHR miss cycles 3432system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 658325502 # number of ReadExReq MSHR miss cycles 3433system.l2c.ReadExReq_mshr_miss_latency::total 1737940004 # number of ReadExReq MSHR miss cycles 3434system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 2329000 # number of ReadSharedReq MSHR miss cycles 3435system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 211000 # number of ReadSharedReq MSHR miss cycles 3436system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1437895505 # number of ReadSharedReq MSHR miss cycles 3437system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 746740501 # number of ReadSharedReq MSHR miss cycles 3438system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13242511370 # number of ReadSharedReq MSHR miss cycles 3439system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 582000 # number of ReadSharedReq MSHR miss cycles 3440system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 87500 # number of ReadSharedReq MSHR miss cycles 3441system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 213731003 # number of ReadSharedReq MSHR miss cycles 3442system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 94873501 # number of ReadSharedReq MSHR miss cycles 3443system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1020101648 # number of ReadSharedReq MSHR miss cycles 3444system.l2c.ReadSharedReq_mshr_miss_latency::total 16759063028 # number of ReadSharedReq MSHR miss cycles 3445system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2329000 # number of demand (read+write) MSHR miss cycles 3446system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 211000 # number of demand (read+write) MSHR miss cycles 3447system.l2c.demand_mshr_miss_latency::cpu0.inst 1437895505 # number of demand (read+write) MSHR miss cycles 3448system.l2c.demand_mshr_miss_latency::cpu0.data 1826355003 # number of demand (read+write) MSHR miss cycles 3449system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13242511370 # number of demand (read+write) MSHR miss cycles 3450system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 582000 # number of demand (read+write) MSHR miss cycles 3451system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 87500 # number of demand (read+write) MSHR miss cycles 3452system.l2c.demand_mshr_miss_latency::cpu1.inst 213731003 # number of demand (read+write) MSHR miss cycles 3453system.l2c.demand_mshr_miss_latency::cpu1.data 753199003 # number of demand (read+write) MSHR miss cycles 3454system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1020101648 # number of demand (read+write) MSHR miss cycles 3455system.l2c.demand_mshr_miss_latency::total 18497003032 # number of demand (read+write) MSHR miss cycles 3456system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2329000 # number of overall MSHR miss cycles 3457system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 211000 # number of overall MSHR miss cycles 3458system.l2c.overall_mshr_miss_latency::cpu0.inst 1437895505 # number of overall MSHR miss cycles 3459system.l2c.overall_mshr_miss_latency::cpu0.data 1826355003 # number of overall MSHR miss cycles 3460system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13242511370 # number of overall MSHR miss cycles 3461system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 582000 # number of overall MSHR miss cycles 3462system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 87500 # number of overall MSHR miss cycles 3463system.l2c.overall_mshr_miss_latency::cpu1.inst 213731003 # number of overall MSHR miss cycles 3464system.l2c.overall_mshr_miss_latency::cpu1.data 753199003 # number of overall MSHR miss cycles 3465system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1020101648 # number of overall MSHR miss cycles 3466system.l2c.overall_mshr_miss_latency::total 18497003032 # number of overall MSHR miss cycles 3467system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 192566500 # number of ReadReq MSHR uncacheable cycles 3468system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5794669001 # number of ReadReq MSHR uncacheable cycles 3469system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6627000 # number of ReadReq MSHR uncacheable cycles 3470system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 361914000 # number of ReadReq MSHR uncacheable cycles 3471system.l2c.ReadReq_mshr_uncacheable_latency::total 6355776501 # number of ReadReq MSHR uncacheable cycles 3472system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 192566500 # number of overall MSHR uncacheable cycles 3473system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5794669001 # number of overall MSHR uncacheable cycles 3474system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6627000 # number of overall MSHR uncacheable cycles 3475system.l2c.overall_mshr_uncacheable_latency::cpu1.data 361914000 # number of overall MSHR uncacheable cycles 3476system.l2c.overall_mshr_uncacheable_latency::total 6355776501 # number of overall MSHR uncacheable cycles 3477system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3478system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3479system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.216931 # mshr miss rate for UpgradeReq accesses 3480system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.507788 # mshr miss rate for UpgradeReq accesses 3481system.l2c.UpgradeReq_mshr_miss_rate::total 0.250795 # mshr miss rate for UpgradeReq accesses 3482system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.245871 # mshr miss rate for SCUpgradeReq accesses 3483system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.580297 # mshr miss rate for SCUpgradeReq accesses 3484system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.397995 # mshr miss rate for SCUpgradeReq accesses 3485system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.742569 # mshr miss rate for ReadExReq accesses 3486system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.866272 # mshr miss rate for ReadExReq accesses 3487system.l2c.ReadExReq_mshr_miss_rate::total 0.791651 # mshr miss rate for ReadExReq accesses 3488system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.142105 # mshr miss rate for ReadSharedReq accesses 3489system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.038462 # mshr miss rate for ReadSharedReq accesses 3490system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.371964 # mshr miss rate for ReadSharedReq accesses 3491system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.164051 # mshr miss rate for ReadSharedReq accesses 3492system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743093 # mshr miss rate for ReadSharedReq accesses 3493system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.087500 # mshr miss rate for ReadSharedReq accesses 3494system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for ReadSharedReq accesses 3495system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.174978 # mshr miss rate for ReadSharedReq accesses 3496system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.104281 # mshr miss rate for ReadSharedReq accesses 3497system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.598941 # mshr miss rate for ReadSharedReq accesses 3498system.l2c.ReadSharedReq_mshr_miss_rate::total 0.529073 # mshr miss rate for ReadSharedReq accesses 3499system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.142105 # mshr miss rate for demand accesses 3500system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.038462 # mshr miss rate for demand accesses 3501system.l2c.demand_mshr_miss_rate::cpu0.inst 0.371964 # mshr miss rate for demand accesses 3502system.l2c.demand_mshr_miss_rate::cpu0.data 0.290234 # mshr miss rate for demand accesses 3503system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743093 # mshr miss rate for demand accesses 3504system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.087500 # mshr miss rate for demand accesses 3505system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for demand accesses 3506system.l2c.demand_mshr_miss_rate::cpu1.inst 0.174978 # mshr miss rate for demand accesses 3507system.l2c.demand_mshr_miss_rate::cpu1.data 0.473323 # mshr miss rate for demand accesses 3508system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.598941 # mshr miss rate for demand accesses 3509system.l2c.demand_mshr_miss_rate::total 0.548277 # mshr miss rate for demand accesses 3510system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.142105 # mshr miss rate for overall accesses 3511system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.038462 # mshr miss rate for overall accesses 3512system.l2c.overall_mshr_miss_rate::cpu0.inst 0.371964 # mshr miss rate for overall accesses 3513system.l2c.overall_mshr_miss_rate::cpu0.data 0.290234 # mshr miss rate for overall accesses 3514system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743093 # mshr miss rate for overall accesses 3515system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.087500 # mshr miss rate for overall accesses 3516system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for overall accesses 3517system.l2c.overall_mshr_miss_rate::cpu1.inst 0.174978 # mshr miss rate for overall accesses 3518system.l2c.overall_mshr_miss_rate::cpu1.data 0.473323 # mshr miss rate for overall accesses 3519system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.598941 # mshr miss rate for overall accesses 3520system.l2c.overall_mshr_miss_rate::total 0.548277 # mshr miss rate for overall accesses 3521system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23778.161175 # average UpgradeReq mshr miss latency 3522system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22762.540599 # average UpgradeReq mshr miss latency 3523system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23538.749468 # average UpgradeReq mshr miss latency 3524system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25746.564885 # average SCUpgradeReq mshr miss latency 3525system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24922.093023 # average SCUpgradeReq mshr miss latency 3526system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25199.742931 # average SCUpgradeReq mshr miss latency 3527system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92734.453015 # average ReadExReq mshr miss latency 3528system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73695.903056 # average ReadExReq mshr miss latency 3529system.l2c.ReadExReq_avg_mshr_miss_latency::total 84468.529964 # average ReadExReq mshr miss latency 3530system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 86259.259259 # average ReadSharedReq mshr miss latency 3531system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average ReadSharedReq mshr miss latency 3532system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73130.683806 # average ReadSharedReq mshr miss latency 3533system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80991.377549 # average ReadSharedReq mshr miss latency 3534system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99385.423509 # average ReadSharedReq mshr miss latency 3535system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 83142.857143 # average ReadSharedReq mshr miss latency 3536system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 87500 # average ReadSharedReq mshr miss latency 3537system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76142.145707 # average ReadSharedReq mshr miss latency 3538system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82858.952838 # average ReadSharedReq mshr miss latency 3539system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125196.569465 # average ReadSharedReq mshr miss latency 3540system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96170.540261 # average ReadSharedReq mshr miss latency 3541system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86259.259259 # average overall mshr miss latency 3542system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency 3543system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73130.683806 # average overall mshr miss latency 3544system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87544.578804 # average overall mshr miss latency 3545system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99385.423509 # average overall mshr miss latency 3546system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 83142.857143 # average overall mshr miss latency 3547system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 87500 # average overall mshr miss latency 3548system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76142.145707 # average overall mshr miss latency 3549system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74736.952074 # average overall mshr miss latency 3550system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125196.569465 # average overall mshr miss latency 3551system.l2c.demand_avg_mshr_miss_latency::total 94934.807877 # average overall mshr miss latency 3552system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86259.259259 # average overall mshr miss latency 3553system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency 3554system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73130.683806 # average overall mshr miss latency 3555system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87544.578804 # average overall mshr miss latency 3556system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99385.423509 # average overall mshr miss latency 3557system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83142.857143 # average overall mshr miss latency 3558system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 87500 # average overall mshr miss latency 3559system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76142.145707 # average overall mshr miss latency 3560system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74736.952074 # average overall mshr miss latency 3561system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125196.569465 # average overall mshr miss latency 3562system.l2c.overall_avg_mshr_miss_latency::total 94934.807877 # average overall mshr miss latency 3563system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average ReadReq mshr uncacheable latency 3564system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182388.624878 # average ReadReq mshr uncacheable latency 3565system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64970.588235 # average ReadReq mshr uncacheable latency 3566system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117695.609756 # average ReadReq mshr uncacheable latency 3567system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167473.228663 # average ReadReq mshr uncacheable latency 3568system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average overall mshr uncacheable latency 3569system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96223.393849 # average overall mshr uncacheable latency 3570system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64970.588235 # average overall mshr uncacheable latency 3571system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65683.121597 # average overall mshr uncacheable latency 3572system.l2c.overall_avg_mshr_uncacheable_latency::total 92332.159059 # average overall mshr uncacheable latency 3573system.membus.snoop_filter.tot_requests 523609 # Total number of requests made to the snoop filter. 3574system.membus.snoop_filter.hit_single_requests 298426 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3575system.membus.snoop_filter.hit_multi_requests 572 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3576system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3577system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3578system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3579system.membus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3580system.membus.trans_dist::ReadReq 37951 # Transaction distribution 3581system.membus.trans_dist::ReadResp 212466 # Transaction distribution 3582system.membus.trans_dist::WriteReq 30885 # Transaction distribution 3583system.membus.trans_dist::WriteResp 30885 # Transaction distribution 3584system.membus.trans_dist::WritebackDirty 139949 # Transaction distribution 3585system.membus.trans_dist::CleanEvict 17155 # Transaction distribution 3586system.membus.trans_dist::UpgradeReq 74789 # Transaction distribution 3587system.membus.trans_dist::SCUpgradeReq 40592 # Transaction distribution 3588system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 3589system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 3590system.membus.trans_dist::ReadExReq 40333 # Transaction distribution 3591system.membus.trans_dist::ReadExResp 20490 # Transaction distribution 3592system.membus.trans_dist::ReadSharedReq 174516 # Transaction distribution 3593system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 3594system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes) 3595system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes) 3596system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13608 # Packet count per connected master and slave (bytes) 3597system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661161 # Packet count per connected master and slave (bytes) 3598system.membus.pkt_count_system.l2c.mem_side::total 782719 # Packet count per connected master and slave (bytes) 3599system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) 3600system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) 3601system.membus.pkt_count::total 855668 # Packet count per connected master and slave (bytes) 3602system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) 3603system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes) 3604system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27216 # Cumulative packet size per connected master and slave (bytes) 3605system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19151816 # Cumulative packet size per connected master and slave (bytes) 3606system.membus.pkt_size_system.l2c.mem_side::total 19342114 # Cumulative packet size per connected master and slave (bytes) 3607system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 3608system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) 3609system.membus.pkt_size::total 21660258 # Cumulative packet size per connected master and slave (bytes) 3610system.membus.snoops 122014 # Total snoops (count) 3611system.membus.snoop_fanout::samples 435296 # Request fanout histogram 3612system.membus.snoop_fanout::mean 0.011884 # Request fanout histogram 3613system.membus.snoop_fanout::stdev 0.108364 # Request fanout histogram 3614system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3615system.membus.snoop_fanout::0 430123 98.81% 98.81% # Request fanout histogram 3616system.membus.snoop_fanout::1 5173 1.19% 100.00% # Request fanout histogram 3617system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3618system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3619system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3620system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3621system.membus.snoop_fanout::total 435296 # Request fanout histogram 3622system.membus.reqLayer0.occupancy 81593499 # Layer occupancy (ticks) 3623system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3624system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks) 3625system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3626system.membus.reqLayer2.occupancy 11516500 # Layer occupancy (ticks) 3627system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3628system.membus.reqLayer5.occupancy 1022226685 # Layer occupancy (ticks) 3629system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3630system.membus.respLayer2.occupancy 1121401156 # Layer occupancy (ticks) 3631system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3632system.membus.respLayer3.occupancy 1360881 # Layer occupancy (ticks) 3633system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3634system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3635system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3636system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3637system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3638system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3639system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3640system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3641system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3642system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3643system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3644system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3645system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3646system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3647system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3648system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3649system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3650system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3651system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3652system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3653system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3654system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3655system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3656system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3657system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3658system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3659system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3660system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3661system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3662system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3663system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3664system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3665system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3666system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3667system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3668system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3669system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3670system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3671system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3672system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3673system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3674system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3675system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3676system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3677system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3678system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3679system.realview.ethernet.droppedPackets 0 # number of packets dropped 3680system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3681system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3682system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3683system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3684system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3685system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3686system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3687system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3688system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3689system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3690system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3691system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3692system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3693system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3694system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3695system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3696system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3697system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3698system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3699system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3700system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3701system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3702system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3703system.toL2Bus.snoop_filter.tot_requests 1012829 # Total number of requests made to the snoop filter. 3704system.toL2Bus.snoop_filter.hit_single_requests 548493 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3705system.toL2Bus.snoop_filter.hit_multi_requests 154614 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3706system.toL2Bus.snoop_filter.tot_snoops 20965 # Total number of snoops made to the snoop filter. 3707system.toL2Bus.snoop_filter.hit_single_snoops 19995 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3708system.toL2Bus.snoop_filter.hit_multi_snoops 970 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3709system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states 3710system.toL2Bus.trans_dist::ReadReq 37954 # Transaction distribution 3711system.toL2Bus.trans_dist::ReadResp 485832 # Transaction distribution 3712system.toL2Bus.trans_dist::WriteReq 30885 # Transaction distribution 3713system.toL2Bus.trans_dist::WriteResp 30885 # Transaction distribution 3714system.toL2Bus.trans_dist::WritebackDirty 370603 # Transaction distribution 3715system.toL2Bus.trans_dist::CleanEvict 122893 # Transaction distribution 3716system.toL2Bus.trans_dist::UpgradeReq 109820 # Transaction distribution 3717system.toL2Bus.trans_dist::SCUpgradeReq 43534 # Transaction distribution 3718system.toL2Bus.trans_dist::UpgradeResp 153354 # Transaction distribution 3719system.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution 3720system.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution 3721system.toL2Bus.trans_dist::ReadExReq 51065 # Transaction distribution 3722system.toL2Bus.trans_dist::ReadExResp 51065 # Transaction distribution 3723system.toL2Bus.trans_dist::ReadSharedReq 447881 # Transaction distribution 3724system.toL2Bus.trans_dist::InvalidateReq 4599 # Transaction distribution 3725system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1241884 # Packet count per connected master and slave (bytes) 3726system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 315944 # Packet count per connected master and slave (bytes) 3727system.toL2Bus.pkt_count::total 1557828 # Packet count per connected master and slave (bytes) 3728system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34423168 # Cumulative packet size per connected master and slave (bytes) 3729system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5674082 # Cumulative packet size per connected master and slave (bytes) 3730system.toL2Bus.pkt_size::total 40097250 # Cumulative packet size per connected master and slave (bytes) 3731system.toL2Bus.snoops 382843 # Total snoops (count) 3732system.toL2Bus.snoop_fanout::samples 858573 # Request fanout histogram 3733system.toL2Bus.snoop_fanout::mean 0.374933 # Request fanout histogram 3734system.toL2Bus.snoop_fanout::stdev 0.486434 # Request fanout histogram 3735system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3736system.toL2Bus.snoop_fanout::0 537636 62.62% 62.62% # Request fanout histogram 3737system.toL2Bus.snoop_fanout::1 319967 37.27% 99.89% # Request fanout histogram 3738system.toL2Bus.snoop_fanout::2 970 0.11% 100.00% # Request fanout histogram 3739system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3740system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3741system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3742system.toL2Bus.snoop_fanout::total 858573 # Request fanout histogram 3743system.toL2Bus.reqLayer0.occupancy 885446562 # Layer occupancy (ticks) 3744system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3745system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks) 3746system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3747system.toL2Bus.respLayer0.occupancy 647873032 # Layer occupancy (ticks) 3748system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3749system.toL2Bus.respLayer1.occupancy 232753441 # Layer occupancy (ticks) 3750system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3751system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3752system.cpu0.kern.inst.quiesce 1828 # number of quiesce instructions executed 3753system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3754system.cpu1.kern.inst.quiesce 2763 # number of quiesce instructions executed 3755 3756---------- End Simulation Statistics ----------