1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.825951 # Number of seconds simulated
4sim_ticks 2825951018000 # Number of ticks simulated
5final_tick 2825951018000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 126581 # Simulator instruction rate (inst/s)
8host_op_rate 153564 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2973571752 # Simulator tick rate (ticks/s)
10host_mem_usage 617520 # Number of bytes of host memory used
11host_seconds 950.36 # Real time elapsed on the host
12sim_insts 120297223 # Number of instructions simulated
13sim_ops 145940268 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1286144 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 1281192 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8384576 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 320 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 188912 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 582932 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 428544 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
27system.physmem.bytes_read::total 12155436 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 1286144 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 188912 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 1475056 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 8692480 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
34system.physmem.bytes_written::total 8710044 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 22343 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 20539 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 131009 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 5 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.inst 3020 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.data 9129 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.l2cache.prefetcher 6696 # Number of read requests responded to by this memory
45system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
46system.physmem.num_reads::total 192785 # Number of read requests responded to by this memory
47system.physmem.num_writes::writebacks 135820 # Number of write requests responded to by this memory
48system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
50system.physmem.num_writes::total 140211 # Number of write requests responded to by this memory
51system.physmem.bw_read::cpu0.dtb.walker 566 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.inst 455119 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.data 453367 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.l2cache.prefetcher 2966993 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.dtb.walker 113 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.inst 66849 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.data 206278 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.l2cache.prefetcher 151646 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::total 4301361 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::cpu0.inst 455119 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu1.inst 66849 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::total 521968 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_write::writebacks 3075949 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::cpu0.data 6201 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::total 3082164 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_total::writebacks 3075949 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.dtb.walker 566 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.inst 455119 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.data 459568 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.l2cache.prefetcher 2966993 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.inst 66849 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.data 206292 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.l2cache.prefetcher 151646 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::total 7383525 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.readReqs 192786 # Number of read requests accepted
84system.physmem.writeReqs 140211 # Number of write requests accepted
85system.physmem.readBursts 192786 # Number of DRAM read bursts, including those serviced by the write queue
86system.physmem.writeBursts 140211 # Number of DRAM write bursts, including those merged in the write queue
87system.physmem.bytesReadDRAM 12328960 # Total number of bytes read from DRAM
88system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue
89system.physmem.bytesWritten 8722752 # Total number of bytes written to DRAM
90system.physmem.bytesReadSys 12155500 # Total read bytes from the system interface side
91system.physmem.bytesWrittenSys 8710044 # Total written bytes from the system interface side
92system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue
93system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one
94system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
95system.physmem.perBankRdBursts::0 11498 # Per bank write bursts
96system.physmem.perBankRdBursts::1 11843 # Per bank write bursts
97system.physmem.perBankRdBursts::2 12508 # Per bank write bursts
98system.physmem.perBankRdBursts::3 12790 # Per bank write bursts
99system.physmem.perBankRdBursts::4 14191 # Per bank write bursts
100system.physmem.perBankRdBursts::5 11869 # Per bank write bursts
101system.physmem.perBankRdBursts::6 11798 # Per bank write bursts
102system.physmem.perBankRdBursts::7 11857 # Per bank write bursts
103system.physmem.perBankRdBursts::8 12385 # Per bank write bursts
104system.physmem.perBankRdBursts::9 12638 # Per bank write bursts
105system.physmem.perBankRdBursts::10 11524 # Per bank write bursts
106system.physmem.perBankRdBursts::11 10795 # Per bank write bursts
107system.physmem.perBankRdBursts::12 11419 # Per bank write bursts
108system.physmem.perBankRdBursts::13 12202 # Per bank write bursts
109system.physmem.perBankRdBursts::14 11695 # Per bank write bursts
110system.physmem.perBankRdBursts::15 11628 # Per bank write bursts
111system.physmem.perBankWrBursts::0 8335 # Per bank write bursts
112system.physmem.perBankWrBursts::1 8752 # Per bank write bursts
113system.physmem.perBankWrBursts::2 9292 # Per bank write bursts
114system.physmem.perBankWrBursts::3 9229 # Per bank write bursts
115system.physmem.perBankWrBursts::4 7962 # Per bank write bursts
116system.physmem.perBankWrBursts::5 8394 # Per bank write bursts
117system.physmem.perBankWrBursts::6 8300 # Per bank write bursts
118system.physmem.perBankWrBursts::7 8278 # Per bank write bursts
119system.physmem.perBankWrBursts::8 8796 # Per bank write bursts
120system.physmem.perBankWrBursts::9 9162 # Per bank write bursts
121system.physmem.perBankWrBursts::10 8546 # Per bank write bursts
122system.physmem.perBankWrBursts::11 8147 # Per bank write bursts
123system.physmem.perBankWrBursts::12 8256 # Per bank write bursts
124system.physmem.perBankWrBursts::13 8410 # Per bank write bursts
125system.physmem.perBankWrBursts::14 8295 # Per bank write bursts
126system.physmem.perBankWrBursts::15 8139 # Per bank write bursts
127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128system.physmem.numWrRetry 6 # Number of times write queue was full causing retry
129system.physmem.totGap 2825950731000 # Total gap between requests
130system.physmem.readPktSize::0 0 # Read request sizes (log2)
131system.physmem.readPktSize::1 0 # Read request sizes (log2)
132system.physmem.readPktSize::2 551 # Read request sizes (log2)
133system.physmem.readPktSize::3 28 # Read request sizes (log2)
134system.physmem.readPktSize::4 3087 # Read request sizes (log2)
135system.physmem.readPktSize::5 0 # Read request sizes (log2)
136system.physmem.readPktSize::6 189120 # Read request sizes (log2)
137system.physmem.writePktSize::0 0 # Write request sizes (log2)
138system.physmem.writePktSize::1 0 # Write request sizes (log2)
139system.physmem.writePktSize::2 4391 # Write request sizes (log2)
140system.physmem.writePktSize::3 0 # Write request sizes (log2)
141system.physmem.writePktSize::4 0 # Write request sizes (log2)
142system.physmem.writePktSize::5 0 # Write request sizes (log2)
143system.physmem.writePktSize::6 135820 # Write request sizes (log2)
144system.physmem.rdQLenPdf::0 58633 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 71115 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 15338 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 12619 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 8378 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 7227 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 6243 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::7 5114 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::8 4480 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::9 1398 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::10 907 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::11 653 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::12 279 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::13 238 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
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183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::15 2723 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::16 3577 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::17 4190 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::18 4774 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::19 5406 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::20 5763 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::21 6710 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::22 7308 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::23 8419 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::24 8358 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::25 9796 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::26 10601 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::27 9066 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::28 9176 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::29 10699 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::30 8900 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::31 8132 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::32 7787 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::33 704 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::34 533 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::35 411 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::36 241 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::37 198 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::38 196 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::39 211 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::40 152 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::41 138 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::42 188 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::43 175 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::44 157 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::45 93 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::46 157 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::48 89 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::49 105 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::50 126 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::52 85 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::53 125 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::55 96 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::56 108 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::57 112 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::58 47 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::59 38 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::61 26 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see
240system.physmem.bytesPerActivate::samples 88838 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::mean 236.966703 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::gmean 133.563892 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::stdev 301.532977 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::0-127 48504 54.60% 54.60% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::128-255 17119 19.27% 73.87% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::256-383 5692 6.41% 80.28% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::384-511 3330 3.75% 84.02% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::512-639 2666 3.00% 87.02% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::640-767 1452 1.63% 88.66% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::768-895 904 1.02% 89.68% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::896-1023 1002 1.13% 90.80% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::1024-1151 8169 9.20% 100.00% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::total 88838 # Bytes accessed per row activation
254system.physmem.rdPerTurnAround::samples 6725 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::mean 28.644610 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::stdev 576.008815 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::0-2047 6723 99.97% 99.97% # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::total 6725 # Reads before turning the bus around for writes
261system.physmem.wrPerTurnAround::samples 6725 # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::mean 20.266617 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::gmean 18.732165 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::stdev 12.286650 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::16-19 5583 83.02% 83.02% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::20-23 392 5.83% 88.85% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::24-27 83 1.23% 90.08% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::28-31 55 0.82% 90.90% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::32-35 273 4.06% 94.96% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::36-39 27 0.40% 95.36% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::40-43 22 0.33% 95.69% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::44-47 18 0.27% 95.96% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::48-51 21 0.31% 96.27% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::52-55 12 0.18% 96.45% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::56-59 9 0.13% 96.58% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::60-63 9 0.13% 96.71% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::64-67 148 2.20% 98.91% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::68-71 9 0.13% 99.05% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::72-75 7 0.10% 99.15% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::76-79 7 0.10% 99.26% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::80-83 12 0.18% 99.43% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::84-87 3 0.04% 99.48% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::88-91 1 0.01% 99.49% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::92-95 2 0.03% 99.52% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::96-99 2 0.03% 99.55% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::100-103 2 0.03% 99.58% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::104-107 2 0.03% 99.61% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::108-111 4 0.06% 99.67% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::116-119 1 0.01% 99.69% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::128-131 11 0.16% 99.85% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::132-135 1 0.01% 99.87% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::140-143 3 0.04% 99.91% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::144-147 1 0.01% 99.93% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::152-155 1 0.01% 99.94% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::160-163 3 0.04% 99.99% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::172-175 1 0.01% 100.00% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::total 6725 # Writes before turning the bus around for reads
298system.physmem.totQLat 6328126220 # Total ticks spent queuing
299system.physmem.totMemAccLat 9940126220 # Total ticks spent from burst creation until serviced by the DRAM
300system.physmem.totBusLat 963200000 # Total ticks spent in databus transfers
301system.physmem.avgQLat 32849.49 # Average queueing delay per DRAM burst
302system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
303system.physmem.avgMemAccLat 51599.49 # Average memory access latency per DRAM burst
304system.physmem.avgRdBW 4.36 # Average DRAM read bandwidth in MiByte/s
305system.physmem.avgWrBW 3.09 # Average achieved write bandwidth in MiByte/s
306system.physmem.avgRdBWSys 4.30 # Average system read bandwidth in MiByte/s
307system.physmem.avgWrBWSys 3.08 # Average system write bandwidth in MiByte/s
308system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
309system.physmem.busUtil 0.06 # Data bus utilization in percentage
310system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
311system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
312system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
313system.physmem.avgWrQLen 21.86 # Average write queue length when enqueuing
314system.physmem.readRowHits 160949 # Number of row buffer hits during reads
315system.physmem.writeRowHits 79145 # Number of row buffer hits during writes
316system.physmem.readRowHitRate 83.55 # Row buffer hit rate for reads
317system.physmem.writeRowHitRate 58.06 # Row buffer hit rate for writes
318system.physmem.avgGap 8486414.99 # Average gap between requests
319system.physmem.pageHitRate 72.99 # Row buffer hit rate, read and write combined
320system.physmem_0.actEnergy 340562880 # Energy for activate commands per rank (pJ)
321system.physmem_0.preEnergy 185823000 # Energy for precharge commands per rank (pJ)
322system.physmem_0.readEnergy 767153400 # Energy for read commands per rank (pJ)
323system.physmem_0.writeEnergy 444152160 # Energy for write commands per rank (pJ)
324system.physmem_0.refreshEnergy 184577274960 # Energy for refresh commands per rank (pJ)
325system.physmem_0.actBackEnergy 79601761125 # Energy for active background per rank (pJ)
326system.physmem_0.preBackEnergy 1625743658250 # Energy for precharge background per rank (pJ)
327system.physmem_0.totalEnergy 1891660385775 # Total energy per rank (pJ)
328system.physmem_0.averagePower 669.389284 # Core power per rank (mW)
329system.physmem_0.memoryStateTime::IDLE 2704476978140 # Time in different power states
330system.physmem_0.memoryStateTime::REF 94364660000 # Time in different power states
331system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
332system.physmem_0.memoryStateTime::ACT 27109359860 # Time in different power states
333system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
334system.physmem_1.actEnergy 331052400 # Energy for activate commands per rank (pJ)
335system.physmem_1.preEnergy 180633750 # Energy for precharge commands per rank (pJ)
336system.physmem_1.readEnergy 735430800 # Energy for read commands per rank (pJ)
337system.physmem_1.writeEnergy 439026480 # Energy for write commands per rank (pJ)
338system.physmem_1.refreshEnergy 184577274960 # Energy for refresh commands per rank (pJ)
339system.physmem_1.actBackEnergy 79228268055 # Energy for active background per rank (pJ)
340system.physmem_1.preBackEnergy 1626071283750 # Energy for precharge background per rank (pJ)
341system.physmem_1.totalEnergy 1891562970195 # Total energy per rank (pJ)
342system.physmem_1.averagePower 669.354813 # Core power per rank (mW)
343system.physmem_1.memoryStateTime::IDLE 2705022466825 # Time in different power states
344system.physmem_1.memoryStateTime::REF 94364660000 # Time in different power states
345system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
346system.physmem_1.memoryStateTime::ACT 26562494425 # Time in different power states
347system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
348system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory
349system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory
350system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory
351system.realview.nvmem.bytes_inst_read::cpu0.inst 112 # Number of instructions bytes read from this memory
352system.realview.nvmem.bytes_inst_read::cpu1.inst 176 # Number of instructions bytes read from this memory
353system.realview.nvmem.bytes_inst_read::total 288 # Number of instructions bytes read from this memory
354system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory

--- 9 unchanged lines hidden (view full) ---

364system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s)
365system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s)
366system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
367system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
368system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
369system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
370system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
371system.cf0.dma_write_txs 631 # Number of DMA write transactions.
372system.cpu0.branchPred.lookups 23820996 # Number of BP lookups
373system.cpu0.branchPred.condPredicted 15588859 # Number of conditional branches predicted
374system.cpu0.branchPred.condIncorrect 920395 # Number of conditional branches incorrect
375system.cpu0.branchPred.BTBLookups 14518297 # Number of BTB lookups
376system.cpu0.branchPred.BTBHits 9504336 # Number of BTB hits
377system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
378system.cpu0.branchPred.BTBHitPct 65.464538 # BTB Hit Percentage
379system.cpu0.branchPred.usedRAS 3840995 # Number of times the RAS was used to get a target.
380system.cpu0.branchPred.RASInCorrect 33136 # Number of incorrect RAS predictions.
381system.cpu0.branchPred.indirectLookups 1356781 # Number of indirect predictor lookups.
382system.cpu0.branchPred.indirectHits 1203053 # Number of indirect target hits.
383system.cpu0.branchPred.indirectMisses 153728 # Number of indirect misses.
384system.cpu0.branchPredindirectMispredicted 48358 # Number of mispredicted indirect branches.
385system.cpu_clk_domain.clock 500 # Clock period in ticks
386system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

407system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
408system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
409system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
410system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
411system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
412system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
413system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
414system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
415system.cpu0.dtb.walker.walks 66654 # Table walker walks requested
416system.cpu0.dtb.walker.walksShort 66654 # Table walker walks initiated with short descriptors
417system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25108 # Level at which table walker walks with short descriptors terminate
418system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18968 # Level at which table walker walks with short descriptors terminate
419system.cpu0.dtb.walker.walksSquashedBefore 22578 # Table walks squashed before starting
420system.cpu0.dtb.walker.walkWaitTime::samples 44076 # Table walker wait (enqueue to first request) latency
421system.cpu0.dtb.walker.walkWaitTime::mean 460.137036 # Table walker wait (enqueue to first request) latency
422system.cpu0.dtb.walker.walkWaitTime::stdev 2988.406264 # Table walker wait (enqueue to first request) latency
423system.cpu0.dtb.walker.walkWaitTime::0-8191 42948 97.44% 97.44% # Table walker wait (enqueue to first request) latency
424system.cpu0.dtb.walker.walkWaitTime::8192-16383 855 1.94% 99.38% # Table walker wait (enqueue to first request) latency
425system.cpu0.dtb.walker.walkWaitTime::16384-24575 123 0.28% 99.66% # Table walker wait (enqueue to first request) latency
426system.cpu0.dtb.walker.walkWaitTime::24576-32767 110 0.25% 99.91% # Table walker wait (enqueue to first request) latency
427system.cpu0.dtb.walker.walkWaitTime::32768-40959 6 0.01% 99.92% # Table walker wait (enqueue to first request) latency
428system.cpu0.dtb.walker.walkWaitTime::40960-49151 18 0.04% 99.96% # Table walker wait (enqueue to first request) latency
429system.cpu0.dtb.walker.walkWaitTime::57344-65535 13 0.03% 99.99% # Table walker wait (enqueue to first request) latency
430system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
431system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
432system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
433system.cpu0.dtb.walker.walkWaitTime::total 44076 # Table walker wait (enqueue to first request) latency
434system.cpu0.dtb.walker.walkCompletionTime::samples 16898 # Table walker service (enqueue to completion) latency
435system.cpu0.dtb.walker.walkCompletionTime::mean 11121.375311 # Table walker service (enqueue to completion) latency
436system.cpu0.dtb.walker.walkCompletionTime::gmean 9757.603879 # Table walker service (enqueue to completion) latency
437system.cpu0.dtb.walker.walkCompletionTime::stdev 6791.562531 # Table walker service (enqueue to completion) latency
438system.cpu0.dtb.walker.walkCompletionTime::0-16383 15594 92.28% 92.28% # Table walker service (enqueue to completion) latency
439system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1190 7.04% 99.33% # Table walker service (enqueue to completion) latency
440system.cpu0.dtb.walker.walkCompletionTime::32768-49151 80 0.47% 99.80% # Table walker service (enqueue to completion) latency
441system.cpu0.dtb.walker.walkCompletionTime::49152-65535 11 0.07% 99.86% # Table walker service (enqueue to completion) latency
442system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.01% 99.87% # Table walker service (enqueue to completion) latency
443system.cpu0.dtb.walker.walkCompletionTime::98304-114687 8 0.05% 99.92% # Table walker service (enqueue to completion) latency
444system.cpu0.dtb.walker.walkCompletionTime::114688-131071 13 0.08% 99.99% # Table walker service (enqueue to completion) latency
445system.cpu0.dtb.walker.walkCompletionTime::229376-245759 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
446system.cpu0.dtb.walker.walkCompletionTime::total 16898 # Table walker service (enqueue to completion) latency
447system.cpu0.dtb.walker.walksPending::samples 90055870948 # Table walker pending requests distribution
448system.cpu0.dtb.walker.walksPending::mean 0.547875 # Table walker pending requests distribution
449system.cpu0.dtb.walker.walksPending::stdev 0.509370 # Table walker pending requests distribution
450system.cpu0.dtb.walker.walksPending::0-1 89997968948 99.94% 99.94% # Table walker pending requests distribution
451system.cpu0.dtb.walker.walksPending::2-3 40556500 0.05% 99.98% # Table walker pending requests distribution
452system.cpu0.dtb.walker.walksPending::4-5 7037000 0.01% 99.99% # Table walker pending requests distribution
453system.cpu0.dtb.walker.walksPending::6-7 4893500 0.01% 99.99% # Table walker pending requests distribution
454system.cpu0.dtb.walker.walksPending::8-9 1776500 0.00% 100.00% # Table walker pending requests distribution
455system.cpu0.dtb.walker.walksPending::10-11 1132500 0.00% 100.00% # Table walker pending requests distribution
456system.cpu0.dtb.walker.walksPending::12-13 1239500 0.00% 100.00% # Table walker pending requests distribution
457system.cpu0.dtb.walker.walksPending::14-15 1264500 0.00% 100.00% # Table walker pending requests distribution
458system.cpu0.dtb.walker.walksPending::16-17 2000 0.00% 100.00% # Table walker pending requests distribution
459system.cpu0.dtb.walker.walksPending::total 90055870948 # Table walker pending requests distribution
460system.cpu0.dtb.walker.walkPageSizes::4K 5227 78.38% 78.38% # Table walker page sizes translated
461system.cpu0.dtb.walker.walkPageSizes::1M 1442 21.62% 100.00% # Table walker page sizes translated
462system.cpu0.dtb.walker.walkPageSizes::total 6669 # Table walker page sizes translated
463system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66654 # Table walker requests started/completed, data/inst
464system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
465system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66654 # Table walker requests started/completed, data/inst
466system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6669 # Table walker requests started/completed, data/inst
467system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
468system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6669 # Table walker requests started/completed, data/inst
469system.cpu0.dtb.walker.walkRequestOrigin::total 73323 # Table walker requests started/completed, data/inst
470system.cpu0.dtb.inst_hits 0 # ITB inst hits
471system.cpu0.dtb.inst_misses 0 # ITB inst misses
472system.cpu0.dtb.read_hits 17666854 # DTB read hits
473system.cpu0.dtb.read_misses 56136 # DTB read misses
474system.cpu0.dtb.write_hits 14559303 # DTB write hits
475system.cpu0.dtb.write_misses 10518 # DTB write misses
476system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
477system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
478system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
479system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
480system.cpu0.dtb.flush_entries 3504 # Number of entries that have been flushed from TLB
481system.cpu0.dtb.align_faults 145 # Number of TLB faults due to alignment restrictions
482system.cpu0.dtb.prefetch_faults 2262 # Number of TLB faults due to prefetch
483system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
484system.cpu0.dtb.perms_faults 861 # Number of TLB faults due to permissions restrictions
485system.cpu0.dtb.read_accesses 17722990 # DTB read accesses
486system.cpu0.dtb.write_accesses 14569821 # DTB write accesses
487system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
488system.cpu0.dtb.hits 32226157 # DTB hits
489system.cpu0.dtb.misses 66654 # DTB misses
490system.cpu0.dtb.accesses 32292811 # DTB accesses
491system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
492system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
493system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
494system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
495system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
496system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
497system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
498system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

512system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
513system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
514system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
515system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
516system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
517system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
518system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
519system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
520system.cpu0.itb.walker.walks 10841 # Table walker walks requested
521system.cpu0.itb.walker.walksShort 10841 # Table walker walks initiated with short descriptors
522system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3909 # Level at which table walker walks with short descriptors terminate
523system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5864 # Level at which table walker walks with short descriptors terminate
524system.cpu0.itb.walker.walksSquashedBefore 1068 # Table walks squashed before starting
525system.cpu0.itb.walker.walkWaitTime::samples 9773 # Table walker wait (enqueue to first request) latency
526system.cpu0.itb.walker.walkWaitTime::mean 421.927760 # Table walker wait (enqueue to first request) latency
527system.cpu0.itb.walker.walkWaitTime::stdev 2234.177799 # Table walker wait (enqueue to first request) latency
528system.cpu0.itb.walker.walkWaitTime::0-4095 9414 96.33% 96.33% # Table walker wait (enqueue to first request) latency
529system.cpu0.itb.walker.walkWaitTime::4096-8191 161 1.65% 97.97% # Table walker wait (enqueue to first request) latency
530system.cpu0.itb.walker.walkWaitTime::8192-12287 108 1.11% 99.08% # Table walker wait (enqueue to first request) latency
531system.cpu0.itb.walker.walkWaitTime::12288-16383 59 0.60% 99.68% # Table walker wait (enqueue to first request) latency
532system.cpu0.itb.walker.walkWaitTime::16384-20479 8 0.08% 99.76% # Table walker wait (enqueue to first request) latency
533system.cpu0.itb.walker.walkWaitTime::20480-24575 12 0.12% 99.89% # Table walker wait (enqueue to first request) latency
534system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.92% # Table walker wait (enqueue to first request) latency
535system.cpu0.itb.walker.walkWaitTime::28672-32767 3 0.03% 99.95% # Table walker wait (enqueue to first request) latency
536system.cpu0.itb.walker.walkWaitTime::32768-36863 3 0.03% 99.98% # Table walker wait (enqueue to first request) latency
537system.cpu0.itb.walker.walkWaitTime::36864-40959 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency
538system.cpu0.itb.walker.walkWaitTime::total 9773 # Table walker wait (enqueue to first request) latency
539system.cpu0.itb.walker.walkCompletionTime::samples 3645 # Table walker service (enqueue to completion) latency
540system.cpu0.itb.walker.walkCompletionTime::mean 12199.451303 # Table walker service (enqueue to completion) latency
541system.cpu0.itb.walker.walkCompletionTime::gmean 11419.234768 # Table walker service (enqueue to completion) latency
542system.cpu0.itb.walker.walkCompletionTime::stdev 4654.618910 # Table walker service (enqueue to completion) latency
543system.cpu0.itb.walker.walkCompletionTime::0-8191 570 15.64% 15.64% # Table walker service (enqueue to completion) latency
544system.cpu0.itb.walker.walkCompletionTime::8192-16383 2859 78.44% 94.07% # Table walker service (enqueue to completion) latency
545system.cpu0.itb.walker.walkCompletionTime::16384-24575 148 4.06% 98.13% # Table walker service (enqueue to completion) latency
546system.cpu0.itb.walker.walkCompletionTime::24576-32767 43 1.18% 99.31% # Table walker service (enqueue to completion) latency
547system.cpu0.itb.walker.walkCompletionTime::32768-40959 22 0.60% 99.92% # Table walker service (enqueue to completion) latency
548system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.03% 99.95% # Table walker service (enqueue to completion) latency
549system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
550system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
551system.cpu0.itb.walker.walkCompletionTime::total 3645 # Table walker service (enqueue to completion) latency
552system.cpu0.itb.walker.walksPending::samples 21336382212 # Table walker pending requests distribution
553system.cpu0.itb.walker.walksPending::mean 0.847765 # Table walker pending requests distribution
554system.cpu0.itb.walker.walksPending::stdev 0.359386 # Table walker pending requests distribution
555system.cpu0.itb.walker.walksPending::0 3249113500 15.23% 15.23% # Table walker pending requests distribution
556system.cpu0.itb.walker.walksPending::1 18086389212 84.77% 100.00% # Table walker pending requests distribution
557system.cpu0.itb.walker.walksPending::2 793000 0.00% 100.00% # Table walker pending requests distribution
558system.cpu0.itb.walker.walksPending::3 86500 0.00% 100.00% # Table walker pending requests distribution
559system.cpu0.itb.walker.walksPending::total 21336382212 # Table walker pending requests distribution
560system.cpu0.itb.walker.walkPageSizes::4K 2247 87.19% 87.19% # Table walker page sizes translated
561system.cpu0.itb.walker.walkPageSizes::1M 330 12.81% 100.00% # Table walker page sizes translated
562system.cpu0.itb.walker.walkPageSizes::total 2577 # Table walker page sizes translated
563system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
564system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10841 # Table walker requests started/completed, data/inst
565system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10841 # Table walker requests started/completed, data/inst
566system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
567system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2577 # Table walker requests started/completed, data/inst
568system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2577 # Table walker requests started/completed, data/inst
569system.cpu0.itb.walker.walkRequestOrigin::total 13418 # Table walker requests started/completed, data/inst
570system.cpu0.itb.inst_hits 37363257 # ITB inst hits
571system.cpu0.itb.inst_misses 10841 # ITB inst misses
572system.cpu0.itb.read_hits 0 # DTB read hits
573system.cpu0.itb.read_misses 0 # DTB read misses
574system.cpu0.itb.write_hits 0 # DTB write hits
575system.cpu0.itb.write_misses 0 # DTB write misses
576system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
577system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
578system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
579system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
580system.cpu0.itb.flush_entries 2348 # Number of entries that have been flushed from TLB
581system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
582system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
583system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
584system.cpu0.itb.perms_faults 1915 # Number of TLB faults due to permissions restrictions
585system.cpu0.itb.read_accesses 0 # DTB read accesses
586system.cpu0.itb.write_accesses 0 # DTB write accesses
587system.cpu0.itb.inst_accesses 37374098 # ITB inst accesses
588system.cpu0.itb.hits 37363257 # DTB hits
589system.cpu0.itb.misses 10841 # DTB misses
590system.cpu0.itb.accesses 37374098 # DTB accesses
591system.cpu0.numCycles 130634754 # number of cpu cycles simulated
592system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
593system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
594system.cpu0.fetch.icacheStallCycles 18759180 # Number of cycles fetch is stalled on an Icache miss
595system.cpu0.fetch.Insts 111594210 # Number of instructions fetch has processed
596system.cpu0.fetch.Branches 23820996 # Number of branches that fetch encountered
597system.cpu0.fetch.predictedBranches 14548384 # Number of branches that fetch has predicted taken
598system.cpu0.fetch.Cycles 105958075 # Number of cycles fetch has run and was not squashing or blocked
599system.cpu0.fetch.SquashCycles 2723782 # Number of cycles fetch has spent squashing
600system.cpu0.fetch.TlbCycles 147803 # Number of cycles fetch has spent waiting for tlb
601system.cpu0.fetch.MiscStallCycles 57411 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
602system.cpu0.fetch.PendingTrapStallCycles 403538 # Number of stall cycles due to pending traps
603system.cpu0.fetch.PendingQuiesceStallCycles 420731 # Number of stall cycles due to pending quiesce instructions
604system.cpu0.fetch.IcacheWaitRetryStallCycles 91570 # Number of stall cycles due to full MSHR
605system.cpu0.fetch.CacheLines 37362977 # Number of cache lines fetched
606system.cpu0.fetch.IcacheSquashes 256682 # Number of outstanding Icache misses that were squashed
607system.cpu0.fetch.ItlbSquashes 5313 # Number of outstanding ITLB misses that were squashed
608system.cpu0.fetch.rateDist::samples 127200199 # Number of instructions fetched each cycle (Total)
609system.cpu0.fetch.rateDist::mean 1.057439 # Number of instructions fetched each cycle (Total)
610system.cpu0.fetch.rateDist::stdev 1.258294 # Number of instructions fetched each cycle (Total)
611system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
612system.cpu0.fetch.rateDist::0 65301995 51.34% 51.34% # Number of instructions fetched each cycle (Total)
613system.cpu0.fetch.rateDist::1 21243041 16.70% 68.04% # Number of instructions fetched each cycle (Total)
614system.cpu0.fetch.rateDist::2 8702131 6.84% 74.88% # Number of instructions fetched each cycle (Total)
615system.cpu0.fetch.rateDist::3 31953032 25.12% 100.00% # Number of instructions fetched each cycle (Total)
616system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
617system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
618system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
619system.cpu0.fetch.rateDist::total 127200199 # Number of instructions fetched each cycle (Total)
620system.cpu0.fetch.branchRate 0.182348 # Number of branch fetches per cycle
621system.cpu0.fetch.rate 0.854246 # Number of inst fetches per cycle
622system.cpu0.decode.IdleCycles 19580299 # Number of cycles decode is idle
623system.cpu0.decode.BlockedCycles 60730761 # Number of cycles decode is blocked
624system.cpu0.decode.RunCycles 40895062 # Number of cycles decode is running
625system.cpu0.decode.UnblockCycles 4960019 # Number of cycles decode is unblocking
626system.cpu0.decode.SquashCycles 1034058 # Number of cycles decode is squashing
627system.cpu0.decode.BranchResolved 3027631 # Number of times decode resolved a branch
628system.cpu0.decode.BranchMispred 331959 # Number of times decode detected a branch misprediction
629system.cpu0.decode.DecodedInsts 109730420 # Number of instructions handled by decode
630system.cpu0.decode.SquashedInsts 3757258 # Number of squashed instructions handled by decode
631system.cpu0.rename.SquashCycles 1034058 # Number of cycles rename is squashing
632system.cpu0.rename.IdleCycles 25213970 # Number of cycles rename is idle
633system.cpu0.rename.BlockCycles 12473804 # Number of cycles rename is blocking
634system.cpu0.rename.serializeStallCycles 37385885 # count of cycles rename stalled for serializing inst
635system.cpu0.rename.RunCycles 40084231 # Number of cycles rename is running
636system.cpu0.rename.UnblockCycles 11008251 # Number of cycles rename is unblocking
637system.cpu0.rename.RenamedInsts 104776923 # Number of instructions processed by rename
638system.cpu0.rename.SquashedInsts 1005898 # Number of squashed instructions processed by rename
639system.cpu0.rename.ROBFullEvents 1454281 # Number of times rename has blocked due to ROB full
640system.cpu0.rename.IQFullEvents 163264 # Number of times rename has blocked due to IQ full
641system.cpu0.rename.LQFullEvents 59868 # Number of times rename has blocked due to LQ full
642system.cpu0.rename.SQFullEvents 6802738 # Number of times rename has blocked due to SQ full
643system.cpu0.rename.RenamedOperands 108917617 # Number of destination operands rename has renamed
644system.cpu0.rename.RenameLookups 478329249 # Number of register rename lookups that rename has made
645system.cpu0.rename.int_rename_lookups 119800886 # Number of integer rename lookups
646system.cpu0.rename.fp_rename_lookups 9453 # Number of floating rename lookups
647system.cpu0.rename.CommittedMaps 97884799 # Number of HB maps that are committed
648system.cpu0.rename.UndoneMaps 11032807 # Number of HB maps that are undone due to squashing
649system.cpu0.rename.serializingInsts 1224750 # count of serializing insts renamed
650system.cpu0.rename.tempSerializingInsts 1083467 # count of temporary serializing insts renamed
651system.cpu0.rename.skidInsts 12359769 # count of insts added to the skid buffer
652system.cpu0.memDep0.insertedLoads 18590109 # Number of loads inserted to the mem dependence unit.
653system.cpu0.memDep0.insertedStores 16025944 # Number of stores inserted to the mem dependence unit.
654system.cpu0.memDep0.conflictingLoads 1692928 # Number of conflicting loads.
655system.cpu0.memDep0.conflictingStores 2223672 # Number of conflicting stores.
656system.cpu0.iq.iqInstsAdded 101900058 # Number of instructions added to the IQ (excludes non-spec)
657system.cpu0.iq.iqNonSpecInstsAdded 1687234 # Number of non-speculative instructions added to the IQ
658system.cpu0.iq.iqInstsIssued 100089682 # Number of instructions issued
659system.cpu0.iq.iqSquashedInstsIssued 451563 # Number of squashed instructions issued
660system.cpu0.iq.iqSquashedInstsExamined 8991464 # Number of squashed instructions iterated over during squash; mainly for profiling
661system.cpu0.iq.iqSquashedOperandsExamined 21250511 # Number of squashed operands that are examined and possibly removed from graph
662system.cpu0.iq.iqSquashedNonSpecRemoved 118873 # Number of squashed non-spec instructions that were removed
663system.cpu0.iq.issued_per_cycle::samples 127200199 # Number of insts issued each cycle
664system.cpu0.iq.issued_per_cycle::mean 0.786867 # Number of insts issued each cycle
665system.cpu0.iq.issued_per_cycle::stdev 1.029325 # Number of insts issued each cycle
666system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
667system.cpu0.iq.issued_per_cycle::0 71273767 56.03% 56.03% # Number of insts issued each cycle
668system.cpu0.iq.issued_per_cycle::1 23216726 18.25% 74.28% # Number of insts issued each cycle
669system.cpu0.iq.issued_per_cycle::2 22358125 17.58% 91.86% # Number of insts issued each cycle
670system.cpu0.iq.issued_per_cycle::3 9249672 7.27% 99.13% # Number of insts issued each cycle
671system.cpu0.iq.issued_per_cycle::4 1101855 0.87% 100.00% # Number of insts issued each cycle
672system.cpu0.iq.issued_per_cycle::5 54 0.00% 100.00% # Number of insts issued each cycle
673system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
674system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
675system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
676system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
677system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
678system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
679system.cpu0.iq.issued_per_cycle::total 127200199 # Number of insts issued each cycle
680system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
681system.cpu0.iq.fu_full::IntAlu 9294441 40.55% 40.55% # attempts to use FU when none available
682system.cpu0.iq.fu_full::IntMult 68 0.00% 40.55% # attempts to use FU when none available
683system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.55% # attempts to use FU when none available
684system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.55% # attempts to use FU when none available
685system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.55% # attempts to use FU when none available
686system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.55% # attempts to use FU when none available
687system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.55% # attempts to use FU when none available
688system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.55% # attempts to use FU when none available
689system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.55% # attempts to use FU when none available
690system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.55% # attempts to use FU when none available
691system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.55% # attempts to use FU when none available
692system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.55% # attempts to use FU when none available
693system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.55% # attempts to use FU when none available
694system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.55% # attempts to use FU when none available
695system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.55% # attempts to use FU when none available
696system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.55% # attempts to use FU when none available
697system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.55% # attempts to use FU when none available
698system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.55% # attempts to use FU when none available
699system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.55% # attempts to use FU when none available
700system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.55% # attempts to use FU when none available
701system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.55% # attempts to use FU when none available
702system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.55% # attempts to use FU when none available
703system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.55% # attempts to use FU when none available
704system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.55% # attempts to use FU when none available
705system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.55% # attempts to use FU when none available
706system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.55% # attempts to use FU when none available
707system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.55% # attempts to use FU when none available
708system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.55% # attempts to use FU when none available
709system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.55% # attempts to use FU when none available
710system.cpu0.iq.fu_full::MemRead 5565368 24.28% 64.83% # attempts to use FU when none available
711system.cpu0.iq.fu_full::MemWrite 8061478 35.17% 100.00% # attempts to use FU when none available
712system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
713system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
714system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued
715system.cpu0.iq.FU_type_0::IntAlu 66026932 65.97% 65.97% # Type of FU issued
716system.cpu0.iq.FU_type_0::IntMult 92216 0.09% 66.06% # Type of FU issued
717system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.06% # Type of FU issued
718system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.06% # Type of FU issued
719system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued
720system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued
721system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued
722system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued
723system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued
724system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued
725system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.06% # Type of FU issued
726system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.06% # Type of FU issued
727system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.06% # Type of FU issued
728system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.06% # Type of FU issued
729system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.06% # Type of FU issued
730system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.06% # Type of FU issued
731system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.06% # Type of FU issued
732system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued
733system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued
734system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued
735system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued
736system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued
737system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued
738system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued
739system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.06% # Type of FU issued
740system.cpu0.iq.FU_type_0::SimdFloatMisc 8071 0.01% 66.07% # Type of FU issued
741system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.07% # Type of FU issued
742system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.07% # Type of FU issued
743system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.07% # Type of FU issued
744system.cpu0.iq.FU_type_0::MemRead 18353253 18.34% 84.41% # Type of FU issued
745system.cpu0.iq.FU_type_0::MemWrite 15606936 15.59% 100.00% # Type of FU issued
746system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
747system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
748system.cpu0.iq.FU_type_0::total 100089682 # Type of FU issued
749system.cpu0.iq.rate 0.766180 # Inst issue rate
750system.cpu0.iq.fu_busy_cnt 22921355 # FU busy when requested
751system.cpu0.iq.fu_busy_rate 0.229008 # FU busy rate (busy events/executed inst)
752system.cpu0.iq.int_inst_queue_reads 350720067 # Number of integer instruction queue reads
753system.cpu0.iq.int_inst_queue_writes 112586232 # Number of integer instruction queue writes
754system.cpu0.iq.int_inst_queue_wakeup_accesses 98062666 # Number of integer instruction queue wakeup accesses
755system.cpu0.iq.fp_inst_queue_reads 32413 # Number of floating instruction queue reads
756system.cpu0.iq.fp_inst_queue_writes 11362 # Number of floating instruction queue writes
757system.cpu0.iq.fp_inst_queue_wakeup_accesses 9718 # Number of floating instruction queue wakeup accesses
758system.cpu0.iq.int_alu_accesses 122987773 # Number of integer alu accesses
759system.cpu0.iq.fp_alu_accesses 20991 # Number of floating point alu accesses
760system.cpu0.iew.lsq.thread0.forwLoads 362703 # Number of loads that had data forwarded from stores
761system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
762system.cpu0.iew.lsq.thread0.squashedLoads 1887830 # Number of loads squashed
763system.cpu0.iew.lsq.thread0.ignoredResponses 2440 # Number of memory responses ignored because the instruction is squashed
764system.cpu0.iew.lsq.thread0.memOrderViolation 18911 # Number of memory ordering violations
765system.cpu0.iew.lsq.thread0.squashedStores 876012 # Number of stores squashed
766system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
767system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
768system.cpu0.iew.lsq.thread0.rescheduledLoads 109448 # Number of loads that were rescheduled
769system.cpu0.iew.lsq.thread0.cacheBlocked 364606 # Number of times an access to memory failed due to the cache being blocked
770system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
771system.cpu0.iew.iewSquashCycles 1034058 # Number of cycles IEW is squashing
772system.cpu0.iew.iewBlockCycles 1622257 # Number of cycles IEW is blocking
773system.cpu0.iew.iewUnblockCycles 187065 # Number of cycles IEW is unblocking
774system.cpu0.iew.iewDispatchedInsts 103740401 # Number of instructions dispatched to IQ
775system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
776system.cpu0.iew.iewDispLoadInsts 18590109 # Number of dispatched load instructions
777system.cpu0.iew.iewDispStoreInsts 16025944 # Number of dispatched store instructions
778system.cpu0.iew.iewDispNonSpecInsts 873149 # Number of dispatched non-speculative instructions
779system.cpu0.iew.iewIQFullEvents 28190 # Number of times the IQ has become full, causing a stall
780system.cpu0.iew.iewLSQFullEvents 135133 # Number of times the LSQ has become full, causing a stall
781system.cpu0.iew.memOrderViolationEvents 18911 # Number of memory order violations
782system.cpu0.iew.predictedTakenIncorrect 251727 # Number of branches that were predicted taken incorrectly
783system.cpu0.iew.predictedNotTakenIncorrect 397563 # Number of branches that were predicted not taken incorrectly
784system.cpu0.iew.branchMispredicts 649290 # Number of branch mispredicts detected at execute
785system.cpu0.iew.iewExecutedInsts 99070135 # Number of executed instructions
786system.cpu0.iew.iewExecLoadInsts 17913102 # Number of load instructions executed
787system.cpu0.iew.iewExecSquashedInsts 953014 # Number of squashed instructions skipped in execute
788system.cpu0.iew.exec_swp 0 # number of swp insts executed
789system.cpu0.iew.exec_nop 153109 # number of nop insts executed
790system.cpu0.iew.exec_refs 33359413 # number of memory reference insts executed
791system.cpu0.iew.exec_branches 16770669 # Number of branches executed
792system.cpu0.iew.exec_stores 15446311 # Number of stores executed
793system.cpu0.iew.exec_rate 0.758375 # Inst execution rate
794system.cpu0.iew.wb_sent 98522156 # cumulative count of insts sent to commit
795system.cpu0.iew.wb_count 98072384 # cumulative count of insts written-back
796system.cpu0.iew.wb_producers 51087973 # num instructions producing a value
797system.cpu0.iew.wb_consumers 84406715 # num instructions consuming a value
798system.cpu0.iew.wb_rate 0.750737 # insts written-back per cycle
799system.cpu0.iew.wb_fanout 0.605260 # average fanout of values written-back
800system.cpu0.commit.commitSquashedInsts 7992419 # The number of squashed insts skipped by commit
801system.cpu0.commit.commitNonSpecStalls 1568361 # The number of times commit has been forced to stall to communicate backwards
802system.cpu0.commit.branchMispredicts 592562 # The number of times a branch was mispredicted
803system.cpu0.commit.committed_per_cycle::samples 125525573 # Number of insts commited each cycle
804system.cpu0.commit.committed_per_cycle::mean 0.754570 # Number of insts commited each cycle
805system.cpu0.commit.committed_per_cycle::stdev 1.472389 # Number of insts commited each cycle
806system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
807system.cpu0.commit.committed_per_cycle::0 81342054 64.80% 64.80% # Number of insts commited each cycle
808system.cpu0.commit.committed_per_cycle::1 24610935 19.61% 84.41% # Number of insts commited each cycle
809system.cpu0.commit.committed_per_cycle::2 8228457 6.56% 90.96% # Number of insts commited each cycle
810system.cpu0.commit.committed_per_cycle::3 3212332 2.56% 93.52% # Number of insts commited each cycle
811system.cpu0.commit.committed_per_cycle::4 3423017 2.73% 96.25% # Number of insts commited each cycle
812system.cpu0.commit.committed_per_cycle::5 1492381 1.19% 97.44% # Number of insts commited each cycle
813system.cpu0.commit.committed_per_cycle::6 1160319 0.92% 98.36% # Number of insts commited each cycle
814system.cpu0.commit.committed_per_cycle::7 551485 0.44% 98.80% # Number of insts commited each cycle
815system.cpu0.commit.committed_per_cycle::8 1504593 1.20% 100.00% # Number of insts commited each cycle
816system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
817system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
818system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
819system.cpu0.commit.committed_per_cycle::total 125525573 # Number of insts commited each cycle
820system.cpu0.commit.committedInsts 78721743 # Number of instructions committed
821system.cpu0.commit.committedOps 94717871 # Number of ops (including micro ops) committed
822system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
823system.cpu0.commit.refs 31852210 # Number of memory references committed
824system.cpu0.commit.loads 16702278 # Number of loads committed
825system.cpu0.commit.membars 645830 # Number of memory barriers committed
826system.cpu0.commit.branches 16170329 # Number of branches committed
827system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions.
828system.cpu0.commit.int_insts 81695650 # Number of committed integer instructions.
829system.cpu0.commit.function_calls 1925626 # Number of function calls committed.
830system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
831system.cpu0.commit.op_class_0::IntAlu 62767692 66.27% 66.27% # Class of committed instruction
832system.cpu0.commit.op_class_0::IntMult 89898 0.09% 66.36% # Class of committed instruction
833system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.36% # Class of committed instruction
834system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.36% # Class of committed instruction
835system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.36% # Class of committed instruction
836system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.36% # Class of committed instruction
837system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.36% # Class of committed instruction
838system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.36% # Class of committed instruction
839system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.36% # Class of committed instruction
840system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.36% # Class of committed instruction
841system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.36% # Class of committed instruction
842system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.36% # Class of committed instruction
843system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.36% # Class of committed instruction
844system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.36% # Class of committed instruction
845system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.36% # Class of committed instruction
846system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.36% # Class of committed instruction
847system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.36% # Class of committed instruction
848system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.36% # Class of committed instruction
849system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.36% # Class of committed instruction
850system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.36% # Class of committed instruction
851system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.36% # Class of committed instruction
852system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.36% # Class of committed instruction
853system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.36% # Class of committed instruction
854system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.36% # Class of committed instruction
855system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.36% # Class of committed instruction
856system.cpu0.commit.op_class_0::SimdFloatMisc 8071 0.01% 66.37% # Class of committed instruction
857system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.37% # Class of committed instruction
858system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.37% # Class of committed instruction
859system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.37% # Class of committed instruction
860system.cpu0.commit.op_class_0::MemRead 16702278 17.63% 84.01% # Class of committed instruction
861system.cpu0.commit.op_class_0::MemWrite 15149932 15.99% 100.00% # Class of committed instruction
862system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
863system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
864system.cpu0.commit.op_class_0::total 94717871 # Class of committed instruction
865system.cpu0.commit.bw_lim_events 1504593 # number cycles where commit BW limit reached
866system.cpu0.rob.rob_reads 222549197 # The number of ROB reads
867system.cpu0.rob.rob_writes 207085893 # The number of ROB writes
868system.cpu0.timesIdled 123342 # Number of times that the entire CPU went into an idle state and unscheduled itself
869system.cpu0.idleCycles 3434555 # Total number of cycles that the CPU has spent unscheduled due to idling
870system.cpu0.quiesceCycles 5521267593 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
871system.cpu0.committedInsts 78599691 # Number of Instructions Simulated
872system.cpu0.committedOps 94595819 # Number of Ops (including micro ops) Simulated
873system.cpu0.cpi 1.662026 # CPI: Cycles Per Instruction
874system.cpu0.cpi_total 1.662026 # CPI: Total CPI of All Threads
875system.cpu0.ipc 0.601675 # IPC: Instructions Per Cycle
876system.cpu0.ipc_total 0.601675 # IPC: Total IPC of All Threads
877system.cpu0.int_regfile_reads 110021691 # number of integer regfile reads
878system.cpu0.int_regfile_writes 59386115 # number of integer regfile writes
879system.cpu0.fp_regfile_reads 8176 # number of floating regfile reads
880system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes
881system.cpu0.cc_regfile_reads 349047979 # number of cc regfile reads
882system.cpu0.cc_regfile_writes 40883845 # number of cc regfile writes
883system.cpu0.misc_regfile_reads 177564457 # number of misc regfile reads
884system.cpu0.misc_regfile_writes 1222085 # number of misc regfile writes
885system.cpu0.dcache.tags.replacements 709600 # number of replacements
886system.cpu0.dcache.tags.tagsinuse 499.965510 # Cycle average of tags in use
887system.cpu0.dcache.tags.total_refs 28702051 # Total number of references to valid blocks.
888system.cpu0.dcache.tags.sampled_refs 710112 # Sample count of references to valid blocks.
889system.cpu0.dcache.tags.avg_refs 40.419048 # Average number of references to valid blocks.
890system.cpu0.dcache.tags.warmup_cycle 278078500 # Cycle when the warmup percentage was hit.
891system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.965510 # Average occupied blocks per requestor
892system.cpu0.dcache.tags.occ_percent::cpu0.data 0.976495 # Average percentage of cache occupancy
893system.cpu0.dcache.tags.occ_percent::total 0.976495 # Average percentage of cache occupancy
894system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
895system.cpu0.dcache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id
896system.cpu0.dcache.tags.age_task_id_blocks_1024::1 334 # Occupied blocks per task id
897system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
898system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
899system.cpu0.dcache.tags.tag_accesses 63247390 # Number of tag accesses
900system.cpu0.dcache.tags.data_accesses 63247390 # Number of data accesses
901system.cpu0.dcache.ReadReq_hits::cpu0.data 15498209 # number of ReadReq hits
902system.cpu0.dcache.ReadReq_hits::total 15498209 # number of ReadReq hits
903system.cpu0.dcache.WriteReq_hits::cpu0.data 11982969 # number of WriteReq hits
904system.cpu0.dcache.WriteReq_hits::total 11982969 # number of WriteReq hits
905system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307264 # number of SoftPFReq hits
906system.cpu0.dcache.SoftPFReq_hits::total 307264 # number of SoftPFReq hits
907system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 362251 # number of LoadLockedReq hits
908system.cpu0.dcache.LoadLockedReq_hits::total 362251 # number of LoadLockedReq hits
909system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360359 # number of StoreCondReq hits
910system.cpu0.dcache.StoreCondReq_hits::total 360359 # number of StoreCondReq hits
911system.cpu0.dcache.demand_hits::cpu0.data 27481178 # number of demand (read+write) hits
912system.cpu0.dcache.demand_hits::total 27481178 # number of demand (read+write) hits
913system.cpu0.dcache.overall_hits::cpu0.data 27788442 # number of overall hits
914system.cpu0.dcache.overall_hits::total 27788442 # number of overall hits
915system.cpu0.dcache.ReadReq_misses::cpu0.data 646938 # number of ReadReq misses
916system.cpu0.dcache.ReadReq_misses::total 646938 # number of ReadReq misses
917system.cpu0.dcache.WriteReq_misses::cpu0.data 1889976 # number of WriteReq misses
918system.cpu0.dcache.WriteReq_misses::total 1889976 # number of WriteReq misses
919system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147980 # number of SoftPFReq misses
920system.cpu0.dcache.SoftPFReq_misses::total 147980 # number of SoftPFReq misses
921system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25182 # number of LoadLockedReq misses
922system.cpu0.dcache.LoadLockedReq_misses::total 25182 # number of LoadLockedReq misses
923system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20295 # number of StoreCondReq misses
924system.cpu0.dcache.StoreCondReq_misses::total 20295 # number of StoreCondReq misses
925system.cpu0.dcache.demand_misses::cpu0.data 2536914 # number of demand (read+write) misses
926system.cpu0.dcache.demand_misses::total 2536914 # number of demand (read+write) misses
927system.cpu0.dcache.overall_misses::cpu0.data 2684894 # number of overall misses
928system.cpu0.dcache.overall_misses::total 2684894 # number of overall misses
929system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8613079000 # number of ReadReq miss cycles
930system.cpu0.dcache.ReadReq_miss_latency::total 8613079000 # number of ReadReq miss cycles
931system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29673912872 # number of WriteReq miss cycles
932system.cpu0.dcache.WriteReq_miss_latency::total 29673912872 # number of WriteReq miss cycles
933system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 399362500 # number of LoadLockedReq miss cycles
934system.cpu0.dcache.LoadLockedReq_miss_latency::total 399362500 # number of LoadLockedReq miss cycles
935system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 493278500 # number of StoreCondReq miss cycles
936system.cpu0.dcache.StoreCondReq_miss_latency::total 493278500 # number of StoreCondReq miss cycles
937system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 493500 # number of StoreCondFailReq miss cycles
938system.cpu0.dcache.StoreCondFailReq_miss_latency::total 493500 # number of StoreCondFailReq miss cycles
939system.cpu0.dcache.demand_miss_latency::cpu0.data 38286991872 # number of demand (read+write) miss cycles
940system.cpu0.dcache.demand_miss_latency::total 38286991872 # number of demand (read+write) miss cycles
941system.cpu0.dcache.overall_miss_latency::cpu0.data 38286991872 # number of overall miss cycles
942system.cpu0.dcache.overall_miss_latency::total 38286991872 # number of overall miss cycles
943system.cpu0.dcache.ReadReq_accesses::cpu0.data 16145147 # number of ReadReq accesses(hits+misses)
944system.cpu0.dcache.ReadReq_accesses::total 16145147 # number of ReadReq accesses(hits+misses)
945system.cpu0.dcache.WriteReq_accesses::cpu0.data 13872945 # number of WriteReq accesses(hits+misses)
946system.cpu0.dcache.WriteReq_accesses::total 13872945 # number of WriteReq accesses(hits+misses)
947system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 455244 # number of SoftPFReq accesses(hits+misses)
948system.cpu0.dcache.SoftPFReq_accesses::total 455244 # number of SoftPFReq accesses(hits+misses)
949system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387433 # number of LoadLockedReq accesses(hits+misses)
950system.cpu0.dcache.LoadLockedReq_accesses::total 387433 # number of LoadLockedReq accesses(hits+misses)
951system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 380654 # number of StoreCondReq accesses(hits+misses)
952system.cpu0.dcache.StoreCondReq_accesses::total 380654 # number of StoreCondReq accesses(hits+misses)
953system.cpu0.dcache.demand_accesses::cpu0.data 30018092 # number of demand (read+write) accesses
954system.cpu0.dcache.demand_accesses::total 30018092 # number of demand (read+write) accesses
955system.cpu0.dcache.overall_accesses::cpu0.data 30473336 # number of overall (read+write) accesses
956system.cpu0.dcache.overall_accesses::total 30473336 # number of overall (read+write) accesses
957system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040070 # miss rate for ReadReq accesses
958system.cpu0.dcache.ReadReq_miss_rate::total 0.040070 # miss rate for ReadReq accesses
959system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136235 # miss rate for WriteReq accesses
960system.cpu0.dcache.WriteReq_miss_rate::total 0.136235 # miss rate for WriteReq accesses
961system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325056 # miss rate for SoftPFReq accesses
962system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325056 # miss rate for SoftPFReq accesses
963system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064997 # miss rate for LoadLockedReq accesses
964system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064997 # miss rate for LoadLockedReq accesses
965system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053316 # miss rate for StoreCondReq accesses
966system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053316 # miss rate for StoreCondReq accesses
967system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084513 # miss rate for demand accesses
968system.cpu0.dcache.demand_miss_rate::total 0.084513 # miss rate for demand accesses
969system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088106 # miss rate for overall accesses
970system.cpu0.dcache.overall_miss_rate::total 0.088106 # miss rate for overall accesses
971system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13313.608105 # average ReadReq miss latency
972system.cpu0.dcache.ReadReq_avg_miss_latency::total 13313.608105 # average ReadReq miss latency
973system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15700.682375 # average WriteReq miss latency
974system.cpu0.dcache.WriteReq_avg_miss_latency::total 15700.682375 # average WriteReq miss latency
975system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15859.046144 # average LoadLockedReq miss latency
976system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15859.046144 # average LoadLockedReq miss latency
977system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24305.420054 # average StoreCondReq miss latency
978system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24305.420054 # average StoreCondReq miss latency
979system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
980system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
981system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15091.954978 # average overall miss latency
982system.cpu0.dcache.demand_avg_miss_latency::total 15091.954978 # average overall miss latency
983system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14260.150260 # average overall miss latency
984system.cpu0.dcache.overall_avg_miss_latency::total 14260.150260 # average overall miss latency
985system.cpu0.dcache.blocked_cycles::no_mshrs 1062 # number of cycles access was blocked
986system.cpu0.dcache.blocked_cycles::no_targets 4223116 # number of cycles access was blocked
987system.cpu0.dcache.blocked::no_mshrs 45 # number of cycles access was blocked
988system.cpu0.dcache.blocked::no_targets 202030 # number of cycles access was blocked
989system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.600000 # average number of cycles each access was blocked
990system.cpu0.dcache.avg_blocked_cycles::no_targets 20.903410 # average number of cycles each access was blocked
991system.cpu0.dcache.writebacks::writebacks 709603 # number of writebacks
992system.cpu0.dcache.writebacks::total 709603 # number of writebacks
993system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 260771 # number of ReadReq MSHR hits
994system.cpu0.dcache.ReadReq_mshr_hits::total 260771 # number of ReadReq MSHR hits
995system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1564893 # number of WriteReq MSHR hits
996system.cpu0.dcache.WriteReq_mshr_hits::total 1564893 # number of WriteReq MSHR hits
997system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18568 # number of LoadLockedReq MSHR hits
998system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18568 # number of LoadLockedReq MSHR hits
999system.cpu0.dcache.demand_mshr_hits::cpu0.data 1825664 # number of demand (read+write) MSHR hits
1000system.cpu0.dcache.demand_mshr_hits::total 1825664 # number of demand (read+write) MSHR hits
1001system.cpu0.dcache.overall_mshr_hits::cpu0.data 1825664 # number of overall MSHR hits
1002system.cpu0.dcache.overall_mshr_hits::total 1825664 # number of overall MSHR hits
1003system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 386167 # number of ReadReq MSHR misses
1004system.cpu0.dcache.ReadReq_mshr_misses::total 386167 # number of ReadReq MSHR misses
1005system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325083 # number of WriteReq MSHR misses
1006system.cpu0.dcache.WriteReq_mshr_misses::total 325083 # number of WriteReq MSHR misses
1007system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102058 # number of SoftPFReq MSHR misses
1008system.cpu0.dcache.SoftPFReq_mshr_misses::total 102058 # number of SoftPFReq MSHR misses
1009system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6614 # number of LoadLockedReq MSHR misses
1010system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6614 # number of LoadLockedReq MSHR misses
1011system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20295 # number of StoreCondReq MSHR misses
1012system.cpu0.dcache.StoreCondReq_mshr_misses::total 20295 # number of StoreCondReq MSHR misses
1013system.cpu0.dcache.demand_mshr_misses::cpu0.data 711250 # number of demand (read+write) MSHR misses
1014system.cpu0.dcache.demand_mshr_misses::total 711250 # number of demand (read+write) MSHR misses
1015system.cpu0.dcache.overall_mshr_misses::cpu0.data 813308 # number of overall MSHR misses
1016system.cpu0.dcache.overall_mshr_misses::total 813308 # number of overall MSHR misses
1017system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20340 # number of ReadReq MSHR uncacheable
1018system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20340 # number of ReadReq MSHR uncacheable
1019system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19033 # number of WriteReq MSHR uncacheable
1020system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19033 # number of WriteReq MSHR uncacheable
1021system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39373 # number of overall MSHR uncacheable misses
1022system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39373 # number of overall MSHR uncacheable misses
1023system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4553087000 # number of ReadReq MSHR miss cycles
1024system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4553087000 # number of ReadReq MSHR miss cycles
1025system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6070046902 # number of WriteReq MSHR miss cycles
1026system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6070046902 # number of WriteReq MSHR miss cycles
1027system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1659761500 # number of SoftPFReq MSHR miss cycles
1028system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1659761500 # number of SoftPFReq MSHR miss cycles
1029system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 103454000 # number of LoadLockedReq MSHR miss cycles
1030system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103454000 # number of LoadLockedReq MSHR miss cycles
1031system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 472996500 # number of StoreCondReq MSHR miss cycles
1032system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 472996500 # number of StoreCondReq MSHR miss cycles
1033system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 480500 # number of StoreCondFailReq MSHR miss cycles
1034system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 480500 # number of StoreCondFailReq MSHR miss cycles
1035system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10623133902 # number of demand (read+write) MSHR miss cycles
1036system.cpu0.dcache.demand_mshr_miss_latency::total 10623133902 # number of demand (read+write) MSHR miss cycles
1037system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12282895402 # number of overall MSHR miss cycles
1038system.cpu0.dcache.overall_mshr_miss_latency::total 12282895402 # number of overall MSHR miss cycles
1039system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4534665000 # number of ReadReq MSHR uncacheable cycles
1040system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4534665000 # number of ReadReq MSHR uncacheable cycles
1041system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4534665000 # number of overall MSHR uncacheable cycles
1042system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4534665000 # number of overall MSHR uncacheable cycles
1043system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023918 # mshr miss rate for ReadReq accesses
1044system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023918 # mshr miss rate for ReadReq accesses
1045system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023433 # mshr miss rate for WriteReq accesses
1046system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023433 # mshr miss rate for WriteReq accesses
1047system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224183 # mshr miss rate for SoftPFReq accesses
1048system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224183 # mshr miss rate for SoftPFReq accesses
1049system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017071 # mshr miss rate for LoadLockedReq accesses
1050system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017071 # mshr miss rate for LoadLockedReq accesses
1051system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053316 # mshr miss rate for StoreCondReq accesses
1052system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053316 # mshr miss rate for StoreCondReq accesses
1053system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023694 # mshr miss rate for demand accesses
1054system.cpu0.dcache.demand_mshr_miss_rate::total 0.023694 # mshr miss rate for demand accesses
1055system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026689 # mshr miss rate for overall accesses
1056system.cpu0.dcache.overall_mshr_miss_rate::total 0.026689 # mshr miss rate for overall accesses
1057system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11790.461122 # average ReadReq mshr miss latency
1058system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11790.461122 # average ReadReq mshr miss latency
1059system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18672.298773 # average WriteReq mshr miss latency
1060system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18672.298773 # average WriteReq mshr miss latency
1061system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16262.924024 # average SoftPFReq mshr miss latency
1062system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16262.924024 # average SoftPFReq mshr miss latency
1063system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15641.669187 # average LoadLockedReq mshr miss latency
1064system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15641.669187 # average LoadLockedReq mshr miss latency
1065system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23306.060606 # average StoreCondReq mshr miss latency
1066system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23306.060606 # average StoreCondReq mshr miss latency
1067system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
1068system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1069system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14935.864889 # average overall mshr miss latency
1070system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14935.864889 # average overall mshr miss latency
1071system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15102.390979 # average overall mshr miss latency
1072system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15102.390979 # average overall mshr miss latency
1073system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222943.215339 # average ReadReq mshr uncacheable latency
1074system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222943.215339 # average ReadReq mshr uncacheable latency
1075system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115171.945242 # average overall mshr uncacheable latency
1076system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115171.945242 # average overall mshr uncacheable latency
1077system.cpu0.icache.tags.replacements 1244973 # number of replacements
1078system.cpu0.icache.tags.tagsinuse 511.762786 # Cycle average of tags in use
1079system.cpu0.icache.tags.total_refs 36061117 # Total number of references to valid blocks.
1080system.cpu0.icache.tags.sampled_refs 1245485 # Sample count of references to valid blocks.
1081system.cpu0.icache.tags.avg_refs 28.953474 # Average number of references to valid blocks.
1082system.cpu0.icache.tags.warmup_cycle 6512698000 # Cycle when the warmup percentage was hit.
1083system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762786 # Average occupied blocks per requestor
1084system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999537 # Average percentage of cache occupancy
1085system.cpu0.icache.tags.occ_percent::total 0.999537 # Average percentage of cache occupancy
1086system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1087system.cpu0.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id
1088system.cpu0.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id
1089system.cpu0.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id
1090system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1091system.cpu0.icache.tags.tag_accesses 75964361 # Number of tag accesses
1092system.cpu0.icache.tags.data_accesses 75964361 # Number of data accesses
1093system.cpu0.icache.ReadReq_hits::cpu0.inst 36061117 # number of ReadReq hits
1094system.cpu0.icache.ReadReq_hits::total 36061117 # number of ReadReq hits
1095system.cpu0.icache.demand_hits::cpu0.inst 36061117 # number of demand (read+write) hits
1096system.cpu0.icache.demand_hits::total 36061117 # number of demand (read+write) hits
1097system.cpu0.icache.overall_hits::cpu0.inst 36061117 # number of overall hits
1098system.cpu0.icache.overall_hits::total 36061117 # number of overall hits
1099system.cpu0.icache.ReadReq_misses::cpu0.inst 1298298 # number of ReadReq misses
1100system.cpu0.icache.ReadReq_misses::total 1298298 # number of ReadReq misses
1101system.cpu0.icache.demand_misses::cpu0.inst 1298298 # number of demand (read+write) misses
1102system.cpu0.icache.demand_misses::total 1298298 # number of demand (read+write) misses
1103system.cpu0.icache.overall_misses::cpu0.inst 1298298 # number of overall misses
1104system.cpu0.icache.overall_misses::total 1298298 # number of overall misses
1105system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13095750432 # number of ReadReq miss cycles
1106system.cpu0.icache.ReadReq_miss_latency::total 13095750432 # number of ReadReq miss cycles
1107system.cpu0.icache.demand_miss_latency::cpu0.inst 13095750432 # number of demand (read+write) miss cycles
1108system.cpu0.icache.demand_miss_latency::total 13095750432 # number of demand (read+write) miss cycles
1109system.cpu0.icache.overall_miss_latency::cpu0.inst 13095750432 # number of overall miss cycles
1110system.cpu0.icache.overall_miss_latency::total 13095750432 # number of overall miss cycles
1111system.cpu0.icache.ReadReq_accesses::cpu0.inst 37359415 # number of ReadReq accesses(hits+misses)
1112system.cpu0.icache.ReadReq_accesses::total 37359415 # number of ReadReq accesses(hits+misses)
1113system.cpu0.icache.demand_accesses::cpu0.inst 37359415 # number of demand (read+write) accesses
1114system.cpu0.icache.demand_accesses::total 37359415 # number of demand (read+write) accesses
1115system.cpu0.icache.overall_accesses::cpu0.inst 37359415 # number of overall (read+write) accesses
1116system.cpu0.icache.overall_accesses::total 37359415 # number of overall (read+write) accesses
1117system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034752 # miss rate for ReadReq accesses
1118system.cpu0.icache.ReadReq_miss_rate::total 0.034752 # miss rate for ReadReq accesses
1119system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034752 # miss rate for demand accesses
1120system.cpu0.icache.demand_miss_rate::total 0.034752 # miss rate for demand accesses
1121system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034752 # miss rate for overall accesses
1122system.cpu0.icache.overall_miss_rate::total 0.034752 # miss rate for overall accesses
1123system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10086.860206 # average ReadReq miss latency
1124system.cpu0.icache.ReadReq_avg_miss_latency::total 10086.860206 # average ReadReq miss latency
1125system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10086.860206 # average overall miss latency
1126system.cpu0.icache.demand_avg_miss_latency::total 10086.860206 # average overall miss latency
1127system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10086.860206 # average overall miss latency
1128system.cpu0.icache.overall_avg_miss_latency::total 10086.860206 # average overall miss latency
1129system.cpu0.icache.blocked_cycles::no_mshrs 1564537 # number of cycles access was blocked
1130system.cpu0.icache.blocked_cycles::no_targets 822 # number of cycles access was blocked
1131system.cpu0.icache.blocked::no_mshrs 111550 # number of cycles access was blocked
1132system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked
1133system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.025433 # average number of cycles each access was blocked
1134system.cpu0.icache.avg_blocked_cycles::no_targets 74.727273 # average number of cycles each access was blocked
1135system.cpu0.icache.writebacks::writebacks 1244973 # number of writebacks
1136system.cpu0.icache.writebacks::total 1244973 # number of writebacks
1137system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 52766 # number of ReadReq MSHR hits
1138system.cpu0.icache.ReadReq_mshr_hits::total 52766 # number of ReadReq MSHR hits
1139system.cpu0.icache.demand_mshr_hits::cpu0.inst 52766 # number of demand (read+write) MSHR hits
1140system.cpu0.icache.demand_mshr_hits::total 52766 # number of demand (read+write) MSHR hits
1141system.cpu0.icache.overall_mshr_hits::cpu0.inst 52766 # number of overall MSHR hits
1142system.cpu0.icache.overall_mshr_hits::total 52766 # number of overall MSHR hits
1143system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1245532 # number of ReadReq MSHR misses
1144system.cpu0.icache.ReadReq_mshr_misses::total 1245532 # number of ReadReq MSHR misses
1145system.cpu0.icache.demand_mshr_misses::cpu0.inst 1245532 # number of demand (read+write) MSHR misses
1146system.cpu0.icache.demand_mshr_misses::total 1245532 # number of demand (read+write) MSHR misses
1147system.cpu0.icache.overall_mshr_misses::cpu0.inst 1245532 # number of overall MSHR misses
1148system.cpu0.icache.overall_mshr_misses::total 1245532 # number of overall MSHR misses
1149system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable
1150system.cpu0.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable
1151system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses
1152system.cpu0.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses
1153system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11887458427 # number of ReadReq MSHR miss cycles
1154system.cpu0.icache.ReadReq_mshr_miss_latency::total 11887458427 # number of ReadReq MSHR miss cycles
1155system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11887458427 # number of demand (read+write) MSHR miss cycles
1156system.cpu0.icache.demand_mshr_miss_latency::total 11887458427 # number of demand (read+write) MSHR miss cycles
1157system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11887458427 # number of overall MSHR miss cycles
1158system.cpu0.icache.overall_mshr_miss_latency::total 11887458427 # number of overall MSHR miss cycles
1159system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 269145498 # number of ReadReq MSHR uncacheable cycles
1160system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 269145498 # number of ReadReq MSHR uncacheable cycles
1161system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 269145498 # number of overall MSHR uncacheable cycles
1162system.cpu0.icache.overall_mshr_uncacheable_latency::total 269145498 # number of overall MSHR uncacheable cycles
1163system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033339 # mshr miss rate for ReadReq accesses
1164system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033339 # mshr miss rate for ReadReq accesses
1165system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033339 # mshr miss rate for demand accesses
1166system.cpu0.icache.demand_mshr_miss_rate::total 0.033339 # mshr miss rate for demand accesses
1167system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033339 # mshr miss rate for overall accesses
1168system.cpu0.icache.overall_mshr_miss_rate::total 0.033339 # mshr miss rate for overall accesses
1169system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9544.081105 # average ReadReq mshr miss latency
1170system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9544.081105 # average ReadReq mshr miss latency
1171system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9544.081105 # average overall mshr miss latency
1172system.cpu0.icache.demand_avg_mshr_miss_latency::total 9544.081105 # average overall mshr miss latency
1173system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9544.081105 # average overall mshr miss latency
1174system.cpu0.icache.overall_avg_mshr_miss_latency::total 9544.081105 # average overall mshr miss latency
1175system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average ReadReq mshr uncacheable latency
1176system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460 # average ReadReq mshr uncacheable latency
1177system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average overall mshr uncacheable latency
1178system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460 # average overall mshr uncacheable latency
1179system.cpu0.l2cache.prefetcher.num_hwpf_issued 1836444 # number of hwpf issued
1180system.cpu0.l2cache.prefetcher.pfIdentified 1838932 # number of prefetch candidates identified
1181system.cpu0.l2cache.prefetcher.pfBufferHit 2249 # number of redundant prefetches already in prefetch queue
1182system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1183system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1184system.cpu0.l2cache.prefetcher.pfSpanPage 237260 # number of prefetches not generated due to page crossing
1185system.cpu0.l2cache.tags.replacements 275777 # number of replacements
1186system.cpu0.l2cache.tags.tagsinuse 16077.094616 # Cycle average of tags in use
1187system.cpu0.l2cache.tags.total_refs 3264993 # Total number of references to valid blocks.
1188system.cpu0.l2cache.tags.sampled_refs 291873 # Sample count of references to valid blocks.
1189system.cpu0.l2cache.tags.avg_refs 11.186348 # Average number of references to valid blocks.
1190system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1191system.cpu0.l2cache.tags.occ_blocks::writebacks 14642.260262 # Average occupied blocks per requestor
1192system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 14.030425 # Average occupied blocks per requestor
1193system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.082237 # Average occupied blocks per requestor
1194system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1420.721692 # Average occupied blocks per requestor
1195system.cpu0.l2cache.tags.occ_percent::writebacks 0.893693 # Average percentage of cache occupancy
1196system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000856 # Average percentage of cache occupancy
1197system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy
1198system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.086714 # Average percentage of cache occupancy
1199system.cpu0.l2cache.tags.occ_percent::total 0.981268 # Average percentage of cache occupancy
1200system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1015 # Occupied blocks per task id
1201system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id
1202system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15073 # Occupied blocks per task id
1203system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 44 # Occupied blocks per task id
1204system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 314 # Occupied blocks per task id
1205system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 375 # Occupied blocks per task id
1206system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 282 # Occupied blocks per task id
1207system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
1208system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
1209system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
1210system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
1211system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 477 # Occupied blocks per task id
1212system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4659 # Occupied blocks per task id
1213system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6956 # Occupied blocks per task id
1214system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2859 # Occupied blocks per task id
1215system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061951 # Percentage of cache occupancy per task id
1216system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id
1217system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.919983 # Percentage of cache occupancy per task id
1218system.cpu0.l2cache.tags.tag_accesses 66024498 # Number of tag accesses
1219system.cpu0.l2cache.tags.data_accesses 66024498 # Number of data accesses
1220system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55983 # number of ReadReq hits
1221system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13286 # number of ReadReq hits
1222system.cpu0.l2cache.ReadReq_hits::total 69269 # number of ReadReq hits
1223system.cpu0.l2cache.WritebackDirty_hits::writebacks 482066 # number of WritebackDirty hits
1224system.cpu0.l2cache.WritebackDirty_hits::total 482066 # number of WritebackDirty hits
1225system.cpu0.l2cache.WritebackClean_hits::writebacks 1441412 # number of WritebackClean hits
1226system.cpu0.l2cache.WritebackClean_hits::total 1441412 # number of WritebackClean hits
1227system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits
1228system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
1229system.cpu0.l2cache.ReadExReq_hits::cpu0.data 221318 # number of ReadExReq hits
1230system.cpu0.l2cache.ReadExReq_hits::total 221318 # number of ReadExReq hits
1231system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1193309 # number of ReadCleanReq hits
1232system.cpu0.l2cache.ReadCleanReq_hits::total 1193309 # number of ReadCleanReq hits
1233system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 398313 # number of ReadSharedReq hits
1234system.cpu0.l2cache.ReadSharedReq_hits::total 398313 # number of ReadSharedReq hits
1235system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55983 # number of demand (read+write) hits
1236system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13286 # number of demand (read+write) hits
1237system.cpu0.l2cache.demand_hits::cpu0.inst 1193309 # number of demand (read+write) hits
1238system.cpu0.l2cache.demand_hits::cpu0.data 619631 # number of demand (read+write) hits
1239system.cpu0.l2cache.demand_hits::total 1882209 # number of demand (read+write) hits
1240system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55983 # number of overall hits
1241system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13286 # number of overall hits
1242system.cpu0.l2cache.overall_hits::cpu0.inst 1193309 # number of overall hits
1243system.cpu0.l2cache.overall_hits::cpu0.data 619631 # number of overall hits
1244system.cpu0.l2cache.overall_hits::total 1882209 # number of overall hits
1245system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 409 # number of ReadReq misses
1246system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 145 # number of ReadReq misses
1247system.cpu0.l2cache.ReadReq_misses::total 554 # number of ReadReq misses
1248system.cpu0.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses
1249system.cpu0.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses
1250system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55455 # number of UpgradeReq misses
1251system.cpu0.l2cache.UpgradeReq_misses::total 55455 # number of UpgradeReq misses
1252system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20295 # number of SCUpgradeReq misses
1253system.cpu0.l2cache.SCUpgradeReq_misses::total 20295 # number of SCUpgradeReq misses
1254system.cpu0.l2cache.ReadExReq_misses::cpu0.data 48487 # number of ReadExReq misses
1255system.cpu0.l2cache.ReadExReq_misses::total 48487 # number of ReadExReq misses
1256system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 52186 # number of ReadCleanReq misses
1257system.cpu0.l2cache.ReadCleanReq_misses::total 52186 # number of ReadCleanReq misses
1258system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 96414 # number of ReadSharedReq misses
1259system.cpu0.l2cache.ReadSharedReq_misses::total 96414 # number of ReadSharedReq misses
1260system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 409 # number of demand (read+write) misses
1261system.cpu0.l2cache.demand_misses::cpu0.itb.walker 145 # number of demand (read+write) misses
1262system.cpu0.l2cache.demand_misses::cpu0.inst 52186 # number of demand (read+write) misses
1263system.cpu0.l2cache.demand_misses::cpu0.data 144901 # number of demand (read+write) misses
1264system.cpu0.l2cache.demand_misses::total 197641 # number of demand (read+write) misses
1265system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 409 # number of overall misses
1266system.cpu0.l2cache.overall_misses::cpu0.itb.walker 145 # number of overall misses
1267system.cpu0.l2cache.overall_misses::cpu0.inst 52186 # number of overall misses
1268system.cpu0.l2cache.overall_misses::cpu0.data 144901 # number of overall misses
1269system.cpu0.l2cache.overall_misses::total 197641 # number of overall misses
1270system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11428500 # number of ReadReq miss cycles
1271system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3458500 # number of ReadReq miss cycles
1272system.cpu0.l2cache.ReadReq_miss_latency::total 14887000 # number of ReadReq miss cycles
1273system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 116593500 # number of UpgradeReq miss cycles
1274system.cpu0.l2cache.UpgradeReq_miss_latency::total 116593500 # number of UpgradeReq miss cycles
1275system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 25461000 # number of SCUpgradeReq miss cycles
1276system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 25461000 # number of SCUpgradeReq miss cycles
1277system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 459500 # number of SCUpgradeFailReq miss cycles
1278system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 459500 # number of SCUpgradeFailReq miss cycles
1279system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2707524000 # number of ReadExReq miss cycles
1280system.cpu0.l2cache.ReadExReq_miss_latency::total 2707524000 # number of ReadExReq miss cycles
1281system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2738746000 # number of ReadCleanReq miss cycles
1282system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2738746000 # number of ReadCleanReq miss cycles
1283system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2927576997 # number of ReadSharedReq miss cycles
1284system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2927576997 # number of ReadSharedReq miss cycles
1285system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11428500 # number of demand (read+write) miss cycles
1286system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3458500 # number of demand (read+write) miss cycles
1287system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2738746000 # number of demand (read+write) miss cycles
1288system.cpu0.l2cache.demand_miss_latency::cpu0.data 5635100997 # number of demand (read+write) miss cycles
1289system.cpu0.l2cache.demand_miss_latency::total 8388733997 # number of demand (read+write) miss cycles
1290system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11428500 # number of overall miss cycles
1291system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3458500 # number of overall miss cycles
1292system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2738746000 # number of overall miss cycles
1293system.cpu0.l2cache.overall_miss_latency::cpu0.data 5635100997 # number of overall miss cycles
1294system.cpu0.l2cache.overall_miss_latency::total 8388733997 # number of overall miss cycles
1295system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 56392 # number of ReadReq accesses(hits+misses)
1296system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 13431 # number of ReadReq accesses(hits+misses)
1297system.cpu0.l2cache.ReadReq_accesses::total 69823 # number of ReadReq accesses(hits+misses)
1298system.cpu0.l2cache.WritebackDirty_accesses::writebacks 482067 # number of WritebackDirty accesses(hits+misses)
1299system.cpu0.l2cache.WritebackDirty_accesses::total 482067 # number of WritebackDirty accesses(hits+misses)
1300system.cpu0.l2cache.WritebackClean_accesses::writebacks 1441412 # number of WritebackClean accesses(hits+misses)
1301system.cpu0.l2cache.WritebackClean_accesses::total 1441412 # number of WritebackClean accesses(hits+misses)
1302system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55456 # number of UpgradeReq accesses(hits+misses)
1303system.cpu0.l2cache.UpgradeReq_accesses::total 55456 # number of UpgradeReq accesses(hits+misses)
1304system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20295 # number of SCUpgradeReq accesses(hits+misses)
1305system.cpu0.l2cache.SCUpgradeReq_accesses::total 20295 # number of SCUpgradeReq accesses(hits+misses)
1306system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269805 # number of ReadExReq accesses(hits+misses)
1307system.cpu0.l2cache.ReadExReq_accesses::total 269805 # number of ReadExReq accesses(hits+misses)
1308system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1245495 # number of ReadCleanReq accesses(hits+misses)
1309system.cpu0.l2cache.ReadCleanReq_accesses::total 1245495 # number of ReadCleanReq accesses(hits+misses)
1310system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 494727 # number of ReadSharedReq accesses(hits+misses)
1311system.cpu0.l2cache.ReadSharedReq_accesses::total 494727 # number of ReadSharedReq accesses(hits+misses)
1312system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 56392 # number of demand (read+write) accesses
1313system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 13431 # number of demand (read+write) accesses
1314system.cpu0.l2cache.demand_accesses::cpu0.inst 1245495 # number of demand (read+write) accesses
1315system.cpu0.l2cache.demand_accesses::cpu0.data 764532 # number of demand (read+write) accesses
1316system.cpu0.l2cache.demand_accesses::total 2079850 # number of demand (read+write) accesses
1317system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 56392 # number of overall (read+write) accesses
1318system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 13431 # number of overall (read+write) accesses
1319system.cpu0.l2cache.overall_accesses::cpu0.inst 1245495 # number of overall (read+write) accesses
1320system.cpu0.l2cache.overall_accesses::cpu0.data 764532 # number of overall (read+write) accesses
1321system.cpu0.l2cache.overall_accesses::total 2079850 # number of overall (read+write) accesses
1322system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007253 # miss rate for ReadReq accesses
1323system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.010796 # miss rate for ReadReq accesses
1324system.cpu0.l2cache.ReadReq_miss_rate::total 0.007934 # miss rate for ReadReq accesses
1325system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000002 # miss rate for WritebackDirty accesses
1326system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000002 # miss rate for WritebackDirty accesses
1327system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999982 # miss rate for UpgradeReq accesses
1328system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999982 # miss rate for UpgradeReq accesses
1329system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1330system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1331system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.179711 # miss rate for ReadExReq accesses
1332system.cpu0.l2cache.ReadExReq_miss_rate::total 0.179711 # miss rate for ReadExReq accesses
1333system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.041900 # miss rate for ReadCleanReq accesses
1334system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.041900 # miss rate for ReadCleanReq accesses
1335system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.194883 # miss rate for ReadSharedReq accesses
1336system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.194883 # miss rate for ReadSharedReq accesses
1337system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007253 # miss rate for demand accesses
1338system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.010796 # miss rate for demand accesses
1339system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041900 # miss rate for demand accesses
1340system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.189529 # miss rate for demand accesses
1341system.cpu0.l2cache.demand_miss_rate::total 0.095027 # miss rate for demand accesses
1342system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007253 # miss rate for overall accesses
1343system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.010796 # miss rate for overall accesses
1344system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041900 # miss rate for overall accesses
1345system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.189529 # miss rate for overall accesses
1346system.cpu0.l2cache.overall_miss_rate::total 0.095027 # miss rate for overall accesses
1347system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27942.542787 # average ReadReq miss latency
1348system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23851.724138 # average ReadReq miss latency
1349system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26871.841155 # average ReadReq miss latency
1350system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 2102.488504 # average UpgradeReq miss latency
1351system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 2102.488504 # average UpgradeReq miss latency
1352system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1254.545455 # average SCUpgradeReq miss latency
1353system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1254.545455 # average SCUpgradeReq miss latency
1354system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency
1355system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
1356system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55840.204591 # average ReadExReq miss latency
1357system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55840.204591 # average ReadExReq miss latency
1358system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 52480.473690 # average ReadCleanReq miss latency
1359system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 52480.473690 # average ReadCleanReq miss latency
1360system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 30364.646182 # average ReadSharedReq miss latency
1361system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 30364.646182 # average ReadSharedReq miss latency
1362system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27942.542787 # average overall miss latency
1363system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23851.724138 # average overall miss latency
1364system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 52480.473690 # average overall miss latency
1365system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38889.317513 # average overall miss latency
1366system.cpu0.l2cache.demand_avg_miss_latency::total 42444.300510 # average overall miss latency
1367system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27942.542787 # average overall miss latency
1368system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23851.724138 # average overall miss latency
1369system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 52480.473690 # average overall miss latency
1370system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38889.317513 # average overall miss latency
1371system.cpu0.l2cache.overall_avg_miss_latency::total 42444.300510 # average overall miss latency
1372system.cpu0.l2cache.blocked_cycles::no_mshrs 92 # number of cycles access was blocked
1373system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1374system.cpu0.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked
1375system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1376system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 30.666667 # average number of cycles each access was blocked
1377system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1378system.cpu0.l2cache.unused_prefetches 10565 # number of HardPF blocks evicted w/o reference
1379system.cpu0.l2cache.writebacks::writebacks 229088 # number of writebacks
1380system.cpu0.l2cache.writebacks::total 229088 # number of writebacks
1381system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5680 # number of ReadExReq MSHR hits
1382system.cpu0.l2cache.ReadExReq_mshr_hits::total 5680 # number of ReadExReq MSHR hits
1383system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 39 # number of ReadCleanReq MSHR hits
1384system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 39 # number of ReadCleanReq MSHR hits
1385system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 771 # number of ReadSharedReq MSHR hits
1386system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 771 # number of ReadSharedReq MSHR hits
1387system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 39 # number of demand (read+write) MSHR hits
1388system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6451 # number of demand (read+write) MSHR hits
1389system.cpu0.l2cache.demand_mshr_hits::total 6490 # number of demand (read+write) MSHR hits
1390system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 39 # number of overall MSHR hits
1391system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6451 # number of overall MSHR hits
1392system.cpu0.l2cache.overall_mshr_hits::total 6490 # number of overall MSHR hits
1393system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 409 # number of ReadReq MSHR misses
1394system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 145 # number of ReadReq MSHR misses
1395system.cpu0.l2cache.ReadReq_mshr_misses::total 554 # number of ReadReq MSHR misses
1396system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses
1397system.cpu0.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses
1398system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 255939 # number of HardPFReq MSHR misses
1399system.cpu0.l2cache.HardPFReq_mshr_misses::total 255939 # number of HardPFReq MSHR misses
1400system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55455 # number of UpgradeReq MSHR misses
1401system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55455 # number of UpgradeReq MSHR misses
1402system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20295 # number of SCUpgradeReq MSHR misses
1403system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20295 # number of SCUpgradeReq MSHR misses
1404system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42807 # number of ReadExReq MSHR misses
1405system.cpu0.l2cache.ReadExReq_mshr_misses::total 42807 # number of ReadExReq MSHR misses
1406system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 52147 # number of ReadCleanReq MSHR misses
1407system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 52147 # number of ReadCleanReq MSHR misses
1408system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 95643 # number of ReadSharedReq MSHR misses
1409system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 95643 # number of ReadSharedReq MSHR misses
1410system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 409 # number of demand (read+write) MSHR misses
1411system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 145 # number of demand (read+write) MSHR misses
1412system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 52147 # number of demand (read+write) MSHR misses
1413system.cpu0.l2cache.demand_mshr_misses::cpu0.data 138450 # number of demand (read+write) MSHR misses
1414system.cpu0.l2cache.demand_mshr_misses::total 191151 # number of demand (read+write) MSHR misses
1415system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 409 # number of overall MSHR misses
1416system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 145 # number of overall MSHR misses
1417system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 52147 # number of overall MSHR misses
1418system.cpu0.l2cache.overall_mshr_misses::cpu0.data 138450 # number of overall MSHR misses
1419system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 255939 # number of overall MSHR misses
1420system.cpu0.l2cache.overall_mshr_misses::total 447090 # number of overall MSHR misses
1421system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable
1422system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20340 # number of ReadReq MSHR uncacheable
1423system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23343 # number of ReadReq MSHR uncacheable
1424system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19033 # number of WriteReq MSHR uncacheable
1425system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19033 # number of WriteReq MSHR uncacheable
1426system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses
1427system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39373 # number of overall MSHR uncacheable misses
1428system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 42376 # number of overall MSHR uncacheable misses
1429system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 8974500 # number of ReadReq MSHR miss cycles
1430system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2588500 # number of ReadReq MSHR miss cycles
1431system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 11563000 # number of ReadReq MSHR miss cycles
1432system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15061119493 # number of HardPFReq MSHR miss cycles
1433system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15061119493 # number of HardPFReq MSHR miss cycles
1434system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1081830000 # number of UpgradeReq MSHR miss cycles
1435system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1081830000 # number of UpgradeReq MSHR miss cycles
1436system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 319630999 # number of SCUpgradeReq MSHR miss cycles
1437system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 319630999 # number of SCUpgradeReq MSHR miss cycles
1438system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 381500 # number of SCUpgradeFailReq MSHR miss cycles
1439system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 381500 # number of SCUpgradeFailReq MSHR miss cycles
1440system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1771002000 # number of ReadExReq MSHR miss cycles
1441system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1771002000 # number of ReadExReq MSHR miss cycles
1442system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2424780500 # number of ReadCleanReq MSHR miss cycles
1443system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2424780500 # number of ReadCleanReq MSHR miss cycles
1444system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2310424997 # number of ReadSharedReq MSHR miss cycles
1445system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2310424997 # number of ReadSharedReq MSHR miss cycles
1446system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 8974500 # number of demand (read+write) MSHR miss cycles
1447system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2588500 # number of demand (read+write) MSHR miss cycles
1448system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2424780500 # number of demand (read+write) MSHR miss cycles
1449system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4081426997 # number of demand (read+write) MSHR miss cycles
1450system.cpu0.l2cache.demand_mshr_miss_latency::total 6517770497 # number of demand (read+write) MSHR miss cycles
1451system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 8974500 # number of overall MSHR miss cycles
1452system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2588500 # number of overall MSHR miss cycles
1453system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2424780500 # number of overall MSHR miss cycles
1454system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4081426997 # number of overall MSHR miss cycles
1455system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15061119493 # number of overall MSHR miss cycles
1456system.cpu0.l2cache.overall_mshr_miss_latency::total 21578889990 # number of overall MSHR miss cycles
1457system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 246621000 # number of ReadReq MSHR uncacheable cycles
1458system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4371667500 # number of ReadReq MSHR uncacheable cycles
1459system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4618288500 # number of ReadReq MSHR uncacheable cycles
1460system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 246621000 # number of overall MSHR uncacheable cycles
1461system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4371667500 # number of overall MSHR uncacheable cycles
1462system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4618288500 # number of overall MSHR uncacheable cycles
1463system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007253 # mshr miss rate for ReadReq accesses
1464system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.010796 # mshr miss rate for ReadReq accesses
1465system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.007934 # mshr miss rate for ReadReq accesses
1466system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for WritebackDirty accesses
1467system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000002 # mshr miss rate for WritebackDirty accesses
1468system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1469system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1470system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses
1471system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses
1472system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1473system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1474system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158659 # mshr miss rate for ReadExReq accesses
1475system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158659 # mshr miss rate for ReadExReq accesses
1476system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041868 # mshr miss rate for ReadCleanReq accesses
1477system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041868 # mshr miss rate for ReadCleanReq accesses
1478system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.193325 # mshr miss rate for ReadSharedReq accesses
1479system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.193325 # mshr miss rate for ReadSharedReq accesses
1480system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007253 # mshr miss rate for demand accesses
1481system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.010796 # mshr miss rate for demand accesses
1482system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041868 # mshr miss rate for demand accesses
1483system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181091 # mshr miss rate for demand accesses
1484system.cpu0.l2cache.demand_mshr_miss_rate::total 0.091906 # mshr miss rate for demand accesses
1485system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007253 # mshr miss rate for overall accesses
1486system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.010796 # mshr miss rate for overall accesses
1487system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041868 # mshr miss rate for overall accesses
1488system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181091 # mshr miss rate for overall accesses
1489system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1490system.cpu0.l2cache.overall_mshr_miss_rate::total 0.214963 # mshr miss rate for overall accesses
1491system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21942.542787 # average ReadReq mshr miss latency
1492system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17851.724138 # average ReadReq mshr miss latency
1493system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20871.841155 # average ReadReq mshr miss latency
1494system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58846.520042 # average HardPFReq mshr miss latency
1495system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58846.520042 # average HardPFReq mshr miss latency
1496system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19508.249932 # average UpgradeReq mshr miss latency
1497system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19508.249932 # average UpgradeReq mshr miss latency
1498system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15749.248534 # average SCUpgradeReq mshr miss latency
1499system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15749.248534 # average SCUpgradeReq mshr miss latency
1500system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency
1501system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
1502system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41371.784988 # average ReadExReq mshr miss latency
1503system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41371.784988 # average ReadExReq mshr miss latency
1504system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 46498.945289 # average ReadCleanReq mshr miss latency
1505system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 46498.945289 # average ReadCleanReq mshr miss latency
1506system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24156.760003 # average ReadSharedReq mshr miss latency
1507system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24156.760003 # average ReadSharedReq mshr miss latency
1508system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21942.542787 # average overall mshr miss latency
1509system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17851.724138 # average overall mshr miss latency
1510system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 46498.945289 # average overall mshr miss latency
1511system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29479.429375 # average overall mshr miss latency
1512system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34097.496205 # average overall mshr miss latency
1513system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21942.542787 # average overall mshr miss latency
1514system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17851.724138 # average overall mshr miss latency
1515system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 46498.945289 # average overall mshr miss latency
1516system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29479.429375 # average overall mshr miss latency
1517system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58846.520042 # average overall mshr miss latency
1518system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48265.203852 # average overall mshr miss latency
1519system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average ReadReq mshr uncacheable latency
1520system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 214929.572271 # average ReadReq mshr uncacheable latency
1521system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 197844.685773 # average ReadReq mshr uncacheable latency
1522system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average overall mshr uncacheable latency
1523system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111032.115917 # average overall mshr uncacheable latency
1524system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 108983.587408 # average overall mshr uncacheable latency
1525system.cpu0.toL2Bus.snoop_filter.tot_requests 4059553 # Total number of requests made to the snoop filter.
1526system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2049525 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1527system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31130 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1528system.cpu0.toL2Bus.snoop_filter.tot_snoops 322631 # Total number of snoops made to the snoop filter.
1529system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 318742 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1530system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3889 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1531system.cpu0.toL2Bus.trans_dist::ReadReq 102054 # Transaction distribution
1532system.cpu0.toL2Bus.trans_dist::ReadResp 1891052 # Transaction distribution
1533system.cpu0.toL2Bus.trans_dist::WriteReq 19033 # Transaction distribution
1534system.cpu0.toL2Bus.trans_dist::WriteResp 19033 # Transaction distribution
1535system.cpu0.toL2Bus.trans_dist::WritebackDirty 711408 # Transaction distribution
1536system.cpu0.toL2Bus.trans_dist::WritebackClean 1472505 # Transaction distribution
1537system.cpu0.toL2Bus.trans_dist::CleanEvict 201922 # Transaction distribution
1538system.cpu0.toL2Bus.trans_dist::HardPFReq 326386 # Transaction distribution
1539system.cpu0.toL2Bus.trans_dist::UpgradeReq 87454 # Transaction distribution
1540system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42857 # Transaction distribution
1541system.cpu0.toL2Bus.trans_dist::UpgradeResp 113442 # Transaction distribution
1542system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution
1543system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 28 # Transaction distribution
1544system.cpu0.toL2Bus.trans_dist::ReadExReq 288333 # Transaction distribution
1545system.cpu0.toL2Bus.trans_dist::ReadExResp 284690 # Transaction distribution
1546system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1245532 # Transaction distribution
1547system.cpu0.toL2Bus.trans_dist::ReadSharedReq 576445 # Transaction distribution
1548system.cpu0.toL2Bus.trans_dist::InvalidateReq 3297 # Transaction distribution
1549system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3742005 # Packet count per connected master and slave (bytes)
1550system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2570285 # Packet count per connected master and slave (bytes)
1551system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29068 # Packet count per connected master and slave (bytes)
1552system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119436 # Packet count per connected master and slave (bytes)
1553system.cpu0.toL2Bus.pkt_count::total 6460794 # Packet count per connected master and slave (bytes)
1554system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 159437936 # Cumulative packet size per connected master and slave (bytes)
1555system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98528220 # Cumulative packet size per connected master and slave (bytes)
1556system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53724 # Cumulative packet size per connected master and slave (bytes)
1557system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 225568 # Cumulative packet size per connected master and slave (bytes)
1558system.cpu0.toL2Bus.pkt_size::total 258245448 # Cumulative packet size per connected master and slave (bytes)
1559system.cpu0.toL2Bus.snoops 1026066 # Total snoops (count)
1560system.cpu0.toL2Bus.snoop_fanout::samples 3122672 # Request fanout histogram
1561system.cpu0.toL2Bus.snoop_fanout::mean 0.120692 # Request fanout histogram
1562system.cpu0.toL2Bus.snoop_fanout::stdev 0.329569 # Request fanout histogram
1563system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1564system.cpu0.toL2Bus.snoop_fanout::0 2749681 88.06% 88.06% # Request fanout histogram
1565system.cpu0.toL2Bus.snoop_fanout::1 369102 11.82% 99.88% # Request fanout histogram
1566system.cpu0.toL2Bus.snoop_fanout::2 3889 0.12% 100.00% # Request fanout histogram
1567system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1568system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1569system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1570system.cpu0.toL2Bus.snoop_fanout::total 3122672 # Request fanout histogram
1571system.cpu0.toL2Bus.reqLayer0.occupancy 4044815993 # Layer occupancy (ticks)
1572system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1573system.cpu0.toL2Bus.snoopLayer0.occupancy 114413841 # Layer occupancy (ticks)
1574system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1575system.cpu0.toL2Bus.respLayer0.occupancy 1871838919 # Layer occupancy (ticks)
1576system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1577system.cpu0.toL2Bus.respLayer1.occupancy 1215906771 # Layer occupancy (ticks)
1578system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1579system.cpu0.toL2Bus.respLayer2.occupancy 15648976 # Layer occupancy (ticks)
1580system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1581system.cpu0.toL2Bus.respLayer3.occupancy 63082921 # Layer occupancy (ticks)
1582system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1583system.cpu1.branchPred.lookups 34009026 # Number of BP lookups
1584system.cpu1.branchPred.condPredicted 11598982 # Number of conditional branches predicted
1585system.cpu1.branchPred.condIncorrect 286954 # Number of conditional branches incorrect
1586system.cpu1.branchPred.BTBLookups 18822923 # Number of BTB lookups
1587system.cpu1.branchPred.BTBHits 6035110 # Number of BTB hits
1588system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1589system.cpu1.branchPred.BTBHitPct 32.062555 # BTB Hit Percentage
1590system.cpu1.branchPred.usedRAS 12529712 # Number of times the RAS was used to get a target.
1591system.cpu1.branchPred.RASInCorrect 7339 # Number of incorrect RAS predictions.
1592system.cpu1.branchPred.indirectLookups 9024222 # Number of indirect predictor lookups.
1593system.cpu1.branchPred.indirectHits 8987643 # Number of indirect target hits.
1594system.cpu1.branchPred.indirectMisses 36579 # Number of indirect misses.
1595system.cpu1.branchPredindirectMispredicted 11117 # Number of mispredicted indirect branches.
1596system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1597system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1598system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1599system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1600system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1601system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1602system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1603system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1617system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1618system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1619system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1620system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1621system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1622system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1623system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1624system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1625system.cpu1.dtb.walker.walks 22019 # Table walker walks requested
1626system.cpu1.dtb.walker.walksShort 22019 # Table walker walks initiated with short descriptors
1627system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8988 # Level at which table walker walks with short descriptors terminate
1628system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5922 # Level at which table walker walks with short descriptors terminate
1629system.cpu1.dtb.walker.walksSquashedBefore 7109 # Table walks squashed before starting
1630system.cpu1.dtb.walker.walkWaitTime::samples 14910 # Table walker wait (enqueue to first request) latency
1631system.cpu1.dtb.walker.walkWaitTime::mean 597.183099 # Table walker wait (enqueue to first request) latency
1632system.cpu1.dtb.walker.walkWaitTime::stdev 3274.563107 # Table walker wait (enqueue to first request) latency
1633system.cpu1.dtb.walker.walkWaitTime::0-4095 14271 95.71% 95.71% # Table walker wait (enqueue to first request) latency
1634system.cpu1.dtb.walker.walkWaitTime::4096-8191 175 1.17% 96.89% # Table walker wait (enqueue to first request) latency
1635system.cpu1.dtb.walker.walkWaitTime::8192-12287 226 1.52% 98.40% # Table walker wait (enqueue to first request) latency
1636system.cpu1.dtb.walker.walkWaitTime::12288-16383 97 0.65% 99.05% # Table walker wait (enqueue to first request) latency
1637system.cpu1.dtb.walker.walkWaitTime::16384-20479 36 0.24% 99.30% # Table walker wait (enqueue to first request) latency
1638system.cpu1.dtb.walker.walkWaitTime::20480-24575 18 0.12% 99.42% # Table walker wait (enqueue to first request) latency
1639system.cpu1.dtb.walker.walkWaitTime::24576-28671 9 0.06% 99.48% # Table walker wait (enqueue to first request) latency
1640system.cpu1.dtb.walker.walkWaitTime::28672-32767 63 0.42% 99.90% # Table walker wait (enqueue to first request) latency
1641system.cpu1.dtb.walker.walkWaitTime::32768-36863 6 0.04% 99.94% # Table walker wait (enqueue to first request) latency
1642system.cpu1.dtb.walker.walkWaitTime::36864-40959 4 0.03% 99.97% # Table walker wait (enqueue to first request) latency
1643system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency
1644system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
1645system.cpu1.dtb.walker.walkWaitTime::53248-57343 3 0.02% 100.00% # Table walker wait (enqueue to first request) latency
1646system.cpu1.dtb.walker.walkWaitTime::total 14910 # Table walker wait (enqueue to first request) latency
1647system.cpu1.dtb.walker.walkCompletionTime::samples 5586 # Table walker service (enqueue to completion) latency
1648system.cpu1.dtb.walker.walkCompletionTime::mean 11231.919083 # Table walker service (enqueue to completion) latency
1649system.cpu1.dtb.walker.walkCompletionTime::gmean 9899.070869 # Table walker service (enqueue to completion) latency
1650system.cpu1.dtb.walker.walkCompletionTime::stdev 6145.006909 # Table walker service (enqueue to completion) latency
1651system.cpu1.dtb.walker.walkCompletionTime::0-8191 1859 33.28% 33.28% # Table walker service (enqueue to completion) latency
1652system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3110 55.67% 88.95% # Table walker service (enqueue to completion) latency
1653system.cpu1.dtb.walker.walkCompletionTime::16384-24575 395 7.07% 96.03% # Table walker service (enqueue to completion) latency
1654system.cpu1.dtb.walker.walkCompletionTime::24576-32767 162 2.90% 98.93% # Table walker service (enqueue to completion) latency
1655system.cpu1.dtb.walker.walkCompletionTime::32768-40959 30 0.54% 99.46% # Table walker service (enqueue to completion) latency
1656system.cpu1.dtb.walker.walkCompletionTime::40960-49151 25 0.45% 99.91% # Table walker service (enqueue to completion) latency
1657system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.04% 99.95% # Table walker service (enqueue to completion) latency
1658system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.04% 99.98% # Table walker service (enqueue to completion) latency
1659system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
1660system.cpu1.dtb.walker.walkCompletionTime::total 5586 # Table walker service (enqueue to completion) latency
1661system.cpu1.dtb.walker.walksPending::samples 72596800264 # Table walker pending requests distribution
1662system.cpu1.dtb.walker.walksPending::mean 0.178979 # Table walker pending requests distribution
1663system.cpu1.dtb.walker.walksPending::stdev 0.387926 # Table walker pending requests distribution
1664system.cpu1.dtb.walker.walksPending::0 59651088264 82.17% 82.17% # Table walker pending requests distribution
1665system.cpu1.dtb.walker.walksPending::1 12923549000 17.80% 99.97% # Table walker pending requests distribution
1666system.cpu1.dtb.walker.walksPending::2 13278500 0.02% 99.99% # Table walker pending requests distribution
1667system.cpu1.dtb.walker.walksPending::3 4124000 0.01% 99.99% # Table walker pending requests distribution
1668system.cpu1.dtb.walker.walksPending::4 1159000 0.00% 100.00% # Table walker pending requests distribution
1669system.cpu1.dtb.walker.walksPending::5 892500 0.00% 100.00% # Table walker pending requests distribution
1670system.cpu1.dtb.walker.walksPending::6 1267000 0.00% 100.00% # Table walker pending requests distribution
1671system.cpu1.dtb.walker.walksPending::7 399000 0.00% 100.00% # Table walker pending requests distribution
1672system.cpu1.dtb.walker.walksPending::8 261000 0.00% 100.00% # Table walker pending requests distribution
1673system.cpu1.dtb.walker.walksPending::9 175000 0.00% 100.00% # Table walker pending requests distribution
1674system.cpu1.dtb.walker.walksPending::10 102500 0.00% 100.00% # Table walker pending requests distribution
1675system.cpu1.dtb.walker.walksPending::11 47000 0.00% 100.00% # Table walker pending requests distribution
1676system.cpu1.dtb.walker.walksPending::12 179500 0.00% 100.00% # Table walker pending requests distribution
1677system.cpu1.dtb.walker.walksPending::13 63000 0.00% 100.00% # Table walker pending requests distribution
1678system.cpu1.dtb.walker.walksPending::14 38500 0.00% 100.00% # Table walker pending requests distribution
1679system.cpu1.dtb.walker.walksPending::15 176500 0.00% 100.00% # Table walker pending requests distribution
1680system.cpu1.dtb.walker.walksPending::total 72596800264 # Table walker pending requests distribution
1681system.cpu1.dtb.walker.walkPageSizes::4K 1935 74.77% 74.77% # Table walker page sizes translated
1682system.cpu1.dtb.walker.walkPageSizes::1M 653 25.23% 100.00% # Table walker page sizes translated
1683system.cpu1.dtb.walker.walkPageSizes::total 2588 # Table walker page sizes translated
1684system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 22019 # Table walker requests started/completed, data/inst
1685system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1686system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 22019 # Table walker requests started/completed, data/inst
1687system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2588 # Table walker requests started/completed, data/inst
1688system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1689system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst
1690system.cpu1.dtb.walker.walkRequestOrigin::total 24607 # Table walker requests started/completed, data/inst
1691system.cpu1.dtb.inst_hits 0 # ITB inst hits
1692system.cpu1.dtb.inst_misses 0 # ITB inst misses
1693system.cpu1.dtb.read_hits 10217146 # DTB read hits
1694system.cpu1.dtb.read_misses 19031 # DTB read misses
1695system.cpu1.dtb.write_hits 6545704 # DTB write hits
1696system.cpu1.dtb.write_misses 2988 # DTB write misses
1697system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
1698system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1699system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1700system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1701system.cpu1.dtb.flush_entries 2034 # Number of entries that have been flushed from TLB
1702system.cpu1.dtb.align_faults 49 # Number of TLB faults due to alignment restrictions
1703system.cpu1.dtb.prefetch_faults 375 # Number of TLB faults due to prefetch
1704system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1705system.cpu1.dtb.perms_faults 389 # Number of TLB faults due to permissions restrictions
1706system.cpu1.dtb.read_accesses 10236177 # DTB read accesses
1707system.cpu1.dtb.write_accesses 6548692 # DTB write accesses
1708system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1709system.cpu1.dtb.hits 16762850 # DTB hits
1710system.cpu1.dtb.misses 22019 # DTB misses
1711system.cpu1.dtb.accesses 16784869 # DTB accesses
1712system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1713system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1714system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1715system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1716system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1717system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1718system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1719system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1733system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1734system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1735system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1736system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1737system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1738system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1739system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1740system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1741system.cpu1.itb.walker.walks 6065 # Table walker walks requested
1742system.cpu1.itb.walker.walksShort 6065 # Table walker walks initiated with short descriptors
1743system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2849 # Level at which table walker walks with short descriptors terminate
1744system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2599 # Level at which table walker walks with short descriptors terminate
1745system.cpu1.itb.walker.walksSquashedBefore 617 # Table walks squashed before starting
1746system.cpu1.itb.walker.walkWaitTime::samples 5448 # Table walker wait (enqueue to first request) latency
1747system.cpu1.itb.walker.walkWaitTime::mean 300.018355 # Table walker wait (enqueue to first request) latency
1748system.cpu1.itb.walker.walkWaitTime::stdev 2054.443929 # Table walker wait (enqueue to first request) latency
1749system.cpu1.itb.walker.walkWaitTime::0-4095 5317 97.60% 97.60% # Table walker wait (enqueue to first request) latency
1750system.cpu1.itb.walker.walkWaitTime::4096-8191 57 1.05% 98.64% # Table walker wait (enqueue to first request) latency
1751system.cpu1.itb.walker.walkWaitTime::8192-12287 30 0.55% 99.19% # Table walker wait (enqueue to first request) latency
1752system.cpu1.itb.walker.walkWaitTime::12288-16383 22 0.40% 99.60% # Table walker wait (enqueue to first request) latency
1753system.cpu1.itb.walker.walkWaitTime::16384-20479 8 0.15% 99.74% # Table walker wait (enqueue to first request) latency
1754system.cpu1.itb.walker.walkWaitTime::20480-24575 4 0.07% 99.82% # Table walker wait (enqueue to first request) latency
1755system.cpu1.itb.walker.walkWaitTime::24576-28671 5 0.09% 99.91% # Table walker wait (enqueue to first request) latency
1756system.cpu1.itb.walker.walkWaitTime::28672-32767 3 0.06% 99.96% # Table walker wait (enqueue to first request) latency
1757system.cpu1.itb.walker.walkWaitTime::32768-36863 2 0.04% 100.00% # Table walker wait (enqueue to first request) latency
1758system.cpu1.itb.walker.walkWaitTime::total 5448 # Table walker wait (enqueue to first request) latency
1759system.cpu1.itb.walker.walkCompletionTime::samples 1777 # Table walker service (enqueue to completion) latency
1760system.cpu1.itb.walker.walkCompletionTime::mean 11882.104671 # Table walker service (enqueue to completion) latency
1761system.cpu1.itb.walker.walkCompletionTime::gmean 10854.352895 # Table walker service (enqueue to completion) latency
1762system.cpu1.itb.walker.walkCompletionTime::stdev 5876.427895 # Table walker service (enqueue to completion) latency
1763system.cpu1.itb.walker.walkCompletionTime::0-8191 298 16.77% 16.77% # Table walker service (enqueue to completion) latency
1764system.cpu1.itb.walker.walkCompletionTime::8192-16383 1356 76.31% 93.08% # Table walker service (enqueue to completion) latency
1765system.cpu1.itb.walker.walkCompletionTime::16384-24575 64 3.60% 96.68% # Table walker service (enqueue to completion) latency
1766system.cpu1.itb.walker.walkCompletionTime::24576-32767 25 1.41% 98.09% # Table walker service (enqueue to completion) latency
1767system.cpu1.itb.walker.walkCompletionTime::32768-40959 23 1.29% 99.38% # Table walker service (enqueue to completion) latency
1768system.cpu1.itb.walker.walkCompletionTime::40960-49151 4 0.23% 99.61% # Table walker service (enqueue to completion) latency
1769system.cpu1.itb.walker.walkCompletionTime::49152-57343 3 0.17% 99.77% # Table walker service (enqueue to completion) latency
1770system.cpu1.itb.walker.walkCompletionTime::57344-65535 3 0.17% 99.94% # Table walker service (enqueue to completion) latency
1771system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency
1772system.cpu1.itb.walker.walkCompletionTime::total 1777 # Table walker service (enqueue to completion) latency
1773system.cpu1.itb.walker.walksPending::samples 16742440916 # Table walker pending requests distribution
1774system.cpu1.itb.walker.walksPending::mean 0.881191 # Table walker pending requests distribution
1775system.cpu1.itb.walker.walksPending::stdev 0.323702 # Table walker pending requests distribution
1776system.cpu1.itb.walker.walksPending::0 1989886764 11.89% 11.89% # Table walker pending requests distribution
1777system.cpu1.itb.walker.walksPending::1 14751845152 88.11% 100.00% # Table walker pending requests distribution
1778system.cpu1.itb.walker.walksPending::2 691000 0.00% 100.00% # Table walker pending requests distribution
1779system.cpu1.itb.walker.walksPending::3 18000 0.00% 100.00% # Table walker pending requests distribution
1780system.cpu1.itb.walker.walksPending::total 16742440916 # Table walker pending requests distribution
1781system.cpu1.itb.walker.walkPageSizes::4K 988 85.17% 85.17% # Table walker page sizes translated
1782system.cpu1.itb.walker.walkPageSizes::1M 172 14.83% 100.00% # Table walker page sizes translated
1783system.cpu1.itb.walker.walkPageSizes::total 1160 # Table walker page sizes translated
1784system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1785system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6065 # Table walker requests started/completed, data/inst
1786system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6065 # Table walker requests started/completed, data/inst
1787system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1788system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1160 # Table walker requests started/completed, data/inst
1789system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1160 # Table walker requests started/completed, data/inst
1790system.cpu1.itb.walker.walkRequestOrigin::total 7225 # Table walker requests started/completed, data/inst
1791system.cpu1.itb.inst_hits 43720811 # ITB inst hits
1792system.cpu1.itb.inst_misses 6065 # ITB inst misses
1793system.cpu1.itb.read_hits 0 # DTB read hits
1794system.cpu1.itb.read_misses 0 # DTB read misses
1795system.cpu1.itb.write_hits 0 # DTB write hits
1796system.cpu1.itb.write_misses 0 # DTB write misses
1797system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
1798system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1799system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1800system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1801system.cpu1.itb.flush_entries 1192 # Number of entries that have been flushed from TLB
1802system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1803system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1804system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1805system.cpu1.itb.perms_faults 560 # Number of TLB faults due to permissions restrictions
1806system.cpu1.itb.read_accesses 0 # DTB read accesses
1807system.cpu1.itb.write_accesses 0 # DTB write accesses
1808system.cpu1.itb.inst_accesses 43726876 # ITB inst accesses
1809system.cpu1.itb.hits 43720811 # DTB hits
1810system.cpu1.itb.misses 6065 # DTB misses
1811system.cpu1.itb.accesses 43726876 # DTB accesses
1812system.cpu1.numCycles 106544770 # number of cpu cycles simulated
1813system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1814system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1815system.cpu1.fetch.icacheStallCycles 10285169 # Number of cycles fetch is stalled on an Icache miss
1816system.cpu1.fetch.Insts 109329590 # Number of instructions fetch has processed
1817system.cpu1.fetch.Branches 34009026 # Number of branches that fetch encountered
1818system.cpu1.fetch.predictedBranches 27552465 # Number of branches that fetch has predicted taken
1819system.cpu1.fetch.Cycles 93003678 # Number of cycles fetch has run and was not squashing or blocked
1820system.cpu1.fetch.SquashCycles 3760962 # Number of cycles fetch has spent squashing
1821system.cpu1.fetch.TlbCycles 80448 # Number of cycles fetch has spent waiting for tlb
1822system.cpu1.fetch.MiscStallCycles 30144 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1823system.cpu1.fetch.PendingTrapStallCycles 178688 # Number of stall cycles due to pending traps
1824system.cpu1.fetch.PendingQuiesceStallCycles 297988 # Number of stall cycles due to pending quiesce instructions
1825system.cpu1.fetch.IcacheWaitRetryStallCycles 23992 # Number of stall cycles due to full MSHR
1826system.cpu1.fetch.CacheLines 43719656 # Number of cache lines fetched
1827system.cpu1.fetch.IcacheSquashes 111494 # Number of outstanding Icache misses that were squashed
1828system.cpu1.fetch.ItlbSquashes 2187 # Number of outstanding ITLB misses that were squashed
1829system.cpu1.fetch.rateDist::samples 105780588 # Number of instructions fetched each cycle (Total)
1830system.cpu1.fetch.rateDist::mean 1.280193 # Number of instructions fetched each cycle (Total)
1831system.cpu1.fetch.rateDist::stdev 1.339076 # Number of instructions fetched each cycle (Total)
1832system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1833system.cpu1.fetch.rateDist::0 48754447 46.09% 46.09% # Number of instructions fetched each cycle (Total)
1834system.cpu1.fetch.rateDist::1 14049982 13.28% 59.37% # Number of instructions fetched each cycle (Total)
1835system.cpu1.fetch.rateDist::2 7558912 7.15% 66.52% # Number of instructions fetched each cycle (Total)
1836system.cpu1.fetch.rateDist::3 35417247 33.48% 100.00% # Number of instructions fetched each cycle (Total)
1837system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1838system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1839system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
1840system.cpu1.fetch.rateDist::total 105780588 # Number of instructions fetched each cycle (Total)
1841system.cpu1.fetch.branchRate 0.319199 # Number of branch fetches per cycle
1842system.cpu1.fetch.rate 1.026138 # Number of inst fetches per cycle
1843system.cpu1.decode.IdleCycles 13239589 # Number of cycles decode is idle
1844system.cpu1.decode.BlockedCycles 62906745 # Number of cycles decode is blocked
1845system.cpu1.decode.RunCycles 26778529 # Number of cycles decode is running
1846system.cpu1.decode.UnblockCycles 1104926 # Number of cycles decode is unblocking
1847system.cpu1.decode.SquashCycles 1750799 # Number of cycles decode is squashing
1848system.cpu1.decode.BranchResolved 750846 # Number of times decode resolved a branch
1849system.cpu1.decode.BranchMispred 132411 # Number of times decode detected a branch misprediction
1850system.cpu1.decode.DecodedInsts 68206477 # Number of instructions handled by decode
1851system.cpu1.decode.SquashedInsts 1115402 # Number of squashed instructions handled by decode
1852system.cpu1.rename.SquashCycles 1750799 # Number of cycles rename is squashing
1853system.cpu1.rename.IdleCycles 17653779 # Number of cycles rename is idle
1854system.cpu1.rename.BlockCycles 2374666 # Number of cycles rename is blocking
1855system.cpu1.rename.serializeStallCycles 57902702 # count of cycles rename stalled for serializing inst
1856system.cpu1.rename.RunCycles 23447751 # Number of cycles rename is running
1857system.cpu1.rename.UnblockCycles 2650891 # Number of cycles rename is unblocking
1858system.cpu1.rename.RenamedInsts 55293666 # Number of instructions processed by rename
1859system.cpu1.rename.SquashedInsts 220143 # Number of squashed instructions processed by rename
1860system.cpu1.rename.ROBFullEvents 265669 # Number of times rename has blocked due to ROB full
1861system.cpu1.rename.IQFullEvents 37332 # Number of times rename has blocked due to IQ full
1862system.cpu1.rename.LQFullEvents 18647 # Number of times rename has blocked due to LQ full
1863system.cpu1.rename.SQFullEvents 1622767 # Number of times rename has blocked due to SQ full
1864system.cpu1.rename.RenamedOperands 55225885 # Number of destination operands rename has renamed
1865system.cpu1.rename.RenameLookups 261143833 # Number of register rename lookups that rename has made
1866system.cpu1.rename.int_rename_lookups 58792741 # Number of integer rename lookups
1867system.cpu1.rename.fp_rename_lookups 1698 # Number of floating rename lookups
1868system.cpu1.rename.CommittedMaps 52650074 # Number of HB maps that are committed
1869system.cpu1.rename.UndoneMaps 2575811 # Number of HB maps that are undone due to squashing
1870system.cpu1.rename.serializingInsts 1881943 # count of serializing insts renamed
1871system.cpu1.rename.tempSerializingInsts 1808403 # count of temporary serializing insts renamed
1872system.cpu1.rename.skidInsts 13140602 # count of insts added to the skid buffer
1873system.cpu1.memDep0.insertedLoads 10477180 # Number of loads inserted to the mem dependence unit.
1874system.cpu1.memDep0.insertedStores 6893389 # Number of stores inserted to the mem dependence unit.
1875system.cpu1.memDep0.conflictingLoads 629902 # Number of conflicting loads.
1876system.cpu1.memDep0.conflictingStores 660425 # Number of conflicting stores.
1877system.cpu1.iq.iqInstsAdded 54420167 # Number of instructions added to the IQ (excludes non-spec)
1878system.cpu1.iq.iqNonSpecInstsAdded 587049 # Number of non-speculative instructions added to the IQ
1879system.cpu1.iq.iqInstsIssued 54175023 # Number of instructions issued
1880system.cpu1.iq.iqSquashedInstsIssued 95968 # Number of squashed instructions issued
1881system.cpu1.iq.iqSquashedInstsExamined 3662766 # Number of squashed instructions iterated over during squash; mainly for profiling
1882system.cpu1.iq.iqSquashedOperandsExamined 5235414 # Number of squashed operands that are examined and possibly removed from graph
1883system.cpu1.iq.iqSquashedNonSpecRemoved 44205 # Number of squashed non-spec instructions that were removed
1884system.cpu1.iq.issued_per_cycle::samples 105780588 # Number of insts issued each cycle
1885system.cpu1.iq.issued_per_cycle::mean 0.512145 # Number of insts issued each cycle
1886system.cpu1.iq.issued_per_cycle::stdev 0.849831 # Number of insts issued each cycle
1887system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1888system.cpu1.iq.issued_per_cycle::0 72358023 68.40% 68.40% # Number of insts issued each cycle
1889system.cpu1.iq.issued_per_cycle::1 16614078 15.71% 84.11% # Number of insts issued each cycle
1890system.cpu1.iq.issued_per_cycle::2 13151335 12.43% 96.54% # Number of insts issued each cycle
1891system.cpu1.iq.issued_per_cycle::3 3370344 3.19% 99.73% # Number of insts issued each cycle
1892system.cpu1.iq.issued_per_cycle::4 286797 0.27% 100.00% # Number of insts issued each cycle
1893system.cpu1.iq.issued_per_cycle::5 11 0.00% 100.00% # Number of insts issued each cycle
1894system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
1895system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
1896system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
1897system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1898system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1899system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
1900system.cpu1.iq.issued_per_cycle::total 105780588 # Number of insts issued each cycle
1901system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1902system.cpu1.iq.fu_full::IntAlu 2941757 45.24% 45.24% # attempts to use FU when none available
1903system.cpu1.iq.fu_full::IntMult 670 0.01% 45.26% # attempts to use FU when none available
1904system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.26% # attempts to use FU when none available
1905system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.26% # attempts to use FU when none available
1906system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.26% # attempts to use FU when none available
1907system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.26% # attempts to use FU when none available
1908system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.26% # attempts to use FU when none available
1909system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.26% # attempts to use FU when none available
1910system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.26% # attempts to use FU when none available
1911system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.26% # attempts to use FU when none available
1912system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.26% # attempts to use FU when none available
1913system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.26% # attempts to use FU when none available
1914system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.26% # attempts to use FU when none available
1915system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.26% # attempts to use FU when none available
1916system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.26% # attempts to use FU when none available
1917system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.26% # attempts to use FU when none available
1918system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.26% # attempts to use FU when none available
1919system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.26% # attempts to use FU when none available
1920system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.26% # attempts to use FU when none available
1921system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.26% # attempts to use FU when none available
1922system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.26% # attempts to use FU when none available
1923system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.26% # attempts to use FU when none available
1924system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.26% # attempts to use FU when none available
1925system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.26% # attempts to use FU when none available
1926system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.26% # attempts to use FU when none available
1927system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.26% # attempts to use FU when none available
1928system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.26% # attempts to use FU when none available
1929system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.26% # attempts to use FU when none available
1930system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.26% # attempts to use FU when none available
1931system.cpu1.iq.fu_full::MemRead 1685952 25.93% 71.19% # attempts to use FU when none available
1932system.cpu1.iq.fu_full::MemWrite 1873492 28.81% 100.00% # attempts to use FU when none available
1933system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1934system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1935system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued
1936system.cpu1.iq.FU_type_0::IntAlu 36944686 68.20% 68.20% # Type of FU issued
1937system.cpu1.iq.FU_type_0::IntMult 46486 0.09% 68.28% # Type of FU issued
1938system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.28% # Type of FU issued
1939system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.28% # Type of FU issued
1940system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.28% # Type of FU issued
1941system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.28% # Type of FU issued
1942system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.28% # Type of FU issued
1943system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.28% # Type of FU issued
1944system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.28% # Type of FU issued
1945system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.28% # Type of FU issued
1946system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.28% # Type of FU issued
1947system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.28% # Type of FU issued
1948system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.28% # Type of FU issued
1949system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.28% # Type of FU issued
1950system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.28% # Type of FU issued
1951system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.28% # Type of FU issued
1952system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.28% # Type of FU issued
1953system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.28% # Type of FU issued
1954system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.28% # Type of FU issued
1955system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.28% # Type of FU issued
1956system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.28% # Type of FU issued
1957system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.28% # Type of FU issued
1958system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.28% # Type of FU issued
1959system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.28% # Type of FU issued
1960system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.28% # Type of FU issued
1961system.cpu1.iq.FU_type_0::SimdFloatMisc 3329 0.01% 68.29% # Type of FU issued
1962system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.29% # Type of FU issued
1963system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.29% # Type of FU issued
1964system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.29% # Type of FU issued
1965system.cpu1.iq.FU_type_0::MemRead 10429510 19.25% 87.54% # Type of FU issued
1966system.cpu1.iq.FU_type_0::MemWrite 6750946 12.46% 100.00% # Type of FU issued
1967system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1968system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1969system.cpu1.iq.FU_type_0::total 54175023 # Type of FU issued
1970system.cpu1.iq.rate 0.508472 # Inst issue rate
1971system.cpu1.iq.fu_busy_cnt 6501871 # FU busy when requested
1972system.cpu1.iq.fu_busy_rate 0.120016 # FU busy rate (busy events/executed inst)
1973system.cpu1.iq.int_inst_queue_reads 220722500 # Number of integer instruction queue reads
1974system.cpu1.iq.int_inst_queue_writes 58678222 # Number of integer instruction queue writes
1975system.cpu1.iq.int_inst_queue_wakeup_accesses 52198206 # Number of integer instruction queue wakeup accesses
1976system.cpu1.iq.fp_inst_queue_reads 5973 # Number of floating instruction queue reads
1977system.cpu1.iq.fp_inst_queue_writes 2102 # Number of floating instruction queue writes
1978system.cpu1.iq.fp_inst_queue_wakeup_accesses 1789 # Number of floating instruction queue wakeup accesses
1979system.cpu1.iq.int_alu_accesses 60672989 # Number of integer alu accesses
1980system.cpu1.iq.fp_alu_accesses 3839 # Number of floating point alu accesses
1981system.cpu1.iew.lsq.thread0.forwLoads 91219 # Number of loads that had data forwarded from stores
1982system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1983system.cpu1.iew.lsq.thread0.squashedLoads 444760 # Number of loads squashed
1984system.cpu1.iew.lsq.thread0.ignoredResponses 748 # Number of memory responses ignored because the instruction is squashed
1985system.cpu1.iew.lsq.thread0.memOrderViolation 10369 # Number of memory ordering violations
1986system.cpu1.iew.lsq.thread0.squashedStores 281379 # Number of stores squashed
1987system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1988system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1989system.cpu1.iew.lsq.thread0.rescheduledLoads 52226 # Number of loads that were rescheduled
1990system.cpu1.iew.lsq.thread0.cacheBlocked 78419 # Number of times an access to memory failed due to the cache being blocked
1991system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1992system.cpu1.iew.iewSquashCycles 1750799 # Number of cycles IEW is squashing
1993system.cpu1.iew.iewBlockCycles 547306 # Number of cycles IEW is blocking
1994system.cpu1.iew.iewUnblockCycles 107318 # Number of cycles IEW is unblocking
1995system.cpu1.iew.iewDispatchedInsts 55048106 # Number of instructions dispatched to IQ
1996system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
1997system.cpu1.iew.iewDispLoadInsts 10477180 # Number of dispatched load instructions
1998system.cpu1.iew.iewDispStoreInsts 6893389 # Number of dispatched store instructions
1999system.cpu1.iew.iewDispNonSpecInsts 299581 # Number of dispatched non-speculative instructions
2000system.cpu1.iew.iewIQFullEvents 8072 # Number of times the IQ has become full, causing a stall
2001system.cpu1.iew.iewLSQFullEvents 92519 # Number of times the LSQ has become full, causing a stall
2002system.cpu1.iew.memOrderViolationEvents 10369 # Number of memory order violations
2003system.cpu1.iew.predictedTakenIncorrect 45476 # Number of branches that were predicted taken incorrectly
2004system.cpu1.iew.predictedNotTakenIncorrect 122774 # Number of branches that were predicted not taken incorrectly
2005system.cpu1.iew.branchMispredicts 168250 # Number of branch mispredicts detected at execute
2006system.cpu1.iew.iewExecutedInsts 53925594 # Number of executed instructions
2007system.cpu1.iew.iewExecLoadInsts 10330118 # Number of load instructions executed
2008system.cpu1.iew.iewExecSquashedInsts 227431 # Number of squashed instructions skipped in execute
2009system.cpu1.iew.exec_swp 0 # number of swp insts executed
2010system.cpu1.iew.exec_nop 40890 # number of nop insts executed
2011system.cpu1.iew.exec_refs 17028825 # number of memory reference insts executed
2012system.cpu1.iew.exec_branches 11888375 # Number of branches executed
2013system.cpu1.iew.exec_stores 6698707 # Number of stores executed
2014system.cpu1.iew.exec_rate 0.506131 # Inst execution rate
2015system.cpu1.iew.wb_sent 53782194 # cumulative count of insts sent to commit
2016system.cpu1.iew.wb_count 52199995 # cumulative count of insts written-back
2017system.cpu1.iew.wb_producers 25393405 # num instructions producing a value
2018system.cpu1.iew.wb_consumers 38775074 # num instructions consuming a value
2019system.cpu1.iew.wb_rate 0.489935 # insts written-back per cycle
2020system.cpu1.iew.wb_fanout 0.654890 # average fanout of values written-back
2021system.cpu1.commit.commitSquashedInsts 3417074 # The number of squashed insts skipped by commit
2022system.cpu1.commit.commitNonSpecStalls 542844 # The number of times commit has been forced to stall to communicate backwards
2023system.cpu1.commit.branchMispredicts 157272 # The number of times a branch was mispredicted
2024system.cpu1.commit.committed_per_cycle::samples 103878319 # Number of insts commited each cycle
2025system.cpu1.commit.committed_per_cycle::mean 0.494591 # Number of insts commited each cycle
2026system.cpu1.commit.committed_per_cycle::stdev 1.150147 # Number of insts commited each cycle
2027system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2028system.cpu1.commit.committed_per_cycle::0 77963106 75.05% 75.05% # Number of insts commited each cycle
2029system.cpu1.commit.committed_per_cycle::1 14542376 14.00% 89.05% # Number of insts commited each cycle
2030system.cpu1.commit.committed_per_cycle::2 6113605 5.89% 94.94% # Number of insts commited each cycle
2031system.cpu1.commit.committed_per_cycle::3 710011 0.68% 95.62% # Number of insts commited each cycle
2032system.cpu1.commit.committed_per_cycle::4 1999110 1.92% 97.55% # Number of insts commited each cycle
2033system.cpu1.commit.committed_per_cycle::5 1749013 1.68% 99.23% # Number of insts commited each cycle
2034system.cpu1.commit.committed_per_cycle::6 272868 0.26% 99.49% # Number of insts commited each cycle
2035system.cpu1.commit.committed_per_cycle::7 126868 0.12% 99.61% # Number of insts commited each cycle
2036system.cpu1.commit.committed_per_cycle::8 401362 0.39% 100.00% # Number of insts commited each cycle
2037system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2038system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2039system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2040system.cpu1.commit.committed_per_cycle::total 103878319 # Number of insts commited each cycle
2041system.cpu1.commit.committedInsts 41730387 # Number of instructions committed
2042system.cpu1.commit.committedOps 51377304 # Number of ops (including micro ops) committed
2043system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2044system.cpu1.commit.refs 16644430 # Number of memory references committed
2045system.cpu1.commit.loads 10032420 # Number of loads committed
2046system.cpu1.commit.membars 210881 # Number of memory barriers committed
2047system.cpu1.commit.branches 11730295 # Number of branches committed
2048system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions.
2049system.cpu1.commit.int_insts 46164743 # Number of committed integer instructions.
2050system.cpu1.commit.function_calls 3380868 # Number of function calls committed.
2051system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2052system.cpu1.commit.op_class_0::IntAlu 34684147 67.51% 67.51% # Class of committed instruction
2053system.cpu1.commit.op_class_0::IntMult 45398 0.09% 67.60% # Class of committed instruction
2054system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.60% # Class of committed instruction
2055system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.60% # Class of committed instruction
2056system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.60% # Class of committed instruction
2057system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.60% # Class of committed instruction
2058system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.60% # Class of committed instruction
2059system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.60% # Class of committed instruction
2060system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.60% # Class of committed instruction
2061system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.60% # Class of committed instruction
2062system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.60% # Class of committed instruction
2063system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.60% # Class of committed instruction
2064system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.60% # Class of committed instruction
2065system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.60% # Class of committed instruction
2066system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.60% # Class of committed instruction
2067system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.60% # Class of committed instruction
2068system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.60% # Class of committed instruction
2069system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.60% # Class of committed instruction
2070system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.60% # Class of committed instruction
2071system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.60% # Class of committed instruction
2072system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.60% # Class of committed instruction
2073system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.60% # Class of committed instruction
2074system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.60% # Class of committed instruction
2075system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.60% # Class of committed instruction
2076system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.60% # Class of committed instruction
2077system.cpu1.commit.op_class_0::SimdFloatMisc 3329 0.01% 67.60% # Class of committed instruction
2078system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.60% # Class of committed instruction
2079system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.60% # Class of committed instruction
2080system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.60% # Class of committed instruction
2081system.cpu1.commit.op_class_0::MemRead 10032420 19.53% 87.13% # Class of committed instruction
2082system.cpu1.commit.op_class_0::MemWrite 6612010 12.87% 100.00% # Class of committed instruction
2083system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2084system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2085system.cpu1.commit.op_class_0::total 51377304 # Class of committed instruction
2086system.cpu1.commit.bw_lim_events 401362 # number cycles where commit BW limit reached
2087system.cpu1.rob.rob_reads 138158228 # The number of ROB reads
2088system.cpu1.rob.rob_writes 111482281 # The number of ROB writes
2089system.cpu1.timesIdled 55620 # Number of times that the entire CPU went into an idle state and unscheduled itself
2090system.cpu1.idleCycles 764182 # Total number of cycles that the CPU has spent unscheduled due to idling
2091system.cpu1.quiesceCycles 5544797786 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2092system.cpu1.committedInsts 41697532 # Number of Instructions Simulated
2093system.cpu1.committedOps 51344449 # Number of Ops (including micro ops) Simulated
2094system.cpu1.cpi 2.555182 # CPI: Cycles Per Instruction
2095system.cpu1.cpi_total 2.555182 # CPI: Total CPI of All Threads
2096system.cpu1.ipc 0.391362 # IPC: Instructions Per Cycle
2097system.cpu1.ipc_total 0.391362 # IPC: Total IPC of All Threads
2098system.cpu1.int_regfile_reads 56568285 # number of integer regfile reads
2099system.cpu1.int_regfile_writes 35909809 # number of integer regfile writes
2100system.cpu1.fp_regfile_reads 1388 # number of floating regfile reads
2101system.cpu1.fp_regfile_writes 516 # number of floating regfile writes
2102system.cpu1.cc_regfile_reads 192177585 # number of cc regfile reads
2103system.cpu1.cc_regfile_writes 15728126 # number of cc regfile writes
2104system.cpu1.misc_regfile_reads 146901400 # number of misc regfile reads
2105system.cpu1.misc_regfile_writes 390692 # number of misc regfile writes
2106system.cpu1.dcache.tags.replacements 191412 # number of replacements
2107system.cpu1.dcache.tags.tagsinuse 467.958660 # Cycle average of tags in use
2108system.cpu1.dcache.tags.total_refs 15830019 # Total number of references to valid blocks.
2109system.cpu1.dcache.tags.sampled_refs 191751 # Sample count of references to valid blocks.
2110system.cpu1.dcache.tags.avg_refs 82.555079 # Average number of references to valid blocks.
2111system.cpu1.dcache.tags.warmup_cycle 89229031500 # Cycle when the warmup percentage was hit.
2112system.cpu1.dcache.tags.occ_blocks::cpu1.data 467.958660 # Average occupied blocks per requestor
2113system.cpu1.dcache.tags.occ_percent::cpu1.data 0.913982 # Average percentage of cache occupancy
2114system.cpu1.dcache.tags.occ_percent::total 0.913982 # Average percentage of cache occupancy
2115system.cpu1.dcache.tags.occ_task_id_blocks::1024 339 # Occupied blocks per task id
2116system.cpu1.dcache.tags.age_task_id_blocks_1024::2 338 # Occupied blocks per task id
2117system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
2118system.cpu1.dcache.tags.occ_task_id_percent::1024 0.662109 # Percentage of cache occupancy per task id
2119system.cpu1.dcache.tags.tag_accesses 33166441 # Number of tag accesses
2120system.cpu1.dcache.tags.data_accesses 33166441 # Number of data accesses
2121system.cpu1.dcache.ReadReq_hits::cpu1.data 9618480 # number of ReadReq hits
2122system.cpu1.dcache.ReadReq_hits::total 9618480 # number of ReadReq hits
2123system.cpu1.dcache.WriteReq_hits::cpu1.data 5953541 # number of WriteReq hits
2124system.cpu1.dcache.WriteReq_hits::total 5953541 # number of WriteReq hits
2125system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50151 # number of SoftPFReq hits
2126system.cpu1.dcache.SoftPFReq_hits::total 50151 # number of SoftPFReq hits
2127system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79497 # number of LoadLockedReq hits
2128system.cpu1.dcache.LoadLockedReq_hits::total 79497 # number of LoadLockedReq hits
2129system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71560 # number of StoreCondReq hits
2130system.cpu1.dcache.StoreCondReq_hits::total 71560 # number of StoreCondReq hits
2131system.cpu1.dcache.demand_hits::cpu1.data 15572021 # number of demand (read+write) hits
2132system.cpu1.dcache.demand_hits::total 15572021 # number of demand (read+write) hits
2133system.cpu1.dcache.overall_hits::cpu1.data 15622172 # number of overall hits
2134system.cpu1.dcache.overall_hits::total 15622172 # number of overall hits
2135system.cpu1.dcache.ReadReq_misses::cpu1.data 219751 # number of ReadReq misses
2136system.cpu1.dcache.ReadReq_misses::total 219751 # number of ReadReq misses
2137system.cpu1.dcache.WriteReq_misses::cpu1.data 400027 # number of WriteReq misses
2138system.cpu1.dcache.WriteReq_misses::total 400027 # number of WriteReq misses
2139system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30362 # number of SoftPFReq misses
2140system.cpu1.dcache.SoftPFReq_misses::total 30362 # number of SoftPFReq misses
2141system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18466 # number of LoadLockedReq misses
2142system.cpu1.dcache.LoadLockedReq_misses::total 18466 # number of LoadLockedReq misses
2143system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23631 # number of StoreCondReq misses
2144system.cpu1.dcache.StoreCondReq_misses::total 23631 # number of StoreCondReq misses
2145system.cpu1.dcache.demand_misses::cpu1.data 619778 # number of demand (read+write) misses
2146system.cpu1.dcache.demand_misses::total 619778 # number of demand (read+write) misses
2147system.cpu1.dcache.overall_misses::cpu1.data 650140 # number of overall misses
2148system.cpu1.dcache.overall_misses::total 650140 # number of overall misses
2149system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3494026000 # number of ReadReq miss cycles
2150system.cpu1.dcache.ReadReq_miss_latency::total 3494026000 # number of ReadReq miss cycles
2151system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9769416956 # number of WriteReq miss cycles
2152system.cpu1.dcache.WriteReq_miss_latency::total 9769416956 # number of WriteReq miss cycles
2153system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 360558000 # number of LoadLockedReq miss cycles
2154system.cpu1.dcache.LoadLockedReq_miss_latency::total 360558000 # number of LoadLockedReq miss cycles
2155system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 577732000 # number of StoreCondReq miss cycles
2156system.cpu1.dcache.StoreCondReq_miss_latency::total 577732000 # number of StoreCondReq miss cycles
2157system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 853500 # number of StoreCondFailReq miss cycles
2158system.cpu1.dcache.StoreCondFailReq_miss_latency::total 853500 # number of StoreCondFailReq miss cycles
2159system.cpu1.dcache.demand_miss_latency::cpu1.data 13263442956 # number of demand (read+write) miss cycles
2160system.cpu1.dcache.demand_miss_latency::total 13263442956 # number of demand (read+write) miss cycles
2161system.cpu1.dcache.overall_miss_latency::cpu1.data 13263442956 # number of overall miss cycles
2162system.cpu1.dcache.overall_miss_latency::total 13263442956 # number of overall miss cycles
2163system.cpu1.dcache.ReadReq_accesses::cpu1.data 9838231 # number of ReadReq accesses(hits+misses)
2164system.cpu1.dcache.ReadReq_accesses::total 9838231 # number of ReadReq accesses(hits+misses)
2165system.cpu1.dcache.WriteReq_accesses::cpu1.data 6353568 # number of WriteReq accesses(hits+misses)
2166system.cpu1.dcache.WriteReq_accesses::total 6353568 # number of WriteReq accesses(hits+misses)
2167system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80513 # number of SoftPFReq accesses(hits+misses)
2168system.cpu1.dcache.SoftPFReq_accesses::total 80513 # number of SoftPFReq accesses(hits+misses)
2169system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97963 # number of LoadLockedReq accesses(hits+misses)
2170system.cpu1.dcache.LoadLockedReq_accesses::total 97963 # number of LoadLockedReq accesses(hits+misses)
2171system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95191 # number of StoreCondReq accesses(hits+misses)
2172system.cpu1.dcache.StoreCondReq_accesses::total 95191 # number of StoreCondReq accesses(hits+misses)
2173system.cpu1.dcache.demand_accesses::cpu1.data 16191799 # number of demand (read+write) accesses
2174system.cpu1.dcache.demand_accesses::total 16191799 # number of demand (read+write) accesses
2175system.cpu1.dcache.overall_accesses::cpu1.data 16272312 # number of overall (read+write) accesses
2176system.cpu1.dcache.overall_accesses::total 16272312 # number of overall (read+write) accesses
2177system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022336 # miss rate for ReadReq accesses
2178system.cpu1.dcache.ReadReq_miss_rate::total 0.022336 # miss rate for ReadReq accesses
2179system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.062961 # miss rate for WriteReq accesses
2180system.cpu1.dcache.WriteReq_miss_rate::total 0.062961 # miss rate for WriteReq accesses
2181system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377107 # miss rate for SoftPFReq accesses
2182system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377107 # miss rate for SoftPFReq accesses
2183system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.188500 # miss rate for LoadLockedReq accesses
2184system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.188500 # miss rate for LoadLockedReq accesses
2185system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248248 # miss rate for StoreCondReq accesses
2186system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248248 # miss rate for StoreCondReq accesses
2187system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038277 # miss rate for demand accesses
2188system.cpu1.dcache.demand_miss_rate::total 0.038277 # miss rate for demand accesses
2189system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039954 # miss rate for overall accesses
2190system.cpu1.dcache.overall_miss_rate::total 0.039954 # miss rate for overall accesses
2191system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15899.932196 # average ReadReq miss latency
2192system.cpu1.dcache.ReadReq_avg_miss_latency::total 15899.932196 # average ReadReq miss latency
2193system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24421.893912 # average WriteReq miss latency
2194system.cpu1.dcache.WriteReq_avg_miss_latency::total 24421.893912 # average WriteReq miss latency
2195system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19525.506336 # average LoadLockedReq miss latency
2196system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19525.506336 # average LoadLockedReq miss latency
2197system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24448.055520 # average StoreCondReq miss latency
2198system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24448.055520 # average StoreCondReq miss latency
2199system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
2200system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2201system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21400.312622 # average overall miss latency
2202system.cpu1.dcache.demand_avg_miss_latency::total 21400.312622 # average overall miss latency
2203system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20400.902815 # average overall miss latency
2204system.cpu1.dcache.overall_avg_miss_latency::total 20400.902815 # average overall miss latency
2205system.cpu1.dcache.blocked_cycles::no_mshrs 349 # number of cycles access was blocked
2206system.cpu1.dcache.blocked_cycles::no_targets 1422803 # number of cycles access was blocked
2207system.cpu1.dcache.blocked::no_mshrs 30 # number of cycles access was blocked
2208system.cpu1.dcache.blocked::no_targets 40164 # number of cycles access was blocked
2209system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.633333 # average number of cycles each access was blocked
2210system.cpu1.dcache.avg_blocked_cycles::no_targets 35.424833 # average number of cycles each access was blocked
2211system.cpu1.dcache.writebacks::writebacks 191413 # number of writebacks
2212system.cpu1.dcache.writebacks::total 191413 # number of writebacks
2213system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 80045 # number of ReadReq MSHR hits
2214system.cpu1.dcache.ReadReq_mshr_hits::total 80045 # number of ReadReq MSHR hits
2215system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 309351 # number of WriteReq MSHR hits
2216system.cpu1.dcache.WriteReq_mshr_hits::total 309351 # number of WriteReq MSHR hits
2217system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13126 # number of LoadLockedReq MSHR hits
2218system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13126 # number of LoadLockedReq MSHR hits
2219system.cpu1.dcache.demand_mshr_hits::cpu1.data 389396 # number of demand (read+write) MSHR hits
2220system.cpu1.dcache.demand_mshr_hits::total 389396 # number of demand (read+write) MSHR hits
2221system.cpu1.dcache.overall_mshr_hits::cpu1.data 389396 # number of overall MSHR hits
2222system.cpu1.dcache.overall_mshr_hits::total 389396 # number of overall MSHR hits
2223system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139706 # number of ReadReq MSHR misses
2224system.cpu1.dcache.ReadReq_mshr_misses::total 139706 # number of ReadReq MSHR misses
2225system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90676 # number of WriteReq MSHR misses
2226system.cpu1.dcache.WriteReq_mshr_misses::total 90676 # number of WriteReq MSHR misses
2227system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28955 # number of SoftPFReq MSHR misses
2228system.cpu1.dcache.SoftPFReq_mshr_misses::total 28955 # number of SoftPFReq MSHR misses
2229system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5340 # number of LoadLockedReq MSHR misses
2230system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5340 # number of LoadLockedReq MSHR misses
2231system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23631 # number of StoreCondReq MSHR misses
2232system.cpu1.dcache.StoreCondReq_mshr_misses::total 23631 # number of StoreCondReq MSHR misses
2233system.cpu1.dcache.demand_mshr_misses::cpu1.data 230382 # number of demand (read+write) MSHR misses
2234system.cpu1.dcache.demand_mshr_misses::total 230382 # number of demand (read+write) MSHR misses
2235system.cpu1.dcache.overall_mshr_misses::cpu1.data 259337 # number of overall MSHR misses
2236system.cpu1.dcache.overall_mshr_misses::total 259337 # number of overall MSHR misses
2237system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14528 # number of ReadReq MSHR uncacheable
2238system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14528 # number of ReadReq MSHR uncacheable
2239system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11864 # number of WriteReq MSHR uncacheable
2240system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11864 # number of WriteReq MSHR uncacheable
2241system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26392 # number of overall MSHR uncacheable misses
2242system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26392 # number of overall MSHR uncacheable misses
2243system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1929657000 # number of ReadReq MSHR miss cycles
2244system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1929657000 # number of ReadReq MSHR miss cycles
2245system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2407624467 # number of WriteReq MSHR miss cycles
2246system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2407624467 # number of WriteReq MSHR miss cycles
2247system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 488405000 # number of SoftPFReq MSHR miss cycles
2248system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 488405000 # number of SoftPFReq MSHR miss cycles
2249system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91592000 # number of LoadLockedReq MSHR miss cycles
2250system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91592000 # number of LoadLockedReq MSHR miss cycles
2251system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 554116000 # number of StoreCondReq MSHR miss cycles
2252system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 554116000 # number of StoreCondReq MSHR miss cycles
2253system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 838500 # number of StoreCondFailReq MSHR miss cycles
2254system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 838500 # number of StoreCondFailReq MSHR miss cycles
2255system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4337281467 # number of demand (read+write) MSHR miss cycles
2256system.cpu1.dcache.demand_mshr_miss_latency::total 4337281467 # number of demand (read+write) MSHR miss cycles
2257system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4825686467 # number of overall MSHR miss cycles
2258system.cpu1.dcache.overall_mshr_miss_latency::total 4825686467 # number of overall MSHR miss cycles
2259system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2529035000 # number of ReadReq MSHR uncacheable cycles
2260system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2529035000 # number of ReadReq MSHR uncacheable cycles
2261system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2529035000 # number of overall MSHR uncacheable cycles
2262system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2529035000 # number of overall MSHR uncacheable cycles
2263system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014200 # mshr miss rate for ReadReq accesses
2264system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014200 # mshr miss rate for ReadReq accesses
2265system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014272 # mshr miss rate for WriteReq accesses
2266system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014272 # mshr miss rate for WriteReq accesses
2267system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359631 # mshr miss rate for SoftPFReq accesses
2268system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359631 # mshr miss rate for SoftPFReq accesses
2269system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054510 # mshr miss rate for LoadLockedReq accesses
2270system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054510 # mshr miss rate for LoadLockedReq accesses
2271system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248248 # mshr miss rate for StoreCondReq accesses
2272system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248248 # mshr miss rate for StoreCondReq accesses
2273system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014228 # mshr miss rate for demand accesses
2274system.cpu1.dcache.demand_mshr_miss_rate::total 0.014228 # mshr miss rate for demand accesses
2275system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015937 # mshr miss rate for overall accesses
2276system.cpu1.dcache.overall_mshr_miss_rate::total 0.015937 # mshr miss rate for overall accesses
2277system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13812.270053 # average ReadReq mshr miss latency
2278system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13812.270053 # average ReadReq mshr miss latency
2279system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26551.948333 # average WriteReq mshr miss latency
2280system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26551.948333 # average WriteReq mshr miss latency
2281system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16867.725781 # average SoftPFReq mshr miss latency
2282system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16867.725781 # average SoftPFReq mshr miss latency
2283system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17152.059925 # average LoadLockedReq mshr miss latency
2284system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17152.059925 # average LoadLockedReq mshr miss latency
2285system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23448.690280 # average StoreCondReq mshr miss latency
2286system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23448.690280 # average StoreCondReq mshr miss latency
2287system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
2288system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2289system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18826.477186 # average overall mshr miss latency
2290system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18826.477186 # average overall mshr miss latency
2291system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18607.782411 # average overall mshr miss latency
2292system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18607.782411 # average overall mshr miss latency
2293system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174080.052313 # average ReadReq mshr uncacheable latency
2294system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174080.052313 # average ReadReq mshr uncacheable latency
2295system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95825.818430 # average overall mshr uncacheable latency
2296system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95825.818430 # average overall mshr uncacheable latency
2297system.cpu1.icache.tags.replacements 601488 # number of replacements
2298system.cpu1.icache.tags.tagsinuse 499.448304 # Cycle average of tags in use
2299system.cpu1.icache.tags.total_refs 43094812 # Total number of references to valid blocks.
2300system.cpu1.icache.tags.sampled_refs 602000 # Sample count of references to valid blocks.
2301system.cpu1.icache.tags.avg_refs 71.586066 # Average number of references to valid blocks.
2302system.cpu1.icache.tags.warmup_cycle 79058224000 # Cycle when the warmup percentage was hit.
2303system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.448304 # Average occupied blocks per requestor
2304system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975485 # Average percentage of cache occupancy
2305system.cpu1.icache.tags.occ_percent::total 0.975485 # Average percentage of cache occupancy
2306system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2307system.cpu1.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id
2308system.cpu1.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id
2309system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2310system.cpu1.icache.tags.tag_accesses 88040802 # Number of tag accesses
2311system.cpu1.icache.tags.data_accesses 88040802 # Number of data accesses
2312system.cpu1.icache.ReadReq_hits::cpu1.inst 43094812 # number of ReadReq hits
2313system.cpu1.icache.ReadReq_hits::total 43094812 # number of ReadReq hits
2314system.cpu1.icache.demand_hits::cpu1.inst 43094812 # number of demand (read+write) hits
2315system.cpu1.icache.demand_hits::total 43094812 # number of demand (read+write) hits
2316system.cpu1.icache.overall_hits::cpu1.inst 43094812 # number of overall hits
2317system.cpu1.icache.overall_hits::total 43094812 # number of overall hits
2318system.cpu1.icache.ReadReq_misses::cpu1.inst 624586 # number of ReadReq misses
2319system.cpu1.icache.ReadReq_misses::total 624586 # number of ReadReq misses
2320system.cpu1.icache.demand_misses::cpu1.inst 624586 # number of demand (read+write) misses
2321system.cpu1.icache.demand_misses::total 624586 # number of demand (read+write) misses
2322system.cpu1.icache.overall_misses::cpu1.inst 624586 # number of overall misses
2323system.cpu1.icache.overall_misses::total 624586 # number of overall misses
2324system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5619455793 # number of ReadReq miss cycles
2325system.cpu1.icache.ReadReq_miss_latency::total 5619455793 # number of ReadReq miss cycles
2326system.cpu1.icache.demand_miss_latency::cpu1.inst 5619455793 # number of demand (read+write) miss cycles
2327system.cpu1.icache.demand_miss_latency::total 5619455793 # number of demand (read+write) miss cycles
2328system.cpu1.icache.overall_miss_latency::cpu1.inst 5619455793 # number of overall miss cycles
2329system.cpu1.icache.overall_miss_latency::total 5619455793 # number of overall miss cycles
2330system.cpu1.icache.ReadReq_accesses::cpu1.inst 43719398 # number of ReadReq accesses(hits+misses)
2331system.cpu1.icache.ReadReq_accesses::total 43719398 # number of ReadReq accesses(hits+misses)
2332system.cpu1.icache.demand_accesses::cpu1.inst 43719398 # number of demand (read+write) accesses
2333system.cpu1.icache.demand_accesses::total 43719398 # number of demand (read+write) accesses
2334system.cpu1.icache.overall_accesses::cpu1.inst 43719398 # number of overall (read+write) accesses
2335system.cpu1.icache.overall_accesses::total 43719398 # number of overall (read+write) accesses
2336system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014286 # miss rate for ReadReq accesses
2337system.cpu1.icache.ReadReq_miss_rate::total 0.014286 # miss rate for ReadReq accesses
2338system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014286 # miss rate for demand accesses
2339system.cpu1.icache.demand_miss_rate::total 0.014286 # miss rate for demand accesses
2340system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014286 # miss rate for overall accesses
2341system.cpu1.icache.overall_miss_rate::total 0.014286 # miss rate for overall accesses
2342system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8997.088941 # average ReadReq miss latency
2343system.cpu1.icache.ReadReq_avg_miss_latency::total 8997.088941 # average ReadReq miss latency
2344system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8997.088941 # average overall miss latency
2345system.cpu1.icache.demand_avg_miss_latency::total 8997.088941 # average overall miss latency
2346system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8997.088941 # average overall miss latency
2347system.cpu1.icache.overall_avg_miss_latency::total 8997.088941 # average overall miss latency
2348system.cpu1.icache.blocked_cycles::no_mshrs 497106 # number of cycles access was blocked
2349system.cpu1.icache.blocked_cycles::no_targets 2 # number of cycles access was blocked
2350system.cpu1.icache.blocked::no_mshrs 41763 # number of cycles access was blocked
2351system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
2352system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.903024 # average number of cycles each access was blocked
2353system.cpu1.icache.avg_blocked_cycles::no_targets 2 # average number of cycles each access was blocked
2354system.cpu1.icache.writebacks::writebacks 601488 # number of writebacks
2355system.cpu1.icache.writebacks::total 601488 # number of writebacks
2356system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22580 # number of ReadReq MSHR hits
2357system.cpu1.icache.ReadReq_mshr_hits::total 22580 # number of ReadReq MSHR hits
2358system.cpu1.icache.demand_mshr_hits::cpu1.inst 22580 # number of demand (read+write) MSHR hits
2359system.cpu1.icache.demand_mshr_hits::total 22580 # number of demand (read+write) MSHR hits
2360system.cpu1.icache.overall_mshr_hits::cpu1.inst 22580 # number of overall MSHR hits
2361system.cpu1.icache.overall_mshr_hits::total 22580 # number of overall MSHR hits
2362system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 602006 # number of ReadReq MSHR misses
2363system.cpu1.icache.ReadReq_mshr_misses::total 602006 # number of ReadReq MSHR misses
2364system.cpu1.icache.demand_mshr_misses::cpu1.inst 602006 # number of demand (read+write) MSHR misses
2365system.cpu1.icache.demand_mshr_misses::total 602006 # number of demand (read+write) MSHR misses
2366system.cpu1.icache.overall_mshr_misses::cpu1.inst 602006 # number of overall MSHR misses
2367system.cpu1.icache.overall_mshr_misses::total 602006 # number of overall MSHR misses
2368system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable
2369system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable
2370system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses
2371system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses
2372system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5157000587 # number of ReadReq MSHR miss cycles
2373system.cpu1.icache.ReadReq_mshr_miss_latency::total 5157000587 # number of ReadReq MSHR miss cycles
2374system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5157000587 # number of demand (read+write) MSHR miss cycles
2375system.cpu1.icache.demand_mshr_miss_latency::total 5157000587 # number of demand (read+write) MSHR miss cycles
2376system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5157000587 # number of overall MSHR miss cycles
2377system.cpu1.icache.overall_mshr_miss_latency::total 5157000587 # number of overall MSHR miss cycles
2378system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9463000 # number of ReadReq MSHR uncacheable cycles
2379system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9463000 # number of ReadReq MSHR uncacheable cycles
2380system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9463000 # number of overall MSHR uncacheable cycles
2381system.cpu1.icache.overall_mshr_uncacheable_latency::total 9463000 # number of overall MSHR uncacheable cycles
2382system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013770 # mshr miss rate for ReadReq accesses
2383system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013770 # mshr miss rate for ReadReq accesses
2384system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013770 # mshr miss rate for demand accesses
2385system.cpu1.icache.demand_mshr_miss_rate::total 0.013770 # mshr miss rate for demand accesses
2386system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013770 # mshr miss rate for overall accesses
2387system.cpu1.icache.overall_mshr_miss_rate::total 0.013770 # mshr miss rate for overall accesses
2388system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8566.360779 # average ReadReq mshr miss latency
2389system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8566.360779 # average ReadReq mshr miss latency
2390system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8566.360779 # average overall mshr miss latency
2391system.cpu1.icache.demand_avg_mshr_miss_latency::total 8566.360779 # average overall mshr miss latency
2392system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8566.360779 # average overall mshr miss latency
2393system.cpu1.icache.overall_avg_mshr_miss_latency::total 8566.360779 # average overall mshr miss latency
2394system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92774.509804 # average ReadReq mshr uncacheable latency
2395system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92774.509804 # average ReadReq mshr uncacheable latency
2396system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92774.509804 # average overall mshr uncacheable latency
2397system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92774.509804 # average overall mshr uncacheable latency
2398system.cpu1.l2cache.prefetcher.num_hwpf_issued 196563 # number of hwpf issued
2399system.cpu1.l2cache.prefetcher.pfIdentified 197115 # number of prefetch candidates identified
2400system.cpu1.l2cache.prefetcher.pfBufferHit 493 # number of redundant prefetches already in prefetch queue
2401system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
2402system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2403system.cpu1.l2cache.prefetcher.pfSpanPage 59469 # number of prefetches not generated due to page crossing
2404system.cpu1.l2cache.tags.replacements 47848 # number of replacements
2405system.cpu1.l2cache.tags.tagsinuse 15152.810983 # Cycle average of tags in use
2406system.cpu1.l2cache.tags.total_refs 1369588 # Total number of references to valid blocks.
2407system.cpu1.l2cache.tags.sampled_refs 62482 # Sample count of references to valid blocks.
2408system.cpu1.l2cache.tags.avg_refs 21.919721 # Average number of references to valid blocks.
2409system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2410system.cpu1.l2cache.tags.occ_blocks::writebacks 14657.752176 # Average occupied blocks per requestor
2411system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.247040 # Average occupied blocks per requestor
2412system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.961226 # Average occupied blocks per requestor
2413system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 482.850541 # Average occupied blocks per requestor
2414system.cpu1.l2cache.tags.occ_percent::writebacks 0.894638 # Average percentage of cache occupancy
2415system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000564 # Average percentage of cache occupancy
2416system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000181 # Average percentage of cache occupancy
2417system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.029471 # Average percentage of cache occupancy
2418system.cpu1.l2cache.tags.occ_percent::total 0.924854 # Average percentage of cache occupancy
2419system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1015 # Occupied blocks per task id
2420system.cpu1.l2cache.tags.occ_task_id_blocks::1023 31 # Occupied blocks per task id
2421system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13588 # Occupied blocks per task id
2422system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 15 # Occupied blocks per task id
2423system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 873 # Occupied blocks per task id
2424system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 127 # Occupied blocks per task id
2425system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id
2426system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id
2427system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
2428system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 454 # Occupied blocks per task id
2429system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8865 # Occupied blocks per task id
2430system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4269 # Occupied blocks per task id
2431system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.061951 # Percentage of cache occupancy per task id
2432system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001892 # Percentage of cache occupancy per task id
2433system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.829346 # Percentage of cache occupancy per task id
2434system.cpu1.l2cache.tags.tag_accesses 27297276 # Number of tag accesses
2435system.cpu1.l2cache.tags.data_accesses 27297276 # Number of data accesses
2436system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 17323 # number of ReadReq hits
2437system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6382 # number of ReadReq hits
2438system.cpu1.l2cache.ReadReq_hits::total 23705 # number of ReadReq hits
2439system.cpu1.l2cache.WritebackDirty_hits::writebacks 116494 # number of WritebackDirty hits
2440system.cpu1.l2cache.WritebackDirty_hits::total 116494 # number of WritebackDirty hits
2441system.cpu1.l2cache.WritebackClean_hits::writebacks 663845 # number of WritebackClean hits
2442system.cpu1.l2cache.WritebackClean_hits::total 663845 # number of WritebackClean hits
2443system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27330 # number of ReadExReq hits
2444system.cpu1.l2cache.ReadExReq_hits::total 27330 # number of ReadExReq hits
2445system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 585501 # number of ReadCleanReq hits
2446system.cpu1.l2cache.ReadCleanReq_hits::total 585501 # number of ReadCleanReq hits
2447system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 105069 # number of ReadSharedReq hits
2448system.cpu1.l2cache.ReadSharedReq_hits::total 105069 # number of ReadSharedReq hits
2449system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 17323 # number of demand (read+write) hits
2450system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6382 # number of demand (read+write) hits
2451system.cpu1.l2cache.demand_hits::cpu1.inst 585501 # number of demand (read+write) hits
2452system.cpu1.l2cache.demand_hits::cpu1.data 132399 # number of demand (read+write) hits
2453system.cpu1.l2cache.demand_hits::total 741605 # number of demand (read+write) hits
2454system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 17323 # number of overall hits
2455system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6382 # number of overall hits
2456system.cpu1.l2cache.overall_hits::cpu1.inst 585501 # number of overall hits
2457system.cpu1.l2cache.overall_hits::cpu1.data 132399 # number of overall hits
2458system.cpu1.l2cache.overall_hits::total 741605 # number of overall hits
2459system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 436 # number of ReadReq misses
2460system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 251 # number of ReadReq misses
2461system.cpu1.l2cache.ReadReq_misses::total 687 # number of ReadReq misses
2462system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29837 # number of UpgradeReq misses
2463system.cpu1.l2cache.UpgradeReq_misses::total 29837 # number of UpgradeReq misses
2464system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23628 # number of SCUpgradeReq misses
2465system.cpu1.l2cache.SCUpgradeReq_misses::total 23628 # number of SCUpgradeReq misses
2466system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses
2467system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
2468system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34183 # number of ReadExReq misses
2469system.cpu1.l2cache.ReadExReq_misses::total 34183 # number of ReadExReq misses
2470system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 16502 # number of ReadCleanReq misses
2471system.cpu1.l2cache.ReadCleanReq_misses::total 16502 # number of ReadCleanReq misses
2472system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 68911 # number of ReadSharedReq misses
2473system.cpu1.l2cache.ReadSharedReq_misses::total 68911 # number of ReadSharedReq misses
2474system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 436 # number of demand (read+write) misses
2475system.cpu1.l2cache.demand_misses::cpu1.itb.walker 251 # number of demand (read+write) misses
2476system.cpu1.l2cache.demand_misses::cpu1.inst 16502 # number of demand (read+write) misses
2477system.cpu1.l2cache.demand_misses::cpu1.data 103094 # number of demand (read+write) misses
2478system.cpu1.l2cache.demand_misses::total 120283 # number of demand (read+write) misses
2479system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 436 # number of overall misses
2480system.cpu1.l2cache.overall_misses::cpu1.itb.walker 251 # number of overall misses
2481system.cpu1.l2cache.overall_misses::cpu1.inst 16502 # number of overall misses
2482system.cpu1.l2cache.overall_misses::cpu1.data 103094 # number of overall misses
2483system.cpu1.l2cache.overall_misses::total 120283 # number of overall misses
2484system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9535000 # number of ReadReq miss cycles
2485system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5307000 # number of ReadReq miss cycles
2486system.cpu1.l2cache.ReadReq_miss_latency::total 14842000 # number of ReadReq miss cycles
2487system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 65279500 # number of UpgradeReq miss cycles
2488system.cpu1.l2cache.UpgradeReq_miss_latency::total 65279500 # number of UpgradeReq miss cycles
2489system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 35645500 # number of SCUpgradeReq miss cycles
2490system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 35645500 # number of SCUpgradeReq miss cycles
2491system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 815499 # number of SCUpgradeFailReq miss cycles
2492system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 815499 # number of SCUpgradeFailReq miss cycles
2493system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1382048000 # number of ReadExReq miss cycles
2494system.cpu1.l2cache.ReadExReq_miss_latency::total 1382048000 # number of ReadExReq miss cycles
2495system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 678918000 # number of ReadCleanReq miss cycles
2496system.cpu1.l2cache.ReadCleanReq_miss_latency::total 678918000 # number of ReadCleanReq miss cycles
2497system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1543279999 # number of ReadSharedReq miss cycles
2498system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1543279999 # number of ReadSharedReq miss cycles
2499system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9535000 # number of demand (read+write) miss cycles
2500system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5307000 # number of demand (read+write) miss cycles
2501system.cpu1.l2cache.demand_miss_latency::cpu1.inst 678918000 # number of demand (read+write) miss cycles
2502system.cpu1.l2cache.demand_miss_latency::cpu1.data 2925327999 # number of demand (read+write) miss cycles
2503system.cpu1.l2cache.demand_miss_latency::total 3619087999 # number of demand (read+write) miss cycles
2504system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9535000 # number of overall miss cycles
2505system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5307000 # number of overall miss cycles
2506system.cpu1.l2cache.overall_miss_latency::cpu1.inst 678918000 # number of overall miss cycles
2507system.cpu1.l2cache.overall_miss_latency::cpu1.data 2925327999 # number of overall miss cycles
2508system.cpu1.l2cache.overall_miss_latency::total 3619087999 # number of overall miss cycles
2509system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17759 # number of ReadReq accesses(hits+misses)
2510system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 6633 # number of ReadReq accesses(hits+misses)
2511system.cpu1.l2cache.ReadReq_accesses::total 24392 # number of ReadReq accesses(hits+misses)
2512system.cpu1.l2cache.WritebackDirty_accesses::writebacks 116494 # number of WritebackDirty accesses(hits+misses)
2513system.cpu1.l2cache.WritebackDirty_accesses::total 116494 # number of WritebackDirty accesses(hits+misses)
2514system.cpu1.l2cache.WritebackClean_accesses::writebacks 663845 # number of WritebackClean accesses(hits+misses)
2515system.cpu1.l2cache.WritebackClean_accesses::total 663845 # number of WritebackClean accesses(hits+misses)
2516system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29837 # number of UpgradeReq accesses(hits+misses)
2517system.cpu1.l2cache.UpgradeReq_accesses::total 29837 # number of UpgradeReq accesses(hits+misses)
2518system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23628 # number of SCUpgradeReq accesses(hits+misses)
2519system.cpu1.l2cache.SCUpgradeReq_accesses::total 23628 # number of SCUpgradeReq accesses(hits+misses)
2520system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
2521system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
2522system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61513 # number of ReadExReq accesses(hits+misses)
2523system.cpu1.l2cache.ReadExReq_accesses::total 61513 # number of ReadExReq accesses(hits+misses)
2524system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 602003 # number of ReadCleanReq accesses(hits+misses)
2525system.cpu1.l2cache.ReadCleanReq_accesses::total 602003 # number of ReadCleanReq accesses(hits+misses)
2526system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 173980 # number of ReadSharedReq accesses(hits+misses)
2527system.cpu1.l2cache.ReadSharedReq_accesses::total 173980 # number of ReadSharedReq accesses(hits+misses)
2528system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17759 # number of demand (read+write) accesses
2529system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 6633 # number of demand (read+write) accesses
2530system.cpu1.l2cache.demand_accesses::cpu1.inst 602003 # number of demand (read+write) accesses
2531system.cpu1.l2cache.demand_accesses::cpu1.data 235493 # number of demand (read+write) accesses
2532system.cpu1.l2cache.demand_accesses::total 861888 # number of demand (read+write) accesses
2533system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17759 # number of overall (read+write) accesses
2534system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 6633 # number of overall (read+write) accesses
2535system.cpu1.l2cache.overall_accesses::cpu1.inst 602003 # number of overall (read+write) accesses
2536system.cpu1.l2cache.overall_accesses::cpu1.data 235493 # number of overall (read+write) accesses
2537system.cpu1.l2cache.overall_accesses::total 861888 # number of overall (read+write) accesses
2538system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.024551 # miss rate for ReadReq accesses
2539system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.037841 # miss rate for ReadReq accesses
2540system.cpu1.l2cache.ReadReq_miss_rate::total 0.028165 # miss rate for ReadReq accesses
2541system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
2542system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
2543system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2544system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2545system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2546system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2547system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555704 # miss rate for ReadExReq accesses
2548system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555704 # miss rate for ReadExReq accesses
2549system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.027412 # miss rate for ReadCleanReq accesses
2550system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.027412 # miss rate for ReadCleanReq accesses
2551system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.396086 # miss rate for ReadSharedReq accesses
2552system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.396086 # miss rate for ReadSharedReq accesses
2553system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.024551 # miss rate for demand accesses
2554system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.037841 # miss rate for demand accesses
2555system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.027412 # miss rate for demand accesses
2556system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.437779 # miss rate for demand accesses
2557system.cpu1.l2cache.demand_miss_rate::total 0.139558 # miss rate for demand accesses
2558system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.024551 # miss rate for overall accesses
2559system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.037841 # miss rate for overall accesses
2560system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.027412 # miss rate for overall accesses
2561system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.437779 # miss rate for overall accesses
2562system.cpu1.l2cache.overall_miss_rate::total 0.139558 # miss rate for overall accesses
2563system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21869.266055 # average ReadReq miss latency
2564system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21143.426295 # average ReadReq miss latency
2565system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21604.075691 # average ReadReq miss latency
2566system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2187.870764 # average UpgradeReq miss latency
2567system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2187.870764 # average UpgradeReq miss latency
2568system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1508.612663 # average SCUpgradeReq miss latency
2569system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1508.612663 # average SCUpgradeReq miss latency
2570system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 271833 # average SCUpgradeFailReq miss latency
2571system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 271833 # average SCUpgradeFailReq miss latency
2572system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40430.857444 # average ReadExReq miss latency
2573system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40430.857444 # average ReadExReq miss latency
2574system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 41141.558599 # average ReadCleanReq miss latency
2575system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 41141.558599 # average ReadCleanReq miss latency
2576system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22395.263441 # average ReadSharedReq miss latency
2577system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22395.263441 # average ReadSharedReq miss latency
2578system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21869.266055 # average overall miss latency
2579system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21143.426295 # average overall miss latency
2580system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 41141.558599 # average overall miss latency
2581system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28375.346761 # average overall miss latency
2582system.cpu1.l2cache.demand_avg_miss_latency::total 30088.108868 # average overall miss latency
2583system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21869.266055 # average overall miss latency
2584system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21143.426295 # average overall miss latency
2585system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 41141.558599 # average overall miss latency
2586system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28375.346761 # average overall miss latency
2587system.cpu1.l2cache.overall_avg_miss_latency::total 30088.108868 # average overall miss latency
2588system.cpu1.l2cache.blocked_cycles::no_mshrs 77 # number of cycles access was blocked
2589system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2590system.cpu1.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked
2591system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2592system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 25.666667 # average number of cycles each access was blocked
2593system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2594system.cpu1.l2cache.unused_prefetches 878 # number of HardPF blocks evicted w/o reference
2595system.cpu1.l2cache.writebacks::writebacks 32705 # number of writebacks
2596system.cpu1.l2cache.writebacks::total 32705 # number of writebacks
2597system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 447 # number of ReadExReq MSHR hits
2598system.cpu1.l2cache.ReadExReq_mshr_hits::total 447 # number of ReadExReq MSHR hits
2599system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 9 # number of ReadCleanReq MSHR hits
2600system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits
2601system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 70 # number of ReadSharedReq MSHR hits
2602system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 70 # number of ReadSharedReq MSHR hits
2603system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits
2604system.cpu1.l2cache.demand_mshr_hits::cpu1.data 517 # number of demand (read+write) MSHR hits
2605system.cpu1.l2cache.demand_mshr_hits::total 526 # number of demand (read+write) MSHR hits
2606system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits
2607system.cpu1.l2cache.overall_mshr_hits::cpu1.data 517 # number of overall MSHR hits
2608system.cpu1.l2cache.overall_mshr_hits::total 526 # number of overall MSHR hits
2609system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 436 # number of ReadReq MSHR misses
2610system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 251 # number of ReadReq MSHR misses
2611system.cpu1.l2cache.ReadReq_mshr_misses::total 687 # number of ReadReq MSHR misses
2612system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25391 # number of HardPFReq MSHR misses
2613system.cpu1.l2cache.HardPFReq_mshr_misses::total 25391 # number of HardPFReq MSHR misses
2614system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29837 # number of UpgradeReq MSHR misses
2615system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29837 # number of UpgradeReq MSHR misses
2616system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23628 # number of SCUpgradeReq MSHR misses
2617system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23628 # number of SCUpgradeReq MSHR misses
2618system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses
2619system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
2620system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33736 # number of ReadExReq MSHR misses
2621system.cpu1.l2cache.ReadExReq_mshr_misses::total 33736 # number of ReadExReq MSHR misses
2622system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 16493 # number of ReadCleanReq MSHR misses
2623system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 16493 # number of ReadCleanReq MSHR misses
2624system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 68841 # number of ReadSharedReq MSHR misses
2625system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 68841 # number of ReadSharedReq MSHR misses
2626system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 436 # number of demand (read+write) MSHR misses
2627system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 251 # number of demand (read+write) MSHR misses
2628system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 16493 # number of demand (read+write) MSHR misses
2629system.cpu1.l2cache.demand_mshr_misses::cpu1.data 102577 # number of demand (read+write) MSHR misses
2630system.cpu1.l2cache.demand_mshr_misses::total 119757 # number of demand (read+write) MSHR misses
2631system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 436 # number of overall MSHR misses
2632system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 251 # number of overall MSHR misses
2633system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 16493 # number of overall MSHR misses
2634system.cpu1.l2cache.overall_mshr_misses::cpu1.data 102577 # number of overall MSHR misses
2635system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25391 # number of overall MSHR misses
2636system.cpu1.l2cache.overall_mshr_misses::total 145148 # number of overall MSHR misses
2637system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable
2638system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14528 # number of ReadReq MSHR uncacheable
2639system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14630 # number of ReadReq MSHR uncacheable
2640system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11864 # number of WriteReq MSHR uncacheable
2641system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11864 # number of WriteReq MSHR uncacheable
2642system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses
2643system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26392 # number of overall MSHR uncacheable misses
2644system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26494 # number of overall MSHR uncacheable misses
2645system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6919000 # number of ReadReq MSHR miss cycles
2646system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3801000 # number of ReadReq MSHR miss cycles
2647system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10720000 # number of ReadReq MSHR miss cycles
2648system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1003077137 # number of HardPFReq MSHR miss cycles
2649system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1003077137 # number of HardPFReq MSHR miss cycles
2650system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 504358500 # number of UpgradeReq MSHR miss cycles
2651system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 504358500 # number of UpgradeReq MSHR miss cycles
2652system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 376609000 # number of SCUpgradeReq MSHR miss cycles
2653system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 376609000 # number of SCUpgradeReq MSHR miss cycles
2654system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 725499 # number of SCUpgradeFailReq MSHR miss cycles
2655system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 725499 # number of SCUpgradeFailReq MSHR miss cycles
2656system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1128947000 # number of ReadExReq MSHR miss cycles
2657system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1128947000 # number of ReadExReq MSHR miss cycles
2658system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 579803500 # number of ReadCleanReq MSHR miss cycles
2659system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 579803500 # number of ReadCleanReq MSHR miss cycles
2660system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1128190999 # number of ReadSharedReq MSHR miss cycles
2661system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1128190999 # number of ReadSharedReq MSHR miss cycles
2662system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6919000 # number of demand (read+write) MSHR miss cycles
2663system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3801000 # number of demand (read+write) MSHR miss cycles
2664system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 579803500 # number of demand (read+write) MSHR miss cycles
2665system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2257137999 # number of demand (read+write) MSHR miss cycles
2666system.cpu1.l2cache.demand_mshr_miss_latency::total 2847661499 # number of demand (read+write) MSHR miss cycles
2667system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6919000 # number of overall MSHR miss cycles
2668system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3801000 # number of overall MSHR miss cycles
2669system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 579803500 # number of overall MSHR miss cycles
2670system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2257137999 # number of overall MSHR miss cycles
2671system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1003077137 # number of overall MSHR miss cycles
2672system.cpu1.l2cache.overall_mshr_miss_latency::total 3850738636 # number of overall MSHR miss cycles
2673system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8698000 # number of ReadReq MSHR uncacheable cycles
2674system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2412762500 # number of ReadReq MSHR uncacheable cycles
2675system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2421460500 # number of ReadReq MSHR uncacheable cycles
2676system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8698000 # number of overall MSHR uncacheable cycles
2677system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2412762500 # number of overall MSHR uncacheable cycles
2678system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2421460500 # number of overall MSHR uncacheable cycles
2679system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024551 # mshr miss rate for ReadReq accesses
2680system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.037841 # mshr miss rate for ReadReq accesses
2681system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028165 # mshr miss rate for ReadReq accesses
2682system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2683system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2684system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2685system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2686system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2687system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2688system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2689system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2690system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.548437 # mshr miss rate for ReadExReq accesses
2691system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.548437 # mshr miss rate for ReadExReq accesses
2692system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027397 # mshr miss rate for ReadCleanReq accesses
2693system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.027397 # mshr miss rate for ReadCleanReq accesses
2694system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.395683 # mshr miss rate for ReadSharedReq accesses
2695system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.395683 # mshr miss rate for ReadSharedReq accesses
2696system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024551 # mshr miss rate for demand accesses
2697system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.037841 # mshr miss rate for demand accesses
2698system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.027397 # mshr miss rate for demand accesses
2699system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.435584 # mshr miss rate for demand accesses
2700system.cpu1.l2cache.demand_mshr_miss_rate::total 0.138947 # mshr miss rate for demand accesses
2701system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024551 # mshr miss rate for overall accesses
2702system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.037841 # mshr miss rate for overall accesses
2703system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.027397 # mshr miss rate for overall accesses
2704system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.435584 # mshr miss rate for overall accesses
2705system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2706system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168407 # mshr miss rate for overall accesses
2707system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15869.266055 # average ReadReq mshr miss latency
2708system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15143.426295 # average ReadReq mshr miss latency
2709system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15604.075691 # average ReadReq mshr miss latency
2710system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39505.223780 # average HardPFReq mshr miss latency
2711system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39505.223780 # average HardPFReq mshr miss latency
2712system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16903.793947 # average UpgradeReq mshr miss latency
2713system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16903.793947 # average UpgradeReq mshr miss latency
2714system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15939.097681 # average SCUpgradeReq mshr miss latency
2715system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15939.097681 # average SCUpgradeReq mshr miss latency
2716system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 241833 # average SCUpgradeFailReq mshr miss latency
2717system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 241833 # average SCUpgradeFailReq mshr miss latency
2718system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33464.162912 # average ReadExReq mshr miss latency
2719system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33464.162912 # average ReadExReq mshr miss latency
2720system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 35154.520099 # average ReadCleanReq mshr miss latency
2721system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 35154.520099 # average ReadCleanReq mshr miss latency
2722system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16388.358667 # average ReadSharedReq mshr miss latency
2723system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16388.358667 # average ReadSharedReq mshr miss latency
2724system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15869.266055 # average overall mshr miss latency
2725system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15143.426295 # average overall mshr miss latency
2726system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 35154.520099 # average overall mshr miss latency
2727system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22004.328446 # average overall mshr miss latency
2728system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23778.664287 # average overall mshr miss latency
2729system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15869.266055 # average overall mshr miss latency
2730system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15143.426295 # average overall mshr miss latency
2731system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 35154.520099 # average overall mshr miss latency
2732system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22004.328446 # average overall mshr miss latency
2733system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39505.223780 # average overall mshr miss latency
2734system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26529.739549 # average overall mshr miss latency
2735system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85274.509804 # average ReadReq mshr uncacheable latency
2736system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166076.713932 # average ReadReq mshr uncacheable latency
2737system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165513.362953 # average ReadReq mshr uncacheable latency
2738system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85274.509804 # average overall mshr uncacheable latency
2739system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91420.222037 # average overall mshr uncacheable latency
2740system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91396.561486 # average overall mshr uncacheable latency
2741system.cpu1.toL2Bus.snoop_filter.tot_requests 1693819 # Total number of requests made to the snoop filter.
2742system.cpu1.toL2Bus.snoop_filter.hit_single_requests 856333 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2743system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12567 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2744system.cpu1.toL2Bus.snoop_filter.tot_snoops 183235 # Total number of snoops made to the snoop filter.
2745system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 181854 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2746system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1381 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2747system.cpu1.toL2Bus.trans_dist::ReadReq 43509 # Transaction distribution
2748system.cpu1.toL2Bus.trans_dist::ReadResp 857970 # Transaction distribution
2749system.cpu1.toL2Bus.trans_dist::WriteReq 11864 # Transaction distribution
2750system.cpu1.toL2Bus.trans_dist::WriteResp 11864 # Transaction distribution
2751system.cpu1.toL2Bus.trans_dist::WritebackDirty 150213 # Transaction distribution
2752system.cpu1.toL2Bus.trans_dist::WritebackClean 676407 # Transaction distribution
2753system.cpu1.toL2Bus.trans_dist::CleanEvict 108999 # Transaction distribution
2754system.cpu1.toL2Bus.trans_dist::HardPFReq 30864 # Transaction distribution
2755system.cpu1.toL2Bus.trans_dist::UpgradeReq 72606 # Transaction distribution
2756system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41945 # Transaction distribution
2757system.cpu1.toL2Bus.trans_dist::UpgradeResp 86317 # Transaction distribution
2758system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution
2759system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 28 # Transaction distribution
2760system.cpu1.toL2Bus.trans_dist::ReadExReq 68814 # Transaction distribution
2761system.cpu1.toL2Bus.trans_dist::ReadExResp 66024 # Transaction distribution
2762system.cpu1.toL2Bus.trans_dist::ReadCleanReq 602006 # Transaction distribution
2763system.cpu1.toL2Bus.trans_dist::ReadSharedReq 255355 # Transaction distribution
2764system.cpu1.toL2Bus.trans_dist::InvalidateReq 206 # Transaction distribution
2765system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1805701 # Packet count per connected master and slave (bytes)
2766system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 897982 # Packet count per connected master and slave (bytes)
2767system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14680 # Packet count per connected master and slave (bytes)
2768system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38591 # Packet count per connected master and slave (bytes)
2769system.cpu1.toL2Bus.pkt_count::total 2756954 # Packet count per connected master and slave (bytes)
2770system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 77025056 # Cumulative packet size per connected master and slave (bytes)
2771system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30176714 # Cumulative packet size per connected master and slave (bytes)
2772system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 26532 # Cumulative packet size per connected master and slave (bytes)
2773system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 71036 # Cumulative packet size per connected master and slave (bytes)
2774system.cpu1.toL2Bus.pkt_size::total 107299338 # Cumulative packet size per connected master and slave (bytes)
2775system.cpu1.toL2Bus.snoops 403916 # Total snoops (count)
2776system.cpu1.toL2Bus.snoop_fanout::samples 1269906 # Request fanout histogram
2777system.cpu1.toL2Bus.snoop_fanout::mean 0.163115 # Request fanout histogram
2778system.cpu1.toL2Bus.snoop_fanout::stdev 0.372403 # Request fanout histogram
2779system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2780system.cpu1.toL2Bus.snoop_fanout::0 1064146 83.80% 83.80% # Request fanout histogram
2781system.cpu1.toL2Bus.snoop_fanout::1 204379 16.09% 99.89% # Request fanout histogram
2782system.cpu1.toL2Bus.snoop_fanout::2 1381 0.11% 100.00% # Request fanout histogram
2783system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2784system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2785system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2786system.cpu1.toL2Bus.snoop_fanout::total 1269906 # Request fanout histogram
2787system.cpu1.toL2Bus.reqLayer0.occupancy 1668457495 # Layer occupancy (ticks)
2788system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2789system.cpu1.toL2Bus.snoopLayer0.occupancy 80964876 # Layer occupancy (ticks)
2790system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2791system.cpu1.toL2Bus.respLayer0.occupancy 903243234 # Layer occupancy (ticks)
2792system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2793system.cpu1.toL2Bus.respLayer1.occupancy 401728937 # Layer occupancy (ticks)
2794system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2795system.cpu1.toL2Bus.respLayer2.occupancy 8056980 # Layer occupancy (ticks)
2796system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2797system.cpu1.toL2Bus.respLayer3.occupancy 20851461 # Layer occupancy (ticks)
2798system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2799system.iobus.trans_dist::ReadReq 31007 # Transaction distribution
2800system.iobus.trans_dist::ReadResp 31007 # Transaction distribution
2801system.iobus.trans_dist::WriteReq 59421 # Transaction distribution
2802system.iobus.trans_dist::WriteResp 59421 # Transaction distribution
2803system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes)
2804system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2805system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2806system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
2807system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
2808system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)

--- 6 unchanged lines hidden (view full) ---

2815system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2816system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
2817system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
2818system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
2819system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
2820system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
2821system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2822system.iobus.pkt_count_system.bridge.master::total 107914 # Packet count per connected master and slave (bytes)
2823system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72942 # Packet count per connected master and slave (bytes)
2824system.iobus.pkt_count_system.realview.ide.dma::total 72942 # Packet count per connected master and slave (bytes)
2825system.iobus.pkt_count::total 180856 # Packet count per connected master and slave (bytes)
2826system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes)
2827system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2828system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2829system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
2830system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
2831system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
2832system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
2833system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)

--- 4 unchanged lines hidden (view full) ---

2838system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2839system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2840system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
2841system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
2842system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2843system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
2844system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2845system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes)
2846system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321208 # Cumulative packet size per connected master and slave (bytes)
2847system.iobus.pkt_size_system.realview.ide.dma::total 2321208 # Cumulative packet size per connected master and slave (bytes)
2848system.iobus.pkt_size::total 2484002 # Cumulative packet size per connected master and slave (bytes)
2849system.iobus.reqLayer0.occupancy 40388000 # Layer occupancy (ticks)
2850system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2851system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks)
2852system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2853system.iobus.reqLayer2.occupancy 330000 # Layer occupancy (ticks)
2854system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2855system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks)
2856system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2857system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks)
2858system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2859system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks)
2860system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2861system.iobus.reqLayer8.occupancy 574500 # Layer occupancy (ticks)
2862system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2863system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks)
2864system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2865system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
2866system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2867system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks)
2868system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2869system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks)
2870system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2871system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks)
2872system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2873system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
2874system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2875system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
2876system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2877system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
2878system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2879system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2880system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2881system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks)
2882system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2883system.iobus.reqLayer23.occupancy 6116000 # Layer occupancy (ticks)
2884system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2885system.iobus.reqLayer24.occupancy 33795000 # Layer occupancy (ticks)
2886system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2887system.iobus.reqLayer25.occupancy 187654365 # Layer occupancy (ticks)
2888system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2889system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks)
2890system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2891system.iobus.respLayer3.occupancy 36766000 # Layer occupancy (ticks)
2892system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2893system.iocache.tags.replacements 36453 # number of replacements
2894system.iocache.tags.tagsinuse 14.555427 # Cycle average of tags in use
2895system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2896system.iocache.tags.sampled_refs 36469 # Sample count of references to valid blocks.
2897system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2898system.iocache.tags.warmup_cycle 255133996000 # Cycle when the warmup percentage was hit.
2899system.iocache.tags.occ_blocks::realview.ide 14.555427 # Average occupied blocks per requestor
2900system.iocache.tags.occ_percent::realview.ide 0.909714 # Average percentage of cache occupancy
2901system.iocache.tags.occ_percent::total 0.909714 # Average percentage of cache occupancy
2902system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2903system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2904system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2905system.iocache.tags.tag_accesses 328239 # Number of tag accesses
2906system.iocache.tags.data_accesses 328239 # Number of data accesses
2907system.iocache.ReadReq_misses::realview.ide 247 # number of ReadReq misses
2908system.iocache.ReadReq_misses::total 247 # number of ReadReq misses
2909system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2910system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2911system.iocache.demand_misses::realview.ide 36471 # number of demand (read+write) misses
2912system.iocache.demand_misses::total 36471 # number of demand (read+write) misses
2913system.iocache.overall_misses::realview.ide 36471 # number of overall misses
2914system.iocache.overall_misses::total 36471 # number of overall misses
2915system.iocache.ReadReq_miss_latency::realview.ide 32034877 # number of ReadReq miss cycles
2916system.iocache.ReadReq_miss_latency::total 32034877 # number of ReadReq miss cycles
2917system.iocache.WriteLineReq_miss_latency::realview.ide 4302643488 # number of WriteLineReq miss cycles
2918system.iocache.WriteLineReq_miss_latency::total 4302643488 # number of WriteLineReq miss cycles
2919system.iocache.demand_miss_latency::realview.ide 4334678365 # number of demand (read+write) miss cycles
2920system.iocache.demand_miss_latency::total 4334678365 # number of demand (read+write) miss cycles
2921system.iocache.overall_miss_latency::realview.ide 4334678365 # number of overall miss cycles
2922system.iocache.overall_miss_latency::total 4334678365 # number of overall miss cycles
2923system.iocache.ReadReq_accesses::realview.ide 247 # number of ReadReq accesses(hits+misses)
2924system.iocache.ReadReq_accesses::total 247 # number of ReadReq accesses(hits+misses)
2925system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2926system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2927system.iocache.demand_accesses::realview.ide 36471 # number of demand (read+write) accesses
2928system.iocache.demand_accesses::total 36471 # number of demand (read+write) accesses
2929system.iocache.overall_accesses::realview.ide 36471 # number of overall (read+write) accesses
2930system.iocache.overall_accesses::total 36471 # number of overall (read+write) accesses
2931system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2932system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2933system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2934system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2935system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2936system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2937system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2938system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2939system.iocache.ReadReq_avg_miss_latency::realview.ide 129695.858300 # average ReadReq miss latency
2940system.iocache.ReadReq_avg_miss_latency::total 129695.858300 # average ReadReq miss latency
2941system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118778.806537 # average WriteLineReq miss latency
2942system.iocache.WriteLineReq_avg_miss_latency::total 118778.806537 # average WriteLineReq miss latency
2943system.iocache.demand_avg_miss_latency::realview.ide 118852.742316 # average overall miss latency
2944system.iocache.demand_avg_miss_latency::total 118852.742316 # average overall miss latency
2945system.iocache.overall_avg_miss_latency::realview.ide 118852.742316 # average overall miss latency
2946system.iocache.overall_avg_miss_latency::total 118852.742316 # average overall miss latency
2947system.iocache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked
2948system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2949system.iocache.blocked::no_mshrs 5 # number of cycles access was blocked
2950system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2951system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked
2952system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2953system.iocache.writebacks::writebacks 36206 # number of writebacks
2954system.iocache.writebacks::total 36206 # number of writebacks
2955system.iocache.ReadReq_mshr_misses::realview.ide 247 # number of ReadReq MSHR misses
2956system.iocache.ReadReq_mshr_misses::total 247 # number of ReadReq MSHR misses
2957system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2958system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2959system.iocache.demand_mshr_misses::realview.ide 36471 # number of demand (read+write) MSHR misses
2960system.iocache.demand_mshr_misses::total 36471 # number of demand (read+write) MSHR misses
2961system.iocache.overall_mshr_misses::realview.ide 36471 # number of overall MSHR misses
2962system.iocache.overall_mshr_misses::total 36471 # number of overall MSHR misses
2963system.iocache.ReadReq_mshr_miss_latency::realview.ide 19684877 # number of ReadReq MSHR miss cycles
2964system.iocache.ReadReq_mshr_miss_latency::total 19684877 # number of ReadReq MSHR miss cycles
2965system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2489128459 # number of WriteLineReq MSHR miss cycles
2966system.iocache.WriteLineReq_mshr_miss_latency::total 2489128459 # number of WriteLineReq MSHR miss cycles
2967system.iocache.demand_mshr_miss_latency::realview.ide 2508813336 # number of demand (read+write) MSHR miss cycles
2968system.iocache.demand_mshr_miss_latency::total 2508813336 # number of demand (read+write) MSHR miss cycles
2969system.iocache.overall_mshr_miss_latency::realview.ide 2508813336 # number of overall MSHR miss cycles
2970system.iocache.overall_mshr_miss_latency::total 2508813336 # number of overall MSHR miss cycles
2971system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2972system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2973system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2974system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2975system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2976system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2977system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2978system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2979system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79695.858300 # average ReadReq mshr miss latency
2980system.iocache.ReadReq_avg_mshr_miss_latency::total 79695.858300 # average ReadReq mshr miss latency
2981system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68714.897830 # average WriteLineReq mshr miss latency
2982system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68714.897830 # average WriteLineReq mshr miss latency
2983system.iocache.demand_avg_mshr_miss_latency::realview.ide 68789.266431 # average overall mshr miss latency
2984system.iocache.demand_avg_mshr_miss_latency::total 68789.266431 # average overall mshr miss latency
2985system.iocache.overall_avg_mshr_miss_latency::realview.ide 68789.266431 # average overall mshr miss latency
2986system.iocache.overall_avg_mshr_miss_latency::total 68789.266431 # average overall mshr miss latency
2987system.l2c.tags.replacements 126939 # number of replacements
2988system.l2c.tags.tagsinuse 63214.740893 # Cycle average of tags in use
2989system.l2c.tags.total_refs 439035 # Total number of references to valid blocks.
2990system.l2c.tags.sampled_refs 190800 # Sample count of references to valid blocks.
2991system.l2c.tags.avg_refs 2.301022 # Average number of references to valid blocks.
2992system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2993system.l2c.tags.occ_blocks::writebacks 13659.794415 # Average occupied blocks per requestor
2994system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.383881 # Average occupied blocks per requestor
2995system.l2c.tags.occ_blocks::cpu0.itb.walker 1.061858 # Average occupied blocks per requestor
2996system.l2c.tags.occ_blocks::cpu0.inst 8032.623601 # Average occupied blocks per requestor
2997system.l2c.tags.occ_blocks::cpu0.data 2877.626716 # Average occupied blocks per requestor
2998system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34705.867730 # Average occupied blocks per requestor
2999system.l2c.tags.occ_blocks::cpu1.dtb.walker 3.664427 # Average occupied blocks per requestor
3000system.l2c.tags.occ_blocks::cpu1.itb.walker 0.910014 # Average occupied blocks per requestor
3001system.l2c.tags.occ_blocks::cpu1.inst 1967.326736 # Average occupied blocks per requestor
3002system.l2c.tags.occ_blocks::cpu1.data 460.362743 # Average occupied blocks per requestor
3003system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1490.118772 # Average occupied blocks per requestor
3004system.l2c.tags.occ_percent::writebacks 0.208432 # Average percentage of cache occupancy
3005system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000235 # Average percentage of cache occupancy
3006system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy
3007system.l2c.tags.occ_percent::cpu0.inst 0.122568 # Average percentage of cache occupancy
3008system.l2c.tags.occ_percent::cpu0.data 0.043909 # Average percentage of cache occupancy
3009system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.529570 # Average percentage of cache occupancy
3010system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000056 # Average percentage of cache occupancy
3011system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy
3012system.l2c.tags.occ_percent::cpu1.inst 0.030019 # Average percentage of cache occupancy
3013system.l2c.tags.occ_percent::cpu1.data 0.007025 # Average percentage of cache occupancy
3014system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022737 # Average percentage of cache occupancy
3015system.l2c.tags.occ_percent::total 0.964580 # Average percentage of cache occupancy
3016system.l2c.tags.occ_task_id_blocks::1022 29285 # Occupied blocks per task id
3017system.l2c.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id
3018system.l2c.tags.occ_task_id_blocks::1024 34558 # Occupied blocks per task id
3019system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id
3020system.l2c.tags.age_task_id_blocks_1022::2 182 # Occupied blocks per task id
3021system.l2c.tags.age_task_id_blocks_1022::3 5757 # Occupied blocks per task id
3022system.l2c.tags.age_task_id_blocks_1022::4 23342 # Occupied blocks per task id
3023system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
3024system.l2c.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id
3025system.l2c.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
3026system.l2c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
3027system.l2c.tags.age_task_id_blocks_1024::2 611 # Occupied blocks per task id
3028system.l2c.tags.age_task_id_blocks_1024::3 6476 # Occupied blocks per task id
3029system.l2c.tags.age_task_id_blocks_1024::4 27436 # Occupied blocks per task id
3030system.l2c.tags.occ_task_id_percent::1022 0.446854 # Percentage of cache occupancy per task id
3031system.l2c.tags.occ_task_id_percent::1023 0.000275 # Percentage of cache occupancy per task id
3032system.l2c.tags.occ_task_id_percent::1024 0.527313 # Percentage of cache occupancy per task id
3033system.l2c.tags.tag_accesses 6030021 # Number of tag accesses
3034system.l2c.tags.data_accesses 6030021 # Number of data accesses
3035system.l2c.WritebackDirty_hits::writebacks 261794 # number of WritebackDirty hits
3036system.l2c.WritebackDirty_hits::total 261794 # number of WritebackDirty hits
3037system.l2c.UpgradeReq_hits::cpu0.data 32586 # number of UpgradeReq hits
3038system.l2c.UpgradeReq_hits::cpu1.data 2322 # number of UpgradeReq hits
3039system.l2c.UpgradeReq_hits::total 34908 # number of UpgradeReq hits
3040system.l2c.SCUpgradeReq_hits::cpu0.data 2057 # number of SCUpgradeReq hits
3041system.l2c.SCUpgradeReq_hits::cpu1.data 1031 # number of SCUpgradeReq hits
3042system.l2c.SCUpgradeReq_hits::total 3088 # number of SCUpgradeReq hits
3043system.l2c.ReadExReq_hits::cpu0.data 3923 # number of ReadExReq hits
3044system.l2c.ReadExReq_hits::cpu1.data 1723 # number of ReadExReq hits
3045system.l2c.ReadExReq_hits::total 5646 # number of ReadExReq hits
3046system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 188 # number of ReadSharedReq hits
3047system.l2c.ReadSharedReq_hits::cpu0.itb.walker 73 # number of ReadSharedReq hits
3048system.l2c.ReadSharedReq_hits::cpu0.inst 32795 # number of ReadSharedReq hits
3049system.l2c.ReadSharedReq_hits::cpu0.data 46613 # number of ReadSharedReq hits
3050system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46486 # number of ReadSharedReq hits
3051system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 68 # number of ReadSharedReq hits
3052system.l2c.ReadSharedReq_hits::cpu1.itb.walker 36 # number of ReadSharedReq hits
3053system.l2c.ReadSharedReq_hits::cpu1.inst 13556 # number of ReadSharedReq hits
3054system.l2c.ReadSharedReq_hits::cpu1.data 9028 # number of ReadSharedReq hits
3055system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5103 # number of ReadSharedReq hits
3056system.l2c.ReadSharedReq_hits::total 153946 # number of ReadSharedReq hits
3057system.l2c.demand_hits::cpu0.dtb.walker 188 # number of demand (read+write) hits
3058system.l2c.demand_hits::cpu0.itb.walker 73 # number of demand (read+write) hits
3059system.l2c.demand_hits::cpu0.inst 32795 # number of demand (read+write) hits
3060system.l2c.demand_hits::cpu0.data 50536 # number of demand (read+write) hits
3061system.l2c.demand_hits::cpu0.l2cache.prefetcher 46486 # number of demand (read+write) hits
3062system.l2c.demand_hits::cpu1.dtb.walker 68 # number of demand (read+write) hits
3063system.l2c.demand_hits::cpu1.itb.walker 36 # number of demand (read+write) hits
3064system.l2c.demand_hits::cpu1.inst 13556 # number of demand (read+write) hits
3065system.l2c.demand_hits::cpu1.data 10751 # number of demand (read+write) hits
3066system.l2c.demand_hits::cpu1.l2cache.prefetcher 5103 # number of demand (read+write) hits
3067system.l2c.demand_hits::total 159592 # number of demand (read+write) hits
3068system.l2c.overall_hits::cpu0.dtb.walker 188 # number of overall hits
3069system.l2c.overall_hits::cpu0.itb.walker 73 # number of overall hits
3070system.l2c.overall_hits::cpu0.inst 32795 # number of overall hits
3071system.l2c.overall_hits::cpu0.data 50536 # number of overall hits
3072system.l2c.overall_hits::cpu0.l2cache.prefetcher 46486 # number of overall hits
3073system.l2c.overall_hits::cpu1.dtb.walker 68 # number of overall hits
3074system.l2c.overall_hits::cpu1.itb.walker 36 # number of overall hits
3075system.l2c.overall_hits::cpu1.inst 13556 # number of overall hits
3076system.l2c.overall_hits::cpu1.data 10751 # number of overall hits
3077system.l2c.overall_hits::cpu1.l2cache.prefetcher 5103 # number of overall hits
3078system.l2c.overall_hits::total 159592 # number of overall hits
3079system.l2c.UpgradeReq_misses::cpu0.data 9262 # number of UpgradeReq misses
3080system.l2c.UpgradeReq_misses::cpu1.data 3049 # number of UpgradeReq misses
3081system.l2c.UpgradeReq_misses::total 12311 # number of UpgradeReq misses
3082system.l2c.SCUpgradeReq_misses::cpu0.data 797 # number of SCUpgradeReq misses
3083system.l2c.SCUpgradeReq_misses::cpu1.data 1327 # number of SCUpgradeReq misses
3084system.l2c.SCUpgradeReq_misses::total 2124 # number of SCUpgradeReq misses
3085system.l2c.ReadExReq_misses::cpu0.data 11181 # number of ReadExReq misses
3086system.l2c.ReadExReq_misses::cpu1.data 8169 # number of ReadExReq misses
3087system.l2c.ReadExReq_misses::total 19350 # number of ReadExReq misses
3088system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 25 # number of ReadSharedReq misses
3089system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses
3090system.l2c.ReadSharedReq_misses::cpu0.inst 19352 # number of ReadSharedReq misses
3091system.l2c.ReadSharedReq_misses::cpu0.data 9056 # number of ReadSharedReq misses
3092system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 131166 # number of ReadSharedReq misses
3093system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 5 # number of ReadSharedReq misses
3094system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses
3095system.l2c.ReadSharedReq_misses::cpu1.inst 2936 # number of ReadSharedReq misses
3096system.l2c.ReadSharedReq_misses::cpu1.data 955 # number of ReadSharedReq misses
3097system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6696 # number of ReadSharedReq misses
3098system.l2c.ReadSharedReq_misses::total 170195 # number of ReadSharedReq misses
3099system.l2c.demand_misses::cpu0.dtb.walker 25 # number of demand (read+write) misses
3100system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
3101system.l2c.demand_misses::cpu0.inst 19352 # number of demand (read+write) misses
3102system.l2c.demand_misses::cpu0.data 20237 # number of demand (read+write) misses
3103system.l2c.demand_misses::cpu0.l2cache.prefetcher 131166 # number of demand (read+write) misses
3104system.l2c.demand_misses::cpu1.dtb.walker 5 # number of demand (read+write) misses
3105system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
3106system.l2c.demand_misses::cpu1.inst 2936 # number of demand (read+write) misses
3107system.l2c.demand_misses::cpu1.data 9124 # number of demand (read+write) misses
3108system.l2c.demand_misses::cpu1.l2cache.prefetcher 6696 # number of demand (read+write) misses
3109system.l2c.demand_misses::total 189545 # number of demand (read+write) misses
3110system.l2c.overall_misses::cpu0.dtb.walker 25 # number of overall misses
3111system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
3112system.l2c.overall_misses::cpu0.inst 19352 # number of overall misses
3113system.l2c.overall_misses::cpu0.data 20237 # number of overall misses
3114system.l2c.overall_misses::cpu0.l2cache.prefetcher 131166 # number of overall misses
3115system.l2c.overall_misses::cpu1.dtb.walker 5 # number of overall misses
3116system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
3117system.l2c.overall_misses::cpu1.inst 2936 # number of overall misses
3118system.l2c.overall_misses::cpu1.data 9124 # number of overall misses
3119system.l2c.overall_misses::cpu1.l2cache.prefetcher 6696 # number of overall misses
3120system.l2c.overall_misses::total 189545 # number of overall misses
3121system.l2c.UpgradeReq_miss_latency::cpu0.data 10685000 # number of UpgradeReq miss cycles
3122system.l2c.UpgradeReq_miss_latency::cpu1.data 2955500 # number of UpgradeReq miss cycles
3123system.l2c.UpgradeReq_miss_latency::total 13640500 # number of UpgradeReq miss cycles
3124system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1570500 # number of SCUpgradeReq miss cycles
3125system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1260500 # number of SCUpgradeReq miss cycles
3126system.l2c.SCUpgradeReq_miss_latency::total 2831000 # number of SCUpgradeReq miss cycles
3127system.l2c.ReadExReq_miss_latency::cpu0.data 1150734500 # number of ReadExReq miss cycles
3128system.l2c.ReadExReq_miss_latency::cpu1.data 687988500 # number of ReadExReq miss cycles
3129system.l2c.ReadExReq_miss_latency::total 1838723000 # number of ReadExReq miss cycles
3130system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 2363000 # number of ReadSharedReq miss cycles
3131system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 241000 # number of ReadSharedReq miss cycles
3132system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1607400500 # number of ReadSharedReq miss cycles
3133system.l2c.ReadSharedReq_miss_latency::cpu0.data 824224000 # number of ReadSharedReq miss cycles
3134system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 14216291987 # number of ReadSharedReq miss cycles
3135system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 522500 # number of ReadSharedReq miss cycles
3136system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 83500 # number of ReadSharedReq miss cycles
3137system.l2c.ReadSharedReq_miss_latency::cpu1.inst 250906500 # number of ReadSharedReq miss cycles
3138system.l2c.ReadSharedReq_miss_latency::cpu1.data 89245500 # number of ReadSharedReq miss cycles
3139system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 887434795 # number of ReadSharedReq miss cycles
3140system.l2c.ReadSharedReq_miss_latency::total 17878713282 # number of ReadSharedReq miss cycles
3141system.l2c.demand_miss_latency::cpu0.dtb.walker 2363000 # number of demand (read+write) miss cycles
3142system.l2c.demand_miss_latency::cpu0.itb.walker 241000 # number of demand (read+write) miss cycles
3143system.l2c.demand_miss_latency::cpu0.inst 1607400500 # number of demand (read+write) miss cycles
3144system.l2c.demand_miss_latency::cpu0.data 1974958500 # number of demand (read+write) miss cycles
3145system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14216291987 # number of demand (read+write) miss cycles
3146system.l2c.demand_miss_latency::cpu1.dtb.walker 522500 # number of demand (read+write) miss cycles
3147system.l2c.demand_miss_latency::cpu1.itb.walker 83500 # number of demand (read+write) miss cycles
3148system.l2c.demand_miss_latency::cpu1.inst 250906500 # number of demand (read+write) miss cycles
3149system.l2c.demand_miss_latency::cpu1.data 777234000 # number of demand (read+write) miss cycles
3150system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 887434795 # number of demand (read+write) miss cycles
3151system.l2c.demand_miss_latency::total 19717436282 # number of demand (read+write) miss cycles
3152system.l2c.overall_miss_latency::cpu0.dtb.walker 2363000 # number of overall miss cycles
3153system.l2c.overall_miss_latency::cpu0.itb.walker 241000 # number of overall miss cycles
3154system.l2c.overall_miss_latency::cpu0.inst 1607400500 # number of overall miss cycles
3155system.l2c.overall_miss_latency::cpu0.data 1974958500 # number of overall miss cycles
3156system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14216291987 # number of overall miss cycles
3157system.l2c.overall_miss_latency::cpu1.dtb.walker 522500 # number of overall miss cycles
3158system.l2c.overall_miss_latency::cpu1.itb.walker 83500 # number of overall miss cycles
3159system.l2c.overall_miss_latency::cpu1.inst 250906500 # number of overall miss cycles
3160system.l2c.overall_miss_latency::cpu1.data 777234000 # number of overall miss cycles
3161system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 887434795 # number of overall miss cycles
3162system.l2c.overall_miss_latency::total 19717436282 # number of overall miss cycles
3163system.l2c.WritebackDirty_accesses::writebacks 261794 # number of WritebackDirty accesses(hits+misses)
3164system.l2c.WritebackDirty_accesses::total 261794 # number of WritebackDirty accesses(hits+misses)
3165system.l2c.UpgradeReq_accesses::cpu0.data 41848 # number of UpgradeReq accesses(hits+misses)
3166system.l2c.UpgradeReq_accesses::cpu1.data 5371 # number of UpgradeReq accesses(hits+misses)
3167system.l2c.UpgradeReq_accesses::total 47219 # number of UpgradeReq accesses(hits+misses)
3168system.l2c.SCUpgradeReq_accesses::cpu0.data 2854 # number of SCUpgradeReq accesses(hits+misses)
3169system.l2c.SCUpgradeReq_accesses::cpu1.data 2358 # number of SCUpgradeReq accesses(hits+misses)
3170system.l2c.SCUpgradeReq_accesses::total 5212 # number of SCUpgradeReq accesses(hits+misses)
3171system.l2c.ReadExReq_accesses::cpu0.data 15104 # number of ReadExReq accesses(hits+misses)
3172system.l2c.ReadExReq_accesses::cpu1.data 9892 # number of ReadExReq accesses(hits+misses)
3173system.l2c.ReadExReq_accesses::total 24996 # number of ReadExReq accesses(hits+misses)
3174system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 213 # number of ReadSharedReq accesses(hits+misses)
3175system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 76 # number of ReadSharedReq accesses(hits+misses)
3176system.l2c.ReadSharedReq_accesses::cpu0.inst 52147 # number of ReadSharedReq accesses(hits+misses)
3177system.l2c.ReadSharedReq_accesses::cpu0.data 55669 # number of ReadSharedReq accesses(hits+misses)
3178system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 177652 # number of ReadSharedReq accesses(hits+misses)
3179system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 73 # number of ReadSharedReq accesses(hits+misses)
3180system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 37 # number of ReadSharedReq accesses(hits+misses)
3181system.l2c.ReadSharedReq_accesses::cpu1.inst 16492 # number of ReadSharedReq accesses(hits+misses)
3182system.l2c.ReadSharedReq_accesses::cpu1.data 9983 # number of ReadSharedReq accesses(hits+misses)
3183system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11799 # number of ReadSharedReq accesses(hits+misses)
3184system.l2c.ReadSharedReq_accesses::total 324141 # number of ReadSharedReq accesses(hits+misses)
3185system.l2c.demand_accesses::cpu0.dtb.walker 213 # number of demand (read+write) accesses
3186system.l2c.demand_accesses::cpu0.itb.walker 76 # number of demand (read+write) accesses
3187system.l2c.demand_accesses::cpu0.inst 52147 # number of demand (read+write) accesses
3188system.l2c.demand_accesses::cpu0.data 70773 # number of demand (read+write) accesses
3189system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177652 # number of demand (read+write) accesses
3190system.l2c.demand_accesses::cpu1.dtb.walker 73 # number of demand (read+write) accesses
3191system.l2c.demand_accesses::cpu1.itb.walker 37 # number of demand (read+write) accesses
3192system.l2c.demand_accesses::cpu1.inst 16492 # number of demand (read+write) accesses
3193system.l2c.demand_accesses::cpu1.data 19875 # number of demand (read+write) accesses
3194system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11799 # number of demand (read+write) accesses
3195system.l2c.demand_accesses::total 349137 # number of demand (read+write) accesses
3196system.l2c.overall_accesses::cpu0.dtb.walker 213 # number of overall (read+write) accesses
3197system.l2c.overall_accesses::cpu0.itb.walker 76 # number of overall (read+write) accesses
3198system.l2c.overall_accesses::cpu0.inst 52147 # number of overall (read+write) accesses
3199system.l2c.overall_accesses::cpu0.data 70773 # number of overall (read+write) accesses
3200system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177652 # number of overall (read+write) accesses
3201system.l2c.overall_accesses::cpu1.dtb.walker 73 # number of overall (read+write) accesses
3202system.l2c.overall_accesses::cpu1.itb.walker 37 # number of overall (read+write) accesses
3203system.l2c.overall_accesses::cpu1.inst 16492 # number of overall (read+write) accesses
3204system.l2c.overall_accesses::cpu1.data 19875 # number of overall (read+write) accesses
3205system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11799 # number of overall (read+write) accesses
3206system.l2c.overall_accesses::total 349137 # number of overall (read+write) accesses
3207system.l2c.UpgradeReq_miss_rate::cpu0.data 0.221325 # miss rate for UpgradeReq accesses
3208system.l2c.UpgradeReq_miss_rate::cpu1.data 0.567678 # miss rate for UpgradeReq accesses
3209system.l2c.UpgradeReq_miss_rate::total 0.260721 # miss rate for UpgradeReq accesses
3210system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.279257 # miss rate for SCUpgradeReq accesses
3211system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.562765 # miss rate for SCUpgradeReq accesses
3212system.l2c.SCUpgradeReq_miss_rate::total 0.407521 # miss rate for SCUpgradeReq accesses
3213system.l2c.ReadExReq_miss_rate::cpu0.data 0.740267 # miss rate for ReadExReq accesses
3214system.l2c.ReadExReq_miss_rate::cpu1.data 0.825819 # miss rate for ReadExReq accesses
3215system.l2c.ReadExReq_miss_rate::total 0.774124 # miss rate for ReadExReq accesses
3216system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.117371 # miss rate for ReadSharedReq accesses
3217system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.039474 # miss rate for ReadSharedReq accesses
3218system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.371105 # miss rate for ReadSharedReq accesses
3219system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.162676 # miss rate for ReadSharedReq accesses
3220system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.738331 # miss rate for ReadSharedReq accesses
3221system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.068493 # miss rate for ReadSharedReq accesses
3222system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.027027 # miss rate for ReadSharedReq accesses
3223system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.178026 # miss rate for ReadSharedReq accesses
3224system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.095663 # miss rate for ReadSharedReq accesses
3225system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.567506 # miss rate for ReadSharedReq accesses
3226system.l2c.ReadSharedReq_miss_rate::total 0.525065 # miss rate for ReadSharedReq accesses
3227system.l2c.demand_miss_rate::cpu0.dtb.walker 0.117371 # miss rate for demand accesses
3228system.l2c.demand_miss_rate::cpu0.itb.walker 0.039474 # miss rate for demand accesses
3229system.l2c.demand_miss_rate::cpu0.inst 0.371105 # miss rate for demand accesses
3230system.l2c.demand_miss_rate::cpu0.data 0.285942 # miss rate for demand accesses
3231system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.738331 # miss rate for demand accesses
3232system.l2c.demand_miss_rate::cpu1.dtb.walker 0.068493 # miss rate for demand accesses
3233system.l2c.demand_miss_rate::cpu1.itb.walker 0.027027 # miss rate for demand accesses
3234system.l2c.demand_miss_rate::cpu1.inst 0.178026 # miss rate for demand accesses
3235system.l2c.demand_miss_rate::cpu1.data 0.459069 # miss rate for demand accesses
3236system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.567506 # miss rate for demand accesses
3237system.l2c.demand_miss_rate::total 0.542896 # miss rate for demand accesses
3238system.l2c.overall_miss_rate::cpu0.dtb.walker 0.117371 # miss rate for overall accesses
3239system.l2c.overall_miss_rate::cpu0.itb.walker 0.039474 # miss rate for overall accesses
3240system.l2c.overall_miss_rate::cpu0.inst 0.371105 # miss rate for overall accesses
3241system.l2c.overall_miss_rate::cpu0.data 0.285942 # miss rate for overall accesses
3242system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.738331 # miss rate for overall accesses
3243system.l2c.overall_miss_rate::cpu1.dtb.walker 0.068493 # miss rate for overall accesses
3244system.l2c.overall_miss_rate::cpu1.itb.walker 0.027027 # miss rate for overall accesses
3245system.l2c.overall_miss_rate::cpu1.inst 0.178026 # miss rate for overall accesses
3246system.l2c.overall_miss_rate::cpu1.data 0.459069 # miss rate for overall accesses
3247system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.567506 # miss rate for overall accesses
3248system.l2c.overall_miss_rate::total 0.542896 # miss rate for overall accesses
3249system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1153.638523 # average UpgradeReq miss latency
3250system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 969.334208 # average UpgradeReq miss latency
3251system.l2c.UpgradeReq_avg_miss_latency::total 1107.992852 # average UpgradeReq miss latency
3252system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1970.514429 # average SCUpgradeReq miss latency
3253system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 949.886963 # average SCUpgradeReq miss latency
3254system.l2c.SCUpgradeReq_avg_miss_latency::total 1332.862524 # average SCUpgradeReq miss latency
3255system.l2c.ReadExReq_avg_miss_latency::cpu0.data 102918.746087 # average ReadExReq miss latency
3256system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84219.427102 # average ReadExReq miss latency
3257system.l2c.ReadExReq_avg_miss_latency::total 95024.444444 # average ReadExReq miss latency
3258system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 94520 # average ReadSharedReq miss latency
3259system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 80333.333333 # average ReadSharedReq miss latency
3260system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83061.208144 # average ReadSharedReq miss latency
3261system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 91014.134276 # average ReadSharedReq miss latency
3262system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 108383.971357 # average ReadSharedReq miss latency
3263system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 104500 # average ReadSharedReq miss latency
3264system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 83500 # average ReadSharedReq miss latency
3265system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 85458.617166 # average ReadSharedReq miss latency
3266system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 93450.785340 # average ReadSharedReq miss latency
3267system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 132532.078106 # average ReadSharedReq miss latency
3268system.l2c.ReadSharedReq_avg_miss_latency::total 105048.404959 # average ReadSharedReq miss latency
3269system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 94520 # average overall miss latency
3270system.l2c.demand_avg_miss_latency::cpu0.itb.walker 80333.333333 # average overall miss latency
3271system.l2c.demand_avg_miss_latency::cpu0.inst 83061.208144 # average overall miss latency
3272system.l2c.demand_avg_miss_latency::cpu0.data 97591.466126 # average overall miss latency
3273system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 108383.971357 # average overall miss latency
3274system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 104500 # average overall miss latency
3275system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency
3276system.l2c.demand_avg_miss_latency::cpu1.inst 85458.617166 # average overall miss latency
3277system.l2c.demand_avg_miss_latency::cpu1.data 85185.664182 # average overall miss latency
3278system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132532.078106 # average overall miss latency
3279system.l2c.demand_avg_miss_latency::total 104025.093155 # average overall miss latency
3280system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 94520 # average overall miss latency
3281system.l2c.overall_avg_miss_latency::cpu0.itb.walker 80333.333333 # average overall miss latency
3282system.l2c.overall_avg_miss_latency::cpu0.inst 83061.208144 # average overall miss latency
3283system.l2c.overall_avg_miss_latency::cpu0.data 97591.466126 # average overall miss latency
3284system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 108383.971357 # average overall miss latency
3285system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 104500 # average overall miss latency
3286system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency
3287system.l2c.overall_avg_miss_latency::cpu1.inst 85458.617166 # average overall miss latency
3288system.l2c.overall_avg_miss_latency::cpu1.data 85185.664182 # average overall miss latency
3289system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132532.078106 # average overall miss latency
3290system.l2c.overall_avg_miss_latency::total 104025.093155 # average overall miss latency
3291system.l2c.blocked_cycles::no_mshrs 838 # number of cycles access was blocked
3292system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
3293system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked
3294system.l2c.blocked::no_targets 0 # number of cycles access was blocked
3295system.l2c.avg_blocked_cycles::no_mshrs 104.750000 # average number of cycles each access was blocked
3296system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3297system.l2c.writebacks::writebacks 99614 # number of writebacks
3298system.l2c.writebacks::total 99614 # number of writebacks
3299system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 2 # number of ReadSharedReq MSHR hits
3300system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 7 # number of ReadSharedReq MSHR hits
3301system.l2c.ReadSharedReq_mshr_hits::total 9 # number of ReadSharedReq MSHR hits
3302system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits
3303system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
3304system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
3305system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits
3306system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
3307system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits
3308system.l2c.CleanEvict_mshr_misses::writebacks 3468 # number of CleanEvict MSHR misses
3309system.l2c.CleanEvict_mshr_misses::total 3468 # number of CleanEvict MSHR misses
3310system.l2c.UpgradeReq_mshr_misses::cpu0.data 9262 # number of UpgradeReq MSHR misses
3311system.l2c.UpgradeReq_mshr_misses::cpu1.data 3049 # number of UpgradeReq MSHR misses
3312system.l2c.UpgradeReq_mshr_misses::total 12311 # number of UpgradeReq MSHR misses
3313system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 797 # number of SCUpgradeReq MSHR misses
3314system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1327 # number of SCUpgradeReq MSHR misses
3315system.l2c.SCUpgradeReq_mshr_misses::total 2124 # number of SCUpgradeReq MSHR misses
3316system.l2c.ReadExReq_mshr_misses::cpu0.data 11181 # number of ReadExReq MSHR misses
3317system.l2c.ReadExReq_mshr_misses::cpu1.data 8169 # number of ReadExReq MSHR misses
3318system.l2c.ReadExReq_mshr_misses::total 19350 # number of ReadExReq MSHR misses
3319system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 25 # number of ReadSharedReq MSHR misses
3320system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3 # number of ReadSharedReq MSHR misses
3321system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19350 # number of ReadSharedReq MSHR misses
3322system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9056 # number of ReadSharedReq MSHR misses
3323system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 131166 # number of ReadSharedReq MSHR misses
3324system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 5 # number of ReadSharedReq MSHR misses
3325system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses
3326system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2929 # number of ReadSharedReq MSHR misses
3327system.l2c.ReadSharedReq_mshr_misses::cpu1.data 955 # number of ReadSharedReq MSHR misses
3328system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6696 # number of ReadSharedReq MSHR misses
3329system.l2c.ReadSharedReq_mshr_misses::total 170186 # number of ReadSharedReq MSHR misses
3330system.l2c.demand_mshr_misses::cpu0.dtb.walker 25 # number of demand (read+write) MSHR misses
3331system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses
3332system.l2c.demand_mshr_misses::cpu0.inst 19350 # number of demand (read+write) MSHR misses
3333system.l2c.demand_mshr_misses::cpu0.data 20237 # number of demand (read+write) MSHR misses
3334system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 131166 # number of demand (read+write) MSHR misses
3335system.l2c.demand_mshr_misses::cpu1.dtb.walker 5 # number of demand (read+write) MSHR misses
3336system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
3337system.l2c.demand_mshr_misses::cpu1.inst 2929 # number of demand (read+write) MSHR misses
3338system.l2c.demand_mshr_misses::cpu1.data 9124 # number of demand (read+write) MSHR misses
3339system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6696 # number of demand (read+write) MSHR misses
3340system.l2c.demand_mshr_misses::total 189536 # number of demand (read+write) MSHR misses
3341system.l2c.overall_mshr_misses::cpu0.dtb.walker 25 # number of overall MSHR misses
3342system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses
3343system.l2c.overall_mshr_misses::cpu0.inst 19350 # number of overall MSHR misses
3344system.l2c.overall_mshr_misses::cpu0.data 20237 # number of overall MSHR misses
3345system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 131166 # number of overall MSHR misses
3346system.l2c.overall_mshr_misses::cpu1.dtb.walker 5 # number of overall MSHR misses
3347system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
3348system.l2c.overall_mshr_misses::cpu1.inst 2929 # number of overall MSHR misses
3349system.l2c.overall_mshr_misses::cpu1.data 9124 # number of overall MSHR misses
3350system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6696 # number of overall MSHR misses
3351system.l2c.overall_mshr_misses::total 189536 # number of overall MSHR misses
3352system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable
3353system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20340 # number of ReadReq MSHR uncacheable
3354system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable
3355system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14525 # number of ReadReq MSHR uncacheable
3356system.l2c.ReadReq_mshr_uncacheable::total 37970 # number of ReadReq MSHR uncacheable
3357system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19033 # number of WriteReq MSHR uncacheable
3358system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11864 # number of WriteReq MSHR uncacheable
3359system.l2c.WriteReq_mshr_uncacheable::total 30897 # number of WriteReq MSHR uncacheable
3360system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses
3361system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39373 # number of overall MSHR uncacheable misses
3362system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses
3363system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26389 # number of overall MSHR uncacheable misses
3364system.l2c.overall_mshr_uncacheable_misses::total 68867 # number of overall MSHR uncacheable misses
3365system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 221469500 # number of UpgradeReq MSHR miss cycles
3366system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 70279500 # number of UpgradeReq MSHR miss cycles
3367system.l2c.UpgradeReq_mshr_miss_latency::total 291749000 # number of UpgradeReq MSHR miss cycles
3368system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 20549499 # number of SCUpgradeReq MSHR miss cycles
3369system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 32977500 # number of SCUpgradeReq MSHR miss cycles
3370system.l2c.SCUpgradeReq_mshr_miss_latency::total 53526999 # number of SCUpgradeReq MSHR miss cycles
3371system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1038924500 # number of ReadExReq MSHR miss cycles
3372system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 606298001 # number of ReadExReq MSHR miss cycles
3373system.l2c.ReadExReq_mshr_miss_latency::total 1645222501 # number of ReadExReq MSHR miss cycles
3374system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 2113000 # number of ReadSharedReq MSHR miss cycles
3375system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 211000 # number of ReadSharedReq MSHR miss cycles
3376system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1413871007 # number of ReadSharedReq MSHR miss cycles
3377system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 733663501 # number of ReadSharedReq MSHR miss cycles
3378system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12904628993 # number of ReadSharedReq MSHR miss cycles
3379system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 472500 # number of ReadSharedReq MSHR miss cycles
3380system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 73500 # number of ReadSharedReq MSHR miss cycles
3381system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 221234502 # number of ReadSharedReq MSHR miss cycles
3382system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 79695500 # number of ReadSharedReq MSHR miss cycles
3383system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 820473798 # number of ReadSharedReq MSHR miss cycles
3384system.l2c.ReadSharedReq_mshr_miss_latency::total 16176437301 # number of ReadSharedReq MSHR miss cycles
3385system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2113000 # number of demand (read+write) MSHR miss cycles
3386system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 211000 # number of demand (read+write) MSHR miss cycles
3387system.l2c.demand_mshr_miss_latency::cpu0.inst 1413871007 # number of demand (read+write) MSHR miss cycles
3388system.l2c.demand_mshr_miss_latency::cpu0.data 1772588001 # number of demand (read+write) MSHR miss cycles
3389system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12904628993 # number of demand (read+write) MSHR miss cycles
3390system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 472500 # number of demand (read+write) MSHR miss cycles
3391system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 73500 # number of demand (read+write) MSHR miss cycles
3392system.l2c.demand_mshr_miss_latency::cpu1.inst 221234502 # number of demand (read+write) MSHR miss cycles
3393system.l2c.demand_mshr_miss_latency::cpu1.data 685993501 # number of demand (read+write) MSHR miss cycles
3394system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 820473798 # number of demand (read+write) MSHR miss cycles
3395system.l2c.demand_mshr_miss_latency::total 17821659802 # number of demand (read+write) MSHR miss cycles
3396system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2113000 # number of overall MSHR miss cycles
3397system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 211000 # number of overall MSHR miss cycles
3398system.l2c.overall_mshr_miss_latency::cpu0.inst 1413871007 # number of overall MSHR miss cycles
3399system.l2c.overall_mshr_miss_latency::cpu0.data 1772588001 # number of overall MSHR miss cycles
3400system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12904628993 # number of overall MSHR miss cycles
3401system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 472500 # number of overall MSHR miss cycles
3402system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 73500 # number of overall MSHR miss cycles
3403system.l2c.overall_mshr_miss_latency::cpu1.inst 221234502 # number of overall MSHR miss cycles
3404system.l2c.overall_mshr_miss_latency::cpu1.data 685993501 # number of overall MSHR miss cycles
3405system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 820473798 # number of overall MSHR miss cycles
3406system.l2c.overall_mshr_miss_latency::total 17821659802 # number of overall MSHR miss cycles
3407system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 192566500 # number of ReadReq MSHR uncacheable cycles
3408system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4005508001 # number of ReadReq MSHR uncacheable cycles
3409system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6861000 # number of ReadReq MSHR uncacheable cycles
3410system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2151256501 # number of ReadReq MSHR uncacheable cycles
3411system.l2c.ReadReq_mshr_uncacheable_latency::total 6356192002 # number of ReadReq MSHR uncacheable cycles
3412system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 192566500 # number of overall MSHR uncacheable cycles
3413system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4005508001 # number of overall MSHR uncacheable cycles
3414system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6861000 # number of overall MSHR uncacheable cycles
3415system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2151256501 # number of overall MSHR uncacheable cycles
3416system.l2c.overall_mshr_uncacheable_latency::total 6356192002 # number of overall MSHR uncacheable cycles
3417system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3418system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3419system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.221325 # mshr miss rate for UpgradeReq accesses
3420system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.567678 # mshr miss rate for UpgradeReq accesses
3421system.l2c.UpgradeReq_mshr_miss_rate::total 0.260721 # mshr miss rate for UpgradeReq accesses
3422system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.279257 # mshr miss rate for SCUpgradeReq accesses
3423system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.562765 # mshr miss rate for SCUpgradeReq accesses
3424system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.407521 # mshr miss rate for SCUpgradeReq accesses
3425system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.740267 # mshr miss rate for ReadExReq accesses
3426system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.825819 # mshr miss rate for ReadExReq accesses
3427system.l2c.ReadExReq_mshr_miss_rate::total 0.774124 # mshr miss rate for ReadExReq accesses
3428system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.117371 # mshr miss rate for ReadSharedReq accesses
3429system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.039474 # mshr miss rate for ReadSharedReq accesses
3430system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.371066 # mshr miss rate for ReadSharedReq accesses
3431system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.162676 # mshr miss rate for ReadSharedReq accesses
3432system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738331 # mshr miss rate for ReadSharedReq accesses
3433system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.068493 # mshr miss rate for ReadSharedReq accesses
3434system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.027027 # mshr miss rate for ReadSharedReq accesses
3435system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.177601 # mshr miss rate for ReadSharedReq accesses
3436system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.095663 # mshr miss rate for ReadSharedReq accesses
3437system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.567506 # mshr miss rate for ReadSharedReq accesses
3438system.l2c.ReadSharedReq_mshr_miss_rate::total 0.525037 # mshr miss rate for ReadSharedReq accesses
3439system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.117371 # mshr miss rate for demand accesses
3440system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.039474 # mshr miss rate for demand accesses
3441system.l2c.demand_mshr_miss_rate::cpu0.inst 0.371066 # mshr miss rate for demand accesses
3442system.l2c.demand_mshr_miss_rate::cpu0.data 0.285942 # mshr miss rate for demand accesses
3443system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738331 # mshr miss rate for demand accesses
3444system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.068493 # mshr miss rate for demand accesses
3445system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.027027 # mshr miss rate for demand accesses
3446system.l2c.demand_mshr_miss_rate::cpu1.inst 0.177601 # mshr miss rate for demand accesses
3447system.l2c.demand_mshr_miss_rate::cpu1.data 0.459069 # mshr miss rate for demand accesses
3448system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.567506 # mshr miss rate for demand accesses
3449system.l2c.demand_mshr_miss_rate::total 0.542870 # mshr miss rate for demand accesses
3450system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.117371 # mshr miss rate for overall accesses
3451system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.039474 # mshr miss rate for overall accesses
3452system.l2c.overall_mshr_miss_rate::cpu0.inst 0.371066 # mshr miss rate for overall accesses
3453system.l2c.overall_mshr_miss_rate::cpu0.data 0.285942 # mshr miss rate for overall accesses
3454system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738331 # mshr miss rate for overall accesses
3455system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.068493 # mshr miss rate for overall accesses
3456system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.027027 # mshr miss rate for overall accesses
3457system.l2c.overall_mshr_miss_rate::cpu1.inst 0.177601 # mshr miss rate for overall accesses
3458system.l2c.overall_mshr_miss_rate::cpu1.data 0.459069 # mshr miss rate for overall accesses
3459system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.567506 # mshr miss rate for overall accesses
3460system.l2c.overall_mshr_miss_rate::total 0.542870 # mshr miss rate for overall accesses
3461system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23911.628158 # average UpgradeReq mshr miss latency
3462system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23050.016399 # average UpgradeReq mshr miss latency
3463system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23698.237349 # average UpgradeReq mshr miss latency
3464system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25783.562108 # average SCUpgradeReq mshr miss latency
3465system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24851.168048 # average SCUpgradeReq mshr miss latency
3466system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25201.035311 # average SCUpgradeReq mshr miss latency
3467system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92918.746087 # average ReadExReq mshr miss latency
3468system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74219.366018 # average ReadExReq mshr miss latency
3469system.l2c.ReadExReq_avg_mshr_miss_latency::total 85024.418656 # average ReadExReq mshr miss latency
3470system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 84520 # average ReadSharedReq mshr miss latency
3471system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average ReadSharedReq mshr miss latency
3472system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73068.269096 # average ReadSharedReq mshr miss latency
3473system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 81014.079174 # average ReadSharedReq mshr miss latency
3474system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98383.948531 # average ReadSharedReq mshr miss latency
3475system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 94500 # average ReadSharedReq mshr miss latency
3476system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average ReadSharedReq mshr miss latency
3477system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75532.434961 # average ReadSharedReq mshr miss latency
3478system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83450.785340 # average ReadSharedReq mshr miss latency
3479system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122531.929211 # average ReadSharedReq mshr miss latency
3480system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 95051.515994 # average ReadSharedReq mshr miss latency
3481system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84520 # average overall mshr miss latency
3482system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency
3483system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73068.269096 # average overall mshr miss latency
3484system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87591.441469 # average overall mshr miss latency
3485system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98383.948531 # average overall mshr miss latency
3486system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 94500 # average overall mshr miss latency
3487system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency
3488system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75532.434961 # average overall mshr miss latency
3489system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75185.609491 # average overall mshr miss latency
3490system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122531.929211 # average overall mshr miss latency
3491system.l2c.demand_avg_mshr_miss_latency::total 94027.835356 # average overall mshr miss latency
3492system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84520 # average overall mshr miss latency
3493system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency
3494system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73068.269096 # average overall mshr miss latency
3495system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87591.441469 # average overall mshr miss latency
3496system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98383.948531 # average overall mshr miss latency
3497system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 94500 # average overall mshr miss latency
3498system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency
3499system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75532.434961 # average overall mshr miss latency
3500system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75185.609491 # average overall mshr miss latency
3501system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122531.929211 # average overall mshr miss latency
3502system.l2c.overall_avg_mshr_miss_latency::total 94027.835356 # average overall mshr miss latency
3503system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average ReadReq mshr uncacheable latency
3504system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196927.630334 # average ReadReq mshr uncacheable latency
3505system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67264.705882 # average ReadReq mshr uncacheable latency
3506system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148107.160138 # average ReadReq mshr uncacheable latency
3507system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167400.368765 # average ReadReq mshr uncacheable latency
3508system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average overall mshr uncacheable latency
3509system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101732.354685 # average overall mshr uncacheable latency
3510system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67264.705882 # average overall mshr uncacheable latency
3511system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81520.955739 # average overall mshr uncacheable latency
3512system.l2c.overall_avg_mshr_uncacheable_latency::total 92296.629765 # average overall mshr uncacheable latency
3513system.membus.snoop_filter.tot_requests 514606 # Total number of requests made to the snoop filter.
3514system.membus.snoop_filter.hit_single_requests 294659 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3515system.membus.snoop_filter.hit_multi_requests 567 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3516system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
3517system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3518system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3519system.membus.trans_dist::ReadReq 37970 # Transaction distribution
3520system.membus.trans_dist::ReadResp 208402 # Transaction distribution
3521system.membus.trans_dist::WriteReq 30897 # Transaction distribution
3522system.membus.trans_dist::WriteResp 30897 # Transaction distribution
3523system.membus.trans_dist::WritebackDirty 135820 # Transaction distribution
3524system.membus.trans_dist::CleanEvict 15995 # Transaction distribution
3525system.membus.trans_dist::UpgradeReq 76425 # Transaction distribution
3526system.membus.trans_dist::SCUpgradeReq 40810 # Transaction distribution
3527system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
3528system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
3529system.membus.trans_dist::ReadExReq 38865 # Transaction distribution
3530system.membus.trans_dist::ReadExResp 19252 # Transaction distribution
3531system.membus.trans_dist::ReadSharedReq 170433 # Transaction distribution
3532system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
3533system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes)
3534system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes)
3535system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13670 # Packet count per connected master and slave (bytes)
3536system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 646867 # Packet count per connected master and slave (bytes)
3537system.membus.pkt_count_system.l2c.mem_side::total 768487 # Packet count per connected master and slave (bytes)
3538system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes)
3539system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes)
3540system.membus.pkt_count::total 841426 # Packet count per connected master and slave (bytes)
3541system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes)
3542system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes)
3543system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27340 # Cumulative packet size per connected master and slave (bytes)
3544system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18547336 # Cumulative packet size per connected master and slave (bytes)
3545system.membus.pkt_size_system.l2c.mem_side::total 18737758 # Cumulative packet size per connected master and slave (bytes)
3546system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
3547system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
3548system.membus.pkt_size::total 21055902 # Cumulative packet size per connected master and slave (bytes)
3549system.membus.snoops 122883 # Total snoops (count)
3550system.membus.snoop_fanout::samples 431628 # Request fanout histogram
3551system.membus.snoop_fanout::mean 0.011899 # Request fanout histogram
3552system.membus.snoop_fanout::stdev 0.108432 # Request fanout histogram
3553system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3554system.membus.snoop_fanout::0 426492 98.81% 98.81% # Request fanout histogram
3555system.membus.snoop_fanout::1 5136 1.19% 100.00% # Request fanout histogram
3556system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3557system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3558system.membus.snoop_fanout::min_value 0 # Request fanout histogram
3559system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3560system.membus.snoop_fanout::total 431628 # Request fanout histogram
3561system.membus.reqLayer0.occupancy 81611500 # Layer occupancy (ticks)
3562system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3563system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks)
3564system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3565system.membus.reqLayer2.occupancy 11561000 # Layer occupancy (ticks)
3566system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3567system.membus.reqLayer5.occupancy 995379161 # Layer occupancy (ticks)
3568system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3569system.membus.respLayer2.occupancy 1093943847 # Layer occupancy (ticks)
3570system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3571system.membus.respLayer3.occupancy 1316877 # Layer occupancy (ticks)
3572system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3573system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3574system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3575system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3576system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3577system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3578system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3579system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA

--- 26 unchanged lines hidden (view full) ---

3606system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3607system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
3608system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
3609system.realview.ethernet.droppedPackets 0 # number of packets dropped
3610system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3611system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3612system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3613system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3614system.toL2Bus.snoop_filter.tot_requests 1005681 # Total number of requests made to the snoop filter.
3615system.toL2Bus.snoop_filter.hit_single_requests 545297 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3616system.toL2Bus.snoop_filter.hit_multi_requests 156423 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3617system.toL2Bus.snoop_filter.tot_snoops 20020 # Total number of snoops made to the snoop filter.
3618system.toL2Bus.snoop_filter.hit_single_snoops 19070 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3619system.toL2Bus.snoop_filter.hit_multi_snoops 950 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3620system.toL2Bus.trans_dist::ReadReq 37973 # Transaction distribution
3621system.toL2Bus.trans_dist::ReadResp 482978 # Transaction distribution
3622system.toL2Bus.trans_dist::WriteReq 30897 # Transaction distribution
3623system.toL2Bus.trans_dist::WriteResp 30897 # Transaction distribution
3624system.toL2Bus.trans_dist::WritebackDirty 361408 # Transaction distribution
3625system.toL2Bus.trans_dist::CleanEvict 120637 # Transaction distribution
3626system.toL2Bus.trans_dist::UpgradeReq 111235 # Transaction distribution
3627system.toL2Bus.trans_dist::SCUpgradeReq 43898 # Transaction distribution
3628system.toL2Bus.trans_dist::UpgradeResp 155133 # Transaction distribution
3629system.toL2Bus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution
3630system.toL2Bus.trans_dist::UpgradeFailResp 28 # Transaction distribution
3631system.toL2Bus.trans_dist::ReadExReq 50623 # Transaction distribution
3632system.toL2Bus.trans_dist::ReadExResp 50623 # Transaction distribution
3633system.toL2Bus.trans_dist::ReadSharedReq 445008 # Transaction distribution
3634system.toL2Bus.trans_dist::InvalidateReq 4567 # Transaction distribution
3635system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1196695 # Packet count per connected master and slave (bytes)
3636system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 348487 # Packet count per connected master and slave (bytes)
3637system.toL2Bus.pkt_count::total 1545182 # Packet count per connected master and slave (bytes)
3638system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34087104 # Cumulative packet size per connected master and slave (bytes)
3639system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5287070 # Cumulative packet size per connected master and slave (bytes)
3640system.toL2Bus.pkt_size::total 39374174 # Cumulative packet size per connected master and slave (bytes)
3641system.toL2Bus.snoops 380983 # Total snoops (count)
3642system.toL2Bus.snoop_fanout::samples 851193 # Request fanout histogram
3643system.toL2Bus.snoop_fanout::mean 0.382254 # Request fanout histogram
3644system.toL2Bus.snoop_fanout::stdev 0.488230 # Request fanout histogram
3645system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3646system.toL2Bus.snoop_fanout::0 526771 61.89% 61.89% # Request fanout histogram
3647system.toL2Bus.snoop_fanout::1 323472 38.00% 99.89% # Request fanout histogram
3648system.toL2Bus.snoop_fanout::2 950 0.11% 100.00% # Request fanout histogram
3649system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3650system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3651system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3652system.toL2Bus.snoop_fanout::total 851193 # Request fanout histogram
3653system.toL2Bus.reqLayer0.occupancy 876200249 # Layer occupancy (ticks)
3654system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3655system.toL2Bus.snoopLayer0.occupancy 348123 # Layer occupancy (ticks)
3656system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3657system.toL2Bus.respLayer0.occupancy 630764010 # Layer occupancy (ticks)
3658system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3659system.toL2Bus.respLayer1.occupancy 246030993 # Layer occupancy (ticks)
3660system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3661system.cpu0.kern.inst.arm 0 # number of arm instructions executed
3662system.cpu0.kern.inst.quiesce 1854 # number of quiesce instructions executed
3663system.cpu1.kern.inst.arm 0 # number of arm instructions executed
3664system.cpu1.kern.inst.quiesce 2756 # number of quiesce instructions executed
3665
3666---------- End Simulation Statistics ----------