1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.827390 # Number of seconds simulated
4sim_ticks 2827390179000 # Number of ticks simulated
5final_tick 2827390179000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 115301 # Simulator instruction rate (inst/s)
8host_op_rate 139868 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2711751203 # Simulator tick rate (ticks/s)
10host_mem_usage 622004 # Number of bytes of host memory used
11host_seconds 1042.64 # Real time elapsed on the host
12sim_insts 120217407 # Number of instructions simulated
13sim_ops 145833000 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 1792 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1297536 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 1327400 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8611392 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 181424 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 629012 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 447552 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
27system.physmem.bytes_read::total 12497708 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 1297536 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 181424 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 1478960 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 8852800 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
34system.physmem.bytes_written::total 8870364 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 28 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 22521 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 21261 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 134553 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.inst 2903 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.data 9849 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.l2cache.prefetcher 6993 # Number of read requests responded to by this memory
45system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
46system.physmem.num_reads::total 198133 # Number of read requests responded to by this memory
47system.physmem.num_writes::writebacks 138325 # Number of write requests responded to by this memory
48system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
50system.physmem.num_writes::total 142716 # Number of write requests responded to by this memory
51system.physmem.bw_read::cpu0.dtb.walker 634 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.inst 458916 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.data 469479 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.l2cache.prefetcher 3045703 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.dtb.walker 136 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.inst 64167 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.data 222471 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.l2cache.prefetcher 158292 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::total 4420228 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::cpu0.inst 458916 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu1.inst 64167 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::total 523083 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_write::writebacks 3131085 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::cpu0.data 6198 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::total 3137297 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_total::writebacks 3131085 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.dtb.walker 634 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.inst 458916 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.data 475677 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.l2cache.prefetcher 3045703 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.dtb.walker 136 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.inst 64167 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.data 222485 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.l2cache.prefetcher 158292 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::total 7557525 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.readReqs 198134 # Number of read requests accepted
84system.physmem.writeReqs 142716 # Number of write requests accepted
85system.physmem.readBursts 198134 # Number of DRAM read bursts, including those serviced by the write queue
86system.physmem.writeBursts 142716 # Number of DRAM write bursts, including those merged in the write queue
87system.physmem.bytesReadDRAM 12670976 # Total number of bytes read from DRAM
88system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue
89system.physmem.bytesWritten 8883264 # Total number of bytes written to DRAM
90system.physmem.bytesReadSys 12497772 # Total read bytes from the system interface side
91system.physmem.bytesWrittenSys 8870364 # Total written bytes from the system interface side
92system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue
93system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
94system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
95system.physmem.perBankRdBursts::0 12497 # Per bank write bursts
96system.physmem.perBankRdBursts::1 12182 # Per bank write bursts
97system.physmem.perBankRdBursts::2 12917 # Per bank write bursts
98system.physmem.perBankRdBursts::3 12745 # Per bank write bursts
99system.physmem.perBankRdBursts::4 14769 # Per bank write bursts
100system.physmem.perBankRdBursts::5 12267 # Per bank write bursts
101system.physmem.perBankRdBursts::6 12449 # Per bank write bursts
102system.physmem.perBankRdBursts::7 12406 # Per bank write bursts
103system.physmem.perBankRdBursts::8 12316 # Per bank write bursts
104system.physmem.perBankRdBursts::9 12005 # Per bank write bursts
105system.physmem.perBankRdBursts::10 11767 # Per bank write bursts
106system.physmem.perBankRdBursts::11 10930 # Per bank write bursts
107system.physmem.perBankRdBursts::12 12080 # Per bank write bursts
108system.physmem.perBankRdBursts::13 12638 # Per bank write bursts
109system.physmem.perBankRdBursts::14 12372 # Per bank write bursts
110system.physmem.perBankRdBursts::15 11644 # Per bank write bursts
111system.physmem.perBankWrBursts::0 9110 # Per bank write bursts
112system.physmem.perBankWrBursts::1 9003 # Per bank write bursts
113system.physmem.perBankWrBursts::2 9525 # Per bank write bursts
114system.physmem.perBankWrBursts::3 9146 # Per bank write bursts
115system.physmem.perBankWrBursts::4 8599 # Per bank write bursts
116system.physmem.perBankWrBursts::5 8760 # Per bank write bursts
117system.physmem.perBankWrBursts::6 8787 # Per bank write bursts
118system.physmem.perBankWrBursts::7 8590 # Per bank write bursts
119system.physmem.perBankWrBursts::8 8640 # Per bank write bursts
120system.physmem.perBankWrBursts::9 8402 # Per bank write bursts
121system.physmem.perBankWrBursts::10 8397 # Per bank write bursts
122system.physmem.perBankWrBursts::11 7923 # Per bank write bursts
123system.physmem.perBankWrBursts::12 8683 # Per bank write bursts
124system.physmem.perBankWrBursts::13 8738 # Per bank write bursts
125system.physmem.perBankWrBursts::14 8625 # Per bank write bursts
126system.physmem.perBankWrBursts::15 7873 # Per bank write bursts
127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128system.physmem.numWrRetry 13 # Number of times write queue was full causing retry
129system.physmem.totGap 2827389912000 # Total gap between requests
130system.physmem.readPktSize::0 0 # Read request sizes (log2)
131system.physmem.readPktSize::1 0 # Read request sizes (log2)
132system.physmem.readPktSize::2 551 # Read request sizes (log2)
133system.physmem.readPktSize::3 28 # Read request sizes (log2)
134system.physmem.readPktSize::4 3087 # Read request sizes (log2)
135system.physmem.readPktSize::5 0 # Read request sizes (log2)
136system.physmem.readPktSize::6 194468 # Read request sizes (log2)
137system.physmem.writePktSize::0 0 # Write request sizes (log2)
138system.physmem.writePktSize::1 0 # Write request sizes (log2)
139system.physmem.writePktSize::2 4391 # Write request sizes (log2)
140system.physmem.writePktSize::3 0 # Write request sizes (log2)
141system.physmem.writePktSize::4 0 # Write request sizes (log2)
142system.physmem.writePktSize::5 0 # Write request sizes (log2)
143system.physmem.writePktSize::6 138325 # Write request sizes (log2)
144system.physmem.rdQLenPdf::0 63072 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 74912 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 13439 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 10395 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 8664 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 7526 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 6556 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::7 5382 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::8 4708 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::9 1378 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::10 855 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::11 585 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::12 259 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::13 231 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
165system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see

--- 11 unchanged lines hidden (view full) ---

183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::15 2653 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::16 3705 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::17 4835 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::18 4665 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::19 5857 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::20 5830 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::21 6370 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::22 6999 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::23 7929 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::24 7989 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::25 8736 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::26 9851 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::27 9099 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::28 9885 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::29 12144 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::30 9599 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::31 8596 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::32 8331 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::33 1397 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::34 519 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::35 425 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::36 342 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::37 283 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::38 213 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::39 145 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::40 166 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::41 183 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::43 156 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::44 124 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::45 115 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::46 126 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::47 91 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::48 129 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::51 113 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::52 103 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::53 85 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::54 121 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::57 82 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::59 68 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::60 42 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::63 32 # What write queue length does an incoming req see
240system.physmem.bytesPerActivate::samples 90813 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::mean 237.346812 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::gmean 134.326622 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::stdev 300.184335 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::0-127 49078 54.04% 54.04% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::128-255 17700 19.49% 73.53% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::256-383 6123 6.74% 80.28% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::384-511 3320 3.66% 83.93% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::512-639 2774 3.05% 86.99% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::640-767 1638 1.80% 88.79% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::768-895 995 1.10% 89.89% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::896-1023 978 1.08% 90.96% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::1024-1151 8207 9.04% 100.00% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::total 90813 # Bytes accessed per row activation
254system.physmem.rdPerTurnAround::samples 6724 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::mean 29.444230 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::stdev 548.218856 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::0-2047 6721 99.96% 99.96% # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.99% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::total 6724 # Reads before turning the bus around for writes
261system.physmem.wrPerTurnAround::samples 6724 # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::mean 20.642623 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::gmean 18.824239 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::stdev 13.739703 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::16-19 5581 83.00% 83.00% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::20-23 483 7.18% 90.18% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::24-27 96 1.43% 91.61% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::28-31 46 0.68% 92.30% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::32-35 45 0.67% 92.97% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::36-39 26 0.39% 93.35% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::40-43 56 0.83% 94.19% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::44-47 16 0.24% 94.42% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::48-51 112 1.67% 96.09% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::52-55 17 0.25% 96.34% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::56-59 5 0.07% 96.42% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::60-63 15 0.22% 96.64% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::64-67 76 1.13% 97.77% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::68-71 5 0.07% 97.84% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::72-75 5 0.07% 97.92% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::76-79 30 0.45% 98.36% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::80-83 72 1.07% 99.43% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::84-87 5 0.07% 99.51% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::92-95 1 0.01% 99.52% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::96-99 3 0.04% 99.57% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::100-103 1 0.01% 99.58% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::104-107 1 0.01% 99.60% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::108-111 1 0.01% 99.61% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::116-119 1 0.01% 99.63% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::120-123 1 0.01% 99.64% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::128-131 7 0.10% 99.75% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::136-139 2 0.03% 99.78% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::140-143 3 0.04% 99.82% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::144-147 6 0.09% 99.91% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::156-159 1 0.01% 99.93% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::160-163 1 0.01% 99.94% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::168-171 1 0.01% 99.96% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::176-179 3 0.04% 100.00% # Writes before turning the bus around for reads
298system.physmem.wrPerTurnAround::total 6724 # Writes before turning the bus around for reads
299system.physmem.totQLat 6642491804 # Total ticks spent queuing
300system.physmem.totMemAccLat 10354691804 # Total ticks spent from burst creation until serviced by the DRAM
301system.physmem.totBusLat 989920000 # Total ticks spent in databus transfers
302system.physmem.avgQLat 33550.65 # Average queueing delay per DRAM burst
303system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
304system.physmem.avgMemAccLat 52300.65 # Average memory access latency per DRAM burst
305system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s
306system.physmem.avgWrBW 3.14 # Average achieved write bandwidth in MiByte/s
307system.physmem.avgRdBWSys 4.42 # Average system read bandwidth in MiByte/s
308system.physmem.avgWrBWSys 3.14 # Average system write bandwidth in MiByte/s
309system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
310system.physmem.busUtil 0.06 # Data bus utilization in percentage
311system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
312system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
313system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
314system.physmem.avgWrQLen 28.40 # Average write queue length when enqueuing
315system.physmem.readRowHits 165266 # Number of row buffer hits during reads
316system.physmem.writeRowHits 80705 # Number of row buffer hits during writes
317system.physmem.readRowHitRate 83.47 # Row buffer hit rate for reads
318system.physmem.writeRowHitRate 58.14 # Row buffer hit rate for writes
319system.physmem.avgGap 8295114.90 # Average gap between requests
320system.physmem.pageHitRate 73.03 # Row buffer hit rate, read and write combined
321system.physmem_0.actEnergy 356771520 # Energy for activate commands per rank (pJ)
322system.physmem_0.preEnergy 194667000 # Energy for precharge commands per rank (pJ)
323system.physmem_0.readEnergy 797401800 # Energy for read commands per rank (pJ)
324system.physmem_0.writeEnergy 463449600 # Energy for write commands per rank (pJ)
325system.physmem_0.refreshEnergy 184671358560 # Energy for refresh commands per rank (pJ)
326system.physmem_0.actBackEnergy 80516584620 # Energy for active background per rank (pJ)
327system.physmem_0.preBackEnergy 1625805455250 # Energy for precharge background per rank (pJ)
328system.physmem_0.totalEnergy 1892805688350 # Total energy per rank (pJ)
329system.physmem_0.averagePower 669.453328 # Core power per rank (mW)
330system.physmem_0.memoryStateTime::IDLE 2704566595208 # Time in different power states
331system.physmem_0.memoryStateTime::REF 94412760000 # Time in different power states
332system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
333system.physmem_0.memoryStateTime::ACT 28410820792 # Time in different power states
334system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
335system.physmem_1.actEnergy 329774760 # Energy for activate commands per rank (pJ)
336system.physmem_1.preEnergy 179936625 # Energy for precharge commands per rank (pJ)
337system.physmem_1.readEnergy 746865600 # Energy for read commands per rank (pJ)
338system.physmem_1.writeEnergy 435980880 # Energy for write commands per rank (pJ)
339system.physmem_1.refreshEnergy 184671358560 # Energy for refresh commands per rank (pJ)
340system.physmem_1.actBackEnergy 80145816435 # Energy for active background per rank (pJ)
341system.physmem_1.preBackEnergy 1626130690500 # Energy for precharge background per rank (pJ)
342system.physmem_1.totalEnergy 1892640423360 # Total energy per rank (pJ)
343system.physmem_1.averagePower 669.394877 # Core power per rank (mW)
344system.physmem_1.memoryStateTime::IDLE 2705113148361 # Time in different power states
345system.physmem_1.memoryStateTime::REF 94412760000 # Time in different power states
346system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
347system.physmem_1.memoryStateTime::ACT 27864169139 # Time in different power states
348system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
349system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory
350system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory
351system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory
352system.realview.nvmem.bytes_inst_read::cpu0.inst 112 # Number of instructions bytes read from this memory
353system.realview.nvmem.bytes_inst_read::cpu1.inst 176 # Number of instructions bytes read from this memory
354system.realview.nvmem.bytes_inst_read::total 288 # Number of instructions bytes read from this memory
355system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory
356system.realview.nvmem.num_reads::cpu1.inst 11 # Number of read requests responded to by this memory
357system.realview.nvmem.num_reads::total 18 # Number of read requests responded to by this memory
358system.realview.nvmem.bw_read::cpu0.inst 40 # Total read bandwidth from this memory (bytes/s)
359system.realview.nvmem.bw_read::cpu1.inst 62 # Total read bandwidth from this memory (bytes/s)
360system.realview.nvmem.bw_read::total 102 # Total read bandwidth from this memory (bytes/s)
361system.realview.nvmem.bw_inst_read::cpu0.inst 40 # Instruction read bandwidth from this memory (bytes/s)
362system.realview.nvmem.bw_inst_read::cpu1.inst 62 # Instruction read bandwidth from this memory (bytes/s)
363system.realview.nvmem.bw_inst_read::total 102 # Instruction read bandwidth from this memory (bytes/s)
364system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s)
365system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s)
366system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s)
367system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
368system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
369system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
370system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
371system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
372system.cf0.dma_write_txs 631 # Number of DMA write transactions.
373system.cpu0.branchPred.lookups 53911245 # Number of BP lookups
374system.cpu0.branchPred.condPredicted 24947324 # Number of conditional branches predicted
375system.cpu0.branchPred.condIncorrect 985007 # Number of conditional branches incorrect
376system.cpu0.branchPred.BTBLookups 32642222 # Number of BTB lookups
377system.cpu0.branchPred.BTBHits 14256732 # Number of BTB hits
378system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
379system.cpu0.branchPred.BTBHitPct 43.675740 # BTB Hit Percentage
380system.cpu0.branchPred.usedRAS 15584760 # Number of times the RAS was used to get a target.
381system.cpu0.branchPred.RASInCorrect 34685 # Number of incorrect RAS predictions.
382system.cpu0.branchPred.indirectLookups 10159968 # Number of indirect predictor lookups.
383system.cpu0.branchPred.indirectHits 9991718 # Number of indirect target hits.
384system.cpu0.branchPred.indirectMisses 168250 # Number of indirect misses.
385system.cpu0.branchPredindirectMispredicted 52822 # Number of mispredicted indirect branches.
386system.cpu_clk_domain.clock 500 # Clock period in ticks
387system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

408system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
409system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
410system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
411system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
412system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
413system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
414system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
415system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
416system.cpu0.dtb.walker.walks 71875 # Table walker walks requested
417system.cpu0.dtb.walker.walksShort 71875 # Table walker walks initiated with short descriptors
418system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26071 # Level at which table walker walks with short descriptors terminate
419system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21701 # Level at which table walker walks with short descriptors terminate
420system.cpu0.dtb.walker.walksSquashedBefore 24103 # Table walks squashed before starting
421system.cpu0.dtb.walker.walkWaitTime::samples 47772 # Table walker wait (enqueue to first request) latency
422system.cpu0.dtb.walker.walkWaitTime::mean 520.796701 # Table walker wait (enqueue to first request) latency
423system.cpu0.dtb.walker.walkWaitTime::stdev 3158.268863 # Table walker wait (enqueue to first request) latency
424system.cpu0.dtb.walker.walkWaitTime::0-8191 46423 97.18% 97.18% # Table walker wait (enqueue to first request) latency
425system.cpu0.dtb.walker.walkWaitTime::8192-16383 981 2.05% 99.23% # Table walker wait (enqueue to first request) latency
426system.cpu0.dtb.walker.walkWaitTime::16384-24575 165 0.35% 99.58% # Table walker wait (enqueue to first request) latency
427system.cpu0.dtb.walker.walkWaitTime::24576-32767 156 0.33% 99.90% # Table walker wait (enqueue to first request) latency
428system.cpu0.dtb.walker.walkWaitTime::32768-40959 17 0.04% 99.94% # Table walker wait (enqueue to first request) latency
429system.cpu0.dtb.walker.walkWaitTime::40960-49151 25 0.05% 99.99% # Table walker wait (enqueue to first request) latency
430system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
431system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
432system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
433system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
434system.cpu0.dtb.walker.walkWaitTime::114688-122879 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
435system.cpu0.dtb.walker.walkWaitTime::total 47772 # Table walker wait (enqueue to first request) latency
436system.cpu0.dtb.walker.walkCompletionTime::samples 18721 # Table walker service (enqueue to completion) latency
437system.cpu0.dtb.walker.walkCompletionTime::mean 11203.514770 # Table walker service (enqueue to completion) latency
438system.cpu0.dtb.walker.walkCompletionTime::gmean 9623.609798 # Table walker service (enqueue to completion) latency
439system.cpu0.dtb.walker.walkCompletionTime::stdev 9038.861696 # Table walker service (enqueue to completion) latency
440system.cpu0.dtb.walker.walkCompletionTime::0-32767 18593 99.32% 99.32% # Table walker service (enqueue to completion) latency
441system.cpu0.dtb.walker.walkCompletionTime::32768-65535 88 0.47% 99.79% # Table walker service (enqueue to completion) latency
442system.cpu0.dtb.walker.walkCompletionTime::131072-163839 23 0.12% 99.91% # Table walker service (enqueue to completion) latency
443system.cpu0.dtb.walker.walkCompletionTime::163840-196607 16 0.09% 99.99% # Table walker service (enqueue to completion) latency
444system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
445system.cpu0.dtb.walker.walkCompletionTime::total 18721 # Table walker service (enqueue to completion) latency
446system.cpu0.dtb.walker.walksPending::samples 87200107652 # Table walker pending requests distribution
447system.cpu0.dtb.walker.walksPending::mean 0.546732 # Table walker pending requests distribution
448system.cpu0.dtb.walker.walksPending::stdev 0.508218 # Table walker pending requests distribution
449system.cpu0.dtb.walker.walksPending::0 39687331700 45.51% 45.51% # Table walker pending requests distribution
450system.cpu0.dtb.walker.walksPending::1 47447148952 54.41% 99.92% # Table walker pending requests distribution
451system.cpu0.dtb.walker.walksPending::2 30000500 0.03% 99.96% # Table walker pending requests distribution
452system.cpu0.dtb.walker.walksPending::3 16923500 0.02% 99.98% # Table walker pending requests distribution
453system.cpu0.dtb.walker.walksPending::4 5972000 0.01% 99.99% # Table walker pending requests distribution
454system.cpu0.dtb.walker.walksPending::5 3342500 0.00% 99.99% # Table walker pending requests distribution
455system.cpu0.dtb.walker.walksPending::6 3974500 0.00% 99.99% # Table walker pending requests distribution
456system.cpu0.dtb.walker.walksPending::7 1269500 0.00% 100.00% # Table walker pending requests distribution
457system.cpu0.dtb.walker.walksPending::8 992000 0.00% 100.00% # Table walker pending requests distribution
458system.cpu0.dtb.walker.walksPending::9 652500 0.00% 100.00% # Table walker pending requests distribution
459system.cpu0.dtb.walker.walksPending::10 669000 0.00% 100.00% # Table walker pending requests distribution
460system.cpu0.dtb.walker.walksPending::11 287500 0.00% 100.00% # Table walker pending requests distribution
461system.cpu0.dtb.walker.walksPending::12 887500 0.00% 100.00% # Table walker pending requests distribution
462system.cpu0.dtb.walker.walksPending::13 113500 0.00% 100.00% # Table walker pending requests distribution
463system.cpu0.dtb.walker.walksPending::14 101000 0.00% 100.00% # Table walker pending requests distribution
464system.cpu0.dtb.walker.walksPending::15 441500 0.00% 100.00% # Table walker pending requests distribution
465system.cpu0.dtb.walker.walksPending::total 87200107652 # Table walker pending requests distribution
466system.cpu0.dtb.walker.walkPageSizes::4K 5974 77.64% 77.64% # Table walker page sizes translated
467system.cpu0.dtb.walker.walkPageSizes::1M 1720 22.36% 100.00% # Table walker page sizes translated
468system.cpu0.dtb.walker.walkPageSizes::total 7694 # Table walker page sizes translated
469system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 71875 # Table walker requests started/completed, data/inst
470system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
471system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 71875 # Table walker requests started/completed, data/inst
472system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7694 # Table walker requests started/completed, data/inst
473system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
474system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7694 # Table walker requests started/completed, data/inst
475system.cpu0.dtb.walker.walkRequestOrigin::total 79569 # Table walker requests started/completed, data/inst
476system.cpu0.dtb.inst_hits 0 # ITB inst hits
477system.cpu0.dtb.inst_misses 0 # ITB inst misses
478system.cpu0.dtb.read_hits 24391036 # DTB read hits
479system.cpu0.dtb.read_misses 61424 # DTB read misses
480system.cpu0.dtb.write_hits 18141184 # DTB write hits
481system.cpu0.dtb.write_misses 10451 # DTB write misses
482system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
483system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
484system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
485system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
486system.cpu0.dtb.flush_entries 3871 # Number of entries that have been flushed from TLB
487system.cpu0.dtb.align_faults 259 # Number of TLB faults due to alignment restrictions
488system.cpu0.dtb.prefetch_faults 2351 # Number of TLB faults due to prefetch
489system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
490system.cpu0.dtb.perms_faults 984 # Number of TLB faults due to permissions restrictions
491system.cpu0.dtb.read_accesses 24452460 # DTB read accesses
492system.cpu0.dtb.write_accesses 18151635 # DTB write accesses
493system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
494system.cpu0.dtb.hits 42532220 # DTB hits
495system.cpu0.dtb.misses 71875 # DTB misses
496system.cpu0.dtb.accesses 42604095 # DTB accesses
497system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
498system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
499system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
500system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
501system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
502system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
503system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
504system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

518system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
519system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
520system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
521system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
522system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
523system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
524system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
525system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
526system.cpu0.itb.walker.walks 11562 # Table walker walks requested
527system.cpu0.itb.walker.walksShort 11562 # Table walker walks initiated with short descriptors
528system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4001 # Level at which table walker walks with short descriptors terminate
529system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6396 # Level at which table walker walks with short descriptors terminate
530system.cpu0.itb.walker.walksSquashedBefore 1165 # Table walks squashed before starting
531system.cpu0.itb.walker.walkWaitTime::samples 10397 # Table walker wait (enqueue to first request) latency
532system.cpu0.itb.walker.walkWaitTime::mean 461.575454 # Table walker wait (enqueue to first request) latency
533system.cpu0.itb.walker.walkWaitTime::stdev 2367.707906 # Table walker wait (enqueue to first request) latency
534system.cpu0.itb.walker.walkWaitTime::0-4095 9981 96.00% 96.00% # Table walker wait (enqueue to first request) latency
535system.cpu0.itb.walker.walkWaitTime::4096-8191 185 1.78% 97.78% # Table walker wait (enqueue to first request) latency
536system.cpu0.itb.walker.walkWaitTime::8192-12287 127 1.22% 99.00% # Table walker wait (enqueue to first request) latency
537system.cpu0.itb.walker.walkWaitTime::12288-16383 59 0.57% 99.57% # Table walker wait (enqueue to first request) latency
538system.cpu0.itb.walker.walkWaitTime::16384-20479 11 0.11% 99.67% # Table walker wait (enqueue to first request) latency
539system.cpu0.itb.walker.walkWaitTime::20480-24575 23 0.22% 99.89% # Table walker wait (enqueue to first request) latency
540system.cpu0.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.91% # Table walker wait (enqueue to first request) latency
541system.cpu0.itb.walker.walkWaitTime::28672-32767 2 0.02% 99.93% # Table walker wait (enqueue to first request) latency
542system.cpu0.itb.walker.walkWaitTime::32768-36863 4 0.04% 99.97% # Table walker wait (enqueue to first request) latency
543system.cpu0.itb.walker.walkWaitTime::36864-40959 3 0.03% 100.00% # Table walker wait (enqueue to first request) latency
544system.cpu0.itb.walker.walkWaitTime::total 10397 # Table walker wait (enqueue to first request) latency
545system.cpu0.itb.walker.walkCompletionTime::samples 4031 # Table walker service (enqueue to completion) latency
546system.cpu0.itb.walker.walkCompletionTime::mean 11997.147110 # Table walker service (enqueue to completion) latency
547system.cpu0.itb.walker.walkCompletionTime::gmean 11095.550949 # Table walker service (enqueue to completion) latency
548system.cpu0.itb.walker.walkCompletionTime::stdev 5265.028524 # Table walker service (enqueue to completion) latency
549system.cpu0.itb.walker.walkCompletionTime::0-16383 3778 93.72% 93.72% # Table walker service (enqueue to completion) latency
550system.cpu0.itb.walker.walkCompletionTime::16384-32767 218 5.41% 99.13% # Table walker service (enqueue to completion) latency
551system.cpu0.itb.walker.walkCompletionTime::32768-49151 33 0.82% 99.95% # Table walker service (enqueue to completion) latency
552system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
553system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
554system.cpu0.itb.walker.walkCompletionTime::total 4031 # Table walker service (enqueue to completion) latency
555system.cpu0.itb.walker.walksPending::samples 22774753212 # Table walker pending requests distribution
556system.cpu0.itb.walker.walksPending::mean 0.815515 # Table walker pending requests distribution
557system.cpu0.itb.walker.walksPending::stdev 0.388020 # Table walker pending requests distribution
558system.cpu0.itb.walker.walksPending::0 4202728000 18.45% 18.45% # Table walker pending requests distribution
559system.cpu0.itb.walker.walksPending::1 18570993712 81.54% 100.00% # Table walker pending requests distribution
560system.cpu0.itb.walker.walksPending::2 925000 0.00% 100.00% # Table walker pending requests distribution
561system.cpu0.itb.walker.walksPending::3 106500 0.00% 100.00% # Table walker pending requests distribution
562system.cpu0.itb.walker.walksPending::total 22774753212 # Table walker pending requests distribution
563system.cpu0.itb.walker.walkPageSizes::4K 2507 87.47% 87.47% # Table walker page sizes translated
564system.cpu0.itb.walker.walkPageSizes::1M 359 12.53% 100.00% # Table walker page sizes translated
565system.cpu0.itb.walker.walkPageSizes::total 2866 # Table walker page sizes translated
566system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
567system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11562 # Table walker requests started/completed, data/inst
568system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11562 # Table walker requests started/completed, data/inst
569system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
570system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2866 # Table walker requests started/completed, data/inst
571system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2866 # Table walker requests started/completed, data/inst
572system.cpu0.itb.walker.walkRequestOrigin::total 14428 # Table walker requests started/completed, data/inst
573system.cpu0.itb.inst_hits 74050785 # ITB inst hits
574system.cpu0.itb.inst_misses 11562 # ITB inst misses
575system.cpu0.itb.read_hits 0 # DTB read hits
576system.cpu0.itb.read_misses 0 # DTB read misses
577system.cpu0.itb.write_hits 0 # DTB write hits
578system.cpu0.itb.write_misses 0 # DTB write misses
579system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
580system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
581system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
582system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
583system.cpu0.itb.flush_entries 2601 # Number of entries that have been flushed from TLB
584system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
585system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
586system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
587system.cpu0.itb.perms_faults 2163 # Number of TLB faults due to permissions restrictions
588system.cpu0.itb.read_accesses 0 # DTB read accesses
589system.cpu0.itb.write_accesses 0 # DTB write accesses
590system.cpu0.itb.inst_accesses 74062347 # ITB inst accesses
591system.cpu0.itb.hits 74050785 # DTB hits
592system.cpu0.itb.misses 11562 # DTB misses
593system.cpu0.itb.accesses 74062347 # DTB accesses
594system.cpu0.numCycles 210807967 # number of cpu cycles simulated
595system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
596system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
597system.cpu0.fetch.icacheStallCycles 21220653 # Number of cycles fetch is stalled on an Icache miss
598system.cpu0.fetch.Insts 200130599 # Number of instructions fetch has processed
599system.cpu0.fetch.Branches 53911245 # Number of branches that fetch encountered
600system.cpu0.fetch.predictedBranches 39833210 # Number of branches that fetch has predicted taken
601system.cpu0.fetch.Cycles 180362708 # Number of cycles fetch has run and was not squashing or blocked
602system.cpu0.fetch.SquashCycles 5820684 # Number of cycles fetch has spent squashing
603system.cpu0.fetch.TlbCycles 154995 # Number of cycles fetch has spent waiting for tlb
604system.cpu0.fetch.MiscStallCycles 66964 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
605system.cpu0.fetch.PendingTrapStallCycles 420974 # Number of stall cycles due to pending traps
606system.cpu0.fetch.PendingQuiesceStallCycles 452324 # Number of stall cycles due to pending quiesce instructions
607system.cpu0.fetch.IcacheWaitRetryStallCycles 103497 # Number of stall cycles due to full MSHR
608system.cpu0.fetch.CacheLines 74050081 # Number of cache lines fetched
609system.cpu0.fetch.IcacheSquashes 272746 # Number of outstanding Icache misses that were squashed
610system.cpu0.fetch.ItlbSquashes 5705 # Number of outstanding ITLB misses that were squashed
611system.cpu0.fetch.rateDist::samples 205692457 # Number of instructions fetched each cycle (Total)
612system.cpu0.fetch.rateDist::mean 1.188766 # Number of instructions fetched each cycle (Total)
613system.cpu0.fetch.rateDist::stdev 1.306289 # Number of instructions fetched each cycle (Total)
614system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
615system.cpu0.fetch.rateDist::0 98524588 47.90% 47.90% # Number of instructions fetched each cycle (Total)
616system.cpu0.fetch.rateDist::1 31037557 15.09% 62.99% # Number of instructions fetched each cycle (Total)
617system.cpu0.fetch.rateDist::2 14908217 7.25% 70.24% # Number of instructions fetched each cycle (Total)
618system.cpu0.fetch.rateDist::3 61222095 29.76% 100.00% # Number of instructions fetched each cycle (Total)
619system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
620system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
621system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
622system.cpu0.fetch.rateDist::total 205692457 # Number of instructions fetched each cycle (Total)
623system.cpu0.fetch.branchRate 0.255736 # Number of branch fetches per cycle
624system.cpu0.fetch.rate 0.949350 # Number of inst fetches per cycle
625system.cpu0.decode.IdleCycles 26429213 # Number of cycles decode is idle
626system.cpu0.decode.BlockedCycles 111222366 # Number of cycles decode is blocked
627system.cpu0.decode.RunCycles 60319076 # Number of cycles decode is running
628system.cpu0.decode.UnblockCycles 5157963 # Number of cycles decode is unblocking
629system.cpu0.decode.SquashCycles 2563839 # Number of cycles decode is squashing
630system.cpu0.decode.BranchResolved 3171648 # Number of times decode resolved a branch
631system.cpu0.decode.BranchMispred 350947 # Number of times decode detected a branch misprediction
632system.cpu0.decode.DecodedInsts 158388827 # Number of instructions handled by decode
633system.cpu0.decode.SquashedInsts 4014782 # Number of squashed instructions handled by decode
634system.cpu0.rename.SquashCycles 2563839 # Number of cycles rename is squashing
635system.cpu0.rename.IdleCycles 35280795 # Number of cycles rename is idle
636system.cpu0.rename.BlockCycles 13301493 # Number of cycles rename is blocking
637system.cpu0.rename.serializeStallCycles 85153816 # count of cycles rename stalled for serializing inst
638system.cpu0.rename.RunCycles 56482950 # Number of cycles rename is running
639system.cpu0.rename.UnblockCycles 12909564 # Number of cycles rename is unblocking
640system.cpu0.rename.RenamedInsts 141500597 # Number of instructions processed by rename
641system.cpu0.rename.SquashedInsts 1085672 # Number of squashed instructions processed by rename
642system.cpu0.rename.ROBFullEvents 1524488 # Number of times rename has blocked due to ROB full
643system.cpu0.rename.IQFullEvents 177088 # Number of times rename has blocked due to IQ full
644system.cpu0.rename.LQFullEvents 62946 # Number of times rename has blocked due to LQ full
645system.cpu0.rename.SQFullEvents 8550384 # Number of times rename has blocked due to SQ full
646system.cpu0.rename.RenamedOperands 145816753 # Number of destination operands rename has renamed
647system.cpu0.rename.RenameLookups 652563275 # Number of register rename lookups that rename has made
648system.cpu0.rename.int_rename_lookups 157207618 # Number of integer rename lookups
649system.cpu0.rename.fp_rename_lookups 11000 # Number of floating rename lookups
650system.cpu0.rename.CommittedMaps 133932927 # Number of HB maps that are committed
651system.cpu0.rename.UndoneMaps 11883815 # Number of HB maps that are undone due to squashing
652system.cpu0.rename.serializingInsts 2738789 # count of serializing insts renamed
653system.cpu0.rename.tempSerializingInsts 2591099 # count of temporary serializing insts renamed
654system.cpu0.rename.skidInsts 23044959 # count of insts added to the skid buffer
655system.cpu0.memDep0.insertedLoads 25364147 # Number of loads inserted to the mem dependence unit.
656system.cpu0.memDep0.insertedStores 19673316 # Number of stores inserted to the mem dependence unit.
657system.cpu0.memDep0.conflictingLoads 1767343 # Number of conflicting loads.
658system.cpu0.memDep0.conflictingStores 2535257 # Number of conflicting stores.
659system.cpu0.iq.iqInstsAdded 138424520 # Number of instructions added to the IQ (excludes non-spec)
660system.cpu0.iq.iqNonSpecInstsAdded 1769995 # Number of non-speculative instructions added to the IQ
661system.cpu0.iq.iqInstsIssued 136412034 # Number of instructions issued
662system.cpu0.iq.iqSquashedInstsIssued 484040 # Number of squashed instructions issued
663system.cpu0.iq.iqSquashedInstsExamined 11120854 # Number of squashed instructions iterated over during squash; mainly for profiling
664system.cpu0.iq.iqSquashedOperandsExamined 22999814 # Number of squashed operands that are examined and possibly removed from graph
665system.cpu0.iq.iqSquashedNonSpecRemoved 127192 # Number of squashed non-spec instructions that were removed
666system.cpu0.iq.issued_per_cycle::samples 205692457 # Number of insts issued each cycle
667system.cpu0.iq.issued_per_cycle::mean 0.663184 # Number of insts issued each cycle
668system.cpu0.iq.issued_per_cycle::stdev 0.962224 # Number of insts issued each cycle
669system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
670system.cpu0.iq.issued_per_cycle::0 126945183 61.72% 61.72% # Number of insts issued each cycle
671system.cpu0.iq.issued_per_cycle::1 34499506 16.77% 78.49% # Number of insts issued each cycle
672system.cpu0.iq.issued_per_cycle::2 31998886 15.56% 94.05% # Number of insts issued each cycle
673system.cpu0.iq.issued_per_cycle::3 11080832 5.39% 99.43% # Number of insts issued each cycle
674system.cpu0.iq.issued_per_cycle::4 1167990 0.57% 100.00% # Number of insts issued each cycle
675system.cpu0.iq.issued_per_cycle::5 60 0.00% 100.00% # Number of insts issued each cycle
676system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
677system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
678system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
679system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
680system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
681system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
682system.cpu0.iq.issued_per_cycle::total 205692457 # Number of insts issued each cycle
683system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
684system.cpu0.iq.fu_full::IntAlu 11130033 43.82% 43.82% # attempts to use FU when none available
685system.cpu0.iq.fu_full::IntMult 71 0.00% 43.82% # attempts to use FU when none available
686system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.82% # attempts to use FU when none available
687system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.82% # attempts to use FU when none available
688system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.82% # attempts to use FU when none available
689system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.82% # attempts to use FU when none available
690system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.82% # attempts to use FU when none available
691system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.82% # attempts to use FU when none available
692system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.82% # attempts to use FU when none available
693system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.82% # attempts to use FU when none available
694system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.82% # attempts to use FU when none available
695system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.82% # attempts to use FU when none available
696system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.82% # attempts to use FU when none available
697system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.82% # attempts to use FU when none available
698system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.82% # attempts to use FU when none available
699system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.82% # attempts to use FU when none available
700system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.82% # attempts to use FU when none available
701system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.82% # attempts to use FU when none available
702system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.82% # attempts to use FU when none available
703system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.82% # attempts to use FU when none available
704system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.82% # attempts to use FU when none available
705system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.82% # attempts to use FU when none available
706system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.82% # attempts to use FU when none available
707system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.82% # attempts to use FU when none available
708system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.82% # attempts to use FU when none available
709system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.82% # attempts to use FU when none available
710system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.82% # attempts to use FU when none available
711system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.82% # attempts to use FU when none available
712system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.82% # attempts to use FU when none available
713system.cpu0.iq.fu_full::MemRead 5937286 23.38% 67.20% # attempts to use FU when none available
714system.cpu0.iq.fu_full::MemWrite 8330186 32.80% 100.00% # attempts to use FU when none available
715system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
716system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
717system.cpu0.iq.FU_type_0::No_OpClass 2315 0.00% 0.00% # Type of FU issued
718system.cpu0.iq.FU_type_0::IntAlu 91960000 67.41% 67.42% # Type of FU issued
719system.cpu0.iq.FU_type_0::IntMult 113905 0.08% 67.50% # Type of FU issued
720system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.50% # Type of FU issued
721system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.50% # Type of FU issued
722system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.50% # Type of FU issued
723system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.50% # Type of FU issued
724system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.50% # Type of FU issued
725system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.50% # Type of FU issued
726system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.50% # Type of FU issued
727system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.50% # Type of FU issued
728system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.50% # Type of FU issued
729system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.50% # Type of FU issued
730system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.50% # Type of FU issued
731system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.50% # Type of FU issued
732system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.50% # Type of FU issued
733system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.50% # Type of FU issued
734system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.50% # Type of FU issued
735system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.50% # Type of FU issued
736system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.50% # Type of FU issued
737system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.50% # Type of FU issued
738system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.50% # Type of FU issued
739system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.50% # Type of FU issued
740system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.50% # Type of FU issued
741system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.50% # Type of FU issued
742system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 67.50% # Type of FU issued
743system.cpu0.iq.FU_type_0::SimdFloatMisc 8243 0.01% 67.50% # Type of FU issued
744system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.50% # Type of FU issued
745system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.50% # Type of FU issued
746system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.50% # Type of FU issued
747system.cpu0.iq.FU_type_0::MemRead 25115664 18.41% 85.92% # Type of FU issued
748system.cpu0.iq.FU_type_0::MemWrite 19211906 14.08% 100.00% # Type of FU issued
749system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
750system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
751system.cpu0.iq.FU_type_0::total 136412034 # Type of FU issued
752system.cpu0.iq.rate 0.647091 # Inst issue rate
753system.cpu0.iq.fu_busy_cnt 25397576 # FU busy when requested
754system.cpu0.iq.fu_busy_rate 0.186183 # FU busy rate (busy events/executed inst)
755system.cpu0.iq.int_inst_queue_reads 504359597 # Number of integer instruction queue reads
756system.cpu0.iq.int_inst_queue_writes 151322890 # Number of integer instruction queue writes
757system.cpu0.iq.int_inst_queue_wakeup_accesses 132769388 # Number of integer instruction queue wakeup accesses
758system.cpu0.iq.fp_inst_queue_reads 38543 # Number of floating instruction queue reads
759system.cpu0.iq.fp_inst_queue_writes 13252 # Number of floating instruction queue writes
760system.cpu0.iq.fp_inst_queue_wakeup_accesses 11438 # Number of floating instruction queue wakeup accesses
761system.cpu0.iq.int_alu_accesses 161782111 # Number of integer alu accesses
762system.cpu0.iq.fp_alu_accesses 25184 # Number of floating point alu accesses
763system.cpu0.iew.lsq.thread0.forwLoads 383563 # Number of loads that had data forwarded from stores
764system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
765system.cpu0.iew.lsq.thread0.squashedLoads 2036205 # Number of loads squashed
766system.cpu0.iew.lsq.thread0.ignoredResponses 2638 # Number of memory responses ignored because the instruction is squashed
767system.cpu0.iew.lsq.thread0.memOrderViolation 20853 # Number of memory ordering violations
768system.cpu0.iew.lsq.thread0.squashedStores 948035 # Number of stores squashed
769system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
770system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
771system.cpu0.iew.lsq.thread0.rescheduledLoads 126036 # Number of loads that were rescheduled
772system.cpu0.iew.lsq.thread0.cacheBlocked 394781 # Number of times an access to memory failed due to the cache being blocked
773system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
774system.cpu0.iew.iewSquashCycles 2563839 # Number of cycles IEW is squashing
775system.cpu0.iew.iewBlockCycles 1921080 # Number of cycles IEW is blocking
776system.cpu0.iew.iewUnblockCycles 231914 # Number of cycles IEW is unblocking
777system.cpu0.iew.iewDispatchedInsts 140382056 # Number of instructions dispatched to IQ
778system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
779system.cpu0.iew.iewDispLoadInsts 25364147 # Number of dispatched load instructions
780system.cpu0.iew.iewDispStoreInsts 19673316 # Number of dispatched store instructions
781system.cpu0.iew.iewDispNonSpecInsts 906447 # Number of dispatched non-speculative instructions
782system.cpu0.iew.iewIQFullEvents 31018 # Number of times the IQ has become full, causing a stall
783system.cpu0.iew.iewLSQFullEvents 175567 # Number of times the LSQ has become full, causing a stall
784system.cpu0.iew.memOrderViolationEvents 20853 # Number of memory order violations
785system.cpu0.iew.predictedTakenIncorrect 275420 # Number of branches that were predicted taken incorrectly
786system.cpu0.iew.predictedNotTakenIncorrect 424017 # Number of branches that were predicted not taken incorrectly
787system.cpu0.iew.branchMispredicts 699437 # Number of branch mispredicts detected at execute
788system.cpu0.iew.iewExecutedInsts 135325292 # Number of executed instructions
789system.cpu0.iew.iewExecLoadInsts 24646519 # Number of load instructions executed
790system.cpu0.iew.iewExecSquashedInsts 1015002 # Number of squashed instructions skipped in execute
791system.cpu0.iew.exec_swp 0 # number of swp insts executed
792system.cpu0.iew.exec_nop 187541 # number of nop insts executed
793system.cpu0.iew.exec_refs 43690093 # number of memory reference insts executed
794system.cpu0.iew.exec_branches 26111417 # Number of branches executed
795system.cpu0.iew.exec_stores 19043574 # Number of stores executed
796system.cpu0.iew.exec_rate 0.641936 # Inst execution rate
797system.cpu0.iew.wb_sent 134725872 # cumulative count of insts sent to commit
798system.cpu0.iew.wb_count 132780826 # cumulative count of insts written-back
799system.cpu0.iew.wb_producers 67751819 # num instructions producing a value
800system.cpu0.iew.wb_consumers 109549817 # num instructions consuming a value
801system.cpu0.iew.wb_rate 0.629866 # insts written-back per cycle
802system.cpu0.iew.wb_fanout 0.618457 # average fanout of values written-back
803system.cpu0.commit.commitSquashedInsts 10037586 # The number of squashed insts skipped by commit
804system.cpu0.commit.commitNonSpecStalls 1642803 # The number of times commit has been forced to stall to communicate backwards
805system.cpu0.commit.branchMispredicts 638504 # The number of times a branch was mispredicted
806system.cpu0.commit.committed_per_cycle::samples 202442995 # Number of insts commited each cycle
807system.cpu0.commit.committed_per_cycle::mean 0.638330 # Number of insts commited each cycle
808system.cpu0.commit.committed_per_cycle::stdev 1.339217 # Number of insts commited each cycle
809system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
810system.cpu0.commit.committed_per_cycle::0 140546392 69.43% 69.43% # Number of insts commited each cycle
811system.cpu0.commit.committed_per_cycle::1 34245976 16.92% 86.34% # Number of insts commited each cycle
812system.cpu0.commit.committed_per_cycle::2 12926596 6.39% 92.73% # Number of insts commited each cycle
813system.cpu0.commit.committed_per_cycle::3 3383235 1.67% 94.40% # Number of insts commited each cycle
814system.cpu0.commit.committed_per_cycle::4 4977119 2.46% 96.86% # Number of insts commited each cycle
815system.cpu0.commit.committed_per_cycle::5 2872114 1.42% 98.28% # Number of insts commited each cycle
816system.cpu0.commit.committed_per_cycle::6 1322991 0.65% 98.93% # Number of insts commited each cycle
817system.cpu0.commit.committed_per_cycle::7 578946 0.29% 99.21% # Number of insts commited each cycle
818system.cpu0.commit.committed_per_cycle::8 1589626 0.79% 100.00% # Number of insts commited each cycle
819system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
820system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
821system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
822system.cpu0.commit.committed_per_cycle::total 202442995 # Number of insts commited each cycle
823system.cpu0.commit.committedInsts 106684229 # Number of instructions committed
824system.cpu0.commit.committedOps 129225495 # Number of ops (including micro ops) committed
825system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
826system.cpu0.commit.refs 42053222 # Number of memory references committed
827system.cpu0.commit.loads 23327941 # Number of loads committed
828system.cpu0.commit.membars 666720 # Number of memory barriers committed
829system.cpu0.commit.branches 25467916 # Number of branches committed
830system.cpu0.commit.fp_insts 11428 # Number of committed floating point instructions.
831system.cpu0.commit.int_insts 112793765 # Number of committed integer instructions.
832system.cpu0.commit.function_calls 4892953 # Number of function calls committed.
833system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
834system.cpu0.commit.op_class_0::IntAlu 87052485 67.36% 67.36% # Class of committed instruction
835system.cpu0.commit.op_class_0::IntMult 111545 0.09% 67.45% # Class of committed instruction
836system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.45% # Class of committed instruction
837system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.45% # Class of committed instruction
838system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.45% # Class of committed instruction
839system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.45% # Class of committed instruction
840system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.45% # Class of committed instruction
841system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.45% # Class of committed instruction
842system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.45% # Class of committed instruction
843system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.45% # Class of committed instruction
844system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.45% # Class of committed instruction
845system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.45% # Class of committed instruction
846system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.45% # Class of committed instruction
847system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.45% # Class of committed instruction
848system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.45% # Class of committed instruction
849system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.45% # Class of committed instruction
850system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.45% # Class of committed instruction
851system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.45% # Class of committed instruction
852system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.45% # Class of committed instruction
853system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.45% # Class of committed instruction
854system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.45% # Class of committed instruction
855system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.45% # Class of committed instruction
856system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.45% # Class of committed instruction
857system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.45% # Class of committed instruction
858system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.45% # Class of committed instruction
859system.cpu0.commit.op_class_0::SimdFloatMisc 8243 0.01% 67.46% # Class of committed instruction
860system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.46% # Class of committed instruction
861system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.46% # Class of committed instruction
862system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.46% # Class of committed instruction
863system.cpu0.commit.op_class_0::MemRead 23327941 18.05% 85.51% # Class of committed instruction
864system.cpu0.commit.op_class_0::MemWrite 18725281 14.49% 100.00% # Class of committed instruction
865system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
866system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
867system.cpu0.commit.op_class_0::total 129225495 # Class of committed instruction
868system.cpu0.commit.bw_lim_events 1589626 # number cycles where commit BW limit reached
869system.cpu0.rob.rob_reads 316721982 # The number of ROB reads
870system.cpu0.rob.rob_writes 281765642 # The number of ROB writes
871system.cpu0.timesIdled 131866 # Number of times that the entire CPU went into an idle state and unscheduled itself
872system.cpu0.idleCycles 5115510 # Total number of cycles that the CPU has spent unscheduled due to idling
873system.cpu0.quiesceCycles 5443972636 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
874system.cpu0.committedInsts 106532386 # Number of Instructions Simulated
875system.cpu0.committedOps 129073652 # Number of Ops (including micro ops) Simulated
876system.cpu0.cpi 1.978816 # CPI: Cycles Per Instruction
877system.cpu0.cpi_total 1.978816 # CPI: Total CPI of All Threads
878system.cpu0.ipc 0.505353 # IPC: Instructions Per Cycle
879system.cpu0.ipc_total 0.505353 # IPC: Total IPC of All Threads
880system.cpu0.int_regfile_reads 146797472 # number of integer regfile reads
881system.cpu0.int_regfile_writes 83857123 # number of integer regfile writes
882system.cpu0.fp_regfile_reads 9583 # number of floating regfile reads
883system.cpu0.fp_regfile_writes 2716 # number of floating regfile writes
884system.cpu0.cc_regfile_reads 477737826 # number of cc regfile reads
885system.cpu0.cc_regfile_writes 51222601 # number of cc regfile writes
886system.cpu0.misc_regfile_reads 282455977 # number of misc regfile reads
887system.cpu0.misc_regfile_writes 1264842 # number of misc regfile writes
888system.cpu0.dcache.tags.replacements 752726 # number of replacements
889system.cpu0.dcache.tags.tagsinuse 494.858519 # Cycle average of tags in use
890system.cpu0.dcache.tags.total_refs 38773458 # Total number of references to valid blocks.
891system.cpu0.dcache.tags.sampled_refs 753238 # Sample count of references to valid blocks.
892system.cpu0.dcache.tags.avg_refs 51.475706 # Average number of references to valid blocks.
893system.cpu0.dcache.tags.warmup_cycle 426635500 # Cycle when the warmup percentage was hit.
894system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.858519 # Average occupied blocks per requestor
895system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966521 # Average percentage of cache occupancy
896system.cpu0.dcache.tags.occ_percent::total 0.966521 # Average percentage of cache occupancy
897system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
898system.cpu0.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id
899system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id
900system.cpu0.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
901system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
902system.cpu0.dcache.tags.tag_accesses 83704103 # Number of tag accesses
903system.cpu0.dcache.tags.data_accesses 83704103 # Number of data accesses
904system.cpu0.dcache.ReadReq_hits::cpu0.data 22086605 # number of ReadReq hits
905system.cpu0.dcache.ReadReq_hits::total 22086605 # number of ReadReq hits
906system.cpu0.dcache.WriteReq_hits::cpu0.data 15435818 # number of WriteReq hits
907system.cpu0.dcache.WriteReq_hits::total 15435818 # number of WriteReq hits
908system.cpu0.dcache.SoftPFReq_hits::cpu0.data 316186 # number of SoftPFReq hits
909system.cpu0.dcache.SoftPFReq_hits::total 316186 # number of SoftPFReq hits
910system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 372593 # number of LoadLockedReq hits
911system.cpu0.dcache.LoadLockedReq_hits::total 372593 # number of LoadLockedReq hits
912system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370988 # number of StoreCondReq hits
913system.cpu0.dcache.StoreCondReq_hits::total 370988 # number of StoreCondReq hits
914system.cpu0.dcache.demand_hits::cpu0.data 37522423 # number of demand (read+write) hits
915system.cpu0.dcache.demand_hits::total 37522423 # number of demand (read+write) hits
916system.cpu0.dcache.overall_hits::cpu0.data 37838609 # number of overall hits
917system.cpu0.dcache.overall_hits::total 37838609 # number of overall hits
918system.cpu0.dcache.ReadReq_misses::cpu0.data 688506 # number of ReadReq misses
919system.cpu0.dcache.ReadReq_misses::total 688506 # number of ReadReq misses
920system.cpu0.dcache.WriteReq_misses::cpu0.data 1977745 # number of WriteReq misses
921system.cpu0.dcache.WriteReq_misses::total 1977745 # number of WriteReq misses
922system.cpu0.dcache.SoftPFReq_misses::cpu0.data 154100 # number of SoftPFReq misses
923system.cpu0.dcache.SoftPFReq_misses::total 154100 # number of SoftPFReq misses
924system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25656 # number of LoadLockedReq misses
925system.cpu0.dcache.LoadLockedReq_misses::total 25656 # number of LoadLockedReq misses
926system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20273 # number of StoreCondReq misses
927system.cpu0.dcache.StoreCondReq_misses::total 20273 # number of StoreCondReq misses
928system.cpu0.dcache.demand_misses::cpu0.data 2666251 # number of demand (read+write) misses
929system.cpu0.dcache.demand_misses::total 2666251 # number of demand (read+write) misses
930system.cpu0.dcache.overall_misses::cpu0.data 2820351 # number of overall misses
931system.cpu0.dcache.overall_misses::total 2820351 # number of overall misses
932system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9974637500 # number of ReadReq miss cycles
933system.cpu0.dcache.ReadReq_miss_latency::total 9974637500 # number of ReadReq miss cycles
934system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36928416860 # number of WriteReq miss cycles
935system.cpu0.dcache.WriteReq_miss_latency::total 36928416860 # number of WriteReq miss cycles
936system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 417346500 # number of LoadLockedReq miss cycles
937system.cpu0.dcache.LoadLockedReq_miss_latency::total 417346500 # number of LoadLockedReq miss cycles
938system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 525290500 # number of StoreCondReq miss cycles
939system.cpu0.dcache.StoreCondReq_miss_latency::total 525290500 # number of StoreCondReq miss cycles
940system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 179000 # number of StoreCondFailReq miss cycles
941system.cpu0.dcache.StoreCondFailReq_miss_latency::total 179000 # number of StoreCondFailReq miss cycles
942system.cpu0.dcache.demand_miss_latency::cpu0.data 46903054360 # number of demand (read+write) miss cycles
943system.cpu0.dcache.demand_miss_latency::total 46903054360 # number of demand (read+write) miss cycles
944system.cpu0.dcache.overall_miss_latency::cpu0.data 46903054360 # number of overall miss cycles
945system.cpu0.dcache.overall_miss_latency::total 46903054360 # number of overall miss cycles
946system.cpu0.dcache.ReadReq_accesses::cpu0.data 22775111 # number of ReadReq accesses(hits+misses)
947system.cpu0.dcache.ReadReq_accesses::total 22775111 # number of ReadReq accesses(hits+misses)
948system.cpu0.dcache.WriteReq_accesses::cpu0.data 17413563 # number of WriteReq accesses(hits+misses)
949system.cpu0.dcache.WriteReq_accesses::total 17413563 # number of WriteReq accesses(hits+misses)
950system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 470286 # number of SoftPFReq accesses(hits+misses)
951system.cpu0.dcache.SoftPFReq_accesses::total 470286 # number of SoftPFReq accesses(hits+misses)
952system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 398249 # number of LoadLockedReq accesses(hits+misses)
953system.cpu0.dcache.LoadLockedReq_accesses::total 398249 # number of LoadLockedReq accesses(hits+misses)
954system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391261 # number of StoreCondReq accesses(hits+misses)
955system.cpu0.dcache.StoreCondReq_accesses::total 391261 # number of StoreCondReq accesses(hits+misses)
956system.cpu0.dcache.demand_accesses::cpu0.data 40188674 # number of demand (read+write) accesses
957system.cpu0.dcache.demand_accesses::total 40188674 # number of demand (read+write) accesses
958system.cpu0.dcache.overall_accesses::cpu0.data 40658960 # number of overall (read+write) accesses
959system.cpu0.dcache.overall_accesses::total 40658960 # number of overall (read+write) accesses
960system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030231 # miss rate for ReadReq accesses
961system.cpu0.dcache.ReadReq_miss_rate::total 0.030231 # miss rate for ReadReq accesses
962system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.113575 # miss rate for WriteReq accesses
963system.cpu0.dcache.WriteReq_miss_rate::total 0.113575 # miss rate for WriteReq accesses
964system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.327673 # miss rate for SoftPFReq accesses
965system.cpu0.dcache.SoftPFReq_miss_rate::total 0.327673 # miss rate for SoftPFReq accesses
966system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064422 # miss rate for LoadLockedReq accesses
967system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064422 # miss rate for LoadLockedReq accesses
968system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051815 # miss rate for StoreCondReq accesses
969system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051815 # miss rate for StoreCondReq accesses
970system.cpu0.dcache.demand_miss_rate::cpu0.data 0.066343 # miss rate for demand accesses
971system.cpu0.dcache.demand_miss_rate::total 0.066343 # miss rate for demand accesses
972system.cpu0.dcache.overall_miss_rate::cpu0.data 0.069366 # miss rate for overall accesses
973system.cpu0.dcache.overall_miss_rate::total 0.069366 # miss rate for overall accesses
974system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14487.364671 # average ReadReq miss latency
975system.cpu0.dcache.ReadReq_avg_miss_latency::total 14487.364671 # average ReadReq miss latency
976system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18671.980897 # average WriteReq miss latency
977system.cpu0.dcache.WriteReq_avg_miss_latency::total 18671.980897 # average WriteReq miss latency
978system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16267.013564 # average LoadLockedReq miss latency
979system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16267.013564 # average LoadLockedReq miss latency
980system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25910.842007 # average StoreCondReq miss latency
981system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25910.842007 # average StoreCondReq miss latency
982system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
983system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
984system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17591.387443 # average overall miss latency
985system.cpu0.dcache.demand_avg_miss_latency::total 17591.387443 # average overall miss latency
986system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16630.218849 # average overall miss latency
987system.cpu0.dcache.overall_avg_miss_latency::total 16630.218849 # average overall miss latency
988system.cpu0.dcache.blocked_cycles::no_mshrs 989 # number of cycles access was blocked
989system.cpu0.dcache.blocked_cycles::no_targets 5684279 # number of cycles access was blocked
990system.cpu0.dcache.blocked::no_mshrs 52 # number of cycles access was blocked
991system.cpu0.dcache.blocked::no_targets 212555 # number of cycles access was blocked
992system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.019231 # average number of cycles each access was blocked
993system.cpu0.dcache.avg_blocked_cycles::no_targets 26.742627 # average number of cycles each access was blocked
994system.cpu0.dcache.fast_writes 0 # number of fast writes performed
995system.cpu0.dcache.cache_copies 0 # number of cache copies performed
996system.cpu0.dcache.writebacks::writebacks 752726 # number of writebacks
997system.cpu0.dcache.writebacks::total 752726 # number of writebacks
998system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276877 # number of ReadReq MSHR hits
999system.cpu0.dcache.ReadReq_mshr_hits::total 276877 # number of ReadReq MSHR hits
1000system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1641015 # number of WriteReq MSHR hits
1001system.cpu0.dcache.WriteReq_mshr_hits::total 1641015 # number of WriteReq MSHR hits
1002system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18966 # number of LoadLockedReq MSHR hits
1003system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18966 # number of LoadLockedReq MSHR hits
1004system.cpu0.dcache.demand_mshr_hits::cpu0.data 1917892 # number of demand (read+write) MSHR hits
1005system.cpu0.dcache.demand_mshr_hits::total 1917892 # number of demand (read+write) MSHR hits
1006system.cpu0.dcache.overall_mshr_hits::cpu0.data 1917892 # number of overall MSHR hits
1007system.cpu0.dcache.overall_mshr_hits::total 1917892 # number of overall MSHR hits
1008system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 411629 # number of ReadReq MSHR misses
1009system.cpu0.dcache.ReadReq_mshr_misses::total 411629 # number of ReadReq MSHR misses
1010system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 336730 # number of WriteReq MSHR misses
1011system.cpu0.dcache.WriteReq_mshr_misses::total 336730 # number of WriteReq MSHR misses
1012system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 107461 # number of SoftPFReq MSHR misses
1013system.cpu0.dcache.SoftPFReq_mshr_misses::total 107461 # number of SoftPFReq MSHR misses
1014system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6690 # number of LoadLockedReq MSHR misses
1015system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6690 # number of LoadLockedReq MSHR misses
1016system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20273 # number of StoreCondReq MSHR misses
1017system.cpu0.dcache.StoreCondReq_mshr_misses::total 20273 # number of StoreCondReq MSHR misses
1018system.cpu0.dcache.demand_mshr_misses::cpu0.data 748359 # number of demand (read+write) MSHR misses
1019system.cpu0.dcache.demand_mshr_misses::total 748359 # number of demand (read+write) MSHR misses
1020system.cpu0.dcache.overall_mshr_misses::cpu0.data 855820 # number of overall MSHR misses
1021system.cpu0.dcache.overall_mshr_misses::total 855820 # number of overall MSHR misses
1022system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31816 # number of ReadReq MSHR uncacheable
1023system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31816 # number of ReadReq MSHR uncacheable
1024system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable
1025system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable
1026system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60315 # number of overall MSHR uncacheable misses
1027system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60315 # number of overall MSHR uncacheable misses
1028system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5149646500 # number of ReadReq MSHR miss cycles
1029system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5149646500 # number of ReadReq MSHR miss cycles
1030system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7737247391 # number of WriteReq MSHR miss cycles
1031system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7737247391 # number of WriteReq MSHR miss cycles
1032system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1800196500 # number of SoftPFReq MSHR miss cycles
1033system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1800196500 # number of SoftPFReq MSHR miss cycles
1034system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 108932500 # number of LoadLockedReq MSHR miss cycles
1035system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 108932500 # number of LoadLockedReq MSHR miss cycles
1036system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 505022500 # number of StoreCondReq MSHR miss cycles
1037system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 505022500 # number of StoreCondReq MSHR miss cycles
1038system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 174000 # number of StoreCondFailReq MSHR miss cycles
1039system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 174000 # number of StoreCondFailReq MSHR miss cycles
1040system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12886893891 # number of demand (read+write) MSHR miss cycles
1041system.cpu0.dcache.demand_mshr_miss_latency::total 12886893891 # number of demand (read+write) MSHR miss cycles
1042system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14687090391 # number of overall MSHR miss cycles
1043system.cpu0.dcache.overall_mshr_miss_latency::total 14687090391 # number of overall MSHR miss cycles
1044system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6623903000 # number of ReadReq MSHR uncacheable cycles
1045system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6623903000 # number of ReadReq MSHR uncacheable cycles
1046system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5395425500 # number of WriteReq MSHR uncacheable cycles
1047system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5395425500 # number of WriteReq MSHR uncacheable cycles
1048system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12019328500 # number of overall MSHR uncacheable cycles
1049system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12019328500 # number of overall MSHR uncacheable cycles
1050system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.018074 # mshr miss rate for ReadReq accesses
1051system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.018074 # mshr miss rate for ReadReq accesses
1052system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019337 # mshr miss rate for WriteReq accesses
1053system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019337 # mshr miss rate for WriteReq accesses
1054system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228501 # mshr miss rate for SoftPFReq accesses
1055system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228501 # mshr miss rate for SoftPFReq accesses
1056system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016799 # mshr miss rate for LoadLockedReq accesses
1057system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016799 # mshr miss rate for LoadLockedReq accesses
1058system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051815 # mshr miss rate for StoreCondReq accesses
1059system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051815 # mshr miss rate for StoreCondReq accesses
1060system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018621 # mshr miss rate for demand accesses
1061system.cpu0.dcache.demand_mshr_miss_rate::total 0.018621 # mshr miss rate for demand accesses
1062system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.021049 # mshr miss rate for overall accesses
1063system.cpu0.dcache.overall_mshr_miss_rate::total 0.021049 # mshr miss rate for overall accesses
1064system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12510.407430 # average ReadReq mshr miss latency
1065system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12510.407430 # average ReadReq mshr miss latency
1066system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22977.600425 # average WriteReq mshr miss latency
1067system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22977.600425 # average WriteReq mshr miss latency
1068system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16752.091456 # average SoftPFReq mshr miss latency
1069system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16752.091456 # average SoftPFReq mshr miss latency
1070system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16282.884903 # average LoadLockedReq mshr miss latency
1071system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16282.884903 # average LoadLockedReq mshr miss latency
1072system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24911.088640 # average StoreCondReq mshr miss latency
1073system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24911.088640 # average StoreCondReq mshr miss latency
1074system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
1075system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1076system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17220.202992 # average overall mshr miss latency
1077system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17220.202992 # average overall mshr miss latency
1078system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17161.424588 # average overall mshr miss latency
1079system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17161.424588 # average overall mshr miss latency
1080system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208194.084737 # average ReadReq mshr uncacheable latency
1081system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208194.084737 # average ReadReq mshr uncacheable latency
1082system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189319.818239 # average WriteReq mshr uncacheable latency
1083system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189319.818239 # average WriteReq mshr uncacheable latency
1084system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199275.942966 # average overall mshr uncacheable latency
1085system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199275.942966 # average overall mshr uncacheable latency
1086system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1087system.cpu0.icache.tags.replacements 1311471 # number of replacements
1088system.cpu0.icache.tags.tagsinuse 511.728689 # Cycle average of tags in use
1089system.cpu0.icache.tags.total_refs 72677991 # Total number of references to valid blocks.
1090system.cpu0.icache.tags.sampled_refs 1311983 # Sample count of references to valid blocks.
1091system.cpu0.icache.tags.avg_refs 55.395528 # Average number of references to valid blocks.
1092system.cpu0.icache.tags.warmup_cycle 8207383000 # Cycle when the warmup percentage was hit.
1093system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.728689 # Average occupied blocks per requestor
1094system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999470 # Average percentage of cache occupancy
1095system.cpu0.icache.tags.occ_percent::total 0.999470 # Average percentage of cache occupancy
1096system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1097system.cpu0.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id
1098system.cpu0.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id
1099system.cpu0.icache.tags.age_task_id_blocks_1024::2 124 # Occupied blocks per task id
1100system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1101system.cpu0.icache.tags.tag_accesses 149404895 # Number of tag accesses
1102system.cpu0.icache.tags.data_accesses 149404895 # Number of data accesses
1103system.cpu0.icache.ReadReq_hits::cpu0.inst 72677991 # number of ReadReq hits
1104system.cpu0.icache.ReadReq_hits::total 72677991 # number of ReadReq hits
1105system.cpu0.icache.demand_hits::cpu0.inst 72677991 # number of demand (read+write) hits
1106system.cpu0.icache.demand_hits::total 72677991 # number of demand (read+write) hits
1107system.cpu0.icache.overall_hits::cpu0.inst 72677991 # number of overall hits
1108system.cpu0.icache.overall_hits::total 72677991 # number of overall hits
1109system.cpu0.icache.ReadReq_misses::cpu0.inst 1368448 # number of ReadReq misses
1110system.cpu0.icache.ReadReq_misses::total 1368448 # number of ReadReq misses
1111system.cpu0.icache.demand_misses::cpu0.inst 1368448 # number of demand (read+write) misses
1112system.cpu0.icache.demand_misses::total 1368448 # number of demand (read+write) misses
1113system.cpu0.icache.overall_misses::cpu0.inst 1368448 # number of overall misses
1114system.cpu0.icache.overall_misses::total 1368448 # number of overall misses
1115system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14924586060 # number of ReadReq miss cycles
1116system.cpu0.icache.ReadReq_miss_latency::total 14924586060 # number of ReadReq miss cycles
1117system.cpu0.icache.demand_miss_latency::cpu0.inst 14924586060 # number of demand (read+write) miss cycles
1118system.cpu0.icache.demand_miss_latency::total 14924586060 # number of demand (read+write) miss cycles
1119system.cpu0.icache.overall_miss_latency::cpu0.inst 14924586060 # number of overall miss cycles
1120system.cpu0.icache.overall_miss_latency::total 14924586060 # number of overall miss cycles
1121system.cpu0.icache.ReadReq_accesses::cpu0.inst 74046439 # number of ReadReq accesses(hits+misses)
1122system.cpu0.icache.ReadReq_accesses::total 74046439 # number of ReadReq accesses(hits+misses)
1123system.cpu0.icache.demand_accesses::cpu0.inst 74046439 # number of demand (read+write) accesses
1124system.cpu0.icache.demand_accesses::total 74046439 # number of demand (read+write) accesses
1125system.cpu0.icache.overall_accesses::cpu0.inst 74046439 # number of overall (read+write) accesses
1126system.cpu0.icache.overall_accesses::total 74046439 # number of overall (read+write) accesses
1127system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.018481 # miss rate for ReadReq accesses
1128system.cpu0.icache.ReadReq_miss_rate::total 0.018481 # miss rate for ReadReq accesses
1129system.cpu0.icache.demand_miss_rate::cpu0.inst 0.018481 # miss rate for demand accesses
1130system.cpu0.icache.demand_miss_rate::total 0.018481 # miss rate for demand accesses
1131system.cpu0.icache.overall_miss_rate::cpu0.inst 0.018481 # miss rate for overall accesses
1132system.cpu0.icache.overall_miss_rate::total 0.018481 # miss rate for overall accesses
1133system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10906.213506 # average ReadReq miss latency
1134system.cpu0.icache.ReadReq_avg_miss_latency::total 10906.213506 # average ReadReq miss latency
1135system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10906.213506 # average overall miss latency
1136system.cpu0.icache.demand_avg_miss_latency::total 10906.213506 # average overall miss latency
1137system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10906.213506 # average overall miss latency
1138system.cpu0.icache.overall_avg_miss_latency::total 10906.213506 # average overall miss latency
1139system.cpu0.icache.blocked_cycles::no_mshrs 1977903 # number of cycles access was blocked
1140system.cpu0.icache.blocked_cycles::no_targets 1805 # number of cycles access was blocked
1141system.cpu0.icache.blocked::no_mshrs 120515 # number of cycles access was blocked
1142system.cpu0.icache.blocked::no_targets 16 # number of cycles access was blocked
1143system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.412090 # average number of cycles each access was blocked
1144system.cpu0.icache.avg_blocked_cycles::no_targets 112.812500 # average number of cycles each access was blocked
1145system.cpu0.icache.fast_writes 0 # number of fast writes performed
1146system.cpu0.icache.cache_copies 0 # number of cache copies performed
1147system.cpu0.icache.writebacks::writebacks 1311471 # number of writebacks
1148system.cpu0.icache.writebacks::total 1311471 # number of writebacks
1149system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 56430 # number of ReadReq MSHR hits
1150system.cpu0.icache.ReadReq_mshr_hits::total 56430 # number of ReadReq MSHR hits
1151system.cpu0.icache.demand_mshr_hits::cpu0.inst 56430 # number of demand (read+write) MSHR hits
1152system.cpu0.icache.demand_mshr_hits::total 56430 # number of demand (read+write) MSHR hits
1153system.cpu0.icache.overall_mshr_hits::cpu0.inst 56430 # number of overall MSHR hits
1154system.cpu0.icache.overall_mshr_hits::total 56430 # number of overall MSHR hits
1155system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1312018 # number of ReadReq MSHR misses
1156system.cpu0.icache.ReadReq_mshr_misses::total 1312018 # number of ReadReq MSHR misses
1157system.cpu0.icache.demand_mshr_misses::cpu0.inst 1312018 # number of demand (read+write) MSHR misses
1158system.cpu0.icache.demand_mshr_misses::total 1312018 # number of demand (read+write) MSHR misses
1159system.cpu0.icache.overall_mshr_misses::cpu0.inst 1312018 # number of overall MSHR misses
1160system.cpu0.icache.overall_mshr_misses::total 1312018 # number of overall MSHR misses
1161system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable
1162system.cpu0.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable
1163system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses
1164system.cpu0.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses
1165system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13396366068 # number of ReadReq MSHR miss cycles
1166system.cpu0.icache.ReadReq_mshr_miss_latency::total 13396366068 # number of ReadReq MSHR miss cycles
1167system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13396366068 # number of demand (read+write) MSHR miss cycles
1168system.cpu0.icache.demand_mshr_miss_latency::total 13396366068 # number of demand (read+write) MSHR miss cycles
1169system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13396366068 # number of overall MSHR miss cycles
1170system.cpu0.icache.overall_mshr_miss_latency::total 13396366068 # number of overall MSHR miss cycles
1171system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 420576498 # number of ReadReq MSHR uncacheable cycles
1172system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 420576498 # number of ReadReq MSHR uncacheable cycles
1173system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 420576498 # number of overall MSHR uncacheable cycles
1174system.cpu0.icache.overall_mshr_uncacheable_latency::total 420576498 # number of overall MSHR uncacheable cycles
1175system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017719 # mshr miss rate for ReadReq accesses
1176system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017719 # mshr miss rate for ReadReq accesses
1177system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017719 # mshr miss rate for demand accesses
1178system.cpu0.icache.demand_mshr_miss_rate::total 0.017719 # mshr miss rate for demand accesses
1179system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017719 # mshr miss rate for overall accesses
1180system.cpu0.icache.overall_mshr_miss_rate::total 0.017719 # mshr miss rate for overall accesses
1181system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10210.504786 # average ReadReq mshr miss latency
1182system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10210.504786 # average ReadReq mshr miss latency
1183system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10210.504786 # average overall mshr miss latency
1184system.cpu0.icache.demand_avg_mshr_miss_latency::total 10210.504786 # average overall mshr miss latency
1185system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10210.504786 # average overall mshr miss latency
1186system.cpu0.icache.overall_avg_mshr_miss_latency::total 10210.504786 # average overall mshr miss latency
1187system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140052.113886 # average ReadReq mshr uncacheable latency
1188system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140052.113886 # average ReadReq mshr uncacheable latency
1189system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140052.113886 # average overall mshr uncacheable latency
1190system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140052.113886 # average overall mshr uncacheable latency
1191system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1192system.cpu0.l2cache.prefetcher.num_hwpf_issued 1932548 # number of hwpf issued
1193system.cpu0.l2cache.prefetcher.pfIdentified 1935408 # number of prefetch candidates identified
1194system.cpu0.l2cache.prefetcher.pfBufferHit 2604 # number of redundant prefetches already in prefetch queue
1195system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1196system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1197system.cpu0.l2cache.prefetcher.pfSpanPage 246016 # number of prefetches not generated due to page crossing
1198system.cpu0.l2cache.tags.replacements 282767 # number of replacements
1199system.cpu0.l2cache.tags.tagsinuse 16108.615116 # Cycle average of tags in use
1200system.cpu0.l2cache.tags.total_refs 3429175 # Total number of references to valid blocks.
1201system.cpu0.l2cache.tags.sampled_refs 298912 # Sample count of references to valid blocks.
1202system.cpu0.l2cache.tags.avg_refs 11.472189 # Average number of references to valid blocks.
1203system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1204system.cpu0.l2cache.tags.occ_blocks::writebacks 14681.579143 # Average occupied blocks per requestor
1205system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.440463 # Average occupied blocks per requestor
1206system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.496999 # Average occupied blocks per requestor
1207system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1415.098510 # Average occupied blocks per requestor
1208system.cpu0.l2cache.tags.occ_percent::writebacks 0.896092 # Average percentage of cache occupancy
1209system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000698 # Average percentage of cache occupancy
1210system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000030 # Average percentage of cache occupancy
1211system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.086371 # Average percentage of cache occupancy
1212system.cpu0.l2cache.tags.occ_percent::total 0.983192 # Average percentage of cache occupancy
1213system.cpu0.l2cache.tags.occ_task_id_blocks::1022 981 # Occupied blocks per task id
1214system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id
1215system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15155 # Occupied blocks per task id
1216system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 39 # Occupied blocks per task id
1217system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 298 # Occupied blocks per task id
1218system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 453 # Occupied blocks per task id
1219system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 191 # Occupied blocks per task id
1220system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id
1221system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
1222system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id
1223system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
1224system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 511 # Occupied blocks per task id
1225system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4586 # Occupied blocks per task id
1226system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7902 # Occupied blocks per task id
1227system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2036 # Occupied blocks per task id
1228system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.059875 # Percentage of cache occupancy per task id
1229system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id
1230system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.924988 # Percentage of cache occupancy per task id
1231system.cpu0.l2cache.tags.tag_accesses 69610425 # Number of tag accesses
1232system.cpu0.l2cache.tags.data_accesses 69610425 # Number of data accesses
1233system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 60495 # number of ReadReq hits
1234system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13905 # number of ReadReq hits
1235system.cpu0.l2cache.ReadReq_hits::total 74400 # number of ReadReq hits
1236system.cpu0.l2cache.WritebackDirty_hits::writebacks 507703 # number of WritebackDirty hits
1237system.cpu0.l2cache.WritebackDirty_hits::total 507703 # number of WritebackDirty hits
1238system.cpu0.l2cache.WritebackClean_hits::writebacks 1523854 # number of WritebackClean hits
1239system.cpu0.l2cache.WritebackClean_hits::total 1523854 # number of WritebackClean hits
1240system.cpu0.l2cache.ReadExReq_hits::cpu0.data 206993 # number of ReadExReq hits
1241system.cpu0.l2cache.ReadExReq_hits::total 206993 # number of ReadExReq hits
1242system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1258247 # number of ReadCleanReq hits
1243system.cpu0.l2cache.ReadCleanReq_hits::total 1258247 # number of ReadCleanReq hits
1244system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 428473 # number of ReadSharedReq hits
1245system.cpu0.l2cache.ReadSharedReq_hits::total 428473 # number of ReadSharedReq hits
1246system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 60495 # number of demand (read+write) hits
1247system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13905 # number of demand (read+write) hits
1248system.cpu0.l2cache.demand_hits::cpu0.inst 1258247 # number of demand (read+write) hits
1249system.cpu0.l2cache.demand_hits::cpu0.data 635466 # number of demand (read+write) hits
1250system.cpu0.l2cache.demand_hits::total 1968113 # number of demand (read+write) hits
1251system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 60495 # number of overall hits
1252system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13905 # number of overall hits
1253system.cpu0.l2cache.overall_hits::cpu0.inst 1258247 # number of overall hits
1254system.cpu0.l2cache.overall_hits::cpu0.data 635466 # number of overall hits
1255system.cpu0.l2cache.overall_hits::total 1968113 # number of overall hits
1256system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 354 # number of ReadReq misses
1257system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 125 # number of ReadReq misses
1258system.cpu0.l2cache.ReadReq_misses::total 479 # number of ReadReq misses
1259system.cpu0.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses
1260system.cpu0.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses
1261system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55429 # number of UpgradeReq misses
1262system.cpu0.l2cache.UpgradeReq_misses::total 55429 # number of UpgradeReq misses
1263system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20273 # number of SCUpgradeReq misses
1264system.cpu0.l2cache.SCUpgradeReq_misses::total 20273 # number of SCUpgradeReq misses
1265system.cpu0.l2cache.ReadExReq_misses::cpu0.data 74521 # number of ReadExReq misses
1266system.cpu0.l2cache.ReadExReq_misses::total 74521 # number of ReadExReq misses
1267system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 53742 # number of ReadCleanReq misses
1268system.cpu0.l2cache.ReadCleanReq_misses::total 53742 # number of ReadCleanReq misses
1269system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 97171 # number of ReadSharedReq misses
1270system.cpu0.l2cache.ReadSharedReq_misses::total 97171 # number of ReadSharedReq misses
1271system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 354 # number of demand (read+write) misses
1272system.cpu0.l2cache.demand_misses::cpu0.itb.walker 125 # number of demand (read+write) misses
1273system.cpu0.l2cache.demand_misses::cpu0.inst 53742 # number of demand (read+write) misses
1274system.cpu0.l2cache.demand_misses::cpu0.data 171692 # number of demand (read+write) misses
1275system.cpu0.l2cache.demand_misses::total 225913 # number of demand (read+write) misses
1276system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 354 # number of overall misses
1277system.cpu0.l2cache.overall_misses::cpu0.itb.walker 125 # number of overall misses
1278system.cpu0.l2cache.overall_misses::cpu0.inst 53742 # number of overall misses
1279system.cpu0.l2cache.overall_misses::cpu0.data 171692 # number of overall misses
1280system.cpu0.l2cache.overall_misses::total 225913 # number of overall misses
1281system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11980000 # number of ReadReq miss cycles
1282system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3266000 # number of ReadReq miss cycles
1283system.cpu0.l2cache.ReadReq_miss_latency::total 15246000 # number of ReadReq miss cycles
1284system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 178815000 # number of UpgradeReq miss cycles
1285system.cpu0.l2cache.UpgradeReq_miss_latency::total 178815000 # number of UpgradeReq miss cycles
1286system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 41943500 # number of SCUpgradeReq miss cycles
1287system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 41943500 # number of SCUpgradeReq miss cycles
1288system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 166500 # number of SCUpgradeFailReq miss cycles
1289system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 166500 # number of SCUpgradeFailReq miss cycles
1290system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 4097480997 # number of ReadExReq miss cycles
1291system.cpu0.l2cache.ReadExReq_miss_latency::total 4097480997 # number of ReadExReq miss cycles
1292system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3752300498 # number of ReadCleanReq miss cycles
1293system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3752300498 # number of ReadCleanReq miss cycles
1294system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3420930498 # number of ReadSharedReq miss cycles
1295system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3420930498 # number of ReadSharedReq miss cycles
1296system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11980000 # number of demand (read+write) miss cycles
1297system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3266000 # number of demand (read+write) miss cycles
1298system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3752300498 # number of demand (read+write) miss cycles
1299system.cpu0.l2cache.demand_miss_latency::cpu0.data 7518411495 # number of demand (read+write) miss cycles
1300system.cpu0.l2cache.demand_miss_latency::total 11285957993 # number of demand (read+write) miss cycles
1301system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11980000 # number of overall miss cycles
1302system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3266000 # number of overall miss cycles
1303system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3752300498 # number of overall miss cycles
1304system.cpu0.l2cache.overall_miss_latency::cpu0.data 7518411495 # number of overall miss cycles
1305system.cpu0.l2cache.overall_miss_latency::total 11285957993 # number of overall miss cycles
1306system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 60849 # number of ReadReq accesses(hits+misses)
1307system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 14030 # number of ReadReq accesses(hits+misses)
1308system.cpu0.l2cache.ReadReq_accesses::total 74879 # number of ReadReq accesses(hits+misses)
1309system.cpu0.l2cache.WritebackDirty_accesses::writebacks 507704 # number of WritebackDirty accesses(hits+misses)
1310system.cpu0.l2cache.WritebackDirty_accesses::total 507704 # number of WritebackDirty accesses(hits+misses)
1311system.cpu0.l2cache.WritebackClean_accesses::writebacks 1523854 # number of WritebackClean accesses(hits+misses)
1312system.cpu0.l2cache.WritebackClean_accesses::total 1523854 # number of WritebackClean accesses(hits+misses)
1313system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55429 # number of UpgradeReq accesses(hits+misses)
1314system.cpu0.l2cache.UpgradeReq_accesses::total 55429 # number of UpgradeReq accesses(hits+misses)
1315system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20273 # number of SCUpgradeReq accesses(hits+misses)
1316system.cpu0.l2cache.SCUpgradeReq_accesses::total 20273 # number of SCUpgradeReq accesses(hits+misses)
1317system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 281514 # number of ReadExReq accesses(hits+misses)
1318system.cpu0.l2cache.ReadExReq_accesses::total 281514 # number of ReadExReq accesses(hits+misses)
1319system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1311989 # number of ReadCleanReq accesses(hits+misses)
1320system.cpu0.l2cache.ReadCleanReq_accesses::total 1311989 # number of ReadCleanReq accesses(hits+misses)
1321system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 525644 # number of ReadSharedReq accesses(hits+misses)
1322system.cpu0.l2cache.ReadSharedReq_accesses::total 525644 # number of ReadSharedReq accesses(hits+misses)
1323system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 60849 # number of demand (read+write) accesses
1324system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 14030 # number of demand (read+write) accesses
1325system.cpu0.l2cache.demand_accesses::cpu0.inst 1311989 # number of demand (read+write) accesses
1326system.cpu0.l2cache.demand_accesses::cpu0.data 807158 # number of demand (read+write) accesses
1327system.cpu0.l2cache.demand_accesses::total 2194026 # number of demand (read+write) accesses
1328system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 60849 # number of overall (read+write) accesses
1329system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 14030 # number of overall (read+write) accesses
1330system.cpu0.l2cache.overall_accesses::cpu0.inst 1311989 # number of overall (read+write) accesses
1331system.cpu0.l2cache.overall_accesses::cpu0.data 807158 # number of overall (read+write) accesses
1332system.cpu0.l2cache.overall_accesses::total 2194026 # number of overall (read+write) accesses
1333system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.005818 # miss rate for ReadReq accesses
1334system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.008909 # miss rate for ReadReq accesses
1335system.cpu0.l2cache.ReadReq_miss_rate::total 0.006397 # miss rate for ReadReq accesses
1336system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000002 # miss rate for WritebackDirty accesses
1337system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000002 # miss rate for WritebackDirty accesses
1338system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
1339system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1340system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1341system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1342system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.264715 # miss rate for ReadExReq accesses
1343system.cpu0.l2cache.ReadExReq_miss_rate::total 0.264715 # miss rate for ReadExReq accesses
1344system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040962 # miss rate for ReadCleanReq accesses
1345system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040962 # miss rate for ReadCleanReq accesses
1346system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.184861 # miss rate for ReadSharedReq accesses
1347system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.184861 # miss rate for ReadSharedReq accesses
1348system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.005818 # miss rate for demand accesses
1349system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.008909 # miss rate for demand accesses
1350system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040962 # miss rate for demand accesses
1351system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.212712 # miss rate for demand accesses
1352system.cpu0.l2cache.demand_miss_rate::total 0.102967 # miss rate for demand accesses
1353system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.005818 # miss rate for overall accesses
1354system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.008909 # miss rate for overall accesses
1355system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040962 # miss rate for overall accesses
1356system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.212712 # miss rate for overall accesses
1357system.cpu0.l2cache.overall_miss_rate::total 0.102967 # miss rate for overall accesses
1358system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33841.807910 # average ReadReq miss latency
1359system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26128 # average ReadReq miss latency
1360system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31828.810021 # average ReadReq miss latency
1361system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3226.018871 # average UpgradeReq miss latency
1362system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3226.018871 # average UpgradeReq miss latency
1363system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2068.934050 # average SCUpgradeReq miss latency
1364system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2068.934050 # average SCUpgradeReq miss latency
1365system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency
1366system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
1367system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54984.246011 # average ReadExReq miss latency
1368system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54984.246011 # average ReadExReq miss latency
1369system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 69820.633732 # average ReadCleanReq miss latency
1370system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 69820.633732 # average ReadCleanReq miss latency
1371system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35205.261837 # average ReadSharedReq miss latency
1372system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35205.261837 # average ReadSharedReq miss latency
1373system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33841.807910 # average overall miss latency
1374system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26128 # average overall miss latency
1375system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 69820.633732 # average overall miss latency
1376system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43790.109586 # average overall miss latency
1377system.cpu0.l2cache.demand_avg_miss_latency::total 49957.098498 # average overall miss latency
1378system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33841.807910 # average overall miss latency
1379system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26128 # average overall miss latency
1380system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 69820.633732 # average overall miss latency
1381system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43790.109586 # average overall miss latency
1382system.cpu0.l2cache.overall_avg_miss_latency::total 49957.098498 # average overall miss latency
1383system.cpu0.l2cache.blocked_cycles::no_mshrs 204 # number of cycles access was blocked
1384system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1385system.cpu0.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked
1386system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1387system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
1388system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1389system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1390system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1391system.cpu0.l2cache.unused_prefetches 10407 # number of HardPF blocks evicted w/o reference
1392system.cpu0.l2cache.writebacks::writebacks 233202 # number of writebacks
1393system.cpu0.l2cache.writebacks::total 233202 # number of writebacks
1394system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
1395system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
1396system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 32963 # number of ReadExReq MSHR hits
1397system.cpu0.l2cache.ReadExReq_mshr_hits::total 32963 # number of ReadExReq MSHR hits
1398system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 42 # number of ReadCleanReq MSHR hits
1399system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 42 # number of ReadCleanReq MSHR hits
1400system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 774 # number of ReadSharedReq MSHR hits
1401system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 774 # number of ReadSharedReq MSHR hits
1402system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
1403system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 42 # number of demand (read+write) MSHR hits
1404system.cpu0.l2cache.demand_mshr_hits::cpu0.data 33737 # number of demand (read+write) MSHR hits
1405system.cpu0.l2cache.demand_mshr_hits::total 33780 # number of demand (read+write) MSHR hits
1406system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
1407system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 42 # number of overall MSHR hits
1408system.cpu0.l2cache.overall_mshr_hits::cpu0.data 33737 # number of overall MSHR hits
1409system.cpu0.l2cache.overall_mshr_hits::total 33780 # number of overall MSHR hits
1410system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 353 # number of ReadReq MSHR misses
1411system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 125 # number of ReadReq MSHR misses
1412system.cpu0.l2cache.ReadReq_mshr_misses::total 478 # number of ReadReq MSHR misses
1413system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses
1414system.cpu0.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses
1415system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 262414 # number of HardPFReq MSHR misses
1416system.cpu0.l2cache.HardPFReq_mshr_misses::total 262414 # number of HardPFReq MSHR misses
1417system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55429 # number of UpgradeReq MSHR misses
1418system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55429 # number of UpgradeReq MSHR misses
1419system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20273 # number of SCUpgradeReq MSHR misses
1420system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20273 # number of SCUpgradeReq MSHR misses
1421system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41558 # number of ReadExReq MSHR misses
1422system.cpu0.l2cache.ReadExReq_mshr_misses::total 41558 # number of ReadExReq MSHR misses
1423system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 53700 # number of ReadCleanReq MSHR misses
1424system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 53700 # number of ReadCleanReq MSHR misses
1425system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 96397 # number of ReadSharedReq MSHR misses
1426system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 96397 # number of ReadSharedReq MSHR misses
1427system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 353 # number of demand (read+write) MSHR misses
1428system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 125 # number of demand (read+write) MSHR misses
1429system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 53700 # number of demand (read+write) MSHR misses
1430system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137955 # number of demand (read+write) MSHR misses
1431system.cpu0.l2cache.demand_mshr_misses::total 192133 # number of demand (read+write) MSHR misses
1432system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 353 # number of overall MSHR misses
1433system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 125 # number of overall MSHR misses
1434system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 53700 # number of overall MSHR misses
1435system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137955 # number of overall MSHR misses
1436system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 262414 # number of overall MSHR misses
1437system.cpu0.l2cache.overall_mshr_misses::total 454547 # number of overall MSHR misses
1438system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable
1439system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31816 # number of ReadReq MSHR uncacheable
1440system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 34819 # number of ReadReq MSHR uncacheable
1441system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable
1442system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable
1443system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses
1444system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60315 # number of overall MSHR uncacheable misses
1445system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63318 # number of overall MSHR uncacheable misses
1446system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 9841000 # number of ReadReq MSHR miss cycles
1447system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2516000 # number of ReadReq MSHR miss cycles
1448system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 12357000 # number of ReadReq MSHR miss cycles
1449system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 22141788258 # number of HardPFReq MSHR miss cycles
1450system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 22141788258 # number of HardPFReq MSHR miss cycles
1451system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1433561500 # number of UpgradeReq MSHR miss cycles
1452system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1433561500 # number of UpgradeReq MSHR miss cycles
1453system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 351805000 # number of SCUpgradeReq MSHR miss cycles
1454system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 351805000 # number of SCUpgradeReq MSHR miss cycles
1455system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 136500 # number of SCUpgradeFailReq MSHR miss cycles
1456system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 136500 # number of SCUpgradeFailReq MSHR miss cycles
1457system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2493972500 # number of ReadExReq MSHR miss cycles
1458system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2493972500 # number of ReadExReq MSHR miss cycles
1459system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3428273498 # number of ReadCleanReq MSHR miss cycles
1460system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3428273498 # number of ReadCleanReq MSHR miss cycles
1461system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2782772498 # number of ReadSharedReq MSHR miss cycles
1462system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2782772498 # number of ReadSharedReq MSHR miss cycles
1463system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 9841000 # number of demand (read+write) MSHR miss cycles
1464system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2516000 # number of demand (read+write) MSHR miss cycles
1465system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3428273498 # number of demand (read+write) MSHR miss cycles
1466system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5276744998 # number of demand (read+write) MSHR miss cycles
1467system.cpu0.l2cache.demand_mshr_miss_latency::total 8717375496 # number of demand (read+write) MSHR miss cycles
1468system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 9841000 # number of overall MSHR miss cycles
1469system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2516000 # number of overall MSHR miss cycles
1470system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3428273498 # number of overall MSHR miss cycles
1471system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5276744998 # number of overall MSHR miss cycles
1472system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 22141788258 # number of overall MSHR miss cycles
1473system.cpu0.l2cache.overall_mshr_miss_latency::total 30859163754 # number of overall MSHR miss cycles
1474system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 398052500 # number of ReadReq MSHR uncacheable cycles
1475system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6369072500 # number of ReadReq MSHR uncacheable cycles
1476system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6767125000 # number of ReadReq MSHR uncacheable cycles
1477system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5178546465 # number of WriteReq MSHR uncacheable cycles
1478system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5178546465 # number of WriteReq MSHR uncacheable cycles
1479system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 398052500 # number of overall MSHR uncacheable cycles
1480system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11547618965 # number of overall MSHR uncacheable cycles
1481system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11945671465 # number of overall MSHR uncacheable cycles
1482system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005801 # mshr miss rate for ReadReq accesses
1483system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.008909 # mshr miss rate for ReadReq accesses
1484system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.006384 # mshr miss rate for ReadReq accesses
1485system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for WritebackDirty accesses
1486system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000002 # mshr miss rate for WritebackDirty accesses
1487system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1488system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1489system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
1490system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1491system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1492system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1493system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.147623 # mshr miss rate for ReadExReq accesses
1494system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.147623 # mshr miss rate for ReadExReq accesses
1495system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040930 # mshr miss rate for ReadCleanReq accesses
1496system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040930 # mshr miss rate for ReadCleanReq accesses
1497system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.183388 # mshr miss rate for ReadSharedReq accesses
1498system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.183388 # mshr miss rate for ReadSharedReq accesses
1499system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.005801 # mshr miss rate for demand accesses
1500system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.008909 # mshr miss rate for demand accesses
1501system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040930 # mshr miss rate for demand accesses
1502system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.170914 # mshr miss rate for demand accesses
1503system.cpu0.l2cache.demand_mshr_miss_rate::total 0.087571 # mshr miss rate for demand accesses
1504system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.005801 # mshr miss rate for overall accesses
1505system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.008909 # mshr miss rate for overall accesses
1506system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040930 # mshr miss rate for overall accesses
1507system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.170914 # mshr miss rate for overall accesses
1508system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1509system.cpu0.l2cache.overall_mshr_miss_rate::total 0.207175 # mshr miss rate for overall accesses
1510system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27878.186969 # average ReadReq mshr miss latency
1511system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20128 # average ReadReq mshr miss latency
1512system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25851.464435 # average ReadReq mshr miss latency
1513system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84377.313169 # average HardPFReq mshr miss latency
1514system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 84377.313169 # average HardPFReq mshr miss latency
1515system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25863.022966 # average UpgradeReq mshr miss latency
1516system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25863.022966 # average UpgradeReq mshr miss latency
1517system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17353.376412 # average SCUpgradeReq mshr miss latency
1518system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17353.376412 # average SCUpgradeReq mshr miss latency
1519system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency
1520system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
1521system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60011.850907 # average ReadExReq mshr miss latency
1522system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60011.850907 # average ReadExReq mshr miss latency
1523system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 63841.219702 # average ReadCleanReq mshr miss latency
1524system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63841.219702 # average ReadCleanReq mshr miss latency
1525system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28867.833003 # average ReadSharedReq mshr miss latency
1526system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28867.833003 # average ReadSharedReq mshr miss latency
1527system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27878.186969 # average overall mshr miss latency
1528system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20128 # average overall mshr miss latency
1529system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 63841.219702 # average overall mshr miss latency
1530system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38249.755341 # average overall mshr miss latency
1531system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 45371.568112 # average overall mshr miss latency
1532system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27878.186969 # average overall mshr miss latency
1533system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20128 # average overall mshr miss latency
1534system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 63841.219702 # average overall mshr miss latency
1535system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38249.755341 # average overall mshr miss latency
1536system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84377.313169 # average overall mshr miss latency
1537system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 67889.929433 # average overall mshr miss latency
1538system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132551.615052 # average ReadReq mshr uncacheable latency
1539system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200184.576942 # average ReadReq mshr uncacheable latency
1540system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194351.503489 # average ReadReq mshr uncacheable latency
1541system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181709.760518 # average WriteReq mshr uncacheable latency
1542system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181709.760518 # average WriteReq mshr uncacheable latency
1543system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132551.615052 # average overall mshr uncacheable latency
1544system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191455.176407 # average overall mshr uncacheable latency
1545system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188661.541189 # average overall mshr uncacheable latency
1546system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1547system.cpu0.toL2Bus.snoop_filter.tot_requests 4281853 # Total number of requests made to the snoop filter.
1548system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2162712 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1549system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 32662 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1550system.cpu0.toL2Bus.snoop_filter.tot_snoops 328300 # Total number of snoops made to the snoop filter.
1551system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 324452 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1552system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3848 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1553system.cpu0.toL2Bus.trans_dist::ReadReq 121117 # Transaction distribution
1554system.cpu0.toL2Bus.trans_dist::ReadResp 2006967 # Transaction distribution
1555system.cpu0.toL2Bus.trans_dist::WriteReq 28499 # Transaction distribution
1556system.cpu0.toL2Bus.trans_dist::WriteResp 28499 # Transaction distribution
1557system.cpu0.toL2Bus.trans_dist::WritebackDirty 741466 # Transaction distribution
1558system.cpu0.toL2Bus.trans_dist::WritebackClean 1556492 # Transaction distribution
1559system.cpu0.toL2Bus.trans_dist::CleanEvict 207602 # Transaction distribution
1560system.cpu0.toL2Bus.trans_dist::HardPFReq 320187 # Transaction distribution
1561system.cpu0.toL2Bus.trans_dist::UpgradeReq 85477 # Transaction distribution
1562system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42629 # Transaction distribution
1563system.cpu0.toL2Bus.trans_dist::UpgradeResp 113152 # Transaction distribution
1564system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 18 # Transaction distribution
1565system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
1566system.cpu0.toL2Bus.trans_dist::ReadExReq 299842 # Transaction distribution
1567system.cpu0.toL2Bus.trans_dist::ReadExResp 296502 # Transaction distribution
1568system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1312018 # Transaction distribution
1569system.cpu0.toL2Bus.trans_dist::ReadSharedReq 596340 # Transaction distribution
1570system.cpu0.toL2Bus.trans_dist::InvalidateReq 3402 # Transaction distribution
1571system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3941483 # Packet count per connected master and slave (bytes)
1572system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2739757 # Packet count per connected master and slave (bytes)
1573system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 30823 # Packet count per connected master and slave (bytes)
1574system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 130322 # Packet count per connected master and slave (bytes)
1575system.cpu0.toL2Bus.pkt_count::total 6842385 # Packet count per connected master and slave (bytes)
1576system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 167949424 # Cumulative packet size per connected master and slave (bytes)
1577system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104071122 # Cumulative packet size per connected master and slave (bytes)
1578system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 56120 # Cumulative packet size per connected master and slave (bytes)
1579system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 243396 # Cumulative packet size per connected master and slave (bytes)
1580system.cpu0.toL2Bus.pkt_size::total 272320062 # Cumulative packet size per connected master and slave (bytes)
1581system.cpu0.toL2Bus.snoops 1018529 # Total snoops (count)
1582system.cpu0.toL2Bus.snoop_fanout::samples 3250936 # Request fanout histogram
1583system.cpu0.toL2Bus.snoop_fanout::mean 0.119239 # Request fanout histogram
1584system.cpu0.toL2Bus.snoop_fanout::stdev 0.327701 # Request fanout histogram
1585system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1586system.cpu0.toL2Bus.snoop_fanout::0 2867147 88.19% 88.19% # Request fanout histogram
1587system.cpu0.toL2Bus.snoop_fanout::1 379941 11.69% 99.88% # Request fanout histogram
1588system.cpu0.toL2Bus.snoop_fanout::2 3848 0.12% 100.00% # Request fanout histogram
1589system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1590system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1591system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1592system.cpu0.toL2Bus.snoop_fanout::total 3250936 # Request fanout histogram
1593system.cpu0.toL2Bus.reqLayer0.occupancy 4282821452 # Layer occupancy (ticks)
1594system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
1595system.cpu0.toL2Bus.snoopLayer0.occupancy 113625688 # Layer occupancy (ticks)
1596system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1597system.cpu0.toL2Bus.respLayer0.occupancy 1971630792 # Layer occupancy (ticks)
1598system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1599system.cpu0.toL2Bus.respLayer1.occupancy 1296047217 # Layer occupancy (ticks)
1600system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1601system.cpu0.toL2Bus.respLayer2.occupancy 16802481 # Layer occupancy (ticks)
1602system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1603system.cpu0.toL2Bus.respLayer3.occupancy 69515913 # Layer occupancy (ticks)
1604system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1605system.cpu1.branchPred.lookups 3871087 # Number of BP lookups
1606system.cpu1.branchPred.condPredicted 2220502 # Number of conditional branches predicted
1607system.cpu1.branchPred.condIncorrect 213805 # Number of conditional branches incorrect
1608system.cpu1.branchPred.BTBLookups 1955914 # Number of BTB lookups
1609system.cpu1.branchPred.BTBHits 1266404 # Number of BTB hits
1610system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1611system.cpu1.branchPred.BTBHitPct 64.747428 # BTB Hit Percentage
1612system.cpu1.branchPred.usedRAS 774472 # Number of times the RAS was used to get a target.
1613system.cpu1.branchPred.RASInCorrect 5638 # Number of incorrect RAS predictions.
1614system.cpu1.branchPred.indirectLookups 216728 # Number of indirect predictor lookups.
1615system.cpu1.branchPred.indirectHits 192718 # Number of indirect target hits.
1616system.cpu1.branchPred.indirectMisses 24010 # Number of indirect misses.
1617system.cpu1.branchPredindirectMispredicted 5536 # Number of mispredicted indirect branches.
1618system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1619system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1620system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1621system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1622system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1623system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1624system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1625system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1639system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1640system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1641system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1642system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1643system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1644system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1645system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1646system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1647system.cpu1.dtb.walker.walks 15135 # Table walker walks requested
1648system.cpu1.dtb.walker.walksShort 15135 # Table walker walks initiated with short descriptors
1649system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8000 # Level at which table walker walks with short descriptors terminate
1650system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3062 # Level at which table walker walks with short descriptors terminate
1651system.cpu1.dtb.walker.walksSquashedBefore 4073 # Table walks squashed before starting
1652system.cpu1.dtb.walker.walkWaitTime::samples 11062 # Table walker wait (enqueue to first request) latency
1653system.cpu1.dtb.walker.walkWaitTime::mean 636.232146 # Table walker wait (enqueue to first request) latency
1654system.cpu1.dtb.walker.walkWaitTime::stdev 3393.246458 # Table walker wait (enqueue to first request) latency
1655system.cpu1.dtb.walker.walkWaitTime::0-4095 10520 95.10% 95.10% # Table walker wait (enqueue to first request) latency
1656system.cpu1.dtb.walker.walkWaitTime::4096-8191 182 1.65% 96.75% # Table walker wait (enqueue to first request) latency
1657system.cpu1.dtb.walker.walkWaitTime::8192-12287 208 1.88% 98.63% # Table walker wait (enqueue to first request) latency
1658system.cpu1.dtb.walker.walkWaitTime::12288-16383 44 0.40% 99.02% # Table walker wait (enqueue to first request) latency
1659system.cpu1.dtb.walker.walkWaitTime::16384-20479 10 0.09% 99.11% # Table walker wait (enqueue to first request) latency
1660system.cpu1.dtb.walker.walkWaitTime::20480-24575 20 0.18% 99.29% # Table walker wait (enqueue to first request) latency
1661system.cpu1.dtb.walker.walkWaitTime::24576-28671 4 0.04% 99.33% # Table walker wait (enqueue to first request) latency
1662system.cpu1.dtb.walker.walkWaitTime::28672-32767 63 0.57% 99.90% # Table walker wait (enqueue to first request) latency
1663system.cpu1.dtb.walker.walkWaitTime::32768-36863 5 0.05% 99.95% # Table walker wait (enqueue to first request) latency
1664system.cpu1.dtb.walker.walkWaitTime::36864-40959 2 0.02% 99.96% # Table walker wait (enqueue to first request) latency
1665system.cpu1.dtb.walker.walkWaitTime::40960-45055 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency
1666system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency
1667system.cpu1.dtb.walker.walkWaitTime::total 11062 # Table walker wait (enqueue to first request) latency
1668system.cpu1.dtb.walker.walkCompletionTime::samples 3287 # Table walker service (enqueue to completion) latency
1669system.cpu1.dtb.walker.walkCompletionTime::mean 11641.922726 # Table walker service (enqueue to completion) latency
1670system.cpu1.dtb.walker.walkCompletionTime::gmean 10290.587277 # Table walker service (enqueue to completion) latency
1671system.cpu1.dtb.walker.walkCompletionTime::stdev 7252.269841 # Table walker service (enqueue to completion) latency
1672system.cpu1.dtb.walker.walkCompletionTime::0-16383 2804 85.31% 85.31% # Table walker service (enqueue to completion) latency
1673system.cpu1.dtb.walker.walkCompletionTime::16384-32767 438 13.33% 98.63% # Table walker service (enqueue to completion) latency
1674system.cpu1.dtb.walker.walkCompletionTime::32768-49151 35 1.06% 99.70% # Table walker service (enqueue to completion) latency
1675system.cpu1.dtb.walker.walkCompletionTime::49152-65535 8 0.24% 99.94% # Table walker service (enqueue to completion) latency
1676system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
1677system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
1678system.cpu1.dtb.walker.walkCompletionTime::total 3287 # Table walker service (enqueue to completion) latency
1679system.cpu1.dtb.walker.walksPending::samples 78326908560 # Table walker pending requests distribution
1680system.cpu1.dtb.walker.walksPending::mean 0.188289 # Table walker pending requests distribution
1681system.cpu1.dtb.walker.walksPending::stdev 0.393350 # Table walker pending requests distribution
1682system.cpu1.dtb.walker.walksPending::0 63608298256 81.21% 81.21% # Table walker pending requests distribution
1683system.cpu1.dtb.walker.walksPending::1 14703547304 18.77% 99.98% # Table walker pending requests distribution
1684system.cpu1.dtb.walker.walksPending::2 10074500 0.01% 99.99% # Table walker pending requests distribution
1685system.cpu1.dtb.walker.walksPending::3 1868000 0.00% 100.00% # Table walker pending requests distribution
1686system.cpu1.dtb.walker.walksPending::4 997000 0.00% 100.00% # Table walker pending requests distribution
1687system.cpu1.dtb.walker.walksPending::5 536500 0.00% 100.00% # Table walker pending requests distribution
1688system.cpu1.dtb.walker.walksPending::6 1004000 0.00% 100.00% # Table walker pending requests distribution
1689system.cpu1.dtb.walker.walksPending::7 156000 0.00% 100.00% # Table walker pending requests distribution
1690system.cpu1.dtb.walker.walksPending::8 32000 0.00% 100.00% # Table walker pending requests distribution
1691system.cpu1.dtb.walker.walksPending::9 91000 0.00% 100.00% # Table walker pending requests distribution
1692system.cpu1.dtb.walker.walksPending::10 15500 0.00% 100.00% # Table walker pending requests distribution
1693system.cpu1.dtb.walker.walksPending::11 43500 0.00% 100.00% # Table walker pending requests distribution
1694system.cpu1.dtb.walker.walksPending::12 105500 0.00% 100.00% # Table walker pending requests distribution
1695system.cpu1.dtb.walker.walksPending::13 9000 0.00% 100.00% # Table walker pending requests distribution
1696system.cpu1.dtb.walker.walksPending::14 4500 0.00% 100.00% # Table walker pending requests distribution
1697system.cpu1.dtb.walker.walksPending::15 126000 0.00% 100.00% # Table walker pending requests distribution
1698system.cpu1.dtb.walker.walksPending::total 78326908560 # Table walker pending requests distribution
1699system.cpu1.dtb.walker.walkPageSizes::4K 1232 71.42% 71.42% # Table walker page sizes translated
1700system.cpu1.dtb.walker.walkPageSizes::1M 493 28.58% 100.00% # Table walker page sizes translated
1701system.cpu1.dtb.walker.walkPageSizes::total 1725 # Table walker page sizes translated
1702system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15135 # Table walker requests started/completed, data/inst
1703system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1704system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15135 # Table walker requests started/completed, data/inst
1705system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1725 # Table walker requests started/completed, data/inst
1706system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1707system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1725 # Table walker requests started/completed, data/inst
1708system.cpu1.dtb.walker.walkRequestOrigin::total 16860 # Table walker requests started/completed, data/inst
1709system.cpu1.dtb.inst_hits 0 # ITB inst hits
1710system.cpu1.dtb.inst_misses 0 # ITB inst misses
1711system.cpu1.dtb.read_hits 3481626 # DTB read hits
1712system.cpu1.dtb.read_misses 13250 # DTB read misses
1713system.cpu1.dtb.write_hits 2942267 # DTB write hits
1714system.cpu1.dtb.write_misses 1885 # DTB write misses
1715system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
1716system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1717system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1718system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1719system.cpu1.dtb.flush_entries 1665 # Number of entries that have been flushed from TLB
1720system.cpu1.dtb.align_faults 44 # Number of TLB faults due to alignment restrictions
1721system.cpu1.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch
1722system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1723system.cpu1.dtb.perms_faults 252 # Number of TLB faults due to permissions restrictions
1724system.cpu1.dtb.read_accesses 3494876 # DTB read accesses
1725system.cpu1.dtb.write_accesses 2944152 # DTB write accesses
1726system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1727system.cpu1.dtb.hits 6423893 # DTB hits
1728system.cpu1.dtb.misses 15135 # DTB misses
1729system.cpu1.dtb.accesses 6439028 # DTB accesses
1730system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1731system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1732system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1733system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1734system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1735system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1736system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1737system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1751system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1752system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1753system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1754system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1755system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1756system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1757system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1758system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1759system.cpu1.itb.walker.walks 5379 # Table walker walks requested
1760system.cpu1.itb.walker.walksShort 5379 # Table walker walks initiated with short descriptors
1761system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2691 # Level at which table walker walks with short descriptors terminate
1762system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2153 # Level at which table walker walks with short descriptors terminate
1763system.cpu1.itb.walker.walksSquashedBefore 535 # Table walks squashed before starting
1764system.cpu1.itb.walker.walkWaitTime::samples 4844 # Table walker wait (enqueue to first request) latency
1765system.cpu1.itb.walker.walkWaitTime::mean 218.414533 # Table walker wait (enqueue to first request) latency
1766system.cpu1.itb.walker.walkWaitTime::stdev 1692.156629 # Table walker wait (enqueue to first request) latency
1767system.cpu1.itb.walker.walkWaitTime::0-2047 4709 97.21% 97.21% # Table walker wait (enqueue to first request) latency
1768system.cpu1.itb.walker.walkWaitTime::2048-4095 42 0.87% 98.08% # Table walker wait (enqueue to first request) latency
1769system.cpu1.itb.walker.walkWaitTime::4096-6143 42 0.87% 98.95% # Table walker wait (enqueue to first request) latency
1770system.cpu1.itb.walker.walkWaitTime::6144-8191 13 0.27% 99.22% # Table walker wait (enqueue to first request) latency
1771system.cpu1.itb.walker.walkWaitTime::8192-10239 10 0.21% 99.42% # Table walker wait (enqueue to first request) latency
1772system.cpu1.itb.walker.walkWaitTime::10240-12287 7 0.14% 99.57% # Table walker wait (enqueue to first request) latency
1773system.cpu1.itb.walker.walkWaitTime::12288-14335 4 0.08% 99.65% # Table walker wait (enqueue to first request) latency
1774system.cpu1.itb.walker.walkWaitTime::14336-16383 5 0.10% 99.75% # Table walker wait (enqueue to first request) latency
1775system.cpu1.itb.walker.walkWaitTime::16384-18431 2 0.04% 99.79% # Table walker wait (enqueue to first request) latency
1776system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.04% 99.83% # Table walker wait (enqueue to first request) latency
1777system.cpu1.itb.walker.walkWaitTime::26624-28671 6 0.12% 99.96% # Table walker wait (enqueue to first request) latency
1778system.cpu1.itb.walker.walkWaitTime::28672-30719 2 0.04% 100.00% # Table walker wait (enqueue to first request) latency
1779system.cpu1.itb.walker.walkWaitTime::total 4844 # Table walker wait (enqueue to first request) latency
1780system.cpu1.itb.walker.walkCompletionTime::samples 1373 # Table walker service (enqueue to completion) latency
1781system.cpu1.itb.walker.walkCompletionTime::mean 10949.016752 # Table walker service (enqueue to completion) latency
1782system.cpu1.itb.walker.walkCompletionTime::gmean 9997.704100 # Table walker service (enqueue to completion) latency
1783system.cpu1.itb.walker.walkCompletionTime::stdev 5248.867098 # Table walker service (enqueue to completion) latency
1784system.cpu1.itb.walker.walkCompletionTime::0-8191 278 20.25% 20.25% # Table walker service (enqueue to completion) latency
1785system.cpu1.itb.walker.walkCompletionTime::8192-16383 1006 73.27% 93.52% # Table walker service (enqueue to completion) latency
1786system.cpu1.itb.walker.walkCompletionTime::16384-24575 56 4.08% 97.60% # Table walker service (enqueue to completion) latency
1787system.cpu1.itb.walker.walkCompletionTime::24576-32767 16 1.17% 98.76% # Table walker service (enqueue to completion) latency
1788system.cpu1.itb.walker.walkCompletionTime::32768-40959 9 0.66% 99.42% # Table walker service (enqueue to completion) latency
1789system.cpu1.itb.walker.walkCompletionTime::40960-49151 5 0.36% 99.78% # Table walker service (enqueue to completion) latency
1790system.cpu1.itb.walker.walkCompletionTime::49152-57343 2 0.15% 99.93% # Table walker service (enqueue to completion) latency
1791system.cpu1.itb.walker.walkCompletionTime::73728-81919 1 0.07% 100.00% # Table walker service (enqueue to completion) latency
1792system.cpu1.itb.walker.walkCompletionTime::total 1373 # Table walker service (enqueue to completion) latency
1793system.cpu1.itb.walker.walksPending::samples 18192386416 # Table walker pending requests distribution
1794system.cpu1.itb.walker.walksPending::mean 0.925541 # Table walker pending requests distribution
1795system.cpu1.itb.walker.walksPending::stdev 0.262684 # Table walker pending requests distribution
1796system.cpu1.itb.walker.walksPending::0 1355392264 7.45% 7.45% # Table walker pending requests distribution
1797system.cpu1.itb.walker.walksPending::1 16836194152 92.55% 100.00% # Table walker pending requests distribution
1798system.cpu1.itb.walker.walksPending::2 800000 0.00% 100.00% # Table walker pending requests distribution
1799system.cpu1.itb.walker.walksPending::total 18192386416 # Table walker pending requests distribution
1800system.cpu1.itb.walker.walkPageSizes::4K 695 82.94% 82.94% # Table walker page sizes translated
1801system.cpu1.itb.walker.walkPageSizes::1M 143 17.06% 100.00% # Table walker page sizes translated
1802system.cpu1.itb.walker.walkPageSizes::total 838 # Table walker page sizes translated
1803system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1804system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5379 # Table walker requests started/completed, data/inst
1805system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5379 # Table walker requests started/completed, data/inst
1806system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1807system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 838 # Table walker requests started/completed, data/inst
1808system.cpu1.itb.walker.walkRequestOrigin_Completed::total 838 # Table walker requests started/completed, data/inst
1809system.cpu1.itb.walker.walkRequestOrigin::total 6217 # Table walker requests started/completed, data/inst
1810system.cpu1.itb.inst_hits 6965528 # ITB inst hits
1811system.cpu1.itb.inst_misses 5379 # ITB inst misses
1812system.cpu1.itb.read_hits 0 # DTB read hits
1813system.cpu1.itb.read_misses 0 # DTB read misses
1814system.cpu1.itb.write_hits 0 # DTB write hits
1815system.cpu1.itb.write_misses 0 # DTB write misses
1816system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
1817system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1818system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1819system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1820system.cpu1.itb.flush_entries 902 # Number of entries that have been flushed from TLB
1821system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1822system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1823system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1824system.cpu1.itb.perms_faults 384 # Number of TLB faults due to permissions restrictions
1825system.cpu1.itb.read_accesses 0 # DTB read accesses
1826system.cpu1.itb.write_accesses 0 # DTB write accesses
1827system.cpu1.itb.inst_accesses 6970907 # ITB inst accesses
1828system.cpu1.itb.hits 6965528 # DTB hits
1829system.cpu1.itb.misses 5379 # DTB misses
1830system.cpu1.itb.accesses 6970907 # DTB accesses
1831system.cpu1.numCycles 32092744 # number of cpu cycles simulated
1832system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1833system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1834system.cpu1.fetch.icacheStallCycles 7782299 # Number of cycles fetch is stalled on an Icache miss
1835system.cpu1.fetch.Insts 20640770 # Number of instructions fetch has processed
1836system.cpu1.fetch.Branches 3871087 # Number of branches that fetch encountered
1837system.cpu1.fetch.predictedBranches 2233594 # Number of branches that fetch has predicted taken
1838system.cpu1.fetch.Cycles 22614955 # Number of cycles fetch has run and was not squashing or blocked
1839system.cpu1.fetch.SquashCycles 645830 # Number of cycles fetch has spent squashing
1840system.cpu1.fetch.TlbCycles 74008 # Number of cycles fetch has spent waiting for tlb
1841system.cpu1.fetch.MiscStallCycles 29636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1842system.cpu1.fetch.PendingTrapStallCycles 160010 # Number of stall cycles due to pending traps
1843system.cpu1.fetch.PendingQuiesceStallCycles 275842 # Number of stall cycles due to pending quiesce instructions
1844system.cpu1.fetch.IcacheWaitRetryStallCycles 16624 # Number of stall cycles due to full MSHR
1845system.cpu1.fetch.CacheLines 6964682 # Number of cache lines fetched
1846system.cpu1.fetch.IcacheSquashes 92359 # Number of outstanding Icache misses that were squashed
1847system.cpu1.fetch.ItlbSquashes 1934 # Number of outstanding ITLB misses that were squashed
1848system.cpu1.fetch.rateDist::samples 31276289 # Number of instructions fetched each cycle (Total)
1849system.cpu1.fetch.rateDist::mean 0.805380 # Number of instructions fetched each cycle (Total)
1850system.cpu1.fetch.rateDist::stdev 1.188121 # Number of instructions fetched each cycle (Total)
1851system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1852system.cpu1.fetch.rateDist::0 19613481 62.71% 62.71% # Number of instructions fetched each cycle (Total)
1853system.cpu1.fetch.rateDist::1 4233968 13.54% 76.25% # Number of instructions fetched each cycle (Total)
1854system.cpu1.fetch.rateDist::2 1331194 4.26% 80.50% # Number of instructions fetched each cycle (Total)
1855system.cpu1.fetch.rateDist::3 6097646 19.50% 100.00% # Number of instructions fetched each cycle (Total)
1856system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1857system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1858system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
1859system.cpu1.fetch.rateDist::total 31276289 # Number of instructions fetched each cycle (Total)
1860system.cpu1.fetch.branchRate 0.120622 # Number of branch fetches per cycle
1861system.cpu1.fetch.rate 0.643160 # Number of inst fetches per cycle
1862system.cpu1.decode.IdleCycles 6336736 # Number of cycles decode is idle
1863system.cpu1.decode.BlockedCycles 16565133 # Number of cycles decode is blocked
1864system.cpu1.decode.RunCycles 7246187 # Number of cycles decode is running
1865system.cpu1.decode.UnblockCycles 914830 # Number of cycles decode is unblocking
1866system.cpu1.decode.SquashCycles 213403 # Number of cycles decode is squashing
1867system.cpu1.decode.BranchResolved 597831 # Number of times decode resolved a branch
1868system.cpu1.decode.BranchMispred 111765 # Number of times decode detected a branch misprediction
1869system.cpu1.decode.DecodedInsts 19357447 # Number of instructions handled by decode
1870system.cpu1.decode.SquashedInsts 835377 # Number of squashed instructions handled by decode
1871system.cpu1.rename.SquashCycles 213403 # Number of cycles rename is squashing
1872system.cpu1.rename.IdleCycles 7521212 # Number of cycles rename is idle
1873system.cpu1.rename.BlockCycles 2374588 # Number of cycles rename is blocking
1874system.cpu1.rename.serializeStallCycles 11566982 # count of cycles rename stalled for serializing inst
1875system.cpu1.rename.RunCycles 6962571 # Number of cycles rename is running
1876system.cpu1.rename.UnblockCycles 2637533 # Number of cycles rename is unblocking
1877system.cpu1.rename.RenamedInsts 18397316 # Number of instructions processed by rename
1878system.cpu1.rename.SquashedInsts 130089 # Number of squashed instructions processed by rename
1879system.cpu1.rename.ROBFullEvents 214163 # Number of times rename has blocked due to ROB full
1880system.cpu1.rename.IQFullEvents 27812 # Number of times rename has blocked due to IQ full
1881system.cpu1.rename.LQFullEvents 12950 # Number of times rename has blocked due to LQ full
1882system.cpu1.rename.SQFullEvents 1772414 # Number of times rename has blocked due to SQ full
1883system.cpu1.rename.RenamedOperands 18194678 # Number of destination operands rename has renamed
1884system.cpu1.rename.RenameLookups 86130501 # Number of register rename lookups that rename has made
1885system.cpu1.rename.int_rename_lookups 21182613 # Number of integer rename lookups
1886system.cpu1.rename.fp_rename_lookups 5 # Number of floating rename lookups
1887system.cpu1.rename.CommittedMaps 16531195 # Number of HB maps that are committed
1888system.cpu1.rename.UndoneMaps 1663483 # Number of HB maps that are undone due to squashing
1889system.cpu1.rename.serializingInsts 369349 # count of serializing insts renamed
1890system.cpu1.rename.tempSerializingInsts 301926 # count of temporary serializing insts renamed
1891system.cpu1.rename.skidInsts 2462039 # count of insts added to the skid buffer
1892system.cpu1.memDep0.insertedLoads 3681622 # Number of loads inserted to the mem dependence unit.
1893system.cpu1.memDep0.insertedStores 3198899 # Number of stores inserted to the mem dependence unit.
1894system.cpu1.memDep0.conflictingLoads 554263 # Number of conflicting loads.
1895system.cpu1.memDep0.conflictingStores 453752 # Number of conflicting stores.
1896system.cpu1.iq.iqInstsAdded 17730825 # Number of instructions added to the IQ (excludes non-spec)
1897system.cpu1.iq.iqNonSpecInstsAdded 507077 # Number of non-speculative instructions added to the IQ
1898system.cpu1.iq.iqInstsIssued 17704327 # Number of instructions issued
1899system.cpu1.iq.iqSquashedInstsIssued 59995 # Number of squashed instructions issued
1900system.cpu1.iq.iqSquashedInstsExamined 1478553 # Number of squashed instructions iterated over during squash; mainly for profiling
1901system.cpu1.iq.iqSquashedOperandsExamined 3387139 # Number of squashed operands that are examined and possibly removed from graph
1902system.cpu1.iq.iqSquashedNonSpecRemoved 37397 # Number of squashed non-spec instructions that were removed
1903system.cpu1.iq.issued_per_cycle::samples 31276289 # Number of insts issued each cycle
1904system.cpu1.iq.issued_per_cycle::mean 0.566062 # Number of insts issued each cycle
1905system.cpu1.iq.issued_per_cycle::stdev 0.918538 # Number of insts issued each cycle
1906system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1907system.cpu1.iq.issued_per_cycle::0 20752127 66.35% 66.35% # Number of insts issued each cycle
1908system.cpu1.iq.issued_per_cycle::1 5297030 16.94% 83.29% # Number of insts issued each cycle
1909system.cpu1.iq.issued_per_cycle::2 3493708 11.17% 94.46% # Number of insts issued each cycle
1910system.cpu1.iq.issued_per_cycle::3 1513821 4.84% 99.30% # Number of insts issued each cycle
1911system.cpu1.iq.issued_per_cycle::4 219597 0.70% 100.00% # Number of insts issued each cycle
1912system.cpu1.iq.issued_per_cycle::5 6 0.00% 100.00% # Number of insts issued each cycle
1913system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
1914system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
1915system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
1916system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1917system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1918system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
1919system.cpu1.iq.issued_per_cycle::total 31276289 # Number of insts issued each cycle
1920system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1921system.cpu1.iq.fu_full::IntAlu 1110256 27.87% 27.87% # attempts to use FU when none available
1922system.cpu1.iq.fu_full::IntMult 673 0.02% 27.89% # attempts to use FU when none available
1923system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.89% # attempts to use FU when none available
1924system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.89% # attempts to use FU when none available
1925system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.89% # attempts to use FU when none available
1926system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.89% # attempts to use FU when none available
1927system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.89% # attempts to use FU when none available
1928system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.89% # attempts to use FU when none available
1929system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.89% # attempts to use FU when none available
1930system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.89% # attempts to use FU when none available
1931system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.89% # attempts to use FU when none available
1932system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.89% # attempts to use FU when none available
1933system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.89% # attempts to use FU when none available
1934system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.89% # attempts to use FU when none available
1935system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.89% # attempts to use FU when none available
1936system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.89% # attempts to use FU when none available
1937system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.89% # attempts to use FU when none available
1938system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.89% # attempts to use FU when none available
1939system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.89% # attempts to use FU when none available
1940system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.89% # attempts to use FU when none available
1941system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.89% # attempts to use FU when none available
1942system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.89% # attempts to use FU when none available
1943system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.89% # attempts to use FU when none available
1944system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.89% # attempts to use FU when none available
1945system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.89% # attempts to use FU when none available
1946system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.89% # attempts to use FU when none available
1947system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.89% # attempts to use FU when none available
1948system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.89% # attempts to use FU when none available
1949system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.89% # attempts to use FU when none available
1950system.cpu1.iq.fu_full::MemRead 1321373 33.17% 61.07% # attempts to use FU when none available
1951system.cpu1.iq.fu_full::MemWrite 1550767 38.93% 100.00% # attempts to use FU when none available
1952system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1953system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1954system.cpu1.iq.FU_type_0::No_OpClass 24 0.00% 0.00% # Type of FU issued
1955system.cpu1.iq.FU_type_0::IntAlu 10922763 61.70% 61.70% # Type of FU issued
1956system.cpu1.iq.FU_type_0::IntMult 25931 0.15% 61.84% # Type of FU issued
1957system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.84% # Type of FU issued
1958system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.84% # Type of FU issued
1959system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.84% # Type of FU issued
1960system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.84% # Type of FU issued
1961system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.84% # Type of FU issued
1962system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.84% # Type of FU issued
1963system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.84% # Type of FU issued
1964system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.84% # Type of FU issued
1965system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.84% # Type of FU issued
1966system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.84% # Type of FU issued
1967system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.84% # Type of FU issued
1968system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.84% # Type of FU issued
1969system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.84% # Type of FU issued
1970system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.84% # Type of FU issued
1971system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.84% # Type of FU issued
1972system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.84% # Type of FU issued
1973system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.84% # Type of FU issued
1974system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.84% # Type of FU issued
1975system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.84% # Type of FU issued
1976system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.84% # Type of FU issued
1977system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.84% # Type of FU issued
1978system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.84% # Type of FU issued
1979system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.84% # Type of FU issued
1980system.cpu1.iq.FU_type_0::SimdFloatMisc 3184 0.02% 61.86% # Type of FU issued
1981system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.86% # Type of FU issued
1982system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.86% # Type of FU issued
1983system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.86% # Type of FU issued
1984system.cpu1.iq.FU_type_0::MemRead 3652522 20.63% 82.49% # Type of FU issued
1985system.cpu1.iq.FU_type_0::MemWrite 3099903 17.51% 100.00% # Type of FU issued
1986system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1987system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1988system.cpu1.iq.FU_type_0::total 17704327 # Type of FU issued
1989system.cpu1.iq.rate 0.551661 # Inst issue rate
1990system.cpu1.iq.fu_busy_cnt 3983069 # FU busy when requested
1991system.cpu1.iq.fu_busy_rate 0.224977 # FU busy rate (busy events/executed inst)
1992system.cpu1.iq.int_inst_queue_reads 70728007 # Number of integer instruction queue reads
1993system.cpu1.iq.int_inst_queue_writes 19724904 # Number of integer instruction queue writes
1994system.cpu1.iq.int_inst_queue_wakeup_accesses 17354196 # Number of integer instruction queue wakeup accesses
1995system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
1996system.cpu1.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
1997system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
1998system.cpu1.iq.int_alu_accesses 21687372 # Number of integer alu accesses
1999system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
2000system.cpu1.iew.lsq.thread0.forwLoads 71019 # Number of loads that had data forwarded from stores
2001system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2002system.cpu1.iew.lsq.thread0.squashedLoads 284912 # Number of loads squashed
2003system.cpu1.iew.lsq.thread0.ignoredResponses 435 # Number of memory responses ignored because the instruction is squashed
2004system.cpu1.iew.lsq.thread0.memOrderViolation 8471 # Number of memory ordering violations
2005system.cpu1.iew.lsq.thread0.squashedStores 200526 # Number of stores squashed
2006system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2007system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2008system.cpu1.iew.lsq.thread0.rescheduledLoads 36020 # Number of loads that were rescheduled
2009system.cpu1.iew.lsq.thread0.cacheBlocked 53245 # Number of times an access to memory failed due to the cache being blocked
2010system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2011system.cpu1.iew.iewSquashCycles 213403 # Number of cycles IEW is squashing
2012system.cpu1.iew.iewBlockCycles 522979 # Number of cycles IEW is blocking
2013system.cpu1.iew.iewUnblockCycles 149253 # Number of cycles IEW is unblocking
2014system.cpu1.iew.iewDispatchedInsts 18243784 # Number of instructions dispatched to IQ
2015system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016system.cpu1.iew.iewDispLoadInsts 3681622 # Number of dispatched load instructions
2017system.cpu1.iew.iewDispStoreInsts 3198899 # Number of dispatched store instructions
2018system.cpu1.iew.iewDispNonSpecInsts 268198 # Number of dispatched non-speculative instructions
2019system.cpu1.iew.iewIQFullEvents 4775 # Number of times the IQ has become full, causing a stall
2020system.cpu1.iew.iewLSQFullEvents 139704 # Number of times the LSQ has become full, causing a stall
2021system.cpu1.iew.memOrderViolationEvents 8471 # Number of memory order violations
2022system.cpu1.iew.predictedTakenIncorrect 19696 # Number of branches that were predicted taken incorrectly
2023system.cpu1.iew.predictedNotTakenIncorrect 91512 # Number of branches that were predicted not taken incorrectly
2024system.cpu1.iew.branchMispredicts 111208 # Number of branch mispredicts detected at execute
2025system.cpu1.iew.iewExecutedInsts 17534609 # Number of executed instructions
2026system.cpu1.iew.iewExecLoadInsts 3585774 # Number of load instructions executed
2027system.cpu1.iew.iewExecSquashedInsts 154586 # Number of squashed instructions skipped in execute
2028system.cpu1.iew.exec_swp 0 # number of swp insts executed
2029system.cpu1.iew.exec_nop 5882 # number of nop insts executed
2030system.cpu1.iew.exec_refs 6645326 # number of memory reference insts executed
2031system.cpu1.iew.exec_branches 2522938 # Number of branches executed
2032system.cpu1.iew.exec_stores 3059552 # Number of stores executed
2033system.cpu1.iew.exec_rate 0.546373 # Inst execution rate
2034system.cpu1.iew.wb_sent 17440127 # cumulative count of insts sent to commit
2035system.cpu1.iew.wb_count 17354196 # cumulative count of insts written-back
2036system.cpu1.iew.wb_producers 8664228 # num instructions producing a value
2037system.cpu1.iew.wb_consumers 13427268 # num instructions consuming a value
2038system.cpu1.iew.wb_rate 0.540751 # insts written-back per cycle
2039system.cpu1.iew.wb_fanout 0.645271 # average fanout of values written-back
2040system.cpu1.commit.commitSquashedInsts 1321053 # The number of squashed insts skipped by commit
2041system.cpu1.commit.commitNonSpecStalls 469680 # The number of times commit has been forced to stall to communicate backwards
2042system.cpu1.commit.branchMispredicts 104293 # The number of times a branch was mispredicted
2043system.cpu1.commit.committed_per_cycle::samples 30960244 # Number of insts commited each cycle
2044system.cpu1.commit.committed_per_cycle::mean 0.541417 # Number of insts commited each cycle
2045system.cpu1.commit.committed_per_cycle::stdev 1.301399 # Number of insts commited each cycle
2046system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2047system.cpu1.commit.committed_per_cycle::0 22892252 73.94% 73.94% # Number of insts commited each cycle
2048system.cpu1.commit.committed_per_cycle::1 4806577 15.52% 89.47% # Number of insts commited each cycle
2049system.cpu1.commit.committed_per_cycle::2 1404802 4.54% 94.00% # Number of insts commited each cycle
2050system.cpu1.commit.committed_per_cycle::3 524965 1.70% 95.70% # Number of insts commited each cycle
2051system.cpu1.commit.committed_per_cycle::4 440442 1.42% 97.12% # Number of insts commited each cycle
2052system.cpu1.commit.committed_per_cycle::5 285091 0.92% 98.04% # Number of insts commited each cycle
2053system.cpu1.commit.committed_per_cycle::6 183452 0.59% 98.63% # Number of insts commited each cycle
2054system.cpu1.commit.committed_per_cycle::7 97903 0.32% 98.95% # Number of insts commited each cycle
2055system.cpu1.commit.committed_per_cycle::8 324760 1.05% 100.00% # Number of insts commited each cycle
2056system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2057system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2058system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2059system.cpu1.commit.committed_per_cycle::total 30960244 # Number of insts commited each cycle
2060system.cpu1.commit.committedInsts 13688085 # Number of instructions committed
2061system.cpu1.commit.committedOps 16762412 # Number of ops (including micro ops) committed
2062system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2063system.cpu1.commit.refs 6395083 # Number of memory references committed
2064system.cpu1.commit.loads 3396710 # Number of loads committed
2065system.cpu1.commit.membars 189727 # Number of memory barriers committed
2066system.cpu1.commit.branches 2413565 # Number of branches committed
2067system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
2068system.cpu1.commit.int_insts 14968527 # Number of committed integer instructions.
2069system.cpu1.commit.function_calls 408976 # Number of function calls committed.
2070system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2071system.cpu1.commit.op_class_0::IntAlu 10339164 61.68% 61.68% # Class of committed instruction
2072system.cpu1.commit.op_class_0::IntMult 24981 0.15% 61.83% # Class of committed instruction
2073system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.83% # Class of committed instruction
2074system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.83% # Class of committed instruction
2075system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.83% # Class of committed instruction
2076system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.83% # Class of committed instruction
2077system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.83% # Class of committed instruction
2078system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.83% # Class of committed instruction
2079system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.83% # Class of committed instruction
2080system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.83% # Class of committed instruction
2081system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.83% # Class of committed instruction
2082system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.83% # Class of committed instruction
2083system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.83% # Class of committed instruction
2084system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.83% # Class of committed instruction
2085system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.83% # Class of committed instruction
2086system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.83% # Class of committed instruction
2087system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.83% # Class of committed instruction
2088system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.83% # Class of committed instruction
2089system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.83% # Class of committed instruction
2090system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.83% # Class of committed instruction
2091system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.83% # Class of committed instruction
2092system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.83% # Class of committed instruction
2093system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.83% # Class of committed instruction
2094system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.83% # Class of committed instruction
2095system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.83% # Class of committed instruction
2096system.cpu1.commit.op_class_0::SimdFloatMisc 3184 0.02% 61.85% # Class of committed instruction
2097system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.85% # Class of committed instruction
2098system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.85% # Class of committed instruction
2099system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.85% # Class of committed instruction
2100system.cpu1.commit.op_class_0::MemRead 3396710 20.26% 82.11% # Class of committed instruction
2101system.cpu1.commit.op_class_0::MemWrite 2998373 17.89% 100.00% # Class of committed instruction
2102system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2103system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2104system.cpu1.commit.op_class_0::total 16762412 # Class of committed instruction
2105system.cpu1.commit.bw_lim_events 324760 # number cycles where commit BW limit reached
2106system.cpu1.rob.rob_reads 47828529 # The number of ROB reads
2107system.cpu1.rob.rob_writes 36474807 # The number of ROB writes
2108system.cpu1.timesIdled 47199 # Number of times that the entire CPU went into an idle state and unscheduled itself
2109system.cpu1.idleCycles 816455 # Total number of cycles that the CPU has spent unscheduled due to idling
2110system.cpu1.quiesceCycles 5622120065 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2111system.cpu1.committedInsts 13685021 # Number of Instructions Simulated
2112system.cpu1.committedOps 16759348 # Number of Ops (including micro ops) Simulated
2113system.cpu1.cpi 2.345100 # CPI: Cycles Per Instruction
2114system.cpu1.cpi_total 2.345100 # CPI: Total CPI of All Threads
2115system.cpu1.ipc 0.426421 # IPC: Instructions Per Cycle
2116system.cpu1.ipc_total 0.426421 # IPC: Total IPC of All Threads
2117system.cpu1.int_regfile_reads 19625898 # number of integer regfile reads
2118system.cpu1.int_regfile_writes 11372751 # number of integer regfile writes
2119system.cpu1.cc_regfile_reads 63035720 # number of cc regfile reads
2120system.cpu1.cc_regfile_writes 5356524 # number of cc regfile writes
2121system.cpu1.misc_regfile_reads 45569068 # number of misc regfile reads
2122system.cpu1.misc_regfile_writes 348886 # number of misc regfile writes
2123system.cpu1.dcache.tags.replacements 147018 # number of replacements
2124system.cpu1.dcache.tags.tagsinuse 469.878055 # Cycle average of tags in use
2125system.cpu1.dcache.tags.total_refs 5728782 # Total number of references to valid blocks.
2126system.cpu1.dcache.tags.sampled_refs 147355 # Sample count of references to valid blocks.
2127system.cpu1.dcache.tags.avg_refs 38.877418 # Average number of references to valid blocks.
2128system.cpu1.dcache.tags.warmup_cycle 104643213000 # Cycle when the warmup percentage was hit.
2129system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.878055 # Average occupied blocks per requestor
2130system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917731 # Average percentage of cache occupancy
2131system.cpu1.dcache.tags.occ_percent::total 0.917731 # Average percentage of cache occupancy
2132system.cpu1.dcache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id
2133system.cpu1.dcache.tags.age_task_id_blocks_1024::2 334 # Occupied blocks per task id
2134system.cpu1.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
2135system.cpu1.dcache.tags.occ_task_id_percent::1024 0.658203 # Percentage of cache occupancy per task id
2136system.cpu1.dcache.tags.tag_accesses 12638529 # Number of tag accesses
2137system.cpu1.dcache.tags.data_accesses 12638529 # Number of data accesses
2138system.cpu1.dcache.ReadReq_hits::cpu1.data 3017876 # number of ReadReq hits
2139system.cpu1.dcache.ReadReq_hits::total 3017876 # number of ReadReq hits
2140system.cpu1.dcache.WriteReq_hits::cpu1.data 2482754 # number of WriteReq hits
2141system.cpu1.dcache.WriteReq_hits::total 2482754 # number of WriteReq hits
2142system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41945 # number of SoftPFReq hits
2143system.cpu1.dcache.SoftPFReq_hits::total 41945 # number of SoftPFReq hits
2144system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69025 # number of LoadLockedReq hits
2145system.cpu1.dcache.LoadLockedReq_hits::total 69025 # number of LoadLockedReq hits
2146system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61066 # number of StoreCondReq hits
2147system.cpu1.dcache.StoreCondReq_hits::total 61066 # number of StoreCondReq hits
2148system.cpu1.dcache.demand_hits::cpu1.data 5500630 # number of demand (read+write) hits
2149system.cpu1.dcache.demand_hits::total 5500630 # number of demand (read+write) hits
2150system.cpu1.dcache.overall_hits::cpu1.data 5542575 # number of overall hits
2151system.cpu1.dcache.overall_hits::total 5542575 # number of overall hits
2152system.cpu1.dcache.ReadReq_misses::cpu1.data 174243 # number of ReadReq misses
2153system.cpu1.dcache.ReadReq_misses::total 174243 # number of ReadReq misses
2154system.cpu1.dcache.WriteReq_misses::cpu1.data 312530 # number of WriteReq misses
2155system.cpu1.dcache.WriteReq_misses::total 312530 # number of WriteReq misses
2156system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23398 # number of SoftPFReq misses
2157system.cpu1.dcache.SoftPFReq_misses::total 23398 # number of SoftPFReq misses
2158system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17766 # number of LoadLockedReq misses
2159system.cpu1.dcache.LoadLockedReq_misses::total 17766 # number of LoadLockedReq misses
2160system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23154 # number of StoreCondReq misses
2161system.cpu1.dcache.StoreCondReq_misses::total 23154 # number of StoreCondReq misses
2162system.cpu1.dcache.demand_misses::cpu1.data 486773 # number of demand (read+write) misses
2163system.cpu1.dcache.demand_misses::total 486773 # number of demand (read+write) misses
2164system.cpu1.dcache.overall_misses::cpu1.data 510171 # number of overall misses
2165system.cpu1.dcache.overall_misses::total 510171 # number of overall misses
2166system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3329111500 # number of ReadReq miss cycles
2167system.cpu1.dcache.ReadReq_miss_latency::total 3329111500 # number of ReadReq miss cycles
2168system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11702941948 # number of WriteReq miss cycles
2169system.cpu1.dcache.WriteReq_miss_latency::total 11702941948 # number of WriteReq miss cycles
2170system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 365873000 # number of LoadLockedReq miss cycles
2171system.cpu1.dcache.LoadLockedReq_miss_latency::total 365873000 # number of LoadLockedReq miss cycles
2172system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 624012000 # number of StoreCondReq miss cycles
2173system.cpu1.dcache.StoreCondReq_miss_latency::total 624012000 # number of StoreCondReq miss cycles
2174system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1848000 # number of StoreCondFailReq miss cycles
2175system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1848000 # number of StoreCondFailReq miss cycles
2176system.cpu1.dcache.demand_miss_latency::cpu1.data 15032053448 # number of demand (read+write) miss cycles
2177system.cpu1.dcache.demand_miss_latency::total 15032053448 # number of demand (read+write) miss cycles
2178system.cpu1.dcache.overall_miss_latency::cpu1.data 15032053448 # number of overall miss cycles
2179system.cpu1.dcache.overall_miss_latency::total 15032053448 # number of overall miss cycles
2180system.cpu1.dcache.ReadReq_accesses::cpu1.data 3192119 # number of ReadReq accesses(hits+misses)
2181system.cpu1.dcache.ReadReq_accesses::total 3192119 # number of ReadReq accesses(hits+misses)
2182system.cpu1.dcache.WriteReq_accesses::cpu1.data 2795284 # number of WriteReq accesses(hits+misses)
2183system.cpu1.dcache.WriteReq_accesses::total 2795284 # number of WriteReq accesses(hits+misses)
2184system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 65343 # number of SoftPFReq accesses(hits+misses)
2185system.cpu1.dcache.SoftPFReq_accesses::total 65343 # number of SoftPFReq accesses(hits+misses)
2186system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86791 # number of LoadLockedReq accesses(hits+misses)
2187system.cpu1.dcache.LoadLockedReq_accesses::total 86791 # number of LoadLockedReq accesses(hits+misses)
2188system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84220 # number of StoreCondReq accesses(hits+misses)
2189system.cpu1.dcache.StoreCondReq_accesses::total 84220 # number of StoreCondReq accesses(hits+misses)
2190system.cpu1.dcache.demand_accesses::cpu1.data 5987403 # number of demand (read+write) accesses
2191system.cpu1.dcache.demand_accesses::total 5987403 # number of demand (read+write) accesses
2192system.cpu1.dcache.overall_accesses::cpu1.data 6052746 # number of overall (read+write) accesses
2193system.cpu1.dcache.overall_accesses::total 6052746 # number of overall (read+write) accesses
2194system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.054585 # miss rate for ReadReq accesses
2195system.cpu1.dcache.ReadReq_miss_rate::total 0.054585 # miss rate for ReadReq accesses
2196system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.111806 # miss rate for WriteReq accesses
2197system.cpu1.dcache.WriteReq_miss_rate::total 0.111806 # miss rate for WriteReq accesses
2198system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.358080 # miss rate for SoftPFReq accesses
2199system.cpu1.dcache.SoftPFReq_miss_rate::total 0.358080 # miss rate for SoftPFReq accesses
2200system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.204699 # miss rate for LoadLockedReq accesses
2201system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.204699 # miss rate for LoadLockedReq accesses
2202system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274923 # miss rate for StoreCondReq accesses
2203system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274923 # miss rate for StoreCondReq accesses
2204system.cpu1.dcache.demand_miss_rate::cpu1.data 0.081300 # miss rate for demand accesses
2205system.cpu1.dcache.demand_miss_rate::total 0.081300 # miss rate for demand accesses
2206system.cpu1.dcache.overall_miss_rate::cpu1.data 0.084288 # miss rate for overall accesses
2207system.cpu1.dcache.overall_miss_rate::total 0.084288 # miss rate for overall accesses
2208system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19106.141997 # average ReadReq miss latency
2209system.cpu1.dcache.ReadReq_avg_miss_latency::total 19106.141997 # average ReadReq miss latency
2210system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37445.819435 # average WriteReq miss latency
2211system.cpu1.dcache.WriteReq_avg_miss_latency::total 37445.819435 # average WriteReq miss latency
2212system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20593.999775 # average LoadLockedReq miss latency
2213system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20593.999775 # average LoadLockedReq miss latency
2214system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26950.505312 # average StoreCondReq miss latency
2215system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26950.505312 # average StoreCondReq miss latency
2216system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
2217system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2218system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30881.033763 # average overall miss latency
2219system.cpu1.dcache.demand_avg_miss_latency::total 30881.033763 # average overall miss latency
2220system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29464.735252 # average overall miss latency
2221system.cpu1.dcache.overall_avg_miss_latency::total 29464.735252 # average overall miss latency
2222system.cpu1.dcache.blocked_cycles::no_mshrs 465 # number of cycles access was blocked
2223system.cpu1.dcache.blocked_cycles::no_targets 1794947 # number of cycles access was blocked
2224system.cpu1.dcache.blocked::no_mshrs 35 # number of cycles access was blocked
2225system.cpu1.dcache.blocked::no_targets 29761 # number of cycles access was blocked
2226system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.285714 # average number of cycles each access was blocked
2227system.cpu1.dcache.avg_blocked_cycles::no_targets 60.312053 # average number of cycles each access was blocked
2228system.cpu1.dcache.fast_writes 0 # number of fast writes performed
2229system.cpu1.dcache.cache_copies 0 # number of cache copies performed
2230system.cpu1.dcache.writebacks::writebacks 147018 # number of writebacks
2231system.cpu1.dcache.writebacks::total 147018 # number of writebacks
2232system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 60609 # number of ReadReq MSHR hits
2233system.cpu1.dcache.ReadReq_mshr_hits::total 60609 # number of ReadReq MSHR hits
2234system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 234531 # number of WriteReq MSHR hits
2235system.cpu1.dcache.WriteReq_mshr_hits::total 234531 # number of WriteReq MSHR hits
2236system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12556 # number of LoadLockedReq MSHR hits
2237system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12556 # number of LoadLockedReq MSHR hits
2238system.cpu1.dcache.demand_mshr_hits::cpu1.data 295140 # number of demand (read+write) MSHR hits
2239system.cpu1.dcache.demand_mshr_hits::total 295140 # number of demand (read+write) MSHR hits
2240system.cpu1.dcache.overall_mshr_hits::cpu1.data 295140 # number of overall MSHR hits
2241system.cpu1.dcache.overall_mshr_hits::total 295140 # number of overall MSHR hits
2242system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 113634 # number of ReadReq MSHR misses
2243system.cpu1.dcache.ReadReq_mshr_misses::total 113634 # number of ReadReq MSHR misses
2244system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 77999 # number of WriteReq MSHR misses
2245system.cpu1.dcache.WriteReq_mshr_misses::total 77999 # number of WriteReq MSHR misses
2246system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 22718 # number of SoftPFReq MSHR misses
2247system.cpu1.dcache.SoftPFReq_mshr_misses::total 22718 # number of SoftPFReq MSHR misses
2248system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5210 # number of LoadLockedReq MSHR misses
2249system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5210 # number of LoadLockedReq MSHR misses
2250system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23154 # number of StoreCondReq MSHR misses
2251system.cpu1.dcache.StoreCondReq_mshr_misses::total 23154 # number of StoreCondReq MSHR misses
2252system.cpu1.dcache.demand_mshr_misses::cpu1.data 191633 # number of demand (read+write) MSHR misses
2253system.cpu1.dcache.demand_mshr_misses::total 191633 # number of demand (read+write) MSHR misses
2254system.cpu1.dcache.overall_mshr_misses::cpu1.data 214351 # number of overall MSHR misses
2255system.cpu1.dcache.overall_mshr_misses::total 214351 # number of overall MSHR misses
2256system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3075 # number of ReadReq MSHR uncacheable
2257system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3075 # number of ReadReq MSHR uncacheable
2258system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2419 # number of WriteReq MSHR uncacheable
2259system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2419 # number of WriteReq MSHR uncacheable
2260system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5494 # number of overall MSHR uncacheable misses
2261system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5494 # number of overall MSHR uncacheable misses
2262system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1698407500 # number of ReadReq MSHR miss cycles
2263system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1698407500 # number of ReadReq MSHR miss cycles
2264system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2883249956 # number of WriteReq MSHR miss cycles
2265system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2883249956 # number of WriteReq MSHR miss cycles
2266system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 419765000 # number of SoftPFReq MSHR miss cycles
2267system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 419765000 # number of SoftPFReq MSHR miss cycles
2268system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 102736000 # number of LoadLockedReq MSHR miss cycles
2269system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 102736000 # number of LoadLockedReq MSHR miss cycles
2270system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 600876000 # number of StoreCondReq MSHR miss cycles
2271system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 600876000 # number of StoreCondReq MSHR miss cycles
2272system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1830000 # number of StoreCondFailReq MSHR miss cycles
2273system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1830000 # number of StoreCondFailReq MSHR miss cycles
2274system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4581657456 # number of demand (read+write) MSHR miss cycles
2275system.cpu1.dcache.demand_mshr_miss_latency::total 4581657456 # number of demand (read+write) MSHR miss cycles
2276system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5001422456 # number of overall MSHR miss cycles
2277system.cpu1.dcache.overall_mshr_miss_latency::total 5001422456 # number of overall MSHR miss cycles
2278system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 438427500 # number of ReadReq MSHR uncacheable cycles
2279system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 438427500 # number of ReadReq MSHR uncacheable cycles
2280system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 301840000 # number of WriteReq MSHR uncacheable cycles
2281system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 301840000 # number of WriteReq MSHR uncacheable cycles
2282system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 740267500 # number of overall MSHR uncacheable cycles
2283system.cpu1.dcache.overall_mshr_uncacheable_latency::total 740267500 # number of overall MSHR uncacheable cycles
2284system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035598 # mshr miss rate for ReadReq accesses
2285system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035598 # mshr miss rate for ReadReq accesses
2286system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027904 # mshr miss rate for WriteReq accesses
2287system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027904 # mshr miss rate for WriteReq accesses
2288system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.347673 # mshr miss rate for SoftPFReq accesses
2289system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.347673 # mshr miss rate for SoftPFReq accesses
2290system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060029 # mshr miss rate for LoadLockedReq accesses
2291system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060029 # mshr miss rate for LoadLockedReq accesses
2292system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274923 # mshr miss rate for StoreCondReq accesses
2293system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274923 # mshr miss rate for StoreCondReq accesses
2294system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032006 # mshr miss rate for demand accesses
2295system.cpu1.dcache.demand_mshr_miss_rate::total 0.032006 # mshr miss rate for demand accesses
2296system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035414 # mshr miss rate for overall accesses
2297system.cpu1.dcache.overall_mshr_miss_rate::total 0.035414 # mshr miss rate for overall accesses
2298system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14946.296883 # average ReadReq mshr miss latency
2299system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14946.296883 # average ReadReq mshr miss latency
2300system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36965.216939 # average WriteReq mshr miss latency
2301system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36965.216939 # average WriteReq mshr miss latency
2302system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18477.198697 # average SoftPFReq mshr miss latency
2303system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18477.198697 # average SoftPFReq mshr miss latency
2304system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19719.001919 # average LoadLockedReq mshr miss latency
2305system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19719.001919 # average LoadLockedReq mshr miss latency
2306system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25951.282716 # average StoreCondReq mshr miss latency
2307system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25951.282716 # average StoreCondReq mshr miss latency
2308system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
2309system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2310system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23908.499350 # average overall mshr miss latency
2311system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23908.499350 # average overall mshr miss latency
2312system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23332.862716 # average overall mshr miss latency
2313system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23332.862716 # average overall mshr miss latency
2314system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142578.048780 # average ReadReq mshr uncacheable latency
2315system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142578.048780 # average ReadReq mshr uncacheable latency
2316system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 124778.834229 # average WriteReq mshr uncacheable latency
2317system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 124778.834229 # average WriteReq mshr uncacheable latency
2318system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134741.081179 # average overall mshr uncacheable latency
2319system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134741.081179 # average overall mshr uncacheable latency
2320system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2321system.cpu1.icache.tags.replacements 532644 # number of replacements
2322system.cpu1.icache.tags.tagsinuse 499.385087 # Cycle average of tags in use
2323system.cpu1.icache.tags.total_refs 6412298 # Total number of references to valid blocks.
2324system.cpu1.icache.tags.sampled_refs 533156 # Sample count of references to valid blocks.
2325system.cpu1.icache.tags.avg_refs 12.027058 # Average number of references to valid blocks.
2326system.cpu1.icache.tags.warmup_cycle 79429210500 # Cycle when the warmup percentage was hit.
2327system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.385087 # Average occupied blocks per requestor
2328system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975361 # Average percentage of cache occupancy
2329system.cpu1.icache.tags.occ_percent::total 0.975361 # Average percentage of cache occupancy
2330system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2331system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id
2332system.cpu1.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id
2333system.cpu1.icache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id
2334system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2335system.cpu1.icache.tags.tag_accesses 14462114 # Number of tag accesses
2336system.cpu1.icache.tags.data_accesses 14462114 # Number of data accesses
2337system.cpu1.icache.ReadReq_hits::cpu1.inst 6412298 # number of ReadReq hits
2338system.cpu1.icache.ReadReq_hits::total 6412298 # number of ReadReq hits
2339system.cpu1.icache.demand_hits::cpu1.inst 6412298 # number of demand (read+write) hits
2340system.cpu1.icache.demand_hits::total 6412298 # number of demand (read+write) hits
2341system.cpu1.icache.overall_hits::cpu1.inst 6412298 # number of overall hits
2342system.cpu1.icache.overall_hits::total 6412298 # number of overall hits
2343system.cpu1.icache.ReadReq_misses::cpu1.inst 552179 # number of ReadReq misses
2344system.cpu1.icache.ReadReq_misses::total 552179 # number of ReadReq misses
2345system.cpu1.icache.demand_misses::cpu1.inst 552179 # number of demand (read+write) misses
2346system.cpu1.icache.demand_misses::total 552179 # number of demand (read+write) misses
2347system.cpu1.icache.overall_misses::cpu1.inst 552179 # number of overall misses
2348system.cpu1.icache.overall_misses::total 552179 # number of overall misses
2349system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5065871620 # number of ReadReq miss cycles
2350system.cpu1.icache.ReadReq_miss_latency::total 5065871620 # number of ReadReq miss cycles
2351system.cpu1.icache.demand_miss_latency::cpu1.inst 5065871620 # number of demand (read+write) miss cycles
2352system.cpu1.icache.demand_miss_latency::total 5065871620 # number of demand (read+write) miss cycles
2353system.cpu1.icache.overall_miss_latency::cpu1.inst 5065871620 # number of overall miss cycles
2354system.cpu1.icache.overall_miss_latency::total 5065871620 # number of overall miss cycles
2355system.cpu1.icache.ReadReq_accesses::cpu1.inst 6964477 # number of ReadReq accesses(hits+misses)
2356system.cpu1.icache.ReadReq_accesses::total 6964477 # number of ReadReq accesses(hits+misses)
2357system.cpu1.icache.demand_accesses::cpu1.inst 6964477 # number of demand (read+write) accesses
2358system.cpu1.icache.demand_accesses::total 6964477 # number of demand (read+write) accesses
2359system.cpu1.icache.overall_accesses::cpu1.inst 6964477 # number of overall (read+write) accesses
2360system.cpu1.icache.overall_accesses::total 6964477 # number of overall (read+write) accesses
2361system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.079285 # miss rate for ReadReq accesses
2362system.cpu1.icache.ReadReq_miss_rate::total 0.079285 # miss rate for ReadReq accesses
2363system.cpu1.icache.demand_miss_rate::cpu1.inst 0.079285 # miss rate for demand accesses
2364system.cpu1.icache.demand_miss_rate::total 0.079285 # miss rate for demand accesses
2365system.cpu1.icache.overall_miss_rate::cpu1.inst 0.079285 # miss rate for overall accesses
2366system.cpu1.icache.overall_miss_rate::total 0.079285 # miss rate for overall accesses
2367system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9174.328651 # average ReadReq miss latency
2368system.cpu1.icache.ReadReq_avg_miss_latency::total 9174.328651 # average ReadReq miss latency
2369system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9174.328651 # average overall miss latency
2370system.cpu1.icache.demand_avg_miss_latency::total 9174.328651 # average overall miss latency
2371system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9174.328651 # average overall miss latency
2372system.cpu1.icache.overall_avg_miss_latency::total 9174.328651 # average overall miss latency
2373system.cpu1.icache.blocked_cycles::no_mshrs 470749 # number of cycles access was blocked
2374system.cpu1.icache.blocked_cycles::no_targets 422 # number of cycles access was blocked
2375system.cpu1.icache.blocked::no_mshrs 34696 # number of cycles access was blocked
2376system.cpu1.icache.blocked::no_targets 4 # number of cycles access was blocked
2377system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.567818 # average number of cycles each access was blocked
2378system.cpu1.icache.avg_blocked_cycles::no_targets 105.500000 # average number of cycles each access was blocked
2379system.cpu1.icache.fast_writes 0 # number of fast writes performed
2380system.cpu1.icache.cache_copies 0 # number of cache copies performed
2381system.cpu1.icache.writebacks::writebacks 532644 # number of writebacks
2382system.cpu1.icache.writebacks::total 532644 # number of writebacks
2383system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 19019 # number of ReadReq MSHR hits
2384system.cpu1.icache.ReadReq_mshr_hits::total 19019 # number of ReadReq MSHR hits
2385system.cpu1.icache.demand_mshr_hits::cpu1.inst 19019 # number of demand (read+write) MSHR hits
2386system.cpu1.icache.demand_mshr_hits::total 19019 # number of demand (read+write) MSHR hits
2387system.cpu1.icache.overall_mshr_hits::cpu1.inst 19019 # number of overall MSHR hits
2388system.cpu1.icache.overall_mshr_hits::total 19019 # number of overall MSHR hits
2389system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 533160 # number of ReadReq MSHR misses
2390system.cpu1.icache.ReadReq_mshr_misses::total 533160 # number of ReadReq MSHR misses
2391system.cpu1.icache.demand_mshr_misses::cpu1.inst 533160 # number of demand (read+write) MSHR misses
2392system.cpu1.icache.demand_mshr_misses::total 533160 # number of demand (read+write) MSHR misses
2393system.cpu1.icache.overall_mshr_misses::cpu1.inst 533160 # number of overall MSHR misses
2394system.cpu1.icache.overall_mshr_misses::total 533160 # number of overall MSHR misses
2395system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable
2396system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable
2397system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses
2398system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses
2399system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4631400380 # number of ReadReq MSHR miss cycles
2400system.cpu1.icache.ReadReq_mshr_miss_latency::total 4631400380 # number of ReadReq MSHR miss cycles
2401system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4631400380 # number of demand (read+write) MSHR miss cycles
2402system.cpu1.icache.demand_mshr_miss_latency::total 4631400380 # number of demand (read+write) MSHR miss cycles
2403system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4631400380 # number of overall MSHR miss cycles
2404system.cpu1.icache.overall_mshr_miss_latency::total 4631400380 # number of overall MSHR miss cycles
2405system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13655000 # number of ReadReq MSHR uncacheable cycles
2406system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13655000 # number of ReadReq MSHR uncacheable cycles
2407system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13655000 # number of overall MSHR uncacheable cycles
2408system.cpu1.icache.overall_mshr_uncacheable_latency::total 13655000 # number of overall MSHR uncacheable cycles
2409system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.076554 # mshr miss rate for ReadReq accesses
2410system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.076554 # mshr miss rate for ReadReq accesses
2411system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.076554 # mshr miss rate for demand accesses
2412system.cpu1.icache.demand_mshr_miss_rate::total 0.076554 # mshr miss rate for demand accesses
2413system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.076554 # mshr miss rate for overall accesses
2414system.cpu1.icache.overall_mshr_miss_rate::total 0.076554 # mshr miss rate for overall accesses
2415system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8686.698890 # average ReadReq mshr miss latency
2416system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8686.698890 # average ReadReq mshr miss latency
2417system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8686.698890 # average overall mshr miss latency
2418system.cpu1.icache.demand_avg_mshr_miss_latency::total 8686.698890 # average overall mshr miss latency
2419system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8686.698890 # average overall mshr miss latency
2420system.cpu1.icache.overall_avg_mshr_miss_latency::total 8686.698890 # average overall mshr miss latency
2421system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133872.549020 # average ReadReq mshr uncacheable latency
2422system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133872.549020 # average ReadReq mshr uncacheable latency
2423system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133872.549020 # average overall mshr uncacheable latency
2424system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133872.549020 # average overall mshr uncacheable latency
2425system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2426system.cpu1.l2cache.prefetcher.num_hwpf_issued 119604 # number of hwpf issued
2427system.cpu1.l2cache.prefetcher.pfIdentified 120343 # number of prefetch candidates identified
2428system.cpu1.l2cache.prefetcher.pfBufferHit 669 # number of redundant prefetches already in prefetch queue
2429system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
2430system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2431system.cpu1.l2cache.prefetcher.pfSpanPage 49745 # number of prefetches not generated due to page crossing
2432system.cpu1.l2cache.tags.replacements 36294 # number of replacements
2433system.cpu1.l2cache.tags.tagsinuse 15213.941609 # Cycle average of tags in use
2434system.cpu1.l2cache.tags.total_refs 1184366 # Total number of references to valid blocks.
2435system.cpu1.l2cache.tags.sampled_refs 51460 # Sample count of references to valid blocks.
2436system.cpu1.l2cache.tags.avg_refs 23.015274 # Average number of references to valid blocks.
2437system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2438system.cpu1.l2cache.tags.occ_blocks::writebacks 14744.109202 # Average occupied blocks per requestor
2439system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 10.751628 # Average occupied blocks per requestor
2440system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 4.727886 # Average occupied blocks per requestor
2441system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 454.352894 # Average occupied blocks per requestor
2442system.cpu1.l2cache.tags.occ_percent::writebacks 0.899909 # Average percentage of cache occupancy
2443system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000656 # Average percentage of cache occupancy
2444system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000289 # Average percentage of cache occupancy
2445system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.027731 # Average percentage of cache occupancy
2446system.cpu1.l2cache.tags.occ_percent::total 0.928585 # Average percentage of cache occupancy
2447system.cpu1.l2cache.tags.occ_task_id_blocks::1022 946 # Occupied blocks per task id
2448system.cpu1.l2cache.tags.occ_task_id_blocks::1023 64 # Occupied blocks per task id
2449system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14156 # Occupied blocks per task id
2450system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 7 # Occupied blocks per task id
2451system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 620 # Occupied blocks per task id
2452system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 319 # Occupied blocks per task id
2453system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id
2454system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 22 # Occupied blocks per task id
2455system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id
2456system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 800 # Occupied blocks per task id
2457system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2726 # Occupied blocks per task id
2458system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10630 # Occupied blocks per task id
2459system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.057739 # Percentage of cache occupancy per task id
2460system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003906 # Percentage of cache occupancy per task id
2461system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.864014 # Percentage of cache occupancy per task id
2462system.cpu1.l2cache.tags.tag_accesses 23534667 # Number of tag accesses
2463system.cpu1.l2cache.tags.data_accesses 23534667 # Number of data accesses
2464system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 11642 # number of ReadReq hits
2465system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 5450 # number of ReadReq hits
2466system.cpu1.l2cache.ReadReq_hits::total 17092 # number of ReadReq hits
2467system.cpu1.l2cache.WritebackDirty_hits::writebacks 91128 # number of WritebackDirty hits
2468system.cpu1.l2cache.WritebackDirty_hits::total 91128 # number of WritebackDirty hits
2469system.cpu1.l2cache.WritebackClean_hits::writebacks 577481 # number of WritebackClean hits
2470system.cpu1.l2cache.WritebackClean_hits::total 577481 # number of WritebackClean hits
2471system.cpu1.l2cache.ReadExReq_hits::cpu1.data 16562 # number of ReadExReq hits
2472system.cpu1.l2cache.ReadExReq_hits::total 16562 # number of ReadExReq hits
2473system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 522608 # number of ReadCleanReq hits
2474system.cpu1.l2cache.ReadCleanReq_hits::total 522608 # number of ReadCleanReq hits
2475system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 77065 # number of ReadSharedReq hits
2476system.cpu1.l2cache.ReadSharedReq_hits::total 77065 # number of ReadSharedReq hits
2477system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 11642 # number of demand (read+write) hits
2478system.cpu1.l2cache.demand_hits::cpu1.itb.walker 5450 # number of demand (read+write) hits
2479system.cpu1.l2cache.demand_hits::cpu1.inst 522608 # number of demand (read+write) hits
2480system.cpu1.l2cache.demand_hits::cpu1.data 93627 # number of demand (read+write) hits
2481system.cpu1.l2cache.demand_hits::total 633327 # number of demand (read+write) hits
2482system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 11642 # number of overall hits
2483system.cpu1.l2cache.overall_hits::cpu1.itb.walker 5450 # number of overall hits
2484system.cpu1.l2cache.overall_hits::cpu1.inst 522608 # number of overall hits
2485system.cpu1.l2cache.overall_hits::cpu1.data 93627 # number of overall hits
2486system.cpu1.l2cache.overall_hits::total 633327 # number of overall hits
2487system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 472 # number of ReadReq misses
2488system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 270 # number of ReadReq misses
2489system.cpu1.l2cache.ReadReq_misses::total 742 # number of ReadReq misses
2490system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29194 # number of UpgradeReq misses
2491system.cpu1.l2cache.UpgradeReq_misses::total 29194 # number of UpgradeReq misses
2492system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23153 # number of SCUpgradeReq misses
2493system.cpu1.l2cache.SCUpgradeReq_misses::total 23153 # number of SCUpgradeReq misses
2494system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses
2495system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
2496system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32879 # number of ReadExReq misses
2497system.cpu1.l2cache.ReadExReq_misses::total 32879 # number of ReadExReq misses
2498system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 10546 # number of ReadCleanReq misses
2499system.cpu1.l2cache.ReadCleanReq_misses::total 10546 # number of ReadCleanReq misses
2500system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 64491 # number of ReadSharedReq misses
2501system.cpu1.l2cache.ReadSharedReq_misses::total 64491 # number of ReadSharedReq misses
2502system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 472 # number of demand (read+write) misses
2503system.cpu1.l2cache.demand_misses::cpu1.itb.walker 270 # number of demand (read+write) misses
2504system.cpu1.l2cache.demand_misses::cpu1.inst 10546 # number of demand (read+write) misses
2505system.cpu1.l2cache.demand_misses::cpu1.data 97370 # number of demand (read+write) misses
2506system.cpu1.l2cache.demand_misses::total 108658 # number of demand (read+write) misses
2507system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 472 # number of overall misses
2508system.cpu1.l2cache.overall_misses::cpu1.itb.walker 270 # number of overall misses
2509system.cpu1.l2cache.overall_misses::cpu1.inst 10546 # number of overall misses
2510system.cpu1.l2cache.overall_misses::cpu1.data 97370 # number of overall misses
2511system.cpu1.l2cache.overall_misses::total 108658 # number of overall misses
2512system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10388000 # number of ReadReq miss cycles
2513system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5548000 # number of ReadReq miss cycles
2514system.cpu1.l2cache.ReadReq_miss_latency::total 15936000 # number of ReadReq miss cycles
2515system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 61302500 # number of UpgradeReq miss cycles
2516system.cpu1.l2cache.UpgradeReq_miss_latency::total 61302500 # number of UpgradeReq miss cycles
2517system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 60199500 # number of SCUpgradeReq miss cycles
2518system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 60199500 # number of SCUpgradeReq miss cycles
2519system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1803000 # number of SCUpgradeFailReq miss cycles
2520system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1803000 # number of SCUpgradeFailReq miss cycles
2521system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1873781500 # number of ReadExReq miss cycles
2522system.cpu1.l2cache.ReadExReq_miss_latency::total 1873781500 # number of ReadExReq miss cycles
2523system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 637936000 # number of ReadCleanReq miss cycles
2524system.cpu1.l2cache.ReadCleanReq_miss_latency::total 637936000 # number of ReadCleanReq miss cycles
2525system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1490442997 # number of ReadSharedReq miss cycles
2526system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1490442997 # number of ReadSharedReq miss cycles
2527system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10388000 # number of demand (read+write) miss cycles
2528system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5548000 # number of demand (read+write) miss cycles
2529system.cpu1.l2cache.demand_miss_latency::cpu1.inst 637936000 # number of demand (read+write) miss cycles
2530system.cpu1.l2cache.demand_miss_latency::cpu1.data 3364224497 # number of demand (read+write) miss cycles
2531system.cpu1.l2cache.demand_miss_latency::total 4018096497 # number of demand (read+write) miss cycles
2532system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10388000 # number of overall miss cycles
2533system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5548000 # number of overall miss cycles
2534system.cpu1.l2cache.overall_miss_latency::cpu1.inst 637936000 # number of overall miss cycles
2535system.cpu1.l2cache.overall_miss_latency::cpu1.data 3364224497 # number of overall miss cycles
2536system.cpu1.l2cache.overall_miss_latency::total 4018096497 # number of overall miss cycles
2537system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 12114 # number of ReadReq accesses(hits+misses)
2538system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 5720 # number of ReadReq accesses(hits+misses)
2539system.cpu1.l2cache.ReadReq_accesses::total 17834 # number of ReadReq accesses(hits+misses)
2540system.cpu1.l2cache.WritebackDirty_accesses::writebacks 91128 # number of WritebackDirty accesses(hits+misses)
2541system.cpu1.l2cache.WritebackDirty_accesses::total 91128 # number of WritebackDirty accesses(hits+misses)
2542system.cpu1.l2cache.WritebackClean_accesses::writebacks 577481 # number of WritebackClean accesses(hits+misses)
2543system.cpu1.l2cache.WritebackClean_accesses::total 577481 # number of WritebackClean accesses(hits+misses)
2544system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29194 # number of UpgradeReq accesses(hits+misses)
2545system.cpu1.l2cache.UpgradeReq_accesses::total 29194 # number of UpgradeReq accesses(hits+misses)
2546system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23153 # number of SCUpgradeReq accesses(hits+misses)
2547system.cpu1.l2cache.SCUpgradeReq_accesses::total 23153 # number of SCUpgradeReq accesses(hits+misses)
2548system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
2549system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
2550system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 49441 # number of ReadExReq accesses(hits+misses)
2551system.cpu1.l2cache.ReadExReq_accesses::total 49441 # number of ReadExReq accesses(hits+misses)
2552system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 533154 # number of ReadCleanReq accesses(hits+misses)
2553system.cpu1.l2cache.ReadCleanReq_accesses::total 533154 # number of ReadCleanReq accesses(hits+misses)
2554system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 141556 # number of ReadSharedReq accesses(hits+misses)
2555system.cpu1.l2cache.ReadSharedReq_accesses::total 141556 # number of ReadSharedReq accesses(hits+misses)
2556system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 12114 # number of demand (read+write) accesses
2557system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 5720 # number of demand (read+write) accesses
2558system.cpu1.l2cache.demand_accesses::cpu1.inst 533154 # number of demand (read+write) accesses
2559system.cpu1.l2cache.demand_accesses::cpu1.data 190997 # number of demand (read+write) accesses
2560system.cpu1.l2cache.demand_accesses::total 741985 # number of demand (read+write) accesses
2561system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 12114 # number of overall (read+write) accesses
2562system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 5720 # number of overall (read+write) accesses
2563system.cpu1.l2cache.overall_accesses::cpu1.inst 533154 # number of overall (read+write) accesses
2564system.cpu1.l2cache.overall_accesses::cpu1.data 190997 # number of overall (read+write) accesses
2565system.cpu1.l2cache.overall_accesses::total 741985 # number of overall (read+write) accesses
2566system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038963 # miss rate for ReadReq accesses
2567system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.047203 # miss rate for ReadReq accesses
2568system.cpu1.l2cache.ReadReq_miss_rate::total 0.041606 # miss rate for ReadReq accesses
2569system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
2570system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
2571system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2572system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2573system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2574system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2575system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.665015 # miss rate for ReadExReq accesses
2576system.cpu1.l2cache.ReadExReq_miss_rate::total 0.665015 # miss rate for ReadExReq accesses
2577system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.019780 # miss rate for ReadCleanReq accesses
2578system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.019780 # miss rate for ReadCleanReq accesses
2579system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.455586 # miss rate for ReadSharedReq accesses
2580system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.455586 # miss rate for ReadSharedReq accesses
2581system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038963 # miss rate for demand accesses
2582system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.047203 # miss rate for demand accesses
2583system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.019780 # miss rate for demand accesses
2584system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.509799 # miss rate for demand accesses
2585system.cpu1.l2cache.demand_miss_rate::total 0.146442 # miss rate for demand accesses
2586system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038963 # miss rate for overall accesses
2587system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.047203 # miss rate for overall accesses
2588system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.019780 # miss rate for overall accesses
2589system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.509799 # miss rate for overall accesses
2590system.cpu1.l2cache.overall_miss_rate::total 0.146442 # miss rate for overall accesses
2591system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22008.474576 # average ReadReq miss latency
2592system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20548.148148 # average ReadReq miss latency
2593system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21477.088949 # average ReadReq miss latency
2594system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2099.832157 # average UpgradeReq miss latency
2595system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2099.832157 # average UpgradeReq miss latency
2596system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2600.073425 # average SCUpgradeReq miss latency
2597system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2600.073425 # average SCUpgradeReq miss latency
2598system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1803000 # average SCUpgradeFailReq miss latency
2599system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1803000 # average SCUpgradeFailReq miss latency
2600system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 56990.221722 # average ReadExReq miss latency
2601system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 56990.221722 # average ReadExReq miss latency
2602system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 60490.802200 # average ReadCleanReq miss latency
2603system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 60490.802200 # average ReadCleanReq miss latency
2604system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23110.868137 # average ReadSharedReq miss latency
2605system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23110.868137 # average ReadSharedReq miss latency
2606system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22008.474576 # average overall miss latency
2607system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20548.148148 # average overall miss latency
2608system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 60490.802200 # average overall miss latency
2609system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34550.934549 # average overall miss latency
2610system.cpu1.l2cache.demand_avg_miss_latency::total 36979.297401 # average overall miss latency
2611system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22008.474576 # average overall miss latency
2612system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20548.148148 # average overall miss latency
2613system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 60490.802200 # average overall miss latency
2614system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34550.934549 # average overall miss latency
2615system.cpu1.l2cache.overall_avg_miss_latency::total 36979.297401 # average overall miss latency
2616system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2617system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2618system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2619system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2620system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2621system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2622system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2623system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2624system.cpu1.l2cache.unused_prefetches 518 # number of HardPF blocks evicted w/o reference
2625system.cpu1.l2cache.writebacks::writebacks 29343 # number of writebacks
2626system.cpu1.l2cache.writebacks::total 29343 # number of writebacks
2627system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1270 # number of ReadExReq MSHR hits
2628system.cpu1.l2cache.ReadExReq_mshr_hits::total 1270 # number of ReadExReq MSHR hits
2629system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 3 # number of ReadCleanReq MSHR hits
2630system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits
2631system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 29 # number of ReadSharedReq MSHR hits
2632system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 29 # number of ReadSharedReq MSHR hits
2633system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits
2634system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1299 # number of demand (read+write) MSHR hits
2635system.cpu1.l2cache.demand_mshr_hits::total 1302 # number of demand (read+write) MSHR hits
2636system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits
2637system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1299 # number of overall MSHR hits
2638system.cpu1.l2cache.overall_mshr_hits::total 1302 # number of overall MSHR hits
2639system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 472 # number of ReadReq MSHR misses
2640system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 270 # number of ReadReq MSHR misses
2641system.cpu1.l2cache.ReadReq_mshr_misses::total 742 # number of ReadReq MSHR misses
2642system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 21229 # number of HardPFReq MSHR misses
2643system.cpu1.l2cache.HardPFReq_mshr_misses::total 21229 # number of HardPFReq MSHR misses
2644system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29194 # number of UpgradeReq MSHR misses
2645system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29194 # number of UpgradeReq MSHR misses
2646system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23153 # number of SCUpgradeReq MSHR misses
2647system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23153 # number of SCUpgradeReq MSHR misses
2648system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses
2649system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
2650system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31609 # number of ReadExReq MSHR misses
2651system.cpu1.l2cache.ReadExReq_mshr_misses::total 31609 # number of ReadExReq MSHR misses
2652system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 10543 # number of ReadCleanReq MSHR misses
2653system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 10543 # number of ReadCleanReq MSHR misses
2654system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 64462 # number of ReadSharedReq MSHR misses
2655system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 64462 # number of ReadSharedReq MSHR misses
2656system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 472 # number of demand (read+write) MSHR misses
2657system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 270 # number of demand (read+write) MSHR misses
2658system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 10543 # number of demand (read+write) MSHR misses
2659system.cpu1.l2cache.demand_mshr_misses::cpu1.data 96071 # number of demand (read+write) MSHR misses
2660system.cpu1.l2cache.demand_mshr_misses::total 107356 # number of demand (read+write) MSHR misses
2661system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 472 # number of overall MSHR misses
2662system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 270 # number of overall MSHR misses
2663system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 10543 # number of overall MSHR misses
2664system.cpu1.l2cache.overall_mshr_misses::cpu1.data 96071 # number of overall MSHR misses
2665system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 21229 # number of overall MSHR misses
2666system.cpu1.l2cache.overall_mshr_misses::total 128585 # number of overall MSHR misses
2667system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable
2668system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3075 # number of ReadReq MSHR uncacheable
2669system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3177 # number of ReadReq MSHR uncacheable
2670system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2419 # number of WriteReq MSHR uncacheable
2671system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2419 # number of WriteReq MSHR uncacheable
2672system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses
2673system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5494 # number of overall MSHR uncacheable misses
2674system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5596 # number of overall MSHR uncacheable misses
2675system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7556000 # number of ReadReq MSHR miss cycles
2676system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3928000 # number of ReadReq MSHR miss cycles
2677system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 11484000 # number of ReadReq MSHR miss cycles
2678system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1356296825 # number of HardPFReq MSHR miss cycles
2679system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1356296825 # number of HardPFReq MSHR miss cycles
2680system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 583735000 # number of UpgradeReq MSHR miss cycles
2681system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 583735000 # number of UpgradeReq MSHR miss cycles
2682system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 426936499 # number of SCUpgradeReq MSHR miss cycles
2683system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 426936499 # number of SCUpgradeReq MSHR miss cycles
2684system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1695000 # number of SCUpgradeFailReq MSHR miss cycles
2685system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1695000 # number of SCUpgradeFailReq MSHR miss cycles
2686system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1581842500 # number of ReadExReq MSHR miss cycles
2687system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1581842500 # number of ReadExReq MSHR miss cycles
2688system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 574617500 # number of ReadCleanReq MSHR miss cycles
2689system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 574617500 # number of ReadCleanReq MSHR miss cycles
2690system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1102358997 # number of ReadSharedReq MSHR miss cycles
2691system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1102358997 # number of ReadSharedReq MSHR miss cycles
2692system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7556000 # number of demand (read+write) MSHR miss cycles
2693system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3928000 # number of demand (read+write) MSHR miss cycles
2694system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 574617500 # number of demand (read+write) MSHR miss cycles
2695system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2684201497 # number of demand (read+write) MSHR miss cycles
2696system.cpu1.l2cache.demand_mshr_miss_latency::total 3270302997 # number of demand (read+write) MSHR miss cycles
2697system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7556000 # number of overall MSHR miss cycles
2698system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3928000 # number of overall MSHR miss cycles
2699system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 574617500 # number of overall MSHR miss cycles
2700system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2684201497 # number of overall MSHR miss cycles
2701system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1356296825 # number of overall MSHR miss cycles
2702system.cpu1.l2cache.overall_mshr_miss_latency::total 4626599822 # number of overall MSHR miss cycles
2703system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12890000 # number of ReadReq MSHR uncacheable cycles
2704system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 413788000 # number of ReadReq MSHR uncacheable cycles
2705system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 426678000 # number of ReadReq MSHR uncacheable cycles
2706system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 283458994 # number of WriteReq MSHR uncacheable cycles
2707system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 283458994 # number of WriteReq MSHR uncacheable cycles
2708system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12890000 # number of overall MSHR uncacheable cycles
2709system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 697246994 # number of overall MSHR uncacheable cycles
2710system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 710136994 # number of overall MSHR uncacheable cycles
2711system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038963 # mshr miss rate for ReadReq accesses
2712system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.047203 # mshr miss rate for ReadReq accesses
2713system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041606 # mshr miss rate for ReadReq accesses
2714system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2715system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2716system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2717system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2718system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2719system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2720system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2721system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2722system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.639328 # mshr miss rate for ReadExReq accesses
2723system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.639328 # mshr miss rate for ReadExReq accesses
2724system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019775 # mshr miss rate for ReadCleanReq accesses
2725system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.019775 # mshr miss rate for ReadCleanReq accesses
2726system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.455382 # mshr miss rate for ReadSharedReq accesses
2727system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.455382 # mshr miss rate for ReadSharedReq accesses
2728system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038963 # mshr miss rate for demand accesses
2729system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.047203 # mshr miss rate for demand accesses
2730system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.019775 # mshr miss rate for demand accesses
2731system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.502997 # mshr miss rate for demand accesses
2732system.cpu1.l2cache.demand_mshr_miss_rate::total 0.144688 # mshr miss rate for demand accesses
2733system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038963 # mshr miss rate for overall accesses
2734system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.047203 # mshr miss rate for overall accesses
2735system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.019775 # mshr miss rate for overall accesses
2736system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.502997 # mshr miss rate for overall accesses
2737system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2738system.cpu1.l2cache.overall_mshr_miss_rate::total 0.173299 # mshr miss rate for overall accesses
2739system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16008.474576 # average ReadReq mshr miss latency
2740system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14548.148148 # average ReadReq mshr miss latency
2741system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15477.088949 # average ReadReq mshr miss latency
2742system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63888.870178 # average HardPFReq mshr miss latency
2743system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 63888.870178 # average HardPFReq mshr miss latency
2744system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19995.033226 # average UpgradeReq mshr miss latency
2745system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19995.033226 # average UpgradeReq mshr miss latency
2746system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18439.791776 # average SCUpgradeReq mshr miss latency
2747system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18439.791776 # average SCUpgradeReq mshr miss latency
2748system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1695000 # average SCUpgradeFailReq mshr miss latency
2749system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1695000 # average SCUpgradeFailReq mshr miss latency
2750system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 50044.053909 # average ReadExReq mshr miss latency
2751system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 50044.053909 # average ReadExReq mshr miss latency
2752system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54502.276392 # average ReadCleanReq mshr miss latency
2753system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54502.276392 # average ReadCleanReq mshr miss latency
2754system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17100.912119 # average ReadSharedReq mshr miss latency
2755system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17100.912119 # average ReadSharedReq mshr miss latency
2756system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16008.474576 # average overall mshr miss latency
2757system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14548.148148 # average overall mshr miss latency
2758system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54502.276392 # average overall mshr miss latency
2759system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27939.768473 # average overall mshr miss latency
2760system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30462.228446 # average overall mshr miss latency
2761system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16008.474576 # average overall mshr miss latency
2762system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14548.148148 # average overall mshr miss latency
2763system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54502.276392 # average overall mshr miss latency
2764system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27939.768473 # average overall mshr miss latency
2765system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63888.870178 # average overall mshr miss latency
2766system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 35980.867302 # average overall mshr miss latency
2767system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126372.549020 # average ReadReq mshr uncacheable latency
2768system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134565.203252 # average ReadReq mshr uncacheable latency
2769system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134302.171860 # average ReadReq mshr uncacheable latency
2770system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117180.237288 # average WriteReq mshr uncacheable latency
2771system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117180.237288 # average WriteReq mshr uncacheable latency
2772system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126372.549020 # average overall mshr uncacheable latency
2773system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126910.628686 # average overall mshr uncacheable latency
2774system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126900.820944 # average overall mshr uncacheable latency
2775system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2776system.cpu1.toL2Bus.snoop_filter.tot_requests 1463686 # Total number of requests made to the snoop filter.
2777system.cpu1.toL2Bus.snoop_filter.hit_single_requests 739552 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2778system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11057 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2779system.cpu1.toL2Bus.snoop_filter.tot_snoops 170999 # Total number of snoops made to the snoop filter.
2780system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 169235 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2781system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1764 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2782system.cpu1.toL2Bus.trans_dist::ReadReq 24298 # Transaction distribution
2783system.cpu1.toL2Bus.trans_dist::ReadResp 736701 # Transaction distribution
2784system.cpu1.toL2Bus.trans_dist::WriteReq 2419 # Transaction distribution
2785system.cpu1.toL2Bus.trans_dist::WriteResp 2419 # Transaction distribution
2786system.cpu1.toL2Bus.trans_dist::WritebackDirty 121677 # Transaction distribution
2787system.cpu1.toL2Bus.trans_dist::WritebackClean 588534 # Transaction distribution
2788system.cpu1.toL2Bus.trans_dist::CleanEvict 90826 # Transaction distribution
2789system.cpu1.toL2Bus.trans_dist::HardPFReq 26224 # Transaction distribution
2790system.cpu1.toL2Bus.trans_dist::UpgradeReq 69999 # Transaction distribution
2791system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41335 # Transaction distribution
2792system.cpu1.toL2Bus.trans_dist::UpgradeResp 85194 # Transaction distribution
2793system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution
2794system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
2795system.cpu1.toL2Bus.trans_dist::ReadExReq 56383 # Transaction distribution
2796system.cpu1.toL2Bus.trans_dist::ReadExResp 54101 # Transaction distribution
2797system.cpu1.toL2Bus.trans_dist::ReadCleanReq 533160 # Transaction distribution
2798system.cpu1.toL2Bus.trans_dist::ReadSharedReq 217797 # Transaction distribution
2799system.cpu1.toL2Bus.trans_dist::InvalidateReq 24 # Transaction distribution
2800system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1599162 # Packet count per connected master and slave (bytes)
2801system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 719912 # Packet count per connected master and slave (bytes)
2802system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12717 # Packet count per connected master and slave (bytes)
2803system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 26238 # Packet count per connected master and slave (bytes)
2804system.cpu1.toL2Bus.pkt_count::total 2358029 # Packet count per connected master and slave (bytes)
2805system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 68212704 # Cumulative packet size per connected master and slave (bytes)
2806system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24362994 # Cumulative packet size per connected master and slave (bytes)
2807system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 22880 # Cumulative packet size per connected master and slave (bytes)
2808system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 48456 # Cumulative packet size per connected master and slave (bytes)
2809system.cpu1.toL2Bus.pkt_size::total 92647034 # Cumulative packet size per connected master and slave (bytes)
2810system.cpu1.toL2Bus.snoops 368307 # Total snoops (count)
2811system.cpu1.toL2Bus.snoop_fanout::samples 1093026 # Request fanout histogram
2812system.cpu1.toL2Bus.snoop_fanout::mean 0.175061 # Request fanout histogram
2813system.cpu1.toL2Bus.snoop_fanout::stdev 0.384243 # Request fanout histogram
2814system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2815system.cpu1.toL2Bus.snoop_fanout::0 903444 82.66% 82.66% # Request fanout histogram
2816system.cpu1.toL2Bus.snoop_fanout::1 187818 17.18% 99.84% # Request fanout histogram
2817system.cpu1.toL2Bus.snoop_fanout::2 1764 0.16% 100.00% # Request fanout histogram
2818system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2819system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2820system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2821system.cpu1.toL2Bus.snoop_fanout::total 1093026 # Request fanout histogram
2822system.cpu1.toL2Bus.reqLayer0.occupancy 1422321490 # Layer occupancy (ticks)
2823system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2824system.cpu1.toL2Bus.snoopLayer0.occupancy 79991516 # Layer occupancy (ticks)
2825system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2826system.cpu1.toL2Bus.respLayer0.occupancy 799908367 # Layer occupancy (ticks)
2827system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2828system.cpu1.toL2Bus.respLayer1.occupancy 318043852 # Layer occupancy (ticks)
2829system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2830system.cpu1.toL2Bus.respLayer2.occupancy 6997998 # Layer occupancy (ticks)
2831system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2832system.cpu1.toL2Bus.respLayer3.occupancy 14133980 # Layer occupancy (ticks)
2833system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2834system.iobus.trans_dist::ReadReq 31018 # Transaction distribution
2835system.iobus.trans_dist::ReadResp 31018 # Transaction distribution
2836system.iobus.trans_dist::WriteReq 59424 # Transaction distribution
2837system.iobus.trans_dist::WriteResp 59424 # Transaction distribution
2838system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes)
2839system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2840system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)

--- 35 unchanged lines hidden (view full) ---

2876system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
2877system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2878system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
2879system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2880system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes)
2881system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
2882system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
2883system.iobus.pkt_size::total 2484060 # Cumulative packet size per connected master and slave (bytes)
2884system.iobus.reqLayer0.occupancy 40405500 # Layer occupancy (ticks)
2885system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2886system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks)
2887system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2888system.iobus.reqLayer2.occupancy 323000 # Layer occupancy (ticks)
2889system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2890system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks)
2891system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2892system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks)
2893system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2894system.iobus.reqLayer7.occupancy 89000 # Layer occupancy (ticks)
2895system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2896system.iobus.reqLayer8.occupancy 574500 # Layer occupancy (ticks)
2897system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2898system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks)
2899system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2900system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks)
2901system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2902system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks)
2903system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2904system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks)
2905system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2906system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks)
2907system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2908system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
2909system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2910system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
2911system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2912system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
2913system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2914system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2915system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2916system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks)
2917system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2918system.iobus.reqLayer23.occupancy 6085500 # Layer occupancy (ticks)
2919system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2920system.iobus.reqLayer24.occupancy 34122000 # Layer occupancy (ticks)
2921system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2922system.iobus.reqLayer25.occupancy 187170938 # Layer occupancy (ticks)
2923system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2924system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks)
2925system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2926system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks)
2927system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2928system.iocache.tags.replacements 36458 # number of replacements
2929system.iocache.tags.tagsinuse 14.550737 # Cycle average of tags in use
2930system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2931system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks.
2932system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2933system.iocache.tags.warmup_cycle 256092273000 # Cycle when the warmup percentage was hit.
2934system.iocache.tags.occ_blocks::realview.ide 14.550737 # Average occupied blocks per requestor
2935system.iocache.tags.occ_percent::realview.ide 0.909421 # Average percentage of cache occupancy
2936system.iocache.tags.occ_percent::total 0.909421 # Average percentage of cache occupancy
2937system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2938system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2939system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2940system.iocache.tags.tag_accesses 328284 # Number of tag accesses
2941system.iocache.tags.data_accesses 328284 # Number of data accesses
2942system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
2943system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
2944system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2945system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2946system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
2947system.iocache.demand_misses::total 252 # number of demand (read+write) misses
2948system.iocache.overall_misses::realview.ide 252 # number of overall misses
2949system.iocache.overall_misses::total 252 # number of overall misses
2950system.iocache.ReadReq_miss_latency::realview.ide 32570877 # number of ReadReq miss cycles
2951system.iocache.ReadReq_miss_latency::total 32570877 # number of ReadReq miss cycles
2952system.iocache.WriteLineReq_miss_latency::realview.ide 4577184061 # number of WriteLineReq miss cycles
2953system.iocache.WriteLineReq_miss_latency::total 4577184061 # number of WriteLineReq miss cycles
2954system.iocache.demand_miss_latency::realview.ide 32570877 # number of demand (read+write) miss cycles
2955system.iocache.demand_miss_latency::total 32570877 # number of demand (read+write) miss cycles
2956system.iocache.overall_miss_latency::realview.ide 32570877 # number of overall miss cycles
2957system.iocache.overall_miss_latency::total 32570877 # number of overall miss cycles
2958system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
2959system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
2960system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2961system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2962system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
2963system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
2964system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
2965system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
2966system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2967system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2968system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2969system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2970system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2971system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2972system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2973system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2974system.iocache.ReadReq_avg_miss_latency::realview.ide 129249.511905 # average ReadReq miss latency
2975system.iocache.ReadReq_avg_miss_latency::total 129249.511905 # average ReadReq miss latency
2976system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126357.775536 # average WriteLineReq miss latency
2977system.iocache.WriteLineReq_avg_miss_latency::total 126357.775536 # average WriteLineReq miss latency
2978system.iocache.demand_avg_miss_latency::realview.ide 129249.511905 # average overall miss latency
2979system.iocache.demand_avg_miss_latency::total 129249.511905 # average overall miss latency
2980system.iocache.overall_avg_miss_latency::realview.ide 129249.511905 # average overall miss latency
2981system.iocache.overall_avg_miss_latency::total 129249.511905 # average overall miss latency
2982system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2983system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2984system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2985system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2986system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2987system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2988system.iocache.fast_writes 0 # number of fast writes performed
2989system.iocache.cache_copies 0 # number of cache copies performed
2990system.iocache.writebacks::writebacks 36206 # number of writebacks
2991system.iocache.writebacks::total 36206 # number of writebacks
2992system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses
2993system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses
2994system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2995system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2996system.iocache.demand_mshr_misses::realview.ide 252 # number of demand (read+write) MSHR misses
2997system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses
2998system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses
2999system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses
3000system.iocache.ReadReq_mshr_miss_latency::realview.ide 19970877 # number of ReadReq MSHR miss cycles
3001system.iocache.ReadReq_mshr_miss_latency::total 19970877 # number of ReadReq MSHR miss cycles
3002system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764245413 # number of WriteLineReq MSHR miss cycles
3003system.iocache.WriteLineReq_mshr_miss_latency::total 2764245413 # number of WriteLineReq MSHR miss cycles
3004system.iocache.demand_mshr_miss_latency::realview.ide 19970877 # number of demand (read+write) MSHR miss cycles
3005system.iocache.demand_mshr_miss_latency::total 19970877 # number of demand (read+write) MSHR miss cycles
3006system.iocache.overall_mshr_miss_latency::realview.ide 19970877 # number of overall MSHR miss cycles
3007system.iocache.overall_mshr_miss_latency::total 19970877 # number of overall MSHR miss cycles
3008system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
3009system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
3010system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
3011system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
3012system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
3013system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
3014system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
3015system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
3016system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79249.511905 # average ReadReq mshr miss latency
3017system.iocache.ReadReq_avg_mshr_miss_latency::total 79249.511905 # average ReadReq mshr miss latency
3018system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76309.778407 # average WriteLineReq mshr miss latency
3019system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76309.778407 # average WriteLineReq mshr miss latency
3020system.iocache.demand_avg_mshr_miss_latency::realview.ide 79249.511905 # average overall mshr miss latency
3021system.iocache.demand_avg_mshr_miss_latency::total 79249.511905 # average overall mshr miss latency
3022system.iocache.overall_avg_mshr_miss_latency::realview.ide 79249.511905 # average overall mshr miss latency
3023system.iocache.overall_avg_mshr_miss_latency::total 79249.511905 # average overall mshr miss latency
3024system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
3025system.l2c.tags.replacements 130481 # number of replacements
3026system.l2c.tags.tagsinuse 63162.524815 # Cycle average of tags in use
3027system.l2c.tags.total_refs 437656 # Total number of references to valid blocks.
3028system.l2c.tags.sampled_refs 194611 # Sample count of references to valid blocks.
3029system.l2c.tags.avg_refs 2.248876 # Average number of references to valid blocks.
3030system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
3031system.l2c.tags.occ_blocks::writebacks 13531.746388 # Average occupied blocks per requestor
3032system.l2c.tags.occ_blocks::cpu0.dtb.walker 17.289436 # Average occupied blocks per requestor
3033system.l2c.tags.occ_blocks::cpu0.itb.walker 1.065903 # Average occupied blocks per requestor
3034system.l2c.tags.occ_blocks::cpu0.inst 8160.706658 # Average occupied blocks per requestor
3035system.l2c.tags.occ_blocks::cpu0.data 2775.310647 # Average occupied blocks per requestor
3036system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33971.574296 # Average occupied blocks per requestor
3037system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.602927 # Average occupied blocks per requestor
3038system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909521 # Average occupied blocks per requestor
3039system.l2c.tags.occ_blocks::cpu1.inst 1734.289932 # Average occupied blocks per requestor
3040system.l2c.tags.occ_blocks::cpu1.data 612.780861 # Average occupied blocks per requestor
3041system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2352.248246 # Average occupied blocks per requestor
3042system.l2c.tags.occ_percent::writebacks 0.206478 # Average percentage of cache occupancy
3043system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000264 # Average percentage of cache occupancy
3044system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy
3045system.l2c.tags.occ_percent::cpu0.inst 0.124523 # Average percentage of cache occupancy
3046system.l2c.tags.occ_percent::cpu0.data 0.042348 # Average percentage of cache occupancy
3047system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.518365 # Average percentage of cache occupancy
3048system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000070 # Average percentage of cache occupancy
3049system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy
3050system.l2c.tags.occ_percent::cpu1.inst 0.026463 # Average percentage of cache occupancy
3051system.l2c.tags.occ_percent::cpu1.data 0.009350 # Average percentage of cache occupancy
3052system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.035892 # Average percentage of cache occupancy
3053system.l2c.tags.occ_percent::total 0.963784 # Average percentage of cache occupancy
3054system.l2c.tags.occ_task_id_blocks::1022 30783 # Occupied blocks per task id
3055system.l2c.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id
3056system.l2c.tags.occ_task_id_blocks::1024 33327 # Occupied blocks per task id
3057system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
3058system.l2c.tags.age_task_id_blocks_1022::2 127 # Occupied blocks per task id
3059system.l2c.tags.age_task_id_blocks_1022::3 5989 # Occupied blocks per task id
3060system.l2c.tags.age_task_id_blocks_1022::4 24666 # Occupied blocks per task id
3061system.l2c.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id
3062system.l2c.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
3063system.l2c.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
3064system.l2c.tags.age_task_id_blocks_1024::2 626 # Occupied blocks per task id
3065system.l2c.tags.age_task_id_blocks_1024::3 4321 # Occupied blocks per task id
3066system.l2c.tags.age_task_id_blocks_1024::4 28334 # Occupied blocks per task id
3067system.l2c.tags.occ_task_id_percent::1022 0.469711 # Percentage of cache occupancy per task id
3068system.l2c.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id
3069system.l2c.tags.occ_task_id_percent::1024 0.508530 # Percentage of cache occupancy per task id
3070system.l2c.tags.tag_accesses 6042349 # Number of tag accesses
3071system.l2c.tags.data_accesses 6042349 # Number of data accesses
3072system.l2c.WritebackDirty_hits::writebacks 262546 # number of WritebackDirty hits
3073system.l2c.WritebackDirty_hits::total 262546 # number of WritebackDirty hits
3074system.l2c.UpgradeReq_hits::cpu0.data 32542 # number of UpgradeReq hits
3075system.l2c.UpgradeReq_hits::cpu1.data 2076 # number of UpgradeReq hits
3076system.l2c.UpgradeReq_hits::total 34618 # number of UpgradeReq hits
3077system.l2c.SCUpgradeReq_hits::cpu0.data 2163 # number of SCUpgradeReq hits
3078system.l2c.SCUpgradeReq_hits::cpu1.data 775 # number of SCUpgradeReq hits
3079system.l2c.SCUpgradeReq_hits::total 2938 # number of SCUpgradeReq hits
3080system.l2c.ReadExReq_hits::cpu0.data 3848 # number of ReadExReq hits
3081system.l2c.ReadExReq_hits::cpu1.data 1021 # number of ReadExReq hits
3082system.l2c.ReadExReq_hits::total 4869 # number of ReadExReq hits
3083system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 186 # number of ReadSharedReq hits
3084system.l2c.ReadSharedReq_hits::cpu0.itb.walker 96 # number of ReadSharedReq hits
3085system.l2c.ReadSharedReq_hits::cpu0.inst 34162 # number of ReadSharedReq hits
3086system.l2c.ReadSharedReq_hits::cpu0.data 48429 # number of ReadSharedReq hits
3087system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46477 # number of ReadSharedReq hits
3088system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 42 # number of ReadSharedReq hits
3089system.l2c.ReadSharedReq_hits::cpu1.itb.walker 13 # number of ReadSharedReq hits
3090system.l2c.ReadSharedReq_hits::cpu1.inst 7717 # number of ReadSharedReq hits
3091system.l2c.ReadSharedReq_hits::cpu1.data 5261 # number of ReadSharedReq hits
3092system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3686 # number of ReadSharedReq hits
3093system.l2c.ReadSharedReq_hits::total 146069 # number of ReadSharedReq hits
3094system.l2c.demand_hits::cpu0.dtb.walker 186 # number of demand (read+write) hits
3095system.l2c.demand_hits::cpu0.itb.walker 96 # number of demand (read+write) hits
3096system.l2c.demand_hits::cpu0.inst 34162 # number of demand (read+write) hits
3097system.l2c.demand_hits::cpu0.data 52277 # number of demand (read+write) hits
3098system.l2c.demand_hits::cpu0.l2cache.prefetcher 46477 # number of demand (read+write) hits
3099system.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits
3100system.l2c.demand_hits::cpu1.itb.walker 13 # number of demand (read+write) hits
3101system.l2c.demand_hits::cpu1.inst 7717 # number of demand (read+write) hits
3102system.l2c.demand_hits::cpu1.data 6282 # number of demand (read+write) hits
3103system.l2c.demand_hits::cpu1.l2cache.prefetcher 3686 # number of demand (read+write) hits
3104system.l2c.demand_hits::total 150938 # number of demand (read+write) hits
3105system.l2c.overall_hits::cpu0.dtb.walker 186 # number of overall hits
3106system.l2c.overall_hits::cpu0.itb.walker 96 # number of overall hits
3107system.l2c.overall_hits::cpu0.inst 34162 # number of overall hits
3108system.l2c.overall_hits::cpu0.data 52277 # number of overall hits
3109system.l2c.overall_hits::cpu0.l2cache.prefetcher 46477 # number of overall hits
3110system.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits
3111system.l2c.overall_hits::cpu1.itb.walker 13 # number of overall hits
3112system.l2c.overall_hits::cpu1.inst 7717 # number of overall hits
3113system.l2c.overall_hits::cpu1.data 6282 # number of overall hits
3114system.l2c.overall_hits::cpu1.l2cache.prefetcher 3686 # number of overall hits
3115system.l2c.overall_hits::total 150938 # number of overall hits
3116system.l2c.UpgradeReq_misses::cpu0.data 9567 # number of UpgradeReq misses
3117system.l2c.UpgradeReq_misses::cpu1.data 2216 # number of UpgradeReq misses
3118system.l2c.UpgradeReq_misses::total 11783 # number of UpgradeReq misses
3119system.l2c.SCUpgradeReq_misses::cpu0.data 708 # number of SCUpgradeReq misses
3120system.l2c.SCUpgradeReq_misses::cpu1.data 1237 # number of SCUpgradeReq misses
3121system.l2c.SCUpgradeReq_misses::total 1945 # number of SCUpgradeReq misses
3122system.l2c.ReadExReq_misses::cpu0.data 11710 # number of ReadExReq misses
3123system.l2c.ReadExReq_misses::cpu1.data 8783 # number of ReadExReq misses
3124system.l2c.ReadExReq_misses::total 20493 # number of ReadExReq misses
3125system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 28 # number of ReadSharedReq misses
3126system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses
3127system.l2c.ReadSharedReq_misses::cpu0.inst 19538 # number of ReadSharedReq misses
3128system.l2c.ReadSharedReq_misses::cpu0.data 9228 # number of ReadSharedReq misses
3129system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134710 # number of ReadSharedReq misses
3130system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 6 # number of ReadSharedReq misses
3131system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses
3132system.l2c.ReadSharedReq_misses::cpu1.inst 2825 # number of ReadSharedReq misses
3133system.l2c.ReadSharedReq_misses::cpu1.data 1059 # number of ReadSharedReq misses
3134system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6993 # number of ReadSharedReq misses
3135system.l2c.ReadSharedReq_misses::total 174391 # number of ReadSharedReq misses
3136system.l2c.demand_misses::cpu0.dtb.walker 28 # number of demand (read+write) misses
3137system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
3138system.l2c.demand_misses::cpu0.inst 19538 # number of demand (read+write) misses
3139system.l2c.demand_misses::cpu0.data 20938 # number of demand (read+write) misses
3140system.l2c.demand_misses::cpu0.l2cache.prefetcher 134710 # number of demand (read+write) misses
3141system.l2c.demand_misses::cpu1.dtb.walker 6 # number of demand (read+write) misses
3142system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
3143system.l2c.demand_misses::cpu1.inst 2825 # number of demand (read+write) misses
3144system.l2c.demand_misses::cpu1.data 9842 # number of demand (read+write) misses
3145system.l2c.demand_misses::cpu1.l2cache.prefetcher 6993 # number of demand (read+write) misses
3146system.l2c.demand_misses::total 194884 # number of demand (read+write) misses
3147system.l2c.overall_misses::cpu0.dtb.walker 28 # number of overall misses
3148system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
3149system.l2c.overall_misses::cpu0.inst 19538 # number of overall misses
3150system.l2c.overall_misses::cpu0.data 20938 # number of overall misses
3151system.l2c.overall_misses::cpu0.l2cache.prefetcher 134710 # number of overall misses
3152system.l2c.overall_misses::cpu1.dtb.walker 6 # number of overall misses
3153system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
3154system.l2c.overall_misses::cpu1.inst 2825 # number of overall misses
3155system.l2c.overall_misses::cpu1.data 9842 # number of overall misses
3156system.l2c.overall_misses::cpu1.l2cache.prefetcher 6993 # number of overall misses
3157system.l2c.overall_misses::total 194884 # number of overall misses
3158system.l2c.UpgradeReq_miss_latency::cpu0.data 21715500 # number of UpgradeReq miss cycles
3159system.l2c.UpgradeReq_miss_latency::cpu1.data 4407500 # number of UpgradeReq miss cycles
3160system.l2c.UpgradeReq_miss_latency::total 26123000 # number of UpgradeReq miss cycles
3161system.l2c.SCUpgradeReq_miss_latency::cpu0.data 5011500 # number of SCUpgradeReq miss cycles
3162system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2024500 # number of SCUpgradeReq miss cycles
3163system.l2c.SCUpgradeReq_miss_latency::total 7036000 # number of SCUpgradeReq miss cycles
3164system.l2c.ReadExReq_miss_latency::cpu0.data 1773470500 # number of ReadExReq miss cycles
3165system.l2c.ReadExReq_miss_latency::cpu1.data 1179481000 # number of ReadExReq miss cycles
3166system.l2c.ReadExReq_miss_latency::total 2952951500 # number of ReadExReq miss cycles
3167system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 4090000 # number of ReadSharedReq miss cycles
3168system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 388000 # number of ReadSharedReq miss cycles
3169system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2590822501 # number of ReadSharedReq miss cycles
3170system.l2c.ReadSharedReq_miss_latency::cpu0.data 1287354500 # number of ReadSharedReq miss cycles
3171system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 21311529164 # number of ReadSharedReq miss cycles
3172system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 838000 # number of ReadSharedReq miss cycles
3173system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 132500 # number of ReadSharedReq miss cycles
3174system.l2c.ReadSharedReq_miss_latency::cpu1.inst 379417500 # number of ReadSharedReq miss cycles
3175system.l2c.ReadSharedReq_miss_latency::cpu1.data 152189500 # number of ReadSharedReq miss cycles
3176system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1275537407 # number of ReadSharedReq miss cycles
3177system.l2c.ReadSharedReq_miss_latency::total 27002299072 # number of ReadSharedReq miss cycles
3178system.l2c.demand_miss_latency::cpu0.dtb.walker 4090000 # number of demand (read+write) miss cycles
3179system.l2c.demand_miss_latency::cpu0.itb.walker 388000 # number of demand (read+write) miss cycles
3180system.l2c.demand_miss_latency::cpu0.inst 2590822501 # number of demand (read+write) miss cycles
3181system.l2c.demand_miss_latency::cpu0.data 3060825000 # number of demand (read+write) miss cycles
3182system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 21311529164 # number of demand (read+write) miss cycles
3183system.l2c.demand_miss_latency::cpu1.dtb.walker 838000 # number of demand (read+write) miss cycles
3184system.l2c.demand_miss_latency::cpu1.itb.walker 132500 # number of demand (read+write) miss cycles
3185system.l2c.demand_miss_latency::cpu1.inst 379417500 # number of demand (read+write) miss cycles
3186system.l2c.demand_miss_latency::cpu1.data 1331670500 # number of demand (read+write) miss cycles
3187system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1275537407 # number of demand (read+write) miss cycles
3188system.l2c.demand_miss_latency::total 29955250572 # number of demand (read+write) miss cycles
3189system.l2c.overall_miss_latency::cpu0.dtb.walker 4090000 # number of overall miss cycles
3190system.l2c.overall_miss_latency::cpu0.itb.walker 388000 # number of overall miss cycles
3191system.l2c.overall_miss_latency::cpu0.inst 2590822501 # number of overall miss cycles
3192system.l2c.overall_miss_latency::cpu0.data 3060825000 # number of overall miss cycles
3193system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 21311529164 # number of overall miss cycles
3194system.l2c.overall_miss_latency::cpu1.dtb.walker 838000 # number of overall miss cycles
3195system.l2c.overall_miss_latency::cpu1.itb.walker 132500 # number of overall miss cycles
3196system.l2c.overall_miss_latency::cpu1.inst 379417500 # number of overall miss cycles
3197system.l2c.overall_miss_latency::cpu1.data 1331670500 # number of overall miss cycles
3198system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1275537407 # number of overall miss cycles
3199system.l2c.overall_miss_latency::total 29955250572 # number of overall miss cycles
3200system.l2c.WritebackDirty_accesses::writebacks 262546 # number of WritebackDirty accesses(hits+misses)
3201system.l2c.WritebackDirty_accesses::total 262546 # number of WritebackDirty accesses(hits+misses)
3202system.l2c.UpgradeReq_accesses::cpu0.data 42109 # number of UpgradeReq accesses(hits+misses)
3203system.l2c.UpgradeReq_accesses::cpu1.data 4292 # number of UpgradeReq accesses(hits+misses)
3204system.l2c.UpgradeReq_accesses::total 46401 # number of UpgradeReq accesses(hits+misses)
3205system.l2c.SCUpgradeReq_accesses::cpu0.data 2871 # number of SCUpgradeReq accesses(hits+misses)
3206system.l2c.SCUpgradeReq_accesses::cpu1.data 2012 # number of SCUpgradeReq accesses(hits+misses)
3207system.l2c.SCUpgradeReq_accesses::total 4883 # number of SCUpgradeReq accesses(hits+misses)
3208system.l2c.ReadExReq_accesses::cpu0.data 15558 # number of ReadExReq accesses(hits+misses)
3209system.l2c.ReadExReq_accesses::cpu1.data 9804 # number of ReadExReq accesses(hits+misses)
3210system.l2c.ReadExReq_accesses::total 25362 # number of ReadExReq accesses(hits+misses)
3211system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 214 # number of ReadSharedReq accesses(hits+misses)
3212system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 99 # number of ReadSharedReq accesses(hits+misses)
3213system.l2c.ReadSharedReq_accesses::cpu0.inst 53700 # number of ReadSharedReq accesses(hits+misses)
3214system.l2c.ReadSharedReq_accesses::cpu0.data 57657 # number of ReadSharedReq accesses(hits+misses)
3215system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 181187 # number of ReadSharedReq accesses(hits+misses)
3216system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 48 # number of ReadSharedReq accesses(hits+misses)
3217system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 14 # number of ReadSharedReq accesses(hits+misses)
3218system.l2c.ReadSharedReq_accesses::cpu1.inst 10542 # number of ReadSharedReq accesses(hits+misses)
3219system.l2c.ReadSharedReq_accesses::cpu1.data 6320 # number of ReadSharedReq accesses(hits+misses)
3220system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 10679 # number of ReadSharedReq accesses(hits+misses)
3221system.l2c.ReadSharedReq_accesses::total 320460 # number of ReadSharedReq accesses(hits+misses)
3222system.l2c.demand_accesses::cpu0.dtb.walker 214 # number of demand (read+write) accesses
3223system.l2c.demand_accesses::cpu0.itb.walker 99 # number of demand (read+write) accesses
3224system.l2c.demand_accesses::cpu0.inst 53700 # number of demand (read+write) accesses
3225system.l2c.demand_accesses::cpu0.data 73215 # number of demand (read+write) accesses
3226system.l2c.demand_accesses::cpu0.l2cache.prefetcher 181187 # number of demand (read+write) accesses
3227system.l2c.demand_accesses::cpu1.dtb.walker 48 # number of demand (read+write) accesses
3228system.l2c.demand_accesses::cpu1.itb.walker 14 # number of demand (read+write) accesses
3229system.l2c.demand_accesses::cpu1.inst 10542 # number of demand (read+write) accesses
3230system.l2c.demand_accesses::cpu1.data 16124 # number of demand (read+write) accesses
3231system.l2c.demand_accesses::cpu1.l2cache.prefetcher 10679 # number of demand (read+write) accesses
3232system.l2c.demand_accesses::total 345822 # number of demand (read+write) accesses
3233system.l2c.overall_accesses::cpu0.dtb.walker 214 # number of overall (read+write) accesses
3234system.l2c.overall_accesses::cpu0.itb.walker 99 # number of overall (read+write) accesses
3235system.l2c.overall_accesses::cpu0.inst 53700 # number of overall (read+write) accesses
3236system.l2c.overall_accesses::cpu0.data 73215 # number of overall (read+write) accesses
3237system.l2c.overall_accesses::cpu0.l2cache.prefetcher 181187 # number of overall (read+write) accesses
3238system.l2c.overall_accesses::cpu1.dtb.walker 48 # number of overall (read+write) accesses
3239system.l2c.overall_accesses::cpu1.itb.walker 14 # number of overall (read+write) accesses
3240system.l2c.overall_accesses::cpu1.inst 10542 # number of overall (read+write) accesses
3241system.l2c.overall_accesses::cpu1.data 16124 # number of overall (read+write) accesses
3242system.l2c.overall_accesses::cpu1.l2cache.prefetcher 10679 # number of overall (read+write) accesses
3243system.l2c.overall_accesses::total 345822 # number of overall (read+write) accesses
3244system.l2c.UpgradeReq_miss_rate::cpu0.data 0.227196 # miss rate for UpgradeReq accesses
3245system.l2c.UpgradeReq_miss_rate::cpu1.data 0.516309 # miss rate for UpgradeReq accesses
3246system.l2c.UpgradeReq_miss_rate::total 0.253938 # miss rate for UpgradeReq accesses
3247system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.246604 # miss rate for SCUpgradeReq accesses
3248system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.614811 # miss rate for SCUpgradeReq accesses
3249system.l2c.SCUpgradeReq_miss_rate::total 0.398321 # miss rate for SCUpgradeReq accesses
3250system.l2c.ReadExReq_miss_rate::cpu0.data 0.752667 # miss rate for ReadExReq accesses
3251system.l2c.ReadExReq_miss_rate::cpu1.data 0.895859 # miss rate for ReadExReq accesses
3252system.l2c.ReadExReq_miss_rate::total 0.808020 # miss rate for ReadExReq accesses
3253system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.130841 # miss rate for ReadSharedReq accesses
3254system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.030303 # miss rate for ReadSharedReq accesses
3255system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.363836 # miss rate for ReadSharedReq accesses
3256system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.160050 # miss rate for ReadSharedReq accesses
3257system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.743486 # miss rate for ReadSharedReq accesses
3258system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for ReadSharedReq accesses
3259system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.071429 # miss rate for ReadSharedReq accesses
3260system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.267976 # miss rate for ReadSharedReq accesses
3261system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.167563 # miss rate for ReadSharedReq accesses
3262system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.654837 # miss rate for ReadSharedReq accesses
3263system.l2c.ReadSharedReq_miss_rate::total 0.544190 # miss rate for ReadSharedReq accesses
3264system.l2c.demand_miss_rate::cpu0.dtb.walker 0.130841 # miss rate for demand accesses
3265system.l2c.demand_miss_rate::cpu0.itb.walker 0.030303 # miss rate for demand accesses
3266system.l2c.demand_miss_rate::cpu0.inst 0.363836 # miss rate for demand accesses
3267system.l2c.demand_miss_rate::cpu0.data 0.285980 # miss rate for demand accesses
3268system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.743486 # miss rate for demand accesses
3269system.l2c.demand_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for demand accesses
3270system.l2c.demand_miss_rate::cpu1.itb.walker 0.071429 # miss rate for demand accesses
3271system.l2c.demand_miss_rate::cpu1.inst 0.267976 # miss rate for demand accesses
3272system.l2c.demand_miss_rate::cpu1.data 0.610394 # miss rate for demand accesses
3273system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.654837 # miss rate for demand accesses
3274system.l2c.demand_miss_rate::total 0.563538 # miss rate for demand accesses
3275system.l2c.overall_miss_rate::cpu0.dtb.walker 0.130841 # miss rate for overall accesses
3276system.l2c.overall_miss_rate::cpu0.itb.walker 0.030303 # miss rate for overall accesses
3277system.l2c.overall_miss_rate::cpu0.inst 0.363836 # miss rate for overall accesses
3278system.l2c.overall_miss_rate::cpu0.data 0.285980 # miss rate for overall accesses
3279system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.743486 # miss rate for overall accesses
3280system.l2c.overall_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for overall accesses
3281system.l2c.overall_miss_rate::cpu1.itb.walker 0.071429 # miss rate for overall accesses
3282system.l2c.overall_miss_rate::cpu1.inst 0.267976 # miss rate for overall accesses
3283system.l2c.overall_miss_rate::cpu1.data 0.610394 # miss rate for overall accesses
3284system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.654837 # miss rate for overall accesses
3285system.l2c.overall_miss_rate::total 0.563538 # miss rate for overall accesses
3286system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2269.833804 # average UpgradeReq miss latency
3287system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1988.944043 # average UpgradeReq miss latency
3288system.l2c.UpgradeReq_avg_miss_latency::total 2217.007553 # average UpgradeReq miss latency
3289system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7078.389831 # average SCUpgradeReq miss latency
3290system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1636.620857 # average SCUpgradeReq miss latency
3291system.l2c.SCUpgradeReq_avg_miss_latency::total 3617.480720 # average SCUpgradeReq miss latency
3292system.l2c.ReadExReq_avg_miss_latency::cpu0.data 151449.231426 # average ReadExReq miss latency
3293system.l2c.ReadExReq_avg_miss_latency::cpu1.data 134291.358306 # average ReadExReq miss latency
3294system.l2c.ReadExReq_avg_miss_latency::total 144095.618016 # average ReadExReq miss latency
3295system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 146071.428571 # average ReadSharedReq miss latency
3296system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 129333.333333 # average ReadSharedReq miss latency
3297system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132604.284011 # average ReadSharedReq miss latency
3298system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139505.255743 # average ReadSharedReq miss latency
3299system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 158203.022522 # average ReadSharedReq miss latency
3300system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 139666.666667 # average ReadSharedReq miss latency
3301system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 132500 # average ReadSharedReq miss latency
3302system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134307.079646 # average ReadSharedReq miss latency
3303system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 143710.576015 # average ReadSharedReq miss latency
3304system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 182402.031603 # average ReadSharedReq miss latency
3305system.l2c.ReadSharedReq_avg_miss_latency::total 154837.686991 # average ReadSharedReq miss latency
3306system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 146071.428571 # average overall miss latency
3307system.l2c.demand_avg_miss_latency::cpu0.itb.walker 129333.333333 # average overall miss latency
3308system.l2c.demand_avg_miss_latency::cpu0.inst 132604.284011 # average overall miss latency
3309system.l2c.demand_avg_miss_latency::cpu0.data 146185.165727 # average overall miss latency
3310system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 158203.022522 # average overall miss latency
3311system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139666.666667 # average overall miss latency
3312system.l2c.demand_avg_miss_latency::cpu1.itb.walker 132500 # average overall miss latency
3313system.l2c.demand_avg_miss_latency::cpu1.inst 134307.079646 # average overall miss latency
3314system.l2c.demand_avg_miss_latency::cpu1.data 135304.866897 # average overall miss latency
3315system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 182402.031603 # average overall miss latency
3316system.l2c.demand_avg_miss_latency::total 153708.106217 # average overall miss latency
3317system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 146071.428571 # average overall miss latency
3318system.l2c.overall_avg_miss_latency::cpu0.itb.walker 129333.333333 # average overall miss latency
3319system.l2c.overall_avg_miss_latency::cpu0.inst 132604.284011 # average overall miss latency
3320system.l2c.overall_avg_miss_latency::cpu0.data 146185.165727 # average overall miss latency
3321system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 158203.022522 # average overall miss latency
3322system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139666.666667 # average overall miss latency
3323system.l2c.overall_avg_miss_latency::cpu1.itb.walker 132500 # average overall miss latency
3324system.l2c.overall_avg_miss_latency::cpu1.inst 134307.079646 # average overall miss latency
3325system.l2c.overall_avg_miss_latency::cpu1.data 135304.866897 # average overall miss latency
3326system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 182402.031603 # average overall miss latency
3327system.l2c.overall_avg_miss_latency::total 153708.106217 # average overall miss latency
3328system.l2c.blocked_cycles::no_mshrs 1429 # number of cycles access was blocked
3329system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
3330system.l2c.blocked::no_mshrs 10 # number of cycles access was blocked
3331system.l2c.blocked::no_targets 0 # number of cycles access was blocked
3332system.l2c.avg_blocked_cycles::no_mshrs 142.900000 # average number of cycles each access was blocked
3333system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3334system.l2c.fast_writes 0 # number of fast writes performed
3335system.l2c.cache_copies 0 # number of cache copies performed
3336system.l2c.writebacks::writebacks 102119 # number of writebacks
3337system.l2c.writebacks::total 102119 # number of writebacks
3338system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 10 # number of ReadSharedReq MSHR hits
3339system.l2c.ReadSharedReq_mshr_hits::cpu0.data 2 # number of ReadSharedReq MSHR hits
3340system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 13 # number of ReadSharedReq MSHR hits
3341system.l2c.ReadSharedReq_mshr_hits::total 25 # number of ReadSharedReq MSHR hits
3342system.l2c.demand_mshr_hits::cpu0.inst 10 # number of demand (read+write) MSHR hits
3343system.l2c.demand_mshr_hits::cpu0.data 2 # number of demand (read+write) MSHR hits
3344system.l2c.demand_mshr_hits::cpu1.inst 13 # number of demand (read+write) MSHR hits
3345system.l2c.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits
3346system.l2c.overall_mshr_hits::cpu0.inst 10 # number of overall MSHR hits
3347system.l2c.overall_mshr_hits::cpu0.data 2 # number of overall MSHR hits
3348system.l2c.overall_mshr_hits::cpu1.inst 13 # number of overall MSHR hits
3349system.l2c.overall_mshr_hits::total 25 # number of overall MSHR hits
3350system.l2c.CleanEvict_mshr_misses::writebacks 3254 # number of CleanEvict MSHR misses
3351system.l2c.CleanEvict_mshr_misses::total 3254 # number of CleanEvict MSHR misses
3352system.l2c.UpgradeReq_mshr_misses::cpu0.data 9567 # number of UpgradeReq MSHR misses
3353system.l2c.UpgradeReq_mshr_misses::cpu1.data 2216 # number of UpgradeReq MSHR misses
3354system.l2c.UpgradeReq_mshr_misses::total 11783 # number of UpgradeReq MSHR misses
3355system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 708 # number of SCUpgradeReq MSHR misses
3356system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1237 # number of SCUpgradeReq MSHR misses
3357system.l2c.SCUpgradeReq_mshr_misses::total 1945 # number of SCUpgradeReq MSHR misses
3358system.l2c.ReadExReq_mshr_misses::cpu0.data 11710 # number of ReadExReq MSHR misses
3359system.l2c.ReadExReq_mshr_misses::cpu1.data 8783 # number of ReadExReq MSHR misses
3360system.l2c.ReadExReq_mshr_misses::total 20493 # number of ReadExReq MSHR misses
3361system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 28 # number of ReadSharedReq MSHR misses
3362system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3 # number of ReadSharedReq MSHR misses
3363system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19528 # number of ReadSharedReq MSHR misses
3364system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9226 # number of ReadSharedReq MSHR misses
3365system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134710 # number of ReadSharedReq MSHR misses
3366system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 6 # number of ReadSharedReq MSHR misses
3367system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses
3368system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2812 # number of ReadSharedReq MSHR misses
3369system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1059 # number of ReadSharedReq MSHR misses
3370system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6993 # number of ReadSharedReq MSHR misses
3371system.l2c.ReadSharedReq_mshr_misses::total 174366 # number of ReadSharedReq MSHR misses
3372system.l2c.demand_mshr_misses::cpu0.dtb.walker 28 # number of demand (read+write) MSHR misses
3373system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses
3374system.l2c.demand_mshr_misses::cpu0.inst 19528 # number of demand (read+write) MSHR misses
3375system.l2c.demand_mshr_misses::cpu0.data 20936 # number of demand (read+write) MSHR misses
3376system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134710 # number of demand (read+write) MSHR misses
3377system.l2c.demand_mshr_misses::cpu1.dtb.walker 6 # number of demand (read+write) MSHR misses
3378system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
3379system.l2c.demand_mshr_misses::cpu1.inst 2812 # number of demand (read+write) MSHR misses
3380system.l2c.demand_mshr_misses::cpu1.data 9842 # number of demand (read+write) MSHR misses
3381system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6993 # number of demand (read+write) MSHR misses
3382system.l2c.demand_mshr_misses::total 194859 # number of demand (read+write) MSHR misses
3383system.l2c.overall_mshr_misses::cpu0.dtb.walker 28 # number of overall MSHR misses
3384system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses
3385system.l2c.overall_mshr_misses::cpu0.inst 19528 # number of overall MSHR misses
3386system.l2c.overall_mshr_misses::cpu0.data 20936 # number of overall MSHR misses
3387system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134710 # number of overall MSHR misses
3388system.l2c.overall_mshr_misses::cpu1.dtb.walker 6 # number of overall MSHR misses
3389system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
3390system.l2c.overall_mshr_misses::cpu1.inst 2812 # number of overall MSHR misses
3391system.l2c.overall_mshr_misses::cpu1.data 9842 # number of overall MSHR misses
3392system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6993 # number of overall MSHR misses
3393system.l2c.overall_mshr_misses::total 194859 # number of overall MSHR misses
3394system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable
3395system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31816 # number of ReadReq MSHR uncacheable
3396system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable
3397system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3072 # number of ReadReq MSHR uncacheable
3398system.l2c.ReadReq_mshr_uncacheable::total 37993 # number of ReadReq MSHR uncacheable
3399system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable
3400system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2419 # number of WriteReq MSHR uncacheable
3401system.l2c.WriteReq_mshr_uncacheable::total 30918 # number of WriteReq MSHR uncacheable
3402system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses
3403system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60315 # number of overall MSHR uncacheable misses
3404system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses
3405system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5491 # number of overall MSHR uncacheable misses
3406system.l2c.overall_mshr_uncacheable_misses::total 68911 # number of overall MSHR uncacheable misses
3407system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 695501500 # number of UpgradeReq MSHR miss cycles
3408system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 159987500 # number of UpgradeReq MSHR miss cycles
3409system.l2c.UpgradeReq_mshr_miss_latency::total 855489000 # number of UpgradeReq MSHR miss cycles
3410system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 52831000 # number of SCUpgradeReq MSHR miss cycles
3411system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 91356500 # number of SCUpgradeReq MSHR miss cycles
3412system.l2c.SCUpgradeReq_mshr_miss_latency::total 144187500 # number of SCUpgradeReq MSHR miss cycles
3413system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1656368005 # number of ReadExReq MSHR miss cycles
3414system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1091646012 # number of ReadExReq MSHR miss cycles
3415system.l2c.ReadExReq_mshr_miss_latency::total 2748014017 # number of ReadExReq MSHR miss cycles
3416system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 3810000 # number of ReadSharedReq MSHR miss cycles
3417system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 358000 # number of ReadSharedReq MSHR miss cycles
3418system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2394651541 # number of ReadSharedReq MSHR miss cycles
3419system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1194908505 # number of ReadSharedReq MSHR miss cycles
3420system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 19964396279 # number of ReadSharedReq MSHR miss cycles
3421system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 778000 # number of ReadSharedReq MSHR miss cycles
3422system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 122500 # number of ReadSharedReq MSHR miss cycles
3423system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 349721537 # number of ReadSharedReq MSHR miss cycles
3424system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 141598503 # number of ReadSharedReq MSHR miss cycles
3425system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1205596470 # number of ReadSharedReq MSHR miss cycles
3426system.l2c.ReadSharedReq_mshr_miss_latency::total 25255941335 # number of ReadSharedReq MSHR miss cycles
3427system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3810000 # number of demand (read+write) MSHR miss cycles
3428system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 358000 # number of demand (read+write) MSHR miss cycles
3429system.l2c.demand_mshr_miss_latency::cpu0.inst 2394651541 # number of demand (read+write) MSHR miss cycles
3430system.l2c.demand_mshr_miss_latency::cpu0.data 2851276510 # number of demand (read+write) MSHR miss cycles
3431system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 19964396279 # number of demand (read+write) MSHR miss cycles
3432system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 778000 # number of demand (read+write) MSHR miss cycles
3433system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 122500 # number of demand (read+write) MSHR miss cycles
3434system.l2c.demand_mshr_miss_latency::cpu1.inst 349721537 # number of demand (read+write) MSHR miss cycles
3435system.l2c.demand_mshr_miss_latency::cpu1.data 1233244515 # number of demand (read+write) MSHR miss cycles
3436system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1205596470 # number of demand (read+write) MSHR miss cycles
3437system.l2c.demand_mshr_miss_latency::total 28003955352 # number of demand (read+write) MSHR miss cycles
3438system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3810000 # number of overall MSHR miss cycles
3439system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 358000 # number of overall MSHR miss cycles
3440system.l2c.overall_mshr_miss_latency::cpu0.inst 2394651541 # number of overall MSHR miss cycles
3441system.l2c.overall_mshr_miss_latency::cpu0.data 2851276510 # number of overall MSHR miss cycles
3442system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 19964396279 # number of overall MSHR miss cycles
3443system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 778000 # number of overall MSHR miss cycles
3444system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 122500 # number of overall MSHR miss cycles
3445system.l2c.overall_mshr_miss_latency::cpu1.inst 349721537 # number of overall MSHR miss cycles
3446system.l2c.overall_mshr_miss_latency::cpu1.data 1233244515 # number of overall MSHR miss cycles
3447system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1205596470 # number of overall MSHR miss cycles
3448system.l2c.overall_mshr_miss_latency::total 28003955352 # number of overall MSHR miss cycles
3449system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 343998000 # number of ReadReq MSHR uncacheable cycles
3450system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5796362003 # number of ReadReq MSHR uncacheable cycles
3451system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11053000 # number of ReadReq MSHR uncacheable cycles
3452system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 358428504 # number of ReadReq MSHR uncacheable cycles
3453system.l2c.ReadReq_mshr_uncacheable_latency::total 6509841507 # number of ReadReq MSHR uncacheable cycles
3454system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4693982535 # number of WriteReq MSHR uncacheable cycles
3455system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 242306006 # number of WriteReq MSHR uncacheable cycles
3456system.l2c.WriteReq_mshr_uncacheable_latency::total 4936288541 # number of WriteReq MSHR uncacheable cycles
3457system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 343998000 # number of overall MSHR uncacheable cycles
3458system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10490344538 # number of overall MSHR uncacheable cycles
3459system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11053000 # number of overall MSHR uncacheable cycles
3460system.l2c.overall_mshr_uncacheable_latency::cpu1.data 600734510 # number of overall MSHR uncacheable cycles
3461system.l2c.overall_mshr_uncacheable_latency::total 11446130048 # number of overall MSHR uncacheable cycles
3462system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3463system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3464system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.227196 # mshr miss rate for UpgradeReq accesses
3465system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.516309 # mshr miss rate for UpgradeReq accesses
3466system.l2c.UpgradeReq_mshr_miss_rate::total 0.253938 # mshr miss rate for UpgradeReq accesses
3467system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.246604 # mshr miss rate for SCUpgradeReq accesses
3468system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.614811 # mshr miss rate for SCUpgradeReq accesses
3469system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.398321 # mshr miss rate for SCUpgradeReq accesses
3470system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.752667 # mshr miss rate for ReadExReq accesses
3471system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.895859 # mshr miss rate for ReadExReq accesses
3472system.l2c.ReadExReq_mshr_miss_rate::total 0.808020 # mshr miss rate for ReadExReq accesses
3473system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.130841 # mshr miss rate for ReadSharedReq accesses
3474system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.030303 # mshr miss rate for ReadSharedReq accesses
3475system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.363650 # mshr miss rate for ReadSharedReq accesses
3476system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.160015 # mshr miss rate for ReadSharedReq accesses
3477system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743486 # mshr miss rate for ReadSharedReq accesses
3478system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for ReadSharedReq accesses
3479system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.071429 # mshr miss rate for ReadSharedReq accesses
3480system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.266743 # mshr miss rate for ReadSharedReq accesses
3481system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.167563 # mshr miss rate for ReadSharedReq accesses
3482system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.654837 # mshr miss rate for ReadSharedReq accesses
3483system.l2c.ReadSharedReq_mshr_miss_rate::total 0.544112 # mshr miss rate for ReadSharedReq accesses
3484system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.130841 # mshr miss rate for demand accesses
3485system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.030303 # mshr miss rate for demand accesses
3486system.l2c.demand_mshr_miss_rate::cpu0.inst 0.363650 # mshr miss rate for demand accesses
3487system.l2c.demand_mshr_miss_rate::cpu0.data 0.285952 # mshr miss rate for demand accesses
3488system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743486 # mshr miss rate for demand accesses
3489system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for demand accesses
3490system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.071429 # mshr miss rate for demand accesses
3491system.l2c.demand_mshr_miss_rate::cpu1.inst 0.266743 # mshr miss rate for demand accesses
3492system.l2c.demand_mshr_miss_rate::cpu1.data 0.610394 # mshr miss rate for demand accesses
3493system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.654837 # mshr miss rate for demand accesses
3494system.l2c.demand_mshr_miss_rate::total 0.563466 # mshr miss rate for demand accesses
3495system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.130841 # mshr miss rate for overall accesses
3496system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.030303 # mshr miss rate for overall accesses
3497system.l2c.overall_mshr_miss_rate::cpu0.inst 0.363650 # mshr miss rate for overall accesses
3498system.l2c.overall_mshr_miss_rate::cpu0.data 0.285952 # mshr miss rate for overall accesses
3499system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743486 # mshr miss rate for overall accesses
3500system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for overall accesses
3501system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.071429 # mshr miss rate for overall accesses
3502system.l2c.overall_mshr_miss_rate::cpu1.inst 0.266743 # mshr miss rate for overall accesses
3503system.l2c.overall_mshr_miss_rate::cpu1.data 0.610394 # mshr miss rate for overall accesses
3504system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.654837 # mshr miss rate for overall accesses
3505system.l2c.overall_mshr_miss_rate::total 0.563466 # mshr miss rate for overall accesses
3506system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72697.972196 # average UpgradeReq mshr miss latency
3507system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72196.525271 # average UpgradeReq mshr miss latency
3508system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72603.666299 # average UpgradeReq mshr miss latency
3509system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74620.056497 # average SCUpgradeReq mshr miss latency
3510system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73853.274050 # average SCUpgradeReq mshr miss latency
3511system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74132.390746 # average SCUpgradeReq mshr miss latency
3512system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141449.018360 # average ReadExReq mshr miss latency
3513system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124290.790391 # average ReadExReq mshr miss latency
3514system.l2c.ReadExReq_avg_mshr_miss_latency::total 134095.252867 # average ReadExReq mshr miss latency
3515system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 136071.428571 # average ReadSharedReq mshr miss latency
3516system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average ReadSharedReq mshr miss latency
3517system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122626.563959 # average ReadSharedReq mshr miss latency
3518system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129515.337633 # average ReadSharedReq mshr miss latency
3519system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148202.778405 # average ReadSharedReq mshr miss latency
3520system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129666.666667 # average ReadSharedReq mshr miss latency
3521system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average ReadSharedReq mshr miss latency
3522system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124367.545164 # average ReadSharedReq mshr miss latency
3523system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 133709.634561 # average ReadSharedReq mshr miss latency
3524system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 172400.467610 # average ReadSharedReq mshr miss latency
3525system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144844.415396 # average ReadSharedReq mshr miss latency
3526system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 136071.428571 # average overall mshr miss latency
3527system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency
3528system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122626.563959 # average overall mshr miss latency
3529system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136190.127532 # average overall mshr miss latency
3530system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148202.778405 # average overall mshr miss latency
3531system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129666.666667 # average overall mshr miss latency
3532system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average overall mshr miss latency
3533system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124367.545164 # average overall mshr miss latency
3534system.l2c.demand_avg_mshr_miss_latency::cpu1.data 125304.258789 # average overall mshr miss latency
3535system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 172400.467610 # average overall mshr miss latency
3536system.l2c.demand_avg_mshr_miss_latency::total 143713.943682 # average overall mshr miss latency
3537system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 136071.428571 # average overall mshr miss latency
3538system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency
3539system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122626.563959 # average overall mshr miss latency
3540system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136190.127532 # average overall mshr miss latency
3541system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148202.778405 # average overall mshr miss latency
3542system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129666.666667 # average overall mshr miss latency
3543system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average overall mshr miss latency
3544system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124367.545164 # average overall mshr miss latency
3545system.l2c.overall_avg_mshr_miss_latency::cpu1.data 125304.258789 # average overall mshr miss latency
3546system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 172400.467610 # average overall mshr miss latency
3547system.l2c.overall_avg_mshr_miss_latency::total 143713.943682 # average overall mshr miss latency
3548system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114551.448551 # average ReadReq mshr uncacheable latency
3549system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182183.869845 # average ReadReq mshr uncacheable latency
3550system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108362.745098 # average ReadReq mshr uncacheable latency
3551system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116675.945312 # average ReadReq mshr uncacheable latency
3552system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171343.181823 # average ReadReq mshr uncacheable latency
3553system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164706.920769 # average WriteReq mshr uncacheable latency
3554system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100167.840430 # average WriteReq mshr uncacheable latency
3555system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159657.433890 # average WriteReq mshr uncacheable latency
3556system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114551.448551 # average overall mshr uncacheable latency
3557system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173925.964321 # average overall mshr uncacheable latency
3558system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108362.745098 # average overall mshr uncacheable latency
3559system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109403.480240 # average overall mshr uncacheable latency
3560system.l2c.overall_avg_mshr_uncacheable_latency::total 166100.187895 # average overall mshr uncacheable latency
3561system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
3562system.membus.trans_dist::ReadReq 37993 # Transaction distribution
3563system.membus.trans_dist::ReadResp 212610 # Transaction distribution
3564system.membus.trans_dist::WriteReq 30918 # Transaction distribution
3565system.membus.trans_dist::WriteResp 30918 # Transaction distribution
3566system.membus.trans_dist::WritebackDirty 138325 # Transaction distribution
3567system.membus.trans_dist::CleanEvict 16163 # Transaction distribution
3568system.membus.trans_dist::UpgradeReq 72828 # Transaction distribution
3569system.membus.trans_dist::SCUpgradeReq 40466 # Transaction distribution
3570system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
3571system.membus.trans_dist::ReadExReq 40267 # Transaction distribution
3572system.membus.trans_dist::ReadExResp 20420 # Transaction distribution
3573system.membus.trans_dist::ReadSharedReq 174618 # Transaction distribution
3574system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
3575system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes)
3576system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes)
3577system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13740 # Packet count per connected master and slave (bytes)
3578system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 656523 # Packet count per connected master and slave (bytes)
3579system.membus.pkt_count_system.l2c.mem_side::total 778231 # Packet count per connected master and slave (bytes)
3580system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes)
3581system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes)
3582system.membus.pkt_count::total 851180 # Packet count per connected master and slave (bytes)
3583system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes)
3584system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes)
3585system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27480 # Cumulative packet size per connected master and slave (bytes)
3586system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19049928 # Cumulative packet size per connected master and slave (bytes)
3587system.membus.pkt_size_system.l2c.mem_side::total 19240508 # Cumulative packet size per connected master and slave (bytes)
3588system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
3589system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
3590system.membus.pkt_size::total 21558652 # Cumulative packet size per connected master and slave (bytes)
3591system.membus.snoops 119912 # Total snoops (count)
3592system.membus.snoop_fanout::samples 587818 # Request fanout histogram
3593system.membus.snoop_fanout::mean 1 # Request fanout histogram
3594system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3595system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3596system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3597system.membus.snoop_fanout::1 587818 100.00% 100.00% # Request fanout histogram
3598system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3599system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3600system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3601system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3602system.membus.snoop_fanout::total 587818 # Request fanout histogram
3603system.membus.reqLayer0.occupancy 81915500 # Layer occupancy (ticks)
3604system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3605system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks)
3606system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3607system.membus.reqLayer2.occupancy 11626486 # Layer occupancy (ticks)
3608system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3609system.membus.reqLayer5.occupancy 1006913072 # Layer occupancy (ticks)
3610system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3611system.membus.respLayer2.occupancy 1122228815 # Layer occupancy (ticks)
3612system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3613system.membus.respLayer3.occupancy 1359881 # Layer occupancy (ticks)
3614system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3615system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3616system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3617system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3618system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3619system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3620system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3621system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA

--- 26 unchanged lines hidden (view full) ---

3648system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3649system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
3650system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
3651system.realview.ethernet.droppedPackets 0 # number of packets dropped
3652system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3653system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3654system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3655system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3656system.toL2Bus.snoop_filter.tot_requests 988623 # Total number of requests made to the snoop filter.
3657system.toL2Bus.snoop_filter.hit_single_requests 533441 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3658system.toL2Bus.snoop_filter.hit_multi_requests 142864 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3659system.toL2Bus.snoop_filter.tot_snoops 21333 # Total number of snoops made to the snoop filter.
3660system.toL2Bus.snoop_filter.hit_single_snoops 20424 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3661system.toL2Bus.snoop_filter.hit_multi_snoops 909 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3662system.toL2Bus.trans_dist::ReadReq 37996 # Transaction distribution
3663system.toL2Bus.trans_dist::ReadResp 474339 # Transaction distribution
3664system.toL2Bus.trans_dist::WriteReq 30918 # Transaction distribution
3665system.toL2Bus.trans_dist::WriteResp 30918 # Transaction distribution
3666system.toL2Bus.trans_dist::WritebackDirty 400884 # Transaction distribution
3667system.toL2Bus.trans_dist::CleanEvict 117322 # Transaction distribution
3668system.toL2Bus.trans_dist::UpgradeReq 107373 # Transaction distribution
3669system.toL2Bus.trans_dist::SCUpgradeReq 43404 # Transaction distribution
3670system.toL2Bus.trans_dist::UpgradeResp 150777 # Transaction distribution
3671system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution
3672system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
3673system.toL2Bus.trans_dist::ReadExReq 50440 # Transaction distribution
3674system.toL2Bus.trans_dist::ReadExResp 50440 # Transaction distribution
3675system.toL2Bus.trans_dist::ReadSharedReq 436359 # Transaction distribution
3676system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
3677system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1256848 # Packet count per connected master and slave (bytes)
3678system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 266902 # Packet count per connected master and slave (bytes)
3679system.toL2Bus.pkt_count::total 1523750 # Packet count per connected master and slave (bytes)
3680system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34918134 # Cumulative packet size per connected master and slave (bytes)
3681system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4292486 # Cumulative packet size per connected master and slave (bytes)
3682system.toL2Bus.pkt_size::total 39210620 # Cumulative packet size per connected master and slave (bytes)
3683system.toL2Bus.snoops 443927 # Total snoops (count)
3684system.toL2Bus.snoop_fanout::samples 909712 # Request fanout histogram
3685system.toL2Bus.snoop_fanout::mean 0.336026 # Request fanout histogram
3686system.toL2Bus.snoop_fanout::stdev 0.474459 # Request fanout histogram
3687system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3688system.toL2Bus.snoop_fanout::0 604934 66.50% 66.50% # Request fanout histogram
3689system.toL2Bus.snoop_fanout::1 303869 33.40% 99.90% # Request fanout histogram
3690system.toL2Bus.snoop_fanout::2 909 0.10% 100.00% # Request fanout histogram
3691system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3692system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3693system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3694system.toL2Bus.snoop_fanout::total 909712 # Request fanout histogram
3695system.toL2Bus.reqLayer0.occupancy 874582688 # Layer occupancy (ticks)
3696system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3697system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks)
3698system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3699system.toL2Bus.respLayer0.occupancy 652718656 # Layer occupancy (ticks)
3700system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3701system.toL2Bus.respLayer1.occupancy 208359113 # Layer occupancy (ticks)
3702system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3703system.cpu0.kern.inst.arm 0 # number of arm instructions executed
3704system.cpu0.kern.inst.quiesce 1876 # number of quiesce instructions executed
3705system.cpu1.kern.inst.arm 0 # number of arm instructions executed
3706system.cpu1.kern.inst.quiesce 2727 # number of quiesce instructions executed
3707
3708---------- End Simulation Statistics ----------