1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.625395 # Number of seconds simulated
4sim_ticks 2625394935000 # Number of ticks simulated
5final_tick 2625394935000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 71798 # Simulator instruction rate (inst/s)
8host_op_rate 87106 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1566670818 # Simulator tick rate (ticks/s)
10host_mem_usage 647044 # Number of bytes of host memory used
11host_seconds 1675.78 # Real time elapsed on the host
12sim_insts 120317196 # Number of instructions simulated
13sim_ops 145970023 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 448 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1152320 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 1224232 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8325184 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 318816 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 736276 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 690624 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
27system.physmem.bytes_read::total 12451228 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 1152320 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 318816 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 1471136 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 9003520 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
34system.physmem.bytes_written::total 9021084 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 7 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 20252 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 19649 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 130081 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.inst 5049 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.data 11525 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.l2cache.prefetcher 10791 # Number of read requests responded to by this memory
45system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
46system.physmem.num_reads::total 197406 # Number of read requests responded to by this memory
47system.physmem.num_writes::writebacks 140680 # Number of write requests responded to by this memory
48system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
50system.physmem.num_writes::total 145071 # Number of write requests responded to by this memory
51system.physmem.bw_read::cpu0.dtb.walker 609 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.itb.walker 171 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.inst 438913 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.data 466304 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.l2cache.prefetcher 3171022 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.dtb.walker 244 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.inst 121435 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.data 280444 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.l2cache.prefetcher 263055 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::realview.ide 366 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::total 4742611 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::cpu0.inst 438913 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu1.inst 121435 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::total 560348 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_write::writebacks 3429396 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::cpu0.data 6675 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::total 3436086 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_total::writebacks 3429396 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.dtb.walker 609 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.itb.walker 171 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.inst 438913 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.data 472979 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.l2cache.prefetcher 3171022 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.dtb.walker 244 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.inst 121435 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.data 280459 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.l2cache.prefetcher 263055 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.ide 366 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::total 8178698 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.readReqs 197407 # Number of read requests accepted
84system.physmem.writeReqs 145071 # Number of write requests accepted
85system.physmem.readBursts 197407 # Number of DRAM read bursts, including those serviced by the write queue
86system.physmem.writeBursts 145071 # Number of DRAM write bursts, including those merged in the write queue
87system.physmem.bytesReadDRAM 12624448 # Total number of bytes read from DRAM
88system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue
89system.physmem.bytesWritten 9033728 # Total number of bytes written to DRAM
90system.physmem.bytesReadSys 12451292 # Total read bytes from the system interface side
91system.physmem.bytesWrittenSys 9021084 # Total written bytes from the system interface side
92system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue
93system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
94system.physmem.neitherReadNorWriteReqs 50333 # Number of requests that are neither read nor write
95system.physmem.perBankRdBursts::0 12702 # Per bank write bursts
96system.physmem.perBankRdBursts::1 12398 # Per bank write bursts
97system.physmem.perBankRdBursts::2 12869 # Per bank write bursts
98system.physmem.perBankRdBursts::3 12803 # Per bank write bursts
99system.physmem.perBankRdBursts::4 14881 # Per bank write bursts
100system.physmem.perBankRdBursts::5 12147 # Per bank write bursts
101system.physmem.perBankRdBursts::6 12755 # Per bank write bursts
102system.physmem.perBankRdBursts::7 12276 # Per bank write bursts
103system.physmem.perBankRdBursts::8 11968 # Per bank write bursts
104system.physmem.perBankRdBursts::9 12044 # Per bank write bursts
105system.physmem.perBankRdBursts::10 11861 # Per bank write bursts
106system.physmem.perBankRdBursts::11 11195 # Per bank write bursts
107system.physmem.perBankRdBursts::12 11579 # Per bank write bursts
108system.physmem.perBankRdBursts::13 12354 # Per bank write bursts
109system.physmem.perBankRdBursts::14 11791 # Per bank write bursts
110system.physmem.perBankRdBursts::15 11634 # Per bank write bursts
111system.physmem.perBankWrBursts::0 9169 # Per bank write bursts
112system.physmem.perBankWrBursts::1 9145 # Per bank write bursts
113system.physmem.perBankWrBursts::2 9512 # Per bank write bursts
114system.physmem.perBankWrBursts::3 9193 # Per bank write bursts
115system.physmem.perBankWrBursts::4 8772 # Per bank write bursts
116system.physmem.perBankWrBursts::5 8759 # Per bank write bursts
117system.physmem.perBankWrBursts::6 9221 # Per bank write bursts
118system.physmem.perBankWrBursts::7 8821 # Per bank write bursts
119system.physmem.perBankWrBursts::8 8638 # Per bank write bursts
120system.physmem.perBankWrBursts::9 8679 # Per bank write bursts
121system.physmem.perBankWrBursts::10 8601 # Per bank write bursts
122system.physmem.perBankWrBursts::11 8338 # Per bank write bursts
123system.physmem.perBankWrBursts::12 8547 # Per bank write bursts
124system.physmem.perBankWrBursts::13 8875 # Per bank write bursts
125system.physmem.perBankWrBursts::14 8631 # Per bank write bursts
126system.physmem.perBankWrBursts::15 8251 # Per bank write bursts
127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128system.physmem.numWrRetry 15 # Number of times write queue was full causing retry
129system.physmem.totGap 2625394672500 # Total gap between requests
130system.physmem.readPktSize::0 0 # Read request sizes (log2)
131system.physmem.readPktSize::1 0 # Read request sizes (log2)
132system.physmem.readPktSize::2 551 # Read request sizes (log2)
133system.physmem.readPktSize::3 28 # Read request sizes (log2)
134system.physmem.readPktSize::4 3086 # Read request sizes (log2)
135system.physmem.readPktSize::5 0 # Read request sizes (log2)
136system.physmem.readPktSize::6 193742 # Read request sizes (log2)
137system.physmem.writePktSize::0 0 # Write request sizes (log2)
138system.physmem.writePktSize::1 0 # Write request sizes (log2)
139system.physmem.writePktSize::2 4391 # Write request sizes (log2)
140system.physmem.writePktSize::3 0 # Write request sizes (log2)
141system.physmem.writePktSize::4 0 # Write request sizes (log2)
142system.physmem.writePktSize::5 0 # Write request sizes (log2)
143system.physmem.writePktSize::6 140680 # Write request sizes (log2)
144system.physmem.rdQLenPdf::0 60453 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 70781 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 16881 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 12152 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 8838 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 7520 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 6581 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::7 5428 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::8 4952 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::9 1308 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::10 972 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::11 775 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::12 324 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::13 266 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
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183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::15 2665 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::16 3161 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::17 4593 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::18 5057 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::19 5456 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::20 6102 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::21 6711 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::22 8346 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::23 8856 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::24 10182 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::25 9756 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::26 9787 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::27 9219 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::28 9902 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::29 11207 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::30 9191 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::31 8461 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::32 7930 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::33 662 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::34 456 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::35 371 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::36 274 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::37 202 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::38 180 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::40 189 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::44 151 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::45 155 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::46 169 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::48 118 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::49 127 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::51 77 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::53 68 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::54 67 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::57 86 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::58 38 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see
240system.physmem.bytesPerActivate::samples 90794 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::mean 238.541225 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::gmean 134.856216 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::stdev 301.373578 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::0-127 48956 53.92% 53.92% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::128-255 17750 19.55% 73.47% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::256-383 6013 6.62% 80.09% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::384-511 3452 3.80% 83.89% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::512-639 2808 3.09% 86.99% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::640-767 1564 1.72% 88.71% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::768-895 893 0.98% 89.69% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::896-1023 995 1.10% 90.79% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::1024-1151 8363 9.21% 100.00% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::total 90794 # Bytes accessed per row activation
254system.physmem.rdPerTurnAround::samples 7077 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::mean 27.872686 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::stdev 551.008017 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::0-2047 7075 99.97% 99.97% # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::total 7077 # Reads before turning the bus around for writes
261system.physmem.wrPerTurnAround::samples 7077 # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::mean 19.945175 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::gmean 18.553311 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::stdev 11.579174 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::16-19 5904 83.43% 83.43% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::20-23 368 5.20% 88.63% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::24-27 217 3.07% 91.69% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::28-31 59 0.83% 92.53% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::32-35 82 1.16% 93.68% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::36-39 159 2.25% 95.93% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::40-43 25 0.35% 96.28% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::44-47 12 0.17% 96.45% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::48-51 13 0.18% 96.64% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::52-55 11 0.16% 96.79% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::56-59 10 0.14% 96.93% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::60-63 6 0.08% 97.02% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::64-67 165 2.33% 99.35% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::68-71 6 0.08% 99.43% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::72-75 3 0.04% 99.48% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::76-79 6 0.08% 99.56% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::80-83 1 0.01% 99.58% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::88-91 3 0.04% 99.62% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::92-95 3 0.04% 99.66% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::96-99 2 0.03% 99.69% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::100-103 1 0.01% 99.70% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::104-107 1 0.01% 99.72% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::124-127 1 0.01% 99.73% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::128-131 10 0.14% 99.87% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::144-147 1 0.01% 99.89% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::148-151 1 0.01% 99.90% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::152-155 1 0.01% 99.92% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::164-167 5 0.07% 99.99% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::176-179 1 0.01% 100.00% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::total 7077 # Writes before turning the bus around for reads
295system.physmem.totQLat 6986626052 # Total ticks spent queuing
296system.physmem.totMemAccLat 10685194802 # Total ticks spent from burst creation until serviced by the DRAM
297system.physmem.totBusLat 986285000 # Total ticks spent in databus transfers
298system.physmem.avgQLat 35418.90 # Average queueing delay per DRAM burst
299system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
300system.physmem.avgMemAccLat 54168.90 # Average memory access latency per DRAM burst
301system.physmem.avgRdBW 4.81 # Average DRAM read bandwidth in MiByte/s
302system.physmem.avgWrBW 3.44 # Average achieved write bandwidth in MiByte/s
303system.physmem.avgRdBWSys 4.74 # Average system read bandwidth in MiByte/s
304system.physmem.avgWrBWSys 3.44 # Average system write bandwidth in MiByte/s
305system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
306system.physmem.busUtil 0.06 # Data bus utilization in percentage
307system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
308system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
309system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing
310system.physmem.avgWrQLen 26.34 # Average write queue length when enqueuing
311system.physmem.readRowHits 164764 # Number of row buffer hits during reads
312system.physmem.writeRowHits 82850 # Number of row buffer hits during writes
313system.physmem.readRowHitRate 83.53 # Row buffer hit rate for reads
314system.physmem.writeRowHitRate 58.69 # Row buffer hit rate for writes
315system.physmem.avgGap 7665878.31 # Average gap between requests
316system.physmem.pageHitRate 73.17 # Row buffer hit rate, read and write combined
317system.physmem_0.actEnergy 357081480 # Energy for activate commands per rank (pJ)
318system.physmem_0.preEnergy 194836125 # Energy for precharge commands per rank (pJ)
319system.physmem_0.readEnergy 802081800 # Energy for read commands per rank (pJ)
320system.physmem_0.writeEnergy 470396160 # Energy for write commands per rank (pJ)
321system.physmem_0.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ)
322system.physmem_0.actBackEnergy 75099546585 # Energy for active background per rank (pJ)
323system.physmem_0.preBackEnergy 1509358032750 # Energy for precharge background per rank (pJ)
324system.physmem_0.totalEnergy 1757759761380 # Total energy per rank (pJ)
325system.physmem_0.averagePower 669.522942 # Core power per rank (mW)
326system.physmem_0.memoryStateTime::IDLE 2510844795677 # Time in different power states
327system.physmem_0.memoryStateTime::REF 87667580000 # Time in different power states
328system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
329system.physmem_0.memoryStateTime::ACT 26879018073 # Time in different power states
330system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
331system.physmem_1.actEnergy 329321160 # Energy for activate commands per rank (pJ)
332system.physmem_1.preEnergy 179689125 # Energy for precharge commands per rank (pJ)
333system.physmem_1.readEnergy 736515000 # Energy for read commands per rank (pJ)
334system.physmem_1.writeEnergy 444268800 # Energy for write commands per rank (pJ)
335system.physmem_1.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ)
336system.physmem_1.actBackEnergy 74435410800 # Energy for active background per rank (pJ)
337system.physmem_1.preBackEnergy 1509940608000 # Energy for precharge background per rank (pJ)
338system.physmem_1.totalEnergy 1757543599365 # Total energy per rank (pJ)
339system.physmem_1.averagePower 669.440607 # Core power per rank (mW)
340system.physmem_1.memoryStateTime::IDLE 2511823665901 # Time in different power states
341system.physmem_1.memoryStateTime::REF 87667580000 # Time in different power states
342system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
343system.physmem_1.memoryStateTime::ACT 25903669599 # Time in different power states
344system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
345system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory
346system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory
347system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory
348system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory
349system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory
350system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory
351system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
352system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
353system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory
354system.realview.nvmem.bw_read::cpu0.inst 49 # Total read bandwidth from this memory (bytes/s)
355system.realview.nvmem.bw_read::cpu1.inst 73 # Total read bandwidth from this memory (bytes/s)
356system.realview.nvmem.bw_read::total 122 # Total read bandwidth from this memory (bytes/s)
357system.realview.nvmem.bw_inst_read::cpu0.inst 49 # Instruction read bandwidth from this memory (bytes/s)
358system.realview.nvmem.bw_inst_read::cpu1.inst 73 # Instruction read bandwidth from this memory (bytes/s)
359system.realview.nvmem.bw_inst_read::total 122 # Instruction read bandwidth from this memory (bytes/s)
360system.realview.nvmem.bw_total::cpu0.inst 49 # Total bandwidth to/from this memory (bytes/s)
361system.realview.nvmem.bw_total::cpu1.inst 73 # Total bandwidth to/from this memory (bytes/s)
362system.realview.nvmem.bw_total::total 122 # Total bandwidth to/from this memory (bytes/s)
363system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
364system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
365system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
366system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
367system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
368system.cf0.dma_write_txs 631 # Number of DMA write transactions.
369system.cpu0.branchPred.lookups 51763361 # Number of BP lookups
370system.cpu0.branchPred.condPredicted 23412597 # Number of conditional branches predicted
371system.cpu0.branchPred.condIncorrect 921572 # Number of conditional branches incorrect
372system.cpu0.branchPred.BTBLookups 31250401 # Number of BTB lookups
373system.cpu0.branchPred.BTBHits 23297364 # Number of BTB hits
374system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
375system.cpu0.branchPred.BTBHitPct 74.550608 # BTB Hit Percentage
376system.cpu0.branchPred.usedRAS 15315613 # Number of times the RAS was used to get a target.
377system.cpu0.branchPred.RASInCorrect 29376 # Number of incorrect RAS predictions.
378system.cpu_clk_domain.clock 500 # Clock period in ticks
379system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
380system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
381system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
382system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
383system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
384system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

400system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
401system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
402system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
403system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
404system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
405system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
406system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
407system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
408system.cpu0.dtb.walker.walks 63347 # Table walker walks requested
409system.cpu0.dtb.walker.walksShort 63347 # Table walker walks initiated with short descriptors
410system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 24259 # Level at which table walker walks with short descriptors terminate
411system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18763 # Level at which table walker walks with short descriptors terminate
412system.cpu0.dtb.walker.walksSquashedBefore 20325 # Table walks squashed before starting
413system.cpu0.dtb.walker.walkWaitTime::samples 43022 # Table walker wait (enqueue to first request) latency
414system.cpu0.dtb.walker.walkWaitTime::mean 472.792990 # Table walker wait (enqueue to first request) latency
415system.cpu0.dtb.walker.walkWaitTime::stdev 2838.942862 # Table walker wait (enqueue to first request) latency
416system.cpu0.dtb.walker.walkWaitTime::0-8191 41882 97.35% 97.35% # Table walker wait (enqueue to first request) latency
417system.cpu0.dtb.walker.walkWaitTime::8192-16383 877 2.04% 99.39% # Table walker wait (enqueue to first request) latency
418system.cpu0.dtb.walker.walkWaitTime::16384-24575 115 0.27% 99.66% # Table walker wait (enqueue to first request) latency
419system.cpu0.dtb.walker.walkWaitTime::24576-32767 113 0.26% 99.92% # Table walker wait (enqueue to first request) latency
420system.cpu0.dtb.walker.walkWaitTime::32768-40959 6 0.01% 99.93% # Table walker wait (enqueue to first request) latency
421system.cpu0.dtb.walker.walkWaitTime::40960-49151 23 0.05% 99.99% # Table walker wait (enqueue to first request) latency
422system.cpu0.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
423system.cpu0.dtb.walker.walkWaitTime::57344-65535 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
424system.cpu0.dtb.walker.walkWaitTime::65536-73727 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
425system.cpu0.dtb.walker.walkWaitTime::total 43022 # Table walker wait (enqueue to first request) latency
426system.cpu0.dtb.walker.walkCompletionTime::samples 16160 # Table walker service (enqueue to completion) latency
427system.cpu0.dtb.walker.walkCompletionTime::mean 9833.168317 # Table walker service (enqueue to completion) latency
428system.cpu0.dtb.walker.walkCompletionTime::gmean 8304.443400 # Table walker service (enqueue to completion) latency
429system.cpu0.dtb.walker.walkCompletionTime::stdev 6846.428458 # Table walker service (enqueue to completion) latency
430system.cpu0.dtb.walker.walkCompletionTime::0-16383 15169 93.87% 93.87% # Table walker service (enqueue to completion) latency
431system.cpu0.dtb.walker.walkCompletionTime::16384-32767 911 5.64% 99.50% # Table walker service (enqueue to completion) latency
432system.cpu0.dtb.walker.walkCompletionTime::32768-49151 54 0.33% 99.84% # Table walker service (enqueue to completion) latency
433system.cpu0.dtb.walker.walkCompletionTime::49152-65535 3 0.02% 99.86% # Table walker service (enqueue to completion) latency
434system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.01% 99.87% # Table walker service (enqueue to completion) latency
435system.cpu0.dtb.walker.walkCompletionTime::98304-114687 20 0.12% 99.99% # Table walker service (enqueue to completion) latency
436system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
437system.cpu0.dtb.walker.walkCompletionTime::total 16160 # Table walker service (enqueue to completion) latency
438system.cpu0.dtb.walker.walksPending::samples 95658285656 # Table walker pending requests distribution
439system.cpu0.dtb.walker.walksPending::mean 0.461466 # Table walker pending requests distribution
440system.cpu0.dtb.walker.walksPending::stdev 0.505385 # Table walker pending requests distribution
441system.cpu0.dtb.walker.walksPending::0-1 95607533656 99.95% 99.95% # Table walker pending requests distribution
442system.cpu0.dtb.walker.walksPending::2-3 37952000 0.04% 99.99% # Table walker pending requests distribution
443system.cpu0.dtb.walker.walksPending::4-5 6012000 0.01% 99.99% # Table walker pending requests distribution
444system.cpu0.dtb.walker.walksPending::6-7 3722000 0.00% 100.00% # Table walker pending requests distribution
445system.cpu0.dtb.walker.walksPending::8-9 1321500 0.00% 100.00% # Table walker pending requests distribution
446system.cpu0.dtb.walker.walksPending::10-11 760000 0.00% 100.00% # Table walker pending requests distribution
447system.cpu0.dtb.walker.walksPending::12-13 604000 0.00% 100.00% # Table walker pending requests distribution
448system.cpu0.dtb.walker.walksPending::14-15 360500 0.00% 100.00% # Table walker pending requests distribution
449system.cpu0.dtb.walker.walksPending::16-17 20000 0.00% 100.00% # Table walker pending requests distribution
450system.cpu0.dtb.walker.walksPending::total 95658285656 # Table walker pending requests distribution
451system.cpu0.dtb.walker.walkPageSizes::4K 5176 77.00% 77.00% # Table walker page sizes translated
452system.cpu0.dtb.walker.walkPageSizes::1M 1546 23.00% 100.00% # Table walker page sizes translated
453system.cpu0.dtb.walker.walkPageSizes::total 6722 # Table walker page sizes translated
454system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 63347 # Table walker requests started/completed, data/inst
455system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
456system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 63347 # Table walker requests started/completed, data/inst
457system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6722 # Table walker requests started/completed, data/inst
458system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
459system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6722 # Table walker requests started/completed, data/inst
460system.cpu0.dtb.walker.walkRequestOrigin::total 70069 # Table walker requests started/completed, data/inst
461system.cpu0.dtb.inst_hits 0 # ITB inst hits
462system.cpu0.dtb.inst_misses 0 # ITB inst misses
463system.cpu0.dtb.read_hits 22737235 # DTB read hits
464system.cpu0.dtb.read_misses 54172 # DTB read misses
465system.cpu0.dtb.write_hits 16921500 # DTB write hits
466system.cpu0.dtb.write_misses 9175 # DTB write misses
467system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
468system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
469system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
470system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
471system.cpu0.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB
472system.cpu0.dtb.align_faults 141 # Number of TLB faults due to alignment restrictions
473system.cpu0.dtb.prefetch_faults 1882 # Number of TLB faults due to prefetch
474system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
475system.cpu0.dtb.perms_faults 854 # Number of TLB faults due to permissions restrictions
476system.cpu0.dtb.read_accesses 22791407 # DTB read accesses
477system.cpu0.dtb.write_accesses 16930675 # DTB write accesses
478system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
479system.cpu0.dtb.hits 39658735 # DTB hits
480system.cpu0.dtb.misses 63347 # DTB misses
481system.cpu0.dtb.accesses 39722082 # DTB accesses
482system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
489system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

503system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
504system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
505system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
506system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
507system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
508system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
509system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
510system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
511system.cpu0.itb.walker.walks 10275 # Table walker walks requested
512system.cpu0.itb.walker.walksShort 10275 # Table walker walks initiated with short descriptors
513system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4076 # Level at which table walker walks with short descriptors terminate
514system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6085 # Level at which table walker walks with short descriptors terminate
515system.cpu0.itb.walker.walksSquashedBefore 114 # Table walks squashed before starting
516system.cpu0.itb.walker.walkWaitTime::samples 10161 # Table walker wait (enqueue to first request) latency
517system.cpu0.itb.walker.walkWaitTime::mean 480.267690 # Table walker wait (enqueue to first request) latency
518system.cpu0.itb.walker.walkWaitTime::stdev 2390.213266 # Table walker wait (enqueue to first request) latency
519system.cpu0.itb.walker.walkWaitTime::0-4095 9738 95.84% 95.84% # Table walker wait (enqueue to first request) latency
520system.cpu0.itb.walker.walkWaitTime::4096-8191 133 1.31% 97.15% # Table walker wait (enqueue to first request) latency
521system.cpu0.itb.walker.walkWaitTime::8192-12287 215 2.12% 99.26% # Table walker wait (enqueue to first request) latency
522system.cpu0.itb.walker.walkWaitTime::12288-16383 37 0.36% 99.63% # Table walker wait (enqueue to first request) latency
523system.cpu0.itb.walker.walkWaitTime::16384-20479 9 0.09% 99.71% # Table walker wait (enqueue to first request) latency
524system.cpu0.itb.walker.walkWaitTime::20480-24575 15 0.15% 99.86% # Table walker wait (enqueue to first request) latency
525system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.89% # Table walker wait (enqueue to first request) latency
526system.cpu0.itb.walker.walkWaitTime::28672-32767 3 0.03% 99.92% # Table walker wait (enqueue to first request) latency
527system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.94% # Table walker wait (enqueue to first request) latency
528system.cpu0.itb.walker.walkWaitTime::36864-40959 4 0.04% 99.98% # Table walker wait (enqueue to first request) latency
529system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
530system.cpu0.itb.walker.walkWaitTime::45056-49151 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
531system.cpu0.itb.walker.walkWaitTime::total 10161 # Table walker wait (enqueue to first request) latency
532system.cpu0.itb.walker.walkCompletionTime::samples 2702 # Table walker service (enqueue to completion) latency
533system.cpu0.itb.walker.walkCompletionTime::mean 11438.934123 # Table walker service (enqueue to completion) latency
534system.cpu0.itb.walker.walkCompletionTime::gmean 10140.740913 # Table walker service (enqueue to completion) latency
535system.cpu0.itb.walker.walkCompletionTime::stdev 6204.580963 # Table walker service (enqueue to completion) latency
536system.cpu0.itb.walker.walkCompletionTime::0-8191 871 32.24% 32.24% # Table walker service (enqueue to completion) latency
537system.cpu0.itb.walker.walkCompletionTime::8192-16383 1681 62.21% 94.45% # Table walker service (enqueue to completion) latency
538system.cpu0.itb.walker.walkCompletionTime::16384-24575 53 1.96% 96.41% # Table walker service (enqueue to completion) latency
539system.cpu0.itb.walker.walkCompletionTime::24576-32767 85 3.15% 99.56% # Table walker service (enqueue to completion) latency
540system.cpu0.itb.walker.walkCompletionTime::32768-40959 7 0.26% 99.81% # Table walker service (enqueue to completion) latency
541system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.85% # Table walker service (enqueue to completion) latency
542system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.89% # Table walker service (enqueue to completion) latency
543system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.93% # Table walker service (enqueue to completion) latency
544system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
545system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
546system.cpu0.itb.walker.walkCompletionTime::total 2702 # Table walker service (enqueue to completion) latency
547system.cpu0.itb.walker.walksPending::samples 22643799124 # Table walker pending requests distribution
548system.cpu0.itb.walker.walksPending::mean 0.979659 # Table walker pending requests distribution
549system.cpu0.itb.walker.walksPending::stdev 0.141451 # Table walker pending requests distribution
550system.cpu0.itb.walker.walksPending::0 461404000 2.04% 2.04% # Table walker pending requests distribution
551system.cpu0.itb.walker.walksPending::1 22181693124 97.96% 100.00% # Table walker pending requests distribution
552system.cpu0.itb.walker.walksPending::2 593000 0.00% 100.00% # Table walker pending requests distribution
553system.cpu0.itb.walker.walksPending::3 109000 0.00% 100.00% # Table walker pending requests distribution
554system.cpu0.itb.walker.walksPending::total 22643799124 # Table walker pending requests distribution
555system.cpu0.itb.walker.walkPageSizes::4K 2268 87.64% 87.64% # Table walker page sizes translated
556system.cpu0.itb.walker.walkPageSizes::1M 320 12.36% 100.00% # Table walker page sizes translated
557system.cpu0.itb.walker.walkPageSizes::total 2588 # Table walker page sizes translated
558system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
559system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10275 # Table walker requests started/completed, data/inst
560system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10275 # Table walker requests started/completed, data/inst
561system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
562system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2588 # Table walker requests started/completed, data/inst
563system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst
564system.cpu0.itb.walker.walkRequestOrigin::total 12863 # Table walker requests started/completed, data/inst
565system.cpu0.itb.inst_hits 70928349 # ITB inst hits
566system.cpu0.itb.inst_misses 10275 # ITB inst misses
567system.cpu0.itb.read_hits 0 # DTB read hits
568system.cpu0.itb.read_misses 0 # DTB read misses
569system.cpu0.itb.write_hits 0 # DTB write hits
570system.cpu0.itb.write_misses 0 # DTB write misses
571system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
572system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
573system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
574system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
575system.cpu0.itb.flush_entries 2365 # Number of entries that have been flushed from TLB
576system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
577system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
578system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
579system.cpu0.itb.perms_faults 1936 # Number of TLB faults due to permissions restrictions
580system.cpu0.itb.read_accesses 0 # DTB read accesses
581system.cpu0.itb.write_accesses 0 # DTB write accesses
582system.cpu0.itb.inst_accesses 70938624 # ITB inst accesses
583system.cpu0.itb.hits 70928349 # DTB hits
584system.cpu0.itb.misses 10275 # DTB misses
585system.cpu0.itb.accesses 70938624 # DTB accesses
586system.cpu0.numCycles 192976868 # number of cpu cycles simulated
587system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
588system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
589system.cpu0.fetch.icacheStallCycles 19363908 # Number of cycles fetch is stalled on an Icache miss
590system.cpu0.fetch.Insts 190332929 # Number of instructions fetch has processed
591system.cpu0.fetch.Branches 51763361 # Number of branches that fetch encountered
592system.cpu0.fetch.predictedBranches 38612977 # Number of branches that fetch has predicted taken
593system.cpu0.fetch.Cycles 166709106 # Number of cycles fetch has run and was not squashing or blocked
594system.cpu0.fetch.SquashCycles 5608958 # Number of cycles fetch has spent squashing
595system.cpu0.fetch.TlbCycles 145099 # Number of cycles fetch has spent waiting for tlb
596system.cpu0.fetch.MiscStallCycles 54692 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
597system.cpu0.fetch.PendingTrapStallCycles 348676 # Number of stall cycles due to pending traps
598system.cpu0.fetch.PendingQuiesceStallCycles 420281 # Number of stall cycles due to pending quiesce instructions
599system.cpu0.fetch.IcacheWaitRetryStallCycles 85262 # Number of stall cycles due to full MSHR
600system.cpu0.fetch.CacheLines 70928958 # Number of cache lines fetched
601system.cpu0.fetch.IcacheSquashes 257958 # Number of outstanding Icache misses that were squashed
602system.cpu0.fetch.ItlbSquashes 4691 # Number of outstanding ITLB misses that were squashed
603system.cpu0.fetch.rateDist::samples 189931503 # Number of instructions fetched each cycle (Total)
604system.cpu0.fetch.rateDist::mean 1.225932 # Number of instructions fetched each cycle (Total)
605system.cpu0.fetch.rateDist::stdev 1.310916 # Number of instructions fetched each cycle (Total)
606system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
607system.cpu0.fetch.rateDist::0 88125904 46.40% 46.40% # Number of instructions fetched each cycle (Total)
608system.cpu0.fetch.rateDist::1 29232702 15.39% 61.79% # Number of instructions fetched each cycle (Total)
609system.cpu0.fetch.rateDist::2 14108338 7.43% 69.22% # Number of instructions fetched each cycle (Total)
610system.cpu0.fetch.rateDist::3 58464559 30.78% 100.00% # Number of instructions fetched each cycle (Total)
611system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
612system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
613system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
614system.cpu0.fetch.rateDist::total 189931503 # Number of instructions fetched each cycle (Total)
615system.cpu0.fetch.branchRate 0.268236 # Number of branch fetches per cycle
616system.cpu0.fetch.rate 0.986299 # Number of inst fetches per cycle
617system.cpu0.decode.IdleCycles 24608865 # Number of cycles decode is idle
618system.cpu0.decode.BlockedCycles 101406874 # Number of cycles decode is blocked
619system.cpu0.decode.RunCycles 56677604 # Number of cycles decode is running
620system.cpu0.decode.UnblockCycles 4757932 # Number of cycles decode is unblocking
621system.cpu0.decode.SquashCycles 2480228 # Number of cycles decode is squashing
622system.cpu0.decode.BranchResolved 2944179 # Number of times decode resolved a branch
623system.cpu0.decode.BranchMispred 328448 # Number of times decode detected a branch misprediction
624system.cpu0.decode.DecodedInsts 148845488 # Number of instructions handled by decode
625system.cpu0.decode.SquashedInsts 3759445 # Number of squashed instructions handled by decode
626system.cpu0.rename.SquashCycles 2480228 # Number of cycles rename is squashing
627system.cpu0.rename.IdleCycles 33020653 # Number of cycles rename is idle
628system.cpu0.rename.BlockCycles 11928133 # Number of cycles rename is blocking
629system.cpu0.rename.serializeStallCycles 79389996 # count of cycles rename stalled for serializing inst
630system.cpu0.rename.RunCycles 52895431 # Number of cycles rename is running
631system.cpu0.rename.UnblockCycles 10217062 # Number of cycles rename is unblocking
632system.cpu0.rename.RenamedInsts 132354164 # Number of instructions processed by rename
633system.cpu0.rename.SquashedInsts 1007004 # Number of squashed instructions processed by rename
634system.cpu0.rename.ROBFullEvents 1382043 # Number of times rename has blocked due to ROB full
635system.cpu0.rename.IQFullEvents 149840 # Number of times rename has blocked due to IQ full
636system.cpu0.rename.LQFullEvents 52195 # Number of times rename has blocked due to LQ full
637system.cpu0.rename.SQFullEvents 6188026 # Number of times rename has blocked due to SQ full
638system.cpu0.rename.RenamedOperands 135879963 # Number of destination operands rename has renamed
639system.cpu0.rename.RenameLookups 611395498 # Number of register rename lookups that rename has made
640system.cpu0.rename.int_rename_lookups 146969281 # Number of integer rename lookups
641system.cpu0.rename.fp_rename_lookups 9373 # Number of floating rename lookups
642system.cpu0.rename.CommittedMaps 124973310 # Number of HB maps that are committed
643system.cpu0.rename.UndoneMaps 10906650 # Number of HB maps that are undone due to squashing
644system.cpu0.rename.serializingInsts 2656416 # count of serializing insts renamed
645system.cpu0.rename.tempSerializingInsts 2518561 # count of temporary serializing insts renamed
646system.cpu0.rename.skidInsts 22027855 # count of insts added to the skid buffer
647system.cpu0.memDep0.insertedLoads 23660512 # Number of loads inserted to the mem dependence unit.
648system.cpu0.memDep0.insertedStores 18424443 # Number of stores inserted to the mem dependence unit.
649system.cpu0.memDep0.conflictingLoads 1639164 # Number of conflicting loads.
650system.cpu0.memDep0.conflictingStores 2432445 # Number of conflicting stores.
651system.cpu0.iq.iqInstsAdded 129487187 # Number of instructions added to the IQ (excludes non-spec)
652system.cpu0.iq.iqNonSpecInstsAdded 1661777 # Number of non-speculative instructions added to the IQ
653system.cpu0.iq.iqInstsIssued 127665829 # Number of instructions issued
654system.cpu0.iq.iqSquashedInstsIssued 454854 # Number of squashed instructions issued
655system.cpu0.iq.iqSquashedInstsExamined 10484678 # Number of squashed instructions iterated over during squash; mainly for profiling
656system.cpu0.iq.iqSquashedOperandsExamined 21309646 # Number of squashed operands that are examined and possibly removed from graph
657system.cpu0.iq.iqSquashedNonSpecRemoved 116701 # Number of squashed non-spec instructions that were removed
658system.cpu0.iq.issued_per_cycle::samples 189931503 # Number of insts issued each cycle
659system.cpu0.iq.issued_per_cycle::mean 0.672168 # Number of insts issued each cycle
660system.cpu0.iq.issued_per_cycle::stdev 0.963951 # Number of insts issued each cycle
661system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
662system.cpu0.iq.issued_per_cycle::0 116041258 61.10% 61.10% # Number of insts issued each cycle
663system.cpu0.iq.issued_per_cycle::1 32572628 17.15% 78.25% # Number of insts issued each cycle
664system.cpu0.iq.issued_per_cycle::2 29941917 15.76% 94.01% # Number of insts issued each cycle
665system.cpu0.iq.issued_per_cycle::3 10293469 5.42% 99.43% # Number of insts issued each cycle
666system.cpu0.iq.issued_per_cycle::4 1082195 0.57% 100.00% # Number of insts issued each cycle
667system.cpu0.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle
668system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
669system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
670system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
671system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
672system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
673system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
674system.cpu0.iq.issued_per_cycle::total 189931503 # Number of insts issued each cycle
675system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
676system.cpu0.iq.fu_full::IntAlu 10298963 43.90% 43.90% # attempts to use FU when none available
677system.cpu0.iq.fu_full::IntMult 129 0.00% 43.91% # attempts to use FU when none available
678system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.91% # attempts to use FU when none available
679system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.91% # attempts to use FU when none available
680system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.91% # attempts to use FU when none available
681system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.91% # attempts to use FU when none available
682system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.91% # attempts to use FU when none available
683system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.91% # attempts to use FU when none available
684system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.91% # attempts to use FU when none available
685system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.91% # attempts to use FU when none available
686system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.91% # attempts to use FU when none available
687system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.91% # attempts to use FU when none available
688system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.91% # attempts to use FU when none available
689system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.91% # attempts to use FU when none available
690system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.91% # attempts to use FU when none available
691system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.91% # attempts to use FU when none available
692system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.91% # attempts to use FU when none available
693system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.91% # attempts to use FU when none available
694system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.91% # attempts to use FU when none available
695system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.91% # attempts to use FU when none available
696system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.91% # attempts to use FU when none available
697system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.91% # attempts to use FU when none available
698system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.91% # attempts to use FU when none available
699system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.91% # attempts to use FU when none available
700system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.91% # attempts to use FU when none available
701system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.91% # attempts to use FU when none available
702system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.91% # attempts to use FU when none available
703system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.91% # attempts to use FU when none available
704system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.91% # attempts to use FU when none available
705system.cpu0.iq.fu_full::MemRead 5415712 23.09% 66.99% # attempts to use FU when none available
706system.cpu0.iq.fu_full::MemWrite 7742693 33.01% 100.00% # attempts to use FU when none available
707system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
708system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
709system.cpu0.iq.FU_type_0::No_OpClass 2272 0.00% 0.00% # Type of FU issued
710system.cpu0.iq.FU_type_0::IntAlu 86175456 67.50% 67.50% # Type of FU issued
711system.cpu0.iq.FU_type_0::IntMult 106512 0.08% 67.59% # Type of FU issued
712system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.59% # Type of FU issued
713system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.59% # Type of FU issued
714system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.59% # Type of FU issued
715system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.59% # Type of FU issued
716system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.59% # Type of FU issued
717system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.59% # Type of FU issued
718system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.59% # Type of FU issued
719system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.59% # Type of FU issued
720system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.59% # Type of FU issued
721system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.59% # Type of FU issued
722system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.59% # Type of FU issued
723system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.59% # Type of FU issued
724system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.59% # Type of FU issued
725system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.59% # Type of FU issued
726system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.59% # Type of FU issued
727system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.59% # Type of FU issued
728system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.59% # Type of FU issued
729system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.59% # Type of FU issued
730system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.59% # Type of FU issued
731system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.59% # Type of FU issued
732system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.59% # Type of FU issued
733system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.59% # Type of FU issued
734system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.59% # Type of FU issued
735system.cpu0.iq.FU_type_0::SimdFloatMisc 7179 0.01% 67.59% # Type of FU issued
736system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.59% # Type of FU issued
737system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.59% # Type of FU issued
738system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.59% # Type of FU issued
739system.cpu0.iq.FU_type_0::MemRead 23410232 18.34% 85.93% # Type of FU issued
740system.cpu0.iq.FU_type_0::MemWrite 17964178 14.07% 100.00% # Type of FU issued
741system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
742system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
743system.cpu0.iq.FU_type_0::total 127665829 # Type of FU issued
744system.cpu0.iq.rate 0.661560 # Inst issue rate
745system.cpu0.iq.fu_busy_cnt 23457497 # FU busy when requested
746system.cpu0.iq.fu_busy_rate 0.183741 # FU busy rate (busy events/executed inst)
747system.cpu0.iq.int_inst_queue_reads 469142790 # Number of integer instruction queue reads
748system.cpu0.iq.int_inst_queue_writes 141641253 # Number of integer instruction queue writes
749system.cpu0.iq.int_inst_queue_wakeup_accesses 124187141 # Number of integer instruction queue wakeup accesses
750system.cpu0.iq.fp_inst_queue_reads 32722 # Number of floating instruction queue reads
751system.cpu0.iq.fp_inst_queue_writes 11272 # Number of floating instruction queue writes
752system.cpu0.iq.fp_inst_queue_wakeup_accesses 9724 # Number of floating instruction queue wakeup accesses
753system.cpu0.iq.int_alu_accesses 151099696 # Number of integer alu accesses
754system.cpu0.iq.fp_alu_accesses 21358 # Number of floating point alu accesses
755system.cpu0.iew.lsq.thread0.forwLoads 349091 # Number of loads that had data forwarded from stores
756system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
757system.cpu0.iew.lsq.thread0.squashedLoads 1883461 # Number of loads squashed
758system.cpu0.iew.lsq.thread0.ignoredResponses 2555 # Number of memory responses ignored because the instruction is squashed
759system.cpu0.iew.lsq.thread0.memOrderViolation 18950 # Number of memory ordering violations
760system.cpu0.iew.lsq.thread0.squashedStores 972383 # Number of stores squashed
761system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
762system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
763system.cpu0.iew.lsq.thread0.rescheduledLoads 113459 # Number of loads that were rescheduled
764system.cpu0.iew.lsq.thread0.cacheBlocked 340118 # Number of times an access to memory failed due to the cache being blocked
765system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
766system.cpu0.iew.iewSquashCycles 2480228 # Number of cycles IEW is squashing
767system.cpu0.iew.iewBlockCycles 1536268 # Number of cycles IEW is blocking
768system.cpu0.iew.iewUnblockCycles 176000 # Number of cycles IEW is unblocking
769system.cpu0.iew.iewDispatchedInsts 131320075 # Number of instructions dispatched to IQ
770system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
771system.cpu0.iew.iewDispLoadInsts 23660512 # Number of dispatched load instructions
772system.cpu0.iew.iewDispStoreInsts 18424443 # Number of dispatched store instructions
773system.cpu0.iew.iewDispNonSpecInsts 851631 # Number of dispatched non-speculative instructions
774system.cpu0.iew.iewIQFullEvents 24928 # Number of times the IQ has become full, causing a stall
775system.cpu0.iew.iewLSQFullEvents 129599 # Number of times the LSQ has become full, causing a stall
776system.cpu0.iew.memOrderViolationEvents 18950 # Number of memory order violations
777system.cpu0.iew.predictedTakenIncorrect 275039 # Number of branches that were predicted taken incorrectly
778system.cpu0.iew.predictedNotTakenIncorrect 375413 # Number of branches that were predicted not taken incorrectly
779system.cpu0.iew.branchMispredicts 650452 # Number of branch mispredicts detected at execute
780system.cpu0.iew.iewExecutedInsts 126634007 # Number of executed instructions
781system.cpu0.iew.iewExecLoadInsts 22982824 # Number of load instructions executed
782system.cpu0.iew.iewExecSquashedInsts 968597 # Number of squashed instructions skipped in execute
783system.cpu0.iew.exec_swp 0 # number of swp insts executed
784system.cpu0.iew.exec_nop 171111 # number of nop insts executed
785system.cpu0.iew.exec_refs 40767921 # number of memory reference insts executed
786system.cpu0.iew.exec_branches 24572908 # Number of branches executed
787system.cpu0.iew.exec_stores 17785097 # Number of stores executed
788system.cpu0.iew.exec_rate 0.656213 # Inst execution rate
789system.cpu0.iew.wb_sent 126104266 # cumulative count of insts sent to commit
790system.cpu0.iew.wb_count 124196865 # cumulative count of insts written-back
791system.cpu0.iew.wb_producers 63208416 # num instructions producing a value
792system.cpu0.iew.wb_consumers 102222094 # num instructions consuming a value
793system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
794system.cpu0.iew.wb_rate 0.643584 # insts written-back per cycle
795system.cpu0.iew.wb_fanout 0.618344 # average fanout of values written-back
796system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
797system.cpu0.commit.commitSquashedInsts 9488534 # The number of squashed insts skipped by commit
798system.cpu0.commit.commitNonSpecStalls 1545076 # The number of times commit has been forced to stall to communicate backwards
799system.cpu0.commit.branchMispredicts 597321 # The number of times a branch was mispredicted
800system.cpu0.commit.committed_per_cycle::samples 186809549 # Number of insts commited each cycle
801system.cpu0.commit.committed_per_cycle::mean 0.646573 # Number of insts commited each cycle
802system.cpu0.commit.committed_per_cycle::stdev 1.344397 # Number of insts commited each cycle
803system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
804system.cpu0.commit.committed_per_cycle::0 128903317 69.00% 69.00% # Number of insts commited each cycle
805system.cpu0.commit.committed_per_cycle::1 31993486 17.13% 86.13% # Number of insts commited each cycle
806system.cpu0.commit.committed_per_cycle::2 12242174 6.55% 92.68% # Number of insts commited each cycle
807system.cpu0.commit.committed_per_cycle::3 3077822 1.65% 94.33% # Number of insts commited each cycle
808system.cpu0.commit.committed_per_cycle::4 4650551 2.49% 96.82% # Number of insts commited each cycle
809system.cpu0.commit.committed_per_cycle::5 2601023 1.39% 98.21% # Number of insts commited each cycle
810system.cpu0.commit.committed_per_cycle::6 1367878 0.73% 98.94% # Number of insts commited each cycle
811system.cpu0.commit.committed_per_cycle::7 526295 0.28% 99.23% # Number of insts commited each cycle
812system.cpu0.commit.committed_per_cycle::8 1447003 0.77% 100.00% # Number of insts commited each cycle
813system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
814system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
815system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
816system.cpu0.commit.committed_per_cycle::total 186809549 # Number of insts commited each cycle
817system.cpu0.commit.committedInsts 99693903 # Number of instructions committed
818system.cpu0.commit.committedOps 120785976 # Number of ops (including micro ops) committed
819system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
820system.cpu0.commit.refs 39229111 # Number of memory references committed
821system.cpu0.commit.loads 21777051 # Number of loads committed
822system.cpu0.commit.membars 629182 # Number of memory barriers committed
823system.cpu0.commit.branches 23976855 # Number of branches committed
824system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions.
825system.cpu0.commit.int_insts 105625598 # Number of committed integer instructions.
826system.cpu0.commit.function_calls 4749745 # Number of function calls committed.
827system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
828system.cpu0.commit.op_class_0::IntAlu 81445291 67.43% 67.43% # Class of committed instruction
829system.cpu0.commit.op_class_0::IntMult 104395 0.09% 67.52% # Class of committed instruction
830system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.52% # Class of committed instruction
831system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.52% # Class of committed instruction
832system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.52% # Class of committed instruction
833system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.52% # Class of committed instruction
834system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.52% # Class of committed instruction
835system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.52% # Class of committed instruction
836system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.52% # Class of committed instruction
837system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.52% # Class of committed instruction
838system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.52% # Class of committed instruction
839system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.52% # Class of committed instruction
840system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.52% # Class of committed instruction
841system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.52% # Class of committed instruction
842system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.52% # Class of committed instruction
843system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.52% # Class of committed instruction
844system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.52% # Class of committed instruction
845system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.52% # Class of committed instruction
846system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.52% # Class of committed instruction
847system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.52% # Class of committed instruction
848system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.52% # Class of committed instruction
849system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.52% # Class of committed instruction
850system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.52% # Class of committed instruction
851system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.52% # Class of committed instruction
852system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.52% # Class of committed instruction
853system.cpu0.commit.op_class_0::SimdFloatMisc 7179 0.01% 67.52% # Class of committed instruction
854system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.52% # Class of committed instruction
855system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.52% # Class of committed instruction
856system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.52% # Class of committed instruction
857system.cpu0.commit.op_class_0::MemRead 21777051 18.03% 85.55% # Class of committed instruction
858system.cpu0.commit.op_class_0::MemWrite 17452060 14.45% 100.00% # Class of committed instruction
859system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
860system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
861system.cpu0.commit.op_class_0::total 120785976 # Class of committed instruction
862system.cpu0.commit.bw_lim_events 1447003 # number cycles where commit BW limit reached
863system.cpu0.rob.rob_reads 292572702 # The number of ROB reads
864system.cpu0.rob.rob_writes 263669539 # The number of ROB writes
865system.cpu0.timesIdled 123127 # Number of times that the entire CPU went into an idle state and unscheduled itself
866system.cpu0.idleCycles 3045365 # Total number of cycles that the CPU has spent unscheduled due to idling
867system.cpu0.quiesceCycles 5057813082 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
868system.cpu0.committedInsts 99572209 # Number of Instructions Simulated
869system.cpu0.committedOps 120664282 # Number of Ops (including micro ops) Simulated
870system.cpu0.cpi 1.938060 # CPI: Cycles Per Instruction
871system.cpu0.cpi_total 1.938060 # CPI: Total CPI of All Threads
872system.cpu0.ipc 0.515980 # IPC: Instructions Per Cycle
873system.cpu0.ipc_total 0.515980 # IPC: Total IPC of All Threads
874system.cpu0.int_regfile_reads 137228019 # number of integer regfile reads
875system.cpu0.int_regfile_writes 78727155 # number of integer regfile writes
876system.cpu0.fp_regfile_reads 8192 # number of floating regfile reads
877system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes
878system.cpu0.cc_regfile_reads 446969794 # number of cc regfile reads
879system.cpu0.cc_regfile_writes 47254034 # number of cc regfile writes
880system.cpu0.misc_regfile_reads 263157526 # number of misc regfile reads
881system.cpu0.misc_regfile_writes 1194331 # number of misc regfile writes
882system.cpu0.dcache.tags.replacements 673421 # number of replacements
883system.cpu0.dcache.tags.tagsinuse 483.801587 # Cycle average of tags in use
884system.cpu0.dcache.tags.total_refs 36230548 # Total number of references to valid blocks.
885system.cpu0.dcache.tags.sampled_refs 673933 # Sample count of references to valid blocks.
886system.cpu0.dcache.tags.avg_refs 53.759866 # Average number of references to valid blocks.
887system.cpu0.dcache.tags.warmup_cycle 274448500 # Cycle when the warmup percentage was hit.
888system.cpu0.dcache.tags.occ_blocks::cpu0.data 483.801587 # Average occupied blocks per requestor
889system.cpu0.dcache.tags.occ_percent::cpu0.data 0.944925 # Average percentage of cache occupancy
890system.cpu0.dcache.tags.occ_percent::total 0.944925 # Average percentage of cache occupancy
891system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
892system.cpu0.dcache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id
893system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id
894system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id
895system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
896system.cpu0.dcache.tags.tag_accesses 78023145 # Number of tag accesses
897system.cpu0.dcache.tags.data_accesses 78023145 # Number of data accesses
898system.cpu0.dcache.ReadReq_hits::cpu0.data 20647656 # number of ReadReq hits
899system.cpu0.dcache.ReadReq_hits::total 20647656 # number of ReadReq hits
900system.cpu0.dcache.WriteReq_hits::cpu0.data 14394101 # number of WriteReq hits
901system.cpu0.dcache.WriteReq_hits::total 14394101 # number of WriteReq hits
902system.cpu0.dcache.SoftPFReq_hits::cpu0.data 296444 # number of SoftPFReq hits
903system.cpu0.dcache.SoftPFReq_hits::total 296444 # number of SoftPFReq hits
904system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354739 # number of LoadLockedReq hits
905system.cpu0.dcache.LoadLockedReq_hits::total 354739 # number of LoadLockedReq hits
906system.cpu0.dcache.StoreCondReq_hits::cpu0.data 351671 # number of StoreCondReq hits
907system.cpu0.dcache.StoreCondReq_hits::total 351671 # number of StoreCondReq hits
908system.cpu0.dcache.demand_hits::cpu0.data 35041757 # number of demand (read+write) hits
909system.cpu0.dcache.demand_hits::total 35041757 # number of demand (read+write) hits
910system.cpu0.dcache.overall_hits::cpu0.data 35338201 # number of overall hits
911system.cpu0.dcache.overall_hits::total 35338201 # number of overall hits
912system.cpu0.dcache.ReadReq_misses::cpu0.data 609728 # number of ReadReq misses
913system.cpu0.dcache.ReadReq_misses::total 609728 # number of ReadReq misses
914system.cpu0.dcache.WriteReq_misses::cpu0.data 1806132 # number of WriteReq misses
915system.cpu0.dcache.WriteReq_misses::total 1806132 # number of WriteReq misses
916system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141710 # number of SoftPFReq misses
917system.cpu0.dcache.SoftPFReq_misses::total 141710 # number of SoftPFReq misses
918system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24359 # number of LoadLockedReq misses
919system.cpu0.dcache.LoadLockedReq_misses::total 24359 # number of LoadLockedReq misses
920system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21165 # number of StoreCondReq misses
921system.cpu0.dcache.StoreCondReq_misses::total 21165 # number of StoreCondReq misses
922system.cpu0.dcache.demand_misses::cpu0.data 2415860 # number of demand (read+write) misses
923system.cpu0.dcache.demand_misses::total 2415860 # number of demand (read+write) misses
924system.cpu0.dcache.overall_misses::cpu0.data 2557570 # number of overall misses
925system.cpu0.dcache.overall_misses::total 2557570 # number of overall misses
926system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8120126000 # number of ReadReq miss cycles
927system.cpu0.dcache.ReadReq_miss_latency::total 8120126000 # number of ReadReq miss cycles
928system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26313440366 # number of WriteReq miss cycles
929system.cpu0.dcache.WriteReq_miss_latency::total 26313440366 # number of WriteReq miss cycles
930system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 385463000 # number of LoadLockedReq miss cycles
931system.cpu0.dcache.LoadLockedReq_miss_latency::total 385463000 # number of LoadLockedReq miss cycles
932system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 480627500 # number of StoreCondReq miss cycles
933system.cpu0.dcache.StoreCondReq_miss_latency::total 480627500 # number of StoreCondReq miss cycles
934system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 430000 # number of StoreCondFailReq miss cycles
935system.cpu0.dcache.StoreCondFailReq_miss_latency::total 430000 # number of StoreCondFailReq miss cycles
936system.cpu0.dcache.demand_miss_latency::cpu0.data 34433566366 # number of demand (read+write) miss cycles
937system.cpu0.dcache.demand_miss_latency::total 34433566366 # number of demand (read+write) miss cycles
938system.cpu0.dcache.overall_miss_latency::cpu0.data 34433566366 # number of overall miss cycles
939system.cpu0.dcache.overall_miss_latency::total 34433566366 # number of overall miss cycles
940system.cpu0.dcache.ReadReq_accesses::cpu0.data 21257384 # number of ReadReq accesses(hits+misses)
941system.cpu0.dcache.ReadReq_accesses::total 21257384 # number of ReadReq accesses(hits+misses)
942system.cpu0.dcache.WriteReq_accesses::cpu0.data 16200233 # number of WriteReq accesses(hits+misses)
943system.cpu0.dcache.WriteReq_accesses::total 16200233 # number of WriteReq accesses(hits+misses)
944system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 438154 # number of SoftPFReq accesses(hits+misses)
945system.cpu0.dcache.SoftPFReq_accesses::total 438154 # number of SoftPFReq accesses(hits+misses)
946system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379098 # number of LoadLockedReq accesses(hits+misses)
947system.cpu0.dcache.LoadLockedReq_accesses::total 379098 # number of LoadLockedReq accesses(hits+misses)
948system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 372836 # number of StoreCondReq accesses(hits+misses)
949system.cpu0.dcache.StoreCondReq_accesses::total 372836 # number of StoreCondReq accesses(hits+misses)
950system.cpu0.dcache.demand_accesses::cpu0.data 37457617 # number of demand (read+write) accesses
951system.cpu0.dcache.demand_accesses::total 37457617 # number of demand (read+write) accesses
952system.cpu0.dcache.overall_accesses::cpu0.data 37895771 # number of overall (read+write) accesses
953system.cpu0.dcache.overall_accesses::total 37895771 # number of overall (read+write) accesses
954system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028683 # miss rate for ReadReq accesses
955system.cpu0.dcache.ReadReq_miss_rate::total 0.028683 # miss rate for ReadReq accesses
956system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.111488 # miss rate for WriteReq accesses
957system.cpu0.dcache.WriteReq_miss_rate::total 0.111488 # miss rate for WriteReq accesses
958system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323425 # miss rate for SoftPFReq accesses
959system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323425 # miss rate for SoftPFReq accesses
960system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064255 # miss rate for LoadLockedReq accesses
961system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064255 # miss rate for LoadLockedReq accesses
962system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056768 # miss rate for StoreCondReq accesses
963system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056768 # miss rate for StoreCondReq accesses
964system.cpu0.dcache.demand_miss_rate::cpu0.data 0.064496 # miss rate for demand accesses
965system.cpu0.dcache.demand_miss_rate::total 0.064496 # miss rate for demand accesses
966system.cpu0.dcache.overall_miss_rate::cpu0.data 0.067490 # miss rate for overall accesses
967system.cpu0.dcache.overall_miss_rate::total 0.067490 # miss rate for overall accesses
968system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13317.620316 # average ReadReq miss latency
969system.cpu0.dcache.ReadReq_avg_miss_latency::total 13317.620316 # average ReadReq miss latency
970system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14568.946437 # average WriteReq miss latency
971system.cpu0.dcache.WriteReq_avg_miss_latency::total 14568.946437 # average WriteReq miss latency
972system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15824.253869 # average LoadLockedReq miss latency
973system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15824.253869 # average LoadLockedReq miss latency
974system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22708.599102 # average StoreCondReq miss latency
975system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22708.599102 # average StoreCondReq miss latency
976system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
977system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
978system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14253.129886 # average overall miss latency
979system.cpu0.dcache.demand_avg_miss_latency::total 14253.129886 # average overall miss latency
980system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13463.391565 # average overall miss latency
981system.cpu0.dcache.overall_avg_miss_latency::total 13463.391565 # average overall miss latency
982system.cpu0.dcache.blocked_cycles::no_mshrs 747 # number of cycles access was blocked
983system.cpu0.dcache.blocked_cycles::no_targets 3913122 # number of cycles access was blocked
984system.cpu0.dcache.blocked::no_mshrs 47 # number of cycles access was blocked
985system.cpu0.dcache.blocked::no_targets 192454 # number of cycles access was blocked
986system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.893617 # average number of cycles each access was blocked
987system.cpu0.dcache.avg_blocked_cycles::no_targets 20.332765 # average number of cycles each access was blocked
988system.cpu0.dcache.fast_writes 0 # number of fast writes performed
989system.cpu0.dcache.cache_copies 0 # number of cache copies performed
990system.cpu0.dcache.writebacks::writebacks 491417 # number of writebacks
991system.cpu0.dcache.writebacks::total 491417 # number of writebacks
992system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 243049 # number of ReadReq MSHR hits
993system.cpu0.dcache.ReadReq_mshr_hits::total 243049 # number of ReadReq MSHR hits
994system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1494093 # number of WriteReq MSHR hits
995system.cpu0.dcache.WriteReq_mshr_hits::total 1494093 # number of WriteReq MSHR hits
996system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18165 # number of LoadLockedReq MSHR hits
997system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18165 # number of LoadLockedReq MSHR hits
998system.cpu0.dcache.demand_mshr_hits::cpu0.data 1737142 # number of demand (read+write) MSHR hits
999system.cpu0.dcache.demand_mshr_hits::total 1737142 # number of demand (read+write) MSHR hits
1000system.cpu0.dcache.overall_mshr_hits::cpu0.data 1737142 # number of overall MSHR hits
1001system.cpu0.dcache.overall_mshr_hits::total 1737142 # number of overall MSHR hits
1002system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 366679 # number of ReadReq MSHR misses
1003system.cpu0.dcache.ReadReq_mshr_misses::total 366679 # number of ReadReq MSHR misses
1004system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312039 # number of WriteReq MSHR misses
1005system.cpu0.dcache.WriteReq_mshr_misses::total 312039 # number of WriteReq MSHR misses
1006system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98387 # number of SoftPFReq MSHR misses
1007system.cpu0.dcache.SoftPFReq_mshr_misses::total 98387 # number of SoftPFReq MSHR misses
1008system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6194 # number of LoadLockedReq MSHR misses
1009system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6194 # number of LoadLockedReq MSHR misses
1010system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21165 # number of StoreCondReq MSHR misses
1011system.cpu0.dcache.StoreCondReq_mshr_misses::total 21165 # number of StoreCondReq MSHR misses
1012system.cpu0.dcache.demand_mshr_misses::cpu0.data 678718 # number of demand (read+write) MSHR misses
1013system.cpu0.dcache.demand_mshr_misses::total 678718 # number of demand (read+write) MSHR misses
1014system.cpu0.dcache.overall_mshr_misses::cpu0.data 777105 # number of overall MSHR misses
1015system.cpu0.dcache.overall_mshr_misses::total 777105 # number of overall MSHR misses
1016system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29394 # number of ReadReq MSHR uncacheable
1017system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29394 # number of ReadReq MSHR uncacheable
1018system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26127 # number of WriteReq MSHR uncacheable
1019system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26127 # number of WriteReq MSHR uncacheable
1020system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 55521 # number of overall MSHR uncacheable misses
1021system.cpu0.dcache.overall_mshr_uncacheable_misses::total 55521 # number of overall MSHR uncacheable misses
1022system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4291687500 # number of ReadReq MSHR miss cycles
1023system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4291687500 # number of ReadReq MSHR miss cycles
1024system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5394914387 # number of WriteReq MSHR miss cycles
1025system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5394914387 # number of WriteReq MSHR miss cycles
1026system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1614083000 # number of SoftPFReq MSHR miss cycles
1027system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1614083000 # number of SoftPFReq MSHR miss cycles
1028system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 96183500 # number of LoadLockedReq MSHR miss cycles
1029system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96183500 # number of LoadLockedReq MSHR miss cycles
1030system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 459474500 # number of StoreCondReq MSHR miss cycles
1031system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 459474500 # number of StoreCondReq MSHR miss cycles
1032system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 418000 # number of StoreCondFailReq MSHR miss cycles
1033system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 418000 # number of StoreCondFailReq MSHR miss cycles
1034system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9686601887 # number of demand (read+write) MSHR miss cycles
1035system.cpu0.dcache.demand_mshr_miss_latency::total 9686601887 # number of demand (read+write) MSHR miss cycles
1036system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11300684887 # number of overall MSHR miss cycles
1037system.cpu0.dcache.overall_mshr_miss_latency::total 11300684887 # number of overall MSHR miss cycles
1038system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5681056500 # number of ReadReq MSHR uncacheable cycles
1039system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5681056500 # number of ReadReq MSHR uncacheable cycles
1040system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4312326500 # number of WriteReq MSHR uncacheable cycles
1041system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4312326500 # number of WriteReq MSHR uncacheable cycles
1042system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9993383000 # number of overall MSHR uncacheable cycles
1043system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9993383000 # number of overall MSHR uncacheable cycles
1044system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017249 # mshr miss rate for ReadReq accesses
1045system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017249 # mshr miss rate for ReadReq accesses
1046system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019261 # mshr miss rate for WriteReq accesses
1047system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019261 # mshr miss rate for WriteReq accesses
1048system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224549 # mshr miss rate for SoftPFReq accesses
1049system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224549 # mshr miss rate for SoftPFReq accesses
1050system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016339 # mshr miss rate for LoadLockedReq accesses
1051system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016339 # mshr miss rate for LoadLockedReq accesses
1052system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056768 # mshr miss rate for StoreCondReq accesses
1053system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056768 # mshr miss rate for StoreCondReq accesses
1054system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018120 # mshr miss rate for demand accesses
1055system.cpu0.dcache.demand_mshr_miss_rate::total 0.018120 # mshr miss rate for demand accesses
1056system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020506 # mshr miss rate for overall accesses
1057system.cpu0.dcache.overall_mshr_miss_rate::total 0.020506 # mshr miss rate for overall accesses
1058system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11704.208586 # average ReadReq mshr miss latency
1059system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11704.208586 # average ReadReq mshr miss latency
1060system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17289.231112 # average WriteReq mshr miss latency
1061system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17289.231112 # average WriteReq mshr miss latency
1062system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16405.449907 # average SoftPFReq mshr miss latency
1063system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16405.449907 # average SoftPFReq mshr miss latency
1064system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15528.495318 # average LoadLockedReq mshr miss latency
1065system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15528.495318 # average LoadLockedReq mshr miss latency
1066system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21709.166076 # average StoreCondReq mshr miss latency
1067system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21709.166076 # average StoreCondReq mshr miss latency
1068system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
1069system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1070system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14271.909522 # average overall mshr miss latency
1071system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14271.909522 # average overall mshr miss latency
1072system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14542.030854 # average overall mshr miss latency
1073system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14542.030854 # average overall mshr miss latency
1074system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193272.657685 # average ReadReq mshr uncacheable latency
1075system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193272.657685 # average ReadReq mshr uncacheable latency
1076system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165052.493589 # average WriteReq mshr uncacheable latency
1077system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165052.493589 # average WriteReq mshr uncacheable latency
1078system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179992.849552 # average overall mshr uncacheable latency
1079system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179992.849552 # average overall mshr uncacheable latency
1080system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1081system.cpu0.icache.tags.replacements 1208444 # number of replacements
1082system.cpu0.icache.tags.tagsinuse 511.748718 # Cycle average of tags in use
1083system.cpu0.icache.tags.total_refs 69666115 # Total number of references to valid blocks.
1084system.cpu0.icache.tags.sampled_refs 1208956 # Sample count of references to valid blocks.
1085system.cpu0.icache.tags.avg_refs 57.625021 # Average number of references to valid blocks.
1086system.cpu0.icache.tags.warmup_cycle 6421480000 # Cycle when the warmup percentage was hit.
1087system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.748718 # Average occupied blocks per requestor
1088system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999509 # Average percentage of cache occupancy
1089system.cpu0.icache.tags.occ_percent::total 0.999509 # Average percentage of cache occupancy
1090system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1091system.cpu0.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
1092system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id
1093system.cpu0.icache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id
1094system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1095system.cpu0.icache.tags.tag_accesses 143059850 # Number of tag accesses
1096system.cpu0.icache.tags.data_accesses 143059850 # Number of data accesses
1097system.cpu0.icache.ReadReq_hits::cpu0.inst 69666115 # number of ReadReq hits
1098system.cpu0.icache.ReadReq_hits::total 69666115 # number of ReadReq hits
1099system.cpu0.icache.demand_hits::cpu0.inst 69666115 # number of demand (read+write) hits
1100system.cpu0.icache.demand_hits::total 69666115 # number of demand (read+write) hits
1101system.cpu0.icache.overall_hits::cpu0.inst 69666115 # number of overall hits
1102system.cpu0.icache.overall_hits::total 69666115 # number of overall hits
1103system.cpu0.icache.ReadReq_misses::cpu0.inst 1259322 # number of ReadReq misses
1104system.cpu0.icache.ReadReq_misses::total 1259322 # number of ReadReq misses
1105system.cpu0.icache.demand_misses::cpu0.inst 1259322 # number of demand (read+write) misses
1106system.cpu0.icache.demand_misses::total 1259322 # number of demand (read+write) misses
1107system.cpu0.icache.overall_misses::cpu0.inst 1259322 # number of overall misses
1108system.cpu0.icache.overall_misses::total 1259322 # number of overall misses
1109system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12306647041 # number of ReadReq miss cycles
1110system.cpu0.icache.ReadReq_miss_latency::total 12306647041 # number of ReadReq miss cycles
1111system.cpu0.icache.demand_miss_latency::cpu0.inst 12306647041 # number of demand (read+write) miss cycles
1112system.cpu0.icache.demand_miss_latency::total 12306647041 # number of demand (read+write) miss cycles
1113system.cpu0.icache.overall_miss_latency::cpu0.inst 12306647041 # number of overall miss cycles
1114system.cpu0.icache.overall_miss_latency::total 12306647041 # number of overall miss cycles
1115system.cpu0.icache.ReadReq_accesses::cpu0.inst 70925437 # number of ReadReq accesses(hits+misses)
1116system.cpu0.icache.ReadReq_accesses::total 70925437 # number of ReadReq accesses(hits+misses)
1117system.cpu0.icache.demand_accesses::cpu0.inst 70925437 # number of demand (read+write) accesses
1118system.cpu0.icache.demand_accesses::total 70925437 # number of demand (read+write) accesses
1119system.cpu0.icache.overall_accesses::cpu0.inst 70925437 # number of overall (read+write) accesses
1120system.cpu0.icache.overall_accesses::total 70925437 # number of overall (read+write) accesses
1121system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017756 # miss rate for ReadReq accesses
1122system.cpu0.icache.ReadReq_miss_rate::total 0.017756 # miss rate for ReadReq accesses
1123system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017756 # miss rate for demand accesses
1124system.cpu0.icache.demand_miss_rate::total 0.017756 # miss rate for demand accesses
1125system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017756 # miss rate for overall accesses
1126system.cpu0.icache.overall_miss_rate::total 0.017756 # miss rate for overall accesses
1127system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9772.438694 # average ReadReq miss latency
1128system.cpu0.icache.ReadReq_avg_miss_latency::total 9772.438694 # average ReadReq miss latency
1129system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9772.438694 # average overall miss latency
1130system.cpu0.icache.demand_avg_miss_latency::total 9772.438694 # average overall miss latency
1131system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9772.438694 # average overall miss latency
1132system.cpu0.icache.overall_avg_miss_latency::total 9772.438694 # average overall miss latency
1133system.cpu0.icache.blocked_cycles::no_mshrs 1459740 # number of cycles access was blocked
1134system.cpu0.icache.blocked_cycles::no_targets 453 # number of cycles access was blocked
1135system.cpu0.icache.blocked::no_mshrs 110714 # number of cycles access was blocked
1136system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked
1137system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.184782 # average number of cycles each access was blocked
1138system.cpu0.icache.avg_blocked_cycles::no_targets 45.300000 # average number of cycles each access was blocked
1139system.cpu0.icache.fast_writes 0 # number of fast writes performed
1140system.cpu0.icache.cache_copies 0 # number of cache copies performed
1141system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 50344 # number of ReadReq MSHR hits
1142system.cpu0.icache.ReadReq_mshr_hits::total 50344 # number of ReadReq MSHR hits
1143system.cpu0.icache.demand_mshr_hits::cpu0.inst 50344 # number of demand (read+write) MSHR hits
1144system.cpu0.icache.demand_mshr_hits::total 50344 # number of demand (read+write) MSHR hits
1145system.cpu0.icache.overall_mshr_hits::cpu0.inst 50344 # number of overall MSHR hits
1146system.cpu0.icache.overall_mshr_hits::total 50344 # number of overall MSHR hits
1147system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1208978 # number of ReadReq MSHR misses
1148system.cpu0.icache.ReadReq_mshr_misses::total 1208978 # number of ReadReq MSHR misses
1149system.cpu0.icache.demand_mshr_misses::cpu0.inst 1208978 # number of demand (read+write) MSHR misses
1150system.cpu0.icache.demand_mshr_misses::total 1208978 # number of demand (read+write) MSHR misses
1151system.cpu0.icache.overall_mshr_misses::cpu0.inst 1208978 # number of overall MSHR misses
1152system.cpu0.icache.overall_mshr_misses::total 1208978 # number of overall MSHR misses
1153system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable
1154system.cpu0.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable
1155system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses
1156system.cpu0.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses
1157system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11179466333 # number of ReadReq MSHR miss cycles
1158system.cpu0.icache.ReadReq_mshr_miss_latency::total 11179466333 # number of ReadReq MSHR miss cycles
1159system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11179466333 # number of demand (read+write) MSHR miss cycles
1160system.cpu0.icache.demand_mshr_miss_latency::total 11179466333 # number of demand (read+write) MSHR miss cycles
1161system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11179466333 # number of overall MSHR miss cycles
1162system.cpu0.icache.overall_mshr_miss_latency::total 11179466333 # number of overall MSHR miss cycles
1163system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265874998 # number of ReadReq MSHR uncacheable cycles
1164system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 265874998 # number of ReadReq MSHR uncacheable cycles
1165system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 265874998 # number of overall MSHR uncacheable cycles
1166system.cpu0.icache.overall_mshr_uncacheable_latency::total 265874998 # number of overall MSHR uncacheable cycles
1167system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017046 # mshr miss rate for ReadReq accesses
1168system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017046 # mshr miss rate for ReadReq accesses
1169system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017046 # mshr miss rate for demand accesses
1170system.cpu0.icache.demand_mshr_miss_rate::total 0.017046 # mshr miss rate for demand accesses
1171system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017046 # mshr miss rate for overall accesses
1172system.cpu0.icache.overall_mshr_miss_rate::total 0.017046 # mshr miss rate for overall accesses
1173system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9247.038683 # average ReadReq mshr miss latency
1174system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9247.038683 # average ReadReq mshr miss latency
1175system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9247.038683 # average overall mshr miss latency
1176system.cpu0.icache.demand_avg_mshr_miss_latency::total 9247.038683 # average overall mshr miss latency
1177system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9247.038683 # average overall mshr miss latency
1178system.cpu0.icache.overall_avg_mshr_miss_latency::total 9247.038683 # average overall mshr miss latency
1179system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88506.990013 # average ReadReq mshr uncacheable latency
1180system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88506.990013 # average ReadReq mshr uncacheable latency
1181system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88506.990013 # average overall mshr uncacheable latency
1182system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88506.990013 # average overall mshr uncacheable latency
1183system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1184system.cpu0.l2cache.prefetcher.num_hwpf_issued 1763942 # number of hwpf issued
1185system.cpu0.l2cache.prefetcher.pfIdentified 1769107 # number of prefetch candidates identified
1186system.cpu0.l2cache.prefetcher.pfBufferHit 4567 # number of redundant prefetches already in prefetch queue
1187system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1188system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1189system.cpu0.l2cache.prefetcher.pfSpanPage 220637 # number of prefetches not generated due to page crossing
1190system.cpu0.l2cache.tags.replacements 266650 # number of replacements
1191system.cpu0.l2cache.tags.tagsinuse 16052.098762 # Cycle average of tags in use
1192system.cpu0.l2cache.tags.total_refs 3449668 # Total number of references to valid blocks.
1193system.cpu0.l2cache.tags.sampled_refs 282876 # Sample count of references to valid blocks.
1194system.cpu0.l2cache.tags.avg_refs 12.194983 # Average number of references to valid blocks.
1195system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1196system.cpu0.l2cache.tags.occ_blocks::writebacks 9287.877050 # Average occupied blocks per requestor
1197system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 13.757624 # Average occupied blocks per requestor
1198system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.215297 # Average occupied blocks per requestor
1199system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4106.053527 # Average occupied blocks per requestor
1200system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1602.376504 # Average occupied blocks per requestor
1201system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1041.818760 # Average occupied blocks per requestor
1202system.cpu0.l2cache.tags.occ_percent::writebacks 0.566887 # Average percentage of cache occupancy
1203system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000840 # Average percentage of cache occupancy
1204system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000013 # Average percentage of cache occupancy
1205system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.250614 # Average percentage of cache occupancy
1206system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.097801 # Average percentage of cache occupancy
1207system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063588 # Average percentage of cache occupancy
1208system.cpu0.l2cache.tags.occ_percent::total 0.979742 # Average percentage of cache occupancy
1209system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1056 # Occupied blocks per task id
1210system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id
1211system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15158 # Occupied blocks per task id
1212system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 44 # Occupied blocks per task id
1213system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 321 # Occupied blocks per task id
1214system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 415 # Occupied blocks per task id
1215system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 276 # Occupied blocks per task id
1216system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id
1217system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id
1218system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
1219system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 414 # Occupied blocks per task id
1220system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4651 # Occupied blocks per task id
1221system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7186 # Occupied blocks per task id
1222system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2852 # Occupied blocks per task id
1223system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.064453 # Percentage of cache occupancy per task id
1224system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id
1225system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.925171 # Percentage of cache occupancy per task id
1226system.cpu0.l2cache.tags.tag_accesses 63497786 # Number of tag accesses
1227system.cpu0.l2cache.tags.data_accesses 63497786 # Number of data accesses
1228system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 50315 # number of ReadReq hits
1229system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12479 # number of ReadReq hits
1230system.cpu0.l2cache.ReadReq_hits::total 62794 # number of ReadReq hits
1231system.cpu0.l2cache.Writeback_hits::writebacks 491416 # number of Writeback hits
1232system.cpu0.l2cache.Writeback_hits::total 491416 # number of Writeback hits
1233system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28453 # number of UpgradeReq hits
1234system.cpu0.l2cache.UpgradeReq_hits::total 28453 # number of UpgradeReq hits
1235system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1608 # number of SCUpgradeReq hits
1236system.cpu0.l2cache.SCUpgradeReq_hits::total 1608 # number of SCUpgradeReq hits
1237system.cpu0.l2cache.ReadExReq_hits::cpu0.data 210730 # number of ReadExReq hits
1238system.cpu0.l2cache.ReadExReq_hits::total 210730 # number of ReadExReq hits
1239system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1158323 # number of ReadCleanReq hits
1240system.cpu0.l2cache.ReadCleanReq_hits::total 1158323 # number of ReadCleanReq hits
1241system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 372689 # number of ReadSharedReq hits
1242system.cpu0.l2cache.ReadSharedReq_hits::total 372689 # number of ReadSharedReq hits
1243system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 50315 # number of demand (read+write) hits
1244system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12479 # number of demand (read+write) hits
1245system.cpu0.l2cache.demand_hits::cpu0.inst 1158323 # number of demand (read+write) hits
1246system.cpu0.l2cache.demand_hits::cpu0.data 583419 # number of demand (read+write) hits
1247system.cpu0.l2cache.demand_hits::total 1804536 # number of demand (read+write) hits
1248system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 50315 # number of overall hits
1249system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12479 # number of overall hits
1250system.cpu0.l2cache.overall_hits::cpu0.inst 1158323 # number of overall hits
1251system.cpu0.l2cache.overall_hits::cpu0.data 583419 # number of overall hits
1252system.cpu0.l2cache.overall_hits::total 1804536 # number of overall hits
1253system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 419 # number of ReadReq misses
1254system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 174 # number of ReadReq misses
1255system.cpu0.l2cache.ReadReq_misses::total 593 # number of ReadReq misses
1256system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27292 # number of UpgradeReq misses
1257system.cpu0.l2cache.UpgradeReq_misses::total 27292 # number of UpgradeReq misses
1258system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19556 # number of SCUpgradeReq misses
1259system.cpu0.l2cache.SCUpgradeReq_misses::total 19556 # number of SCUpgradeReq misses
1260system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses
1261system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
1262system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45826 # number of ReadExReq misses
1263system.cpu0.l2cache.ReadExReq_misses::total 45826 # number of ReadExReq misses
1264system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 50641 # number of ReadCleanReq misses
1265system.cpu0.l2cache.ReadCleanReq_misses::total 50641 # number of ReadCleanReq misses
1266system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 98477 # number of ReadSharedReq misses
1267system.cpu0.l2cache.ReadSharedReq_misses::total 98477 # number of ReadSharedReq misses
1268system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 419 # number of demand (read+write) misses
1269system.cpu0.l2cache.demand_misses::cpu0.itb.walker 174 # number of demand (read+write) misses
1270system.cpu0.l2cache.demand_misses::cpu0.inst 50641 # number of demand (read+write) misses
1271system.cpu0.l2cache.demand_misses::cpu0.data 144303 # number of demand (read+write) misses
1272system.cpu0.l2cache.demand_misses::total 195537 # number of demand (read+write) misses
1273system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 419 # number of overall misses
1274system.cpu0.l2cache.overall_misses::cpu0.itb.walker 174 # number of overall misses
1275system.cpu0.l2cache.overall_misses::cpu0.inst 50641 # number of overall misses
1276system.cpu0.l2cache.overall_misses::cpu0.data 144303 # number of overall misses
1277system.cpu0.l2cache.overall_misses::total 195537 # number of overall misses
1278system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11008500 # number of ReadReq miss cycles
1279system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4405500 # number of ReadReq miss cycles
1280system.cpu0.l2cache.ReadReq_miss_latency::total 15414000 # number of ReadReq miss cycles
1281system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 502449500 # number of UpgradeReq miss cycles
1282system.cpu0.l2cache.UpgradeReq_miss_latency::total 502449500 # number of UpgradeReq miss cycles
1283system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 396768500 # number of SCUpgradeReq miss cycles
1284system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 396768500 # number of SCUpgradeReq miss cycles
1285system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 399000 # number of SCUpgradeFailReq miss cycles
1286system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 399000 # number of SCUpgradeFailReq miss cycles
1287system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2648910998 # number of ReadExReq miss cycles
1288system.cpu0.l2cache.ReadExReq_miss_latency::total 2648910998 # number of ReadExReq miss cycles
1289system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2424883999 # number of ReadCleanReq miss cycles
1290system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2424883999 # number of ReadCleanReq miss cycles
1291system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2835688998 # number of ReadSharedReq miss cycles
1292system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2835688998 # number of ReadSharedReq miss cycles
1293system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11008500 # number of demand (read+write) miss cycles
1294system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4405500 # number of demand (read+write) miss cycles
1295system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2424883999 # number of demand (read+write) miss cycles
1296system.cpu0.l2cache.demand_miss_latency::cpu0.data 5484599996 # number of demand (read+write) miss cycles
1297system.cpu0.l2cache.demand_miss_latency::total 7924897995 # number of demand (read+write) miss cycles
1298system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11008500 # number of overall miss cycles
1299system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4405500 # number of overall miss cycles
1300system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2424883999 # number of overall miss cycles
1301system.cpu0.l2cache.overall_miss_latency::cpu0.data 5484599996 # number of overall miss cycles
1302system.cpu0.l2cache.overall_miss_latency::total 7924897995 # number of overall miss cycles
1303system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 50734 # number of ReadReq accesses(hits+misses)
1304system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12653 # number of ReadReq accesses(hits+misses)
1305system.cpu0.l2cache.ReadReq_accesses::total 63387 # number of ReadReq accesses(hits+misses)
1306system.cpu0.l2cache.Writeback_accesses::writebacks 491416 # number of Writeback accesses(hits+misses)
1307system.cpu0.l2cache.Writeback_accesses::total 491416 # number of Writeback accesses(hits+misses)
1308system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55745 # number of UpgradeReq accesses(hits+misses)
1309system.cpu0.l2cache.UpgradeReq_accesses::total 55745 # number of UpgradeReq accesses(hits+misses)
1310system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21164 # number of SCUpgradeReq accesses(hits+misses)
1311system.cpu0.l2cache.SCUpgradeReq_accesses::total 21164 # number of SCUpgradeReq accesses(hits+misses)
1312system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
1313system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
1314system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256556 # number of ReadExReq accesses(hits+misses)
1315system.cpu0.l2cache.ReadExReq_accesses::total 256556 # number of ReadExReq accesses(hits+misses)
1316system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1208964 # number of ReadCleanReq accesses(hits+misses)
1317system.cpu0.l2cache.ReadCleanReq_accesses::total 1208964 # number of ReadCleanReq accesses(hits+misses)
1318system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 471166 # number of ReadSharedReq accesses(hits+misses)
1319system.cpu0.l2cache.ReadSharedReq_accesses::total 471166 # number of ReadSharedReq accesses(hits+misses)
1320system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 50734 # number of demand (read+write) accesses
1321system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12653 # number of demand (read+write) accesses
1322system.cpu0.l2cache.demand_accesses::cpu0.inst 1208964 # number of demand (read+write) accesses
1323system.cpu0.l2cache.demand_accesses::cpu0.data 727722 # number of demand (read+write) accesses
1324system.cpu0.l2cache.demand_accesses::total 2000073 # number of demand (read+write) accesses
1325system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 50734 # number of overall (read+write) accesses
1326system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12653 # number of overall (read+write) accesses
1327system.cpu0.l2cache.overall_accesses::cpu0.inst 1208964 # number of overall (read+write) accesses
1328system.cpu0.l2cache.overall_accesses::cpu0.data 727722 # number of overall (read+write) accesses
1329system.cpu0.l2cache.overall_accesses::total 2000073 # number of overall (read+write) accesses
1330system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.008259 # miss rate for ReadReq accesses
1331system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.013752 # miss rate for ReadReq accesses
1332system.cpu0.l2cache.ReadReq_miss_rate::total 0.009355 # miss rate for ReadReq accesses
1333system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.489587 # miss rate for UpgradeReq accesses
1334system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.489587 # miss rate for UpgradeReq accesses
1335system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.924022 # miss rate for SCUpgradeReq accesses
1336system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.924022 # miss rate for SCUpgradeReq accesses
1337system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1338system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1339system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.178620 # miss rate for ReadExReq accesses
1340system.cpu0.l2cache.ReadExReq_miss_rate::total 0.178620 # miss rate for ReadExReq accesses
1341system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.041888 # miss rate for ReadCleanReq accesses
1342system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.041888 # miss rate for ReadCleanReq accesses
1343system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.209007 # miss rate for ReadSharedReq accesses
1344system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.209007 # miss rate for ReadSharedReq accesses
1345system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.008259 # miss rate for demand accesses
1346system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.013752 # miss rate for demand accesses
1347system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041888 # miss rate for demand accesses
1348system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.198294 # miss rate for demand accesses
1349system.cpu0.l2cache.demand_miss_rate::total 0.097765 # miss rate for demand accesses
1350system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.008259 # miss rate for overall accesses
1351system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.013752 # miss rate for overall accesses
1352system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041888 # miss rate for overall accesses
1353system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.198294 # miss rate for overall accesses
1354system.cpu0.l2cache.overall_miss_rate::total 0.097765 # miss rate for overall accesses
1355system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26273.269690 # average ReadReq miss latency
1356system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 25318.965517 # average ReadReq miss latency
1357system.cpu0.l2cache.ReadReq_avg_miss_latency::total 25993.254637 # average ReadReq miss latency
1358system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18410.138502 # average UpgradeReq miss latency
1359system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18410.138502 # average UpgradeReq miss latency
1360system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20288.837186 # average SCUpgradeReq miss latency
1361system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20288.837186 # average SCUpgradeReq miss latency
1362system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 399000 # average SCUpgradeFailReq miss latency
1363system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 399000 # average SCUpgradeFailReq miss latency
1364system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 57803.670362 # average ReadExReq miss latency
1365system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 57803.670362 # average ReadExReq miss latency
1366system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 47883.809542 # average ReadCleanReq miss latency
1367system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 47883.809542 # average ReadCleanReq miss latency
1368system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 28795.444601 # average ReadSharedReq miss latency
1369system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 28795.444601 # average ReadSharedReq miss latency
1370system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26273.269690 # average overall miss latency
1371system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 25318.965517 # average overall miss latency
1372system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 47883.809542 # average overall miss latency
1373system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38007.525803 # average overall miss latency
1374system.cpu0.l2cache.demand_avg_miss_latency::total 40528.892205 # average overall miss latency
1375system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26273.269690 # average overall miss latency
1376system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 25318.965517 # average overall miss latency
1377system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 47883.809542 # average overall miss latency
1378system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38007.525803 # average overall miss latency
1379system.cpu0.l2cache.overall_avg_miss_latency::total 40528.892205 # average overall miss latency
1380system.cpu0.l2cache.blocked_cycles::no_mshrs 236 # number of cycles access was blocked
1381system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1382system.cpu0.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked
1383system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1384system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 29.500000 # average number of cycles each access was blocked
1385system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1386system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1387system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1388system.cpu0.l2cache.writebacks::writebacks 193260 # number of writebacks
1389system.cpu0.l2cache.writebacks::total 193260 # number of writebacks
1390system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
1391system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits
1392system.cpu0.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
1393system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6054 # number of ReadExReq MSHR hits
1394system.cpu0.l2cache.ReadExReq_mshr_hits::total 6054 # number of ReadExReq MSHR hits
1395system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 30 # number of ReadCleanReq MSHR hits
1396system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 30 # number of ReadCleanReq MSHR hits
1397system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 713 # number of ReadSharedReq MSHR hits
1398system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 713 # number of ReadSharedReq MSHR hits
1399system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
1400system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits
1401system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 30 # number of demand (read+write) MSHR hits
1402system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6767 # number of demand (read+write) MSHR hits
1403system.cpu0.l2cache.demand_mshr_hits::total 6799 # number of demand (read+write) MSHR hits
1404system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
1405system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits
1406system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 30 # number of overall MSHR hits
1407system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6767 # number of overall MSHR hits
1408system.cpu0.l2cache.overall_mshr_hits::total 6799 # number of overall MSHR hits
1409system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 418 # number of ReadReq MSHR misses
1410system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 173 # number of ReadReq MSHR misses
1411system.cpu0.l2cache.ReadReq_mshr_misses::total 591 # number of ReadReq MSHR misses
1412system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 8374 # number of CleanEvict MSHR misses
1413system.cpu0.l2cache.CleanEvict_mshr_misses::total 8374 # number of CleanEvict MSHR misses
1414system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 232540 # number of HardPFReq MSHR misses
1415system.cpu0.l2cache.HardPFReq_mshr_misses::total 232540 # number of HardPFReq MSHR misses
1416system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27292 # number of UpgradeReq MSHR misses
1417system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27292 # number of UpgradeReq MSHR misses
1418system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19556 # number of SCUpgradeReq MSHR misses
1419system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19556 # number of SCUpgradeReq MSHR misses
1420system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses
1421system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
1422system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 39772 # number of ReadExReq MSHR misses
1423system.cpu0.l2cache.ReadExReq_mshr_misses::total 39772 # number of ReadExReq MSHR misses
1424system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 50611 # number of ReadCleanReq MSHR misses
1425system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 50611 # number of ReadCleanReq MSHR misses
1426system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 97764 # number of ReadSharedReq MSHR misses
1427system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 97764 # number of ReadSharedReq MSHR misses
1428system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 418 # number of demand (read+write) MSHR misses
1429system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 173 # number of demand (read+write) MSHR misses
1430system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 50611 # number of demand (read+write) MSHR misses
1431system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137536 # number of demand (read+write) MSHR misses
1432system.cpu0.l2cache.demand_mshr_misses::total 188738 # number of demand (read+write) MSHR misses
1433system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 418 # number of overall MSHR misses
1434system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 173 # number of overall MSHR misses
1435system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 50611 # number of overall MSHR misses
1436system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137536 # number of overall MSHR misses
1437system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 232540 # number of overall MSHR misses
1438system.cpu0.l2cache.overall_mshr_misses::total 421278 # number of overall MSHR misses
1439system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable
1440system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29394 # number of ReadReq MSHR uncacheable
1441system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 32398 # number of ReadReq MSHR uncacheable
1442system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 26127 # number of WriteReq MSHR uncacheable
1443system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 26127 # number of WriteReq MSHR uncacheable
1444system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses
1445system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 55521 # number of overall MSHR uncacheable misses
1446system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 58525 # number of overall MSHR uncacheable misses
1447system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 8479500 # number of ReadReq MSHR miss cycles
1448system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3355000 # number of ReadReq MSHR miss cycles
1449system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 11834500 # number of ReadReq MSHR miss cycles
1450system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15228773142 # number of HardPFReq MSHR miss cycles
1451system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15228773142 # number of HardPFReq MSHR miss cycles
1452system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 539452500 # number of UpgradeReq MSHR miss cycles
1453system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 539452500 # number of UpgradeReq MSHR miss cycles
1454system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 299483497 # number of SCUpgradeReq MSHR miss cycles
1455system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 299483497 # number of SCUpgradeReq MSHR miss cycles
1456system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 327000 # number of SCUpgradeFailReq MSHR miss cycles
1457system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 327000 # number of SCUpgradeFailReq MSHR miss cycles
1458system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1648200500 # number of ReadExReq MSHR miss cycles
1459system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1648200500 # number of ReadExReq MSHR miss cycles
1460system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2120543999 # number of ReadCleanReq MSHR miss cycles
1461system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2120543999 # number of ReadCleanReq MSHR miss cycles
1462system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2210587998 # number of ReadSharedReq MSHR miss cycles
1463system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2210587998 # number of ReadSharedReq MSHR miss cycles
1464system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 8479500 # number of demand (read+write) MSHR miss cycles
1465system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3355000 # number of demand (read+write) MSHR miss cycles
1466system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2120543999 # number of demand (read+write) MSHR miss cycles
1467system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3858788498 # number of demand (read+write) MSHR miss cycles
1468system.cpu0.l2cache.demand_mshr_miss_latency::total 5991166997 # number of demand (read+write) MSHR miss cycles
1469system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 8479500 # number of overall MSHR miss cycles
1470system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3355000 # number of overall MSHR miss cycles
1471system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2120543999 # number of overall MSHR miss cycles
1472system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3858788498 # number of overall MSHR miss cycles
1473system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15228773142 # number of overall MSHR miss cycles
1474system.cpu0.l2cache.overall_mshr_miss_latency::total 21219940139 # number of overall MSHR miss cycles
1475system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 243342000 # number of ReadReq MSHR uncacheable cycles
1476system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5445807000 # number of ReadReq MSHR uncacheable cycles
1477system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5689149000 # number of ReadReq MSHR uncacheable cycles
1478system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4113464958 # number of WriteReq MSHR uncacheable cycles
1479system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4113464958 # number of WriteReq MSHR uncacheable cycles
1480system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 243342000 # number of overall MSHR uncacheable cycles
1481system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9559271958 # number of overall MSHR uncacheable cycles
1482system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9802613958 # number of overall MSHR uncacheable cycles
1483system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008239 # mshr miss rate for ReadReq accesses
1484system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013673 # mshr miss rate for ReadReq accesses
1485system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009324 # mshr miss rate for ReadReq accesses
1486system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1487system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1488system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1489system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1490system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.489587 # mshr miss rate for UpgradeReq accesses
1491system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.489587 # mshr miss rate for UpgradeReq accesses
1492system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.924022 # mshr miss rate for SCUpgradeReq accesses
1493system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.924022 # mshr miss rate for SCUpgradeReq accesses
1494system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1495system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1496system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155023 # mshr miss rate for ReadExReq accesses
1497system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155023 # mshr miss rate for ReadExReq accesses
1498system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041863 # mshr miss rate for ReadCleanReq accesses
1499system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041863 # mshr miss rate for ReadCleanReq accesses
1500system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.207494 # mshr miss rate for ReadSharedReq accesses
1501system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.207494 # mshr miss rate for ReadSharedReq accesses
1502system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008239 # mshr miss rate for demand accesses
1503system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013673 # mshr miss rate for demand accesses
1504system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041863 # mshr miss rate for demand accesses
1505system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.188995 # mshr miss rate for demand accesses
1506system.cpu0.l2cache.demand_mshr_miss_rate::total 0.094366 # mshr miss rate for demand accesses
1507system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008239 # mshr miss rate for overall accesses
1508system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013673 # mshr miss rate for overall accesses
1509system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041863 # mshr miss rate for overall accesses
1510system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.188995 # mshr miss rate for overall accesses
1511system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1512system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210631 # mshr miss rate for overall accesses
1513system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167 # average ReadReq mshr miss latency
1514system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584 # average ReadReq mshr miss latency
1515system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20024.534687 # average ReadReq mshr miss latency
1516system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65488.832640 # average HardPFReq mshr miss latency
1517system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65488.832640 # average HardPFReq mshr miss latency
1518system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19765.957057 # average UpgradeReq mshr miss latency
1519system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19765.957057 # average UpgradeReq mshr miss latency
1520system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15314.148957 # average SCUpgradeReq mshr miss latency
1521system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15314.148957 # average SCUpgradeReq mshr miss latency
1522system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 327000 # average SCUpgradeFailReq mshr miss latency
1523system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 327000 # average SCUpgradeFailReq mshr miss latency
1524system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41441.227497 # average ReadExReq mshr miss latency
1525system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41441.227497 # average ReadExReq mshr miss latency
1526system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 41898.875719 # average ReadCleanReq mshr miss latency
1527system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 41898.875719 # average ReadCleanReq mshr miss latency
1528system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22611.472505 # average ReadSharedReq mshr miss latency
1529system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22611.472505 # average ReadSharedReq mshr miss latency
1530system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167 # average overall mshr miss latency
1531system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584 # average overall mshr miss latency
1532system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 41898.875719 # average overall mshr miss latency
1533system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28056.570629 # average overall mshr miss latency
1534system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31743.300220 # average overall mshr miss latency
1535system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167 # average overall mshr miss latency
1536system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584 # average overall mshr miss latency
1537system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 41898.875719 # average overall mshr miss latency
1538system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28056.570629 # average overall mshr miss latency
1539system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65488.832640 # average overall mshr miss latency
1540system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50370.397075 # average overall mshr miss latency
1541system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81005.992011 # average ReadReq mshr uncacheable latency
1542system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185269.340682 # average ReadReq mshr uncacheable latency
1543system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175601.858139 # average ReadReq mshr uncacheable latency
1544system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157441.151223 # average WriteReq mshr uncacheable latency
1545system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157441.151223 # average WriteReq mshr uncacheable latency
1546system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81005.992011 # average overall mshr uncacheable latency
1547system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 172173.987464 # average overall mshr uncacheable latency
1548system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 167494.471730 # average overall mshr uncacheable latency
1549system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1550system.cpu0.toL2Bus.trans_dist::ReadReq 116134 # Transaction distribution
1551system.cpu0.toL2Bus.trans_dist::ReadResp 1839025 # Transaction distribution
1552system.cpu0.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution
1553system.cpu0.toL2Bus.trans_dist::WriteResp 26127 # Transaction distribution
1554system.cpu0.toL2Bus.trans_dist::Writeback 864426 # Transaction distribution
1555system.cpu0.toL2Bus.trans_dist::CleanEvict 1492254 # Transaction distribution
1556system.cpu0.toL2Bus.trans_dist::HardPFReq 304971 # Transaction distribution
1557system.cpu0.toL2Bus.trans_dist::UpgradeReq 91775 # Transaction distribution
1558system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43512 # Transaction distribution
1559system.cpu0.toL2Bus.trans_dist::UpgradeResp 114568 # Transaction distribution
1560system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
1561system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
1562system.cpu0.toL2Bus.trans_dist::ReadExReq 284553 # Transaction distribution
1563system.cpu0.toL2Bus.trans_dist::ReadExResp 270414 # Transaction distribution
1564system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1208978 # Transaction distribution
1565system.cpu0.toL2Bus.trans_dist::ReadSharedReq 592867 # Transaction distribution
1566system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
1567system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3608808 # Packet count per connected master and slave (bytes)
1568system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2486821 # Packet count per connected master and slave (bytes)
1569system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28899 # Packet count per connected master and slave (bytes)
1570system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 112519 # Packet count per connected master and slave (bytes)
1571system.cpu0.toL2Bus.pkt_count::total 6237047 # Packet count per connected master and slave (bytes)
1572system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 77421632 # Cumulative packet size per connected master and slave (bytes)
1573system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82196692 # Cumulative packet size per connected master and slave (bytes)
1574system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50612 # Cumulative packet size per connected master and slave (bytes)
1575system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 202936 # Cumulative packet size per connected master and slave (bytes)
1576system.cpu0.toL2Bus.pkt_size::total 159871872 # Cumulative packet size per connected master and slave (bytes)
1577system.cpu0.toL2Bus.snoops 1179844 # Total snoops (count)
1578system.cpu0.toL2Bus.snoop_fanout::samples 5097277 # Request fanout histogram
1579system.cpu0.toL2Bus.snoop_fanout::mean 1.224281 # Request fanout histogram
1580system.cpu0.toL2Bus.snoop_fanout::stdev 0.417108 # Request fanout histogram
1581system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1582system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1583system.cpu0.toL2Bus.snoop_fanout::1 3954053 77.57% 77.57% # Request fanout histogram
1584system.cpu0.toL2Bus.snoop_fanout::2 1143224 22.43% 100.00% # Request fanout histogram
1585system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1586system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1587system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1588system.cpu0.toL2Bus.snoop_fanout::total 5097277 # Request fanout histogram
1589system.cpu0.toL2Bus.reqLayer0.occupancy 2520550941 # Layer occupancy (ticks)
1590system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1591system.cpu0.toL2Bus.snoopLayer0.occupancy 112317000 # Layer occupancy (ticks)
1592system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1593system.cpu0.toL2Bus.respLayer0.occupancy 1816757420 # Layer occupancy (ticks)
1594system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1595system.cpu0.toL2Bus.respLayer1.occupancy 1173564387 # Layer occupancy (ticks)
1596system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1597system.cpu0.toL2Bus.respLayer2.occupancy 16253983 # Layer occupancy (ticks)
1598system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1599system.cpu0.toL2Bus.respLayer3.occupancy 61816936 # Layer occupancy (ticks)
1600system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1601system.cpu1.branchPred.lookups 6152669 # Number of BP lookups
1602system.cpu1.branchPred.condPredicted 3868120 # Number of conditional branches predicted
1603system.cpu1.branchPred.condIncorrect 360109 # Number of conditional branches incorrect
1604system.cpu1.branchPred.BTBLookups 3337115 # Number of BTB lookups
1605system.cpu1.branchPred.BTBHits 2452438 # Number of BTB hits
1606system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1607system.cpu1.branchPred.BTBHitPct 73.489766 # BTB Hit Percentage
1608system.cpu1.branchPred.usedRAS 1042883 # Number of times the RAS was used to get a target.
1609system.cpu1.branchPred.RASInCorrect 10537 # Number of incorrect RAS predictions.
1610system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1611system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1612system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1613system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1614system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1615system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1616system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1617system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1631system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1632system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1633system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1634system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1635system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1636system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1637system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1638system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1639system.cpu1.dtb.walker.walks 24322 # Table walker walks requested
1640system.cpu1.dtb.walker.walksShort 24322 # Table walker walks initiated with short descriptors
1641system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11233 # Level at which table walker walks with short descriptors terminate
1642system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5990 # Level at which table walker walks with short descriptors terminate
1643system.cpu1.dtb.walker.walksSquashedBefore 7099 # Table walks squashed before starting
1644system.cpu1.dtb.walker.walkWaitTime::samples 17223 # Table walker wait (enqueue to first request) latency
1645system.cpu1.dtb.walker.walkWaitTime::mean 438.425361 # Table walker wait (enqueue to first request) latency
1646system.cpu1.dtb.walker.walkWaitTime::stdev 2740.461547 # Table walker wait (enqueue to first request) latency
1647system.cpu1.dtb.walker.walkWaitTime::0-4095 16689 96.90% 96.90% # Table walker wait (enqueue to first request) latency
1648system.cpu1.dtb.walker.walkWaitTime::4096-8191 124 0.72% 97.62% # Table walker wait (enqueue to first request) latency
1649system.cpu1.dtb.walker.walkWaitTime::8192-12287 219 1.27% 98.89% # Table walker wait (enqueue to first request) latency
1650system.cpu1.dtb.walker.walkWaitTime::12288-16383 86 0.50% 99.39% # Table walker wait (enqueue to first request) latency
1651system.cpu1.dtb.walker.walkWaitTime::16384-20479 20 0.12% 99.51% # Table walker wait (enqueue to first request) latency
1652system.cpu1.dtb.walker.walkWaitTime::20480-24575 13 0.08% 99.58% # Table walker wait (enqueue to first request) latency
1653system.cpu1.dtb.walker.walkWaitTime::24576-28671 39 0.23% 99.81% # Table walker wait (enqueue to first request) latency
1654system.cpu1.dtb.walker.walkWaitTime::28672-32767 13 0.08% 99.88% # Table walker wait (enqueue to first request) latency
1655system.cpu1.dtb.walker.walkWaitTime::32768-36863 16 0.09% 99.98% # Table walker wait (enqueue to first request) latency
1656system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
1657system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
1658system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency
1659system.cpu1.dtb.walker.walkWaitTime::total 17223 # Table walker wait (enqueue to first request) latency
1660system.cpu1.dtb.walker.walkCompletionTime::samples 5609 # Table walker service (enqueue to completion) latency
1661system.cpu1.dtb.walker.walkCompletionTime::mean 10144.232484 # Table walker service (enqueue to completion) latency
1662system.cpu1.dtb.walker.walkCompletionTime::gmean 8674.966878 # Table walker service (enqueue to completion) latency
1663system.cpu1.dtb.walker.walkCompletionTime::stdev 6379.427582 # Table walker service (enqueue to completion) latency
1664system.cpu1.dtb.walker.walkCompletionTime::0-8191 2437 43.45% 43.45% # Table walker service (enqueue to completion) latency
1665system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2571 45.84% 89.29% # Table walker service (enqueue to completion) latency
1666system.cpu1.dtb.walker.walkCompletionTime::16384-24575 453 8.08% 97.36% # Table walker service (enqueue to completion) latency
1667system.cpu1.dtb.walker.walkCompletionTime::24576-32767 115 2.05% 99.41% # Table walker service (enqueue to completion) latency
1668system.cpu1.dtb.walker.walkCompletionTime::32768-40959 3 0.05% 99.47% # Table walker service (enqueue to completion) latency
1669system.cpu1.dtb.walker.walkCompletionTime::40960-49151 25 0.45% 99.91% # Table walker service (enqueue to completion) latency
1670system.cpu1.dtb.walker.walkCompletionTime::90112-98303 4 0.07% 99.98% # Table walker service (enqueue to completion) latency
1671system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
1672system.cpu1.dtb.walker.walkCompletionTime::total 5609 # Table walker service (enqueue to completion) latency
1673system.cpu1.dtb.walker.walksPending::samples 69613371380 # Table walker pending requests distribution
1674system.cpu1.dtb.walker.walksPending::mean 0.373428 # Table walker pending requests distribution
1675system.cpu1.dtb.walker.walksPending::stdev 0.487046 # Table walker pending requests distribution
1676system.cpu1.dtb.walker.walksPending::0 43658416792 62.72% 62.72% # Table walker pending requests distribution
1677system.cpu1.dtb.walker.walksPending::1 25935559588 37.26% 99.97% # Table walker pending requests distribution
1678system.cpu1.dtb.walker.walksPending::2 12091000 0.02% 99.99% # Table walker pending requests distribution
1679system.cpu1.dtb.walker.walksPending::3 3523500 0.01% 99.99% # Table walker pending requests distribution
1680system.cpu1.dtb.walker.walksPending::4 1046500 0.00% 100.00% # Table walker pending requests distribution
1681system.cpu1.dtb.walker.walksPending::5 593000 0.00% 100.00% # Table walker pending requests distribution
1682system.cpu1.dtb.walker.walksPending::6 908500 0.00% 100.00% # Table walker pending requests distribution
1683system.cpu1.dtb.walker.walksPending::7 323500 0.00% 100.00% # Table walker pending requests distribution
1684system.cpu1.dtb.walker.walksPending::8 151000 0.00% 100.00% # Table walker pending requests distribution
1685system.cpu1.dtb.walker.walksPending::9 143500 0.00% 100.00% # Table walker pending requests distribution
1686system.cpu1.dtb.walker.walksPending::10 80500 0.00% 100.00% # Table walker pending requests distribution
1687system.cpu1.dtb.walker.walksPending::11 88500 0.00% 100.00% # Table walker pending requests distribution
1688system.cpu1.dtb.walker.walksPending::12 153000 0.00% 100.00% # Table walker pending requests distribution
1689system.cpu1.dtb.walker.walksPending::13 38000 0.00% 100.00% # Table walker pending requests distribution
1690system.cpu1.dtb.walker.walksPending::14 28000 0.00% 100.00% # Table walker pending requests distribution
1691system.cpu1.dtb.walker.walksPending::15 226500 0.00% 100.00% # Table walker pending requests distribution
1692system.cpu1.dtb.walker.walksPending::total 69613371380 # Table walker pending requests distribution
1693system.cpu1.dtb.walker.walkPageSizes::4K 1968 73.85% 73.85% # Table walker page sizes translated
1694system.cpu1.dtb.walker.walkPageSizes::1M 697 26.15% 100.00% # Table walker page sizes translated
1695system.cpu1.dtb.walker.walkPageSizes::total 2665 # Table walker page sizes translated
1696system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24322 # Table walker requests started/completed, data/inst
1697system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1698system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24322 # Table walker requests started/completed, data/inst
1699system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2665 # Table walker requests started/completed, data/inst
1700system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1701system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2665 # Table walker requests started/completed, data/inst
1702system.cpu1.dtb.walker.walkRequestOrigin::total 26987 # Table walker requests started/completed, data/inst
1703system.cpu1.dtb.inst_hits 0 # ITB inst hits
1704system.cpu1.dtb.inst_misses 0 # ITB inst misses
1705system.cpu1.dtb.read_hits 5224196 # DTB read hits
1706system.cpu1.dtb.read_misses 21002 # DTB read misses
1707system.cpu1.dtb.write_hits 4300766 # DTB write hits
1708system.cpu1.dtb.write_misses 3320 # DTB write misses
1709system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
1710system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1711system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1712system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1713system.cpu1.dtb.flush_entries 2043 # Number of entries that have been flushed from TLB
1714system.cpu1.dtb.align_faults 67 # Number of TLB faults due to alignment restrictions
1715system.cpu1.dtb.prefetch_faults 616 # Number of TLB faults due to prefetch
1716system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1717system.cpu1.dtb.perms_faults 364 # Number of TLB faults due to permissions restrictions
1718system.cpu1.dtb.read_accesses 5245198 # DTB read accesses
1719system.cpu1.dtb.write_accesses 4304086 # DTB write accesses
1720system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1721system.cpu1.dtb.hits 9524962 # DTB hits
1722system.cpu1.dtb.misses 24322 # DTB misses
1723system.cpu1.dtb.accesses 9549284 # DTB accesses
1724system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1725system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1726system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1727system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1728system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1729system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1730system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1731system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1745system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1746system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1747system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1748system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1749system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1750system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1751system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1752system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1753system.cpu1.itb.walker.walks 6842 # Table walker walks requested
1754system.cpu1.itb.walker.walksShort 6842 # Table walker walks initiated with short descriptors
1755system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4094 # Level at which table walker walks with short descriptors terminate
1756system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2680 # Level at which table walker walks with short descriptors terminate
1757system.cpu1.itb.walker.walksSquashedBefore 68 # Table walks squashed before starting
1758system.cpu1.itb.walker.walkWaitTime::samples 6774 # Table walker wait (enqueue to first request) latency
1759system.cpu1.itb.walker.walkWaitTime::mean 241.142604 # Table walker wait (enqueue to first request) latency
1760system.cpu1.itb.walker.walkWaitTime::stdev 1918.263476 # Table walker wait (enqueue to first request) latency
1761system.cpu1.itb.walker.walkWaitTime::0-4095 6651 98.18% 98.18% # Table walker wait (enqueue to first request) latency
1762system.cpu1.itb.walker.walkWaitTime::4096-8191 49 0.72% 98.91% # Table walker wait (enqueue to first request) latency
1763system.cpu1.itb.walker.walkWaitTime::8192-12287 35 0.52% 99.42% # Table walker wait (enqueue to first request) latency
1764system.cpu1.itb.walker.walkWaitTime::12288-16383 15 0.22% 99.65% # Table walker wait (enqueue to first request) latency
1765system.cpu1.itb.walker.walkWaitTime::16384-20479 5 0.07% 99.72% # Table walker wait (enqueue to first request) latency
1766system.cpu1.itb.walker.walkWaitTime::20480-24575 10 0.15% 99.87% # Table walker wait (enqueue to first request) latency
1767system.cpu1.itb.walker.walkWaitTime::24576-28671 5 0.07% 99.94% # Table walker wait (enqueue to first request) latency
1768system.cpu1.itb.walker.walkWaitTime::28672-32767 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency
1769system.cpu1.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
1770system.cpu1.itb.walker.walkWaitTime::49152-53247 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
1771system.cpu1.itb.walker.walkWaitTime::total 6774 # Table walker wait (enqueue to first request) latency
1772system.cpu1.itb.walker.walkCompletionTime::samples 1233 # Table walker service (enqueue to completion) latency
1773system.cpu1.itb.walker.walkCompletionTime::mean 11141.524736 # Table walker service (enqueue to completion) latency
1774system.cpu1.itb.walker.walkCompletionTime::gmean 9875.363796 # Table walker service (enqueue to completion) latency
1775system.cpu1.itb.walker.walkCompletionTime::stdev 6280.061079 # Table walker service (enqueue to completion) latency
1776system.cpu1.itb.walker.walkCompletionTime::0-8191 357 28.95% 28.95% # Table walker service (enqueue to completion) latency
1777system.cpu1.itb.walker.walkCompletionTime::8192-16383 797 64.64% 93.59% # Table walker service (enqueue to completion) latency
1778system.cpu1.itb.walker.walkCompletionTime::16384-24575 18 1.46% 95.05% # Table walker service (enqueue to completion) latency
1779system.cpu1.itb.walker.walkCompletionTime::24576-32767 48 3.89% 98.95% # Table walker service (enqueue to completion) latency
1780system.cpu1.itb.walker.walkCompletionTime::32768-40959 5 0.41% 99.35% # Table walker service (enqueue to completion) latency
1781system.cpu1.itb.walker.walkCompletionTime::40960-49151 7 0.57% 99.92% # Table walker service (enqueue to completion) latency
1782system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.08% 100.00% # Table walker service (enqueue to completion) latency
1783system.cpu1.itb.walker.walkCompletionTime::total 1233 # Table walker service (enqueue to completion) latency
1784system.cpu1.itb.walker.walksPending::samples 18042065828 # Table walker pending requests distribution
1785system.cpu1.itb.walker.walksPending::mean 0.988332 # Table walker pending requests distribution
1786system.cpu1.itb.walker.walksPending::stdev 0.107619 # Table walker pending requests distribution
1787system.cpu1.itb.walker.walksPending::0 210878764 1.17% 1.17% # Table walker pending requests distribution
1788system.cpu1.itb.walker.walksPending::1 17830879064 98.83% 100.00% # Table walker pending requests distribution
1789system.cpu1.itb.walker.walksPending::2 267500 0.00% 100.00% # Table walker pending requests distribution
1790system.cpu1.itb.walker.walksPending::3 19000 0.00% 100.00% # Table walker pending requests distribution
1791system.cpu1.itb.walker.walksPending::4 21500 0.00% 100.00% # Table walker pending requests distribution
1792system.cpu1.itb.walker.walksPending::total 18042065828 # Table walker pending requests distribution
1793system.cpu1.itb.walker.walkPageSizes::4K 995 85.41% 85.41% # Table walker page sizes translated
1794system.cpu1.itb.walker.walkPageSizes::1M 170 14.59% 100.00% # Table walker page sizes translated
1795system.cpu1.itb.walker.walkPageSizes::total 1165 # Table walker page sizes translated
1796system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1797system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6842 # Table walker requests started/completed, data/inst
1798system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6842 # Table walker requests started/completed, data/inst
1799system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1800system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1165 # Table walker requests started/completed, data/inst
1801system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1165 # Table walker requests started/completed, data/inst
1802system.cpu1.itb.walker.walkRequestOrigin::total 8007 # Table walker requests started/completed, data/inst
1803system.cpu1.itb.inst_hits 10488200 # ITB inst hits
1804system.cpu1.itb.inst_misses 6842 # ITB inst misses
1805system.cpu1.itb.read_hits 0 # DTB read hits
1806system.cpu1.itb.read_misses 0 # DTB read misses
1807system.cpu1.itb.write_hits 0 # DTB write hits
1808system.cpu1.itb.write_misses 0 # DTB write misses
1809system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
1810system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1811system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1812system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1813system.cpu1.itb.flush_entries 1196 # Number of entries that have been flushed from TLB
1814system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1815system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1816system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1817system.cpu1.itb.perms_faults 530 # Number of TLB faults due to permissions restrictions
1818system.cpu1.itb.read_accesses 0 # DTB read accesses
1819system.cpu1.itb.write_accesses 0 # DTB write accesses
1820system.cpu1.itb.inst_accesses 10495042 # ITB inst accesses
1821system.cpu1.itb.hits 10488200 # DTB hits
1822system.cpu1.itb.misses 6842 # DTB misses
1823system.cpu1.itb.accesses 10495042 # DTB accesses
1824system.cpu1.numCycles 43023242 # number of cpu cycles simulated
1825system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1826system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1827system.cpu1.fetch.icacheStallCycles 9545006 # Number of cycles fetch is stalled on an Icache miss
1828system.cpu1.fetch.Insts 31536140 # Number of instructions fetch has processed
1829system.cpu1.fetch.Branches 6152669 # Number of branches that fetch encountered
1830system.cpu1.fetch.predictedBranches 3495321 # Number of branches that fetch has predicted taken
1831system.cpu1.fetch.Cycles 31308638 # Number of cycles fetch has run and was not squashing or blocked
1832system.cpu1.fetch.SquashCycles 988880 # Number of cycles fetch has spent squashing
1833system.cpu1.fetch.TlbCycles 91081 # Number of cycles fetch has spent waiting for tlb
1834system.cpu1.fetch.MiscStallCycles 40105 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1835system.cpu1.fetch.PendingTrapStallCycles 214294 # Number of stall cycles due to pending traps
1836system.cpu1.fetch.PendingQuiesceStallCycles 338691 # Number of stall cycles due to pending quiesce instructions
1837system.cpu1.fetch.IcacheWaitRetryStallCycles 30719 # Number of stall cycles due to full MSHR
1838system.cpu1.fetch.CacheLines 10487595 # Number of cache lines fetched
1839system.cpu1.fetch.IcacheSquashes 131638 # Number of outstanding Icache misses that were squashed
1840system.cpu1.fetch.ItlbSquashes 2429 # Number of outstanding ITLB misses that were squashed
1841system.cpu1.fetch.rateDist::samples 42062974 # Number of instructions fetched each cycle (Total)
1842system.cpu1.fetch.rateDist::mean 0.911933 # Number of instructions fetched each cycle (Total)
1843system.cpu1.fetch.rateDist::stdev 1.224898 # Number of instructions fetched each cycle (Total)
1844system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1845system.cpu1.fetch.rateDist::0 24350235 57.89% 57.89% # Number of instructions fetched each cycle (Total)
1846system.cpu1.fetch.rateDist::1 6287044 14.95% 72.84% # Number of instructions fetched each cycle (Total)
1847system.cpu1.fetch.rateDist::2 2205515 5.24% 78.08% # Number of instructions fetched each cycle (Total)
1848system.cpu1.fetch.rateDist::3 9220180 21.92% 100.00% # Number of instructions fetched each cycle (Total)
1849system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1850system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1851system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
1852system.cpu1.fetch.rateDist::total 42062974 # Number of instructions fetched each cycle (Total)
1853system.cpu1.fetch.branchRate 0.143008 # Number of branch fetches per cycle
1854system.cpu1.fetch.rate 0.733002 # Number of inst fetches per cycle
1855system.cpu1.decode.IdleCycles 8267663 # Number of cycles decode is idle
1856system.cpu1.decode.BlockedCycles 20626897 # Number of cycles decode is blocked
1857system.cpu1.decode.RunCycles 11490517 # Number of cycles decode is running
1858system.cpu1.decode.UnblockCycles 1337775 # Number of cycles decode is unblocking
1859system.cpu1.decode.SquashCycles 340122 # Number of cycles decode is squashing
1860system.cpu1.decode.BranchResolved 874675 # Number of times decode resolved a branch
1861system.cpu1.decode.BranchMispred 157334 # Number of times decode detected a branch misprediction
1862system.cpu1.decode.DecodedInsts 30100708 # Number of instructions handled by decode
1863system.cpu1.decode.SquashedInsts 1379443 # Number of squashed instructions handled by decode
1864system.cpu1.rename.SquashCycles 340122 # Number of cycles rename is squashing
1865system.cpu1.rename.IdleCycles 10041900 # Number of cycles rename is idle
1866system.cpu1.rename.BlockCycles 2603998 # Number of cycles rename is blocking
1867system.cpu1.rename.serializeStallCycles 14921640 # count of cycles rename stalled for serializing inst
1868system.cpu1.rename.RunCycles 11019721 # Number of cycles rename is running
1869system.cpu1.rename.UnblockCycles 3135593 # Number of cycles rename is unblocking
1870system.cpu1.rename.RenamedInsts 28621166 # Number of instructions processed by rename
1871system.cpu1.rename.SquashedInsts 281517 # Number of squashed instructions processed by rename
1872system.cpu1.rename.ROBFullEvents 330506 # Number of times rename has blocked due to ROB full
1873system.cpu1.rename.IQFullEvents 50454 # Number of times rename has blocked due to IQ full
1874system.cpu1.rename.LQFullEvents 20125 # Number of times rename has blocked due to LQ full
1875system.cpu1.rename.SQFullEvents 1923436 # Number of times rename has blocked due to SQ full
1876system.cpu1.rename.RenamedOperands 29030542 # Number of destination operands rename has renamed
1877system.cpu1.rename.RenameLookups 132294985 # Number of register rename lookups that rename has made
1878system.cpu1.rename.int_rename_lookups 32813170 # Number of integer rename lookups
1879system.cpu1.rename.fp_rename_lookups 1657 # Number of floating rename lookups
1880system.cpu1.rename.CommittedMaps 25609862 # Number of HB maps that are committed
1881system.cpu1.rename.UndoneMaps 3420680 # Number of HB maps that are undone due to squashing
1882system.cpu1.rename.serializingInsts 453393 # count of serializing insts renamed
1883system.cpu1.rename.tempSerializingInsts 375590 # count of temporary serializing insts renamed
1884system.cpu1.rename.skidInsts 3438293 # count of insts added to the skid buffer
1885system.cpu1.memDep0.insertedLoads 5562789 # Number of loads inserted to the mem dependence unit.
1886system.cpu1.memDep0.insertedStores 4719499 # Number of stores inserted to the mem dependence unit.
1887system.cpu1.memDep0.conflictingLoads 701110 # Number of conflicting loads.
1888system.cpu1.memDep0.conflictingStores 705314 # Number of conflicting stores.
1889system.cpu1.iq.iqInstsAdded 27634808 # Number of instructions added to the IQ (excludes non-spec)
1890system.cpu1.iq.iqNonSpecInstsAdded 626900 # Number of non-speculative instructions added to the IQ
1891system.cpu1.iq.iqInstsIssued 27144127 # Number of instructions issued
1892system.cpu1.iq.iqSquashedInstsIssued 143701 # Number of squashed instructions issued
1893system.cpu1.iq.iqSquashedInstsExamined 2955966 # Number of squashed instructions iterated over during squash; mainly for profiling
1894system.cpu1.iq.iqSquashedOperandsExamined 6891737 # Number of squashed operands that are examined and possibly removed from graph
1895system.cpu1.iq.iqSquashedNonSpecRemoved 53840 # Number of squashed non-spec instructions that were removed
1896system.cpu1.iq.issued_per_cycle::samples 42062974 # Number of insts issued each cycle
1897system.cpu1.iq.issued_per_cycle::mean 0.645321 # Number of insts issued each cycle
1898system.cpu1.iq.issued_per_cycle::stdev 0.965357 # Number of insts issued each cycle
1899system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1900system.cpu1.iq.issued_per_cycle::0 26343154 62.63% 62.63% # Number of insts issued each cycle
1901system.cpu1.iq.issued_per_cycle::1 7337268 17.44% 80.07% # Number of insts issued each cycle
1902system.cpu1.iq.issued_per_cycle::2 5660550 13.46% 93.53% # Number of insts issued each cycle
1903system.cpu1.iq.issued_per_cycle::3 2402263 5.71% 99.24% # Number of insts issued each cycle
1904system.cpu1.iq.issued_per_cycle::4 319725 0.76% 100.00% # Number of insts issued each cycle
1905system.cpu1.iq.issued_per_cycle::5 14 0.00% 100.00% # Number of insts issued each cycle
1906system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
1907system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
1908system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
1909system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1910system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1911system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
1912system.cpu1.iq.issued_per_cycle::total 42062974 # Number of insts issued each cycle
1913system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1914system.cpu1.iq.fu_full::IntAlu 1996325 32.40% 32.40% # attempts to use FU when none available
1915system.cpu1.iq.fu_full::IntMult 609 0.01% 32.40% # attempts to use FU when none available
1916system.cpu1.iq.fu_full::IntDiv 0 0.00% 32.40% # attempts to use FU when none available
1917system.cpu1.iq.fu_full::FloatAdd 0 0.00% 32.40% # attempts to use FU when none available
1918system.cpu1.iq.fu_full::FloatCmp 0 0.00% 32.40% # attempts to use FU when none available
1919system.cpu1.iq.fu_full::FloatCvt 0 0.00% 32.40% # attempts to use FU when none available
1920system.cpu1.iq.fu_full::FloatMult 0 0.00% 32.40% # attempts to use FU when none available
1921system.cpu1.iq.fu_full::FloatDiv 0 0.00% 32.40% # attempts to use FU when none available
1922system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 32.40% # attempts to use FU when none available
1923system.cpu1.iq.fu_full::SimdAdd 0 0.00% 32.40% # attempts to use FU when none available
1924system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 32.40% # attempts to use FU when none available
1925system.cpu1.iq.fu_full::SimdAlu 0 0.00% 32.40% # attempts to use FU when none available
1926system.cpu1.iq.fu_full::SimdCmp 0 0.00% 32.40% # attempts to use FU when none available
1927system.cpu1.iq.fu_full::SimdCvt 0 0.00% 32.40% # attempts to use FU when none available
1928system.cpu1.iq.fu_full::SimdMisc 0 0.00% 32.40% # attempts to use FU when none available
1929system.cpu1.iq.fu_full::SimdMult 0 0.00% 32.40% # attempts to use FU when none available
1930system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 32.40% # attempts to use FU when none available
1931system.cpu1.iq.fu_full::SimdShift 0 0.00% 32.40% # attempts to use FU when none available
1932system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 32.40% # attempts to use FU when none available
1933system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 32.40% # attempts to use FU when none available
1934system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 32.40% # attempts to use FU when none available
1935system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 32.40% # attempts to use FU when none available
1936system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 32.40% # attempts to use FU when none available
1937system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 32.40% # attempts to use FU when none available
1938system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 32.40% # attempts to use FU when none available
1939system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 32.40% # attempts to use FU when none available
1940system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 32.40% # attempts to use FU when none available
1941system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.40% # attempts to use FU when none available
1942system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 32.40% # attempts to use FU when none available
1943system.cpu1.iq.fu_full::MemRead 1885144 30.59% 63.00% # attempts to use FU when none available
1944system.cpu1.iq.fu_full::MemWrite 2280359 37.00% 100.00% # attempts to use FU when none available
1945system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1946system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1947system.cpu1.iq.FU_type_0::No_OpClass 67 0.00% 0.00% # Type of FU issued
1948system.cpu1.iq.FU_type_0::IntAlu 17084879 62.94% 62.94% # Type of FU issued
1949system.cpu1.iq.FU_type_0::IntMult 34880 0.13% 63.07% # Type of FU issued
1950system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 63.07% # Type of FU issued
1951system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 63.07% # Type of FU issued
1952system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 63.07% # Type of FU issued
1953system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 63.07% # Type of FU issued
1954system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 63.07% # Type of FU issued
1955system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 63.07% # Type of FU issued
1956system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 63.07% # Type of FU issued
1957system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 63.07% # Type of FU issued
1958system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 63.07% # Type of FU issued
1959system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 63.07% # Type of FU issued
1960system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 63.07% # Type of FU issued
1961system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 63.07% # Type of FU issued
1962system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 63.07% # Type of FU issued
1963system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 63.07% # Type of FU issued
1964system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 63.07% # Type of FU issued
1965system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 63.07% # Type of FU issued
1966system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.07% # Type of FU issued
1967system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 63.07% # Type of FU issued
1968system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.07% # Type of FU issued
1969system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.07% # Type of FU issued
1970system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.07% # Type of FU issued
1971system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.07% # Type of FU issued
1972system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.07% # Type of FU issued
1973system.cpu1.iq.FU_type_0::SimdFloatMisc 4083 0.02% 63.09% # Type of FU issued
1974system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 63.09% # Type of FU issued
1975system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.09% # Type of FU issued
1976system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.09% # Type of FU issued
1977system.cpu1.iq.FU_type_0::MemRead 5473288 20.16% 83.25% # Type of FU issued
1978system.cpu1.iq.FU_type_0::MemWrite 4546930 16.75% 100.00% # Type of FU issued
1979system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1980system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1981system.cpu1.iq.FU_type_0::total 27144127 # Type of FU issued
1982system.cpu1.iq.rate 0.630918 # Inst issue rate
1983system.cpu1.iq.fu_busy_cnt 6162437 # FU busy when requested
1984system.cpu1.iq.fu_busy_rate 0.227027 # FU busy rate (busy events/executed inst)
1985system.cpu1.iq.int_inst_queue_reads 102651570 # Number of integer instruction queue reads
1986system.cpu1.iq.int_inst_queue_writes 31226183 # Number of integer instruction queue writes
1987system.cpu1.iq.int_inst_queue_wakeup_accesses 26510239 # Number of integer instruction queue wakeup accesses
1988system.cpu1.iq.fp_inst_queue_reads 5796 # Number of floating instruction queue reads
1989system.cpu1.iq.fp_inst_queue_writes 2046 # Number of floating instruction queue writes
1990system.cpu1.iq.fp_inst_queue_wakeup_accesses 1784 # Number of floating instruction queue wakeup accesses
1991system.cpu1.iq.int_alu_accesses 33302783 # Number of integer alu accesses
1992system.cpu1.iq.fp_alu_accesses 3714 # Number of floating point alu accesses
1993system.cpu1.iew.lsq.thread0.forwLoads 106694 # Number of loads that had data forwarded from stores
1994system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1995system.cpu1.iew.lsq.thread0.squashedLoads 599497 # Number of loads squashed
1996system.cpu1.iew.lsq.thread0.ignoredResponses 782 # Number of memory responses ignored because the instruction is squashed
1997system.cpu1.iew.lsq.thread0.memOrderViolation 10594 # Number of memory ordering violations
1998system.cpu1.iew.lsq.thread0.squashedStores 400513 # Number of stores squashed
1999system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2000system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2001system.cpu1.iew.lsq.thread0.rescheduledLoads 46755 # Number of loads that were rescheduled
2002system.cpu1.iew.lsq.thread0.cacheBlocked 99859 # Number of times an access to memory failed due to the cache being blocked
2003system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2004system.cpu1.iew.iewSquashCycles 340122 # Number of cycles IEW is squashing
2005system.cpu1.iew.iewBlockCycles 663664 # Number of cycles IEW is blocking
2006system.cpu1.iew.iewUnblockCycles 112730 # Number of cycles IEW is unblocking
2007system.cpu1.iew.iewDispatchedInsts 28316728 # Number of instructions dispatched to IQ
2008system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2009system.cpu1.iew.iewDispLoadInsts 5562789 # Number of dispatched load instructions
2010system.cpu1.iew.iewDispStoreInsts 4719499 # Number of dispatched store instructions
2011system.cpu1.iew.iewDispNonSpecInsts 329074 # Number of dispatched non-speculative instructions
2012system.cpu1.iew.iewIQFullEvents 12650 # Number of times the IQ has become full, causing a stall
2013system.cpu1.iew.iewLSQFullEvents 90576 # Number of times the LSQ has become full, causing a stall
2014system.cpu1.iew.memOrderViolationEvents 10594 # Number of memory order violations
2015system.cpu1.iew.predictedTakenIncorrect 71921 # Number of branches that were predicted taken incorrectly
2016system.cpu1.iew.predictedNotTakenIncorrect 150578 # Number of branches that were predicted not taken incorrectly
2017system.cpu1.iew.branchMispredicts 222499 # Number of branch mispredicts detected at execute
2018system.cpu1.iew.iewExecutedInsts 26808358 # Number of executed instructions
2019system.cpu1.iew.iewExecLoadInsts 5342958 # Number of load instructions executed
2020system.cpu1.iew.iewExecSquashedInsts 311471 # Number of squashed instructions skipped in execute
2021system.cpu1.iew.exec_swp 0 # number of swp insts executed
2022system.cpu1.iew.exec_nop 55020 # number of nop insts executed
2023system.cpu1.iew.exec_refs 9813397 # number of memory reference insts executed
2024system.cpu1.iew.exec_branches 4108906 # Number of branches executed
2025system.cpu1.iew.exec_stores 4470439 # Number of stores executed
2026system.cpu1.iew.exec_rate 0.623113 # Inst execution rate
2027system.cpu1.iew.wb_sent 26632744 # cumulative count of insts sent to commit
2028system.cpu1.iew.wb_count 26512023 # cumulative count of insts written-back
2029system.cpu1.iew.wb_producers 13415515 # num instructions producing a value
2030system.cpu1.iew.wb_consumers 21195279 # num instructions consuming a value
2031system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
2032system.cpu1.iew.wb_rate 0.616226 # insts written-back per cycle
2033system.cpu1.iew.wb_fanout 0.632948 # average fanout of values written-back
2034system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
2035system.cpu1.commit.commitSquashedInsts 2659330 # The number of squashed insts skipped by commit
2036system.cpu1.commit.commitNonSpecStalls 573060 # The number of times commit has been forced to stall to communicate backwards
2037system.cpu1.commit.branchMispredicts 205791 # The number of times a branch was mispredicted
2038system.cpu1.commit.committed_per_cycle::samples 41503303 # Number of insts commited each cycle
2039system.cpu1.commit.committed_per_cycle::mean 0.610529 # Number of insts commited each cycle
2040system.cpu1.commit.committed_per_cycle::stdev 1.356545 # Number of insts commited each cycle
2041system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2042system.cpu1.commit.committed_per_cycle::0 29410485 70.86% 70.86% # Number of insts commited each cycle
2043system.cpu1.commit.committed_per_cycle::1 7042051 16.97% 87.83% # Number of insts commited each cycle
2044system.cpu1.commit.committed_per_cycle::2 2116509 5.10% 92.93% # Number of insts commited each cycle
2045system.cpu1.commit.committed_per_cycle::3 864843 2.08% 95.01% # Number of insts commited each cycle
2046system.cpu1.commit.committed_per_cycle::4 769424 1.85% 96.87% # Number of insts commited each cycle
2047system.cpu1.commit.committed_per_cycle::5 435639 1.05% 97.92% # Number of insts commited each cycle
2048system.cpu1.commit.committed_per_cycle::6 276731 0.67% 98.58% # Number of insts commited each cycle
2049system.cpu1.commit.committed_per_cycle::7 147889 0.36% 98.94% # Number of insts commited each cycle
2050system.cpu1.commit.committed_per_cycle::8 439732 1.06% 100.00% # Number of insts commited each cycle
2051system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2052system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2053system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2054system.cpu1.commit.committed_per_cycle::total 41503303 # Number of insts commited each cycle
2055system.cpu1.commit.committedInsts 20778200 # Number of instructions committed
2056system.cpu1.commit.committedOps 25338954 # Number of ops (including micro ops) committed
2057system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2058system.cpu1.commit.refs 9282278 # Number of memory references committed
2059system.cpu1.commit.loads 4963292 # Number of loads committed
2060system.cpu1.commit.membars 229830 # Number of memory barriers committed
2061system.cpu1.commit.branches 3902679 # Number of branches committed
2062system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions.
2063system.cpu1.commit.int_insts 22267919 # Number of committed integer instructions.
2064system.cpu1.commit.function_calls 549742 # Number of function calls committed.
2065system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2066system.cpu1.commit.op_class_0::IntAlu 16018762 63.22% 63.22% # Class of committed instruction
2067system.cpu1.commit.op_class_0::IntMult 33831 0.13% 63.35% # Class of committed instruction
2068system.cpu1.commit.op_class_0::IntDiv 0 0.00% 63.35% # Class of committed instruction
2069system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 63.35% # Class of committed instruction
2070system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 63.35% # Class of committed instruction
2071system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 63.35% # Class of committed instruction
2072system.cpu1.commit.op_class_0::FloatMult 0 0.00% 63.35% # Class of committed instruction
2073system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 63.35% # Class of committed instruction
2074system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 63.35% # Class of committed instruction
2075system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 63.35% # Class of committed instruction
2076system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 63.35% # Class of committed instruction
2077system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 63.35% # Class of committed instruction
2078system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 63.35% # Class of committed instruction
2079system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 63.35% # Class of committed instruction
2080system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 63.35% # Class of committed instruction
2081system.cpu1.commit.op_class_0::SimdMult 0 0.00% 63.35% # Class of committed instruction
2082system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 63.35% # Class of committed instruction
2083system.cpu1.commit.op_class_0::SimdShift 0 0.00% 63.35% # Class of committed instruction
2084system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 63.35% # Class of committed instruction
2085system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 63.35% # Class of committed instruction
2086system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 63.35% # Class of committed instruction
2087system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 63.35% # Class of committed instruction
2088system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 63.35% # Class of committed instruction
2089system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 63.35% # Class of committed instruction
2090system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 63.35% # Class of committed instruction
2091system.cpu1.commit.op_class_0::SimdFloatMisc 4083 0.02% 63.37% # Class of committed instruction
2092system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 63.37% # Class of committed instruction
2093system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.37% # Class of committed instruction
2094system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.37% # Class of committed instruction
2095system.cpu1.commit.op_class_0::MemRead 4963292 19.59% 82.96% # Class of committed instruction
2096system.cpu1.commit.op_class_0::MemWrite 4318986 17.04% 100.00% # Class of committed instruction
2097system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2098system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2099system.cpu1.commit.op_class_0::total 25338954 # Class of committed instruction
2100system.cpu1.commit.bw_lim_events 439732 # number cycles where commit BW limit reached
2101system.cpu1.rob.rob_reads 67911551 # The number of ROB reads
2102system.cpu1.rob.rob_writes 56552827 # The number of ROB writes
2103system.cpu1.timesIdled 67532 # Number of times that the entire CPU went into an idle state and unscheduled itself
2104system.cpu1.idleCycles 960268 # Total number of cycles that the CPU has spent unscheduled due to idling
2105system.cpu1.quiesceCycles 5207215501 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2106system.cpu1.committedInsts 20744987 # Number of Instructions Simulated
2107system.cpu1.committedOps 25305741 # Number of Ops (including micro ops) Simulated
2108system.cpu1.cpi 2.073910 # CPI: Cycles Per Instruction
2109system.cpu1.cpi_total 2.073910 # CPI: Total CPI of All Threads
2110system.cpu1.ipc 0.482181 # IPC: Instructions Per Cycle
2111system.cpu1.ipc_total 0.482181 # IPC: Total IPC of All Threads
2112system.cpu1.int_regfile_reads 29917814 # number of integer regfile reads
2113system.cpu1.int_regfile_writes 16874088 # number of integer regfile writes
2114system.cpu1.fp_regfile_reads 1382 # number of floating regfile reads
2115system.cpu1.fp_regfile_writes 516 # number of floating regfile writes
2116system.cpu1.cc_regfile_reads 95785070 # number of cc regfile reads
2117system.cpu1.cc_regfile_writes 9455596 # number of cc regfile writes
2118system.cpu1.misc_regfile_reads 60806398 # number of misc regfile reads
2119system.cpu1.misc_regfile_writes 422782 # number of misc regfile writes
2120system.cpu1.dcache.tags.replacements 228231 # number of replacements
2121system.cpu1.dcache.tags.tagsinuse 478.409113 # Cycle average of tags in use
2122system.cpu1.dcache.tags.total_refs 8403253 # Total number of references to valid blocks.
2123system.cpu1.dcache.tags.sampled_refs 228545 # Sample count of references to valid blocks.
2124system.cpu1.dcache.tags.avg_refs 36.768483 # Average number of references to valid blocks.
2125system.cpu1.dcache.tags.warmup_cycle 103444079500 # Cycle when the warmup percentage was hit.
2126system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.409113 # Average occupied blocks per requestor
2127system.cpu1.dcache.tags.occ_percent::cpu1.data 0.934393 # Average percentage of cache occupancy
2128system.cpu1.dcache.tags.occ_percent::total 0.934393 # Average percentage of cache occupancy
2129system.cpu1.dcache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id
2130system.cpu1.dcache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id
2131system.cpu1.dcache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id
2132system.cpu1.dcache.tags.occ_task_id_percent::1024 0.613281 # Percentage of cache occupancy per task id
2133system.cpu1.dcache.tags.tag_accesses 18586968 # Number of tag accesses
2134system.cpu1.dcache.tags.data_accesses 18586968 # Number of data accesses
2135system.cpu1.dcache.ReadReq_hits::cpu1.data 4548259 # number of ReadReq hits
2136system.cpu1.dcache.ReadReq_hits::total 4548259 # number of ReadReq hits
2137system.cpu1.dcache.WriteReq_hits::cpu1.data 3563356 # number of WriteReq hits
2138system.cpu1.dcache.WriteReq_hits::total 3563356 # number of WriteReq hits
2139system.cpu1.dcache.SoftPFReq_hits::cpu1.data 63759 # number of SoftPFReq hits
2140system.cpu1.dcache.SoftPFReq_hits::total 63759 # number of SoftPFReq hits
2141system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87271 # number of LoadLockedReq hits
2142system.cpu1.dcache.LoadLockedReq_hits::total 87271 # number of LoadLockedReq hits
2143system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79516 # number of StoreCondReq hits
2144system.cpu1.dcache.StoreCondReq_hits::total 79516 # number of StoreCondReq hits
2145system.cpu1.dcache.demand_hits::cpu1.data 8111615 # number of demand (read+write) hits
2146system.cpu1.dcache.demand_hits::total 8111615 # number of demand (read+write) hits
2147system.cpu1.dcache.overall_hits::cpu1.data 8175374 # number of overall hits
2148system.cpu1.dcache.overall_hits::total 8175374 # number of overall hits
2149system.cpu1.dcache.ReadReq_misses::cpu1.data 254647 # number of ReadReq misses
2150system.cpu1.dcache.ReadReq_misses::total 254647 # number of ReadReq misses
2151system.cpu1.dcache.WriteReq_misses::cpu1.data 480567 # number of WriteReq misses
2152system.cpu1.dcache.WriteReq_misses::total 480567 # number of WriteReq misses
2153system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35928 # number of SoftPFReq misses
2154system.cpu1.dcache.SoftPFReq_misses::total 35928 # number of SoftPFReq misses
2155system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19211 # number of LoadLockedReq misses
2156system.cpu1.dcache.LoadLockedReq_misses::total 19211 # number of LoadLockedReq misses
2157system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23462 # number of StoreCondReq misses
2158system.cpu1.dcache.StoreCondReq_misses::total 23462 # number of StoreCondReq misses
2159system.cpu1.dcache.demand_misses::cpu1.data 735214 # number of demand (read+write) misses
2160system.cpu1.dcache.demand_misses::total 735214 # number of demand (read+write) misses
2161system.cpu1.dcache.overall_misses::cpu1.data 771142 # number of overall misses
2162system.cpu1.dcache.overall_misses::total 771142 # number of overall misses
2163system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4017153000 # number of ReadReq miss cycles
2164system.cpu1.dcache.ReadReq_miss_latency::total 4017153000 # number of ReadReq miss cycles
2165system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11025282924 # number of WriteReq miss cycles
2166system.cpu1.dcache.WriteReq_miss_latency::total 11025282924 # number of WriteReq miss cycles
2167system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 376163500 # number of LoadLockedReq miss cycles
2168system.cpu1.dcache.LoadLockedReq_miss_latency::total 376163500 # number of LoadLockedReq miss cycles
2169system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 545526500 # number of StoreCondReq miss cycles
2170system.cpu1.dcache.StoreCondReq_miss_latency::total 545526500 # number of StoreCondReq miss cycles
2171system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 528500 # number of StoreCondFailReq miss cycles
2172system.cpu1.dcache.StoreCondFailReq_miss_latency::total 528500 # number of StoreCondFailReq miss cycles
2173system.cpu1.dcache.demand_miss_latency::cpu1.data 15042435924 # number of demand (read+write) miss cycles
2174system.cpu1.dcache.demand_miss_latency::total 15042435924 # number of demand (read+write) miss cycles
2175system.cpu1.dcache.overall_miss_latency::cpu1.data 15042435924 # number of overall miss cycles
2176system.cpu1.dcache.overall_miss_latency::total 15042435924 # number of overall miss cycles
2177system.cpu1.dcache.ReadReq_accesses::cpu1.data 4802906 # number of ReadReq accesses(hits+misses)
2178system.cpu1.dcache.ReadReq_accesses::total 4802906 # number of ReadReq accesses(hits+misses)
2179system.cpu1.dcache.WriteReq_accesses::cpu1.data 4043923 # number of WriteReq accesses(hits+misses)
2180system.cpu1.dcache.WriteReq_accesses::total 4043923 # number of WriteReq accesses(hits+misses)
2181system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 99687 # number of SoftPFReq accesses(hits+misses)
2182system.cpu1.dcache.SoftPFReq_accesses::total 99687 # number of SoftPFReq accesses(hits+misses)
2183system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 106482 # number of LoadLockedReq accesses(hits+misses)
2184system.cpu1.dcache.LoadLockedReq_accesses::total 106482 # number of LoadLockedReq accesses(hits+misses)
2185system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102978 # number of StoreCondReq accesses(hits+misses)
2186system.cpu1.dcache.StoreCondReq_accesses::total 102978 # number of StoreCondReq accesses(hits+misses)
2187system.cpu1.dcache.demand_accesses::cpu1.data 8846829 # number of demand (read+write) accesses
2188system.cpu1.dcache.demand_accesses::total 8846829 # number of demand (read+write) accesses
2189system.cpu1.dcache.overall_accesses::cpu1.data 8946516 # number of overall (read+write) accesses
2190system.cpu1.dcache.overall_accesses::total 8946516 # number of overall (read+write) accesses
2191system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.053019 # miss rate for ReadReq accesses
2192system.cpu1.dcache.ReadReq_miss_rate::total 0.053019 # miss rate for ReadReq accesses
2193system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.118837 # miss rate for WriteReq accesses
2194system.cpu1.dcache.WriteReq_miss_rate::total 0.118837 # miss rate for WriteReq accesses
2195system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.360408 # miss rate for SoftPFReq accesses
2196system.cpu1.dcache.SoftPFReq_miss_rate::total 0.360408 # miss rate for SoftPFReq accesses
2197system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.180415 # miss rate for LoadLockedReq accesses
2198system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.180415 # miss rate for LoadLockedReq accesses
2199system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.227835 # miss rate for StoreCondReq accesses
2200system.cpu1.dcache.StoreCondReq_miss_rate::total 0.227835 # miss rate for StoreCondReq accesses
2201system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083105 # miss rate for demand accesses
2202system.cpu1.dcache.demand_miss_rate::total 0.083105 # miss rate for demand accesses
2203system.cpu1.dcache.overall_miss_rate::cpu1.data 0.086195 # miss rate for overall accesses
2204system.cpu1.dcache.overall_miss_rate::total 0.086195 # miss rate for overall accesses
2205system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15775.379250 # average ReadReq miss latency
2206system.cpu1.dcache.ReadReq_avg_miss_latency::total 15775.379250 # average ReadReq miss latency
2207system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22942.238905 # average WriteReq miss latency
2208system.cpu1.dcache.WriteReq_avg_miss_latency::total 22942.238905 # average WriteReq miss latency
2209system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19580.630889 # average LoadLockedReq miss latency
2210system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19580.630889 # average LoadLockedReq miss latency
2211system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23251.491774 # average StoreCondReq miss latency
2212system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23251.491774 # average StoreCondReq miss latency
2213system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
2214system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2215system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20459.942172 # average overall miss latency
2216system.cpu1.dcache.demand_avg_miss_latency::total 20459.942172 # average overall miss latency
2217system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19506.700354 # average overall miss latency
2218system.cpu1.dcache.overall_avg_miss_latency::total 19506.700354 # average overall miss latency
2219system.cpu1.dcache.blocked_cycles::no_mshrs 359 # number of cycles access was blocked
2220system.cpu1.dcache.blocked_cycles::no_targets 1638919 # number of cycles access was blocked
2221system.cpu1.dcache.blocked::no_mshrs 40 # number of cycles access was blocked
2222system.cpu1.dcache.blocked::no_targets 49248 # number of cycles access was blocked
2223system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.975000 # average number of cycles each access was blocked
2224system.cpu1.dcache.avg_blocked_cycles::no_targets 33.278895 # average number of cycles each access was blocked
2225system.cpu1.dcache.fast_writes 0 # number of fast writes performed
2226system.cpu1.dcache.cache_copies 0 # number of cache copies performed
2227system.cpu1.dcache.writebacks::writebacks 137260 # number of writebacks
2228system.cpu1.dcache.writebacks::total 137260 # number of writebacks
2229system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 91413 # number of ReadReq MSHR hits
2230system.cpu1.dcache.ReadReq_mshr_hits::total 91413 # number of ReadReq MSHR hits
2231system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 375801 # number of WriteReq MSHR hits
2232system.cpu1.dcache.WriteReq_mshr_hits::total 375801 # number of WriteReq MSHR hits
2233system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13808 # number of LoadLockedReq MSHR hits
2234system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13808 # number of LoadLockedReq MSHR hits
2235system.cpu1.dcache.demand_mshr_hits::cpu1.data 467214 # number of demand (read+write) MSHR hits
2236system.cpu1.dcache.demand_mshr_hits::total 467214 # number of demand (read+write) MSHR hits
2237system.cpu1.dcache.overall_mshr_hits::cpu1.data 467214 # number of overall MSHR hits
2238system.cpu1.dcache.overall_mshr_hits::total 467214 # number of overall MSHR hits
2239system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163234 # number of ReadReq MSHR misses
2240system.cpu1.dcache.ReadReq_mshr_misses::total 163234 # number of ReadReq MSHR misses
2241system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104766 # number of WriteReq MSHR misses
2242system.cpu1.dcache.WriteReq_mshr_misses::total 104766 # number of WriteReq MSHR misses
2243system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32551 # number of SoftPFReq MSHR misses
2244system.cpu1.dcache.SoftPFReq_mshr_misses::total 32551 # number of SoftPFReq MSHR misses
2245system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5403 # number of LoadLockedReq MSHR misses
2246system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5403 # number of LoadLockedReq MSHR misses
2247system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23462 # number of StoreCondReq MSHR misses
2248system.cpu1.dcache.StoreCondReq_mshr_misses::total 23462 # number of StoreCondReq MSHR misses
2249system.cpu1.dcache.demand_mshr_misses::cpu1.data 268000 # number of demand (read+write) MSHR misses
2250system.cpu1.dcache.demand_mshr_misses::total 268000 # number of demand (read+write) MSHR misses
2251system.cpu1.dcache.overall_mshr_misses::cpu1.data 300551 # number of overall MSHR misses
2252system.cpu1.dcache.overall_mshr_misses::total 300551 # number of overall MSHR misses
2253system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5603 # number of ReadReq MSHR uncacheable
2254system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5603 # number of ReadReq MSHR uncacheable
2255system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4908 # number of WriteReq MSHR uncacheable
2256system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4908 # number of WriteReq MSHR uncacheable
2257system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10511 # number of overall MSHR uncacheable misses
2258system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10511 # number of overall MSHR uncacheable misses
2259system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2247760000 # number of ReadReq MSHR miss cycles
2260system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2247760000 # number of ReadReq MSHR miss cycles
2261system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2639771935 # number of WriteReq MSHR miss cycles
2262system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2639771935 # number of WriteReq MSHR miss cycles
2263system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 542309000 # number of SoftPFReq MSHR miss cycles
2264system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 542309000 # number of SoftPFReq MSHR miss cycles
2265system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 101732500 # number of LoadLockedReq MSHR miss cycles
2266system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 101732500 # number of LoadLockedReq MSHR miss cycles
2267system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 522075500 # number of StoreCondReq MSHR miss cycles
2268system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 522075500 # number of StoreCondReq MSHR miss cycles
2269system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 517500 # number of StoreCondFailReq MSHR miss cycles
2270system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 517500 # number of StoreCondFailReq MSHR miss cycles
2271system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4887531935 # number of demand (read+write) MSHR miss cycles
2272system.cpu1.dcache.demand_mshr_miss_latency::total 4887531935 # number of demand (read+write) MSHR miss cycles
2273system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5429840935 # number of overall MSHR miss cycles
2274system.cpu1.dcache.overall_mshr_miss_latency::total 5429840935 # number of overall MSHR miss cycles
2275system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 989470000 # number of ReadReq MSHR uncacheable cycles
2276system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 989470000 # number of ReadReq MSHR uncacheable cycles
2277system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 857954500 # number of WriteReq MSHR uncacheable cycles
2278system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 857954500 # number of WriteReq MSHR uncacheable cycles
2279system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1847424500 # number of overall MSHR uncacheable cycles
2280system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1847424500 # number of overall MSHR uncacheable cycles
2281system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033987 # mshr miss rate for ReadReq accesses
2282system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033987 # mshr miss rate for ReadReq accesses
2283system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025907 # mshr miss rate for WriteReq accesses
2284system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025907 # mshr miss rate for WriteReq accesses
2285system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.326532 # mshr miss rate for SoftPFReq accesses
2286system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.326532 # mshr miss rate for SoftPFReq accesses
2287system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050741 # mshr miss rate for LoadLockedReq accesses
2288system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050741 # mshr miss rate for LoadLockedReq accesses
2289system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.227835 # mshr miss rate for StoreCondReq accesses
2290system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.227835 # mshr miss rate for StoreCondReq accesses
2291system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030293 # mshr miss rate for demand accesses
2292system.cpu1.dcache.demand_mshr_miss_rate::total 0.030293 # mshr miss rate for demand accesses
2293system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033594 # mshr miss rate for overall accesses
2294system.cpu1.dcache.overall_mshr_miss_rate::total 0.033594 # mshr miss rate for overall accesses
2295system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13770.170430 # average ReadReq mshr miss latency
2296system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13770.170430 # average ReadReq mshr miss latency
2297system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25196.838049 # average WriteReq mshr miss latency
2298system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25196.838049 # average WriteReq mshr miss latency
2299system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16660.286934 # average SoftPFReq mshr miss latency
2300system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16660.286934 # average SoftPFReq mshr miss latency
2301system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18828.891357 # average LoadLockedReq mshr miss latency
2302system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18828.891357 # average LoadLockedReq mshr miss latency
2303system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22251.960617 # average StoreCondReq mshr miss latency
2304system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22251.960617 # average StoreCondReq mshr miss latency
2305system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
2306system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2307system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18237.059459 # average overall mshr miss latency
2308system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18237.059459 # average overall mshr miss latency
2309system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18066.288034 # average overall mshr miss latency
2310system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18066.288034 # average overall mshr miss latency
2311system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176596.466179 # average ReadReq mshr uncacheable latency
2312system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176596.466179 # average ReadReq mshr uncacheable latency
2313system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174807.355338 # average WriteReq mshr uncacheable latency
2314system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 174807.355338 # average WriteReq mshr uncacheable latency
2315system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 175761.059842 # average overall mshr uncacheable latency
2316system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 175761.059842 # average overall mshr uncacheable latency
2317system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2318system.cpu1.icache.tags.replacements 661426 # number of replacements
2319system.cpu1.icache.tags.tagsinuse 498.525577 # Cycle average of tags in use
2320system.cpu1.icache.tags.total_refs 9800007 # Total number of references to valid blocks.
2321system.cpu1.icache.tags.sampled_refs 661938 # Sample count of references to valid blocks.
2322system.cpu1.icache.tags.avg_refs 14.805023 # Average number of references to valid blocks.
2323system.cpu1.icache.tags.warmup_cycle 78861824000 # Cycle when the warmup percentage was hit.
2324system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.525577 # Average occupied blocks per requestor
2325system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973683 # Average percentage of cache occupancy
2326system.cpu1.icache.tags.occ_percent::total 0.973683 # Average percentage of cache occupancy
2327system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2328system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id
2329system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id
2330system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2331system.cpu1.icache.tags.tag_accesses 21636569 # Number of tag accesses
2332system.cpu1.icache.tags.data_accesses 21636569 # Number of data accesses
2333system.cpu1.icache.ReadReq_hits::cpu1.inst 9800007 # number of ReadReq hits
2334system.cpu1.icache.ReadReq_hits::total 9800007 # number of ReadReq hits
2335system.cpu1.icache.demand_hits::cpu1.inst 9800007 # number of demand (read+write) hits
2336system.cpu1.icache.demand_hits::total 9800007 # number of demand (read+write) hits
2337system.cpu1.icache.overall_hits::cpu1.inst 9800007 # number of overall hits
2338system.cpu1.icache.overall_hits::total 9800007 # number of overall hits
2339system.cpu1.icache.ReadReq_misses::cpu1.inst 687303 # number of ReadReq misses
2340system.cpu1.icache.ReadReq_misses::total 687303 # number of ReadReq misses
2341system.cpu1.icache.demand_misses::cpu1.inst 687303 # number of demand (read+write) misses
2342system.cpu1.icache.demand_misses::total 687303 # number of demand (read+write) misses
2343system.cpu1.icache.overall_misses::cpu1.inst 687303 # number of overall misses
2344system.cpu1.icache.overall_misses::total 687303 # number of overall misses
2345system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6263235013 # number of ReadReq miss cycles
2346system.cpu1.icache.ReadReq_miss_latency::total 6263235013 # number of ReadReq miss cycles
2347system.cpu1.icache.demand_miss_latency::cpu1.inst 6263235013 # number of demand (read+write) miss cycles
2348system.cpu1.icache.demand_miss_latency::total 6263235013 # number of demand (read+write) miss cycles
2349system.cpu1.icache.overall_miss_latency::cpu1.inst 6263235013 # number of overall miss cycles
2350system.cpu1.icache.overall_miss_latency::total 6263235013 # number of overall miss cycles
2351system.cpu1.icache.ReadReq_accesses::cpu1.inst 10487310 # number of ReadReq accesses(hits+misses)
2352system.cpu1.icache.ReadReq_accesses::total 10487310 # number of ReadReq accesses(hits+misses)
2353system.cpu1.icache.demand_accesses::cpu1.inst 10487310 # number of demand (read+write) accesses
2354system.cpu1.icache.demand_accesses::total 10487310 # number of demand (read+write) accesses
2355system.cpu1.icache.overall_accesses::cpu1.inst 10487310 # number of overall (read+write) accesses
2356system.cpu1.icache.overall_accesses::total 10487310 # number of overall (read+write) accesses
2357system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.065537 # miss rate for ReadReq accesses
2358system.cpu1.icache.ReadReq_miss_rate::total 0.065537 # miss rate for ReadReq accesses
2359system.cpu1.icache.demand_miss_rate::cpu1.inst 0.065537 # miss rate for demand accesses
2360system.cpu1.icache.demand_miss_rate::total 0.065537 # miss rate for demand accesses
2361system.cpu1.icache.overall_miss_rate::cpu1.inst 0.065537 # miss rate for overall accesses
2362system.cpu1.icache.overall_miss_rate::total 0.065537 # miss rate for overall accesses
2363system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9112.771242 # average ReadReq miss latency
2364system.cpu1.icache.ReadReq_avg_miss_latency::total 9112.771242 # average ReadReq miss latency
2365system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9112.771242 # average overall miss latency
2366system.cpu1.icache.demand_avg_miss_latency::total 9112.771242 # average overall miss latency
2367system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9112.771242 # average overall miss latency
2368system.cpu1.icache.overall_avg_miss_latency::total 9112.771242 # average overall miss latency
2369system.cpu1.icache.blocked_cycles::no_mshrs 638996 # number of cycles access was blocked
2370system.cpu1.icache.blocked_cycles::no_targets 564 # number of cycles access was blocked
2371system.cpu1.icache.blocked::no_mshrs 53890 # number of cycles access was blocked
2372system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
2373system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.857413 # average number of cycles each access was blocked
2374system.cpu1.icache.avg_blocked_cycles::no_targets 564 # average number of cycles each access was blocked
2375system.cpu1.icache.fast_writes 0 # number of fast writes performed
2376system.cpu1.icache.cache_copies 0 # number of cache copies performed
2377system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 25354 # number of ReadReq MSHR hits
2378system.cpu1.icache.ReadReq_mshr_hits::total 25354 # number of ReadReq MSHR hits
2379system.cpu1.icache.demand_mshr_hits::cpu1.inst 25354 # number of demand (read+write) MSHR hits
2380system.cpu1.icache.demand_mshr_hits::total 25354 # number of demand (read+write) MSHR hits
2381system.cpu1.icache.overall_mshr_hits::cpu1.inst 25354 # number of overall MSHR hits
2382system.cpu1.icache.overall_mshr_hits::total 25354 # number of overall MSHR hits
2383system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 661949 # number of ReadReq MSHR misses
2384system.cpu1.icache.ReadReq_mshr_misses::total 661949 # number of ReadReq MSHR misses
2385system.cpu1.icache.demand_mshr_misses::cpu1.inst 661949 # number of demand (read+write) MSHR misses
2386system.cpu1.icache.demand_mshr_misses::total 661949 # number of demand (read+write) MSHR misses
2387system.cpu1.icache.overall_mshr_misses::cpu1.inst 661949 # number of overall MSHR misses
2388system.cpu1.icache.overall_mshr_misses::total 661949 # number of overall MSHR misses
2389system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable
2390system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable
2391system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses
2392system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses
2393system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5721508360 # number of ReadReq MSHR miss cycles
2394system.cpu1.icache.ReadReq_mshr_miss_latency::total 5721508360 # number of ReadReq MSHR miss cycles
2395system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5721508360 # number of demand (read+write) MSHR miss cycles
2396system.cpu1.icache.demand_mshr_miss_latency::total 5721508360 # number of demand (read+write) MSHR miss cycles
2397system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5721508360 # number of overall MSHR miss cycles
2398system.cpu1.icache.overall_mshr_miss_latency::total 5721508360 # number of overall MSHR miss cycles
2399system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8594000 # number of ReadReq MSHR uncacheable cycles
2400system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8594000 # number of ReadReq MSHR uncacheable cycles
2401system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8594000 # number of overall MSHR uncacheable cycles
2402system.cpu1.icache.overall_mshr_uncacheable_latency::total 8594000 # number of overall MSHR uncacheable cycles
2403system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.063119 # mshr miss rate for ReadReq accesses
2404system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.063119 # mshr miss rate for ReadReq accesses
2405system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.063119 # mshr miss rate for demand accesses
2406system.cpu1.icache.demand_mshr_miss_rate::total 0.063119 # mshr miss rate for demand accesses
2407system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.063119 # mshr miss rate for overall accesses
2408system.cpu1.icache.overall_mshr_miss_rate::total 0.063119 # mshr miss rate for overall accesses
2409system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8643.427757 # average ReadReq mshr miss latency
2410system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8643.427757 # average ReadReq mshr miss latency
2411system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8643.427757 # average overall mshr miss latency
2412system.cpu1.icache.demand_avg_mshr_miss_latency::total 8643.427757 # average overall mshr miss latency
2413system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8643.427757 # average overall mshr miss latency
2414system.cpu1.icache.overall_avg_mshr_miss_latency::total 8643.427757 # average overall mshr miss latency
2415system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84254.901961 # average ReadReq mshr uncacheable latency
2416system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 84254.901961 # average ReadReq mshr uncacheable latency
2417system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84254.901961 # average overall mshr uncacheable latency
2418system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 84254.901961 # average overall mshr uncacheable latency
2419system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2420system.cpu1.l2cache.prefetcher.num_hwpf_issued 269622 # number of hwpf issued
2421system.cpu1.l2cache.prefetcher.pfIdentified 270613 # number of prefetch candidates identified
2422system.cpu1.l2cache.prefetcher.pfBufferHit 884 # number of redundant prefetches already in prefetch queue
2423system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
2424system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2425system.cpu1.l2cache.prefetcher.pfSpanPage 67787 # number of prefetches not generated due to page crossing
2426system.cpu1.l2cache.tags.replacements 66660 # number of replacements
2427system.cpu1.l2cache.tags.tagsinuse 15577.889137 # Cycle average of tags in use
2428system.cpu1.l2cache.tags.total_refs 1655246 # Total number of references to valid blocks.
2429system.cpu1.l2cache.tags.sampled_refs 81265 # Sample count of references to valid blocks.
2430system.cpu1.l2cache.tags.avg_refs 20.368498 # Average number of references to valid blocks.
2431system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2432system.cpu1.l2cache.tags.occ_blocks::writebacks 6747.638156 # Average occupied blocks per requestor
2433system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 12.637913 # Average occupied blocks per requestor
2434system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.167789 # Average occupied blocks per requestor
2435system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4673.355619 # Average occupied blocks per requestor
2436system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2625.058292 # Average occupied blocks per requestor
2437system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1517.031368 # Average occupied blocks per requestor
2438system.cpu1.l2cache.tags.occ_percent::writebacks 0.411843 # Average percentage of cache occupancy
2439system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000771 # Average percentage of cache occupancy
2440system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000132 # Average percentage of cache occupancy
2441system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.285239 # Average percentage of cache occupancy
2442system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.160221 # Average percentage of cache occupancy
2443system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.092592 # Average percentage of cache occupancy
2444system.cpu1.l2cache.tags.occ_percent::total 0.950799 # Average percentage of cache occupancy
2445system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1291 # Occupied blocks per task id
2446system.cpu1.l2cache.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id
2447system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13290 # Occupied blocks per task id
2448system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 17 # Occupied blocks per task id
2449system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 868 # Occupied blocks per task id
2450system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 406 # Occupied blocks per task id
2451system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id
2452system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id
2453system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
2454system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 470 # Occupied blocks per task id
2455system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8605 # Occupied blocks per task id
2456system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4215 # Occupied blocks per task id
2457system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078796 # Percentage of cache occupancy per task id
2458system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001465 # Percentage of cache occupancy per task id
2459system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.811157 # Percentage of cache occupancy per task id
2460system.cpu1.l2cache.tags.tag_accesses 30536660 # Number of tag accesses
2461system.cpu1.l2cache.tags.data_accesses 30536660 # Number of data accesses
2462system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 19077 # number of ReadReq hits
2463system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7323 # number of ReadReq hits
2464system.cpu1.l2cache.ReadReq_hits::total 26400 # number of ReadReq hits
2465system.cpu1.l2cache.Writeback_hits::writebacks 137259 # number of Writeback hits
2466system.cpu1.l2cache.Writeback_hits::total 137259 # number of Writeback hits
2467system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2433 # number of UpgradeReq hits
2468system.cpu1.l2cache.UpgradeReq_hits::total 2433 # number of UpgradeReq hits
2469system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1103 # number of SCUpgradeReq hits
2470system.cpu1.l2cache.SCUpgradeReq_hits::total 1103 # number of SCUpgradeReq hits
2471system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38090 # number of ReadExReq hits
2472system.cpu1.l2cache.ReadExReq_hits::total 38090 # number of ReadExReq hits
2473system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 639615 # number of ReadCleanReq hits
2474system.cpu1.l2cache.ReadCleanReq_hits::total 639615 # number of ReadCleanReq hits
2475system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 127678 # number of ReadSharedReq hits
2476system.cpu1.l2cache.ReadSharedReq_hits::total 127678 # number of ReadSharedReq hits
2477system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 19077 # number of demand (read+write) hits
2478system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7323 # number of demand (read+write) hits
2479system.cpu1.l2cache.demand_hits::cpu1.inst 639615 # number of demand (read+write) hits
2480system.cpu1.l2cache.demand_hits::cpu1.data 165768 # number of demand (read+write) hits
2481system.cpu1.l2cache.demand_hits::total 831783 # number of demand (read+write) hits
2482system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 19077 # number of overall hits
2483system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7323 # number of overall hits
2484system.cpu1.l2cache.overall_hits::cpu1.inst 639615 # number of overall hits
2485system.cpu1.l2cache.overall_hits::cpu1.data 165768 # number of overall hits
2486system.cpu1.l2cache.overall_hits::total 831783 # number of overall hits
2487system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 431 # number of ReadReq misses
2488system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 286 # number of ReadReq misses
2489system.cpu1.l2cache.ReadReq_misses::total 717 # number of ReadReq misses
2490system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses
2491system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses
2492system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29127 # number of UpgradeReq misses
2493system.cpu1.l2cache.UpgradeReq_misses::total 29127 # number of UpgradeReq misses
2494system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22358 # number of SCUpgradeReq misses
2495system.cpu1.l2cache.SCUpgradeReq_misses::total 22358 # number of SCUpgradeReq misses
2496system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses
2497system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
2498system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35752 # number of ReadExReq misses
2499system.cpu1.l2cache.ReadExReq_misses::total 35752 # number of ReadExReq misses
2500system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 22316 # number of ReadCleanReq misses
2501system.cpu1.l2cache.ReadCleanReq_misses::total 22316 # number of ReadCleanReq misses
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2506system.cpu1.l2cache.demand_misses::cpu1.inst 22316 # number of demand (read+write) misses
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2515system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5864000 # number of ReadReq miss cycles
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2517system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 555921000 # number of UpgradeReq miss cycles
2518system.cpu1.l2cache.UpgradeReq_miss_latency::total 555921000 # number of UpgradeReq miss cycles
2519system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449033000 # number of SCUpgradeReq miss cycles
2520system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449033000 # number of SCUpgradeReq miss cycles
2521system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 501000 # number of SCUpgradeFailReq miss cycles
2522system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 501000 # number of SCUpgradeFailReq miss cycles
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2524system.cpu1.l2cache.ReadExReq_miss_latency::total 1528833498 # number of ReadExReq miss cycles
2525system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 894673000 # number of ReadCleanReq miss cycles
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2528system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1746677998 # number of ReadSharedReq miss cycles
2529system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9445500 # number of demand (read+write) miss cycles
2530system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5864000 # number of demand (read+write) miss cycles
2531system.cpu1.l2cache.demand_miss_latency::cpu1.inst 894673000 # number of demand (read+write) miss cycles
2532system.cpu1.l2cache.demand_miss_latency::cpu1.data 3275511496 # number of demand (read+write) miss cycles
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2534system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9445500 # number of overall miss cycles
2535system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5864000 # number of overall miss cycles
2536system.cpu1.l2cache.overall_miss_latency::cpu1.inst 894673000 # number of overall miss cycles
2537system.cpu1.l2cache.overall_miss_latency::cpu1.data 3275511496 # number of overall miss cycles
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2540system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7609 # number of ReadReq accesses(hits+misses)
2541system.cpu1.l2cache.ReadReq_accesses::total 27117 # number of ReadReq accesses(hits+misses)
2542system.cpu1.l2cache.Writeback_accesses::writebacks 137260 # number of Writeback accesses(hits+misses)
2543system.cpu1.l2cache.Writeback_accesses::total 137260 # number of Writeback accesses(hits+misses)
2544system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31560 # number of UpgradeReq accesses(hits+misses)
2545system.cpu1.l2cache.UpgradeReq_accesses::total 31560 # number of UpgradeReq accesses(hits+misses)
2546system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23461 # number of SCUpgradeReq accesses(hits+misses)
2547system.cpu1.l2cache.SCUpgradeReq_accesses::total 23461 # number of SCUpgradeReq accesses(hits+misses)
2548system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
2549system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
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2551system.cpu1.l2cache.ReadExReq_accesses::total 73842 # number of ReadExReq accesses(hits+misses)
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2553system.cpu1.l2cache.ReadCleanReq_accesses::total 661931 # number of ReadCleanReq accesses(hits+misses)
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2555system.cpu1.l2cache.ReadSharedReq_accesses::total 201163 # number of ReadSharedReq accesses(hits+misses)
2556system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 19508 # number of demand (read+write) accesses
2557system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7609 # number of demand (read+write) accesses
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2561system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 19508 # number of overall (read+write) accesses
2562system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7609 # number of overall (read+write) accesses
2563system.cpu1.l2cache.overall_accesses::cpu1.inst 661931 # number of overall (read+write) accesses
2564system.cpu1.l2cache.overall_accesses::cpu1.data 275005 # number of overall (read+write) accesses
2565system.cpu1.l2cache.overall_accesses::total 964053 # number of overall (read+write) accesses
2566system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022094 # miss rate for ReadReq accesses
2567system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.037587 # miss rate for ReadReq accesses
2568system.cpu1.l2cache.ReadReq_miss_rate::total 0.026441 # miss rate for ReadReq accesses
2569system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000007 # miss rate for Writeback accesses
2570system.cpu1.l2cache.Writeback_miss_rate::total 0.000007 # miss rate for Writeback accesses
2571system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.922909 # miss rate for UpgradeReq accesses
2572system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.922909 # miss rate for UpgradeReq accesses
2573system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.952986 # miss rate for SCUpgradeReq accesses
2574system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.952986 # miss rate for SCUpgradeReq accesses
2575system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2576system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2577system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.484169 # miss rate for ReadExReq accesses
2578system.cpu1.l2cache.ReadExReq_miss_rate::total 0.484169 # miss rate for ReadExReq accesses
2579system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.033713 # miss rate for ReadCleanReq accesses
2580system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.033713 # miss rate for ReadCleanReq accesses
2581system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.365301 # miss rate for ReadSharedReq accesses
2582system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.365301 # miss rate for ReadSharedReq accesses
2583system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022094 # miss rate for demand accesses
2584system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.037587 # miss rate for demand accesses
2585system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.033713 # miss rate for demand accesses
2586system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.397218 # miss rate for demand accesses
2587system.cpu1.l2cache.demand_miss_rate::total 0.137202 # miss rate for demand accesses
2588system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022094 # miss rate for overall accesses
2589system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.037587 # miss rate for overall accesses
2590system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.033713 # miss rate for overall accesses
2591system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.397218 # miss rate for overall accesses
2592system.cpu1.l2cache.overall_miss_rate::total 0.137202 # miss rate for overall accesses
2593system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21915.313225 # average ReadReq miss latency
2594system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20503.496503 # average ReadReq miss latency
2595system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21352.161785 # average ReadReq miss latency
2596system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19086.105675 # average UpgradeReq miss latency
2597system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19086.105675 # average UpgradeReq miss latency
2598system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20083.773146 # average SCUpgradeReq miss latency
2599system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20083.773146 # average SCUpgradeReq miss latency
2600system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 501000 # average SCUpgradeFailReq miss latency
2601system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 501000 # average SCUpgradeFailReq miss latency
2602system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42762.181081 # average ReadExReq miss latency
2603system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42762.181081 # average ReadExReq miss latency
2604system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40091.100556 # average ReadCleanReq miss latency
2605system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40091.100556 # average ReadCleanReq miss latency
2606system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23769.177356 # average ReadSharedReq miss latency
2607system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23769.177356 # average ReadSharedReq miss latency
2608system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21915.313225 # average overall miss latency
2609system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20503.496503 # average overall miss latency
2610system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40091.100556 # average overall miss latency
2611system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29985.366643 # average overall miss latency
2612system.cpu1.l2cache.demand_avg_miss_latency::total 31643.562380 # average overall miss latency
2613system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21915.313225 # average overall miss latency
2614system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20503.496503 # average overall miss latency
2615system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40091.100556 # average overall miss latency
2616system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29985.366643 # average overall miss latency
2617system.cpu1.l2cache.overall_avg_miss_latency::total 31643.562380 # average overall miss latency
2618system.cpu1.l2cache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked
2619system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2620system.cpu1.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked
2621system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2622system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 24.800000 # average number of cycles each access was blocked
2623system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2624system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2625system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2626system.cpu1.l2cache.writebacks::writebacks 39050 # number of writebacks
2627system.cpu1.l2cache.writebacks::total 39050 # number of writebacks
2628system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 13 # number of ReadReq MSHR hits
2629system.cpu1.l2cache.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits
2630system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 854 # number of ReadExReq MSHR hits
2631system.cpu1.l2cache.ReadExReq_mshr_hits::total 854 # number of ReadExReq MSHR hits
2632system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 14 # number of ReadCleanReq MSHR hits
2633system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 14 # number of ReadCleanReq MSHR hits
2634system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 144 # number of ReadSharedReq MSHR hits
2635system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 144 # number of ReadSharedReq MSHR hits
2636system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 13 # number of demand (read+write) MSHR hits
2637system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 14 # number of demand (read+write) MSHR hits
2638system.cpu1.l2cache.demand_mshr_hits::cpu1.data 998 # number of demand (read+write) MSHR hits
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2640system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 13 # number of overall MSHR hits
2641system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 14 # number of overall MSHR hits
2642system.cpu1.l2cache.overall_mshr_hits::cpu1.data 998 # number of overall MSHR hits
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2645system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 273 # number of ReadReq MSHR misses
2646system.cpu1.l2cache.ReadReq_mshr_misses::total 704 # number of ReadReq MSHR misses
2647system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses
2648system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses
2649system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 3034 # number of CleanEvict MSHR misses
2650system.cpu1.l2cache.CleanEvict_mshr_misses::total 3034 # number of CleanEvict MSHR misses
2651system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 37433 # number of HardPFReq MSHR misses
2652system.cpu1.l2cache.HardPFReq_mshr_misses::total 37433 # number of HardPFReq MSHR misses
2653system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29127 # number of UpgradeReq MSHR misses
2654system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29127 # number of UpgradeReq MSHR misses
2655system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22358 # number of SCUpgradeReq MSHR misses
2656system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22358 # number of SCUpgradeReq MSHR misses
2657system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses
2658system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
2659system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34898 # number of ReadExReq MSHR misses
2660system.cpu1.l2cache.ReadExReq_mshr_misses::total 34898 # number of ReadExReq MSHR misses
2661system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 22302 # number of ReadCleanReq MSHR misses
2662system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 22302 # number of ReadCleanReq MSHR misses
2663system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 73341 # number of ReadSharedReq MSHR misses
2664system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 73341 # number of ReadSharedReq MSHR misses
2665system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 431 # number of demand (read+write) MSHR misses
2666system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 273 # number of demand (read+write) MSHR misses
2667system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 22302 # number of demand (read+write) MSHR misses
2668system.cpu1.l2cache.demand_mshr_misses::cpu1.data 108239 # number of demand (read+write) MSHR misses
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2670system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 431 # number of overall MSHR misses
2671system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 273 # number of overall MSHR misses
2672system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 22302 # number of overall MSHR misses
2673system.cpu1.l2cache.overall_mshr_misses::cpu1.data 108239 # number of overall MSHR misses
2674system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 37433 # number of overall MSHR misses
2675system.cpu1.l2cache.overall_mshr_misses::total 168678 # number of overall MSHR misses
2676system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable
2677system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5603 # number of ReadReq MSHR uncacheable
2678system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5705 # number of ReadReq MSHR uncacheable
2679system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 4908 # number of WriteReq MSHR uncacheable
2680system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 4908 # number of WriteReq MSHR uncacheable
2681system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses
2682system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10511 # number of overall MSHR uncacheable misses
2683system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10613 # number of overall MSHR uncacheable misses
2684system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6859500 # number of ReadReq MSHR miss cycles
2685system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4063500 # number of ReadReq MSHR miss cycles
2686system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10923000 # number of ReadReq MSHR miss cycles
2687system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1619868588 # number of HardPFReq MSHR miss cycles
2688system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1619868588 # number of HardPFReq MSHR miss cycles
2689system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 495927500 # number of UpgradeReq MSHR miss cycles
2690system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 495927500 # number of UpgradeReq MSHR miss cycles
2691system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 345361500 # number of SCUpgradeReq MSHR miss cycles
2692system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 345361500 # number of SCUpgradeReq MSHR miss cycles
2693system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 435000 # number of SCUpgradeFailReq MSHR miss cycles
2694system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 435000 # number of SCUpgradeFailReq MSHR miss cycles
2695system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1215520500 # number of ReadExReq MSHR miss cycles
2696system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1215520500 # number of ReadExReq MSHR miss cycles
2697system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 760109500 # number of ReadCleanReq MSHR miss cycles
2698system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 760109500 # number of ReadCleanReq MSHR miss cycles
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2700system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1300287998 # number of ReadSharedReq MSHR miss cycles
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2706system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6859500 # number of overall MSHR miss cycles
2707system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4063500 # number of overall MSHR miss cycles
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2709system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2515808498 # number of overall MSHR miss cycles
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2711system.cpu1.l2cache.overall_mshr_miss_latency::total 4906709586 # number of overall MSHR miss cycles
2712system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7829000 # number of ReadReq MSHR uncacheable cycles
2713system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 944359000 # number of ReadReq MSHR uncacheable cycles
2714system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 952188000 # number of ReadReq MSHR uncacheable cycles
2715system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 821025498 # number of WriteReq MSHR uncacheable cycles
2716system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 821025498 # number of WriteReq MSHR uncacheable cycles
2717system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7829000 # number of overall MSHR uncacheable cycles
2718system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1765384498 # number of overall MSHR uncacheable cycles
2719system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1773213498 # number of overall MSHR uncacheable cycles
2720system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022094 # mshr miss rate for ReadReq accesses
2721system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035879 # mshr miss rate for ReadReq accesses
2722system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025962 # mshr miss rate for ReadReq accesses
2723system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000007 # mshr miss rate for Writeback accesses
2724system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000007 # mshr miss rate for Writeback accesses
2725system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2726system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2727system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2728system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2729system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.922909 # mshr miss rate for UpgradeReq accesses
2730system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.922909 # mshr miss rate for UpgradeReq accesses
2731system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.952986 # mshr miss rate for SCUpgradeReq accesses
2732system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.952986 # mshr miss rate for SCUpgradeReq accesses
2733system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2734system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2735system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.472604 # mshr miss rate for ReadExReq accesses
2736system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.472604 # mshr miss rate for ReadExReq accesses
2737system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.033692 # mshr miss rate for ReadCleanReq accesses
2738system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.033692 # mshr miss rate for ReadCleanReq accesses
2739system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.364585 # mshr miss rate for ReadSharedReq accesses
2740system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.364585 # mshr miss rate for ReadSharedReq accesses
2741system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022094 # mshr miss rate for demand accesses
2742system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.035879 # mshr miss rate for demand accesses
2743system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.033692 # mshr miss rate for demand accesses
2744system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.393589 # mshr miss rate for demand accesses
2745system.cpu1.l2cache.demand_mshr_miss_rate::total 0.136139 # mshr miss rate for demand accesses
2746system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022094 # mshr miss rate for overall accesses
2747system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.035879 # mshr miss rate for overall accesses
2748system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.033692 # mshr miss rate for overall accesses
2749system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.393589 # mshr miss rate for overall accesses
2750system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2751system.cpu1.l2cache.overall_mshr_miss_rate::total 0.174968 # mshr miss rate for overall accesses
2752system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225 # average ReadReq mshr miss latency
2753system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385 # average ReadReq mshr miss latency
2754system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15515.625000 # average ReadReq mshr miss latency
2755system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43273.811557 # average HardPFReq mshr miss latency
2756system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43273.811557 # average HardPFReq mshr miss latency
2757system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17026.384454 # average UpgradeReq mshr miss latency
2758system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17026.384454 # average UpgradeReq mshr miss latency
2759system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15446.887020 # average SCUpgradeReq mshr miss latency
2760system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15446.887020 # average SCUpgradeReq mshr miss latency
2761system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 435000 # average SCUpgradeFailReq mshr miss latency
2762system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 435000 # average SCUpgradeFailReq mshr miss latency
2763system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34830.663648 # average ReadExReq mshr miss latency
2764system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34830.663648 # average ReadExReq mshr miss latency
2765system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34082.571070 # average ReadCleanReq mshr miss latency
2766system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34082.571070 # average ReadCleanReq mshr miss latency
2767system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17729.346450 # average ReadSharedReq mshr miss latency
2768system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17729.346450 # average ReadSharedReq mshr miss latency
2769system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225 # average overall mshr miss latency
2770system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385 # average overall mshr miss latency
2771system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34082.571070 # average overall mshr miss latency
2772system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23243.087039 # average overall mshr miss latency
2773system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25043.552120 # average overall mshr miss latency
2774system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225 # average overall mshr miss latency
2775system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385 # average overall mshr miss latency
2776system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34082.571070 # average overall mshr miss latency
2777system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23243.087039 # average overall mshr miss latency
2778system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43273.811557 # average overall mshr miss latency
2779system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29089.208942 # average overall mshr miss latency
2780system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 76754.901961 # average ReadReq mshr uncacheable latency
2781system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168545.243619 # average ReadReq mshr uncacheable latency
2782system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166904.119194 # average ReadReq mshr uncacheable latency
2783system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167283.108802 # average WriteReq mshr uncacheable latency
2784system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 167283.108802 # average WriteReq mshr uncacheable latency
2785system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 76754.901961 # average overall mshr uncacheable latency
2786system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 167955.903149 # average overall mshr uncacheable latency
2787system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 167079.383586 # average overall mshr uncacheable latency
2788system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2789system.cpu1.toL2Bus.trans_dist::ReadReq 70770 # Transaction distribution
2790system.cpu1.toL2Bus.trans_dist::ReadResp 942311 # Transaction distribution
2791system.cpu1.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution
2792system.cpu1.toL2Bus.trans_dist::WriteResp 4908 # Transaction distribution
2793system.cpu1.toL2Bus.trans_dist::Writeback 510267 # Transaction distribution
2794system.cpu1.toL2Bus.trans_dist::CleanEvict 868505 # Transaction distribution
2795system.cpu1.toL2Bus.trans_dist::HardPFReq 48336 # Transaction distribution
2796system.cpu1.toL2Bus.trans_dist::UpgradeReq 75730 # Transaction distribution
2797system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43006 # Transaction distribution
2798system.cpu1.toL2Bus.trans_dist::UpgradeResp 89941 # Transaction distribution
2799system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
2800system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
2801system.cpu1.toL2Bus.trans_dist::ReadExReq 96740 # Transaction distribution
2802system.cpu1.toL2Bus.trans_dist::ReadExResp 79738 # Transaction distribution
2803system.cpu1.toL2Bus.trans_dist::ReadCleanReq 661949 # Transaction distribution
2804system.cpu1.toL2Bus.trans_dist::ReadSharedReq 536905 # Transaction distribution
2805system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
2806system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1973224 # Packet count per connected master and slave (bytes)
2807system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 988189 # Packet count per connected master and slave (bytes)
2808system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17063 # Packet count per connected master and slave (bytes)
2809system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 42721 # Packet count per connected master and slave (bytes)
2810system.cpu1.toL2Bus.pkt_count::total 3021197 # Packet count per connected master and slave (bytes)
2811system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 42365216 # Cumulative packet size per connected master and slave (bytes)
2812system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29405313 # Cumulative packet size per connected master and slave (bytes)
2813system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30436 # Cumulative packet size per connected master and slave (bytes)
2814system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 78032 # Cumulative packet size per connected master and slave (bytes)
2815system.cpu1.toL2Bus.pkt_size::total 71878997 # Cumulative packet size per connected master and slave (bytes)
2816system.cpu1.toL2Bus.snoops 1156869 # Total snoops (count)
2817system.cpu1.toL2Bus.snoop_fanout::samples 2994555 # Request fanout histogram
2818system.cpu1.toL2Bus.snoop_fanout::mean 1.368102 # Request fanout histogram
2819system.cpu1.toL2Bus.snoop_fanout::stdev 0.482289 # Request fanout histogram
2820system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2821system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2822system.cpu1.toL2Bus.snoop_fanout::1 1892252 63.19% 63.19% # Request fanout histogram
2823system.cpu1.toL2Bus.snoop_fanout::2 1102303 36.81% 100.00% # Request fanout histogram
2824system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2825system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
2826system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2827system.cpu1.toL2Bus.snoop_fanout::total 2994555 # Request fanout histogram
2828system.cpu1.toL2Bus.reqLayer0.occupancy 1102178989 # Layer occupancy (ticks)
2829system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2830system.cpu1.toL2Bus.snoopLayer0.occupancy 87567999 # Layer occupancy (ticks)
2831system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2832system.cpu1.toL2Bus.respLayer0.occupancy 993110829 # Layer occupancy (ticks)
2833system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2834system.cpu1.toL2Bus.respLayer1.occupancy 449674318 # Layer occupancy (ticks)
2835system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2836system.cpu1.toL2Bus.respLayer2.occupancy 9464978 # Layer occupancy (ticks)
2837system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2838system.cpu1.toL2Bus.respLayer3.occupancy 23224976 # Layer occupancy (ticks)
2839system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2840system.iobus.trans_dist::ReadReq 31011 # Transaction distribution
2841system.iobus.trans_dist::ReadResp 31011 # Transaction distribution
2842system.iobus.trans_dist::WriteReq 59421 # Transaction distribution
2843system.iobus.trans_dist::WriteResp 59421 # Transaction distribution
2844system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes)
2845system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2846system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
2847system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
2848system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
2849system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 848 # Packet count per connected master and slave (bytes)
2850system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
2851system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2852system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2853system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2854system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
2855system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2856system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
2857system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
2858system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
2859system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
2860system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
2861system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
2862system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2863system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
2864system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2865system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes)
2866system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
2867system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
2868system.iobus.pkt_count::total 180864 # Packet count per connected master and slave (bytes)
2869system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes)
2870system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2871system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
2872system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
2873system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
2874system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 448 # Cumulative packet size per connected master and slave (bytes)
2875system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
2876system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2877system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2878system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2879system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
2880system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2881system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2882system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
2883system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
2884system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2885system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
2886system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
2887system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2888system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
2889system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2890system.iobus.pkt_size_system.bridge.master::total 162793 # Cumulative packet size per connected master and slave (bytes)
2891system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
2892system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
2893system.iobus.pkt_size::total 2484041 # Cumulative packet size per connected master and slave (bytes)
2894system.iobus.reqLayer0.occupancy 40089000 # Layer occupancy (ticks)
2895system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2896system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
2897system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2898system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
2899system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2900system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
2901system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2902system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
2903system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
2904system.iobus.reqLayer7.occupancy 505000 # Layer occupancy (ticks)
2905system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2906system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
2907system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2908system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
2909system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2910system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
2911system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2912system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)

--- 17 unchanged lines hidden (view full) ---

2930system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
2931system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2932system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
2933system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2934system.iobus.reqLayer27.occupancy 187554438 # Layer occupancy (ticks)
2935system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2936system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
2937system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
2938system.iobus.respLayer0.occupancy 84715000 # Layer occupancy (ticks)
2939system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2940system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks)
2941system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2942system.iocache.tags.replacements 36458 # number of replacements
2943system.iocache.tags.tagsinuse 14.446879 # Cycle average of tags in use
2944system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2945system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks.
2946system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2947system.iocache.tags.warmup_cycle 254837974000 # Cycle when the warmup percentage was hit.
2948system.iocache.tags.occ_blocks::realview.ide 14.446879 # Average occupied blocks per requestor
2949system.iocache.tags.occ_percent::realview.ide 0.902930 # Average percentage of cache occupancy
2950system.iocache.tags.occ_percent::total 0.902930 # Average percentage of cache occupancy
2951system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2952system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2953system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2954system.iocache.tags.tag_accesses 328284 # Number of tag accesses
2955system.iocache.tags.data_accesses 328284 # Number of data accesses
2956system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
2957system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
2958system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2959system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2960system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
2961system.iocache.demand_misses::total 252 # number of demand (read+write) misses
2962system.iocache.overall_misses::realview.ide 252 # number of overall misses
2963system.iocache.overall_misses::total 252 # number of overall misses
2964system.iocache.ReadReq_miss_latency::realview.ide 32277877 # number of ReadReq miss cycles
2965system.iocache.ReadReq_miss_latency::total 32277877 # number of ReadReq miss cycles
2966system.iocache.WriteLineReq_miss_latency::realview.ide 4275018561 # number of WriteLineReq miss cycles
2967system.iocache.WriteLineReq_miss_latency::total 4275018561 # number of WriteLineReq miss cycles
2968system.iocache.demand_miss_latency::realview.ide 32277877 # number of demand (read+write) miss cycles
2969system.iocache.demand_miss_latency::total 32277877 # number of demand (read+write) miss cycles
2970system.iocache.overall_miss_latency::realview.ide 32277877 # number of overall miss cycles
2971system.iocache.overall_miss_latency::total 32277877 # number of overall miss cycles
2972system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
2973system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
2974system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2975system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2976system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
2977system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
2978system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
2979system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
2980system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2981system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2982system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2983system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2984system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2985system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2986system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2987system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2988system.iocache.ReadReq_avg_miss_latency::realview.ide 128086.813492 # average ReadReq miss latency
2989system.iocache.ReadReq_avg_miss_latency::total 128086.813492 # average ReadReq miss latency
2990system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118016.192607 # average WriteLineReq miss latency
2991system.iocache.WriteLineReq_avg_miss_latency::total 118016.192607 # average WriteLineReq miss latency
2992system.iocache.demand_avg_miss_latency::realview.ide 128086.813492 # average overall miss latency
2993system.iocache.demand_avg_miss_latency::total 128086.813492 # average overall miss latency
2994system.iocache.overall_avg_miss_latency::realview.ide 128086.813492 # average overall miss latency
2995system.iocache.overall_avg_miss_latency::total 128086.813492 # average overall miss latency
2996system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2997system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2998system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2999system.iocache.blocked::no_targets 0 # number of cycles access was blocked
3000system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
3001system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3002system.iocache.fast_writes 0 # number of fast writes performed
3003system.iocache.cache_copies 0 # number of cache copies performed
3004system.iocache.writebacks::writebacks 36206 # number of writebacks
3005system.iocache.writebacks::total 36206 # number of writebacks
3006system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses
3007system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses
3008system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
3009system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
3010system.iocache.demand_mshr_misses::realview.ide 252 # number of demand (read+write) MSHR misses
3011system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses
3012system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses
3013system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses
3014system.iocache.ReadReq_mshr_miss_latency::realview.ide 19677877 # number of ReadReq MSHR miss cycles
3015system.iocache.ReadReq_mshr_miss_latency::total 19677877 # number of ReadReq MSHR miss cycles
3016system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2463818561 # number of WriteLineReq MSHR miss cycles
3017system.iocache.WriteLineReq_mshr_miss_latency::total 2463818561 # number of WriteLineReq MSHR miss cycles
3018system.iocache.demand_mshr_miss_latency::realview.ide 19677877 # number of demand (read+write) MSHR miss cycles
3019system.iocache.demand_mshr_miss_latency::total 19677877 # number of demand (read+write) MSHR miss cycles
3020system.iocache.overall_mshr_miss_latency::realview.ide 19677877 # number of overall MSHR miss cycles
3021system.iocache.overall_mshr_miss_latency::total 19677877 # number of overall MSHR miss cycles
3022system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
3023system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
3024system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
3025system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
3026system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
3027system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
3028system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
3029system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
3030system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78086.813492 # average ReadReq mshr miss latency
3031system.iocache.ReadReq_avg_mshr_miss_latency::total 78086.813492 # average ReadReq mshr miss latency
3032system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68016.192607 # average WriteLineReq mshr miss latency
3033system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68016.192607 # average WriteLineReq mshr miss latency
3034system.iocache.demand_avg_mshr_miss_latency::realview.ide 78086.813492 # average overall mshr miss latency
3035system.iocache.demand_avg_mshr_miss_latency::total 78086.813492 # average overall mshr miss latency
3036system.iocache.overall_avg_mshr_miss_latency::realview.ide 78086.813492 # average overall mshr miss latency
3037system.iocache.overall_avg_mshr_miss_latency::total 78086.813492 # average overall mshr miss latency
3038system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
3039system.l2c.tags.replacements 136014 # number of replacements
3040system.l2c.tags.tagsinuse 64041.678257 # Cycle average of tags in use
3041system.l2c.tags.total_refs 410908 # Total number of references to valid blocks.
3042system.l2c.tags.sampled_refs 200324 # Sample count of references to valid blocks.
3043system.l2c.tags.avg_refs 2.051217 # Average number of references to valid blocks.
3044system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
3045system.l2c.tags.occ_blocks::writebacks 12985.002975 # Average occupied blocks per requestor
3046system.l2c.tags.occ_blocks::cpu0.dtb.walker 12.737581 # Average occupied blocks per requestor
3047system.l2c.tags.occ_blocks::cpu0.itb.walker 3.016987 # Average occupied blocks per requestor
3048system.l2c.tags.occ_blocks::cpu0.inst 6471.116722 # Average occupied blocks per requestor
3049system.l2c.tags.occ_blocks::cpu0.data 1893.814522 # Average occupied blocks per requestor
3050system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32628.788989 # Average occupied blocks per requestor
3051system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.896219 # Average occupied blocks per requestor
3052system.l2c.tags.occ_blocks::cpu1.itb.walker 1.746917 # Average occupied blocks per requestor
3053system.l2c.tags.occ_blocks::cpu1.inst 3305.203826 # Average occupied blocks per requestor
3054system.l2c.tags.occ_blocks::cpu1.data 1817.254812 # Average occupied blocks per requestor
3055system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4915.098707 # Average occupied blocks per requestor
3056system.l2c.tags.occ_percent::writebacks 0.198135 # Average percentage of cache occupancy
3057system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000194 # Average percentage of cache occupancy
3058system.l2c.tags.occ_percent::cpu0.itb.walker 0.000046 # Average percentage of cache occupancy
3059system.l2c.tags.occ_percent::cpu0.inst 0.098741 # Average percentage of cache occupancy
3060system.l2c.tags.occ_percent::cpu0.data 0.028897 # Average percentage of cache occupancy
3061system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.497876 # Average percentage of cache occupancy
3062system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000120 # Average percentage of cache occupancy
3063system.l2c.tags.occ_percent::cpu1.itb.walker 0.000027 # Average percentage of cache occupancy
3064system.l2c.tags.occ_percent::cpu1.inst 0.050433 # Average percentage of cache occupancy
3065system.l2c.tags.occ_percent::cpu1.data 0.027729 # Average percentage of cache occupancy
3066system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.074998 # Average percentage of cache occupancy
3067system.l2c.tags.occ_percent::total 0.977198 # Average percentage of cache occupancy
3068system.l2c.tags.occ_task_id_blocks::1022 30547 # Occupied blocks per task id
3069system.l2c.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id
3070system.l2c.tags.occ_task_id_blocks::1024 33736 # Occupied blocks per task id
3071system.l2c.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id
3072system.l2c.tags.age_task_id_blocks_1022::3 6158 # Occupied blocks per task id
3073system.l2c.tags.age_task_id_blocks_1022::4 24257 # Occupied blocks per task id
3074system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
3075system.l2c.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id
3076system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
3077system.l2c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
3078system.l2c.tags.age_task_id_blocks_1024::2 442 # Occupied blocks per task id
3079system.l2c.tags.age_task_id_blocks_1024::3 5063 # Occupied blocks per task id
3080system.l2c.tags.age_task_id_blocks_1024::4 28206 # Occupied blocks per task id
3081system.l2c.tags.occ_task_id_percent::1022 0.466110 # Percentage of cache occupancy per task id
3082system.l2c.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id
3083system.l2c.tags.occ_task_id_percent::1024 0.514771 # Percentage of cache occupancy per task id
3084system.l2c.tags.tag_accesses 5562101 # Number of tag accesses
3085system.l2c.tags.data_accesses 5562101 # Number of data accesses
3086system.l2c.Writeback_hits::writebacks 232311 # number of Writeback hits
3087system.l2c.Writeback_hits::total 232311 # number of Writeback hits
3088system.l2c.UpgradeReq_hits::cpu0.data 2454 # number of UpgradeReq hits
3089system.l2c.UpgradeReq_hits::cpu1.data 792 # number of UpgradeReq hits
3090system.l2c.UpgradeReq_hits::total 3246 # number of UpgradeReq hits
3091system.l2c.SCUpgradeReq_hits::cpu0.data 247 # number of SCUpgradeReq hits
3092system.l2c.SCUpgradeReq_hits::cpu1.data 65 # number of SCUpgradeReq hits
3093system.l2c.SCUpgradeReq_hits::total 312 # number of SCUpgradeReq hits
3094system.l2c.ReadExReq_hits::cpu0.data 3756 # number of ReadExReq hits
3095system.l2c.ReadExReq_hits::cpu1.data 1862 # number of ReadExReq hits
3096system.l2c.ReadExReq_hits::total 5618 # number of ReadExReq hits
3097system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 184 # number of ReadSharedReq hits
3098system.l2c.ReadSharedReq_hits::cpu0.itb.walker 89 # number of ReadSharedReq hits
3099system.l2c.ReadSharedReq_hits::cpu0.inst 33340 # number of ReadSharedReq hits
3100system.l2c.ReadSharedReq_hits::cpu0.data 45362 # number of ReadSharedReq hits
3101system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 43171 # number of ReadSharedReq hits
3102system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 54 # number of ReadSharedReq hits
3103system.l2c.ReadSharedReq_hits::cpu1.itb.walker 50 # number of ReadSharedReq hits
3104system.l2c.ReadSharedReq_hits::cpu1.inst 17322 # number of ReadSharedReq hits
3105system.l2c.ReadSharedReq_hits::cpu1.data 11995 # number of ReadSharedReq hits
3106system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 7539 # number of ReadSharedReq hits
3107system.l2c.ReadSharedReq_hits::total 159106 # number of ReadSharedReq hits
3108system.l2c.demand_hits::cpu0.dtb.walker 184 # number of demand (read+write) hits
3109system.l2c.demand_hits::cpu0.itb.walker 89 # number of demand (read+write) hits
3110system.l2c.demand_hits::cpu0.inst 33340 # number of demand (read+write) hits
3111system.l2c.demand_hits::cpu0.data 49118 # number of demand (read+write) hits
3112system.l2c.demand_hits::cpu0.l2cache.prefetcher 43171 # number of demand (read+write) hits
3113system.l2c.demand_hits::cpu1.dtb.walker 54 # number of demand (read+write) hits
3114system.l2c.demand_hits::cpu1.itb.walker 50 # number of demand (read+write) hits
3115system.l2c.demand_hits::cpu1.inst 17322 # number of demand (read+write) hits
3116system.l2c.demand_hits::cpu1.data 13857 # number of demand (read+write) hits
3117system.l2c.demand_hits::cpu1.l2cache.prefetcher 7539 # number of demand (read+write) hits
3118system.l2c.demand_hits::total 164724 # number of demand (read+write) hits
3119system.l2c.overall_hits::cpu0.dtb.walker 184 # number of overall hits
3120system.l2c.overall_hits::cpu0.itb.walker 89 # number of overall hits
3121system.l2c.overall_hits::cpu0.inst 33340 # number of overall hits
3122system.l2c.overall_hits::cpu0.data 49118 # number of overall hits
3123system.l2c.overall_hits::cpu0.l2cache.prefetcher 43171 # number of overall hits
3124system.l2c.overall_hits::cpu1.dtb.walker 54 # number of overall hits
3125system.l2c.overall_hits::cpu1.itb.walker 50 # number of overall hits
3126system.l2c.overall_hits::cpu1.inst 17322 # number of overall hits
3127system.l2c.overall_hits::cpu1.data 13857 # number of overall hits
3128system.l2c.overall_hits::cpu1.l2cache.prefetcher 7539 # number of overall hits
3129system.l2c.overall_hits::total 164724 # number of overall hits
3130system.l2c.UpgradeReq_misses::cpu0.data 8230 # number of UpgradeReq misses
3131system.l2c.UpgradeReq_misses::cpu1.data 3781 # number of UpgradeReq misses
3132system.l2c.UpgradeReq_misses::total 12011 # number of UpgradeReq misses
3133system.l2c.SCUpgradeReq_misses::cpu0.data 840 # number of SCUpgradeReq misses
3134system.l2c.SCUpgradeReq_misses::cpu1.data 1148 # number of SCUpgradeReq misses
3135system.l2c.SCUpgradeReq_misses::total 1988 # number of SCUpgradeReq misses
3136system.l2c.ReadExReq_misses::cpu0.data 11269 # number of ReadExReq misses
3137system.l2c.ReadExReq_misses::cpu1.data 9058 # number of ReadExReq misses
3138system.l2c.ReadExReq_misses::total 20327 # number of ReadExReq misses
3139system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 25 # number of ReadSharedReq misses
3140system.l2c.ReadSharedReq_misses::cpu0.itb.walker 7 # number of ReadSharedReq misses
3141system.l2c.ReadSharedReq_misses::cpu0.inst 17264 # number of ReadSharedReq misses
3142system.l2c.ReadSharedReq_misses::cpu0.data 8071 # number of ReadSharedReq misses
3143system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 130238 # number of ReadSharedReq misses
3144system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 10 # number of ReadSharedReq misses
3145system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2 # number of ReadSharedReq misses
3146system.l2c.ReadSharedReq_misses::cpu1.inst 4969 # number of ReadSharedReq misses
3147system.l2c.ReadSharedReq_misses::cpu1.data 2483 # number of ReadSharedReq misses
3148system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 10791 # number of ReadSharedReq misses
3149system.l2c.ReadSharedReq_misses::total 173860 # number of ReadSharedReq misses
3150system.l2c.demand_misses::cpu0.dtb.walker 25 # number of demand (read+write) misses
3151system.l2c.demand_misses::cpu0.itb.walker 7 # number of demand (read+write) misses
3152system.l2c.demand_misses::cpu0.inst 17264 # number of demand (read+write) misses
3153system.l2c.demand_misses::cpu0.data 19340 # number of demand (read+write) misses
3154system.l2c.demand_misses::cpu0.l2cache.prefetcher 130238 # number of demand (read+write) misses
3155system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses
3156system.l2c.demand_misses::cpu1.itb.walker 2 # number of demand (read+write) misses
3157system.l2c.demand_misses::cpu1.inst 4969 # number of demand (read+write) misses
3158system.l2c.demand_misses::cpu1.data 11541 # number of demand (read+write) misses
3159system.l2c.demand_misses::cpu1.l2cache.prefetcher 10791 # number of demand (read+write) misses
3160system.l2c.demand_misses::total 194187 # number of demand (read+write) misses
3161system.l2c.overall_misses::cpu0.dtb.walker 25 # number of overall misses
3162system.l2c.overall_misses::cpu0.itb.walker 7 # number of overall misses
3163system.l2c.overall_misses::cpu0.inst 17264 # number of overall misses
3164system.l2c.overall_misses::cpu0.data 19340 # number of overall misses
3165system.l2c.overall_misses::cpu0.l2cache.prefetcher 130238 # number of overall misses
3166system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses
3167system.l2c.overall_misses::cpu1.itb.walker 2 # number of overall misses
3168system.l2c.overall_misses::cpu1.inst 4969 # number of overall misses
3169system.l2c.overall_misses::cpu1.data 11541 # number of overall misses
3170system.l2c.overall_misses::cpu1.l2cache.prefetcher 10791 # number of overall misses
3171system.l2c.overall_misses::total 194187 # number of overall misses
3172system.l2c.UpgradeReq_miss_latency::cpu0.data 7636500 # number of UpgradeReq miss cycles
3173system.l2c.UpgradeReq_miss_latency::cpu1.data 4088000 # number of UpgradeReq miss cycles
3174system.l2c.UpgradeReq_miss_latency::total 11724500 # number of UpgradeReq miss cycles
3175system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1275500 # number of SCUpgradeReq miss cycles
3176system.l2c.SCUpgradeReq_miss_latency::cpu1.data 739500 # number of SCUpgradeReq miss cycles
3177system.l2c.SCUpgradeReq_miss_latency::total 2015000 # number of SCUpgradeReq miss cycles
3178system.l2c.ReadExReq_miss_latency::cpu0.data 1086401000 # number of ReadExReq miss cycles
3179system.l2c.ReadExReq_miss_latency::cpu1.data 758222000 # number of ReadExReq miss cycles
3180system.l2c.ReadExReq_miss_latency::total 1844623000 # number of ReadExReq miss cycles
3181system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 2203000 # number of ReadSharedReq miss cycles
3182system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 699000 # number of ReadSharedReq miss cycles
3183system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1415731001 # number of ReadSharedReq miss cycles
3184system.l2c.ReadSharedReq_miss_latency::cpu0.data 721065000 # number of ReadSharedReq miss cycles
3185system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 14450210544 # number of ReadSharedReq miss cycles
3186system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 855000 # number of ReadSharedReq miss cycles
3187system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 165500 # number of ReadSharedReq miss cycles
3188system.l2c.ReadSharedReq_miss_latency::cpu1.inst 421639500 # number of ReadSharedReq miss cycles
3189system.l2c.ReadSharedReq_miss_latency::cpu1.data 224776000 # number of ReadSharedReq miss cycles
3190system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1455323289 # number of ReadSharedReq miss cycles
3191system.l2c.ReadSharedReq_miss_latency::total 18692667834 # number of ReadSharedReq miss cycles
3192system.l2c.demand_miss_latency::cpu0.dtb.walker 2203000 # number of demand (read+write) miss cycles
3193system.l2c.demand_miss_latency::cpu0.itb.walker 699000 # number of demand (read+write) miss cycles
3194system.l2c.demand_miss_latency::cpu0.inst 1415731001 # number of demand (read+write) miss cycles
3195system.l2c.demand_miss_latency::cpu0.data 1807466000 # number of demand (read+write) miss cycles
3196system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14450210544 # number of demand (read+write) miss cycles
3197system.l2c.demand_miss_latency::cpu1.dtb.walker 855000 # number of demand (read+write) miss cycles
3198system.l2c.demand_miss_latency::cpu1.itb.walker 165500 # number of demand (read+write) miss cycles
3199system.l2c.demand_miss_latency::cpu1.inst 421639500 # number of demand (read+write) miss cycles
3200system.l2c.demand_miss_latency::cpu1.data 982998000 # number of demand (read+write) miss cycles
3201system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1455323289 # number of demand (read+write) miss cycles
3202system.l2c.demand_miss_latency::total 20537290834 # number of demand (read+write) miss cycles
3203system.l2c.overall_miss_latency::cpu0.dtb.walker 2203000 # number of overall miss cycles
3204system.l2c.overall_miss_latency::cpu0.itb.walker 699000 # number of overall miss cycles
3205system.l2c.overall_miss_latency::cpu0.inst 1415731001 # number of overall miss cycles
3206system.l2c.overall_miss_latency::cpu0.data 1807466000 # number of overall miss cycles
3207system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14450210544 # number of overall miss cycles
3208system.l2c.overall_miss_latency::cpu1.dtb.walker 855000 # number of overall miss cycles
3209system.l2c.overall_miss_latency::cpu1.itb.walker 165500 # number of overall miss cycles
3210system.l2c.overall_miss_latency::cpu1.inst 421639500 # number of overall miss cycles
3211system.l2c.overall_miss_latency::cpu1.data 982998000 # number of overall miss cycles
3212system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1455323289 # number of overall miss cycles
3213system.l2c.overall_miss_latency::total 20537290834 # number of overall miss cycles
3214system.l2c.Writeback_accesses::writebacks 232311 # number of Writeback accesses(hits+misses)
3215system.l2c.Writeback_accesses::total 232311 # number of Writeback accesses(hits+misses)
3216system.l2c.UpgradeReq_accesses::cpu0.data 10684 # number of UpgradeReq accesses(hits+misses)
3217system.l2c.UpgradeReq_accesses::cpu1.data 4573 # number of UpgradeReq accesses(hits+misses)
3218system.l2c.UpgradeReq_accesses::total 15257 # number of UpgradeReq accesses(hits+misses)
3219system.l2c.SCUpgradeReq_accesses::cpu0.data 1087 # number of SCUpgradeReq accesses(hits+misses)
3220system.l2c.SCUpgradeReq_accesses::cpu1.data 1213 # number of SCUpgradeReq accesses(hits+misses)
3221system.l2c.SCUpgradeReq_accesses::total 2300 # number of SCUpgradeReq accesses(hits+misses)
3222system.l2c.ReadExReq_accesses::cpu0.data 15025 # number of ReadExReq accesses(hits+misses)
3223system.l2c.ReadExReq_accesses::cpu1.data 10920 # number of ReadExReq accesses(hits+misses)
3224system.l2c.ReadExReq_accesses::total 25945 # number of ReadExReq accesses(hits+misses)
3225system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 209 # number of ReadSharedReq accesses(hits+misses)
3226system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 96 # number of ReadSharedReq accesses(hits+misses)
3227system.l2c.ReadSharedReq_accesses::cpu0.inst 50604 # number of ReadSharedReq accesses(hits+misses)
3228system.l2c.ReadSharedReq_accesses::cpu0.data 53433 # number of ReadSharedReq accesses(hits+misses)
3229system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 173409 # number of ReadSharedReq accesses(hits+misses)
3230system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 64 # number of ReadSharedReq accesses(hits+misses)
3231system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 52 # number of ReadSharedReq accesses(hits+misses)
3232system.l2c.ReadSharedReq_accesses::cpu1.inst 22291 # number of ReadSharedReq accesses(hits+misses)
3233system.l2c.ReadSharedReq_accesses::cpu1.data 14478 # number of ReadSharedReq accesses(hits+misses)
3234system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 18330 # number of ReadSharedReq accesses(hits+misses)
3235system.l2c.ReadSharedReq_accesses::total 332966 # number of ReadSharedReq accesses(hits+misses)
3236system.l2c.demand_accesses::cpu0.dtb.walker 209 # number of demand (read+write) accesses
3237system.l2c.demand_accesses::cpu0.itb.walker 96 # number of demand (read+write) accesses
3238system.l2c.demand_accesses::cpu0.inst 50604 # number of demand (read+write) accesses
3239system.l2c.demand_accesses::cpu0.data 68458 # number of demand (read+write) accesses
3240system.l2c.demand_accesses::cpu0.l2cache.prefetcher 173409 # number of demand (read+write) accesses
3241system.l2c.demand_accesses::cpu1.dtb.walker 64 # number of demand (read+write) accesses
3242system.l2c.demand_accesses::cpu1.itb.walker 52 # number of demand (read+write) accesses
3243system.l2c.demand_accesses::cpu1.inst 22291 # number of demand (read+write) accesses
3244system.l2c.demand_accesses::cpu1.data 25398 # number of demand (read+write) accesses
3245system.l2c.demand_accesses::cpu1.l2cache.prefetcher 18330 # number of demand (read+write) accesses
3246system.l2c.demand_accesses::total 358911 # number of demand (read+write) accesses
3247system.l2c.overall_accesses::cpu0.dtb.walker 209 # number of overall (read+write) accesses
3248system.l2c.overall_accesses::cpu0.itb.walker 96 # number of overall (read+write) accesses
3249system.l2c.overall_accesses::cpu0.inst 50604 # number of overall (read+write) accesses
3250system.l2c.overall_accesses::cpu0.data 68458 # number of overall (read+write) accesses
3251system.l2c.overall_accesses::cpu0.l2cache.prefetcher 173409 # number of overall (read+write) accesses
3252system.l2c.overall_accesses::cpu1.dtb.walker 64 # number of overall (read+write) accesses
3253system.l2c.overall_accesses::cpu1.itb.walker 52 # number of overall (read+write) accesses
3254system.l2c.overall_accesses::cpu1.inst 22291 # number of overall (read+write) accesses
3255system.l2c.overall_accesses::cpu1.data 25398 # number of overall (read+write) accesses
3256system.l2c.overall_accesses::cpu1.l2cache.prefetcher 18330 # number of overall (read+write) accesses
3257system.l2c.overall_accesses::total 358911 # number of overall (read+write) accesses
3258system.l2c.UpgradeReq_miss_rate::cpu0.data 0.770311 # miss rate for UpgradeReq accesses
3259system.l2c.UpgradeReq_miss_rate::cpu1.data 0.826810 # miss rate for UpgradeReq accesses
3260system.l2c.UpgradeReq_miss_rate::total 0.787245 # miss rate for UpgradeReq accesses
3261system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.772769 # miss rate for SCUpgradeReq accesses
3262system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.946414 # miss rate for SCUpgradeReq accesses
3263system.l2c.SCUpgradeReq_miss_rate::total 0.864348 # miss rate for SCUpgradeReq accesses
3264system.l2c.ReadExReq_miss_rate::cpu0.data 0.750017 # miss rate for ReadExReq accesses
3265system.l2c.ReadExReq_miss_rate::cpu1.data 0.829487 # miss rate for ReadExReq accesses
3266system.l2c.ReadExReq_miss_rate::total 0.783465 # miss rate for ReadExReq accesses
3267system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.119617 # miss rate for ReadSharedReq accesses
3268system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.072917 # miss rate for ReadSharedReq accesses
3269system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.341159 # miss rate for ReadSharedReq accesses
3270system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.151049 # miss rate for ReadSharedReq accesses
3271system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.751045 # miss rate for ReadSharedReq accesses
3272system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.156250 # miss rate for ReadSharedReq accesses
3273system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.038462 # miss rate for ReadSharedReq accesses
3274system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.222915 # miss rate for ReadSharedReq accesses
3275system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.171502 # miss rate for ReadSharedReq accesses
3276system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.588707 # miss rate for ReadSharedReq accesses
3277system.l2c.ReadSharedReq_miss_rate::total 0.522155 # miss rate for ReadSharedReq accesses
3278system.l2c.demand_miss_rate::cpu0.dtb.walker 0.119617 # miss rate for demand accesses
3279system.l2c.demand_miss_rate::cpu0.itb.walker 0.072917 # miss rate for demand accesses
3280system.l2c.demand_miss_rate::cpu0.inst 0.341159 # miss rate for demand accesses
3281system.l2c.demand_miss_rate::cpu0.data 0.282509 # miss rate for demand accesses
3282system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.751045 # miss rate for demand accesses
3283system.l2c.demand_miss_rate::cpu1.dtb.walker 0.156250 # miss rate for demand accesses
3284system.l2c.demand_miss_rate::cpu1.itb.walker 0.038462 # miss rate for demand accesses
3285system.l2c.demand_miss_rate::cpu1.inst 0.222915 # miss rate for demand accesses
3286system.l2c.demand_miss_rate::cpu1.data 0.454406 # miss rate for demand accesses
3287system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.588707 # miss rate for demand accesses
3288system.l2c.demand_miss_rate::total 0.541045 # miss rate for demand accesses
3289system.l2c.overall_miss_rate::cpu0.dtb.walker 0.119617 # miss rate for overall accesses
3290system.l2c.overall_miss_rate::cpu0.itb.walker 0.072917 # miss rate for overall accesses
3291system.l2c.overall_miss_rate::cpu0.inst 0.341159 # miss rate for overall accesses
3292system.l2c.overall_miss_rate::cpu0.data 0.282509 # miss rate for overall accesses
3293system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.751045 # miss rate for overall accesses
3294system.l2c.overall_miss_rate::cpu1.dtb.walker 0.156250 # miss rate for overall accesses
3295system.l2c.overall_miss_rate::cpu1.itb.walker 0.038462 # miss rate for overall accesses
3296system.l2c.overall_miss_rate::cpu1.inst 0.222915 # miss rate for overall accesses
3297system.l2c.overall_miss_rate::cpu1.data 0.454406 # miss rate for overall accesses
3298system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.588707 # miss rate for overall accesses
3299system.l2c.overall_miss_rate::total 0.541045 # miss rate for overall accesses
3300system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 927.885784 # average UpgradeReq miss latency
3301system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1081.195451 # average UpgradeReq miss latency
3302system.l2c.UpgradeReq_avg_miss_latency::total 976.146865 # average UpgradeReq miss latency
3303system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1518.452381 # average SCUpgradeReq miss latency
3304system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 644.163763 # average SCUpgradeReq miss latency
3305system.l2c.SCUpgradeReq_avg_miss_latency::total 1013.581489 # average SCUpgradeReq miss latency
3306system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96406.158488 # average ReadExReq miss latency
3307system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83707.440936 # average ReadExReq miss latency
3308system.l2c.ReadExReq_avg_miss_latency::total 90747.429527 # average ReadExReq miss latency
3309system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 88120 # average ReadSharedReq miss latency
3310system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 99857.142857 # average ReadSharedReq miss latency
3311system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82004.807750 # average ReadSharedReq miss latency
3312system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 89340.230455 # average ReadSharedReq miss latency
3313system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 110952.337597 # average ReadSharedReq miss latency
3314system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 85500 # average ReadSharedReq miss latency
3315system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 82750 # average ReadSharedReq miss latency
3316system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 84853.994768 # average ReadSharedReq miss latency
3317system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90525.976641 # average ReadSharedReq miss latency
3318system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 134864.543508 # average ReadSharedReq miss latency
3319system.l2c.ReadSharedReq_avg_miss_latency::total 107515.632313 # average ReadSharedReq miss latency
3320system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88120 # average overall miss latency
3321system.l2c.demand_avg_miss_latency::cpu0.itb.walker 99857.142857 # average overall miss latency
3322system.l2c.demand_avg_miss_latency::cpu0.inst 82004.807750 # average overall miss latency
3323system.l2c.demand_avg_miss_latency::cpu0.data 93457.394002 # average overall miss latency
3324system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 110952.337597 # average overall miss latency
3325system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85500 # average overall miss latency
3326system.l2c.demand_avg_miss_latency::cpu1.itb.walker 82750 # average overall miss latency
3327system.l2c.demand_avg_miss_latency::cpu1.inst 84853.994768 # average overall miss latency
3328system.l2c.demand_avg_miss_latency::cpu1.data 85174.421627 # average overall miss latency
3329system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134864.543508 # average overall miss latency
3330system.l2c.demand_avg_miss_latency::total 105760.379603 # average overall miss latency
3331system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88120 # average overall miss latency
3332system.l2c.overall_avg_miss_latency::cpu0.itb.walker 99857.142857 # average overall miss latency
3333system.l2c.overall_avg_miss_latency::cpu0.inst 82004.807750 # average overall miss latency
3334system.l2c.overall_avg_miss_latency::cpu0.data 93457.394002 # average overall miss latency
3335system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 110952.337597 # average overall miss latency
3336system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85500 # average overall miss latency
3337system.l2c.overall_avg_miss_latency::cpu1.itb.walker 82750 # average overall miss latency
3338system.l2c.overall_avg_miss_latency::cpu1.inst 84853.994768 # average overall miss latency
3339system.l2c.overall_avg_miss_latency::cpu1.data 85174.421627 # average overall miss latency
3340system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134864.543508 # average overall miss latency
3341system.l2c.overall_avg_miss_latency::total 105760.379603 # average overall miss latency
3342system.l2c.blocked_cycles::no_mshrs 1319 # number of cycles access was blocked
3343system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
3344system.l2c.blocked::no_mshrs 21 # number of cycles access was blocked
3345system.l2c.blocked::no_targets 0 # number of cycles access was blocked
3346system.l2c.avg_blocked_cycles::no_mshrs 62.809524 # average number of cycles each access was blocked
3347system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3348system.l2c.fast_writes 0 # number of fast writes performed
3349system.l2c.cache_copies 0 # number of cache copies performed
3350system.l2c.writebacks::writebacks 104474 # number of writebacks
3351system.l2c.writebacks::total 104474 # number of writebacks
3352system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits
3353system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 10 # number of ReadSharedReq MSHR hits
3354system.l2c.ReadSharedReq_mshr_hits::total 15 # number of ReadSharedReq MSHR hits
3355system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits
3356system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits
3357system.l2c.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits
3358system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits
3359system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits
3360system.l2c.overall_mshr_hits::total 15 # number of overall MSHR hits
3361system.l2c.CleanEvict_mshr_misses::writebacks 3557 # number of CleanEvict MSHR misses
3362system.l2c.CleanEvict_mshr_misses::total 3557 # number of CleanEvict MSHR misses
3363system.l2c.UpgradeReq_mshr_misses::cpu0.data 8230 # number of UpgradeReq MSHR misses
3364system.l2c.UpgradeReq_mshr_misses::cpu1.data 3781 # number of UpgradeReq MSHR misses
3365system.l2c.UpgradeReq_mshr_misses::total 12011 # number of UpgradeReq MSHR misses
3366system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 840 # number of SCUpgradeReq MSHR misses
3367system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1148 # number of SCUpgradeReq MSHR misses
3368system.l2c.SCUpgradeReq_mshr_misses::total 1988 # number of SCUpgradeReq MSHR misses
3369system.l2c.ReadExReq_mshr_misses::cpu0.data 11269 # number of ReadExReq MSHR misses
3370system.l2c.ReadExReq_mshr_misses::cpu1.data 9058 # number of ReadExReq MSHR misses
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3372system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 25 # number of ReadSharedReq MSHR misses
3373system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 7 # number of ReadSharedReq MSHR misses
3374system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17259 # number of ReadSharedReq MSHR misses
3375system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8071 # number of ReadSharedReq MSHR misses
3376system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 130238 # number of ReadSharedReq MSHR misses
3377system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadSharedReq MSHR misses
3378system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2 # number of ReadSharedReq MSHR misses
3379system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 4959 # number of ReadSharedReq MSHR misses
3380system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2483 # number of ReadSharedReq MSHR misses
3381system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 10791 # number of ReadSharedReq MSHR misses
3382system.l2c.ReadSharedReq_mshr_misses::total 173845 # number of ReadSharedReq MSHR misses
3383system.l2c.demand_mshr_misses::cpu0.dtb.walker 25 # number of demand (read+write) MSHR misses
3384system.l2c.demand_mshr_misses::cpu0.itb.walker 7 # number of demand (read+write) MSHR misses
3385system.l2c.demand_mshr_misses::cpu0.inst 17259 # number of demand (read+write) MSHR misses
3386system.l2c.demand_mshr_misses::cpu0.data 19340 # number of demand (read+write) MSHR misses
3387system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 130238 # number of demand (read+write) MSHR misses
3388system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses
3389system.l2c.demand_mshr_misses::cpu1.itb.walker 2 # number of demand (read+write) MSHR misses
3390system.l2c.demand_mshr_misses::cpu1.inst 4959 # number of demand (read+write) MSHR misses
3391system.l2c.demand_mshr_misses::cpu1.data 11541 # number of demand (read+write) MSHR misses
3392system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 10791 # number of demand (read+write) MSHR misses
3393system.l2c.demand_mshr_misses::total 194172 # number of demand (read+write) MSHR misses
3394system.l2c.overall_mshr_misses::cpu0.dtb.walker 25 # number of overall MSHR misses
3395system.l2c.overall_mshr_misses::cpu0.itb.walker 7 # number of overall MSHR misses
3396system.l2c.overall_mshr_misses::cpu0.inst 17259 # number of overall MSHR misses
3397system.l2c.overall_mshr_misses::cpu0.data 19340 # number of overall MSHR misses
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3403system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 10791 # number of overall MSHR misses
3404system.l2c.overall_mshr_misses::total 194172 # number of overall MSHR misses
3405system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable
3406system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29394 # number of ReadReq MSHR uncacheable
3407system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable
3408system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5600 # number of ReadReq MSHR uncacheable
3409system.l2c.ReadReq_mshr_uncacheable::total 38100 # number of ReadReq MSHR uncacheable
3410system.l2c.WriteReq_mshr_uncacheable::cpu0.data 26127 # number of WriteReq MSHR uncacheable
3411system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4908 # number of WriteReq MSHR uncacheable
3412system.l2c.WriteReq_mshr_uncacheable::total 31035 # number of WriteReq MSHR uncacheable
3413system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses
3414system.l2c.overall_mshr_uncacheable_misses::cpu0.data 55521 # number of overall MSHR uncacheable misses
3415system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses
3416system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10508 # number of overall MSHR uncacheable misses
3417system.l2c.overall_mshr_uncacheable_misses::total 69135 # number of overall MSHR uncacheable misses
3418system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 170692500 # number of UpgradeReq MSHR miss cycles
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3421system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 17547003 # number of SCUpgradeReq MSHR miss cycles
3422system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23836000 # number of SCUpgradeReq MSHR miss cycles
3423system.l2c.SCUpgradeReq_mshr_miss_latency::total 41383003 # number of SCUpgradeReq MSHR miss cycles
3424system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 973711000 # number of ReadExReq MSHR miss cycles
3425system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 667642000 # number of ReadExReq MSHR miss cycles
3426system.l2c.ReadExReq_mshr_miss_latency::total 1641353000 # number of ReadExReq MSHR miss cycles
3427system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 1953000 # number of ReadSharedReq MSHR miss cycles
3428system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 629000 # number of ReadSharedReq MSHR miss cycles
3429system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1242953501 # number of ReadSharedReq MSHR miss cycles
3430system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 640355000 # number of ReadSharedReq MSHR miss cycles
3431system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13147830544 # number of ReadSharedReq MSHR miss cycles
3432system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 755000 # number of ReadSharedReq MSHR miss cycles
3433system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 145500 # number of ReadSharedReq MSHR miss cycles
3434system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 371358500 # number of ReadSharedReq MSHR miss cycles
3435system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 199946000 # number of ReadSharedReq MSHR miss cycles
3436system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1347413289 # number of ReadSharedReq MSHR miss cycles
3437system.l2c.ReadSharedReq_mshr_miss_latency::total 16953339334 # number of ReadSharedReq MSHR miss cycles
3438system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1953000 # number of demand (read+write) MSHR miss cycles
3439system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 629000 # number of demand (read+write) MSHR miss cycles
3440system.l2c.demand_mshr_miss_latency::cpu0.inst 1242953501 # number of demand (read+write) MSHR miss cycles
3441system.l2c.demand_mshr_miss_latency::cpu0.data 1614066000 # number of demand (read+write) MSHR miss cycles
3442system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13147830544 # number of demand (read+write) MSHR miss cycles
3443system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 755000 # number of demand (read+write) MSHR miss cycles
3444system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 145500 # number of demand (read+write) MSHR miss cycles
3445system.l2c.demand_mshr_miss_latency::cpu1.inst 371358500 # number of demand (read+write) MSHR miss cycles
3446system.l2c.demand_mshr_miss_latency::cpu1.data 867588000 # number of demand (read+write) MSHR miss cycles
3447system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1347413289 # number of demand (read+write) MSHR miss cycles
3448system.l2c.demand_mshr_miss_latency::total 18594692334 # number of demand (read+write) MSHR miss cycles
3449system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1953000 # number of overall MSHR miss cycles
3450system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 629000 # number of overall MSHR miss cycles
3451system.l2c.overall_mshr_miss_latency::cpu0.inst 1242953501 # number of overall MSHR miss cycles
3452system.l2c.overall_mshr_miss_latency::cpu0.data 1614066000 # number of overall MSHR miss cycles
3453system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13147830544 # number of overall MSHR miss cycles
3454system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 755000 # number of overall MSHR miss cycles
3455system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 145500 # number of overall MSHR miss cycles
3456system.l2c.overall_mshr_miss_latency::cpu1.inst 371358500 # number of overall MSHR miss cycles
3457system.l2c.overall_mshr_miss_latency::cpu1.data 867588000 # number of overall MSHR miss cycles
3458system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1347413289 # number of overall MSHR miss cycles
3459system.l2c.overall_mshr_miss_latency::total 18594692334 # number of overall MSHR miss cycles
3460system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 189269500 # number of ReadReq MSHR uncacheable cycles
3461system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4916712000 # number of ReadReq MSHR uncacheable cycles
3462system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5992000 # number of ReadReq MSHR uncacheable cycles
3463system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 843515500 # number of ReadReq MSHR uncacheable cycles
3464system.l2c.ReadReq_mshr_uncacheable_latency::total 5955489000 # number of ReadReq MSHR uncacheable cycles
3465system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3669260542 # number of WriteReq MSHR uncacheable cycles
3466system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 737586502 # number of WriteReq MSHR uncacheable cycles
3467system.l2c.WriteReq_mshr_uncacheable_latency::total 4406847044 # number of WriteReq MSHR uncacheable cycles
3468system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 189269500 # number of overall MSHR uncacheable cycles
3469system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8585972542 # number of overall MSHR uncacheable cycles
3470system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5992000 # number of overall MSHR uncacheable cycles
3471system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1581102002 # number of overall MSHR uncacheable cycles
3472system.l2c.overall_mshr_uncacheable_latency::total 10362336044 # number of overall MSHR uncacheable cycles
3473system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3474system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3475system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.770311 # mshr miss rate for UpgradeReq accesses
3476system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.826810 # mshr miss rate for UpgradeReq accesses
3477system.l2c.UpgradeReq_mshr_miss_rate::total 0.787245 # mshr miss rate for UpgradeReq accesses
3478system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.772769 # mshr miss rate for SCUpgradeReq accesses
3479system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.946414 # mshr miss rate for SCUpgradeReq accesses
3480system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.864348 # mshr miss rate for SCUpgradeReq accesses
3481system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.750017 # mshr miss rate for ReadExReq accesses
3482system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.829487 # mshr miss rate for ReadExReq accesses
3483system.l2c.ReadExReq_mshr_miss_rate::total 0.783465 # mshr miss rate for ReadExReq accesses
3484system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.119617 # mshr miss rate for ReadSharedReq accesses
3485system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.072917 # mshr miss rate for ReadSharedReq accesses
3486system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.341060 # mshr miss rate for ReadSharedReq accesses
3487system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.151049 # mshr miss rate for ReadSharedReq accesses
3488system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.751045 # mshr miss rate for ReadSharedReq accesses
3489system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.156250 # mshr miss rate for ReadSharedReq accesses
3490system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.038462 # mshr miss rate for ReadSharedReq accesses
3491system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.222466 # mshr miss rate for ReadSharedReq accesses
3492system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.171502 # mshr miss rate for ReadSharedReq accesses
3493system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.588707 # mshr miss rate for ReadSharedReq accesses
3494system.l2c.ReadSharedReq_mshr_miss_rate::total 0.522110 # mshr miss rate for ReadSharedReq accesses
3495system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.119617 # mshr miss rate for demand accesses
3496system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.072917 # mshr miss rate for demand accesses
3497system.l2c.demand_mshr_miss_rate::cpu0.inst 0.341060 # mshr miss rate for demand accesses
3498system.l2c.demand_mshr_miss_rate::cpu0.data 0.282509 # mshr miss rate for demand accesses
3499system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.751045 # mshr miss rate for demand accesses
3500system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.156250 # mshr miss rate for demand accesses
3501system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.038462 # mshr miss rate for demand accesses
3502system.l2c.demand_mshr_miss_rate::cpu1.inst 0.222466 # mshr miss rate for demand accesses
3503system.l2c.demand_mshr_miss_rate::cpu1.data 0.454406 # mshr miss rate for demand accesses
3504system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.588707 # mshr miss rate for demand accesses
3505system.l2c.demand_mshr_miss_rate::total 0.541003 # mshr miss rate for demand accesses
3506system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.119617 # mshr miss rate for overall accesses
3507system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.072917 # mshr miss rate for overall accesses
3508system.l2c.overall_mshr_miss_rate::cpu0.inst 0.341060 # mshr miss rate for overall accesses
3509system.l2c.overall_mshr_miss_rate::cpu0.data 0.282509 # mshr miss rate for overall accesses
3510system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.751045 # mshr miss rate for overall accesses
3511system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.156250 # mshr miss rate for overall accesses
3512system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.038462 # mshr miss rate for overall accesses
3513system.l2c.overall_mshr_miss_rate::cpu1.inst 0.222466 # mshr miss rate for overall accesses
3514system.l2c.overall_mshr_miss_rate::cpu1.data 0.454406 # mshr miss rate for overall accesses
3515system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.588707 # mshr miss rate for overall accesses
3516system.l2c.overall_mshr_miss_rate::total 0.541003 # mshr miss rate for overall accesses
3517system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20740.279465 # average UpgradeReq mshr miss latency
3518system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20737.900026 # average UpgradeReq mshr miss latency
3519system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20739.530430 # average UpgradeReq mshr miss latency
3520system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20889.289286 # average SCUpgradeReq mshr miss latency
3521system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20763.066202 # average SCUpgradeReq mshr miss latency
3522system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20816.399899 # average SCUpgradeReq mshr miss latency
3523system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 86406.158488 # average ReadExReq mshr miss latency
3524system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73707.440936 # average ReadExReq mshr miss latency
3525system.l2c.ReadExReq_avg_mshr_miss_latency::total 80747.429527 # average ReadExReq mshr miss latency
3526system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 78120 # average ReadSharedReq mshr miss latency
3527system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 89857.142857 # average ReadSharedReq mshr miss latency
3528system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72017.700968 # average ReadSharedReq mshr miss latency
3529system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79340.230455 # average ReadSharedReq mshr miss latency
3530system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 100952.337597 # average ReadSharedReq mshr miss latency
3531system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 75500 # average ReadSharedReq mshr miss latency
3532system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 72750 # average ReadSharedReq mshr miss latency
3533system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74885.763259 # average ReadSharedReq mshr miss latency
3534system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80525.976641 # average ReadSharedReq mshr miss latency
3535system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124864.543508 # average ReadSharedReq mshr miss latency
3536system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97519.855814 # average ReadSharedReq mshr miss latency
3537system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78120 # average overall mshr miss latency
3538system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 89857.142857 # average overall mshr miss latency
3539system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72017.700968 # average overall mshr miss latency
3540system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83457.394002 # average overall mshr miss latency
3541system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 100952.337597 # average overall mshr miss latency
3542system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75500 # average overall mshr miss latency
3543system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 72750 # average overall mshr miss latency
3544system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74885.763259 # average overall mshr miss latency
3545system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75174.421627 # average overall mshr miss latency
3546system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124864.543508 # average overall mshr miss latency
3547system.l2c.demand_avg_mshr_miss_latency::total 95764.025369 # average overall mshr miss latency
3548system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78120 # average overall mshr miss latency
3549system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 89857.142857 # average overall mshr miss latency
3550system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72017.700968 # average overall mshr miss latency
3551system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83457.394002 # average overall mshr miss latency
3552system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 100952.337597 # average overall mshr miss latency
3553system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75500 # average overall mshr miss latency
3554system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 72750 # average overall mshr miss latency
3555system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74885.763259 # average overall mshr miss latency
3556system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75174.421627 # average overall mshr miss latency
3557system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124864.543508 # average overall mshr miss latency
3558system.l2c.overall_avg_mshr_miss_latency::total 95764.025369 # average overall mshr miss latency
3559system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63005.825566 # average ReadReq mshr uncacheable latency
3560system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167269.238620 # average ReadReq mshr uncacheable latency
3561system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58745.098039 # average ReadReq mshr uncacheable latency
3562system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150627.767857 # average ReadReq mshr uncacheable latency
3563system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 156312.047244 # average ReadReq mshr uncacheable latency
3564system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 140439.412944 # average WriteReq mshr uncacheable latency
3565system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150282.498370 # average WriteReq mshr uncacheable latency
3566system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141996.038150 # average WriteReq mshr uncacheable latency
3567system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63005.825566 # average overall mshr uncacheable latency
3568system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 154643.694134 # average overall mshr uncacheable latency
3569system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58745.098039 # average overall mshr uncacheable latency
3570system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 150466.501903 # average overall mshr uncacheable latency
3571system.l2c.overall_avg_mshr_uncacheable_latency::total 149885.528951 # average overall mshr uncacheable latency
3572system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
3573system.membus.trans_dist::ReadReq 38100 # Transaction distribution
3574system.membus.trans_dist::ReadResp 212196 # Transaction distribution
3575system.membus.trans_dist::WriteReq 31035 # Transaction distribution
3576system.membus.trans_dist::WriteResp 31035 # Transaction distribution
3577system.membus.trans_dist::Writeback 140680 # Transaction distribution
3578system.membus.trans_dist::CleanEvict 16716 # Transaction distribution
3579system.membus.trans_dist::UpgradeReq 77066 # Transaction distribution
3580system.membus.trans_dist::SCUpgradeReq 41581 # Transaction distribution
3581system.membus.trans_dist::UpgradeResp 14111 # Transaction distribution
3582system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
3583system.membus.trans_dist::ReadExReq 40212 # Transaction distribution
3584system.membus.trans_dist::ReadExResp 20215 # Transaction distribution
3585system.membus.trans_dist::ReadSharedReq 174097 # Transaction distribution
3586system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
3587system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
3588system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes)
3589system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes)
3590system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14206 # Packet count per connected master and slave (bytes)
3591system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 677829 # Packet count per connected master and slave (bytes)
3592system.membus.pkt_count_system.l2c.mem_side::total 799987 # Packet count per connected master and slave (bytes)
3593system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108934 # Packet count per connected master and slave (bytes)
3594system.membus.pkt_count_system.iocache.mem_side::total 108934 # Packet count per connected master and slave (bytes)
3595system.membus.pkt_count::total 908921 # Packet count per connected master and slave (bytes)
3596system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162793 # Cumulative packet size per connected master and slave (bytes)
3597system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes)
3598system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28412 # Cumulative packet size per connected master and slave (bytes)
3599system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19154168 # Cumulative packet size per connected master and slave (bytes)
3600system.membus.pkt_size_system.l2c.mem_side::total 19345693 # Cumulative packet size per connected master and slave (bytes)
3601system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
3602system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
3603system.membus.pkt_size::total 21663837 # Cumulative packet size per connected master and slave (bytes)
3604system.membus.snoops 125106 # Total snoops (count)
3605system.membus.snoop_fanout::samples 595969 # Request fanout histogram
3606system.membus.snoop_fanout::mean 1 # Request fanout histogram
3607system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3608system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3609system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3610system.membus.snoop_fanout::1 595969 100.00% 100.00% # Request fanout histogram
3611system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3612system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3613system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3614system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3615system.membus.snoop_fanout::total 595969 # Request fanout histogram
3616system.membus.reqLayer0.occupancy 81639500 # Layer occupancy (ticks)
3617system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3618system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks)
3619system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3620system.membus.reqLayer2.occupancy 11797490 # Layer occupancy (ticks)
3621system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3622system.membus.reqLayer5.occupancy 1030129184 # Layer occupancy (ticks)
3623system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3624system.membus.respLayer2.occupancy 1147298884 # Layer occupancy (ticks)
3625system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3626system.membus.respLayer3.occupancy 64422049 # Layer occupancy (ticks)
3627system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3628system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3629system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
3630system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
3631system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
3632system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
3633system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
3634system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR

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3651system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
3652system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3653system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3654system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
3655system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3656system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
3657system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
3658system.realview.ethernet.droppedPackets 0 # number of packets dropped
3659system.toL2Bus.trans_dist::ReadReq 38103 # Transaction distribution
3660system.toL2Bus.trans_dist::ReadResp 495292 # Transaction distribution
3661system.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution
3662system.toL2Bus.trans_dist::WriteResp 31035 # Transaction distribution
3663system.toL2Bus.trans_dist::Writeback 373006 # Transaction distribution
3664system.toL2Bus.trans_dist::CleanEvict 88968 # Transaction distribution
3665system.toL2Bus.trans_dist::UpgradeReq 80200 # Transaction distribution
3666system.toL2Bus.trans_dist::SCUpgradeReq 41893 # Transaction distribution
3667system.toL2Bus.trans_dist::UpgradeResp 122093 # Transaction distribution
3668system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution
3669system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
3670system.toL2Bus.trans_dist::ReadExReq 50895 # Transaction distribution
3671system.toL2Bus.trans_dist::ReadExResp 50895 # Transaction distribution
3672system.toL2Bus.trans_dist::ReadSharedReq 457205 # Transaction distribution
3673system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
3674system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1082088 # Packet count per connected master and slave (bytes)
3675system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 352339 # Packet count per connected master and slave (bytes)
3676system.toL2Bus.pkt_count::total 1434427 # Packet count per connected master and slave (bytes)
3677system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31351112 # Cumulative packet size per connected master and slave (bytes)
3678system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6763093 # Cumulative packet size per connected master and slave (bytes)
3679system.toL2Bus.pkt_size::total 38114205 # Cumulative packet size per connected master and slave (bytes)
3680system.toL2Bus.snoops 462700 # Total snoops (count)
3681system.toL2Bus.snoop_fanout::samples 1239270 # Request fanout histogram
3682system.toL2Bus.snoop_fanout::mean 1.168619 # Request fanout histogram
3683system.toL2Bus.snoop_fanout::stdev 0.374415 # Request fanout histogram
3684system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3685system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3686system.toL2Bus.snoop_fanout::1 1030306 83.14% 83.14% # Request fanout histogram
3687system.toL2Bus.snoop_fanout::2 208964 16.86% 100.00% # Request fanout histogram
3688system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3689system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
3690system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3691system.toL2Bus.snoop_fanout::total 1239270 # Request fanout histogram
3692system.toL2Bus.reqLayer0.occupancy 822017005 # Layer occupancy (ticks)
3693system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3694system.toL2Bus.snoopLayer0.occupancy 355500 # Layer occupancy (ticks)
3695system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3696system.toL2Bus.respLayer0.occupancy 615196241 # Layer occupancy (ticks)
3697system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3698system.toL2Bus.respLayer1.occupancy 261600624 # Layer occupancy (ticks)
3699system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3700system.cpu0.kern.inst.arm 0 # number of arm instructions executed
3701system.cpu0.kern.inst.quiesce 2069 # number of quiesce instructions executed
3702system.cpu1.kern.inst.arm 0 # number of arm instructions executed
3703system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed
3704
3705---------- End Simulation Statistics ----------