1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.621647 # Number of seconds simulated
4sim_ticks 2621647051000 # Number of ticks simulated
5final_tick 2621647051000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 56801 # Simulator instruction rate (inst/s)
8host_op_rate 68443 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2377539464 # Simulator tick rate (ticks/s)
10host_mem_usage 411700 # Number of bytes of host memory used
11host_seconds 1102.67 # Real time elapsed on the host
12sim_insts 62632896 # Number of instructions simulated
13sim_ops 75470296 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.inst 516048 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.data 6568572 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.inst 301968 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.data 2981560 # Number of bytes read from this memory
24system.physmem.bytes_read::total 131479316 # Number of bytes read from this memory
25system.physmem.bytes_inst_read::cpu0.inst 516048 # Number of instructions bytes read from this memory
26system.physmem.bytes_inst_read::cpu1.inst 301968 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::total 818016 # Number of instructions bytes read from this memory
28system.physmem.bytes_written::writebacks 4189696 # Number of bytes written to this memory
29system.physmem.bytes_written::cpu0.data 3029096 # Number of bytes written to this memory
30system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
31system.physmem.bytes_written::total 7218832 # Number of bytes written to this memory
32system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.inst 10590 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.data 102693 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu1.inst 4761 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu1.data 46605 # Number of read requests responded to by this memory
40system.physmem.num_reads::total 15303475 # Number of read requests responded to by this memory
41system.physmem.num_writes::writebacks 65464 # Number of write requests responded to by this memory
42system.physmem.num_writes::cpu0.data 757274 # Number of write requests responded to by this memory
43system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
44system.physmem.num_writes::total 822748 # Number of write requests responded to by this memory
45system.physmem.bw_read::realview.clcd 46196351 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu0.dtb.walker 171 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::cpu0.inst 196841 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_read::cpu0.data 2505513 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu1.inst 115183 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu1.data 1137285 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::total 50151418 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_inst_read::cpu0.inst 196841 # Instruction read bandwidth from this memory (bytes/s)
55system.physmem.bw_inst_read::cpu1.inst 115183 # Instruction read bandwidth from this memory (bytes/s)
56system.physmem.bw_inst_read::total 312024 # Instruction read bandwidth from this memory (bytes/s)
57system.physmem.bw_write::writebacks 1598116 # Write bandwidth from this memory (bytes/s)
58system.physmem.bw_write::cpu0.data 1155417 # Write bandwidth from this memory (bytes/s)
59system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s)
60system.physmem.bw_write::total 2753548 # Write bandwidth from this memory (bytes/s)
61system.physmem.bw_total::writebacks 1598116 # Total bandwidth to/from this memory (bytes/s)
62system.physmem.bw_total::realview.clcd 46196351 # Total bandwidth to/from this memory (bytes/s)
63system.physmem.bw_total::cpu0.dtb.walker 171 # Total bandwidth to/from this memory (bytes/s)
64system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
65system.physmem.bw_total::cpu0.inst 196841 # Total bandwidth to/from this memory (bytes/s)
66system.physmem.bw_total::cpu0.data 3660931 # Total bandwidth to/from this memory (bytes/s)
67system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::cpu1.inst 115183 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu1.data 1137300 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::total 52904966 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.readReqs 15303475 # Number of read requests accepted
72system.physmem.writeReqs 822748 # Number of write requests accepted
73system.physmem.readBursts 15303475 # Number of DRAM read bursts, including those serviced by the write queue
74system.physmem.writeBursts 822748 # Number of DRAM write bursts, including those merged in the write queue
75system.physmem.bytesReadDRAM 977402304 # Total number of bytes read from DRAM
76system.physmem.bytesReadWrQ 2020096 # Total number of bytes read from write queue
77system.physmem.bytesWritten 7239040 # Total number of bytes written to DRAM
78system.physmem.bytesReadSys 131479316 # Total read bytes from the system interface side
79system.physmem.bytesWrittenSys 7218832 # Total written bytes from the system interface side
80system.physmem.servicedByWrQ 31564 # Number of DRAM read bursts serviced by the write queue
81system.physmem.mergedWrBursts 709609 # Number of DRAM write bursts merged with an existing one
82system.physmem.neitherReadNorWriteReqs 12033 # Number of requests that are neither read nor write
83system.physmem.perBankRdBursts::0 956536 # Per bank write bursts
84system.physmem.perBankRdBursts::1 956505 # Per bank write bursts
85system.physmem.perBankRdBursts::2 953083 # Per bank write bursts
86system.physmem.perBankRdBursts::3 951219 # Per bank write bursts
87system.physmem.perBankRdBursts::4 959451 # Per bank write bursts
88system.physmem.perBankRdBursts::5 955886 # Per bank write bursts
89system.physmem.perBankRdBursts::6 953593 # Per bank write bursts
90system.physmem.perBankRdBursts::7 950807 # Per bank write bursts
91system.physmem.perBankRdBursts::8 956024 # Per bank write bursts
92system.physmem.perBankRdBursts::9 956507 # Per bank write bursts
93system.physmem.perBankRdBursts::10 953309 # Per bank write bursts
94system.physmem.perBankRdBursts::11 950948 # Per bank write bursts
95system.physmem.perBankRdBursts::12 956403 # Per bank write bursts
96system.physmem.perBankRdBursts::13 956390 # Per bank write bursts
97system.physmem.perBankRdBursts::14 954120 # Per bank write bursts
98system.physmem.perBankRdBursts::15 951130 # Per bank write bursts
99system.physmem.perBankWrBursts::0 7301 # Per bank write bursts
100system.physmem.perBankWrBursts::1 7301 # Per bank write bursts
101system.physmem.perBankWrBursts::2 6635 # Per bank write bursts
102system.physmem.perBankWrBursts::3 6826 # Per bank write bursts
103system.physmem.perBankWrBursts::4 7245 # Per bank write bursts
104system.physmem.perBankWrBursts::5 6961 # Per bank write bursts
105system.physmem.perBankWrBursts::6 7187 # Per bank write bursts
106system.physmem.perBankWrBursts::7 6869 # Per bank write bursts
107system.physmem.perBankWrBursts::8 6823 # Per bank write bursts
108system.physmem.perBankWrBursts::9 7301 # Per bank write bursts
109system.physmem.perBankWrBursts::10 6956 # Per bank write bursts
110system.physmem.perBankWrBursts::11 6738 # Per bank write bursts
111system.physmem.perBankWrBursts::12 7232 # Per bank write bursts
112system.physmem.perBankWrBursts::13 7102 # Per bank write bursts
113system.physmem.perBankWrBursts::14 7378 # Per bank write bursts
114system.physmem.perBankWrBursts::15 7255 # Per bank write bursts
115system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
116system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
117system.physmem.totGap 2621645657000 # Total gap between requests
118system.physmem.readPktSize::0 0 # Read request sizes (log2)
119system.physmem.readPktSize::1 0 # Read request sizes (log2)
120system.physmem.readPktSize::2 59 # Read request sizes (log2)
121system.physmem.readPktSize::3 15138841 # Read request sizes (log2)
122system.physmem.readPktSize::4 3426 # Read request sizes (log2)
123system.physmem.readPktSize::5 0 # Read request sizes (log2)
124system.physmem.readPktSize::6 161149 # Read request sizes (log2)
125system.physmem.writePktSize::0 0 # Write request sizes (log2)
126system.physmem.writePktSize::1 0 # Write request sizes (log2)
127system.physmem.writePktSize::2 757284 # Write request sizes (log2)
128system.physmem.writePktSize::3 0 # Write request sizes (log2)
129system.physmem.writePktSize::4 0 # Write request sizes (log2)
130system.physmem.writePktSize::5 0 # Write request sizes (log2)
131system.physmem.writePktSize::6 65464 # Write request sizes (log2)
132system.physmem.rdQLenPdf::0 1118217 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::1 965108 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::2 965171 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::3 1074431 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::4 973448 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::5 1034951 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::6 2682221 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::7 2590422 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::8 3372339 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::9 127125 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::10 110466 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::11 101918 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::12 97549 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::13 20170 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::14 19294 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::15 19015 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::16 55 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
164system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::15 2804 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::16 3130 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::17 5680 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::18 6732 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::19 6830 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::20 6759 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::21 6721 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::22 7049 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::23 6856 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::24 6815 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::25 6768 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::26 6678 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::27 6706 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::28 6721 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::29 6692 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::30 6660 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::31 6669 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::32 6637 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::33 96 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::34 62 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::35 41 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::36 13 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
228system.physmem.bytesPerActivate::samples 1014826 # Bytes accessed per row activation
229system.physmem.bytesPerActivate::mean 970.256324 # Bytes accessed per row activation
230system.physmem.bytesPerActivate::gmean 901.955292 # Bytes accessed per row activation
231system.physmem.bytesPerActivate::stdev 206.811149 # Bytes accessed per row activation
232system.physmem.bytesPerActivate::0-127 24748 2.44% 2.44% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::128-255 20792 2.05% 4.49% # Bytes accessed per row activation
234system.physmem.bytesPerActivate::256-383 9109 0.90% 5.39% # Bytes accessed per row activation
235system.physmem.bytesPerActivate::384-511 2441 0.24% 5.63% # Bytes accessed per row activation
236system.physmem.bytesPerActivate::512-639 2631 0.26% 5.88% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::640-767 1759 0.17% 6.06% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::768-895 9074 0.89% 6.95% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::896-1023 1088 0.11% 7.06% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::1024-1151 943184 92.94% 100.00% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::total 1014826 # Bytes accessed per row activation
242system.physmem.rdPerTurnAround::samples 6619 # Reads before turning the bus around for writes
243system.physmem.rdPerTurnAround::mean 2307.281009 # Reads before turning the bus around for writes
244system.physmem.rdPerTurnAround::stdev 96810.313262 # Reads before turning the bus around for writes
245system.physmem.rdPerTurnAround::0-262143 6612 99.89% 99.89% # Reads before turning the bus around for writes
246system.physmem.rdPerTurnAround::262144-524287 1 0.02% 99.91% # Reads before turning the bus around for writes
247system.physmem.rdPerTurnAround::524288-786431 1 0.02% 99.92% # Reads before turning the bus around for writes
248system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.02% 99.94% # Reads before turning the bus around for writes
249system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 2 0.03% 99.97% # Reads before turning the bus around for writes
250system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
251system.physmem.rdPerTurnAround::7.34003e+06-7.60218e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
252system.physmem.rdPerTurnAround::total 6619 # Reads before turning the bus around for writes
253system.physmem.wrPerTurnAround::samples 6619 # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::mean 17.088684 # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::gmean 17.037372 # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::stdev 1.359683 # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::16 3686 55.69% 55.69% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::17 52 0.79% 56.47% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::18 1827 27.60% 84.08% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::19 927 14.01% 98.08% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::20 37 0.56% 98.64% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::21 27 0.41% 99.05% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::22 28 0.42% 99.47% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::23 21 0.32% 99.79% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::24 11 0.17% 99.95% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::28 2 0.03% 100.00% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::total 6619 # Writes before turning the bus around for reads
269system.physmem.totQLat 395207982750 # Total ticks spent queuing
270system.physmem.totMemAccLat 681556314000 # Total ticks spent from burst creation until serviced by the DRAM
271system.physmem.totBusLat 76359555000 # Total ticks spent in databus transfers
272system.physmem.avgQLat 25878.10 # Average queueing delay per DRAM burst
273system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
274system.physmem.avgMemAccLat 44628.10 # Average memory access latency per DRAM burst
275system.physmem.avgRdBW 372.82 # Average DRAM read bandwidth in MiByte/s
276system.physmem.avgWrBW 2.76 # Average achieved write bandwidth in MiByte/s
277system.physmem.avgRdBWSys 50.15 # Average system read bandwidth in MiByte/s
278system.physmem.avgWrBWSys 2.75 # Average system write bandwidth in MiByte/s
279system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
280system.physmem.busUtil 2.93 # Data bus utilization in percentage
281system.physmem.busUtilRead 2.91 # Data bus utilization in percentage for reads
282system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
283system.physmem.avgRdQLen 5.85 # Average read queue length when enqueuing
284system.physmem.avgWrQLen 27.60 # Average write queue length when enqueuing
285system.physmem.readRowHits 14274861 # Number of row buffer hits during reads
286system.physmem.writeRowHits 95334 # Number of row buffer hits during writes
287system.physmem.readRowHitRate 93.47 # Row buffer hit rate for reads
288system.physmem.writeRowHitRate 84.26 # Row buffer hit rate for writes
289system.physmem.avgGap 162570.35 # Average gap between requests
290system.physmem.pageHitRate 93.40 # Row buffer hit rate, read and write combined
291system.physmem.memoryStateTime::IDLE 2271344460000 # Time in different power states
292system.physmem.memoryStateTime::REF 87542520000 # Time in different power states
293system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
294system.physmem.memoryStateTime::ACT 262759227500 # Time in different power states
295system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
296system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory
297system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
298system.realview.nvmem.bytes_read::total 192 # Number of bytes read from this memory
299system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory
300system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory
301system.realview.nvmem.bytes_inst_read::total 192 # Number of instructions bytes read from this memory
302system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory
303system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory
304system.realview.nvmem.num_reads::total 12 # Number of read requests responded to by this memory
305system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s)
306system.realview.nvmem.bw_read::cpu1.inst 55 # Total read bandwidth from this memory (bytes/s)
307system.realview.nvmem.bw_read::total 73 # Total read bandwidth from this memory (bytes/s)
308system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s)
309system.realview.nvmem.bw_inst_read::cpu1.inst 55 # Instruction read bandwidth from this memory (bytes/s)
310system.realview.nvmem.bw_inst_read::total 73 # Instruction read bandwidth from this memory (bytes/s)
311system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s)
312system.realview.nvmem.bw_total::cpu1.inst 55 # Total bandwidth to/from this memory (bytes/s)
313system.realview.nvmem.bw_total::total 73 # Total bandwidth to/from this memory (bytes/s)
314system.membus.throughput 53827614 # Throughput (bytes/s)
315system.membus.trans_dist::ReadReq 16353736 # Transaction distribution
316system.membus.trans_dist::ReadResp 16353736 # Transaction distribution
317system.membus.trans_dist::WriteReq 768463 # Transaction distribution
318system.membus.trans_dist::WriteResp 768463 # Transaction distribution
319system.membus.trans_dist::Writeback 65464 # Transaction distribution
320system.membus.trans_dist::UpgradeReq 28363 # Transaction distribution
321system.membus.trans_dist::SCUpgradeReq 16887 # Transaction distribution
322system.membus.trans_dist::UpgradeResp 12033 # Transaction distribution
323system.membus.trans_dist::ReadExReq 137713 # Transaction distribution
324system.membus.trans_dist::ReadExResp 137251 # Transaction distribution
325system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384346 # Packet count per connected master and slave (bytes)
326system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 24 # Packet count per connected master and slave (bytes)
327system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10950 # Packet count per connected master and slave (bytes)
328system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
329system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2058 # Packet count per connected master and slave (bytes)
330system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1967095 # Packet count per connected master and slave (bytes)
331system.membus.pkt_count_system.l2c.mem_side::total 4364477 # Packet count per connected master and slave (bytes)
332system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
333system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
334system.membus.pkt_count::total 34642109 # Packet count per connected master and slave (bytes)
335system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392641 # Cumulative packet size per connected master and slave (bytes)
336system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 192 # Cumulative packet size per connected master and slave (bytes)
337system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 21900 # Cumulative packet size per connected master and slave (bytes)
338system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
339system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4116 # Cumulative packet size per connected master and slave (bytes)
340system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17587620 # Cumulative packet size per connected master and slave (bytes)
341system.membus.tot_pkt_size_system.l2c.mem_side::total 20006477 # Cumulative packet size per connected master and slave (bytes)
342system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
343system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
344system.membus.tot_pkt_size::total 141117005 # Cumulative packet size per connected master and slave (bytes)
345system.membus.data_through_bus 141117005 # Total data (bytes)
346system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
347system.membus.reqLayer0.occupancy 1559281500 # Layer occupancy (ticks)
348system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
349system.membus.reqLayer1.occupancy 14500 # Layer occupancy (ticks)
350system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
351system.membus.reqLayer2.occupancy 9763000 # Layer occupancy (ticks)
352system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
353system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks)
354system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
355system.membus.reqLayer5.occupancy 1786500 # Layer occupancy (ticks)
356system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
357system.membus.reqLayer6.occupancy 17605374000 # Layer occupancy (ticks)
358system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
359system.membus.respLayer1.occupancy 4830238688 # Layer occupancy (ticks)
360system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
361system.membus.respLayer2.occupancy 37428300697 # Layer occupancy (ticks)
362system.membus.respLayer2.utilization 1.4 # Layer utilization (%)
363system.cpu_clk_domain.clock 500 # Clock period in ticks
364system.l2c.tags.replacements 71035 # number of replacements
365system.l2c.tags.tagsinuse 52844.560777 # Cycle average of tags in use
366system.l2c.tags.total_refs 1830685 # Total number of references to valid blocks.
367system.l2c.tags.sampled_refs 136207 # Sample count of references to valid blocks.
368system.l2c.tags.avg_refs 13.440462 # Average number of references to valid blocks.
369system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
370system.l2c.tags.occ_blocks::writebacks 37821.803984 # Average occupied blocks per requestor
371system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.739512 # Average occupied blocks per requestor
372system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000522 # Average occupied blocks per requestor
373system.l2c.tags.occ_blocks::cpu0.inst 5415.027395 # Average occupied blocks per requestor
374system.l2c.tags.occ_blocks::cpu0.data 6377.582658 # Average occupied blocks per requestor
375system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.953654 # Average occupied blocks per requestor
376system.l2c.tags.occ_blocks::cpu1.inst 2390.174334 # Average occupied blocks per requestor
377system.l2c.tags.occ_blocks::cpu1.data 833.278718 # Average occupied blocks per requestor
378system.l2c.tags.occ_percent::writebacks 0.577115 # Average percentage of cache occupancy
379system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000088 # Average percentage of cache occupancy
380system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
381system.l2c.tags.occ_percent::cpu0.inst 0.082627 # Average percentage of cache occupancy
382system.l2c.tags.occ_percent::cpu0.data 0.097314 # Average percentage of cache occupancy
383system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
384system.l2c.tags.occ_percent::cpu1.inst 0.036471 # Average percentage of cache occupancy
385system.l2c.tags.occ_percent::cpu1.data 0.012715 # Average percentage of cache occupancy
386system.l2c.tags.occ_percent::total 0.806344 # Average percentage of cache occupancy
387system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
388system.l2c.tags.occ_task_id_blocks::1024 65168 # Occupied blocks per task id
389system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
390system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
391system.l2c.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id
392system.l2c.tags.age_task_id_blocks_1024::2 3098 # Occupied blocks per task id
393system.l2c.tags.age_task_id_blocks_1024::3 8323 # Occupied blocks per task id
394system.l2c.tags.age_task_id_blocks_1024::4 53527 # Occupied blocks per task id
395system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
396system.l2c.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id
397system.l2c.tags.tag_accesses 18484845 # Number of tag accesses
398system.l2c.tags.data_accesses 18484845 # Number of data accesses
399system.l2c.ReadReq_hits::cpu0.dtb.walker 20873 # number of ReadReq hits
400system.l2c.ReadReq_hits::cpu0.itb.walker 5362 # number of ReadReq hits
401system.l2c.ReadReq_hits::cpu0.inst 546777 # number of ReadReq hits
402system.l2c.ReadReq_hits::cpu0.data 243323 # number of ReadReq hits
403system.l2c.ReadReq_hits::cpu1.dtb.walker 15709 # number of ReadReq hits
404system.l2c.ReadReq_hits::cpu1.itb.walker 4324 # number of ReadReq hits
405system.l2c.ReadReq_hits::cpu1.inst 434561 # number of ReadReq hits
406system.l2c.ReadReq_hits::cpu1.data 119239 # number of ReadReq hits
407system.l2c.ReadReq_hits::total 1390168 # number of ReadReq hits
408system.l2c.Writeback_hits::writebacks 583269 # number of Writeback hits
409system.l2c.Writeback_hits::total 583269 # number of Writeback hits
410system.l2c.UpgradeReq_hits::cpu0.data 1334 # number of UpgradeReq hits
411system.l2c.UpgradeReq_hits::cpu1.data 378 # number of UpgradeReq hits
412system.l2c.UpgradeReq_hits::total 1712 # number of UpgradeReq hits
413system.l2c.SCUpgradeReq_hits::cpu0.data 271 # number of SCUpgradeReq hits
414system.l2c.SCUpgradeReq_hits::cpu1.data 117 # number of SCUpgradeReq hits
415system.l2c.SCUpgradeReq_hits::total 388 # number of SCUpgradeReq hits
416system.l2c.ReadExReq_hits::cpu0.data 65538 # number of ReadExReq hits
417system.l2c.ReadExReq_hits::cpu1.data 44550 # number of ReadExReq hits
418system.l2c.ReadExReq_hits::total 110088 # number of ReadExReq hits
419system.l2c.demand_hits::cpu0.dtb.walker 20873 # number of demand (read+write) hits
420system.l2c.demand_hits::cpu0.itb.walker 5362 # number of demand (read+write) hits
421system.l2c.demand_hits::cpu0.inst 546777 # number of demand (read+write) hits
422system.l2c.demand_hits::cpu0.data 308861 # number of demand (read+write) hits
423system.l2c.demand_hits::cpu1.dtb.walker 15709 # number of demand (read+write) hits
424system.l2c.demand_hits::cpu1.itb.walker 4324 # number of demand (read+write) hits
425system.l2c.demand_hits::cpu1.inst 434561 # number of demand (read+write) hits
426system.l2c.demand_hits::cpu1.data 163789 # number of demand (read+write) hits
427system.l2c.demand_hits::total 1500256 # number of demand (read+write) hits
428system.l2c.overall_hits::cpu0.dtb.walker 20873 # number of overall hits
429system.l2c.overall_hits::cpu0.itb.walker 5362 # number of overall hits
430system.l2c.overall_hits::cpu0.inst 546777 # number of overall hits
431system.l2c.overall_hits::cpu0.data 308861 # number of overall hits
432system.l2c.overall_hits::cpu1.dtb.walker 15709 # number of overall hits
433system.l2c.overall_hits::cpu1.itb.walker 4324 # number of overall hits
434system.l2c.overall_hits::cpu1.inst 434561 # number of overall hits
435system.l2c.overall_hits::cpu1.data 163789 # number of overall hits
436system.l2c.overall_hits::total 1500256 # number of overall hits
437system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses
438system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
439system.l2c.ReadReq_misses::cpu0.inst 7230 # number of ReadReq misses
440system.l2c.ReadReq_misses::cpu0.data 9897 # number of ReadReq misses
441system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
442system.l2c.ReadReq_misses::cpu1.inst 4714 # number of ReadReq misses
443system.l2c.ReadReq_misses::cpu1.data 2106 # number of ReadReq misses
444system.l2c.ReadReq_misses::total 23958 # number of ReadReq misses
445system.l2c.UpgradeReq_misses::cpu0.data 4509 # number of UpgradeReq misses
446system.l2c.UpgradeReq_misses::cpu1.data 3863 # number of UpgradeReq misses
447system.l2c.UpgradeReq_misses::total 8372 # number of UpgradeReq misses
448system.l2c.SCUpgradeReq_misses::cpu0.data 516 # number of SCUpgradeReq misses
449system.l2c.SCUpgradeReq_misses::cpu1.data 628 # number of SCUpgradeReq misses
450system.l2c.SCUpgradeReq_misses::total 1144 # number of SCUpgradeReq misses
451system.l2c.ReadExReq_misses::cpu0.data 94130 # number of ReadExReq misses
452system.l2c.ReadExReq_misses::cpu1.data 45638 # number of ReadExReq misses
453system.l2c.ReadExReq_misses::total 139768 # number of ReadExReq misses
454system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses
455system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
456system.l2c.demand_misses::cpu0.inst 7230 # number of demand (read+write) misses
457system.l2c.demand_misses::cpu0.data 104027 # number of demand (read+write) misses
458system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
459system.l2c.demand_misses::cpu1.inst 4714 # number of demand (read+write) misses
460system.l2c.demand_misses::cpu1.data 47744 # number of demand (read+write) misses
461system.l2c.demand_misses::total 163726 # number of demand (read+write) misses
462system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses
463system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
464system.l2c.overall_misses::cpu0.inst 7230 # number of overall misses
465system.l2c.overall_misses::cpu0.data 104027 # number of overall misses
466system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
467system.l2c.overall_misses::cpu1.inst 4714 # number of overall misses
468system.l2c.overall_misses::cpu1.data 47744 # number of overall misses
469system.l2c.overall_misses::total 163726 # number of overall misses
470system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 551500 # number of ReadReq miss cycles
471system.l2c.ReadReq_miss_latency::cpu0.itb.walker 150000 # number of ReadReq miss cycles
472system.l2c.ReadReq_miss_latency::cpu0.inst 522312750 # number of ReadReq miss cycles
473system.l2c.ReadReq_miss_latency::cpu0.data 733828247 # number of ReadReq miss cycles
474system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 83500 # number of ReadReq miss cycles
475system.l2c.ReadReq_miss_latency::cpu1.inst 334292999 # number of ReadReq miss cycles
476system.l2c.ReadReq_miss_latency::cpu1.data 165107999 # number of ReadReq miss cycles
477system.l2c.ReadReq_miss_latency::total 1756326995 # number of ReadReq miss cycles
478system.l2c.UpgradeReq_miss_latency::cpu0.data 11295015 # number of UpgradeReq miss cycles
479system.l2c.UpgradeReq_miss_latency::cpu1.data 12799954 # number of UpgradeReq miss cycles
480system.l2c.UpgradeReq_miss_latency::total 24094969 # number of UpgradeReq miss cycles
481system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1793923 # number of SCUpgradeReq miss cycles
482system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1118952 # number of SCUpgradeReq miss cycles
483system.l2c.SCUpgradeReq_miss_latency::total 2912875 # number of SCUpgradeReq miss cycles
484system.l2c.ReadExReq_miss_latency::cpu0.data 6378706625 # number of ReadExReq miss cycles
485system.l2c.ReadExReq_miss_latency::cpu1.data 3294603599 # number of ReadExReq miss cycles
486system.l2c.ReadExReq_miss_latency::total 9673310224 # number of ReadExReq miss cycles
487system.l2c.demand_miss_latency::cpu0.dtb.walker 551500 # number of demand (read+write) miss cycles
488system.l2c.demand_miss_latency::cpu0.itb.walker 150000 # number of demand (read+write) miss cycles
489system.l2c.demand_miss_latency::cpu0.inst 522312750 # number of demand (read+write) miss cycles
490system.l2c.demand_miss_latency::cpu0.data 7112534872 # number of demand (read+write) miss cycles
491system.l2c.demand_miss_latency::cpu1.dtb.walker 83500 # number of demand (read+write) miss cycles
492system.l2c.demand_miss_latency::cpu1.inst 334292999 # number of demand (read+write) miss cycles
493system.l2c.demand_miss_latency::cpu1.data 3459711598 # number of demand (read+write) miss cycles
494system.l2c.demand_miss_latency::total 11429637219 # number of demand (read+write) miss cycles
495system.l2c.overall_miss_latency::cpu0.dtb.walker 551500 # number of overall miss cycles
496system.l2c.overall_miss_latency::cpu0.itb.walker 150000 # number of overall miss cycles
497system.l2c.overall_miss_latency::cpu0.inst 522312750 # number of overall miss cycles
498system.l2c.overall_miss_latency::cpu0.data 7112534872 # number of overall miss cycles
499system.l2c.overall_miss_latency::cpu1.dtb.walker 83500 # number of overall miss cycles
500system.l2c.overall_miss_latency::cpu1.inst 334292999 # number of overall miss cycles
501system.l2c.overall_miss_latency::cpu1.data 3459711598 # number of overall miss cycles
502system.l2c.overall_miss_latency::total 11429637219 # number of overall miss cycles
503system.l2c.ReadReq_accesses::cpu0.dtb.walker 20881 # number of ReadReq accesses(hits+misses)
504system.l2c.ReadReq_accesses::cpu0.itb.walker 5364 # number of ReadReq accesses(hits+misses)
505system.l2c.ReadReq_accesses::cpu0.inst 554007 # number of ReadReq accesses(hits+misses)
506system.l2c.ReadReq_accesses::cpu0.data 253220 # number of ReadReq accesses(hits+misses)
507system.l2c.ReadReq_accesses::cpu1.dtb.walker 15710 # number of ReadReq accesses(hits+misses)
508system.l2c.ReadReq_accesses::cpu1.itb.walker 4324 # number of ReadReq accesses(hits+misses)
509system.l2c.ReadReq_accesses::cpu1.inst 439275 # number of ReadReq accesses(hits+misses)
510system.l2c.ReadReq_accesses::cpu1.data 121345 # number of ReadReq accesses(hits+misses)
511system.l2c.ReadReq_accesses::total 1414126 # number of ReadReq accesses(hits+misses)
512system.l2c.Writeback_accesses::writebacks 583269 # number of Writeback accesses(hits+misses)
513system.l2c.Writeback_accesses::total 583269 # number of Writeback accesses(hits+misses)
514system.l2c.UpgradeReq_accesses::cpu0.data 5843 # number of UpgradeReq accesses(hits+misses)
515system.l2c.UpgradeReq_accesses::cpu1.data 4241 # number of UpgradeReq accesses(hits+misses)
516system.l2c.UpgradeReq_accesses::total 10084 # number of UpgradeReq accesses(hits+misses)
517system.l2c.SCUpgradeReq_accesses::cpu0.data 787 # number of SCUpgradeReq accesses(hits+misses)
518system.l2c.SCUpgradeReq_accesses::cpu1.data 745 # number of SCUpgradeReq accesses(hits+misses)
519system.l2c.SCUpgradeReq_accesses::total 1532 # number of SCUpgradeReq accesses(hits+misses)
520system.l2c.ReadExReq_accesses::cpu0.data 159668 # number of ReadExReq accesses(hits+misses)
521system.l2c.ReadExReq_accesses::cpu1.data 90188 # number of ReadExReq accesses(hits+misses)
522system.l2c.ReadExReq_accesses::total 249856 # number of ReadExReq accesses(hits+misses)
523system.l2c.demand_accesses::cpu0.dtb.walker 20881 # number of demand (read+write) accesses
524system.l2c.demand_accesses::cpu0.itb.walker 5364 # number of demand (read+write) accesses
525system.l2c.demand_accesses::cpu0.inst 554007 # number of demand (read+write) accesses
526system.l2c.demand_accesses::cpu0.data 412888 # number of demand (read+write) accesses
527system.l2c.demand_accesses::cpu1.dtb.walker 15710 # number of demand (read+write) accesses
528system.l2c.demand_accesses::cpu1.itb.walker 4324 # number of demand (read+write) accesses
529system.l2c.demand_accesses::cpu1.inst 439275 # number of demand (read+write) accesses
530system.l2c.demand_accesses::cpu1.data 211533 # number of demand (read+write) accesses
531system.l2c.demand_accesses::total 1663982 # number of demand (read+write) accesses
532system.l2c.overall_accesses::cpu0.dtb.walker 20881 # number of overall (read+write) accesses
533system.l2c.overall_accesses::cpu0.itb.walker 5364 # number of overall (read+write) accesses
534system.l2c.overall_accesses::cpu0.inst 554007 # number of overall (read+write) accesses
535system.l2c.overall_accesses::cpu0.data 412888 # number of overall (read+write) accesses
536system.l2c.overall_accesses::cpu1.dtb.walker 15710 # number of overall (read+write) accesses
537system.l2c.overall_accesses::cpu1.itb.walker 4324 # number of overall (read+write) accesses
538system.l2c.overall_accesses::cpu1.inst 439275 # number of overall (read+write) accesses
539system.l2c.overall_accesses::cpu1.data 211533 # number of overall (read+write) accesses
540system.l2c.overall_accesses::total 1663982 # number of overall (read+write) accesses
541system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000383 # miss rate for ReadReq accesses
542system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000373 # miss rate for ReadReq accesses
543system.l2c.ReadReq_miss_rate::cpu0.inst 0.013050 # miss rate for ReadReq accesses
544system.l2c.ReadReq_miss_rate::cpu0.data 0.039085 # miss rate for ReadReq accesses
545system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000064 # miss rate for ReadReq accesses
546system.l2c.ReadReq_miss_rate::cpu1.inst 0.010731 # miss rate for ReadReq accesses
547system.l2c.ReadReq_miss_rate::cpu1.data 0.017355 # miss rate for ReadReq accesses
548system.l2c.ReadReq_miss_rate::total 0.016942 # miss rate for ReadReq accesses
549system.l2c.UpgradeReq_miss_rate::cpu0.data 0.771693 # miss rate for UpgradeReq accesses
550system.l2c.UpgradeReq_miss_rate::cpu1.data 0.910870 # miss rate for UpgradeReq accesses
551system.l2c.UpgradeReq_miss_rate::total 0.830226 # miss rate for UpgradeReq accesses
552system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.655654 # miss rate for SCUpgradeReq accesses
553system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.842953 # miss rate for SCUpgradeReq accesses
554system.l2c.SCUpgradeReq_miss_rate::total 0.746736 # miss rate for SCUpgradeReq accesses
555system.l2c.ReadExReq_miss_rate::cpu0.data 0.589536 # miss rate for ReadExReq accesses
556system.l2c.ReadExReq_miss_rate::cpu1.data 0.506032 # miss rate for ReadExReq accesses
557system.l2c.ReadExReq_miss_rate::total 0.559394 # miss rate for ReadExReq accesses
558system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000383 # miss rate for demand accesses
559system.l2c.demand_miss_rate::cpu0.itb.walker 0.000373 # miss rate for demand accesses
560system.l2c.demand_miss_rate::cpu0.inst 0.013050 # miss rate for demand accesses
561system.l2c.demand_miss_rate::cpu0.data 0.251950 # miss rate for demand accesses
562system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000064 # miss rate for demand accesses
563system.l2c.demand_miss_rate::cpu1.inst 0.010731 # miss rate for demand accesses
564system.l2c.demand_miss_rate::cpu1.data 0.225705 # miss rate for demand accesses
565system.l2c.demand_miss_rate::total 0.098394 # miss rate for demand accesses
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567system.l2c.overall_miss_rate::cpu0.itb.walker 0.000373 # miss rate for overall accesses
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723system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.910870 # mshr miss rate for UpgradeReq accesses
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725system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.655654 # mshr miss rate for SCUpgradeReq accesses
726system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.842953 # mshr miss rate for SCUpgradeReq accesses
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732system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000373 # mshr miss rate for demand accesses
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736system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010709 # mshr miss rate for demand accesses
737system.l2c.demand_mshr_miss_rate::cpu1.data 0.225648 # mshr miss rate for demand accesses
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739system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000335 # mshr miss rate for overall accesses
740system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000373 # mshr miss rate for overall accesses
741system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013034 # mshr miss rate for overall accesses
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744system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010709 # mshr miss rate for overall accesses
745system.l2c.overall_mshr_miss_rate::cpu1.data 0.225648 # mshr miss rate for overall accesses
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747system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56428.571429 # average ReadReq mshr miss latency
748system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
749system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59721.956793 # average ReadReq mshr miss latency
750system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61615.031614 # average ReadReq mshr miss latency
751system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 71000 # average ReadReq mshr miss latency
752system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58417.995111 # average ReadReq mshr miss latency
753system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66037.248806 # average ReadReq mshr miss latency
754system.l2c.ReadReq_avg_mshr_miss_latency::total 60800.160892 # average ReadReq mshr miss latency
755system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10013.300954 # average UpgradeReq mshr miss latency
756system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.830443 # average UpgradeReq mshr miss latency
757system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10022.312231 # average UpgradeReq mshr miss latency
758system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
759system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10024.084395 # average SCUpgradeReq mshr miss latency
760system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10013.672203 # average SCUpgradeReq mshr miss latency
761system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 55258.513343 # average ReadExReq mshr miss latency
762system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59790.479096 # average ReadExReq mshr miss latency
763system.l2c.ReadExReq_avg_mshr_miss_latency::total 56738.321690 # average ReadExReq mshr miss latency
764system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56428.571429 # average overall mshr miss latency
765system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
766system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59721.956793 # average overall mshr miss latency
767system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55861.716055 # average overall mshr miss latency
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769system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58417.995111 # average overall mshr miss latency
770system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60064.524512 # average overall mshr miss latency
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773system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
774system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59721.956793 # average overall mshr miss latency
775system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55861.716055 # average overall mshr miss latency
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778system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60064.524512 # average overall mshr miss latency
779system.l2c.overall_avg_mshr_miss_latency::total 57331.418810 # average overall mshr miss latency
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781system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
782system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
783system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
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785system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
786system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
787system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency

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792system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
793system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
794system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
795system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
796system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
797system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
798system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
799system.cf0.dma_write_txs 0 # Number of DMA write transactions.
800system.toL2Bus.throughput 57560286 # Throughput (bytes/s)
801system.toL2Bus.trans_dist::ReadReq 2682607 # Transaction distribution
802system.toL2Bus.trans_dist::ReadResp 2682607 # Transaction distribution
803system.toL2Bus.trans_dist::WriteReq 768463 # Transaction distribution
804system.toL2Bus.trans_dist::WriteResp 768463 # Transaction distribution
805system.toL2Bus.trans_dist::Writeback 583269 # Transaction distribution
806system.toL2Bus.trans_dist::UpgradeReq 27558 # Transaction distribution
807system.toL2Bus.trans_dist::SCUpgradeReq 17275 # Transaction distribution
808system.toL2Bus.trans_dist::UpgradeResp 44833 # Transaction distribution
809system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
810system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution
811system.toL2Bus.trans_dist::ReadExReq 261997 # Transaction distribution
812system.toL2Bus.trans_dist::ReadExResp 261997 # Transaction distribution
813system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1115277 # Packet count per connected master and slave (bytes)
814system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2956767 # Packet count per connected master and slave (bytes)
815system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 14518 # Packet count per connected master and slave (bytes)
816system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50368 # Packet count per connected master and slave (bytes)
817system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 879187 # Packet count per connected master and slave (bytes)
818system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2909426 # Packet count per connected master and slave (bytes)
819system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 12099 # Packet count per connected master and slave (bytes)
820system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 38611 # Packet count per connected master and slave (bytes)
821system.toL2Bus.pkt_count::total 7976253 # Packet count per connected master and slave (bytes)
822system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 35510400 # Cumulative packet size per connected master and slave (bytes)
823system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53724619 # Cumulative packet size per connected master and slave (bytes)
824system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21456 # Cumulative packet size per connected master and slave (bytes)
825system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83524 # Cumulative packet size per connected master and slave (bytes)
826system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 28114656 # Cumulative packet size per connected master and slave (bytes)
827system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 29015778 # Cumulative packet size per connected master and slave (bytes)
828system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 17296 # Cumulative packet size per connected master and slave (bytes)
829system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 62840 # Cumulative packet size per connected master and slave (bytes)
830system.toL2Bus.tot_pkt_size::total 146550569 # Cumulative packet size per connected master and slave (bytes)
831system.toL2Bus.data_through_bus 146550569 # Total data (bytes)
832system.toL2Bus.snoop_data_through_bus 4352184 # Total snoop data (bytes)
833system.toL2Bus.reqLayer0.occupancy 4888594820 # Layer occupancy (ticks)
834system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
835system.toL2Bus.respLayer0.occupancy 2503079453 # Layer occupancy (ticks)
836system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
837system.toL2Bus.respLayer1.occupancy 2482730980 # Layer occupancy (ticks)
838system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
839system.toL2Bus.respLayer2.occupancy 9171959 # Layer occupancy (ticks)
840system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
841system.toL2Bus.respLayer3.occupancy 29595779 # Layer occupancy (ticks)
842system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
843system.toL2Bus.respLayer6.occupancy 1980581418 # Layer occupancy (ticks)
844system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%)
845system.toL2Bus.respLayer7.occupancy 2244583247 # Layer occupancy (ticks)
846system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%)
847system.toL2Bus.respLayer8.occupancy 7797450 # Layer occupancy (ticks)
848system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%)
849system.toL2Bus.respLayer9.occupancy 22968355 # Layer occupancy (ticks)
850system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%)
851system.iobus.throughput 47108999 # Throughput (bytes/s)
852system.iobus.trans_dist::ReadReq 16322906 # Transaction distribution
853system.iobus.trans_dist::ReadResp 16322906 # Transaction distribution
854system.iobus.trans_dist::WriteReq 8083 # Transaction distribution
855system.iobus.trans_dist::WriteResp 8083 # Transaction distribution
856system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30944 # Packet count per connected master and slave (bytes)
857system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8814 # Packet count per connected master and slave (bytes)
858system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
859system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1034 # Packet count per connected master and slave (bytes)
860system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
861system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
862system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes)
863system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
864system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
865system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
866system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
867system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
868system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
869system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
870system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
871system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
872system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
873system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
874system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
875system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
876system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
877system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
878system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
879system.iobus.pkt_count_system.bridge.master::total 2384346 # Packet count per connected master and slave (bytes)
880system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
881system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
882system.iobus.pkt_count::total 32661978 # Packet count per connected master and slave (bytes)
883system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40713 # Cumulative packet size per connected master and slave (bytes)
884system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17628 # Cumulative packet size per connected master and slave (bytes)
885system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
886system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2068 # Cumulative packet size per connected master and slave (bytes)
887system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
888system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
889system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes)
890system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
891system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
892system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
893system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
894system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
895system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
896system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
897system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
898system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
899system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
900system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
901system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
902system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
903system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
904system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
905system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
906system.iobus.tot_pkt_size_system.bridge.master::total 2392641 # Cumulative packet size per connected master and slave (bytes)
907system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
908system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
909system.iobus.tot_pkt_size::total 123503169 # Cumulative packet size per connected master and slave (bytes)
910system.iobus.data_through_bus 123503169 # Total data (bytes)
911system.iobus.reqLayer0.occupancy 21713000 # Layer occupancy (ticks)
912system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
913system.iobus.reqLayer1.occupancy 4413000 # Layer occupancy (ticks)
914system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
915system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
916system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
917system.iobus.reqLayer3.occupancy 523000 # Layer occupancy (ticks)
918system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
919system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
920system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
921system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
922system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
923system.iobus.reqLayer6.occupancy 440000 # Layer occupancy (ticks)
924system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
925system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
926system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
927system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
928system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
929system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
930system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
931system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)

--- 17 unchanged lines hidden (view full) ---

949system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
950system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
951system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
952system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
953system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
954system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
955system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
956system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
957system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
958system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
959system.iobus.respLayer0.occupancy 2376263000 # Layer occupancy (ticks)
960system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
961system.iobus.respLayer1.occupancy 38168032303 # Layer occupancy (ticks)
962system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
963system.cpu0.branchPred.lookups 8682194 # Number of BP lookups
964system.cpu0.branchPred.condPredicted 6490987 # Number of conditional branches predicted
965system.cpu0.branchPred.condIncorrect 415813 # Number of conditional branches incorrect
966system.cpu0.branchPred.BTBLookups 5217710 # Number of BTB lookups
967system.cpu0.branchPred.BTBHits 4131218 # Number of BTB hits
968system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
969system.cpu0.branchPred.BTBHitPct 79.176842 # BTB Hit Percentage
970system.cpu0.branchPred.usedRAS 908190 # Number of times the RAS was used to get a target.
971system.cpu0.branchPred.RASInCorrect 19748 # Number of incorrect RAS predictions.
972system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
973system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
974system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
975system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
976system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
977system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
978system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
979system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 7 unchanged lines hidden (view full) ---

987system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
988system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
989system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
990system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
991system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
992system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
993system.cpu0.dtb.inst_hits 0 # ITB inst hits
994system.cpu0.dtb.inst_misses 0 # ITB inst misses
995system.cpu0.dtb.read_hits 10917771 # DTB read hits
996system.cpu0.dtb.read_misses 23643 # DTB read misses
997system.cpu0.dtb.write_hits 7767808 # DTB write hits
998system.cpu0.dtb.write_misses 8146 # DTB write misses
999system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
1000system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1001system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1002system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1003system.cpu0.dtb.flush_entries 1721 # Number of entries that have been flushed from TLB
1004system.cpu0.dtb.align_faults 163 # Number of TLB faults due to alignment restrictions
1005system.cpu0.dtb.prefetch_faults 270 # Number of TLB faults due to prefetch
1006system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1007system.cpu0.dtb.perms_faults 598 # Number of TLB faults due to permissions restrictions
1008system.cpu0.dtb.read_accesses 10941414 # DTB read accesses
1009system.cpu0.dtb.write_accesses 7775954 # DTB write accesses
1010system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
1011system.cpu0.dtb.hits 18685579 # DTB hits
1012system.cpu0.dtb.misses 31789 # DTB misses
1013system.cpu0.dtb.accesses 18717368 # DTB accesses
1014system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1015system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1016system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1017system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1018system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1019system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1020system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1021system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

1027system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1028system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1029system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1030system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1031system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1032system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1033system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1034system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1035system.cpu0.itb.inst_hits 16449037 # ITB inst hits
1036system.cpu0.itb.inst_misses 5743 # ITB inst misses
1037system.cpu0.itb.read_hits 0 # DTB read hits
1038system.cpu0.itb.read_misses 0 # DTB read misses
1039system.cpu0.itb.write_hits 0 # DTB write hits
1040system.cpu0.itb.write_misses 0 # DTB write misses
1041system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
1042system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1043system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1044system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1045system.cpu0.itb.flush_entries 1206 # Number of entries that have been flushed from TLB
1046system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1047system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1048system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1049system.cpu0.itb.perms_faults 2114 # Number of TLB faults due to permissions restrictions
1050system.cpu0.itb.read_accesses 0 # DTB read accesses
1051system.cpu0.itb.write_accesses 0 # DTB write accesses
1052system.cpu0.itb.inst_accesses 16454780 # ITB inst accesses
1053system.cpu0.itb.hits 16449037 # DTB hits
1054system.cpu0.itb.misses 5743 # DTB misses
1055system.cpu0.itb.accesses 16454780 # DTB accesses
1056system.cpu0.numCycles 110984158 # number of cpu cycles simulated
1057system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
1058system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
1059system.cpu0.fetch.icacheStallCycles 29010417 # Number of cycles fetch is stalled on an Icache miss
1060system.cpu0.fetch.Insts 51007104 # Number of instructions fetch has processed
1061system.cpu0.fetch.Branches 8682194 # Number of branches that fetch encountered
1062system.cpu0.fetch.predictedBranches 5039408 # Number of branches that fetch has predicted taken
1063system.cpu0.fetch.Cycles 76702951 # Number of cycles fetch has run and was not squashing or blocked
1064system.cpu0.fetch.SquashCycles 1090474 # Number of cycles fetch has spent squashing
1065system.cpu0.fetch.TlbCycles 80643 # Number of cycles fetch has spent waiting for tlb
1066system.cpu0.fetch.MiscStallCycles 23949 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1067system.cpu0.fetch.PendingTrapStallCycles 71996 # Number of stall cycles due to pending traps
1068system.cpu0.fetch.PendingQuiesceStallCycles 1961272 # Number of stall cycles due to pending quiesce instructions
1069system.cpu0.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR
1070system.cpu0.fetch.CacheLines 16450117 # Number of cache lines fetched
1071system.cpu0.fetch.IcacheSquashes 242573 # Number of outstanding Icache misses that were squashed
1072system.cpu0.fetch.ItlbSquashes 2510 # Number of outstanding ITLB misses that were squashed
1073system.cpu0.fetch.rateDist::samples 108396478 # Number of instructions fetched each cycle (Total)
1074system.cpu0.fetch.rateDist::mean 0.561251 # Number of instructions fetched each cycle (Total)
1075system.cpu0.fetch.rateDist::stdev 1.057421 # Number of instructions fetched each cycle (Total)
1076system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1077system.cpu0.fetch.rateDist::0 80471532 74.24% 74.24% # Number of instructions fetched each cycle (Total)
1078system.cpu0.fetch.rateDist::1 9354408 8.63% 82.87% # Number of instructions fetched each cycle (Total)
1079system.cpu0.fetch.rateDist::2 4228353 3.90% 86.77% # Number of instructions fetched each cycle (Total)
1080system.cpu0.fetch.rateDist::3 14342185 13.23% 100.00% # Number of instructions fetched each cycle (Total)
1081system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1082system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1083system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
1084system.cpu0.fetch.rateDist::total 108396478 # Number of instructions fetched each cycle (Total)
1085system.cpu0.fetch.branchRate 0.078229 # Number of branch fetches per cycle
1086system.cpu0.fetch.rate 0.459589 # Number of inst fetches per cycle
1087system.cpu0.decode.IdleCycles 24273364 # Number of cycles decode is idle
1088system.cpu0.decode.BlockedCycles 59696324 # Number of cycles decode is blocked
1089system.cpu0.decode.RunCycles 21865637 # Number of cycles decode is running
1090system.cpu0.decode.UnblockCycles 2148424 # Number of cycles decode is unblocking
1091system.cpu0.decode.SquashCycles 412729 # Number of cycles decode is squashing
1092system.cpu0.decode.BranchResolved 1100967 # Number of times decode resolved a branch
1093system.cpu0.decode.BranchMispred 134603 # Number of times decode detected a branch misprediction
1094system.cpu0.decode.DecodedInsts 56048449 # Number of instructions handled by decode
1095system.cpu0.decode.SquashedInsts 1161275 # Number of squashed instructions handled by decode
1096system.cpu0.rename.SquashCycles 412729 # Number of cycles rename is squashing
1097system.cpu0.rename.IdleCycles 26181144 # Number of cycles rename is idle
1098system.cpu0.rename.BlockCycles 23163659 # Number of cycles rename is blocking
1099system.cpu0.rename.serializeStallCycles 11818847 # count of cycles rename stalled for serializing inst
1100system.cpu0.rename.RunCycles 22001270 # Number of cycles rename is running
1101system.cpu0.rename.UnblockCycles 24818829 # Number of cycles rename is unblocking
1102system.cpu0.rename.RenamedInsts 54863842 # Number of instructions processed by rename
1103system.cpu0.rename.SquashedInsts 371818 # Number of squashed instructions processed by rename
1104system.cpu0.rename.ROBFullEvents 4330145 # Number of times rename has blocked due to ROB full
1105system.cpu0.rename.IQFullEvents 2622839 # Number of times rename has blocked due to IQ full
1106system.cpu0.rename.LQFullEvents 9842391 # Number of times rename has blocked due to LQ full
1107system.cpu0.rename.SQFullEvents 13156385 # Number of times rename has blocked due to SQ full
1108system.cpu0.rename.RenamedOperands 58083982 # Number of destination operands rename has renamed
1109system.cpu0.rename.RenameLookups 254404471 # Number of register rename lookups that rename has made
1110system.cpu0.rename.int_rename_lookups 69151408 # Number of integer rename lookups
1111system.cpu0.rename.fp_rename_lookups 3820 # Number of floating rename lookups
1112system.cpu0.rename.CommittedMaps 54276662 # Number of HB maps that are committed
1113system.cpu0.rename.UndoneMaps 3807314 # Number of HB maps that are undone due to squashing
1114system.cpu0.rename.serializingInsts 540800 # count of serializing insts renamed
1115system.cpu0.rename.tempSerializingInsts 442723 # count of temporary serializing insts renamed
1116system.cpu0.rename.skidInsts 4591136 # count of insts added to the skid buffer
1117system.cpu0.memDep0.insertedLoads 9492850 # Number of loads inserted to the mem dependence unit.
1118system.cpu0.memDep0.insertedStores 8297955 # Number of stores inserted to the mem dependence unit.
1119system.cpu0.memDep0.conflictingLoads 506397 # Number of conflicting loads.
1120system.cpu0.memDep0.conflictingStores 589876 # Number of conflicting stores.
1121system.cpu0.iq.iqInstsAdded 53569882 # Number of instructions added to the IQ (excludes non-spec)
1122system.cpu0.iq.iqNonSpecInstsAdded 859573 # Number of non-speculative instructions added to the IQ
1123system.cpu0.iq.iqInstsIssued 55433156 # Number of instructions issued
1124system.cpu0.iq.iqSquashedInstsIssued 105167 # Number of squashed instructions issued
1125system.cpu0.iq.iqSquashedInstsExamined 2762956 # Number of squashed instructions iterated over during squash; mainly for profiling
1126system.cpu0.iq.iqSquashedOperandsExamined 5503873 # Number of squashed operands that are examined and possibly removed from graph
1127system.cpu0.iq.iqSquashedNonSpecRemoved 84823 # Number of squashed non-spec instructions that were removed
1128system.cpu0.iq.issued_per_cycle::samples 108396478 # Number of insts issued each cycle
1129system.cpu0.iq.issued_per_cycle::mean 0.511393 # Number of insts issued each cycle
1130system.cpu0.iq.issued_per_cycle::stdev 0.864824 # Number of insts issued each cycle
1131system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1132system.cpu0.iq.issued_per_cycle::0 74367725 68.61% 68.61% # Number of insts issued each cycle
1133system.cpu0.iq.issued_per_cycle::1 17769290 16.39% 85.00% # Number of insts issued each cycle
1134system.cpu0.iq.issued_per_cycle::2 11558620 10.66% 95.66% # Number of insts issued each cycle
1135system.cpu0.iq.issued_per_cycle::3 4256755 3.93% 99.59% # Number of insts issued each cycle
1136system.cpu0.iq.issued_per_cycle::4 444079 0.41% 100.00% # Number of insts issued each cycle
1137system.cpu0.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle
1138system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
1139system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
1140system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
1141system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1142system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1143system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
1144system.cpu0.iq.issued_per_cycle::total 108396478 # Number of insts issued each cycle
1145system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1146system.cpu0.iq.fu_full::IntAlu 3788078 33.87% 33.87% # attempts to use FU when none available
1147system.cpu0.iq.fu_full::IntMult 172 0.00% 33.87% # attempts to use FU when none available
1148system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.87% # attempts to use FU when none available
1149system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.87% # attempts to use FU when none available
1150system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.87% # attempts to use FU when none available
1151system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.87% # attempts to use FU when none available
1152system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.87% # attempts to use FU when none available
1153system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.87% # attempts to use FU when none available
1154system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.87% # attempts to use FU when none available
1155system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.87% # attempts to use FU when none available
1156system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.87% # attempts to use FU when none available
1157system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.87% # attempts to use FU when none available
1158system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.87% # attempts to use FU when none available
1159system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.87% # attempts to use FU when none available
1160system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.87% # attempts to use FU when none available
1161system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.87% # attempts to use FU when none available
1162system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.87% # attempts to use FU when none available
1163system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.87% # attempts to use FU when none available
1164system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.87% # attempts to use FU when none available
1165system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.87% # attempts to use FU when none available
1166system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.87% # attempts to use FU when none available
1167system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.87% # attempts to use FU when none available
1168system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.87% # attempts to use FU when none available
1169system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.87% # attempts to use FU when none available
1170system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.87% # attempts to use FU when none available
1171system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.87% # attempts to use FU when none available
1172system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.87% # attempts to use FU when none available
1173system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available
1174system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.87% # attempts to use FU when none available
1175system.cpu0.iq.fu_full::MemRead 3595287 32.14% 66.01% # attempts to use FU when none available
1176system.cpu0.iq.fu_full::MemWrite 3801407 33.99% 100.00% # attempts to use FU when none available
1177system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1178system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1179system.cpu0.iq.FU_type_0::No_OpClass 14948 0.03% 0.03% # Type of FU issued
1180system.cpu0.iq.FU_type_0::IntAlu 35826739 64.63% 64.66% # Type of FU issued
1181system.cpu0.iq.FU_type_0::IntMult 64782 0.12% 64.77% # Type of FU issued
1182system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 64.77% # Type of FU issued
1183system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 64.77% # Type of FU issued
1184system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 64.77% # Type of FU issued
1185system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 64.77% # Type of FU issued
1186system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 64.77% # Type of FU issued
1187system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 64.77% # Type of FU issued
1188system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 64.77% # Type of FU issued
1189system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 64.77% # Type of FU issued
1190system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 64.77% # Type of FU issued
1191system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 64.77% # Type of FU issued
1192system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 64.77% # Type of FU issued
1193system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 64.77% # Type of FU issued
1194system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 64.77% # Type of FU issued
1195system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 64.77% # Type of FU issued
1196system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 64.77% # Type of FU issued
1197system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 64.77% # Type of FU issued
1198system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 64.77% # Type of FU issued
1199system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 64.77% # Type of FU issued
1200system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 64.77% # Type of FU issued
1201system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 64.77% # Type of FU issued
1202system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 64.77% # Type of FU issued
1203system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 64.77% # Type of FU issued
1204system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 64.77% # Type of FU issued
1205system.cpu0.iq.FU_type_0::SimdFloatMisc 722 0.00% 64.78% # Type of FU issued
1206system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 64.78% # Type of FU issued
1207system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 64.78% # Type of FU issued
1208system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 64.78% # Type of FU issued
1209system.cpu0.iq.FU_type_0::MemRead 11302035 20.39% 85.16% # Type of FU issued
1210system.cpu0.iq.FU_type_0::MemWrite 8223930 14.84% 100.00% # Type of FU issued
1211system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1212system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1213system.cpu0.iq.FU_type_0::total 55433156 # Type of FU issued
1214system.cpu0.iq.rate 0.499469 # Inst issue rate
1215system.cpu0.iq.fu_busy_cnt 11184944 # FU busy when requested
1216system.cpu0.iq.fu_busy_rate 0.201774 # FU busy rate (busy events/executed inst)
1217system.cpu0.iq.int_inst_queue_reads 230540772 # Number of integer instruction queue reads
1218system.cpu0.iq.int_inst_queue_writes 57191232 # Number of integer instruction queue writes
1219system.cpu0.iq.int_inst_queue_wakeup_accesses 52885161 # Number of integer instruction queue wakeup accesses
1220system.cpu0.iq.fp_inst_queue_reads 12129 # Number of floating instruction queue reads
1221system.cpu0.iq.fp_inst_queue_writes 4604 # Number of floating instruction queue writes
1222system.cpu0.iq.fp_inst_queue_wakeup_accesses 3838 # Number of floating instruction queue wakeup accesses
1223system.cpu0.iq.int_alu_accesses 66595213 # Number of integer alu accesses
1224system.cpu0.iq.fp_alu_accesses 7939 # Number of floating point alu accesses
1225system.cpu0.iew.lsq.thread0.forwLoads 146965 # Number of loads that had data forwarded from stores
1226system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1227system.cpu0.iew.lsq.thread0.squashedLoads 634189 # Number of loads squashed
1228system.cpu0.iew.lsq.thread0.ignoredResponses 503 # Number of memory responses ignored because the instruction is squashed
1229system.cpu0.iew.lsq.thread0.memOrderViolation 3442 # Number of memory ordering violations
1230system.cpu0.iew.lsq.thread0.squashedStores 242149 # Number of stores squashed
1231system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1232system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1233system.cpu0.iew.lsq.thread0.rescheduledLoads 1082260 # Number of loads that were rescheduled
1234system.cpu0.iew.lsq.thread0.cacheBlocked 1003693 # Number of times an access to memory failed due to the cache being blocked
1235system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1236system.cpu0.iew.iewSquashCycles 412729 # Number of cycles IEW is squashing
1237system.cpu0.iew.iewBlockCycles 7302695 # Number of cycles IEW is blocking
1238system.cpu0.iew.iewUnblockCycles 6441595 # Number of cycles IEW is unblocking
1239system.cpu0.iew.iewDispatchedInsts 54523303 # Number of instructions dispatched to IQ
1240system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
1241system.cpu0.iew.iewDispLoadInsts 9492850 # Number of dispatched load instructions
1242system.cpu0.iew.iewDispStoreInsts 8297955 # Number of dispatched store instructions
1243system.cpu0.iew.iewDispNonSpecInsts 524870 # Number of dispatched non-speculative instructions
1244system.cpu0.iew.iewIQFullEvents 12318 # Number of times the IQ has become full, causing a stall
1245system.cpu0.iew.iewLSQFullEvents 6420937 # Number of times the LSQ has become full, causing a stall
1246system.cpu0.iew.memOrderViolationEvents 3442 # Number of memory order violations
1247system.cpu0.iew.predictedTakenIncorrect 134210 # Number of branches that were predicted taken incorrectly
1248system.cpu0.iew.predictedNotTakenIncorrect 165432 # Number of branches that were predicted not taken incorrectly
1249system.cpu0.iew.branchMispredicts 299642 # Number of branch mispredicts detected at execute
1250system.cpu0.iew.iewExecutedInsts 55026621 # Number of executed instructions
1251system.cpu0.iew.iewExecLoadInsts 11133456 # Number of load instructions executed
1252system.cpu0.iew.iewExecSquashedInsts 374843 # Number of squashed instructions skipped in execute
1253system.cpu0.iew.exec_swp 0 # number of swp insts executed
1254system.cpu0.iew.exec_nop 93848 # number of nop insts executed
1255system.cpu0.iew.exec_refs 19301977 # number of memory reference insts executed
1256system.cpu0.iew.exec_branches 7332190 # Number of branches executed
1257system.cpu0.iew.exec_stores 8168521 # Number of stores executed
1258system.cpu0.iew.exec_rate 0.495806 # Inst execution rate
1259system.cpu0.iew.wb_sent 54039254 # cumulative count of insts sent to commit
1260system.cpu0.iew.wb_count 52888999 # cumulative count of insts written-back
1261system.cpu0.iew.wb_producers 25110485 # num instructions producing a value
1262system.cpu0.iew.wb_consumers 37735585 # num instructions consuming a value
1263system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1264system.cpu0.iew.wb_rate 0.476545 # insts written-back per cycle
1265system.cpu0.iew.wb_fanout 0.665433 # average fanout of values written-back
1266system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1267system.cpu0.commit.commitSquashedInsts 2480238 # The number of squashed insts skipped by commit
1268system.cpu0.commit.commitNonSpecStalls 774750 # The number of times commit has been forced to stall to communicate backwards
1269system.cpu0.commit.branchMispredicts 283305 # The number of times a branch was mispredicted
1270system.cpu0.commit.committed_per_cycle::samples 107840192 # Number of insts commited each cycle
1271system.cpu0.commit.committed_per_cycle::mean 0.477624 # Number of insts commited each cycle
1272system.cpu0.commit.committed_per_cycle::stdev 1.224539 # Number of insts commited each cycle
1273system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1274system.cpu0.commit.committed_per_cycle::0 82912194 76.88% 76.88% # Number of insts commited each cycle
1275system.cpu0.commit.committed_per_cycle::1 14339479 13.30% 90.18% # Number of insts commited each cycle
1276system.cpu0.commit.committed_per_cycle::2 5152045 4.78% 94.96% # Number of insts commited each cycle
1277system.cpu0.commit.committed_per_cycle::3 1572745 1.46% 96.42% # Number of insts commited each cycle
1278system.cpu0.commit.committed_per_cycle::4 1370622 1.27% 97.69% # Number of insts commited each cycle
1279system.cpu0.commit.committed_per_cycle::5 690625 0.64% 98.33% # Number of insts commited each cycle
1280system.cpu0.commit.committed_per_cycle::6 401555 0.37% 98.70% # Number of insts commited each cycle
1281system.cpu0.commit.committed_per_cycle::7 407085 0.38% 99.08% # Number of insts commited each cycle
1282system.cpu0.commit.committed_per_cycle::8 993842 0.92% 100.00% # Number of insts commited each cycle
1283system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1284system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1285system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1286system.cpu0.commit.committed_per_cycle::total 107840192 # Number of insts commited each cycle
1287system.cpu0.commit.committedInsts 43173906 # Number of instructions committed
1288system.cpu0.commit.committedOps 51507078 # Number of ops (including micro ops) committed
1289system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
1290system.cpu0.commit.refs 16914467 # Number of memory references committed
1291system.cpu0.commit.loads 8858661 # Number of loads committed
1292system.cpu0.commit.membars 263890 # Number of memory barriers committed
1293system.cpu0.commit.branches 7043091 # Number of branches committed
1294system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
1295system.cpu0.commit.int_insts 45505753 # Number of committed integer instructions.
1296system.cpu0.commit.function_calls 666034 # Number of function calls committed.
1297system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
1298system.cpu0.commit.op_class_0::IntAlu 34530023 67.04% 67.04% # Class of committed instruction
1299system.cpu0.commit.op_class_0::IntMult 61866 0.12% 67.16% # Class of committed instruction
1300system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.16% # Class of committed instruction
1301system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.16% # Class of committed instruction
1302system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.16% # Class of committed instruction
1303system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.16% # Class of committed instruction
1304system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.16% # Class of committed instruction
1305system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.16% # Class of committed instruction
1306system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.16% # Class of committed instruction
1307system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.16% # Class of committed instruction
1308system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.16% # Class of committed instruction
1309system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.16% # Class of committed instruction
1310system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.16% # Class of committed instruction
1311system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.16% # Class of committed instruction
1312system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.16% # Class of committed instruction
1313system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.16% # Class of committed instruction
1314system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.16% # Class of committed instruction
1315system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.16% # Class of committed instruction
1316system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.16% # Class of committed instruction
1317system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.16% # Class of committed instruction
1318system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.16% # Class of committed instruction
1319system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.16% # Class of committed instruction
1320system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.16% # Class of committed instruction
1321system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.16% # Class of committed instruction
1322system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.16% # Class of committed instruction
1323system.cpu0.commit.op_class_0::SimdFloatMisc 722 0.00% 67.16% # Class of committed instruction
1324system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.16% # Class of committed instruction
1325system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.16% # Class of committed instruction
1326system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.16% # Class of committed instruction
1327system.cpu0.commit.op_class_0::MemRead 8858661 17.20% 84.36% # Class of committed instruction
1328system.cpu0.commit.op_class_0::MemWrite 8055806 15.64% 100.00% # Class of committed instruction
1329system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1330system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
1331system.cpu0.commit.op_class_0::total 51507078 # Class of committed instruction
1332system.cpu0.commit.bw_lim_events 993842 # number cycles where commit BW limit reached
1333system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
1334system.cpu0.rob.rob_reads 159811836 # The number of ROB reads
1335system.cpu0.rob.rob_writes 108530018 # The number of ROB writes
1336system.cpu0.timesIdled 338876 # Number of times that the entire CPU went into an idle state and unscheduled itself
1337system.cpu0.idleCycles 2587680 # Total number of cycles that the CPU has spent unscheduled due to idling
1338system.cpu0.quiesceCycles 5132257518 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1339system.cpu0.committedInsts 43093164 # Number of Instructions Simulated
1340system.cpu0.committedOps 51426336 # Number of Ops (including micro ops) Simulated
1341system.cpu0.cpi 2.575447 # CPI: Cycles Per Instruction
1342system.cpu0.cpi_total 2.575447 # CPI: Total CPI of All Threads
1343system.cpu0.ipc 0.388282 # IPC: Instructions Per Cycle
1344system.cpu0.ipc_total 0.388282 # IPC: Total IPC of All Threads
1345system.cpu0.int_regfile_reads 67127966 # number of integer regfile reads
1346system.cpu0.int_regfile_writes 33211893 # number of integer regfile writes
1347system.cpu0.fp_regfile_reads 3352 # number of floating regfile reads
1348system.cpu0.fp_regfile_writes 840 # number of floating regfile writes
1349system.cpu0.cc_regfile_reads 191848471 # number of cc regfile reads
1350system.cpu0.cc_regfile_writes 22040987 # number of cc regfile writes
1351system.cpu0.misc_regfile_reads 169210728 # number of misc regfile reads
1352system.cpu0.misc_regfile_writes 593502 # number of misc regfile writes
1353system.cpu0.icache.tags.replacements 554010 # number of replacements
1354system.cpu0.icache.tags.tagsinuse 511.387606 # Cycle average of tags in use
1355system.cpu0.icache.tags.total_refs 15866984 # Total number of references to valid blocks.
1356system.cpu0.icache.tags.sampled_refs 554522 # Sample count of references to valid blocks.
1357system.cpu0.icache.tags.avg_refs 28.613804 # Average number of references to valid blocks.
1358system.cpu0.icache.tags.warmup_cycle 18806389250 # Cycle when the warmup percentage was hit.
1359system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.387606 # Average occupied blocks per requestor
1360system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998804 # Average percentage of cache occupancy
1361system.cpu0.icache.tags.occ_percent::total 0.998804 # Average percentage of cache occupancy
1362system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1363system.cpu0.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id
1364system.cpu0.icache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id
1365system.cpu0.icache.tags.age_task_id_blocks_1024::2 231 # Occupied blocks per task id
1366system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
1367system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1368system.cpu0.icache.tags.tag_accesses 17001271 # Number of tag accesses
1369system.cpu0.icache.tags.data_accesses 17001271 # Number of data accesses
1370system.cpu0.icache.ReadReq_hits::cpu0.inst 15866984 # number of ReadReq hits
1371system.cpu0.icache.ReadReq_hits::total 15866984 # number of ReadReq hits
1372system.cpu0.icache.demand_hits::cpu0.inst 15866984 # number of demand (read+write) hits
1373system.cpu0.icache.demand_hits::total 15866984 # number of demand (read+write) hits
1374system.cpu0.icache.overall_hits::cpu0.inst 15866984 # number of overall hits
1375system.cpu0.icache.overall_hits::total 15866984 # number of overall hits
1376system.cpu0.icache.ReadReq_misses::cpu0.inst 579761 # number of ReadReq misses
1377system.cpu0.icache.ReadReq_misses::total 579761 # number of ReadReq misses
1378system.cpu0.icache.demand_misses::cpu0.inst 579761 # number of demand (read+write) misses
1379system.cpu0.icache.demand_misses::total 579761 # number of demand (read+write) misses
1380system.cpu0.icache.overall_misses::cpu0.inst 579761 # number of overall misses
1381system.cpu0.icache.overall_misses::total 579761 # number of overall misses
1382system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8029558142 # number of ReadReq miss cycles
1383system.cpu0.icache.ReadReq_miss_latency::total 8029558142 # number of ReadReq miss cycles
1384system.cpu0.icache.demand_miss_latency::cpu0.inst 8029558142 # number of demand (read+write) miss cycles
1385system.cpu0.icache.demand_miss_latency::total 8029558142 # number of demand (read+write) miss cycles
1386system.cpu0.icache.overall_miss_latency::cpu0.inst 8029558142 # number of overall miss cycles
1387system.cpu0.icache.overall_miss_latency::total 8029558142 # number of overall miss cycles
1388system.cpu0.icache.ReadReq_accesses::cpu0.inst 16446745 # number of ReadReq accesses(hits+misses)
1389system.cpu0.icache.ReadReq_accesses::total 16446745 # number of ReadReq accesses(hits+misses)
1390system.cpu0.icache.demand_accesses::cpu0.inst 16446745 # number of demand (read+write) accesses
1391system.cpu0.icache.demand_accesses::total 16446745 # number of demand (read+write) accesses
1392system.cpu0.icache.overall_accesses::cpu0.inst 16446745 # number of overall (read+write) accesses
1393system.cpu0.icache.overall_accesses::total 16446745 # number of overall (read+write) accesses
1394system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.035251 # miss rate for ReadReq accesses
1395system.cpu0.icache.ReadReq_miss_rate::total 0.035251 # miss rate for ReadReq accesses
1396system.cpu0.icache.demand_miss_rate::cpu0.inst 0.035251 # miss rate for demand accesses
1397system.cpu0.icache.demand_miss_rate::total 0.035251 # miss rate for demand accesses
1398system.cpu0.icache.overall_miss_rate::cpu0.inst 0.035251 # miss rate for overall accesses
1399system.cpu0.icache.overall_miss_rate::total 0.035251 # miss rate for overall accesses
1400system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13849.772824 # average ReadReq miss latency
1401system.cpu0.icache.ReadReq_avg_miss_latency::total 13849.772824 # average ReadReq miss latency
1402system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13849.772824 # average overall miss latency
1403system.cpu0.icache.demand_avg_miss_latency::total 13849.772824 # average overall miss latency
1404system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13849.772824 # average overall miss latency
1405system.cpu0.icache.overall_avg_miss_latency::total 13849.772824 # average overall miss latency
1406system.cpu0.icache.blocked_cycles::no_mshrs 739 # number of cycles access was blocked
1407system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1408system.cpu0.icache.blocked::no_mshrs 55 # number of cycles access was blocked
1409system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
1410system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.436364 # average number of cycles each access was blocked
1411system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1412system.cpu0.icache.fast_writes 0 # number of fast writes performed
1413system.cpu0.icache.cache_copies 0 # number of cache copies performed
1414system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 25235 # number of ReadReq MSHR hits
1415system.cpu0.icache.ReadReq_mshr_hits::total 25235 # number of ReadReq MSHR hits
1416system.cpu0.icache.demand_mshr_hits::cpu0.inst 25235 # number of demand (read+write) MSHR hits
1417system.cpu0.icache.demand_mshr_hits::total 25235 # number of demand (read+write) MSHR hits
1418system.cpu0.icache.overall_mshr_hits::cpu0.inst 25235 # number of overall MSHR hits
1419system.cpu0.icache.overall_mshr_hits::total 25235 # number of overall MSHR hits
1420system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 554526 # number of ReadReq MSHR misses
1421system.cpu0.icache.ReadReq_mshr_misses::total 554526 # number of ReadReq MSHR misses
1422system.cpu0.icache.demand_mshr_misses::cpu0.inst 554526 # number of demand (read+write) MSHR misses
1423system.cpu0.icache.demand_mshr_misses::total 554526 # number of demand (read+write) MSHR misses
1424system.cpu0.icache.overall_mshr_misses::cpu0.inst 554526 # number of overall MSHR misses
1425system.cpu0.icache.overall_mshr_misses::total 554526 # number of overall MSHR misses
1426system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6629844046 # number of ReadReq MSHR miss cycles
1427system.cpu0.icache.ReadReq_mshr_miss_latency::total 6629844046 # number of ReadReq MSHR miss cycles
1428system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6629844046 # number of demand (read+write) MSHR miss cycles
1429system.cpu0.icache.demand_mshr_miss_latency::total 6629844046 # number of demand (read+write) MSHR miss cycles
1430system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6629844046 # number of overall MSHR miss cycles
1431system.cpu0.icache.overall_mshr_miss_latency::total 6629844046 # number of overall MSHR miss cycles
1432system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 226658500 # number of ReadReq MSHR uncacheable cycles
1433system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 226658500 # number of ReadReq MSHR uncacheable cycles
1434system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 226658500 # number of overall MSHR uncacheable cycles
1435system.cpu0.icache.overall_mshr_uncacheable_latency::total 226658500 # number of overall MSHR uncacheable cycles
1436system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033716 # mshr miss rate for ReadReq accesses
1437system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033716 # mshr miss rate for ReadReq accesses
1438system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033716 # mshr miss rate for demand accesses
1439system.cpu0.icache.demand_mshr_miss_rate::total 0.033716 # mshr miss rate for demand accesses
1440system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033716 # mshr miss rate for overall accesses
1441system.cpu0.icache.overall_mshr_miss_rate::total 0.033716 # mshr miss rate for overall accesses
1442system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11955.875912 # average ReadReq mshr miss latency
1443system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11955.875912 # average ReadReq mshr miss latency
1444system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11955.875912 # average overall mshr miss latency
1445system.cpu0.icache.demand_avg_mshr_miss_latency::total 11955.875912 # average overall mshr miss latency
1446system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11955.875912 # average overall mshr miss latency
1447system.cpu0.icache.overall_avg_mshr_miss_latency::total 11955.875912 # average overall mshr miss latency
1448system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1449system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1450system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1451system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1452system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1453system.cpu0.dcache.tags.replacements 409126 # number of replacements
1454system.cpu0.dcache.tags.tagsinuse 483.194796 # Cycle average of tags in use
1455system.cpu0.dcache.tags.total_refs 12942599 # Total number of references to valid blocks.
1456system.cpu0.dcache.tags.sampled_refs 409638 # Sample count of references to valid blocks.
1457system.cpu0.dcache.tags.avg_refs 31.595211 # Average number of references to valid blocks.
1458system.cpu0.dcache.tags.warmup_cycle 271704250 # Cycle when the warmup percentage was hit.
1459system.cpu0.dcache.tags.occ_blocks::cpu0.data 483.194796 # Average occupied blocks per requestor
1460system.cpu0.dcache.tags.occ_percent::cpu0.data 0.943740 # Average percentage of cache occupancy
1461system.cpu0.dcache.tags.occ_percent::total 0.943740 # Average percentage of cache occupancy
1462system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1463system.cpu0.dcache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id
1464system.cpu0.dcache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id
1465system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
1466system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
1467system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1468system.cpu0.dcache.tags.tag_accesses 63030887 # Number of tag accesses
1469system.cpu0.dcache.tags.data_accesses 63030887 # Number of data accesses
1470system.cpu0.dcache.ReadReq_hits::cpu0.data 8037454 # number of ReadReq hits
1471system.cpu0.dcache.ReadReq_hits::total 8037454 # number of ReadReq hits
1472system.cpu0.dcache.WriteReq_hits::cpu0.data 4509267 # number of WriteReq hits
1473system.cpu0.dcache.WriteReq_hits::total 4509267 # number of WriteReq hits
1474system.cpu0.dcache.SoftPFReq_hits::cpu0.data 46089 # number of SoftPFReq hits
1475system.cpu0.dcache.SoftPFReq_hits::total 46089 # number of SoftPFReq hits
1476system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156971 # number of LoadLockedReq hits
1477system.cpu0.dcache.LoadLockedReq_hits::total 156971 # number of LoadLockedReq hits
1478system.cpu0.dcache.StoreCondReq_hits::cpu0.data 159079 # number of StoreCondReq hits
1479system.cpu0.dcache.StoreCondReq_hits::total 159079 # number of StoreCondReq hits
1480system.cpu0.dcache.demand_hits::cpu0.data 12546721 # number of demand (read+write) hits
1481system.cpu0.dcache.demand_hits::total 12546721 # number of demand (read+write) hits
1482system.cpu0.dcache.overall_hits::cpu0.data 12592810 # number of overall hits
1483system.cpu0.dcache.overall_hits::total 12592810 # number of overall hits
1484system.cpu0.dcache.ReadReq_misses::cpu0.data 406720 # number of ReadReq misses
1485system.cpu0.dcache.ReadReq_misses::total 406720 # number of ReadReq misses
1486system.cpu0.dcache.WriteReq_misses::cpu0.data 2221250 # number of WriteReq misses
1487system.cpu0.dcache.WriteReq_misses::total 2221250 # number of WriteReq misses
1488system.cpu0.dcache.SoftPFReq_misses::cpu0.data 92142 # number of SoftPFReq misses
1489system.cpu0.dcache.SoftPFReq_misses::total 92142 # number of SoftPFReq misses
1490system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10979 # number of LoadLockedReq misses
1491system.cpu0.dcache.LoadLockedReq_misses::total 10979 # number of LoadLockedReq misses
1492system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7659 # number of StoreCondReq misses
1493system.cpu0.dcache.StoreCondReq_misses::total 7659 # number of StoreCondReq misses
1494system.cpu0.dcache.demand_misses::cpu0.data 2627970 # number of demand (read+write) misses
1495system.cpu0.dcache.demand_misses::total 2627970 # number of demand (read+write) misses
1496system.cpu0.dcache.overall_misses::cpu0.data 2720112 # number of overall misses
1497system.cpu0.dcache.overall_misses::total 2720112 # number of overall misses
1498system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5668958645 # number of ReadReq miss cycles
1499system.cpu0.dcache.ReadReq_miss_latency::total 5668958645 # number of ReadReq miss cycles
1500system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 107130503686 # number of WriteReq miss cycles
1501system.cpu0.dcache.WriteReq_miss_latency::total 107130503686 # number of WriteReq miss cycles
1502system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 114563996 # number of LoadLockedReq miss cycles
1503system.cpu0.dcache.LoadLockedReq_miss_latency::total 114563996 # number of LoadLockedReq miss cycles
1504system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44413016 # number of StoreCondReq miss cycles
1505system.cpu0.dcache.StoreCondReq_miss_latency::total 44413016 # number of StoreCondReq miss cycles
1506system.cpu0.dcache.demand_miss_latency::cpu0.data 112799462331 # number of demand (read+write) miss cycles
1507system.cpu0.dcache.demand_miss_latency::total 112799462331 # number of demand (read+write) miss cycles
1508system.cpu0.dcache.overall_miss_latency::cpu0.data 112799462331 # number of overall miss cycles
1509system.cpu0.dcache.overall_miss_latency::total 112799462331 # number of overall miss cycles
1510system.cpu0.dcache.ReadReq_accesses::cpu0.data 8444174 # number of ReadReq accesses(hits+misses)
1511system.cpu0.dcache.ReadReq_accesses::total 8444174 # number of ReadReq accesses(hits+misses)
1512system.cpu0.dcache.WriteReq_accesses::cpu0.data 6730517 # number of WriteReq accesses(hits+misses)
1513system.cpu0.dcache.WriteReq_accesses::total 6730517 # number of WriteReq accesses(hits+misses)
1514system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 138231 # number of SoftPFReq accesses(hits+misses)
1515system.cpu0.dcache.SoftPFReq_accesses::total 138231 # number of SoftPFReq accesses(hits+misses)
1516system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 167950 # number of LoadLockedReq accesses(hits+misses)
1517system.cpu0.dcache.LoadLockedReq_accesses::total 167950 # number of LoadLockedReq accesses(hits+misses)
1518system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166738 # number of StoreCondReq accesses(hits+misses)
1519system.cpu0.dcache.StoreCondReq_accesses::total 166738 # number of StoreCondReq accesses(hits+misses)
1520system.cpu0.dcache.demand_accesses::cpu0.data 15174691 # number of demand (read+write) accesses
1521system.cpu0.dcache.demand_accesses::total 15174691 # number of demand (read+write) accesses
1522system.cpu0.dcache.overall_accesses::cpu0.data 15312922 # number of overall (read+write) accesses
1523system.cpu0.dcache.overall_accesses::total 15312922 # number of overall (read+write) accesses
1524system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.048166 # miss rate for ReadReq accesses
1525system.cpu0.dcache.ReadReq_miss_rate::total 0.048166 # miss rate for ReadReq accesses
1526system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330027 # miss rate for WriteReq accesses
1527system.cpu0.dcache.WriteReq_miss_rate::total 0.330027 # miss rate for WriteReq accesses
1528system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.666580 # miss rate for SoftPFReq accesses
1529system.cpu0.dcache.SoftPFReq_miss_rate::total 0.666580 # miss rate for SoftPFReq accesses
1530system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065371 # miss rate for LoadLockedReq accesses
1531system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065371 # miss rate for LoadLockedReq accesses
1532system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.045934 # miss rate for StoreCondReq accesses
1533system.cpu0.dcache.StoreCondReq_miss_rate::total 0.045934 # miss rate for StoreCondReq accesses
1534system.cpu0.dcache.demand_miss_rate::cpu0.data 0.173181 # miss rate for demand accesses
1535system.cpu0.dcache.demand_miss_rate::total 0.173181 # miss rate for demand accesses
1536system.cpu0.dcache.overall_miss_rate::cpu0.data 0.177635 # miss rate for overall accesses
1537system.cpu0.dcache.overall_miss_rate::total 0.177635 # miss rate for overall accesses
1538system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13938.234277 # average ReadReq miss latency
1539system.cpu0.dcache.ReadReq_avg_miss_latency::total 13938.234277 # average ReadReq miss latency
1540system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48229.827208 # average WriteReq miss latency
1541system.cpu0.dcache.WriteReq_avg_miss_latency::total 48229.827208 # average WriteReq miss latency
1542system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10434.829766 # average LoadLockedReq miss latency
1543system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10434.829766 # average LoadLockedReq miss latency
1544system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5798.800888 # average StoreCondReq miss latency
1545system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5798.800888 # average StoreCondReq miss latency
1546system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 42922.659821 # average overall miss latency
1547system.cpu0.dcache.demand_avg_miss_latency::total 42922.659821 # average overall miss latency
1548system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41468.683029 # average overall miss latency
1549system.cpu0.dcache.overall_avg_miss_latency::total 41468.683029 # average overall miss latency
1550system.cpu0.dcache.blocked_cycles::no_mshrs 14275 # number of cycles access was blocked
1551system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1552system.cpu0.dcache.blocked::no_mshrs 1041 # number of cycles access was blocked
1553system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
1554system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.712776 # average number of cycles each access was blocked
1555system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1556system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1557system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1558system.cpu0.dcache.writebacks::writebacks 375988 # number of writebacks
1559system.cpu0.dcache.writebacks::total 375988 # number of writebacks
1560system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 193747 # number of ReadReq MSHR hits
1561system.cpu0.dcache.ReadReq_mshr_hits::total 193747 # number of ReadReq MSHR hits
1562system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2045363 # number of WriteReq MSHR hits
1563system.cpu0.dcache.WriteReq_mshr_hits::total 2045363 # number of WriteReq MSHR hits
1564system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 1054 # number of LoadLockedReq MSHR hits
1565system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1054 # number of LoadLockedReq MSHR hits
1566system.cpu0.dcache.demand_mshr_hits::cpu0.data 2239110 # number of demand (read+write) MSHR hits
1567system.cpu0.dcache.demand_mshr_hits::total 2239110 # number of demand (read+write) MSHR hits
1568system.cpu0.dcache.overall_mshr_hits::cpu0.data 2239110 # number of overall MSHR hits
1569system.cpu0.dcache.overall_mshr_hits::total 2239110 # number of overall MSHR hits
1570system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 212973 # number of ReadReq MSHR misses
1571system.cpu0.dcache.ReadReq_mshr_misses::total 212973 # number of ReadReq MSHR misses
1572system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175887 # number of WriteReq MSHR misses
1573system.cpu0.dcache.WriteReq_mshr_misses::total 175887 # number of WriteReq MSHR misses
1574system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 54623 # number of SoftPFReq MSHR misses
1575system.cpu0.dcache.SoftPFReq_mshr_misses::total 54623 # number of SoftPFReq MSHR misses
1576system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9925 # number of LoadLockedReq MSHR misses
1577system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9925 # number of LoadLockedReq MSHR misses
1578system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7659 # number of StoreCondReq MSHR misses
1579system.cpu0.dcache.StoreCondReq_mshr_misses::total 7659 # number of StoreCondReq MSHR misses
1580system.cpu0.dcache.demand_mshr_misses::cpu0.data 388860 # number of demand (read+write) MSHR misses
1581system.cpu0.dcache.demand_mshr_misses::total 388860 # number of demand (read+write) MSHR misses
1582system.cpu0.dcache.overall_mshr_misses::cpu0.data 443483 # number of overall MSHR misses
1583system.cpu0.dcache.overall_mshr_misses::total 443483 # number of overall MSHR misses
1584system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2487825853 # number of ReadReq MSHR miss cycles
1585system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2487825853 # number of ReadReq MSHR miss cycles
1586system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7369362883 # number of WriteReq MSHR miss cycles
1587system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7369362883 # number of WriteReq MSHR miss cycles
1588system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1035896777 # number of SoftPFReq MSHR miss cycles
1589system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1035896777 # number of SoftPFReq MSHR miss cycles
1590system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 82981003 # number of LoadLockedReq MSHR miss cycles
1591system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 82981003 # number of LoadLockedReq MSHR miss cycles
1592system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29093984 # number of StoreCondReq MSHR miss cycles
1593system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29093984 # number of StoreCondReq MSHR miss cycles
1594system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9857188736 # number of demand (read+write) MSHR miss cycles
1595system.cpu0.dcache.demand_mshr_miss_latency::total 9857188736 # number of demand (read+write) MSHR miss cycles
1596system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10893085513 # number of overall MSHR miss cycles
1597system.cpu0.dcache.overall_mshr_miss_latency::total 10893085513 # number of overall MSHR miss cycles
1598system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13737621002 # number of ReadReq MSHR uncacheable cycles
1599system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13737621002 # number of ReadReq MSHR uncacheable cycles
1600system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 26275689041 # number of WriteReq MSHR uncacheable cycles
1601system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26275689041 # number of WriteReq MSHR uncacheable cycles
1602system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 40013310043 # number of overall MSHR uncacheable cycles
1603system.cpu0.dcache.overall_mshr_uncacheable_latency::total 40013310043 # number of overall MSHR uncacheable cycles
1604system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025221 # mshr miss rate for ReadReq accesses
1605system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.025221 # mshr miss rate for ReadReq accesses
1606system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026133 # mshr miss rate for WriteReq accesses
1607system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026133 # mshr miss rate for WriteReq accesses
1608system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.395157 # mshr miss rate for SoftPFReq accesses
1609system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.395157 # mshr miss rate for SoftPFReq accesses
1610system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059095 # mshr miss rate for LoadLockedReq accesses
1611system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059095 # mshr miss rate for LoadLockedReq accesses
1612system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.045934 # mshr miss rate for StoreCondReq accesses
1613system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.045934 # mshr miss rate for StoreCondReq accesses
1614system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025626 # mshr miss rate for demand accesses
1615system.cpu0.dcache.demand_mshr_miss_rate::total 0.025626 # mshr miss rate for demand accesses
1616system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028961 # mshr miss rate for overall accesses
1617system.cpu0.dcache.overall_mshr_miss_rate::total 0.028961 # mshr miss rate for overall accesses
1618system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11681.414325 # average ReadReq mshr miss latency
1619system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11681.414325 # average ReadReq mshr miss latency
1620system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41898.280618 # average WriteReq mshr miss latency
1621system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41898.280618 # average WriteReq mshr miss latency
1622system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18964.479743 # average SoftPFReq mshr miss latency
1623system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18964.479743 # average SoftPFReq mshr miss latency
1624system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8360.806348 # average LoadLockedReq mshr miss latency
1625system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8360.806348 # average LoadLockedReq mshr miss latency
1626system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3798.666144 # average StoreCondReq mshr miss latency
1627system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3798.666144 # average StoreCondReq mshr miss latency
1628system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25348.939814 # average overall mshr miss latency
1629system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25348.939814 # average overall mshr miss latency
1630system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24562.577400 # average overall mshr miss latency
1631system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24562.577400 # average overall mshr miss latency
1632system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1633system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1634system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1635system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1636system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1637system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1638system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1639system.cpu1.branchPred.lookups 5001209 # Number of BP lookups
1640system.cpu1.branchPred.condPredicted 3530067 # Number of conditional branches predicted
1641system.cpu1.branchPred.condIncorrect 291977 # Number of conditional branches incorrect
1642system.cpu1.branchPred.BTBLookups 3184313 # Number of BTB lookups
1643system.cpu1.branchPred.BTBHits 2141032 # Number of BTB hits
1644system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1645system.cpu1.branchPred.BTBHitPct 67.236858 # BTB Hit Percentage
1646system.cpu1.branchPred.usedRAS 582225 # Number of times the RAS was used to get a target.
1647system.cpu1.branchPred.RASInCorrect 13211 # Number of incorrect RAS predictions.
1648system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1649system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1650system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1651system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1652system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1653system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1654system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1655system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 7 unchanged lines hidden (view full) ---

1663system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1664system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1665system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1666system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1667system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1668system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1669system.cpu1.dtb.inst_hits 0 # ITB inst hits
1670system.cpu1.dtb.inst_misses 0 # ITB inst misses
1671system.cpu1.dtb.read_hits 21293354 # DTB read hits
1672system.cpu1.dtb.read_misses 17527 # DTB read misses
1673system.cpu1.dtb.write_hits 4063342 # DTB write hits
1674system.cpu1.dtb.write_misses 3266 # DTB write misses
1675system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
1676system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1677system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1678system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1679system.cpu1.dtb.flush_entries 1908 # Number of entries that have been flushed from TLB
1680system.cpu1.dtb.align_faults 789 # Number of TLB faults due to alignment restrictions
1681system.cpu1.dtb.prefetch_faults 274 # Number of TLB faults due to prefetch
1682system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1683system.cpu1.dtb.perms_faults 694 # Number of TLB faults due to permissions restrictions
1684system.cpu1.dtb.read_accesses 21310881 # DTB read accesses
1685system.cpu1.dtb.write_accesses 4066608 # DTB write accesses
1686system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1687system.cpu1.dtb.hits 25356696 # DTB hits
1688system.cpu1.dtb.misses 20793 # DTB misses
1689system.cpu1.dtb.accesses 25377489 # DTB accesses
1690system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1691system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1692system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1693system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1694system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1695system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1696system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1697system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

1703system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1704system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1705system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1706system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1707system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1708system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1709system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1710system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1711system.cpu1.itb.inst_hits 8626509 # ITB inst hits
1712system.cpu1.itb.inst_misses 4363 # ITB inst misses
1713system.cpu1.itb.read_hits 0 # DTB read hits
1714system.cpu1.itb.read_misses 0 # DTB read misses
1715system.cpu1.itb.write_hits 0 # DTB write hits
1716system.cpu1.itb.write_misses 0 # DTB write misses
1717system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
1718system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1719system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1720system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1721system.cpu1.itb.flush_entries 1319 # Number of entries that have been flushed from TLB
1722system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1723system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1724system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1725system.cpu1.itb.perms_faults 2055 # Number of TLB faults due to permissions restrictions
1726system.cpu1.itb.read_accesses 0 # DTB read accesses
1727system.cpu1.itb.write_accesses 0 # DTB write accesses
1728system.cpu1.itb.inst_accesses 8630872 # ITB inst accesses
1729system.cpu1.itb.hits 8626509 # DTB hits
1730system.cpu1.itb.misses 4363 # DTB misses
1731system.cpu1.itb.accesses 8630872 # DTB accesses
1732system.cpu1.numCycles 396849081 # number of cpu cycles simulated
1733system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1734system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1735system.cpu1.fetch.icacheStallCycles 18444788 # Number of cycles fetch is stalled on an Icache miss
1736system.cpu1.fetch.Insts 25760845 # Number of instructions fetch has processed
1737system.cpu1.fetch.Branches 5001209 # Number of branches that fetch encountered
1738system.cpu1.fetch.predictedBranches 2723257 # Number of branches that fetch has predicted taken
1739system.cpu1.fetch.Cycles 375027882 # Number of cycles fetch has run and was not squashing or blocked
1740system.cpu1.fetch.SquashCycles 802688 # Number of cycles fetch has spent squashing
1741system.cpu1.fetch.TlbCycles 60706 # Number of cycles fetch has spent waiting for tlb
1742system.cpu1.fetch.MiscStallCycles 28139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1743system.cpu1.fetch.PendingTrapStallCycles 75697 # Number of stall cycles due to pending traps
1744system.cpu1.fetch.PendingQuiesceStallCycles 1303305 # Number of stall cycles due to pending quiesce instructions
1745system.cpu1.fetch.CacheLines 8624270 # Number of cache lines fetched
1746system.cpu1.fetch.IcacheSquashes 181619 # Number of outstanding Icache misses that were squashed
1747system.cpu1.fetch.ItlbSquashes 1774 # Number of outstanding ITLB misses that were squashed
1748system.cpu1.fetch.rateDist::samples 395341861 # Number of instructions fetched each cycle (Total)
1749system.cpu1.fetch.rateDist::mean 0.079415 # Number of instructions fetched each cycle (Total)
1750system.cpu1.fetch.rateDist::stdev 0.442124 # Number of instructions fetched each cycle (Total)
1751system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1752system.cpu1.fetch.rateDist::0 380851246 96.33% 96.33% # Number of instructions fetched each cycle (Total)
1753system.cpu1.fetch.rateDist::1 4867429 1.23% 97.57% # Number of instructions fetched each cycle (Total)
1754system.cpu1.fetch.rateDist::2 2340779 0.59% 98.16% # Number of instructions fetched each cycle (Total)
1755system.cpu1.fetch.rateDist::3 7282407 1.84% 100.00% # Number of instructions fetched each cycle (Total)
1756system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1757system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1758system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
1759system.cpu1.fetch.rateDist::total 395341861 # Number of instructions fetched each cycle (Total)
1760system.cpu1.fetch.branchRate 0.012602 # Number of branch fetches per cycle
1761system.cpu1.fetch.rate 0.064913 # Number of inst fetches per cycle
1762system.cpu1.decode.IdleCycles 15111141 # Number of cycles decode is idle
1763system.cpu1.decode.BlockedCycles 368322319 # Number of cycles decode is blocked
1764system.cpu1.decode.RunCycles 9619404 # Number of cycles decode is running
1765system.cpu1.decode.UnblockCycles 1988623 # Number of cycles decode is unblocking
1766system.cpu1.decode.SquashCycles 300374 # Number of cycles decode is squashing
1767system.cpu1.decode.BranchResolved 680085 # Number of times decode resolved a branch
1768system.cpu1.decode.BranchMispred 102949 # Number of times decode detected a branch misprediction
1769system.cpu1.decode.DecodedInsts 27336312 # Number of instructions handled by decode
1770system.cpu1.decode.SquashedInsts 828595 # Number of squashed instructions handled by decode
1771system.cpu1.rename.SquashCycles 300374 # Number of cycles rename is squashing
1772system.cpu1.rename.IdleCycles 16508550 # Number of cycles rename is idle
1773system.cpu1.rename.BlockCycles 196017158 # Number of cycles rename is blocking
1774system.cpu1.rename.serializeStallCycles 17889321 # count of cycles rename stalled for serializing inst
1775system.cpu1.rename.RunCycles 9851688 # Number of cycles rename is running
1776system.cpu1.rename.UnblockCycles 154774770 # Number of cycles rename is unblocking
1777system.cpu1.rename.RenamedInsts 26427025 # Number of instructions processed by rename
1778system.cpu1.rename.SquashedInsts 243114 # Number of squashed instructions processed by rename
1779system.cpu1.rename.ROBFullEvents 56891125 # Number of times rename has blocked due to ROB full
1780system.cpu1.rename.IQFullEvents 39780893 # Number of times rename has blocked due to IQ full
1781system.cpu1.rename.LQFullEvents 150628157 # Number of times rename has blocked due to LQ full
1782system.cpu1.rename.SQFullEvents 2138867 # Number of times rename has blocked due to SQ full
1783system.cpu1.rename.RenamedOperands 27113530 # Number of destination operands rename has renamed
1784system.cpu1.rename.RenameLookups 124075273 # Number of register rename lookups that rename has made
1785system.cpu1.rename.int_rename_lookups 31437770 # Number of integer rename lookups
1786system.cpu1.rename.fp_rename_lookups 6241 # Number of floating rename lookups
1787system.cpu1.rename.CommittedMaps 24483458 # Number of HB maps that are committed
1788system.cpu1.rename.UndoneMaps 2630072 # Number of HB maps that are undone due to squashing
1789system.cpu1.rename.serializingInsts 642693 # count of serializing insts renamed
1790system.cpu1.rename.tempSerializingInsts 559165 # count of temporary serializing insts renamed
1791system.cpu1.rename.skidInsts 4862604 # count of insts added to the skid buffer
1792system.cpu1.memDep0.insertedLoads 5657845 # Number of loads inserted to the mem dependence unit.
1793system.cpu1.memDep0.insertedStores 4330093 # Number of stores inserted to the mem dependence unit.
1794system.cpu1.memDep0.conflictingLoads 343073 # Number of conflicting loads.
1795system.cpu1.memDep0.conflictingStores 498131 # Number of conflicting stores.
1796system.cpu1.iq.iqInstsAdded 25260320 # Number of instructions added to the IQ (excludes non-spec)
1797system.cpu1.iq.iqNonSpecInstsAdded 861912 # Number of non-speculative instructions added to the IQ
1798system.cpu1.iq.iqInstsIssued 41442639 # Number of instructions issued
1799system.cpu1.iq.iqSquashedInstsIssued 78274 # Number of squashed instructions issued
1800system.cpu1.iq.iqSquashedInstsExamined 1902061 # Number of squashed instructions iterated over during squash; mainly for profiling
1801system.cpu1.iq.iqSquashedOperandsExamined 3789747 # Number of squashed operands that are examined and possibly removed from graph
1802system.cpu1.iq.iqSquashedNonSpecRemoved 92749 # Number of squashed non-spec instructions that were removed
1803system.cpu1.iq.issued_per_cycle::samples 395341861 # Number of insts issued each cycle
1804system.cpu1.iq.issued_per_cycle::mean 0.104827 # Number of insts issued each cycle
1805system.cpu1.iq.issued_per_cycle::stdev 0.383209 # Number of insts issued each cycle
1806system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1807system.cpu1.iq.issued_per_cycle::0 362283147 91.64% 91.64% # Number of insts issued each cycle
1808system.cpu1.iq.issued_per_cycle::1 26570133 6.72% 98.36% # Number of insts issued each cycle
1809system.cpu1.iq.issued_per_cycle::2 4792582 1.21% 99.57% # Number of insts issued each cycle
1810system.cpu1.iq.issued_per_cycle::3 1496663 0.38% 99.95% # Number of insts issued each cycle
1811system.cpu1.iq.issued_per_cycle::4 199327 0.05% 100.00% # Number of insts issued each cycle
1812system.cpu1.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle
1813system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
1814system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
1815system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
1816system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1817system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1818system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
1819system.cpu1.iq.issued_per_cycle::total 395341861 # Number of insts issued each cycle
1820system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1821system.cpu1.iq.fu_full::IntAlu 1195141 5.96% 5.96% # attempts to use FU when none available
1822system.cpu1.iq.fu_full::IntMult 685 0.00% 5.96% # attempts to use FU when none available
1823system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.96% # attempts to use FU when none available
1824system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.96% # attempts to use FU when none available
1825system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.96% # attempts to use FU when none available
1826system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.96% # attempts to use FU when none available
1827system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.96% # attempts to use FU when none available
1828system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.96% # attempts to use FU when none available
1829system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.96% # attempts to use FU when none available
1830system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.96% # attempts to use FU when none available
1831system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.96% # attempts to use FU when none available
1832system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.96% # attempts to use FU when none available
1833system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.96% # attempts to use FU when none available
1834system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.96% # attempts to use FU when none available
1835system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.96% # attempts to use FU when none available
1836system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.96% # attempts to use FU when none available
1837system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.96% # attempts to use FU when none available
1838system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.96% # attempts to use FU when none available
1839system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.96% # attempts to use FU when none available
1840system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.96% # attempts to use FU when none available
1841system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.96% # attempts to use FU when none available
1842system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.96% # attempts to use FU when none available
1843system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.96% # attempts to use FU when none available
1844system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.96% # attempts to use FU when none available
1845system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.96% # attempts to use FU when none available
1846system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.96% # attempts to use FU when none available
1847system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.96% # attempts to use FU when none available
1848system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.96% # attempts to use FU when none available
1849system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.96% # attempts to use FU when none available
1850system.cpu1.iq.fu_full::MemRead 16909984 84.32% 90.29% # attempts to use FU when none available
1851system.cpu1.iq.fu_full::MemWrite 1947822 9.71% 100.00% # attempts to use FU when none available
1852system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1853system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1854system.cpu1.iq.FU_type_0::No_OpClass 13868 0.03% 0.03% # Type of FU issued
1855system.cpu1.iq.FU_type_0::IntAlu 15563362 37.55% 37.59% # Type of FU issued
1856system.cpu1.iq.FU_type_0::IntMult 33954 0.08% 37.67% # Type of FU issued
1857system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 37.67% # Type of FU issued
1858system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 37.67% # Type of FU issued
1859system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 37.67% # Type of FU issued
1860system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 37.67% # Type of FU issued
1861system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 37.67% # Type of FU issued
1862system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 37.67% # Type of FU issued
1863system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 37.67% # Type of FU issued
1864system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 37.67% # Type of FU issued
1865system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 37.67% # Type of FU issued
1866system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 37.67% # Type of FU issued
1867system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 37.67% # Type of FU issued
1868system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 37.67% # Type of FU issued
1869system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 37.67% # Type of FU issued
1870system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 37.67% # Type of FU issued
1871system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 37.67% # Type of FU issued
1872system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 37.67% # Type of FU issued
1873system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 37.67% # Type of FU issued
1874system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 37.67% # Type of FU issued
1875system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.67% # Type of FU issued
1876system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.67% # Type of FU issued
1877system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.67% # Type of FU issued
1878system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.67% # Type of FU issued
1879system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.67% # Type of FU issued
1880system.cpu1.iq.FU_type_0::SimdFloatMisc 1648 0.00% 37.67% # Type of FU issued
1881system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 37.67% # Type of FU issued
1882system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 37.67% # Type of FU issued
1883system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.67% # Type of FU issued
1884system.cpu1.iq.FU_type_0::MemRead 21553207 52.01% 89.68% # Type of FU issued
1885system.cpu1.iq.FU_type_0::MemWrite 4276600 10.32% 100.00% # Type of FU issued
1886system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1887system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1888system.cpu1.iq.FU_type_0::total 41442639 # Type of FU issued
1889system.cpu1.iq.rate 0.104429 # Inst issue rate
1890system.cpu1.iq.fu_busy_cnt 20053632 # FU busy when requested
1891system.cpu1.iq.fu_busy_rate 0.483889 # FU busy rate (busy events/executed inst)
1892system.cpu1.iq.int_inst_queue_reads 498337881 # Number of integer instruction queue reads
1893system.cpu1.iq.int_inst_queue_writes 28019357 # Number of integer instruction queue writes
1894system.cpu1.iq.int_inst_queue_wakeup_accesses 25018416 # Number of integer instruction queue wakeup accesses
1895system.cpu1.iq.fp_inst_queue_reads 21164 # Number of floating instruction queue reads
1896system.cpu1.iq.fp_inst_queue_writes 7936 # Number of floating instruction queue writes
1897system.cpu1.iq.fp_inst_queue_wakeup_accesses 6759 # Number of floating instruction queue wakeup accesses
1898system.cpu1.iq.int_alu_accesses 61468547 # Number of integer alu accesses
1899system.cpu1.iq.fp_alu_accesses 13856 # Number of floating point alu accesses
1900system.cpu1.iew.lsq.thread0.forwLoads 72058 # Number of loads that had data forwarded from stores
1901system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1902system.cpu1.iew.lsq.thread0.squashedLoads 455146 # Number of loads squashed
1903system.cpu1.iew.lsq.thread0.ignoredResponses 306 # Number of memory responses ignored because the instruction is squashed
1904system.cpu1.iew.lsq.thread0.memOrderViolation 3014 # Number of memory ordering violations
1905system.cpu1.iew.lsq.thread0.squashedStores 163146 # Number of stores squashed
1906system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1907system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1908system.cpu1.iew.lsq.thread0.rescheduledLoads 15996057 # Number of loads that were rescheduled
1909system.cpu1.iew.lsq.thread0.cacheBlocked 1487 # Number of times an access to memory failed due to the cache being blocked
1910system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1911system.cpu1.iew.iewSquashCycles 300374 # Number of cycles IEW is squashing
1912system.cpu1.iew.iewBlockCycles 87167513 # Number of cycles IEW is blocking
1913system.cpu1.iew.iewUnblockCycles 92299631 # Number of cycles IEW is unblocking
1914system.cpu1.iew.iewDispatchedInsts 26204459 # Number of instructions dispatched to IQ
1915system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
1916system.cpu1.iew.iewDispLoadInsts 5657845 # Number of dispatched load instructions
1917system.cpu1.iew.iewDispStoreInsts 4330093 # Number of dispatched store instructions
1918system.cpu1.iew.iewDispNonSpecInsts 630570 # Number of dispatched non-speculative instructions
1919system.cpu1.iew.iewIQFullEvents 9334 # Number of times the IQ has become full, causing a stall
1920system.cpu1.iew.iewLSQFullEvents 92232105 # Number of times the LSQ has become full, causing a stall
1921system.cpu1.iew.memOrderViolationEvents 3014 # Number of memory order violations
1922system.cpu1.iew.predictedTakenIncorrect 83298 # Number of branches that were predicted taken incorrectly
1923system.cpu1.iew.predictedNotTakenIncorrect 118271 # Number of branches that were predicted not taken incorrectly
1924system.cpu1.iew.branchMispredicts 201569 # Number of branch mispredicts detected at execute
1925system.cpu1.iew.iewExecutedInsts 41178523 # Number of executed instructions
1926system.cpu1.iew.iewExecLoadInsts 21441390 # Number of load instructions executed
1927system.cpu1.iew.iewExecSquashedInsts 243431 # Number of squashed instructions skipped in execute
1928system.cpu1.iew.exec_swp 0 # number of swp insts executed
1929system.cpu1.iew.exec_nop 82227 # number of nop insts executed
1930system.cpu1.iew.exec_refs 25682989 # number of memory reference insts executed
1931system.cpu1.iew.exec_branches 3899404 # Number of branches executed
1932system.cpu1.iew.exec_stores 4241599 # Number of stores executed
1933system.cpu1.iew.exec_rate 0.103764 # Inst execution rate
1934system.cpu1.iew.wb_sent 41086324 # cumulative count of insts sent to commit
1935system.cpu1.iew.wb_count 25025175 # cumulative count of insts written-back
1936system.cpu1.iew.wb_producers 11348419 # num instructions producing a value
1937system.cpu1.iew.wb_consumers 16538487 # num instructions consuming a value
1938system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1939system.cpu1.iew.wb_rate 0.063060 # insts written-back per cycle
1940system.cpu1.iew.wb_fanout 0.686182 # average fanout of values written-back
1941system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1942system.cpu1.commit.commitSquashedInsts 1702265 # The number of squashed insts skipped by commit
1943system.cpu1.commit.commitNonSpecStalls 769163 # The number of times commit has been forced to stall to communicate backwards
1944system.cpu1.commit.branchMispredicts 191007 # The number of times a branch was mispredicted
1945system.cpu1.commit.committed_per_cycle::samples 394940200 # Number of insts commited each cycle
1946system.cpu1.commit.committed_per_cycle::mean 0.061056 # Number of insts commited each cycle
1947system.cpu1.commit.committed_per_cycle::stdev 0.422241 # Number of insts commited each cycle
1948system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1949system.cpu1.commit.committed_per_cycle::0 381244473 96.53% 96.53% # Number of insts commited each cycle
1950system.cpu1.commit.committed_per_cycle::1 9114140 2.31% 98.84% # Number of insts commited each cycle
1951system.cpu1.commit.committed_per_cycle::2 2236589 0.57% 99.41% # Number of insts commited each cycle
1952system.cpu1.commit.committed_per_cycle::3 955406 0.24% 99.65% # Number of insts commited each cycle
1953system.cpu1.commit.committed_per_cycle::4 446570 0.11% 99.76% # Number of insts commited each cycle
1954system.cpu1.commit.committed_per_cycle::5 403381 0.10% 99.86% # Number of insts commited each cycle
1955system.cpu1.commit.committed_per_cycle::6 181575 0.05% 99.91% # Number of insts commited each cycle
1956system.cpu1.commit.committed_per_cycle::7 97100 0.02% 99.93% # Number of insts commited each cycle
1957system.cpu1.commit.committed_per_cycle::8 260966 0.07% 100.00% # Number of insts commited each cycle
1958system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1959system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1960system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1961system.cpu1.commit.committed_per_cycle::total 394940200 # Number of insts commited each cycle
1962system.cpu1.commit.committedInsts 19609371 # Number of instructions committed
1963system.cpu1.commit.committedOps 24113599 # Number of ops (including micro ops) committed
1964system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
1965system.cpu1.commit.refs 9369646 # Number of memory references committed
1966system.cpu1.commit.loads 5202699 # Number of loads committed
1967system.cpu1.commit.membars 162322 # Number of memory barriers committed
1968system.cpu1.commit.branches 3698878 # Number of branches committed
1969system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
1970system.cpu1.commit.int_insts 21204966 # Number of committed integer instructions.
1971system.cpu1.commit.function_calls 385194 # Number of function calls committed.
1972system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
1973system.cpu1.commit.op_class_0::IntAlu 14709151 61.00% 61.00% # Class of committed instruction
1974system.cpu1.commit.op_class_0::IntMult 33154 0.14% 61.14% # Class of committed instruction
1975system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.14% # Class of committed instruction
1976system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.14% # Class of committed instruction
1977system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.14% # Class of committed instruction
1978system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.14% # Class of committed instruction
1979system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.14% # Class of committed instruction
1980system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.14% # Class of committed instruction
1981system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.14% # Class of committed instruction
1982system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.14% # Class of committed instruction
1983system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.14% # Class of committed instruction
1984system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.14% # Class of committed instruction
1985system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.14% # Class of committed instruction
1986system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.14% # Class of committed instruction
1987system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.14% # Class of committed instruction
1988system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.14% # Class of committed instruction
1989system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.14% # Class of committed instruction
1990system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.14% # Class of committed instruction
1991system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.14% # Class of committed instruction
1992system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.14% # Class of committed instruction
1993system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.14% # Class of committed instruction
1994system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.14% # Class of committed instruction
1995system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.14% # Class of committed instruction
1996system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.14% # Class of committed instruction
1997system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.14% # Class of committed instruction
1998system.cpu1.commit.op_class_0::SimdFloatMisc 1648 0.01% 61.14% # Class of committed instruction
1999system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.14% # Class of committed instruction
2000system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.14% # Class of committed instruction
2001system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.14% # Class of committed instruction
2002system.cpu1.commit.op_class_0::MemRead 5202699 21.58% 82.72% # Class of committed instruction
2003system.cpu1.commit.op_class_0::MemWrite 4166947 17.28% 100.00% # Class of committed instruction
2004system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2005system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2006system.cpu1.commit.op_class_0::total 24113599 # Class of committed instruction
2007system.cpu1.commit.bw_lim_events 260966 # number cycles where commit BW limit reached
2008system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
2009system.cpu1.rob.rob_reads 419589246 # The number of ROB reads
2010system.cpu1.rob.rob_writes 52032512 # The number of ROB writes
2011system.cpu1.timesIdled 248745 # Number of times that the entire CPU went into an idle state and unscheduled itself
2012system.cpu1.idleCycles 1507220 # Total number of cycles that the CPU has spent unscheduled due to idling
2013system.cpu1.quiesceCycles 4845699469 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2014system.cpu1.committedInsts 19539732 # Number of Instructions Simulated
2015system.cpu1.committedOps 24043960 # Number of Ops (including micro ops) Simulated
2016system.cpu1.cpi 20.309853 # CPI: Cycles Per Instruction
2017system.cpu1.cpi_total 20.309853 # CPI: Total CPI of All Threads
2018system.cpu1.ipc 0.049237 # IPC: Instructions Per Cycle
2019system.cpu1.ipc_total 0.049237 # IPC: Total IPC of All Threads
2020system.cpu1.int_regfile_reads 45343306 # number of integer regfile reads
2021system.cpu1.int_regfile_writes 15599183 # number of integer regfile writes
2022system.cpu1.fp_regfile_reads 5046 # number of floating regfile reads
2023system.cpu1.fp_regfile_writes 2260 # number of floating regfile writes
2024system.cpu1.cc_regfile_reads 139131439 # number of cc regfile reads
2025system.cpu1.cc_regfile_writes 9348976 # number of cc regfile writes
2026system.cpu1.misc_regfile_reads 454367618 # number of misc regfile reads
2027system.cpu1.misc_regfile_writes 623445 # number of misc regfile writes
2028system.cpu1.icache.tags.replacements 439266 # number of replacements
2029system.cpu1.icache.tags.tagsinuse 497.815366 # Cycle average of tags in use
2030system.cpu1.icache.tags.total_refs 8166304 # Total number of references to valid blocks.
2031system.cpu1.icache.tags.sampled_refs 439778 # Sample count of references to valid blocks.
2032system.cpu1.icache.tags.avg_refs 18.569151 # Average number of references to valid blocks.
2033system.cpu1.icache.tags.warmup_cycle 119618152250 # Cycle when the warmup percentage was hit.
2034system.cpu1.icache.tags.occ_blocks::cpu1.inst 497.815366 # Average occupied blocks per requestor
2035system.cpu1.icache.tags.occ_percent::cpu1.inst 0.972296 # Average percentage of cache occupancy
2036system.cpu1.icache.tags.occ_percent::total 0.972296 # Average percentage of cache occupancy
2037system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2038system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id
2039system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
2040system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2041system.cpu1.icache.tags.tag_accesses 9063984 # Number of tag accesses
2042system.cpu1.icache.tags.data_accesses 9063984 # Number of data accesses
2043system.cpu1.icache.ReadReq_hits::cpu1.inst 8166304 # number of ReadReq hits
2044system.cpu1.icache.ReadReq_hits::total 8166304 # number of ReadReq hits
2045system.cpu1.icache.demand_hits::cpu1.inst 8166304 # number of demand (read+write) hits
2046system.cpu1.icache.demand_hits::total 8166304 # number of demand (read+write) hits
2047system.cpu1.icache.overall_hits::cpu1.inst 8166304 # number of overall hits
2048system.cpu1.icache.overall_hits::total 8166304 # number of overall hits
2049system.cpu1.icache.ReadReq_misses::cpu1.inst 457900 # number of ReadReq misses
2050system.cpu1.icache.ReadReq_misses::total 457900 # number of ReadReq misses
2051system.cpu1.icache.demand_misses::cpu1.inst 457900 # number of demand (read+write) misses
2052system.cpu1.icache.demand_misses::total 457900 # number of demand (read+write) misses
2053system.cpu1.icache.overall_misses::cpu1.inst 457900 # number of overall misses
2054system.cpu1.icache.overall_misses::total 457900 # number of overall misses
2055system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6264180115 # number of ReadReq miss cycles
2056system.cpu1.icache.ReadReq_miss_latency::total 6264180115 # number of ReadReq miss cycles
2057system.cpu1.icache.demand_miss_latency::cpu1.inst 6264180115 # number of demand (read+write) miss cycles
2058system.cpu1.icache.demand_miss_latency::total 6264180115 # number of demand (read+write) miss cycles
2059system.cpu1.icache.overall_miss_latency::cpu1.inst 6264180115 # number of overall miss cycles
2060system.cpu1.icache.overall_miss_latency::total 6264180115 # number of overall miss cycles
2061system.cpu1.icache.ReadReq_accesses::cpu1.inst 8624204 # number of ReadReq accesses(hits+misses)
2062system.cpu1.icache.ReadReq_accesses::total 8624204 # number of ReadReq accesses(hits+misses)
2063system.cpu1.icache.demand_accesses::cpu1.inst 8624204 # number of demand (read+write) accesses
2064system.cpu1.icache.demand_accesses::total 8624204 # number of demand (read+write) accesses
2065system.cpu1.icache.overall_accesses::cpu1.inst 8624204 # number of overall (read+write) accesses
2066system.cpu1.icache.overall_accesses::total 8624204 # number of overall (read+write) accesses
2067system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.053095 # miss rate for ReadReq accesses
2068system.cpu1.icache.ReadReq_miss_rate::total 0.053095 # miss rate for ReadReq accesses
2069system.cpu1.icache.demand_miss_rate::cpu1.inst 0.053095 # miss rate for demand accesses
2070system.cpu1.icache.demand_miss_rate::total 0.053095 # miss rate for demand accesses
2071system.cpu1.icache.overall_miss_rate::cpu1.inst 0.053095 # miss rate for overall accesses
2072system.cpu1.icache.overall_miss_rate::total 0.053095 # miss rate for overall accesses
2073system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13680.236111 # average ReadReq miss latency
2074system.cpu1.icache.ReadReq_avg_miss_latency::total 13680.236111 # average ReadReq miss latency
2075system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13680.236111 # average overall miss latency
2076system.cpu1.icache.demand_avg_miss_latency::total 13680.236111 # average overall miss latency
2077system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13680.236111 # average overall miss latency
2078system.cpu1.icache.overall_avg_miss_latency::total 13680.236111 # average overall miss latency
2079system.cpu1.icache.blocked_cycles::no_mshrs 882 # number of cycles access was blocked
2080system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2081system.cpu1.icache.blocked::no_mshrs 53 # number of cycles access was blocked
2082system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
2083system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.641509 # average number of cycles each access was blocked
2084system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2085system.cpu1.icache.fast_writes 0 # number of fast writes performed
2086system.cpu1.icache.cache_copies 0 # number of cache copies performed
2087system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 18120 # number of ReadReq MSHR hits
2088system.cpu1.icache.ReadReq_mshr_hits::total 18120 # number of ReadReq MSHR hits
2089system.cpu1.icache.demand_mshr_hits::cpu1.inst 18120 # number of demand (read+write) MSHR hits
2090system.cpu1.icache.demand_mshr_hits::total 18120 # number of demand (read+write) MSHR hits
2091system.cpu1.icache.overall_mshr_hits::cpu1.inst 18120 # number of overall MSHR hits
2092system.cpu1.icache.overall_mshr_hits::total 18120 # number of overall MSHR hits
2093system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 439780 # number of ReadReq MSHR misses
2094system.cpu1.icache.ReadReq_mshr_misses::total 439780 # number of ReadReq MSHR misses
2095system.cpu1.icache.demand_mshr_misses::cpu1.inst 439780 # number of demand (read+write) MSHR misses
2096system.cpu1.icache.demand_mshr_misses::total 439780 # number of demand (read+write) MSHR misses
2097system.cpu1.icache.overall_mshr_misses::cpu1.inst 439780 # number of overall MSHR misses
2098system.cpu1.icache.overall_mshr_misses::total 439780 # number of overall MSHR misses
2099system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5188034078 # number of ReadReq MSHR miss cycles
2100system.cpu1.icache.ReadReq_mshr_miss_latency::total 5188034078 # number of ReadReq MSHR miss cycles
2101system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5188034078 # number of demand (read+write) MSHR miss cycles
2102system.cpu1.icache.demand_mshr_miss_latency::total 5188034078 # number of demand (read+write) MSHR miss cycles
2103system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5188034078 # number of overall MSHR miss cycles
2104system.cpu1.icache.overall_mshr_miss_latency::total 5188034078 # number of overall MSHR miss cycles
2105system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4304000 # number of ReadReq MSHR uncacheable cycles
2106system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4304000 # number of ReadReq MSHR uncacheable cycles
2107system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4304000 # number of overall MSHR uncacheable cycles
2108system.cpu1.icache.overall_mshr_uncacheable_latency::total 4304000 # number of overall MSHR uncacheable cycles
2109system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.050994 # mshr miss rate for ReadReq accesses
2110system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.050994 # mshr miss rate for ReadReq accesses
2111system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.050994 # mshr miss rate for demand accesses
2112system.cpu1.icache.demand_mshr_miss_rate::total 0.050994 # mshr miss rate for demand accesses
2113system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.050994 # mshr miss rate for overall accesses
2114system.cpu1.icache.overall_mshr_miss_rate::total 0.050994 # mshr miss rate for overall accesses
2115system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11796.884983 # average ReadReq mshr miss latency
2116system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11796.884983 # average ReadReq mshr miss latency
2117system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11796.884983 # average overall mshr miss latency
2118system.cpu1.icache.demand_avg_mshr_miss_latency::total 11796.884983 # average overall mshr miss latency
2119system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11796.884983 # average overall mshr miss latency
2120system.cpu1.icache.overall_avg_mshr_miss_latency::total 11796.884983 # average overall mshr miss latency
2121system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
2122system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2123system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
2124system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2125system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2126system.cpu1.dcache.tags.replacements 227040 # number of replacements
2127system.cpu1.dcache.tags.tagsinuse 492.830733 # Cycle average of tags in use
2128system.cpu1.dcache.tags.total_refs 7082160 # Total number of references to valid blocks.
2129system.cpu1.dcache.tags.sampled_refs 227406 # Sample count of references to valid blocks.
2130system.cpu1.dcache.tags.avg_refs 31.143242 # Average number of references to valid blocks.
2131system.cpu1.dcache.tags.warmup_cycle 99092137500 # Cycle when the warmup percentage was hit.
2132system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.830733 # Average occupied blocks per requestor
2133system.cpu1.dcache.tags.occ_percent::cpu1.data 0.962560 # Average percentage of cache occupancy
2134system.cpu1.dcache.tags.occ_percent::total 0.962560 # Average percentage of cache occupancy
2135system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id
2136system.cpu1.dcache.tags.age_task_id_blocks_1024::2 366 # Occupied blocks per task id
2137system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id
2138system.cpu1.dcache.tags.tag_accesses 32684037 # Number of tag accesses
2139system.cpu1.dcache.tags.data_accesses 32684037 # Number of data accesses
2140system.cpu1.dcache.ReadReq_hits::cpu1.data 3792757 # number of ReadReq hits
2141system.cpu1.dcache.ReadReq_hits::total 3792757 # number of ReadReq hits
2142system.cpu1.dcache.WriteReq_hits::cpu1.data 3094601 # number of WriteReq hits
2143system.cpu1.dcache.WriteReq_hits::total 3094601 # number of WriteReq hits
2144system.cpu1.dcache.SoftPFReq_hits::cpu1.data 14161 # number of SoftPFReq hits
2145system.cpu1.dcache.SoftPFReq_hits::total 14161 # number of SoftPFReq hits
2146system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 75622 # number of LoadLockedReq hits
2147system.cpu1.dcache.LoadLockedReq_hits::total 75622 # number of LoadLockedReq hits
2148system.cpu1.dcache.StoreCondReq_hits::cpu1.data 75613 # number of StoreCondReq hits
2149system.cpu1.dcache.StoreCondReq_hits::total 75613 # number of StoreCondReq hits
2150system.cpu1.dcache.demand_hits::cpu1.data 6887358 # number of demand (read+write) hits
2151system.cpu1.dcache.demand_hits::total 6887358 # number of demand (read+write) hits
2152system.cpu1.dcache.overall_hits::cpu1.data 6901519 # number of overall hits
2153system.cpu1.dcache.overall_hits::total 6901519 # number of overall hits
2154system.cpu1.dcache.ReadReq_misses::cpu1.data 187422 # number of ReadReq misses
2155system.cpu1.dcache.ReadReq_misses::total 187422 # number of ReadReq misses
2156system.cpu1.dcache.WriteReq_misses::cpu1.data 806941 # number of WriteReq misses
2157system.cpu1.dcache.WriteReq_misses::total 806941 # number of WriteReq misses
2158system.cpu1.dcache.SoftPFReq_misses::cpu1.data 41483 # number of SoftPFReq misses
2159system.cpu1.dcache.SoftPFReq_misses::total 41483 # number of SoftPFReq misses
2160system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10414 # number of LoadLockedReq misses
2161system.cpu1.dcache.LoadLockedReq_misses::total 10414 # number of LoadLockedReq misses
2162system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9617 # number of StoreCondReq misses
2163system.cpu1.dcache.StoreCondReq_misses::total 9617 # number of StoreCondReq misses
2164system.cpu1.dcache.demand_misses::cpu1.data 994363 # number of demand (read+write) misses
2165system.cpu1.dcache.demand_misses::total 994363 # number of demand (read+write) misses
2166system.cpu1.dcache.overall_misses::cpu1.data 1035846 # number of overall misses
2167system.cpu1.dcache.overall_misses::total 1035846 # number of overall misses
2168system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2444126213 # number of ReadReq miss cycles
2169system.cpu1.dcache.ReadReq_miss_latency::total 2444126213 # number of ReadReq miss cycles
2170system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 27779707617 # number of WriteReq miss cycles
2171system.cpu1.dcache.WriteReq_miss_latency::total 27779707617 # number of WriteReq miss cycles
2172system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 86490246 # number of LoadLockedReq miss cycles
2173system.cpu1.dcache.LoadLockedReq_miss_latency::total 86490246 # number of LoadLockedReq miss cycles
2174system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53209125 # number of StoreCondReq miss cycles
2175system.cpu1.dcache.StoreCondReq_miss_latency::total 53209125 # number of StoreCondReq miss cycles
2176system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 14000 # number of StoreCondFailReq miss cycles
2177system.cpu1.dcache.StoreCondFailReq_miss_latency::total 14000 # number of StoreCondFailReq miss cycles
2178system.cpu1.dcache.demand_miss_latency::cpu1.data 30223833830 # number of demand (read+write) miss cycles
2179system.cpu1.dcache.demand_miss_latency::total 30223833830 # number of demand (read+write) miss cycles
2180system.cpu1.dcache.overall_miss_latency::cpu1.data 30223833830 # number of overall miss cycles
2181system.cpu1.dcache.overall_miss_latency::total 30223833830 # number of overall miss cycles
2182system.cpu1.dcache.ReadReq_accesses::cpu1.data 3980179 # number of ReadReq accesses(hits+misses)
2183system.cpu1.dcache.ReadReq_accesses::total 3980179 # number of ReadReq accesses(hits+misses)
2184system.cpu1.dcache.WriteReq_accesses::cpu1.data 3901542 # number of WriteReq accesses(hits+misses)
2185system.cpu1.dcache.WriteReq_accesses::total 3901542 # number of WriteReq accesses(hits+misses)
2186system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 55644 # number of SoftPFReq accesses(hits+misses)
2187system.cpu1.dcache.SoftPFReq_accesses::total 55644 # number of SoftPFReq accesses(hits+misses)
2188system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86036 # number of LoadLockedReq accesses(hits+misses)
2189system.cpu1.dcache.LoadLockedReq_accesses::total 86036 # number of LoadLockedReq accesses(hits+misses)
2190system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85230 # number of StoreCondReq accesses(hits+misses)
2191system.cpu1.dcache.StoreCondReq_accesses::total 85230 # number of StoreCondReq accesses(hits+misses)
2192system.cpu1.dcache.demand_accesses::cpu1.data 7881721 # number of demand (read+write) accesses
2193system.cpu1.dcache.demand_accesses::total 7881721 # number of demand (read+write) accesses
2194system.cpu1.dcache.overall_accesses::cpu1.data 7937365 # number of overall (read+write) accesses
2195system.cpu1.dcache.overall_accesses::total 7937365 # number of overall (read+write) accesses
2196system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.047089 # miss rate for ReadReq accesses
2197system.cpu1.dcache.ReadReq_miss_rate::total 0.047089 # miss rate for ReadReq accesses
2198system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.206826 # miss rate for WriteReq accesses
2199system.cpu1.dcache.WriteReq_miss_rate::total 0.206826 # miss rate for WriteReq accesses
2200system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.745507 # miss rate for SoftPFReq accesses
2201system.cpu1.dcache.SoftPFReq_miss_rate::total 0.745507 # miss rate for SoftPFReq accesses
2202system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.121042 # miss rate for LoadLockedReq accesses
2203system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.121042 # miss rate for LoadLockedReq accesses
2204system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112836 # miss rate for StoreCondReq accesses
2205system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112836 # miss rate for StoreCondReq accesses
2206system.cpu1.dcache.demand_miss_rate::cpu1.data 0.126161 # miss rate for demand accesses
2207system.cpu1.dcache.demand_miss_rate::total 0.126161 # miss rate for demand accesses
2208system.cpu1.dcache.overall_miss_rate::cpu1.data 0.130503 # miss rate for overall accesses
2209system.cpu1.dcache.overall_miss_rate::total 0.130503 # miss rate for overall accesses
2210system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13040.764761 # average ReadReq miss latency
2211system.cpu1.dcache.ReadReq_avg_miss_latency::total 13040.764761 # average ReadReq miss latency
2212system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34425.946404 # average WriteReq miss latency
2213system.cpu1.dcache.WriteReq_avg_miss_latency::total 34425.946404 # average WriteReq miss latency
2214system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8305.189745 # average LoadLockedReq miss latency
2215system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8305.189745 # average LoadLockedReq miss latency
2216system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5532.819486 # average StoreCondReq miss latency
2217system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5532.819486 # average StoreCondReq miss latency
2218system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
2219system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2220system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30395.171411 # average overall miss latency
2221system.cpu1.dcache.demand_avg_miss_latency::total 30395.171411 # average overall miss latency
2222system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29177.922037 # average overall miss latency
2223system.cpu1.dcache.overall_avg_miss_latency::total 29177.922037 # average overall miss latency
2224system.cpu1.dcache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked
2225system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2226system.cpu1.dcache.blocked::no_mshrs 723 # number of cycles access was blocked
2227system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
2228system.cpu1.dcache.avg_blocked_cycles::no_mshrs 6.190871 # average number of cycles each access was blocked
2229system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2230system.cpu1.dcache.fast_writes 0 # number of fast writes performed
2231system.cpu1.dcache.cache_copies 0 # number of cache copies performed
2232system.cpu1.dcache.writebacks::writebacks 207281 # number of writebacks
2233system.cpu1.dcache.writebacks::total 207281 # number of writebacks
2234system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 70540 # number of ReadReq MSHR hits
2235system.cpu1.dcache.ReadReq_mshr_hits::total 70540 # number of ReadReq MSHR hits
2236system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 693700 # number of WriteReq MSHR hits
2237system.cpu1.dcache.WriteReq_mshr_hits::total 693700 # number of WriteReq MSHR hits
2238system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 500 # number of LoadLockedReq MSHR hits
2239system.cpu1.dcache.LoadLockedReq_mshr_hits::total 500 # number of LoadLockedReq MSHR hits
2240system.cpu1.dcache.demand_mshr_hits::cpu1.data 764240 # number of demand (read+write) MSHR hits
2241system.cpu1.dcache.demand_mshr_hits::total 764240 # number of demand (read+write) MSHR hits
2242system.cpu1.dcache.overall_mshr_hits::cpu1.data 764240 # number of overall MSHR hits
2243system.cpu1.dcache.overall_mshr_hits::total 764240 # number of overall MSHR hits
2244system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116882 # number of ReadReq MSHR misses
2245system.cpu1.dcache.ReadReq_mshr_misses::total 116882 # number of ReadReq MSHR misses
2246system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 113241 # number of WriteReq MSHR misses
2247system.cpu1.dcache.WriteReq_mshr_misses::total 113241 # number of WriteReq MSHR misses
2248system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23891 # number of SoftPFReq MSHR misses
2249system.cpu1.dcache.SoftPFReq_mshr_misses::total 23891 # number of SoftPFReq MSHR misses
2250system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9914 # number of LoadLockedReq MSHR misses
2251system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9914 # number of LoadLockedReq MSHR misses
2252system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9617 # number of StoreCondReq MSHR misses
2253system.cpu1.dcache.StoreCondReq_mshr_misses::total 9617 # number of StoreCondReq MSHR misses
2254system.cpu1.dcache.demand_mshr_misses::cpu1.data 230123 # number of demand (read+write) MSHR misses
2255system.cpu1.dcache.demand_mshr_misses::total 230123 # number of demand (read+write) MSHR misses
2256system.cpu1.dcache.overall_mshr_misses::cpu1.data 254014 # number of overall MSHR misses
2257system.cpu1.dcache.overall_mshr_misses::total 254014 # number of overall MSHR misses
2258system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1203808322 # number of ReadReq MSHR miss cycles
2259system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1203808322 # number of ReadReq MSHR miss cycles
2260system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3988299754 # number of WriteReq MSHR miss cycles
2261system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3988299754 # number of WriteReq MSHR miss cycles
2262system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 341716536 # number of SoftPFReq MSHR miss cycles
2263system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 341716536 # number of SoftPFReq MSHR miss cycles
2264system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 60834504 # number of LoadLockedReq MSHR miss cycles
2265system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 60834504 # number of LoadLockedReq MSHR miss cycles
2266system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 33974875 # number of StoreCondReq MSHR miss cycles
2267system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 33974875 # number of StoreCondReq MSHR miss cycles
2268system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 12000 # number of StoreCondFailReq MSHR miss cycles
2269system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 12000 # number of StoreCondFailReq MSHR miss cycles
2270system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5192108076 # number of demand (read+write) MSHR miss cycles
2271system.cpu1.dcache.demand_mshr_miss_latency::total 5192108076 # number of demand (read+write) MSHR miss cycles
2272system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5533824612 # number of overall MSHR miss cycles
2273system.cpu1.dcache.overall_mshr_miss_latency::total 5533824612 # number of overall MSHR miss cycles
2274system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168973544758 # number of ReadReq MSHR uncacheable cycles
2275system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168973544758 # number of ReadReq MSHR uncacheable cycles
2276system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 522517625 # number of WriteReq MSHR uncacheable cycles
2277system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 522517625 # number of WriteReq MSHR uncacheable cycles
2278system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 169496062383 # number of overall MSHR uncacheable cycles
2279system.cpu1.dcache.overall_mshr_uncacheable_latency::total 169496062383 # number of overall MSHR uncacheable cycles
2280system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029366 # mshr miss rate for ReadReq accesses
2281system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029366 # mshr miss rate for ReadReq accesses
2282system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029025 # mshr miss rate for WriteReq accesses
2283system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029025 # mshr miss rate for WriteReq accesses
2284system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.429354 # mshr miss rate for SoftPFReq accesses
2285system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.429354 # mshr miss rate for SoftPFReq accesses
2286system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.115231 # mshr miss rate for LoadLockedReq accesses
2287system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.115231 # mshr miss rate for LoadLockedReq accesses
2288system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112836 # mshr miss rate for StoreCondReq accesses
2289system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112836 # mshr miss rate for StoreCondReq accesses
2290system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029197 # mshr miss rate for demand accesses
2291system.cpu1.dcache.demand_mshr_miss_rate::total 0.029197 # mshr miss rate for demand accesses
2292system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032002 # mshr miss rate for overall accesses
2293system.cpu1.dcache.overall_mshr_miss_rate::total 0.032002 # mshr miss rate for overall accesses
2294system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10299.347393 # average ReadReq mshr miss latency
2295system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10299.347393 # average ReadReq mshr miss latency
2296system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35219.573776 # average WriteReq mshr miss latency
2297system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35219.573776 # average WriteReq mshr miss latency
2298system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14303.149136 # average SoftPFReq mshr miss latency
2299system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 14303.149136 # average SoftPFReq mshr miss latency
2300system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6136.221908 # average LoadLockedReq mshr miss latency
2301system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6136.221908 # average LoadLockedReq mshr miss latency
2302system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3532.793491 # average StoreCondReq mshr miss latency
2303system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3532.793491 # average StoreCondReq mshr miss latency
2304system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
2305system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2306system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22562.317004 # average overall mshr miss latency
2307system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22562.317004 # average overall mshr miss latency
2308system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21785.510295 # average overall mshr miss latency
2309system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21785.510295 # average overall mshr miss latency
2310system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
2311system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2312system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
2313system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
2314system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
2315system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2316system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2317system.iocache.tags.replacements 0 # number of replacements

--- 7 unchanged lines hidden (view full) ---

2325system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2326system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2327system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2328system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2329system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2330system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2331system.iocache.fast_writes 0 # number of fast writes performed
2332system.iocache.cache_copies 0 # number of cache copies performed
2333system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736665659303 # number of ReadReq MSHR uncacheable cycles
2334system.iocache.ReadReq_mshr_uncacheable_latency::total 1736665659303 # number of ReadReq MSHR uncacheable cycles
2335system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736665659303 # number of overall MSHR uncacheable cycles
2336system.iocache.overall_mshr_uncacheable_latency::total 1736665659303 # number of overall MSHR uncacheable cycles
2337system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
2338system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2339system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
2340system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2341system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2342system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2343system.cpu0.kern.inst.quiesce 52427 # number of quiesce instructions executed
2344system.cpu1.kern.inst.arm 0 # number of arm instructions executed
2345system.cpu1.kern.inst.quiesce 40685 # number of quiesce instructions executed
2346
2347---------- End Simulation Statistics ----------