1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.593146 # Number of seconds simulated
4sim_ticks 2593146078000 # Number of ticks simulated
5final_tick 2593146078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 66425 # Simulator instruction rate (inst/s)
8host_op_rate 85503 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2731005239 # Simulator tick rate (ticks/s)
10host_mem_usage 409388 # Number of bytes of host memory used
11host_seconds 949.52 # Real time elapsed on the host
12sim_insts 63072130 # Number of instructions simulated
13sim_ops 81187111 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.inst 395328 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.data 4376500 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.inst 426752 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.data 5261232 # Number of bytes read from this memory
23system.physmem.bytes_read::total 131572388 # Number of bytes read from this memory
24system.physmem.bytes_inst_read::cpu0.inst 395328 # Number of instructions bytes read from this memory
25system.physmem.bytes_inst_read::cpu1.inst 426752 # Number of instructions bytes read from this memory
26system.physmem.bytes_inst_read::total 822080 # Number of instructions bytes read from this memory
27system.physmem.bytes_written::writebacks 4282048 # Number of bytes written to this memory
28system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
29system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
30system.physmem.bytes_written::total 7311184 # Number of bytes written to this memory
31system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
32system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu0.inst 6177 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.data 68455 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu1.inst 6668 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu1.data 82233 # Number of read requests responded to by this memory
40system.physmem.num_reads::total 15302381 # Number of read requests responded to by this memory
41system.physmem.num_writes::writebacks 66907 # Number of write requests responded to by this memory
42system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
43system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
44system.physmem.num_writes::total 824191 # Number of write requests responded to by this memory
45system.physmem.bw_read::realview.clcd 46704090 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu0.dtb.walker 346 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::cpu0.inst 152451 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_read::cpu0.data 1687718 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu1.dtb.walker 370 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu1.inst 164569 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu1.data 2028899 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::total 50738518 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_inst_read::cpu0.inst 152451 # Instruction read bandwidth from this memory (bytes/s)
56system.physmem.bw_inst_read::cpu1.inst 164569 # Instruction read bandwidth from this memory (bytes/s)
57system.physmem.bw_inst_read::total 317020 # Instruction read bandwidth from this memory (bytes/s)
58system.physmem.bw_write::writebacks 1651295 # Write bandwidth from this memory (bytes/s)
59system.physmem.bw_write::cpu0.data 6556 # Write bandwidth from this memory (bytes/s)
60system.physmem.bw_write::cpu1.data 1161576 # Write bandwidth from this memory (bytes/s)
61system.physmem.bw_write::total 2819426 # Write bandwidth from this memory (bytes/s)
62system.physmem.bw_total::writebacks 1651295 # Total bandwidth to/from this memory (bytes/s)
63system.physmem.bw_total::realview.clcd 46704090 # Total bandwidth to/from this memory (bytes/s)
64system.physmem.bw_total::cpu0.dtb.walker 346 # Total bandwidth to/from this memory (bytes/s)
65system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
66system.physmem.bw_total::cpu0.inst 152451 # Total bandwidth to/from this memory (bytes/s)
67system.physmem.bw_total::cpu0.data 1694274 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::cpu1.dtb.walker 370 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::cpu1.inst 164569 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu1.data 3190475 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::total 53557944 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.readReqs 15302381 # Total number of read requests seen
74system.physmem.writeReqs 824191 # Total number of write requests seen
75system.physmem.cpureqs 284713 # Reqs generatd by CPU via cache - shady
76system.physmem.bytesRead 979352384 # Total number of bytes read from memory
77system.physmem.bytesWritten 52748224 # Total number of bytes written to memory
78system.physmem.bytesConsumedRd 131572388 # bytesRead derated as per pkt->getSize()
79system.physmem.bytesConsumedWr 7311184 # bytesWritten derated as per pkt->getSize()
80system.physmem.servicedByWrQ 335 # Number of read reqs serviced by write Q
81system.physmem.neitherReadNorWrite 14131 # Reqs where no action is needed
82system.physmem.perBankRdReqs::0 956528 # Track reads on a per bank basis
83system.physmem.perBankRdReqs::1 956655 # Track reads on a per bank basis
84system.physmem.perBankRdReqs::2 956404 # Track reads on a per bank basis
85system.physmem.perBankRdReqs::3 956499 # Track reads on a per bank basis
86system.physmem.perBankRdReqs::4 956473 # Track reads on a per bank basis
87system.physmem.perBankRdReqs::5 956086 # Track reads on a per bank basis
88system.physmem.perBankRdReqs::6 955879 # Track reads on a per bank basis
89system.physmem.perBankRdReqs::7 956080 # Track reads on a per bank basis
90system.physmem.perBankRdReqs::8 957009 # Track reads on a per bank basis
91system.physmem.perBankRdReqs::9 956354 # Track reads on a per bank basis
92system.physmem.perBankRdReqs::10 956393 # Track reads on a per bank basis
93system.physmem.perBankRdReqs::11 956606 # Track reads on a per bank basis
94system.physmem.perBankRdReqs::12 956350 # Track reads on a per bank basis
95system.physmem.perBankRdReqs::13 956542 # Track reads on a per bank basis
96system.physmem.perBankRdReqs::14 956247 # Track reads on a per bank basis
97system.physmem.perBankRdReqs::15 955941 # Track reads on a per bank basis
98system.physmem.perBankWrReqs::0 50875 # Track writes on a per bank basis
99system.physmem.perBankWrReqs::1 51001 # Track writes on a per bank basis
100system.physmem.perBankWrReqs::2 50801 # Track writes on a per bank basis
101system.physmem.perBankWrReqs::3 50933 # Track writes on a per bank basis
102system.physmem.perBankWrReqs::4 51869 # Track writes on a per bank basis
103system.physmem.perBankWrReqs::5 51569 # Track writes on a per bank basis
104system.physmem.perBankWrReqs::6 51383 # Track writes on a per bank basis
105system.physmem.perBankWrReqs::7 51546 # Track writes on a per bank basis
106system.physmem.perBankWrReqs::8 52151 # Track writes on a per bank basis
107system.physmem.perBankWrReqs::9 51788 # Track writes on a per bank basis
108system.physmem.perBankWrReqs::10 51664 # Track writes on a per bank basis
109system.physmem.perBankWrReqs::11 51769 # Track writes on a per bank basis
110system.physmem.perBankWrReqs::12 51735 # Track writes on a per bank basis
111system.physmem.perBankWrReqs::13 51864 # Track writes on a per bank basis
112system.physmem.perBankWrReqs::14 51697 # Track writes on a per bank basis
113system.physmem.perBankWrReqs::15 51546 # Track writes on a per bank basis
114system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
115system.physmem.numWrRetry 1150487 # Number of times wr buffer was full causing retry
116system.physmem.totGap 2593144762500 # Total gap between requests
117system.physmem.readPktSize::0 0 # Categorize read packet sizes
118system.physmem.readPktSize::1 0 # Categorize read packet sizes
119system.physmem.readPktSize::2 105 # Categorize read packet sizes
120system.physmem.readPktSize::3 15138816 # Categorize read packet sizes
121system.physmem.readPktSize::4 0 # Categorize read packet sizes
122system.physmem.readPktSize::5 0 # Categorize read packet sizes
123system.physmem.readPktSize::6 163460 # Categorize read packet sizes
124system.physmem.readPktSize::7 0 # Categorize read packet sizes
125system.physmem.readPktSize::8 0 # Categorize read packet sizes
126system.physmem.writePktSize::0 0 # categorize write packet sizes
127system.physmem.writePktSize::1 0 # categorize write packet sizes
128system.physmem.writePktSize::2 1907771 # categorize write packet sizes
129system.physmem.writePktSize::3 0 # categorize write packet sizes
130system.physmem.writePktSize::4 0 # categorize write packet sizes
131system.physmem.writePktSize::5 0 # categorize write packet sizes
132system.physmem.writePktSize::6 66907 # categorize write packet sizes
133system.physmem.writePktSize::7 0 # categorize write packet sizes
134system.physmem.writePktSize::8 0 # categorize write packet sizes
135system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
136system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
137system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
138system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
139system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
140system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
141system.physmem.neitherpktsize::6 14131 # categorize neither packet sizes
142system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
143system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
144system.physmem.rdQLenPdf::0 15151641 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 94331 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 8809 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 3486 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 2848 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 2557 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 2313 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::7 1993 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::8 1407 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::9 1368 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::10 1369 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::11 6472 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::12 9621 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::13 13063 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::14 592 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::15 97 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::16 54 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::17 23 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
165system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
176system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
177system.physmem.wrQLenPdf::0 3183 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::1 3385 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::2 3534 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::3 3673 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::4 3833 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::5 4027 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::6 4248 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::7 4407 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::8 4586 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::9 35834 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::10 35834 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::11 35834 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::12 35834 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::13 35834 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::14 35834 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::15 35834 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::16 35834 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::17 35834 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::18 35834 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::19 35834 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::20 35834 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::21 35834 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::22 35834 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::23 32652 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::24 32450 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::25 32301 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::26 32162 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::27 32002 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::28 31808 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::29 31587 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::30 31428 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::31 31249 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
210system.physmem.totQLat 47868619345 # Total cycles spent in queuing delays
211system.physmem.totMemAccLat 322210199345 # Sum of mem lat for all requests
212system.physmem.totBusLat 61208184000 # Total cycles spent in databus access
213system.physmem.totBankLat 213133396000 # Total cycles spent in bank access
214system.physmem.avgQLat 3128.25 # Average queueing delay per request
215system.physmem.avgBankLat 13928.42 # Average bank access latency per request
216system.physmem.avgBusLat 4000.00 # Average bus latency per request
217system.physmem.avgMemAccLat 21056.67 # Average memory access latency
218system.physmem.avgRdBW 377.67 # Average achieved read bandwidth in MB/s
219system.physmem.avgWrBW 20.34 # Average achieved write bandwidth in MB/s
220system.physmem.avgConsumedRdBW 50.74 # Average consumed read bandwidth in MB/s
221system.physmem.avgConsumedWrBW 2.82 # Average consumed write bandwidth in MB/s
222system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
223system.physmem.busUtil 2.49 # Data bus utilization in percentage
224system.physmem.avgRdQLen 0.12 # Average read queue length over time
225system.physmem.avgWrQLen 10.88 # Average write queue length over time
226system.physmem.readRowHits 15253448 # Number of row buffer hits during reads
227system.physmem.writeRowHits 789566 # Number of row buffer hits during writes
228system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads
229system.physmem.writeRowHitRate 95.80 # Row buffer hit rate for writes
230system.physmem.avgGap 160799.50 # Average gap between requests
231system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
232system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
233system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
234system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
235system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory
236system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
237system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
238system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
239system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
240system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
241system.realview.nvmem.bw_read::cpu1.inst 148 # Total read bandwidth from this memory (bytes/s)
242system.realview.nvmem.bw_read::total 173 # Total read bandwidth from this memory (bytes/s)
243system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
244system.realview.nvmem.bw_inst_read::cpu1.inst 148 # Instruction read bandwidth from this memory (bytes/s)
245system.realview.nvmem.bw_inst_read::total 173 # Instruction read bandwidth from this memory (bytes/s)
246system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
247system.realview.nvmem.bw_total::cpu1.inst 148 # Total bandwidth to/from this memory (bytes/s)
248system.realview.nvmem.bw_total::total 173 # Total bandwidth to/from this memory (bytes/s)
249system.l2c.replacements 73184 # number of replacements
250system.l2c.tagsinuse 53096.266008 # Cycle average of tags in use
251system.l2c.total_refs 1906265 # Total number of references to valid blocks.
252system.l2c.sampled_refs 138351 # Sample count of references to valid blocks.
253system.l2c.avg_refs 13.778469 # Average number of references to valid blocks.
254system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
255system.l2c.occ_blocks::writebacks 37733.790025 # Average occupied blocks per requestor
256system.l2c.occ_blocks::cpu0.dtb.walker 7.219153 # Average occupied blocks per requestor
257system.l2c.occ_blocks::cpu0.itb.walker 0.000341 # Average occupied blocks per requestor
258system.l2c.occ_blocks::cpu0.inst 4206.047810 # Average occupied blocks per requestor
259system.l2c.occ_blocks::cpu0.data 2960.317078 # Average occupied blocks per requestor
260system.l2c.occ_blocks::cpu1.dtb.walker 11.178862 # Average occupied blocks per requestor
261system.l2c.occ_blocks::cpu1.itb.walker 0.966447 # Average occupied blocks per requestor
262system.l2c.occ_blocks::cpu1.inst 4058.933416 # Average occupied blocks per requestor
263system.l2c.occ_blocks::cpu1.data 4117.812877 # Average occupied blocks per requestor
264system.l2c.occ_percent::writebacks 0.575772 # Average percentage of cache occupancy
265system.l2c.occ_percent::cpu0.dtb.walker 0.000110 # Average percentage of cache occupancy
266system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
267system.l2c.occ_percent::cpu0.inst 0.064179 # Average percentage of cache occupancy
268system.l2c.occ_percent::cpu0.data 0.045171 # Average percentage of cache occupancy
269system.l2c.occ_percent::cpu1.dtb.walker 0.000171 # Average percentage of cache occupancy
270system.l2c.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy
271system.l2c.occ_percent::cpu1.inst 0.061934 # Average percentage of cache occupancy
272system.l2c.occ_percent::cpu1.data 0.062833 # Average percentage of cache occupancy
273system.l2c.occ_percent::total 0.810185 # Average percentage of cache occupancy
274system.l2c.ReadReq_hits::cpu0.dtb.walker 33579 # number of ReadReq hits
275system.l2c.ReadReq_hits::cpu0.itb.walker 4963 # number of ReadReq hits
276system.l2c.ReadReq_hits::cpu0.inst 393016 # number of ReadReq hits
277system.l2c.ReadReq_hits::cpu0.data 165084 # number of ReadReq hits
278system.l2c.ReadReq_hits::cpu1.dtb.walker 53008 # number of ReadReq hits
279system.l2c.ReadReq_hits::cpu1.itb.walker 6038 # number of ReadReq hits
280system.l2c.ReadReq_hits::cpu1.inst 608232 # number of ReadReq hits
281system.l2c.ReadReq_hits::cpu1.data 201468 # number of ReadReq hits
282system.l2c.ReadReq_hits::total 1465388 # number of ReadReq hits
283system.l2c.Writeback_hits::writebacks 583960 # number of Writeback hits
284system.l2c.Writeback_hits::total 583960 # number of Writeback hits
285system.l2c.UpgradeReq_hits::cpu0.data 1107 # number of UpgradeReq hits
286system.l2c.UpgradeReq_hits::cpu1.data 848 # number of UpgradeReq hits
287system.l2c.UpgradeReq_hits::total 1955 # number of UpgradeReq hits
288system.l2c.SCUpgradeReq_hits::cpu0.data 209 # number of SCUpgradeReq hits
289system.l2c.SCUpgradeReq_hits::cpu1.data 159 # number of SCUpgradeReq hits
290system.l2c.SCUpgradeReq_hits::total 368 # number of SCUpgradeReq hits
291system.l2c.ReadExReq_hits::cpu0.data 47823 # number of ReadExReq hits
292system.l2c.ReadExReq_hits::cpu1.data 59123 # number of ReadExReq hits
293system.l2c.ReadExReq_hits::total 106946 # number of ReadExReq hits
294system.l2c.demand_hits::cpu0.dtb.walker 33579 # number of demand (read+write) hits
295system.l2c.demand_hits::cpu0.itb.walker 4963 # number of demand (read+write) hits
296system.l2c.demand_hits::cpu0.inst 393016 # number of demand (read+write) hits
297system.l2c.demand_hits::cpu0.data 212907 # number of demand (read+write) hits
298system.l2c.demand_hits::cpu1.dtb.walker 53008 # number of demand (read+write) hits
299system.l2c.demand_hits::cpu1.itb.walker 6038 # number of demand (read+write) hits
300system.l2c.demand_hits::cpu1.inst 608232 # number of demand (read+write) hits
301system.l2c.demand_hits::cpu1.data 260591 # number of demand (read+write) hits
302system.l2c.demand_hits::total 1572334 # number of demand (read+write) hits
303system.l2c.overall_hits::cpu0.dtb.walker 33579 # number of overall hits
304system.l2c.overall_hits::cpu0.itb.walker 4963 # number of overall hits
305system.l2c.overall_hits::cpu0.inst 393016 # number of overall hits
306system.l2c.overall_hits::cpu0.data 212907 # number of overall hits
307system.l2c.overall_hits::cpu1.dtb.walker 53008 # number of overall hits
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555system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 998025 # number of ReadReq MSHR miss cycles
556system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93002 # number of ReadReq MSHR miss cycles
557system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 243809691 # number of ReadReq MSHR miss cycles
558system.l2c.ReadReq_mshr_miss_latency::cpu0.data 262215347 # number of ReadReq MSHR miss cycles
559system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 849526 # number of ReadReq MSHR miss cycles
560system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 109502 # number of ReadReq MSHR miss cycles
561system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 287575375 # number of ReadReq MSHR miss cycles
562system.l2c.ReadReq_mshr_miss_latency::cpu1.data 287912849 # number of ReadReq MSHR miss cycles
563system.l2c.ReadReq_mshr_miss_latency::total 1083563317 # number of ReadReq MSHR miss cycles
564system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 57255976 # number of UpgradeReq MSHR miss cycles
565system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 44756275 # number of UpgradeReq MSHR miss cycles
566system.l2c.UpgradeReq_mshr_miss_latency::total 102012251 # number of UpgradeReq MSHR miss cycles
567system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7762758 # number of SCUpgradeReq MSHR miss cycles
568system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5877575 # number of SCUpgradeReq MSHR miss cycles
569system.l2c.SCUpgradeReq_mshr_miss_latency::total 13640333 # number of SCUpgradeReq MSHR miss cycles
570system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2369346199 # number of ReadExReq MSHR miss cycles
571system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3313598990 # number of ReadExReq MSHR miss cycles
572system.l2c.ReadExReq_mshr_miss_latency::total 5682945189 # number of ReadExReq MSHR miss cycles
573system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 998025 # number of demand (read+write) MSHR miss cycles
574system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93002 # number of demand (read+write) MSHR miss cycles
575system.l2c.demand_mshr_miss_latency::cpu0.inst 243809691 # number of demand (read+write) MSHR miss cycles
576system.l2c.demand_mshr_miss_latency::cpu0.data 2631561546 # number of demand (read+write) MSHR miss cycles
577system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 849526 # number of demand (read+write) MSHR miss cycles
578system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 109502 # number of demand (read+write) MSHR miss cycles
579system.l2c.demand_mshr_miss_latency::cpu1.inst 287575375 # number of demand (read+write) MSHR miss cycles
580system.l2c.demand_mshr_miss_latency::cpu1.data 3601511839 # number of demand (read+write) MSHR miss cycles
581system.l2c.demand_mshr_miss_latency::total 6766508506 # number of demand (read+write) MSHR miss cycles
582system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 998025 # number of overall MSHR miss cycles
583system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93002 # number of overall MSHR miss cycles
584system.l2c.overall_mshr_miss_latency::cpu0.inst 243809691 # number of overall MSHR miss cycles
585system.l2c.overall_mshr_miss_latency::cpu0.data 2631561546 # number of overall MSHR miss cycles
586system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 849526 # number of overall MSHR miss cycles
587system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 109502 # number of overall MSHR miss cycles
588system.l2c.overall_mshr_miss_latency::cpu1.inst 287575375 # number of overall MSHR miss cycles
589system.l2c.overall_mshr_miss_latency::cpu1.data 3601511839 # number of overall MSHR miss cycles
590system.l2c.overall_mshr_miss_latency::total 6766508506 # number of overall MSHR miss cycles
591system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4558163 # number of ReadReq MSHR uncacheable cycles
592system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12330302064 # number of ReadReq MSHR uncacheable cycles
593system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1815064 # number of ReadReq MSHR uncacheable cycles
594system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154912119500 # number of ReadReq MSHR uncacheable cycles
595system.l2c.ReadReq_mshr_uncacheable_latency::total 167248794791 # number of ReadReq MSHR uncacheable cycles
596system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1062521236 # number of WriteReq MSHR uncacheable cycles
597system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 17116054868 # number of WriteReq MSHR uncacheable cycles
598system.l2c.WriteReq_mshr_uncacheable_latency::total 18178576104 # number of WriteReq MSHR uncacheable cycles
599system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4558163 # number of overall MSHR uncacheable cycles
600system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13392823300 # number of overall MSHR uncacheable cycles
601system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1815064 # number of overall MSHR uncacheable cycles
602system.l2c.overall_mshr_uncacheable_latency::cpu1.data 172028174368 # number of overall MSHR uncacheable cycles
603system.l2c.overall_mshr_uncacheable_latency::total 185427370895 # number of overall MSHR uncacheable cycles
604system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000417 # mshr miss rate for ReadReq accesses
605system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000403 # mshr miss rate for ReadReq accesses
606system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015168 # mshr miss rate for ReadReq accesses
607system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036785 # mshr miss rate for ReadReq accesses
608system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000283 # mshr miss rate for ReadReq accesses
609system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000166 # mshr miss rate for ReadReq accesses
610system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010775 # mshr miss rate for ReadReq accesses
611system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030491 # mshr miss rate for ReadReq accesses
612system.l2c.ReadReq_mshr_miss_rate::total 0.017006 # mshr miss rate for ReadReq accesses
613system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.836990 # mshr miss rate for UpgradeReq accesses
614system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.838538 # mshr miss rate for UpgradeReq accesses
615system.l2c.UpgradeReq_mshr_miss_rate::total 0.837665 # mshr miss rate for UpgradeReq accesses
616system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787169 # mshr miss rate for SCUpgradeReq accesses
617system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.786290 # mshr miss rate for SCUpgradeReq accesses
618system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.786790 # mshr miss rate for SCUpgradeReq accesses
619system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.570486 # mshr miss rate for ReadExReq accesses
620system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.566003 # mshr miss rate for ReadExReq accesses
621system.l2c.ReadExReq_mshr_miss_rate::total 0.568019 # mshr miss rate for ReadExReq accesses
622system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000417 # mshr miss rate for demand accesses
623system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000403 # mshr miss rate for demand accesses
624system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015168 # mshr miss rate for demand accesses
625system.l2c.demand_mshr_miss_rate::cpu0.data 0.246931 # mshr miss rate for demand accesses
626system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000283 # mshr miss rate for demand accesses
627system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000166 # mshr miss rate for demand accesses
628system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010775 # mshr miss rate for demand accesses
629system.l2c.demand_mshr_miss_rate::cpu1.data 0.242525 # mshr miss rate for demand accesses
630system.l2c.demand_mshr_miss_rate::total 0.095478 # mshr miss rate for demand accesses
631system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000417 # mshr miss rate for overall accesses
632system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000403 # mshr miss rate for overall accesses
633system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015168 # mshr miss rate for overall accesses
634system.l2c.overall_mshr_miss_rate::cpu0.data 0.246931 # mshr miss rate for overall accesses
635system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000283 # mshr miss rate for overall accesses
636system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000166 # mshr miss rate for overall accesses
637system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010775 # mshr miss rate for overall accesses
638system.l2c.overall_mshr_miss_rate::cpu1.data 0.242525 # mshr miss rate for overall accesses
639system.l2c.overall_mshr_miss_rate::total 0.095478 # mshr miss rate for overall accesses
640system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71287.500000 # average ReadReq mshr miss latency
641system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average ReadReq mshr miss latency
642system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40279.149347 # average ReadReq mshr miss latency
643system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 41581.881859 # average ReadReq mshr miss latency
644system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average ReadReq mshr miss latency
645system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average ReadReq mshr miss latency
646system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average ReadReq mshr miss latency
647system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45433.619852 # average ReadReq mshr miss latency
648system.l2c.ReadReq_avg_mshr_miss_latency::total 42739.057192 # average ReadReq mshr miss latency
649system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10073.183673 # average UpgradeReq mshr miss latency
650system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10162.641916 # average UpgradeReq mshr miss latency
651system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10112.237411 # average UpgradeReq mshr miss latency
652system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.377749 # average SCUpgradeReq mshr miss latency
653system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10047.136752 # average SCUpgradeReq mshr miss latency
654system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10044.427835 # average SCUpgradeReq mshr miss latency
655system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37301.377525 # average ReadExReq mshr miss latency
656system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42974.593287 # average ReadExReq mshr miss latency
657system.l2c.ReadExReq_avg_mshr_miss_latency::total 40412.054677 # average ReadExReq mshr miss latency
658system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71287.500000 # average overall mshr miss latency
659system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency
660system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40279.149347 # average overall mshr miss latency
661system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37687.956262 # average overall mshr miss latency
662system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average overall mshr miss latency
663system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average overall mshr miss latency
664system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average overall mshr miss latency
665system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43161.341742 # average overall mshr miss latency
666system.l2c.demand_avg_mshr_miss_latency::total 40767.502356 # average overall mshr miss latency
667system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71287.500000 # average overall mshr miss latency
668system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency
669system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40279.149347 # average overall mshr miss latency
670system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37687.956262 # average overall mshr miss latency
671system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average overall mshr miss latency
672system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average overall mshr miss latency
673system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average overall mshr miss latency
674system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43161.341742 # average overall mshr miss latency
675system.l2c.overall_avg_mshr_miss_latency::total 40767.502356 # average overall mshr miss latency
676system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
677system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
678system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
679system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
680system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
681system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
682system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
683system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency

--- 6 unchanged lines hidden (view full) ---

690system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
691system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
692system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
693system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
694system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
695system.cf0.dma_write_txs 0 # Number of DMA write transactions.
696system.cpu0.dtb.inst_hits 0 # ITB inst hits
697system.cpu0.dtb.inst_misses 0 # ITB inst misses
698system.cpu0.dtb.read_hits 9014303 # DTB read hits
699system.cpu0.dtb.read_misses 34965 # DTB read misses
700system.cpu0.dtb.write_hits 5253714 # DTB write hits
701system.cpu0.dtb.write_misses 6399 # DTB write misses
702system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
703system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
704system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
705system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
706system.cpu0.dtb.flush_entries 2155 # Number of entries that have been flushed from TLB
707system.cpu0.dtb.align_faults 1094 # Number of TLB faults due to alignment restrictions
708system.cpu0.dtb.prefetch_faults 321 # Number of TLB faults due to prefetch
709system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
710system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions
711system.cpu0.dtb.read_accesses 9049268 # DTB read accesses
712system.cpu0.dtb.write_accesses 5260113 # DTB write accesses
713system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
714system.cpu0.dtb.hits 14268017 # DTB hits
715system.cpu0.dtb.misses 41364 # DTB misses
716system.cpu0.dtb.accesses 14309381 # DTB accesses
717system.cpu0.itb.inst_hits 4294311 # ITB inst hits
718system.cpu0.itb.inst_misses 5261 # ITB inst misses
719system.cpu0.itb.read_hits 0 # DTB read hits
720system.cpu0.itb.read_misses 0 # DTB read misses
721system.cpu0.itb.write_hits 0 # DTB write hits
722system.cpu0.itb.write_misses 0 # DTB write misses
723system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
724system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
725system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
726system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
727system.cpu0.itb.flush_entries 1385 # Number of entries that have been flushed from TLB
728system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
729system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
730system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
731system.cpu0.itb.perms_faults 1364 # Number of TLB faults due to permissions restrictions
732system.cpu0.itb.read_accesses 0 # DTB read accesses
733system.cpu0.itb.write_accesses 0 # DTB write accesses
734system.cpu0.itb.inst_accesses 4299572 # ITB inst accesses
735system.cpu0.itb.hits 4294311 # DTB hits
736system.cpu0.itb.misses 5261 # DTB misses
737system.cpu0.itb.accesses 4299572 # DTB accesses
738system.cpu0.numCycles 69013505 # number of cpu cycles simulated
739system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
740system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
741system.cpu0.BPredUnit.lookups 6123831 # Number of BP lookups
742system.cpu0.BPredUnit.condPredicted 4675790 # Number of conditional branches predicted
743system.cpu0.BPredUnit.condIncorrect 298271 # Number of conditional branches incorrect
744system.cpu0.BPredUnit.BTBLookups 3798227 # Number of BTB lookups
745system.cpu0.BPredUnit.BTBHits 2989296 # Number of BTB hits
746system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
747system.cpu0.BPredUnit.usedRAS 685728 # Number of times the RAS was used to get a target.
748system.cpu0.BPredUnit.RASInCorrect 28375 # Number of incorrect RAS predictions.
749system.cpu0.fetch.icacheStallCycles 11998527 # Number of cycles fetch is stalled on an Icache miss
750system.cpu0.fetch.Insts 32710943 # Number of instructions fetch has processed
751system.cpu0.fetch.Branches 6123831 # Number of branches that fetch encountered
752system.cpu0.fetch.predictedBranches 3675024 # Number of branches that fetch has predicted taken
753system.cpu0.fetch.Cycles 7667644 # Number of cycles fetch has run and was not squashing or blocked
754system.cpu0.fetch.SquashCycles 1480146 # Number of cycles fetch has spent squashing
755system.cpu0.fetch.TlbCycles 66638 # Number of cycles fetch has spent waiting for tlb
756system.cpu0.fetch.BlockedCycles 21758305 # Number of cycles fetch has spent blocked
757system.cpu0.fetch.MiscStallCycles 5862 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
758system.cpu0.fetch.PendingTrapStallCycles 53793 # Number of stall cycles due to pending traps
759system.cpu0.fetch.PendingQuiesceStallCycles 90248 # Number of stall cycles due to pending quiesce instructions
760system.cpu0.fetch.IcacheWaitRetryStallCycles 221 # Number of stall cycles due to full MSHR
761system.cpu0.fetch.CacheLines 4292744 # Number of cache lines fetched
762system.cpu0.fetch.IcacheSquashes 155269 # Number of outstanding Icache misses that were squashed
763system.cpu0.fetch.ItlbSquashes 2401 # Number of outstanding ITLB misses that were squashed
764system.cpu0.fetch.rateDist::samples 42704543 # Number of instructions fetched each cycle (Total)
765system.cpu0.fetch.rateDist::mean 0.988603 # Number of instructions fetched each cycle (Total)
766system.cpu0.fetch.rateDist::stdev 2.369673 # Number of instructions fetched each cycle (Total)
767system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
768system.cpu0.fetch.rateDist::0 35044149 82.06% 82.06% # Number of instructions fetched each cycle (Total)
769system.cpu0.fetch.rateDist::1 606065 1.42% 83.48% # Number of instructions fetched each cycle (Total)
770system.cpu0.fetch.rateDist::2 793528 1.86% 85.34% # Number of instructions fetched each cycle (Total)
771system.cpu0.fetch.rateDist::3 689319 1.61% 86.95% # Number of instructions fetched each cycle (Total)
772system.cpu0.fetch.rateDist::4 781424 1.83% 88.78% # Number of instructions fetched each cycle (Total)
773system.cpu0.fetch.rateDist::5 567584 1.33% 90.11% # Number of instructions fetched each cycle (Total)
774system.cpu0.fetch.rateDist::6 711320 1.67% 91.78% # Number of instructions fetched each cycle (Total)
775system.cpu0.fetch.rateDist::7 364019 0.85% 92.63% # Number of instructions fetched each cycle (Total)
776system.cpu0.fetch.rateDist::8 3147135 7.37% 100.00% # Number of instructions fetched each cycle (Total)
777system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
778system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
779system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
780system.cpu0.fetch.rateDist::total 42704543 # Number of instructions fetched each cycle (Total)
781system.cpu0.fetch.branchRate 0.088734 # Number of branch fetches per cycle
782system.cpu0.fetch.rate 0.473979 # Number of inst fetches per cycle
783system.cpu0.decode.IdleCycles 12497333 # Number of cycles decode is idle
784system.cpu0.decode.BlockedCycles 21726841 # Number of cycles decode is blocked
785system.cpu0.decode.RunCycles 6896095 # Number of cycles decode is running
786system.cpu0.decode.UnblockCycles 584636 # Number of cycles decode is unblocking
787system.cpu0.decode.SquashCycles 999638 # Number of cycles decode is squashing
788system.cpu0.decode.BranchResolved 951812 # Number of times decode resolved a branch
789system.cpu0.decode.BranchMispred 64726 # Number of times decode detected a branch misprediction
790system.cpu0.decode.DecodedInsts 40836330 # Number of instructions handled by decode
791system.cpu0.decode.SquashedInsts 213865 # Number of squashed instructions handled by decode
792system.cpu0.rename.SquashCycles 999638 # Number of cycles rename is squashing
793system.cpu0.rename.IdleCycles 13071648 # Number of cycles rename is idle
794system.cpu0.rename.BlockCycles 5812993 # Number of cycles rename is blocking
795system.cpu0.rename.serializeStallCycles 13759259 # count of cycles rename stalled for serializing inst
796system.cpu0.rename.RunCycles 6855374 # Number of cycles rename is running
797system.cpu0.rename.UnblockCycles 2205631 # Number of cycles rename is unblocking
798system.cpu0.rename.RenamedInsts 39711904 # Number of instructions processed by rename
799system.cpu0.rename.ROBFullEvents 2173 # Number of times rename has blocked due to ROB full
800system.cpu0.rename.IQFullEvents 427558 # Number of times rename has blocked due to IQ full
801system.cpu0.rename.LSQFullEvents 1242268 # Number of times rename has blocked due to LSQ full
802system.cpu0.rename.FullRegisterEvents 68 # Number of times there has been no free registers
803system.cpu0.rename.RenamedOperands 40116309 # Number of destination operands rename has renamed
804system.cpu0.rename.RenameLookups 179435830 # Number of register rename lookups that rename has made
805system.cpu0.rename.int_rename_lookups 179401258 # Number of integer rename lookups
806system.cpu0.rename.fp_rename_lookups 34572 # Number of floating rename lookups
807system.cpu0.rename.CommittedMaps 31681024 # Number of HB maps that are committed
808system.cpu0.rename.UndoneMaps 8435284 # Number of HB maps that are undone due to squashing
809system.cpu0.rename.serializingInsts 457771 # count of serializing insts renamed
810system.cpu0.rename.tempSerializingInsts 414521 # count of temporary serializing insts renamed
811system.cpu0.rename.skidInsts 5443309 # count of insts added to the skid buffer
812system.cpu0.memDep0.insertedLoads 7819363 # Number of loads inserted to the mem dependence unit.
813system.cpu0.memDep0.insertedStores 5820332 # Number of stores inserted to the mem dependence unit.
814system.cpu0.memDep0.conflictingLoads 1146243 # Number of conflicting loads.
815system.cpu0.memDep0.conflictingStores 1242216 # Number of conflicting stores.
816system.cpu0.iq.iqInstsAdded 37575405 # Number of instructions added to the IQ (excludes non-spec)
817system.cpu0.iq.iqNonSpecInstsAdded 946067 # Number of non-speculative instructions added to the IQ
818system.cpu0.iq.iqInstsIssued 37951575 # Number of instructions issued
819system.cpu0.iq.iqSquashedInstsIssued 82274 # Number of squashed instructions issued
820system.cpu0.iq.iqSquashedInstsExamined 6366228 # Number of squashed instructions iterated over during squash; mainly for profiling
821system.cpu0.iq.iqSquashedOperandsExamined 13456450 # Number of squashed operands that are examined and possibly removed from graph
822system.cpu0.iq.iqSquashedNonSpecRemoved 257591 # Number of squashed non-spec instructions that were removed
823system.cpu0.iq.issued_per_cycle::samples 42704543 # Number of insts issued each cycle
824system.cpu0.iq.issued_per_cycle::mean 0.888701 # Number of insts issued each cycle
825system.cpu0.iq.issued_per_cycle::stdev 1.500077 # Number of insts issued each cycle
826system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
827system.cpu0.iq.issued_per_cycle::0 27159670 63.60% 63.60% # Number of insts issued each cycle
828system.cpu0.iq.issued_per_cycle::1 6000291 14.05% 77.65% # Number of insts issued each cycle
829system.cpu0.iq.issued_per_cycle::2 3232720 7.57% 85.22% # Number of insts issued each cycle
830system.cpu0.iq.issued_per_cycle::3 2489147 5.83% 91.05% # Number of insts issued each cycle
831system.cpu0.iq.issued_per_cycle::4 2132528 4.99% 96.04% # Number of insts issued each cycle
832system.cpu0.iq.issued_per_cycle::5 950123 2.22% 98.27% # Number of insts issued each cycle
833system.cpu0.iq.issued_per_cycle::6 497063 1.16% 99.43% # Number of insts issued each cycle
834system.cpu0.iq.issued_per_cycle::7 188710 0.44% 99.87% # Number of insts issued each cycle
835system.cpu0.iq.issued_per_cycle::8 54291 0.13% 100.00% # Number of insts issued each cycle
836system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
837system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
838system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
839system.cpu0.iq.issued_per_cycle::total 42704543 # Number of insts issued each cycle
840system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
841system.cpu0.iq.fu_full::IntAlu 24659 2.31% 2.31% # attempts to use FU when none available
842system.cpu0.iq.fu_full::IntMult 467 0.04% 2.35% # attempts to use FU when none available
843system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.35% # attempts to use FU when none available
844system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.35% # attempts to use FU when none available
845system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.35% # attempts to use FU when none available
846system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.35% # attempts to use FU when none available
847system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.35% # attempts to use FU when none available
848system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.35% # attempts to use FU when none available
849system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.35% # attempts to use FU when none available
850system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.35% # attempts to use FU when none available
851system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.35% # attempts to use FU when none available
852system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.35% # attempts to use FU when none available
853system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.35% # attempts to use FU when none available
854system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.35% # attempts to use FU when none available
855system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.35% # attempts to use FU when none available
856system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.35% # attempts to use FU when none available
857system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.35% # attempts to use FU when none available
858system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.35% # attempts to use FU when none available
859system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.35% # attempts to use FU when none available
860system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.35% # attempts to use FU when none available
861system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.35% # attempts to use FU when none available
862system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.35% # attempts to use FU when none available
863system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.35% # attempts to use FU when none available
864system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.35% # attempts to use FU when none available
865system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.35% # attempts to use FU when none available
866system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.35% # attempts to use FU when none available
867system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.35% # attempts to use FU when none available
868system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.35% # attempts to use FU when none available
869system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.35% # attempts to use FU when none available
870system.cpu0.iq.fu_full::MemRead 838061 78.41% 80.76% # attempts to use FU when none available
871system.cpu0.iq.fu_full::MemWrite 205631 19.24% 100.00% # attempts to use FU when none available
872system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
873system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
874system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued
875system.cpu0.iq.FU_type_0::IntAlu 22793341 60.06% 60.20% # Type of FU issued
876system.cpu0.iq.FU_type_0::IntMult 48224 0.13% 60.32% # Type of FU issued
877system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued
878system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued
879system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued
880system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued
881system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued
882system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued
883system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued
884system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued
885system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued
886system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued
887system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued
888system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued
889system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.32% # Type of FU issued
890system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued
891system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued
892system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.32% # Type of FU issued
893system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 60.32% # Type of FU issued
894system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued
895system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued
896system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued
897system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued
898system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued
899system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued
900system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.33% # Type of FU issued
901system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.33% # Type of FU issued
902system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 60.33% # Type of FU issued
903system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.33% # Type of FU issued
904system.cpu0.iq.FU_type_0::MemRead 9480747 24.98% 85.31% # Type of FU issued
905system.cpu0.iq.FU_type_0::MemWrite 5576214 14.69% 100.00% # Type of FU issued
906system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
907system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
908system.cpu0.iq.FU_type_0::total 37951575 # Type of FU issued
909system.cpu0.iq.rate 0.549915 # Inst issue rate
910system.cpu0.iq.fu_busy_cnt 1068818 # FU busy when requested
911system.cpu0.iq.fu_busy_rate 0.028163 # FU busy rate (busy events/executed inst)
912system.cpu0.iq.int_inst_queue_reads 119791525 # Number of integer instruction queue reads
913system.cpu0.iq.int_inst_queue_writes 44895833 # Number of integer instruction queue writes
914system.cpu0.iq.int_inst_queue_wakeup_accesses 35071497 # Number of integer instruction queue wakeup accesses
915system.cpu0.iq.fp_inst_queue_reads 8304 # Number of floating instruction queue reads
916system.cpu0.iq.fp_inst_queue_writes 4710 # Number of floating instruction queue writes
917system.cpu0.iq.fp_inst_queue_wakeup_accesses 3884 # Number of floating instruction queue wakeup accesses
918system.cpu0.iq.int_alu_accesses 38963714 # Number of integer alu accesses
919system.cpu0.iq.fp_alu_accesses 4335 # Number of floating point alu accesses
920system.cpu0.iew.lsq.thread0.forwLoads 318123 # Number of loads that had data forwarded from stores
921system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
922system.cpu0.iew.lsq.thread0.squashedLoads 1396327 # Number of loads squashed
923system.cpu0.iew.lsq.thread0.ignoredResponses 2506 # Number of memory responses ignored because the instruction is squashed
924system.cpu0.iew.lsq.thread0.memOrderViolation 13403 # Number of memory ordering violations
925system.cpu0.iew.lsq.thread0.squashedStores 544501 # Number of stores squashed
926system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
927system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
928system.cpu0.iew.lsq.thread0.rescheduledLoads 2149359 # Number of loads that were rescheduled
929system.cpu0.iew.lsq.thread0.cacheBlocked 5385 # Number of times an access to memory failed due to the cache being blocked
930system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
931system.cpu0.iew.iewSquashCycles 999638 # Number of cycles IEW is squashing
932system.cpu0.iew.iewBlockCycles 4184428 # Number of cycles IEW is blocking
933system.cpu0.iew.iewUnblockCycles 103741 # Number of cycles IEW is unblocking
934system.cpu0.iew.iewDispatchedInsts 38639126 # Number of instructions dispatched to IQ
935system.cpu0.iew.iewDispSquashedInsts 85944 # Number of squashed instructions skipped by dispatch
936system.cpu0.iew.iewDispLoadInsts 7819363 # Number of dispatched load instructions
937system.cpu0.iew.iewDispStoreInsts 5820332 # Number of dispatched store instructions
938system.cpu0.iew.iewDispNonSpecInsts 614711 # Number of dispatched non-speculative instructions
939system.cpu0.iew.iewIQFullEvents 41414 # Number of times the IQ has become full, causing a stall
940system.cpu0.iew.iewLSQFullEvents 3290 # Number of times the LSQ has become full, causing a stall
941system.cpu0.iew.memOrderViolationEvents 13403 # Number of memory order violations
942system.cpu0.iew.predictedTakenIncorrect 151339 # Number of branches that were predicted taken incorrectly
943system.cpu0.iew.predictedNotTakenIncorrect 119425 # Number of branches that were predicted not taken incorrectly
944system.cpu0.iew.branchMispredicts 270764 # Number of branch mispredicts detected at execute
945system.cpu0.iew.iewExecutedInsts 37563861 # Number of executed instructions
946system.cpu0.iew.iewExecLoadInsts 9331167 # Number of load instructions executed
947system.cpu0.iew.iewExecSquashedInsts 387714 # Number of squashed instructions skipped in execute
948system.cpu0.iew.exec_swp 0 # number of swp insts executed
949system.cpu0.iew.exec_nop 117654 # number of nop insts executed
950system.cpu0.iew.exec_refs 14857557 # number of memory reference insts executed
951system.cpu0.iew.exec_branches 4958494 # Number of branches executed
952system.cpu0.iew.exec_stores 5526390 # Number of stores executed
953system.cpu0.iew.exec_rate 0.544297 # Inst execution rate
954system.cpu0.iew.wb_sent 37365472 # cumulative count of insts sent to commit
955system.cpu0.iew.wb_count 35075381 # cumulative count of insts written-back
956system.cpu0.iew.wb_producers 18655901 # num instructions producing a value
957system.cpu0.iew.wb_consumers 35819655 # num instructions consuming a value
958system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
959system.cpu0.iew.wb_rate 0.508239 # insts written-back per cycle
960system.cpu0.iew.wb_fanout 0.520829 # average fanout of values written-back
961system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
962system.cpu0.commit.commitSquashedInsts 6205381 # The number of squashed insts skipped by commit
963system.cpu0.commit.commitNonSpecStalls 688476 # The number of times commit has been forced to stall to communicate backwards
964system.cpu0.commit.branchMispredicts 234604 # The number of times a branch was mispredicted
965system.cpu0.commit.committed_per_cycle::samples 41741265 # Number of insts commited each cycle
966system.cpu0.commit.committed_per_cycle::mean 0.766601 # Number of insts commited each cycle
967system.cpu0.commit.committed_per_cycle::stdev 1.727877 # Number of insts commited each cycle
968system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
969system.cpu0.commit.committed_per_cycle::0 29720457 71.20% 71.20% # Number of insts commited each cycle
970system.cpu0.commit.committed_per_cycle::1 5963123 14.29% 85.49% # Number of insts commited each cycle
971system.cpu0.commit.committed_per_cycle::2 1948324 4.67% 90.16% # Number of insts commited each cycle
972system.cpu0.commit.committed_per_cycle::3 1002440 2.40% 92.56% # Number of insts commited each cycle
973system.cpu0.commit.committed_per_cycle::4 789371 1.89% 94.45% # Number of insts commited each cycle
974system.cpu0.commit.committed_per_cycle::5 520489 1.25% 95.69% # Number of insts commited each cycle
975system.cpu0.commit.committed_per_cycle::6 393953 0.94% 96.64% # Number of insts commited each cycle
976system.cpu0.commit.committed_per_cycle::7 216687 0.52% 97.16% # Number of insts commited each cycle
977system.cpu0.commit.committed_per_cycle::8 1186421 2.84% 100.00% # Number of insts commited each cycle
978system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
979system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
980system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
981system.cpu0.commit.committed_per_cycle::total 41741265 # Number of insts commited each cycle
982system.cpu0.commit.committedInsts 24264310 # Number of instructions committed
983system.cpu0.commit.committedOps 31998915 # Number of ops (including micro ops) committed
984system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
985system.cpu0.commit.refs 11698867 # Number of memory references committed
986system.cpu0.commit.loads 6423036 # Number of loads committed
987system.cpu0.commit.membars 234373 # Number of memory barriers committed
988system.cpu0.commit.branches 4346960 # Number of branches committed
989system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
990system.cpu0.commit.int_insts 28266871 # Number of committed integer instructions.
991system.cpu0.commit.function_calls 499893 # Number of function calls committed.
992system.cpu0.commit.bw_lim_events 1186421 # number cycles where commit BW limit reached
993system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
994system.cpu0.rob.rob_reads 77875275 # The number of ROB reads
995system.cpu0.rob.rob_writes 77410136 # The number of ROB writes
996system.cpu0.timesIdled 364830 # Number of times that the entire CPU went into an idle state and unscheduled itself
997system.cpu0.idleCycles 26308962 # Total number of cycles that the CPU has spent unscheduled due to idling
998system.cpu0.quiesceCycles 5117234895 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
999system.cpu0.committedInsts 24183568 # Number of Instructions Simulated
1000system.cpu0.committedOps 31918173 # Number of Ops (including micro ops) Simulated
1001system.cpu0.committedInsts_total 24183568 # Number of Instructions Simulated
1002system.cpu0.cpi 2.853735 # CPI: Cycles Per Instruction
1003system.cpu0.cpi_total 2.853735 # CPI: Total CPI of All Threads
1004system.cpu0.ipc 0.350418 # IPC: Instructions Per Cycle
1005system.cpu0.ipc_total 0.350418 # IPC: Total IPC of All Threads
1006system.cpu0.int_regfile_reads 175323075 # number of integer regfile reads
1007system.cpu0.int_regfile_writes 34853003 # number of integer regfile writes
1008system.cpu0.fp_regfile_reads 3246 # number of floating regfile reads
1009system.cpu0.fp_regfile_writes 906 # number of floating regfile writes
1010system.cpu0.misc_regfile_reads 46878729 # number of misc regfile reads
1011system.cpu0.misc_regfile_writes 527371 # number of misc regfile writes
1012system.cpu0.icache.replacements 399233 # number of replacements
1013system.cpu0.icache.tagsinuse 511.592262 # Cycle average of tags in use
1014system.cpu0.icache.total_refs 3861943 # Total number of references to valid blocks.
1015system.cpu0.icache.sampled_refs 399745 # Sample count of references to valid blocks.
1016system.cpu0.icache.avg_refs 9.661016 # Average number of references to valid blocks.
1017system.cpu0.icache.warmup_cycle 6802423000 # Cycle when the warmup percentage was hit.
1018system.cpu0.icache.occ_blocks::cpu0.inst 511.592262 # Average occupied blocks per requestor
1019system.cpu0.icache.occ_percent::cpu0.inst 0.999204 # Average percentage of cache occupancy
1020system.cpu0.icache.occ_percent::total 0.999204 # Average percentage of cache occupancy
1021system.cpu0.icache.ReadReq_hits::cpu0.inst 3861943 # number of ReadReq hits
1022system.cpu0.icache.ReadReq_hits::total 3861943 # number of ReadReq hits
1023system.cpu0.icache.demand_hits::cpu0.inst 3861943 # number of demand (read+write) hits
1024system.cpu0.icache.demand_hits::total 3861943 # number of demand (read+write) hits
1025system.cpu0.icache.overall_hits::cpu0.inst 3861943 # number of overall hits
1026system.cpu0.icache.overall_hits::total 3861943 # number of overall hits
1027system.cpu0.icache.ReadReq_misses::cpu0.inst 430668 # number of ReadReq misses
1028system.cpu0.icache.ReadReq_misses::total 430668 # number of ReadReq misses
1029system.cpu0.icache.demand_misses::cpu0.inst 430668 # number of demand (read+write) misses
1030system.cpu0.icache.demand_misses::total 430668 # number of demand (read+write) misses
1031system.cpu0.icache.overall_misses::cpu0.inst 430668 # number of overall misses
1032system.cpu0.icache.overall_misses::total 430668 # number of overall misses
1033system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5857521993 # number of ReadReq miss cycles
1034system.cpu0.icache.ReadReq_miss_latency::total 5857521993 # number of ReadReq miss cycles
1035system.cpu0.icache.demand_miss_latency::cpu0.inst 5857521993 # number of demand (read+write) miss cycles
1036system.cpu0.icache.demand_miss_latency::total 5857521993 # number of demand (read+write) miss cycles
1037system.cpu0.icache.overall_miss_latency::cpu0.inst 5857521993 # number of overall miss cycles
1038system.cpu0.icache.overall_miss_latency::total 5857521993 # number of overall miss cycles
1039system.cpu0.icache.ReadReq_accesses::cpu0.inst 4292611 # number of ReadReq accesses(hits+misses)
1040system.cpu0.icache.ReadReq_accesses::total 4292611 # number of ReadReq accesses(hits+misses)
1041system.cpu0.icache.demand_accesses::cpu0.inst 4292611 # number of demand (read+write) accesses
1042system.cpu0.icache.demand_accesses::total 4292611 # number of demand (read+write) accesses
1043system.cpu0.icache.overall_accesses::cpu0.inst 4292611 # number of overall (read+write) accesses
1044system.cpu0.icache.overall_accesses::total 4292611 # number of overall (read+write) accesses
1045system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100328 # miss rate for ReadReq accesses
1046system.cpu0.icache.ReadReq_miss_rate::total 0.100328 # miss rate for ReadReq accesses
1047system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100328 # miss rate for demand accesses
1048system.cpu0.icache.demand_miss_rate::total 0.100328 # miss rate for demand accesses
1049system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100328 # miss rate for overall accesses
1050system.cpu0.icache.overall_miss_rate::total 0.100328 # miss rate for overall accesses
1051system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13601.015151 # average ReadReq miss latency
1052system.cpu0.icache.ReadReq_avg_miss_latency::total 13601.015151 # average ReadReq miss latency
1053system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13601.015151 # average overall miss latency
1054system.cpu0.icache.demand_avg_miss_latency::total 13601.015151 # average overall miss latency
1055system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13601.015151 # average overall miss latency
1056system.cpu0.icache.overall_avg_miss_latency::total 13601.015151 # average overall miss latency
1057system.cpu0.icache.blocked_cycles::no_mshrs 2687 # number of cycles access was blocked
1058system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1059system.cpu0.icache.blocked::no_mshrs 157 # number of cycles access was blocked
1060system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
1061system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.114650 # average number of cycles each access was blocked
1062system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1063system.cpu0.icache.fast_writes 0 # number of fast writes performed
1064system.cpu0.icache.cache_copies 0 # number of cache copies performed
1065system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30901 # number of ReadReq MSHR hits
1066system.cpu0.icache.ReadReq_mshr_hits::total 30901 # number of ReadReq MSHR hits
1067system.cpu0.icache.demand_mshr_hits::cpu0.inst 30901 # number of demand (read+write) MSHR hits
1068system.cpu0.icache.demand_mshr_hits::total 30901 # number of demand (read+write) MSHR hits
1069system.cpu0.icache.overall_mshr_hits::cpu0.inst 30901 # number of overall MSHR hits
1070system.cpu0.icache.overall_mshr_hits::total 30901 # number of overall MSHR hits
1071system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 399767 # number of ReadReq MSHR misses
1072system.cpu0.icache.ReadReq_mshr_misses::total 399767 # number of ReadReq MSHR misses
1073system.cpu0.icache.demand_mshr_misses::cpu0.inst 399767 # number of demand (read+write) MSHR misses
1074system.cpu0.icache.demand_mshr_misses::total 399767 # number of demand (read+write) MSHR misses
1075system.cpu0.icache.overall_mshr_misses::cpu0.inst 399767 # number of overall MSHR misses
1076system.cpu0.icache.overall_mshr_misses::total 399767 # number of overall MSHR misses
1077system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4790784994 # number of ReadReq MSHR miss cycles
1078system.cpu0.icache.ReadReq_mshr_miss_latency::total 4790784994 # number of ReadReq MSHR miss cycles
1079system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4790784994 # number of demand (read+write) MSHR miss cycles
1080system.cpu0.icache.demand_mshr_miss_latency::total 4790784994 # number of demand (read+write) MSHR miss cycles
1081system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4790784994 # number of overall MSHR miss cycles
1082system.cpu0.icache.overall_mshr_miss_latency::total 4790784994 # number of overall MSHR miss cycles
1083system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7139500 # number of ReadReq MSHR uncacheable cycles
1084system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7139500 # number of ReadReq MSHR uncacheable cycles
1085system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7139500 # number of overall MSHR uncacheable cycles
1086system.cpu0.icache.overall_mshr_uncacheable_latency::total 7139500 # number of overall MSHR uncacheable cycles
1087system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for ReadReq accesses
1088system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093129 # mshr miss rate for ReadReq accesses
1089system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for demand accesses
1090system.cpu0.icache.demand_mshr_miss_rate::total 0.093129 # mshr miss rate for demand accesses
1091system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for overall accesses
1092system.cpu0.icache.overall_mshr_miss_rate::total 0.093129 # mshr miss rate for overall accesses
1093system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average ReadReq mshr miss latency
1094system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11983.943132 # average ReadReq mshr miss latency
1095system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average overall mshr miss latency
1096system.cpu0.icache.demand_avg_mshr_miss_latency::total 11983.943132 # average overall mshr miss latency
1097system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average overall mshr miss latency
1098system.cpu0.icache.overall_avg_mshr_miss_latency::total 11983.943132 # average overall mshr miss latency
1099system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1100system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1101system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1102system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1103system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1104system.cpu0.dcache.replacements 274937 # number of replacements
1105system.cpu0.dcache.tagsinuse 481.181813 # Cycle average of tags in use
1106system.cpu0.dcache.total_refs 9516256 # Total number of references to valid blocks.
1107system.cpu0.dcache.sampled_refs 275449 # Sample count of references to valid blocks.
1108system.cpu0.dcache.avg_refs 34.548160 # Average number of references to valid blocks.
1109system.cpu0.dcache.warmup_cycle 36452000 # Cycle when the warmup percentage was hit.
1110system.cpu0.dcache.occ_blocks::cpu0.data 481.181813 # Average occupied blocks per requestor
1111system.cpu0.dcache.occ_percent::cpu0.data 0.939808 # Average percentage of cache occupancy
1112system.cpu0.dcache.occ_percent::total 0.939808 # Average percentage of cache occupancy
1113system.cpu0.dcache.ReadReq_hits::cpu0.data 5887183 # number of ReadReq hits
1114system.cpu0.dcache.ReadReq_hits::total 5887183 # number of ReadReq hits
1115system.cpu0.dcache.WriteReq_hits::cpu0.data 3238358 # number of WriteReq hits
1116system.cpu0.dcache.WriteReq_hits::total 3238358 # number of WriteReq hits
1117system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 173666 # number of LoadLockedReq hits
1118system.cpu0.dcache.LoadLockedReq_hits::total 173666 # number of LoadLockedReq hits
1119system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171542 # number of StoreCondReq hits
1120system.cpu0.dcache.StoreCondReq_hits::total 171542 # number of StoreCondReq hits
1121system.cpu0.dcache.demand_hits::cpu0.data 9125541 # number of demand (read+write) hits
1122system.cpu0.dcache.demand_hits::total 9125541 # number of demand (read+write) hits
1123system.cpu0.dcache.overall_hits::cpu0.data 9125541 # number of overall hits
1124system.cpu0.dcache.overall_hits::total 9125541 # number of overall hits
1125system.cpu0.dcache.ReadReq_misses::cpu0.data 390766 # number of ReadReq misses
1126system.cpu0.dcache.ReadReq_misses::total 390766 # number of ReadReq misses
1127system.cpu0.dcache.WriteReq_misses::cpu0.data 1582021 # number of WriteReq misses
1128system.cpu0.dcache.WriteReq_misses::total 1582021 # number of WriteReq misses
1129system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8872 # number of LoadLockedReq misses
1130system.cpu0.dcache.LoadLockedReq_misses::total 8872 # number of LoadLockedReq misses
1131system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7743 # number of StoreCondReq misses
1132system.cpu0.dcache.StoreCondReq_misses::total 7743 # number of StoreCondReq misses
1133system.cpu0.dcache.demand_misses::cpu0.data 1972787 # number of demand (read+write) misses
1134system.cpu0.dcache.demand_misses::total 1972787 # number of demand (read+write) misses
1135system.cpu0.dcache.overall_misses::cpu0.data 1972787 # number of overall misses
1136system.cpu0.dcache.overall_misses::total 1972787 # number of overall misses
1137system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5377265000 # number of ReadReq miss cycles
1138system.cpu0.dcache.ReadReq_miss_latency::total 5377265000 # number of ReadReq miss cycles
1139system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60881411847 # number of WriteReq miss cycles
1140system.cpu0.dcache.WriteReq_miss_latency::total 60881411847 # number of WriteReq miss cycles
1141system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88222500 # number of LoadLockedReq miss cycles
1142system.cpu0.dcache.LoadLockedReq_miss_latency::total 88222500 # number of LoadLockedReq miss cycles
1143system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50475500 # number of StoreCondReq miss cycles
1144system.cpu0.dcache.StoreCondReq_miss_latency::total 50475500 # number of StoreCondReq miss cycles
1145system.cpu0.dcache.demand_miss_latency::cpu0.data 66258676847 # number of demand (read+write) miss cycles
1146system.cpu0.dcache.demand_miss_latency::total 66258676847 # number of demand (read+write) miss cycles
1147system.cpu0.dcache.overall_miss_latency::cpu0.data 66258676847 # number of overall miss cycles
1148system.cpu0.dcache.overall_miss_latency::total 66258676847 # number of overall miss cycles
1149system.cpu0.dcache.ReadReq_accesses::cpu0.data 6277949 # number of ReadReq accesses(hits+misses)
1150system.cpu0.dcache.ReadReq_accesses::total 6277949 # number of ReadReq accesses(hits+misses)
1151system.cpu0.dcache.WriteReq_accesses::cpu0.data 4820379 # number of WriteReq accesses(hits+misses)
1152system.cpu0.dcache.WriteReq_accesses::total 4820379 # number of WriteReq accesses(hits+misses)
1153system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182538 # number of LoadLockedReq accesses(hits+misses)
1154system.cpu0.dcache.LoadLockedReq_accesses::total 182538 # number of LoadLockedReq accesses(hits+misses)
1155system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179285 # number of StoreCondReq accesses(hits+misses)
1156system.cpu0.dcache.StoreCondReq_accesses::total 179285 # number of StoreCondReq accesses(hits+misses)
1157system.cpu0.dcache.demand_accesses::cpu0.data 11098328 # number of demand (read+write) accesses
1158system.cpu0.dcache.demand_accesses::total 11098328 # number of demand (read+write) accesses
1159system.cpu0.dcache.overall_accesses::cpu0.data 11098328 # number of overall (read+write) accesses
1160system.cpu0.dcache.overall_accesses::total 11098328 # number of overall (read+write) accesses
1161system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062244 # miss rate for ReadReq accesses
1162system.cpu0.dcache.ReadReq_miss_rate::total 0.062244 # miss rate for ReadReq accesses
1163system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.328194 # miss rate for WriteReq accesses
1164system.cpu0.dcache.WriteReq_miss_rate::total 0.328194 # miss rate for WriteReq accesses
1165system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048604 # miss rate for LoadLockedReq accesses
1166system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048604 # miss rate for LoadLockedReq accesses
1167system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043188 # miss rate for StoreCondReq accesses
1168system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043188 # miss rate for StoreCondReq accesses
1169system.cpu0.dcache.demand_miss_rate::cpu0.data 0.177755 # miss rate for demand accesses
1170system.cpu0.dcache.demand_miss_rate::total 0.177755 # miss rate for demand accesses
1171system.cpu0.dcache.overall_miss_rate::cpu0.data 0.177755 # miss rate for overall accesses
1172system.cpu0.dcache.overall_miss_rate::total 0.177755 # miss rate for overall accesses
1173system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13760.831290 # average ReadReq miss latency
1174system.cpu0.dcache.ReadReq_avg_miss_latency::total 13760.831290 # average ReadReq miss latency
1175system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38483.314600 # average WriteReq miss latency
1176system.cpu0.dcache.WriteReq_avg_miss_latency::total 38483.314600 # average WriteReq miss latency
1177system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9943.924707 # average LoadLockedReq miss latency
1178system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9943.924707 # average LoadLockedReq miss latency
1179system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6518.855741 # average StoreCondReq miss latency
1180system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6518.855741 # average StoreCondReq miss latency
1181system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33586.330834 # average overall miss latency
1182system.cpu0.dcache.demand_avg_miss_latency::total 33586.330834 # average overall miss latency
1183system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33586.330834 # average overall miss latency
1184system.cpu0.dcache.overall_avg_miss_latency::total 33586.330834 # average overall miss latency
1185system.cpu0.dcache.blocked_cycles::no_mshrs 8283 # number of cycles access was blocked
1186system.cpu0.dcache.blocked_cycles::no_targets 3369 # number of cycles access was blocked
1187system.cpu0.dcache.blocked::no_mshrs 596 # number of cycles access was blocked
1188system.cpu0.dcache.blocked::no_targets 82 # number of cycles access was blocked
1189system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.897651 # average number of cycles each access was blocked
1190system.cpu0.dcache.avg_blocked_cycles::no_targets 41.085366 # average number of cycles each access was blocked
1191system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1192system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1193system.cpu0.dcache.writebacks::writebacks 255577 # number of writebacks
1194system.cpu0.dcache.writebacks::total 255577 # number of writebacks
1195system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202032 # number of ReadReq MSHR hits
1196system.cpu0.dcache.ReadReq_mshr_hits::total 202032 # number of ReadReq MSHR hits
1197system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1450989 # number of WriteReq MSHR hits
1198system.cpu0.dcache.WriteReq_mshr_hits::total 1450989 # number of WriteReq MSHR hits
1199system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 498 # number of LoadLockedReq MSHR hits
1200system.cpu0.dcache.LoadLockedReq_mshr_hits::total 498 # number of LoadLockedReq MSHR hits
1201system.cpu0.dcache.demand_mshr_hits::cpu0.data 1653021 # number of demand (read+write) MSHR hits
1202system.cpu0.dcache.demand_mshr_hits::total 1653021 # number of demand (read+write) MSHR hits
1203system.cpu0.dcache.overall_mshr_hits::cpu0.data 1653021 # number of overall MSHR hits
1204system.cpu0.dcache.overall_mshr_hits::total 1653021 # number of overall MSHR hits
1205system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188734 # number of ReadReq MSHR misses
1206system.cpu0.dcache.ReadReq_mshr_misses::total 188734 # number of ReadReq MSHR misses
1207system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131032 # number of WriteReq MSHR misses
1208system.cpu0.dcache.WriteReq_mshr_misses::total 131032 # number of WriteReq MSHR misses
1209system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8374 # number of LoadLockedReq MSHR misses
1210system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8374 # number of LoadLockedReq MSHR misses
1211system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7739 # number of StoreCondReq MSHR misses
1212system.cpu0.dcache.StoreCondReq_mshr_misses::total 7739 # number of StoreCondReq MSHR misses
1213system.cpu0.dcache.demand_mshr_misses::cpu0.data 319766 # number of demand (read+write) MSHR misses
1214system.cpu0.dcache.demand_mshr_misses::total 319766 # number of demand (read+write) MSHR misses
1215system.cpu0.dcache.overall_mshr_misses::cpu0.data 319766 # number of overall MSHR misses
1216system.cpu0.dcache.overall_mshr_misses::total 319766 # number of overall MSHR misses
1217system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2333622500 # number of ReadReq MSHR miss cycles
1218system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2333622500 # number of ReadReq MSHR miss cycles
1219system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4054127491 # number of WriteReq MSHR miss cycles
1220system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4054127491 # number of WriteReq MSHR miss cycles
1221system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66245000 # number of LoadLockedReq MSHR miss cycles
1222system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66245000 # number of LoadLockedReq MSHR miss cycles
1223system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34997500 # number of StoreCondReq MSHR miss cycles
1224system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34997500 # number of StoreCondReq MSHR miss cycles
1225system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6387749991 # number of demand (read+write) MSHR miss cycles
1226system.cpu0.dcache.demand_mshr_miss_latency::total 6387749991 # number of demand (read+write) MSHR miss cycles
1227system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6387749991 # number of overall MSHR miss cycles
1228system.cpu0.dcache.overall_mshr_miss_latency::total 6387749991 # number of overall MSHR miss cycles
1229system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13431600500 # number of ReadReq MSHR uncacheable cycles
1230system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13431600500 # number of ReadReq MSHR uncacheable cycles
1231system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199905877 # number of WriteReq MSHR uncacheable cycles
1232system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199905877 # number of WriteReq MSHR uncacheable cycles
1233system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14631506377 # number of overall MSHR uncacheable cycles
1234system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14631506377 # number of overall MSHR uncacheable cycles
1235system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030063 # mshr miss rate for ReadReq accesses
1236system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030063 # mshr miss rate for ReadReq accesses
1237system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027183 # mshr miss rate for WriteReq accesses
1238system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027183 # mshr miss rate for WriteReq accesses
1239system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045875 # mshr miss rate for LoadLockedReq accesses
1240system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045875 # mshr miss rate for LoadLockedReq accesses
1241system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043166 # mshr miss rate for StoreCondReq accesses
1242system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043166 # mshr miss rate for StoreCondReq accesses
1243system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028812 # mshr miss rate for demand accesses
1244system.cpu0.dcache.demand_mshr_miss_rate::total 0.028812 # mshr miss rate for demand accesses
1245system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028812 # mshr miss rate for overall accesses
1246system.cpu0.dcache.overall_mshr_miss_rate::total 0.028812 # mshr miss rate for overall accesses
1247system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12364.611040 # average ReadReq mshr miss latency
1248system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12364.611040 # average ReadReq mshr miss latency
1249system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30939.980241 # average WriteReq mshr miss latency
1250system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30939.980241 # average WriteReq mshr miss latency
1251system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7910.795319 # average LoadLockedReq mshr miss latency
1252system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7910.795319 # average LoadLockedReq mshr miss latency
1253system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4522.225094 # average StoreCondReq mshr miss latency
1254system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4522.225094 # average StoreCondReq mshr miss latency
1255system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19976.326411 # average overall mshr miss latency
1256system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19976.326411 # average overall mshr miss latency
1257system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19976.326411 # average overall mshr miss latency
1258system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19976.326411 # average overall mshr miss latency
1259system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1260system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1261system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1262system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1263system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1264system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1265system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1266system.cpu1.dtb.inst_hits 0 # ITB inst hits
1267system.cpu1.dtb.inst_misses 0 # ITB inst misses
1268system.cpu1.dtb.read_hits 43030291 # DTB read hits
1269system.cpu1.dtb.read_misses 42638 # DTB read misses
1270system.cpu1.dtb.write_hits 6991861 # DTB write hits
1271system.cpu1.dtb.write_misses 11867 # DTB write misses
1272system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
1273system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1274system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1275system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1276system.cpu1.dtb.flush_entries 2362 # Number of entries that have been flushed from TLB
1277system.cpu1.dtb.align_faults 2846 # Number of TLB faults due to alignment restrictions
1278system.cpu1.dtb.prefetch_faults 322 # Number of TLB faults due to prefetch
1279system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1280system.cpu1.dtb.perms_faults 690 # Number of TLB faults due to permissions restrictions
1281system.cpu1.dtb.read_accesses 43072929 # DTB read accesses
1282system.cpu1.dtb.write_accesses 7003728 # DTB write accesses
1283system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1284system.cpu1.dtb.hits 50022152 # DTB hits
1285system.cpu1.dtb.misses 54505 # DTB misses
1286system.cpu1.dtb.accesses 50076657 # DTB accesses
1287system.cpu1.itb.inst_hits 7786412 # ITB inst hits
1288system.cpu1.itb.inst_misses 5635 # ITB inst misses
1289system.cpu1.itb.read_hits 0 # DTB read hits
1290system.cpu1.itb.read_misses 0 # DTB read misses
1291system.cpu1.itb.write_hits 0 # DTB write hits
1292system.cpu1.itb.write_misses 0 # DTB write misses
1293system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
1294system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1295system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1296system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1297system.cpu1.itb.flush_entries 1587 # Number of entries that have been flushed from TLB
1298system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1299system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1300system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1301system.cpu1.itb.perms_faults 1520 # Number of TLB faults due to permissions restrictions
1302system.cpu1.itb.read_accesses 0 # DTB read accesses
1303system.cpu1.itb.write_accesses 0 # DTB write accesses
1304system.cpu1.itb.inst_accesses 7792047 # ITB inst accesses
1305system.cpu1.itb.hits 7786412 # DTB hits
1306system.cpu1.itb.misses 5635 # DTB misses
1307system.cpu1.itb.accesses 7792047 # DTB accesses
1308system.cpu1.numCycles 409024249 # number of cpu cycles simulated
1309system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1310system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1311system.cpu1.BPredUnit.lookups 9020667 # Number of BP lookups
1312system.cpu1.BPredUnit.condPredicted 7346445 # Number of conditional branches predicted
1313system.cpu1.BPredUnit.condIncorrect 421687 # Number of conditional branches incorrect
1314system.cpu1.BPredUnit.BTBLookups 5902094 # Number of BTB lookups
1315system.cpu1.BPredUnit.BTBHits 5066087 # Number of BTB hits
1316system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1317system.cpu1.BPredUnit.usedRAS 810235 # Number of times the RAS was used to get a target.
1318system.cpu1.BPredUnit.RASInCorrect 44717 # Number of incorrect RAS predictions.
1319system.cpu1.fetch.icacheStallCycles 19548819 # Number of cycles fetch is stalled on an Icache miss
1320system.cpu1.fetch.Insts 61628162 # Number of instructions fetch has processed
1321system.cpu1.fetch.Branches 9020667 # Number of branches that fetch encountered
1322system.cpu1.fetch.predictedBranches 5876322 # Number of branches that fetch has predicted taken
1323system.cpu1.fetch.Cycles 13445282 # Number of cycles fetch has run and was not squashing or blocked
1324system.cpu1.fetch.SquashCycles 3432135 # Number of cycles fetch has spent squashing
1325system.cpu1.fetch.TlbCycles 71958 # Number of cycles fetch has spent waiting for tlb
1326system.cpu1.fetch.BlockedCycles 78159434 # Number of cycles fetch has spent blocked
1327system.cpu1.fetch.MiscStallCycles 5756 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1328system.cpu1.fetch.PendingTrapStallCycles 48212 # Number of stall cycles due to pending traps
1329system.cpu1.fetch.PendingQuiesceStallCycles 140837 # Number of stall cycles due to pending quiesce instructions
1330system.cpu1.fetch.IcacheWaitRetryStallCycles 164 # Number of stall cycles due to full MSHR
1331system.cpu1.fetch.CacheLines 7784486 # Number of cache lines fetched
1332system.cpu1.fetch.IcacheSquashes 545452 # Number of outstanding Icache misses that were squashed
1333system.cpu1.fetch.ItlbSquashes 3066 # Number of outstanding ITLB misses that were squashed
1334system.cpu1.fetch.rateDist::samples 113770833 # Number of instructions fetched each cycle (Total)
1335system.cpu1.fetch.rateDist::mean 0.663645 # Number of instructions fetched each cycle (Total)
1336system.cpu1.fetch.rateDist::stdev 1.994153 # Number of instructions fetched each cycle (Total)
1337system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1338system.cpu1.fetch.rateDist::0 100333102 88.19% 88.19% # Number of instructions fetched each cycle (Total)
1339system.cpu1.fetch.rateDist::1 820750 0.72% 88.91% # Number of instructions fetched each cycle (Total)
1340system.cpu1.fetch.rateDist::2 967014 0.85% 89.76% # Number of instructions fetched each cycle (Total)
1341system.cpu1.fetch.rateDist::3 1722421 1.51% 91.27% # Number of instructions fetched each cycle (Total)
1342system.cpu1.fetch.rateDist::4 1420935 1.25% 92.52% # Number of instructions fetched each cycle (Total)
1343system.cpu1.fetch.rateDist::5 598048 0.53% 93.05% # Number of instructions fetched each cycle (Total)
1344system.cpu1.fetch.rateDist::6 1962596 1.73% 94.77% # Number of instructions fetched each cycle (Total)
1345system.cpu1.fetch.rateDist::7 435893 0.38% 95.16% # Number of instructions fetched each cycle (Total)
1346system.cpu1.fetch.rateDist::8 5510074 4.84% 100.00% # Number of instructions fetched each cycle (Total)
1347system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1348system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1349system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1350system.cpu1.fetch.rateDist::total 113770833 # Number of instructions fetched each cycle (Total)
1351system.cpu1.fetch.branchRate 0.022054 # Number of branch fetches per cycle
1352system.cpu1.fetch.rate 0.150671 # Number of inst fetches per cycle
1353system.cpu1.decode.IdleCycles 20932611 # Number of cycles decode is idle
1354system.cpu1.decode.BlockedCycles 77783544 # Number of cycles decode is blocked
1355system.cpu1.decode.RunCycles 12260401 # Number of cycles decode is running
1356system.cpu1.decode.UnblockCycles 543319 # Number of cycles decode is unblocking
1357system.cpu1.decode.SquashCycles 2250958 # Number of cycles decode is squashing
1358system.cpu1.decode.BranchResolved 1146967 # Number of times decode resolved a branch
1359system.cpu1.decode.BranchMispred 100968 # Number of times decode detected a branch misprediction
1360system.cpu1.decode.DecodedInsts 71503765 # Number of instructions handled by decode
1361system.cpu1.decode.SquashedInsts 336196 # Number of squashed instructions handled by decode
1362system.cpu1.rename.SquashCycles 2250958 # Number of cycles rename is squashing
1363system.cpu1.rename.IdleCycles 22152530 # Number of cycles rename is idle
1364system.cpu1.rename.BlockCycles 32126143 # Number of cycles rename is blocking
1365system.cpu1.rename.serializeStallCycles 41276446 # count of cycles rename stalled for serializing inst
1366system.cpu1.rename.RunCycles 11489660 # Number of cycles rename is running
1367system.cpu1.rename.UnblockCycles 4475096 # Number of cycles rename is unblocking
1368system.cpu1.rename.RenamedInsts 67542275 # Number of instructions processed by rename
1369system.cpu1.rename.ROBFullEvents 19496 # Number of times rename has blocked due to ROB full
1370system.cpu1.rename.IQFullEvents 697256 # Number of times rename has blocked due to IQ full
1371system.cpu1.rename.LSQFullEvents 3178756 # Number of times rename has blocked due to LSQ full
1372system.cpu1.rename.FullRegisterEvents 32684 # Number of times there has been no free registers
1373system.cpu1.rename.RenamedOperands 70870880 # Number of destination operands rename has renamed
1374system.cpu1.rename.RenameLookups 310023883 # Number of register rename lookups that rename has made
1375system.cpu1.rename.int_rename_lookups 309964693 # Number of integer rename lookups
1376system.cpu1.rename.fp_rename_lookups 59190 # Number of floating rename lookups
1377system.cpu1.rename.CommittedMaps 50213421 # Number of HB maps that are committed
1378system.cpu1.rename.UndoneMaps 20657459 # Number of HB maps that are undone due to squashing
1379system.cpu1.rename.serializingInsts 473589 # count of serializing insts renamed
1380system.cpu1.rename.tempSerializingInsts 413624 # count of temporary serializing insts renamed
1381system.cpu1.rename.skidInsts 8131877 # count of insts added to the skid buffer
1382system.cpu1.memDep0.insertedLoads 12919526 # Number of loads inserted to the mem dependence unit.
1383system.cpu1.memDep0.insertedStores 8160199 # Number of stores inserted to the mem dependence unit.
1384system.cpu1.memDep0.conflictingLoads 1076421 # Number of conflicting loads.
1385system.cpu1.memDep0.conflictingStores 1515550 # Number of conflicting stores.
1386system.cpu1.iq.iqInstsAdded 62172086 # Number of instructions added to the IQ (excludes non-spec)
1387system.cpu1.iq.iqNonSpecInstsAdded 1201080 # Number of non-speculative instructions added to the IQ
1388system.cpu1.iq.iqInstsIssued 89161848 # Number of instructions issued
1389system.cpu1.iq.iqSquashedInstsIssued 100982 # Number of squashed instructions issued
1390system.cpu1.iq.iqSquashedInstsExamined 13762748 # Number of squashed instructions iterated over during squash; mainly for profiling
1391system.cpu1.iq.iqSquashedOperandsExamined 36926540 # Number of squashed operands that are examined and possibly removed from graph
1392system.cpu1.iq.iqSquashedNonSpecRemoved 280453 # Number of squashed non-spec instructions that were removed
1393system.cpu1.iq.issued_per_cycle::samples 113770833 # Number of insts issued each cycle
1394system.cpu1.iq.issued_per_cycle::mean 0.783697 # Number of insts issued each cycle
1395system.cpu1.iq.issued_per_cycle::stdev 1.520241 # Number of insts issued each cycle
1396system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1397system.cpu1.iq.issued_per_cycle::0 83205809 73.13% 73.13% # Number of insts issued each cycle
1398system.cpu1.iq.issued_per_cycle::1 8622127 7.58% 80.71% # Number of insts issued each cycle
1399system.cpu1.iq.issued_per_cycle::2 4341809 3.82% 84.53% # Number of insts issued each cycle
1400system.cpu1.iq.issued_per_cycle::3 3750529 3.30% 87.83% # Number of insts issued each cycle
1401system.cpu1.iq.issued_per_cycle::4 10472490 9.20% 97.03% # Number of insts issued each cycle
1402system.cpu1.iq.issued_per_cycle::5 1973623 1.73% 98.77% # Number of insts issued each cycle
1403system.cpu1.iq.issued_per_cycle::6 1061651 0.93% 99.70% # Number of insts issued each cycle
1404system.cpu1.iq.issued_per_cycle::7 265825 0.23% 99.93% # Number of insts issued each cycle
1405system.cpu1.iq.issued_per_cycle::8 76970 0.07% 100.00% # Number of insts issued each cycle
1406system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1407system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1408system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1409system.cpu1.iq.issued_per_cycle::total 113770833 # Number of insts issued each cycle
1410system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1411system.cpu1.iq.fu_full::IntAlu 29803 0.38% 0.38% # attempts to use FU when none available
1412system.cpu1.iq.fu_full::IntMult 992 0.01% 0.39% # attempts to use FU when none available
1413system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available
1414system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available
1415system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available
1416system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available
1417system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available
1418system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available
1419system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available
1420system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available
1421system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available
1422system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available
1423system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available
1424system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available
1425system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available
1426system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available
1427system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available
1428system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available
1429system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available
1430system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available
1431system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.39% # attempts to use FU when none available
1432system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.39% # attempts to use FU when none available
1433system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.39% # attempts to use FU when none available
1434system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.39% # attempts to use FU when none available
1435system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.39% # attempts to use FU when none available
1436system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # attempts to use FU when none available
1437system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available
1438system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available
1439system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available
1440system.cpu1.iq.fu_full::MemRead 7572506 95.90% 96.29% # attempts to use FU when none available
1441system.cpu1.iq.fu_full::MemWrite 293239 3.71% 100.00% # attempts to use FU when none available
1442system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1443system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1444system.cpu1.iq.FU_type_0::No_OpClass 314062 0.35% 0.35% # Type of FU issued
1445system.cpu1.iq.FU_type_0::IntAlu 37491969 42.05% 42.40% # Type of FU issued
1446system.cpu1.iq.FU_type_0::IntMult 61148 0.07% 42.47% # Type of FU issued
1447system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.47% # Type of FU issued
1448system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.47% # Type of FU issued
1449system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.47% # Type of FU issued
1450system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.47% # Type of FU issued
1451system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.47% # Type of FU issued
1452system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.47% # Type of FU issued
1453system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.47% # Type of FU issued
1454system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.47% # Type of FU issued
1455system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.47% # Type of FU issued
1456system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.47% # Type of FU issued
1457system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.47% # Type of FU issued
1458system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.47% # Type of FU issued
1459system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.47% # Type of FU issued
1460system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.47% # Type of FU issued
1461system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.47% # Type of FU issued
1462system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.47% # Type of FU issued
1463system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.47% # Type of FU issued
1464system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.47% # Type of FU issued
1465system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.47% # Type of FU issued
1466system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.47% # Type of FU issued
1467system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.47% # Type of FU issued
1468system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.47% # Type of FU issued
1469system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.47% # Type of FU issued
1470system.cpu1.iq.FU_type_0::SimdFloatMisc 1700 0.00% 42.47% # Type of FU issued
1471system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.47% # Type of FU issued
1472system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.47% # Type of FU issued
1473system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.47% # Type of FU issued
1474system.cpu1.iq.FU_type_0::MemRead 43923048 49.26% 91.73% # Type of FU issued
1475system.cpu1.iq.FU_type_0::MemWrite 7369892 8.27% 100.00% # Type of FU issued
1476system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1477system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1478system.cpu1.iq.FU_type_0::total 89161848 # Type of FU issued
1479system.cpu1.iq.rate 0.217987 # Inst issue rate
1480system.cpu1.iq.fu_busy_cnt 7896540 # FU busy when requested
1481system.cpu1.iq.fu_busy_rate 0.088564 # FU busy rate (busy events/executed inst)
1482system.cpu1.iq.int_inst_queue_reads 300131429 # Number of integer instruction queue reads
1483system.cpu1.iq.int_inst_queue_writes 77144913 # Number of integer instruction queue writes
1484system.cpu1.iq.int_inst_queue_wakeup_accesses 54450273 # Number of integer instruction queue wakeup accesses
1485system.cpu1.iq.fp_inst_queue_reads 14948 # Number of floating instruction queue reads
1486system.cpu1.iq.fp_inst_queue_writes 8092 # Number of floating instruction queue writes
1487system.cpu1.iq.fp_inst_queue_wakeup_accesses 6814 # Number of floating instruction queue wakeup accesses
1488system.cpu1.iq.int_alu_accesses 96736439 # Number of integer alu accesses
1489system.cpu1.iq.fp_alu_accesses 7887 # Number of floating point alu accesses
1490system.cpu1.iew.lsq.thread0.forwLoads 357826 # Number of loads that had data forwarded from stores
1491system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1492system.cpu1.iew.lsq.thread0.squashedLoads 2919371 # Number of loads squashed
1493system.cpu1.iew.lsq.thread0.ignoredResponses 4089 # Number of memory responses ignored because the instruction is squashed
1494system.cpu1.iew.lsq.thread0.memOrderViolation 17660 # Number of memory ordering violations
1495system.cpu1.iew.lsq.thread0.squashedStores 1133342 # Number of stores squashed
1496system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1497system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1498system.cpu1.iew.lsq.thread0.rescheduledLoads 31965401 # Number of loads that were rescheduled
1499system.cpu1.iew.lsq.thread0.cacheBlocked 692354 # Number of times an access to memory failed due to the cache being blocked
1500system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1501system.cpu1.iew.iewSquashCycles 2250958 # Number of cycles IEW is squashing
1502system.cpu1.iew.iewBlockCycles 24192691 # Number of cycles IEW is blocking
1503system.cpu1.iew.iewUnblockCycles 367138 # Number of cycles IEW is unblocking
1504system.cpu1.iew.iewDispatchedInsts 63477454 # Number of instructions dispatched to IQ
1505system.cpu1.iew.iewDispSquashedInsts 113697 # Number of squashed instructions skipped by dispatch
1506system.cpu1.iew.iewDispLoadInsts 12919526 # Number of dispatched load instructions
1507system.cpu1.iew.iewDispStoreInsts 8160199 # Number of dispatched store instructions
1508system.cpu1.iew.iewDispNonSpecInsts 893697 # Number of dispatched non-speculative instructions
1509system.cpu1.iew.iewIQFullEvents 68960 # Number of times the IQ has become full, causing a stall
1510system.cpu1.iew.iewLSQFullEvents 3858 # Number of times the LSQ has become full, causing a stall
1511system.cpu1.iew.memOrderViolationEvents 17660 # Number of memory order violations
1512system.cpu1.iew.predictedTakenIncorrect 208465 # Number of branches that were predicted taken incorrectly
1513system.cpu1.iew.predictedNotTakenIncorrect 159370 # Number of branches that were predicted not taken incorrectly
1514system.cpu1.iew.branchMispredicts 367835 # Number of branch mispredicts detected at execute
1515system.cpu1.iew.iewExecutedInsts 87401818 # Number of executed instructions
1516system.cpu1.iew.iewExecLoadInsts 43412086 # Number of load instructions executed
1517system.cpu1.iew.iewExecSquashedInsts 1760030 # Number of squashed instructions skipped in execute
1518system.cpu1.iew.exec_swp 0 # number of swp insts executed
1519system.cpu1.iew.exec_nop 104288 # number of nop insts executed
1520system.cpu1.iew.exec_refs 50709476 # number of memory reference insts executed
1521system.cpu1.iew.exec_branches 7088545 # Number of branches executed
1522system.cpu1.iew.exec_stores 7297390 # Number of stores executed
1523system.cpu1.iew.exec_rate 0.213684 # Inst execution rate
1524system.cpu1.iew.wb_sent 86601126 # cumulative count of insts sent to commit
1525system.cpu1.iew.wb_count 54457087 # cumulative count of insts written-back
1526system.cpu1.iew.wb_producers 30364436 # num instructions producing a value
1527system.cpu1.iew.wb_consumers 54295656 # num instructions consuming a value
1528system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1529system.cpu1.iew.wb_rate 0.133139 # insts written-back per cycle
1530system.cpu1.iew.wb_fanout 0.559242 # average fanout of values written-back
1531system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1532system.cpu1.commit.commitSquashedInsts 13692554 # The number of squashed insts skipped by commit
1533system.cpu1.commit.commitNonSpecStalls 920627 # The number of times commit has been forced to stall to communicate backwards
1534system.cpu1.commit.branchMispredicts 322274 # The number of times a branch was mispredicted
1535system.cpu1.commit.committed_per_cycle::samples 111568344 # Number of insts commited each cycle
1536system.cpu1.commit.committed_per_cycle::mean 0.442227 # Number of insts commited each cycle
1537system.cpu1.commit.committed_per_cycle::stdev 1.413238 # Number of insts commited each cycle
1538system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1539system.cpu1.commit.committed_per_cycle::0 94375668 84.59% 84.59% # Number of insts commited each cycle
1540system.cpu1.commit.committed_per_cycle::1 8446118 7.57% 92.16% # Number of insts commited each cycle
1541system.cpu1.commit.committed_per_cycle::2 2197127 1.97% 94.13% # Number of insts commited each cycle
1542system.cpu1.commit.committed_per_cycle::3 1290727 1.16% 95.29% # Number of insts commited each cycle
1543system.cpu1.commit.committed_per_cycle::4 1277171 1.14% 96.43% # Number of insts commited each cycle
1544system.cpu1.commit.committed_per_cycle::5 591366 0.53% 96.96% # Number of insts commited each cycle
1545system.cpu1.commit.committed_per_cycle::6 1009730 0.91% 97.87% # Number of insts commited each cycle
1546system.cpu1.commit.committed_per_cycle::7 541366 0.49% 98.35% # Number of insts commited each cycle
1547system.cpu1.commit.committed_per_cycle::8 1839071 1.65% 100.00% # Number of insts commited each cycle
1548system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1549system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1550system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1551system.cpu1.commit.committed_per_cycle::total 111568344 # Number of insts commited each cycle
1552system.cpu1.commit.committedInsts 38958201 # Number of instructions committed
1553system.cpu1.commit.committedOps 49338577 # Number of ops (including micro ops) committed
1554system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
1555system.cpu1.commit.refs 17027012 # Number of memory references committed
1556system.cpu1.commit.loads 10000155 # Number of loads committed
1557system.cpu1.commit.membars 202531 # Number of memory barriers committed
1558system.cpu1.commit.branches 6139960 # Number of branches committed
1559system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
1560system.cpu1.commit.int_insts 43727423 # Number of committed integer instructions.
1561system.cpu1.commit.function_calls 556605 # Number of function calls committed.
1562system.cpu1.commit.bw_lim_events 1839071 # number cycles where commit BW limit reached
1563system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
1564system.cpu1.rob.rob_reads 171645222 # The number of ROB reads
1565system.cpu1.rob.rob_writes 128401309 # The number of ROB writes
1566system.cpu1.timesIdled 1423775 # Number of times that the entire CPU went into an idle state and unscheduled itself
1567system.cpu1.idleCycles 295253416 # Total number of cycles that the CPU has spent unscheduled due to idling
1568system.cpu1.quiesceCycles 4776625618 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1569system.cpu1.committedInsts 38888562 # Number of Instructions Simulated
1570system.cpu1.committedOps 49268938 # Number of Ops (including micro ops) Simulated
1571system.cpu1.committedInsts_total 38888562 # Number of Instructions Simulated
1572system.cpu1.cpi 10.517855 # CPI: Cycles Per Instruction
1573system.cpu1.cpi_total 10.517855 # CPI: Total CPI of All Threads
1574system.cpu1.ipc 0.095076 # IPC: Instructions Per Cycle
1575system.cpu1.ipc_total 0.095076 # IPC: Total IPC of All Threads
1576system.cpu1.int_regfile_reads 391481129 # number of integer regfile reads
1577system.cpu1.int_regfile_writes 56596470 # number of integer regfile writes
1578system.cpu1.fp_regfile_reads 4905 # number of floating regfile reads
1579system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes
1580system.cpu1.misc_regfile_reads 81326805 # number of misc regfile reads
1581system.cpu1.misc_regfile_writes 430176 # number of misc regfile writes
1582system.cpu1.icache.replacements 614989 # number of replacements
1583system.cpu1.icache.tagsinuse 498.619037 # Cycle average of tags in use
1584system.cpu1.icache.total_refs 7122851 # Total number of references to valid blocks.
1585system.cpu1.icache.sampled_refs 615501 # Sample count of references to valid blocks.
1586system.cpu1.icache.avg_refs 11.572444 # Average number of references to valid blocks.
1587system.cpu1.icache.warmup_cycle 74507010000 # Cycle when the warmup percentage was hit.
1588system.cpu1.icache.occ_blocks::cpu1.inst 498.619037 # Average occupied blocks per requestor
1589system.cpu1.icache.occ_percent::cpu1.inst 0.973865 # Average percentage of cache occupancy
1590system.cpu1.icache.occ_percent::total 0.973865 # Average percentage of cache occupancy
1591system.cpu1.icache.ReadReq_hits::cpu1.inst 7122851 # number of ReadReq hits
1592system.cpu1.icache.ReadReq_hits::total 7122851 # number of ReadReq hits
1593system.cpu1.icache.demand_hits::cpu1.inst 7122851 # number of demand (read+write) hits
1594system.cpu1.icache.demand_hits::total 7122851 # number of demand (read+write) hits
1595system.cpu1.icache.overall_hits::cpu1.inst 7122851 # number of overall hits
1596system.cpu1.icache.overall_hits::total 7122851 # number of overall hits
1597system.cpu1.icache.ReadReq_misses::cpu1.inst 661583 # number of ReadReq misses
1598system.cpu1.icache.ReadReq_misses::total 661583 # number of ReadReq misses
1599system.cpu1.icache.demand_misses::cpu1.inst 661583 # number of demand (read+write) misses
1600system.cpu1.icache.demand_misses::total 661583 # number of demand (read+write) misses
1601system.cpu1.icache.overall_misses::cpu1.inst 661583 # number of overall misses
1602system.cpu1.icache.overall_misses::total 661583 # number of overall misses
1603system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8883357995 # number of ReadReq miss cycles
1604system.cpu1.icache.ReadReq_miss_latency::total 8883357995 # number of ReadReq miss cycles
1605system.cpu1.icache.demand_miss_latency::cpu1.inst 8883357995 # number of demand (read+write) miss cycles
1606system.cpu1.icache.demand_miss_latency::total 8883357995 # number of demand (read+write) miss cycles
1607system.cpu1.icache.overall_miss_latency::cpu1.inst 8883357995 # number of overall miss cycles
1608system.cpu1.icache.overall_miss_latency::total 8883357995 # number of overall miss cycles
1609system.cpu1.icache.ReadReq_accesses::cpu1.inst 7784434 # number of ReadReq accesses(hits+misses)
1610system.cpu1.icache.ReadReq_accesses::total 7784434 # number of ReadReq accesses(hits+misses)
1611system.cpu1.icache.demand_accesses::cpu1.inst 7784434 # number of demand (read+write) accesses
1612system.cpu1.icache.demand_accesses::total 7784434 # number of demand (read+write) accesses
1613system.cpu1.icache.overall_accesses::cpu1.inst 7784434 # number of overall (read+write) accesses
1614system.cpu1.icache.overall_accesses::total 7784434 # number of overall (read+write) accesses
1615system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084988 # miss rate for ReadReq accesses
1616system.cpu1.icache.ReadReq_miss_rate::total 0.084988 # miss rate for ReadReq accesses
1617system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084988 # miss rate for demand accesses
1618system.cpu1.icache.demand_miss_rate::total 0.084988 # miss rate for demand accesses
1619system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084988 # miss rate for overall accesses
1620system.cpu1.icache.overall_miss_rate::total 0.084988 # miss rate for overall accesses
1621system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13427.427844 # average ReadReq miss latency
1622system.cpu1.icache.ReadReq_avg_miss_latency::total 13427.427844 # average ReadReq miss latency
1623system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13427.427844 # average overall miss latency
1624system.cpu1.icache.demand_avg_miss_latency::total 13427.427844 # average overall miss latency
1625system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13427.427844 # average overall miss latency
1626system.cpu1.icache.overall_avg_miss_latency::total 13427.427844 # average overall miss latency
1627system.cpu1.icache.blocked_cycles::no_mshrs 3547 # number of cycles access was blocked
1628system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1629system.cpu1.icache.blocked::no_mshrs 182 # number of cycles access was blocked
1630system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1631system.cpu1.icache.avg_blocked_cycles::no_mshrs 19.489011 # average number of cycles each access was blocked
1632system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1633system.cpu1.icache.fast_writes 0 # number of fast writes performed
1634system.cpu1.icache.cache_copies 0 # number of cache copies performed
1635system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46050 # number of ReadReq MSHR hits
1636system.cpu1.icache.ReadReq_mshr_hits::total 46050 # number of ReadReq MSHR hits
1637system.cpu1.icache.demand_mshr_hits::cpu1.inst 46050 # number of demand (read+write) MSHR hits
1638system.cpu1.icache.demand_mshr_hits::total 46050 # number of demand (read+write) MSHR hits
1639system.cpu1.icache.overall_mshr_hits::cpu1.inst 46050 # number of overall MSHR hits
1640system.cpu1.icache.overall_mshr_hits::total 46050 # number of overall MSHR hits
1641system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615533 # number of ReadReq MSHR misses
1642system.cpu1.icache.ReadReq_mshr_misses::total 615533 # number of ReadReq MSHR misses
1643system.cpu1.icache.demand_mshr_misses::cpu1.inst 615533 # number of demand (read+write) MSHR misses
1644system.cpu1.icache.demand_mshr_misses::total 615533 # number of demand (read+write) MSHR misses
1645system.cpu1.icache.overall_mshr_misses::cpu1.inst 615533 # number of overall MSHR misses
1646system.cpu1.icache.overall_mshr_misses::total 615533 # number of overall MSHR misses
1647system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7269169496 # number of ReadReq MSHR miss cycles
1648system.cpu1.icache.ReadReq_mshr_miss_latency::total 7269169496 # number of ReadReq MSHR miss cycles
1649system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7269169496 # number of demand (read+write) MSHR miss cycles
1650system.cpu1.icache.demand_mshr_miss_latency::total 7269169496 # number of demand (read+write) MSHR miss cycles
1651system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7269169496 # number of overall MSHR miss cycles
1652system.cpu1.icache.overall_mshr_miss_latency::total 7269169496 # number of overall MSHR miss cycles
1653system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2823500 # number of ReadReq MSHR uncacheable cycles
1654system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2823500 # number of ReadReq MSHR uncacheable cycles
1655system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2823500 # number of overall MSHR uncacheable cycles
1656system.cpu1.icache.overall_mshr_uncacheable_latency::total 2823500 # number of overall MSHR uncacheable cycles
1657system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for ReadReq accesses
1658system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079072 # mshr miss rate for ReadReq accesses
1659system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for demand accesses
1660system.cpu1.icache.demand_mshr_miss_rate::total 0.079072 # mshr miss rate for demand accesses
1661system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for overall accesses
1662system.cpu1.icache.overall_mshr_miss_rate::total 0.079072 # mshr miss rate for overall accesses
1663system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average ReadReq mshr miss latency
1664system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11809.552853 # average ReadReq mshr miss latency
1665system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average overall mshr miss latency
1666system.cpu1.icache.demand_avg_mshr_miss_latency::total 11809.552853 # average overall mshr miss latency
1667system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average overall mshr miss latency
1668system.cpu1.icache.overall_avg_mshr_miss_latency::total 11809.552853 # average overall mshr miss latency
1669system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
1670system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1671system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
1672system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1673system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1674system.cpu1.dcache.replacements 363437 # number of replacements
1675system.cpu1.dcache.tagsinuse 485.666262 # Cycle average of tags in use
1676system.cpu1.dcache.total_refs 13086846 # Total number of references to valid blocks.
1677system.cpu1.dcache.sampled_refs 363802 # Sample count of references to valid blocks.
1678system.cpu1.dcache.avg_refs 35.972441 # Average number of references to valid blocks.
1679system.cpu1.dcache.warmup_cycle 70623957000 # Cycle when the warmup percentage was hit.
1680system.cpu1.dcache.occ_blocks::cpu1.data 485.666262 # Average occupied blocks per requestor
1681system.cpu1.dcache.occ_percent::cpu1.data 0.948567 # Average percentage of cache occupancy
1682system.cpu1.dcache.occ_percent::total 0.948567 # Average percentage of cache occupancy
1683system.cpu1.dcache.ReadReq_hits::cpu1.data 8551806 # number of ReadReq hits
1684system.cpu1.dcache.ReadReq_hits::total 8551806 # number of ReadReq hits
1685system.cpu1.dcache.WriteReq_hits::cpu1.data 4291461 # number of WriteReq hits
1686system.cpu1.dcache.WriteReq_hits::total 4291461 # number of WriteReq hits
1687system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 103521 # number of LoadLockedReq hits
1688system.cpu1.dcache.LoadLockedReq_hits::total 103521 # number of LoadLockedReq hits
1689system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100890 # number of StoreCondReq hits
1690system.cpu1.dcache.StoreCondReq_hits::total 100890 # number of StoreCondReq hits
1691system.cpu1.dcache.demand_hits::cpu1.data 12843267 # number of demand (read+write) hits
1692system.cpu1.dcache.demand_hits::total 12843267 # number of demand (read+write) hits
1693system.cpu1.dcache.overall_hits::cpu1.data 12843267 # number of overall hits
1694system.cpu1.dcache.overall_hits::total 12843267 # number of overall hits
1695system.cpu1.dcache.ReadReq_misses::cpu1.data 401802 # number of ReadReq misses
1696system.cpu1.dcache.ReadReq_misses::total 401802 # number of ReadReq misses
1697system.cpu1.dcache.WriteReq_misses::cpu1.data 1565358 # number of WriteReq misses
1698system.cpu1.dcache.WriteReq_misses::total 1565358 # number of WriteReq misses
1699system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14225 # number of LoadLockedReq misses
1700system.cpu1.dcache.LoadLockedReq_misses::total 14225 # number of LoadLockedReq misses
1701system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10942 # number of StoreCondReq misses
1702system.cpu1.dcache.StoreCondReq_misses::total 10942 # number of StoreCondReq misses
1703system.cpu1.dcache.demand_misses::cpu1.data 1967160 # number of demand (read+write) misses
1704system.cpu1.dcache.demand_misses::total 1967160 # number of demand (read+write) misses
1705system.cpu1.dcache.overall_misses::cpu1.data 1967160 # number of overall misses
1706system.cpu1.dcache.overall_misses::total 1967160 # number of overall misses
1707system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6026246000 # number of ReadReq miss cycles
1708system.cpu1.dcache.ReadReq_miss_latency::total 6026246000 # number of ReadReq miss cycles
1709system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 64613580018 # number of WriteReq miss cycles
1710system.cpu1.dcache.WriteReq_miss_latency::total 64613580018 # number of WriteReq miss cycles
1711system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131651000 # number of LoadLockedReq miss cycles
1712system.cpu1.dcache.LoadLockedReq_miss_latency::total 131651000 # number of LoadLockedReq miss cycles
1713system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58881000 # number of StoreCondReq miss cycles
1714system.cpu1.dcache.StoreCondReq_miss_latency::total 58881000 # number of StoreCondReq miss cycles
1715system.cpu1.dcache.demand_miss_latency::cpu1.data 70639826018 # number of demand (read+write) miss cycles
1716system.cpu1.dcache.demand_miss_latency::total 70639826018 # number of demand (read+write) miss cycles
1717system.cpu1.dcache.overall_miss_latency::cpu1.data 70639826018 # number of overall miss cycles
1718system.cpu1.dcache.overall_miss_latency::total 70639826018 # number of overall miss cycles
1719system.cpu1.dcache.ReadReq_accesses::cpu1.data 8953608 # number of ReadReq accesses(hits+misses)
1720system.cpu1.dcache.ReadReq_accesses::total 8953608 # number of ReadReq accesses(hits+misses)
1721system.cpu1.dcache.WriteReq_accesses::cpu1.data 5856819 # number of WriteReq accesses(hits+misses)
1722system.cpu1.dcache.WriteReq_accesses::total 5856819 # number of WriteReq accesses(hits+misses)
1723system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 117746 # number of LoadLockedReq accesses(hits+misses)
1724system.cpu1.dcache.LoadLockedReq_accesses::total 117746 # number of LoadLockedReq accesses(hits+misses)
1725system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111832 # number of StoreCondReq accesses(hits+misses)
1726system.cpu1.dcache.StoreCondReq_accesses::total 111832 # number of StoreCondReq accesses(hits+misses)
1727system.cpu1.dcache.demand_accesses::cpu1.data 14810427 # number of demand (read+write) accesses
1728system.cpu1.dcache.demand_accesses::total 14810427 # number of demand (read+write) accesses
1729system.cpu1.dcache.overall_accesses::cpu1.data 14810427 # number of overall (read+write) accesses
1730system.cpu1.dcache.overall_accesses::total 14810427 # number of overall (read+write) accesses
1731system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044876 # miss rate for ReadReq accesses
1732system.cpu1.dcache.ReadReq_miss_rate::total 0.044876 # miss rate for ReadReq accesses
1733system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.267271 # miss rate for WriteReq accesses
1734system.cpu1.dcache.WriteReq_miss_rate::total 0.267271 # miss rate for WriteReq accesses
1735system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120811 # miss rate for LoadLockedReq accesses
1736system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120811 # miss rate for LoadLockedReq accesses
1737system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097843 # miss rate for StoreCondReq accesses
1738system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097843 # miss rate for StoreCondReq accesses
1739system.cpu1.dcache.demand_miss_rate::cpu1.data 0.132823 # miss rate for demand accesses
1740system.cpu1.dcache.demand_miss_rate::total 0.132823 # miss rate for demand accesses
1741system.cpu1.dcache.overall_miss_rate::cpu1.data 0.132823 # miss rate for overall accesses
1742system.cpu1.dcache.overall_miss_rate::total 0.132823 # miss rate for overall accesses
1743system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14998.048790 # average ReadReq miss latency
1744system.cpu1.dcache.ReadReq_avg_miss_latency::total 14998.048790 # average ReadReq miss latency
1745system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41277.190277 # average WriteReq miss latency
1746system.cpu1.dcache.WriteReq_avg_miss_latency::total 41277.190277 # average WriteReq miss latency
1747system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9254.903339 # average LoadLockedReq miss latency
1748system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9254.903339 # average LoadLockedReq miss latency
1749system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5381.191738 # average StoreCondReq miss latency
1750system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5381.191738 # average StoreCondReq miss latency
1751system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35909.547784 # average overall miss latency
1752system.cpu1.dcache.demand_avg_miss_latency::total 35909.547784 # average overall miss latency
1753system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35909.547784 # average overall miss latency
1754system.cpu1.dcache.overall_avg_miss_latency::total 35909.547784 # average overall miss latency
1755system.cpu1.dcache.blocked_cycles::no_mshrs 28351 # number of cycles access was blocked
1756system.cpu1.dcache.blocked_cycles::no_targets 15005 # number of cycles access was blocked
1757system.cpu1.dcache.blocked::no_mshrs 3227 # number of cycles access was blocked
1758system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked
1759system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.785559 # average number of cycles each access was blocked
1760system.cpu1.dcache.avg_blocked_cycles::no_targets 89.315476 # average number of cycles each access was blocked
1761system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1762system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1763system.cpu1.dcache.writebacks::writebacks 328383 # number of writebacks
1764system.cpu1.dcache.writebacks::total 328383 # number of writebacks
1765system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170419 # number of ReadReq MSHR hits
1766system.cpu1.dcache.ReadReq_mshr_hits::total 170419 # number of ReadReq MSHR hits
1767system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1402227 # number of WriteReq MSHR hits
1768system.cpu1.dcache.WriteReq_mshr_hits::total 1402227 # number of WriteReq MSHR hits
1769system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1450 # number of LoadLockedReq MSHR hits
1770system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1450 # number of LoadLockedReq MSHR hits
1771system.cpu1.dcache.demand_mshr_hits::cpu1.data 1572646 # number of demand (read+write) MSHR hits
1772system.cpu1.dcache.demand_mshr_hits::total 1572646 # number of demand (read+write) MSHR hits
1773system.cpu1.dcache.overall_mshr_hits::cpu1.data 1572646 # number of overall MSHR hits
1774system.cpu1.dcache.overall_mshr_hits::total 1572646 # number of overall MSHR hits
1775system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231383 # number of ReadReq MSHR misses
1776system.cpu1.dcache.ReadReq_mshr_misses::total 231383 # number of ReadReq MSHR misses
1777system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163131 # number of WriteReq MSHR misses
1778system.cpu1.dcache.WriteReq_mshr_misses::total 163131 # number of WriteReq MSHR misses
1779system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12775 # number of LoadLockedReq MSHR misses
1780system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12775 # number of LoadLockedReq MSHR misses
1781system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10936 # number of StoreCondReq MSHR misses
1782system.cpu1.dcache.StoreCondReq_mshr_misses::total 10936 # number of StoreCondReq MSHR misses
1783system.cpu1.dcache.demand_mshr_misses::cpu1.data 394514 # number of demand (read+write) MSHR misses
1784system.cpu1.dcache.demand_mshr_misses::total 394514 # number of demand (read+write) MSHR misses
1785system.cpu1.dcache.overall_mshr_misses::cpu1.data 394514 # number of overall MSHR misses
1786system.cpu1.dcache.overall_mshr_misses::total 394514 # number of overall MSHR misses
1787system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2870368000 # number of ReadReq MSHR miss cycles
1788system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2870368000 # number of ReadReq MSHR miss cycles
1789system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5301094210 # number of WriteReq MSHR miss cycles
1790system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5301094210 # number of WriteReq MSHR miss cycles
1791system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90117500 # number of LoadLockedReq MSHR miss cycles
1792system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90117500 # number of LoadLockedReq MSHR miss cycles
1793system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 37009000 # number of StoreCondReq MSHR miss cycles
1794system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 37009000 # number of StoreCondReq MSHR miss cycles
1795system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8171462210 # number of demand (read+write) MSHR miss cycles
1796system.cpu1.dcache.demand_mshr_miss_latency::total 8171462210 # number of demand (read+write) MSHR miss cycles
1797system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8171462210 # number of overall MSHR miss cycles
1798system.cpu1.dcache.overall_mshr_miss_latency::total 8171462210 # number of overall MSHR miss cycles
1799system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169263515000 # number of ReadReq MSHR uncacheable cycles
1800system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169263515000 # number of ReadReq MSHR uncacheable cycles
1801system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 26947906394 # number of WriteReq MSHR uncacheable cycles
1802system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 26947906394 # number of WriteReq MSHR uncacheable cycles
1803system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196211421394 # number of overall MSHR uncacheable cycles
1804system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196211421394 # number of overall MSHR uncacheable cycles
1805system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025842 # mshr miss rate for ReadReq accesses
1806system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025842 # mshr miss rate for ReadReq accesses
1807system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027853 # mshr miss rate for WriteReq accesses
1808system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027853 # mshr miss rate for WriteReq accesses
1809system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.108496 # mshr miss rate for LoadLockedReq accesses
1810system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.108496 # mshr miss rate for LoadLockedReq accesses
1811system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097790 # mshr miss rate for StoreCondReq accesses
1812system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097790 # mshr miss rate for StoreCondReq accesses
1813system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026638 # mshr miss rate for demand accesses
1814system.cpu1.dcache.demand_mshr_miss_rate::total 0.026638 # mshr miss rate for demand accesses
1815system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026638 # mshr miss rate for overall accesses
1816system.cpu1.dcache.overall_mshr_miss_rate::total 0.026638 # mshr miss rate for overall accesses
1817system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12405.267457 # average ReadReq mshr miss latency
1818system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12405.267457 # average ReadReq mshr miss latency
1819system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32495.934004 # average WriteReq mshr miss latency
1820system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32495.934004 # average WriteReq mshr miss latency
1821system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7054.207436 # average LoadLockedReq mshr miss latency
1822system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7054.207436 # average LoadLockedReq mshr miss latency
1823system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3384.144111 # average StoreCondReq mshr miss latency
1824system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3384.144111 # average StoreCondReq mshr miss latency
1825system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20712.730626 # average overall mshr miss latency
1826system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20712.730626 # average overall mshr miss latency
1827system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20712.730626 # average overall mshr miss latency
1828system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20712.730626 # average overall mshr miss latency
1829system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1830system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1831system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1832system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1833system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1834system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1835system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1836system.iocache.replacements 0 # number of replacements

--- 5 unchanged lines hidden (view full) ---

1842system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1843system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1844system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1845system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1846system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1847system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1848system.iocache.fast_writes 0 # number of fast writes performed
1849system.iocache.cache_copies 0 # number of cache copies performed
1850system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1082174693399 # number of ReadReq MSHR uncacheable cycles
1851system.iocache.ReadReq_mshr_uncacheable_latency::total 1082174693399 # number of ReadReq MSHR uncacheable cycles
1852system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1082174693399 # number of overall MSHR uncacheable cycles
1853system.iocache.overall_mshr_uncacheable_latency::total 1082174693399 # number of overall MSHR uncacheable cycles
1854system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
1855system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1856system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
1857system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1858system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1859system.cpu0.kern.inst.arm 0 # number of arm instructions executed
1860system.cpu0.kern.inst.quiesce 43757 # number of quiesce instructions executed
1861system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1862system.cpu1.kern.inst.quiesce 53969 # number of quiesce instructions executed
1863
1864---------- End Simulation Statistics ----------