1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.572328 # Number of seconds simulated
4sim_ticks 2572328372500 # Number of ticks simulated
5final_tick 2572328372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 81734 # Simulator instruction rate (inst/s)
8host_op_rate 105574 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 3400147622 # Simulator tick rate (ticks/s)
10host_mem_usage 384052 # Number of bytes of host memory used
11host_seconds 756.53 # Real time elapsed on the host
12sim_insts 61834256 # Number of instructions simulated
13sim_ops 79870174 # Number of ops (including micro ops) simulated
14system.nvmem.bytes_read 384 # Number of bytes read from this memory
15system.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory
16system.nvmem.bytes_written 0 # Number of bytes written to this memory
17system.nvmem.num_reads 6 # Number of read requests responded to by this memory
18system.nvmem.num_writes 0 # Number of write requests responded to by this memory
19system.nvmem.num_other 0 # Number of other requests responded to by this memory
20system.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s)
21system.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s)
22system.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s)
23system.physmem.bytes_read 131402148 # Number of bytes read from this memory
24system.physmem.bytes_inst_read 1183168 # Number of instructions bytes read from this memory
25system.physmem.bytes_written 10205776 # Number of bytes written to this memory
26system.physmem.num_reads 15127689 # Number of read requests responded to by this memory
27system.physmem.num_writes 869419 # Number of write requests responded to by this memory
28system.physmem.num_other 0 # Number of other requests responded to by this memory
29system.physmem.bw_read 51082960 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read 459960 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write 3967525 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_total 55050485 # Total bandwidth to/from this memory (bytes/s)
33system.l2c.replacements 130931 # number of replacements
34system.l2c.tagsinuse 27519.920349 # Cycle average of tags in use
35system.l2c.total_refs 1850900 # Total number of references to valid blocks.
36system.l2c.sampled_refs 160584 # Sample count of references to valid blocks.
37system.l2c.avg_refs 11.526055 # Average number of references to valid blocks.
38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
39system.l2c.occ_blocks::writebacks 15169.797230 # Average occupied blocks per requestor
40system.l2c.occ_blocks::cpu0.dtb.walker 19.693620 # Average occupied blocks per requestor
41system.l2c.occ_blocks::cpu0.itb.walker 0.048154 # Average occupied blocks per requestor
42system.l2c.occ_blocks::cpu0.inst 2916.118065 # Average occupied blocks per requestor
43system.l2c.occ_blocks::cpu0.data 1448.517664 # Average occupied blocks per requestor
44system.l2c.occ_blocks::cpu1.dtb.walker 24.954124 # Average occupied blocks per requestor
45system.l2c.occ_blocks::cpu1.itb.walker 0.021877 # Average occupied blocks per requestor
46system.l2c.occ_blocks::cpu1.inst 3298.971983 # Average occupied blocks per requestor
47system.l2c.occ_blocks::cpu1.data 4641.797632 # Average occupied blocks per requestor
48system.l2c.occ_percent::writebacks 0.231473 # Average percentage of cache occupancy
49system.l2c.occ_percent::cpu0.dtb.walker 0.000301 # Average percentage of cache occupancy
50system.l2c.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
51system.l2c.occ_percent::cpu0.inst 0.044496 # Average percentage of cache occupancy
52system.l2c.occ_percent::cpu0.data 0.022103 # Average percentage of cache occupancy
53system.l2c.occ_percent::cpu1.dtb.walker 0.000381 # Average percentage of cache occupancy
54system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
55system.l2c.occ_percent::cpu1.inst 0.050338 # Average percentage of cache occupancy
56system.l2c.occ_percent::cpu1.data 0.070828 # Average percentage of cache occupancy
57system.l2c.occ_percent::total 0.419921 # Average percentage of cache occupancy
58system.l2c.ReadReq_hits::cpu0.dtb.walker 55824 # number of ReadReq hits
59system.l2c.ReadReq_hits::cpu0.itb.walker 5360 # number of ReadReq hits
60system.l2c.ReadReq_hits::cpu0.inst 353946 # number of ReadReq hits
61system.l2c.ReadReq_hits::cpu0.data 138985 # number of ReadReq hits
62system.l2c.ReadReq_hits::cpu1.dtb.walker 116300 # number of ReadReq hits
63system.l2c.ReadReq_hits::cpu1.itb.walker 6415 # number of ReadReq hits
64system.l2c.ReadReq_hits::cpu1.inst 686444 # number of ReadReq hits
65system.l2c.ReadReq_hits::cpu1.data 224154 # number of ReadReq hits
66system.l2c.ReadReq_hits::total 1587428 # number of ReadReq hits
67system.l2c.Writeback_hits::writebacks 602817 # number of Writeback hits
68system.l2c.Writeback_hits::total 602817 # number of Writeback hits
69system.l2c.UpgradeReq_hits::cpu0.data 916 # number of UpgradeReq hits
70system.l2c.UpgradeReq_hits::cpu1.data 896 # number of UpgradeReq hits
71system.l2c.UpgradeReq_hits::total 1812 # number of UpgradeReq hits
72system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits
73system.l2c.SCUpgradeReq_hits::cpu1.data 349 # number of SCUpgradeReq hits
74system.l2c.SCUpgradeReq_hits::total 559 # number of SCUpgradeReq hits
75system.l2c.ReadExReq_hits::cpu0.data 36704 # number of ReadExReq hits
76system.l2c.ReadExReq_hits::cpu1.data 64640 # number of ReadExReq hits
77system.l2c.ReadExReq_hits::total 101344 # number of ReadExReq hits
78system.l2c.demand_hits::cpu0.dtb.walker 55824 # number of demand (read+write) hits
79system.l2c.demand_hits::cpu0.itb.walker 5360 # number of demand (read+write) hits
80system.l2c.demand_hits::cpu0.inst 353946 # number of demand (read+write) hits
81system.l2c.demand_hits::cpu0.data 175689 # number of demand (read+write) hits
82system.l2c.demand_hits::cpu1.dtb.walker 116300 # number of demand (read+write) hits
83system.l2c.demand_hits::cpu1.itb.walker 6415 # number of demand (read+write) hits
84system.l2c.demand_hits::cpu1.inst 686444 # number of demand (read+write) hits
85system.l2c.demand_hits::cpu1.data 288794 # number of demand (read+write) hits
86system.l2c.demand_hits::total 1688772 # number of demand (read+write) hits
87system.l2c.overall_hits::cpu0.dtb.walker 55824 # number of overall hits
88system.l2c.overall_hits::cpu0.itb.walker 5360 # number of overall hits
89system.l2c.overall_hits::cpu0.inst 353946 # number of overall hits
90system.l2c.overall_hits::cpu0.data 175689 # number of overall hits
91system.l2c.overall_hits::cpu1.dtb.walker 116300 # number of overall hits
92system.l2c.overall_hits::cpu1.itb.walker 6415 # number of overall hits
93system.l2c.overall_hits::cpu1.inst 686444 # number of overall hits
94system.l2c.overall_hits::cpu1.data 288794 # number of overall hits
95system.l2c.overall_hits::total 1688772 # number of overall hits
96system.l2c.ReadReq_misses::cpu0.dtb.walker 75 # number of ReadReq misses
97system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses
98system.l2c.ReadReq_misses::cpu0.inst 9410 # number of ReadReq misses
99system.l2c.ReadReq_misses::cpu0.data 9224 # number of ReadReq misses
100system.l2c.ReadReq_misses::cpu1.dtb.walker 52 # number of ReadReq misses
101system.l2c.ReadReq_misses::cpu1.itb.walker 6 # number of ReadReq misses
102system.l2c.ReadReq_misses::cpu1.inst 8908 # number of ReadReq misses
103system.l2c.ReadReq_misses::cpu1.data 12134 # number of ReadReq misses
104system.l2c.ReadReq_misses::total 39813 # number of ReadReq misses
105system.l2c.UpgradeReq_misses::cpu0.data 5335 # number of UpgradeReq misses
106system.l2c.UpgradeReq_misses::cpu1.data 5536 # number of UpgradeReq misses
107system.l2c.UpgradeReq_misses::total 10871 # number of UpgradeReq misses
108system.l2c.SCUpgradeReq_misses::cpu0.data 765 # number of SCUpgradeReq misses
109system.l2c.SCUpgradeReq_misses::cpu1.data 529 # number of SCUpgradeReq misses
110system.l2c.SCUpgradeReq_misses::total 1294 # number of SCUpgradeReq misses
111system.l2c.ReadExReq_misses::cpu0.data 66271 # number of ReadExReq misses
112system.l2c.ReadExReq_misses::cpu1.data 81270 # number of ReadExReq misses
113system.l2c.ReadExReq_misses::total 147541 # number of ReadExReq misses
114system.l2c.demand_misses::cpu0.dtb.walker 75 # number of demand (read+write) misses
115system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses
116system.l2c.demand_misses::cpu0.inst 9410 # number of demand (read+write) misses
117system.l2c.demand_misses::cpu0.data 75495 # number of demand (read+write) misses
118system.l2c.demand_misses::cpu1.dtb.walker 52 # number of demand (read+write) misses
119system.l2c.demand_misses::cpu1.itb.walker 6 # number of demand (read+write) misses
120system.l2c.demand_misses::cpu1.inst 8908 # number of demand (read+write) misses
121system.l2c.demand_misses::cpu1.data 93404 # number of demand (read+write) misses
122system.l2c.demand_misses::total 187354 # number of demand (read+write) misses
123system.l2c.overall_misses::cpu0.dtb.walker 75 # number of overall misses
124system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses
125system.l2c.overall_misses::cpu0.inst 9410 # number of overall misses
126system.l2c.overall_misses::cpu0.data 75495 # number of overall misses
127system.l2c.overall_misses::cpu1.dtb.walker 52 # number of overall misses
128system.l2c.overall_misses::cpu1.itb.walker 6 # number of overall misses
129system.l2c.overall_misses::cpu1.inst 8908 # number of overall misses
130system.l2c.overall_misses::cpu1.data 93404 # number of overall misses
131system.l2c.overall_misses::total 187354 # number of overall misses
132system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 3910000 # number of ReadReq miss cycles
133system.l2c.ReadReq_miss_latency::cpu0.itb.walker 210000 # number of ReadReq miss cycles
134system.l2c.ReadReq_miss_latency::cpu0.inst 492070500 # number of ReadReq miss cycles
135system.l2c.ReadReq_miss_latency::cpu0.data 481346500 # number of ReadReq miss cycles
136system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 2708500 # number of ReadReq miss cycles
137system.l2c.ReadReq_miss_latency::cpu1.itb.walker 312500 # number of ReadReq miss cycles
138system.l2c.ReadReq_miss_latency::cpu1.inst 465974500 # number of ReadReq miss cycles
139system.l2c.ReadReq_miss_latency::cpu1.data 633905500 # number of ReadReq miss cycles
140system.l2c.ReadReq_miss_latency::total 2080438000 # number of ReadReq miss cycles
141system.l2c.UpgradeReq_miss_latency::cpu0.data 18240000 # number of UpgradeReq miss cycles
142system.l2c.UpgradeReq_miss_latency::cpu1.data 37260500 # number of UpgradeReq miss cycles
143system.l2c.UpgradeReq_miss_latency::total 55500500 # number of UpgradeReq miss cycles
144system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2038000 # number of SCUpgradeReq miss cycles
145system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5120000 # number of SCUpgradeReq miss cycles
146system.l2c.SCUpgradeReq_miss_latency::total 7158000 # number of SCUpgradeReq miss cycles
147system.l2c.ReadExReq_miss_latency::cpu0.data 3474892499 # number of ReadExReq miss cycles
148system.l2c.ReadExReq_miss_latency::cpu1.data 4269418500 # number of ReadExReq miss cycles
149system.l2c.ReadExReq_miss_latency::total 7744310999 # number of ReadExReq miss cycles
150system.l2c.demand_miss_latency::cpu0.dtb.walker 3910000 # number of demand (read+write) miss cycles
151system.l2c.demand_miss_latency::cpu0.itb.walker 210000 # number of demand (read+write) miss cycles
152system.l2c.demand_miss_latency::cpu0.inst 492070500 # number of demand (read+write) miss cycles
153system.l2c.demand_miss_latency::cpu0.data 3956238999 # number of demand (read+write) miss cycles
154system.l2c.demand_miss_latency::cpu1.dtb.walker 2708500 # number of demand (read+write) miss cycles
155system.l2c.demand_miss_latency::cpu1.itb.walker 312500 # number of demand (read+write) miss cycles
156system.l2c.demand_miss_latency::cpu1.inst 465974500 # number of demand (read+write) miss cycles
157system.l2c.demand_miss_latency::cpu1.data 4903324000 # number of demand (read+write) miss cycles
158system.l2c.demand_miss_latency::total 9824748999 # number of demand (read+write) miss cycles
159system.l2c.overall_miss_latency::cpu0.dtb.walker 3910000 # number of overall miss cycles
160system.l2c.overall_miss_latency::cpu0.itb.walker 210000 # number of overall miss cycles
161system.l2c.overall_miss_latency::cpu0.inst 492070500 # number of overall miss cycles
162system.l2c.overall_miss_latency::cpu0.data 3956238999 # number of overall miss cycles
163system.l2c.overall_miss_latency::cpu1.dtb.walker 2708500 # number of overall miss cycles
164system.l2c.overall_miss_latency::cpu1.itb.walker 312500 # number of overall miss cycles
165system.l2c.overall_miss_latency::cpu1.inst 465974500 # number of overall miss cycles
166system.l2c.overall_miss_latency::cpu1.data 4903324000 # number of overall miss cycles
167system.l2c.overall_miss_latency::total 9824748999 # number of overall miss cycles
168system.l2c.ReadReq_accesses::cpu0.dtb.walker 55899 # number of ReadReq accesses(hits+misses)
169system.l2c.ReadReq_accesses::cpu0.itb.walker 5364 # number of ReadReq accesses(hits+misses)
170system.l2c.ReadReq_accesses::cpu0.inst 363356 # number of ReadReq accesses(hits+misses)
171system.l2c.ReadReq_accesses::cpu0.data 148209 # number of ReadReq accesses(hits+misses)
172system.l2c.ReadReq_accesses::cpu1.dtb.walker 116352 # number of ReadReq accesses(hits+misses)
173system.l2c.ReadReq_accesses::cpu1.itb.walker 6421 # number of ReadReq accesses(hits+misses)
174system.l2c.ReadReq_accesses::cpu1.inst 695352 # number of ReadReq accesses(hits+misses)
175system.l2c.ReadReq_accesses::cpu1.data 236288 # number of ReadReq accesses(hits+misses)
176system.l2c.ReadReq_accesses::total 1627241 # number of ReadReq accesses(hits+misses)
177system.l2c.Writeback_accesses::writebacks 602817 # number of Writeback accesses(hits+misses)
178system.l2c.Writeback_accesses::total 602817 # number of Writeback accesses(hits+misses)
179system.l2c.UpgradeReq_accesses::cpu0.data 6251 # number of UpgradeReq accesses(hits+misses)
180system.l2c.UpgradeReq_accesses::cpu1.data 6432 # number of UpgradeReq accesses(hits+misses)
181system.l2c.UpgradeReq_accesses::total 12683 # number of UpgradeReq accesses(hits+misses)
182system.l2c.SCUpgradeReq_accesses::cpu0.data 975 # number of SCUpgradeReq accesses(hits+misses)
183system.l2c.SCUpgradeReq_accesses::cpu1.data 878 # number of SCUpgradeReq accesses(hits+misses)
184system.l2c.SCUpgradeReq_accesses::total 1853 # number of SCUpgradeReq accesses(hits+misses)
185system.l2c.ReadExReq_accesses::cpu0.data 102975 # number of ReadExReq accesses(hits+misses)
186system.l2c.ReadExReq_accesses::cpu1.data 145910 # number of ReadExReq accesses(hits+misses)
187system.l2c.ReadExReq_accesses::total 248885 # number of ReadExReq accesses(hits+misses)
188system.l2c.demand_accesses::cpu0.dtb.walker 55899 # number of demand (read+write) accesses
189system.l2c.demand_accesses::cpu0.itb.walker 5364 # number of demand (read+write) accesses
190system.l2c.demand_accesses::cpu0.inst 363356 # number of demand (read+write) accesses
191system.l2c.demand_accesses::cpu0.data 251184 # number of demand (read+write) accesses
192system.l2c.demand_accesses::cpu1.dtb.walker 116352 # number of demand (read+write) accesses
193system.l2c.demand_accesses::cpu1.itb.walker 6421 # number of demand (read+write) accesses
194system.l2c.demand_accesses::cpu1.inst 695352 # number of demand (read+write) accesses
195system.l2c.demand_accesses::cpu1.data 382198 # number of demand (read+write) accesses
196system.l2c.demand_accesses::total 1876126 # number of demand (read+write) accesses
197system.l2c.overall_accesses::cpu0.dtb.walker 55899 # number of overall (read+write) accesses
198system.l2c.overall_accesses::cpu0.itb.walker 5364 # number of overall (read+write) accesses
199system.l2c.overall_accesses::cpu0.inst 363356 # number of overall (read+write) accesses
200system.l2c.overall_accesses::cpu0.data 251184 # number of overall (read+write) accesses
201system.l2c.overall_accesses::cpu1.dtb.walker 116352 # number of overall (read+write) accesses
202system.l2c.overall_accesses::cpu1.itb.walker 6421 # number of overall (read+write) accesses
203system.l2c.overall_accesses::cpu1.inst 695352 # number of overall (read+write) accesses
204system.l2c.overall_accesses::cpu1.data 382198 # number of overall (read+write) accesses
205system.l2c.overall_accesses::total 1876126 # number of overall (read+write) accesses
206system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for ReadReq accesses
207system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000746 # miss rate for ReadReq accesses
208system.l2c.ReadReq_miss_rate::cpu0.inst 0.025897 # miss rate for ReadReq accesses
209system.l2c.ReadReq_miss_rate::cpu0.data 0.062236 # miss rate for ReadReq accesses
210system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000447 # miss rate for ReadReq accesses
211system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000934 # miss rate for ReadReq accesses
212system.l2c.ReadReq_miss_rate::cpu1.inst 0.012811 # miss rate for ReadReq accesses
213system.l2c.ReadReq_miss_rate::cpu1.data 0.051353 # miss rate for ReadReq accesses
214system.l2c.UpgradeReq_miss_rate::cpu0.data 0.853463 # miss rate for UpgradeReq accesses
215system.l2c.UpgradeReq_miss_rate::cpu1.data 0.860697 # miss rate for UpgradeReq accesses
216system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.784615 # miss rate for SCUpgradeReq accesses
217system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.602506 # miss rate for SCUpgradeReq accesses
218system.l2c.ReadExReq_miss_rate::cpu0.data 0.643564 # miss rate for ReadExReq accesses
219system.l2c.ReadExReq_miss_rate::cpu1.data 0.556987 # miss rate for ReadExReq accesses
220system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for demand accesses
221system.l2c.demand_miss_rate::cpu0.itb.walker 0.000746 # miss rate for demand accesses
222system.l2c.demand_miss_rate::cpu0.inst 0.025897 # miss rate for demand accesses
223system.l2c.demand_miss_rate::cpu0.data 0.300557 # miss rate for demand accesses
224system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000447 # miss rate for demand accesses
225system.l2c.demand_miss_rate::cpu1.itb.walker 0.000934 # miss rate for demand accesses
226system.l2c.demand_miss_rate::cpu1.inst 0.012811 # miss rate for demand accesses
227system.l2c.demand_miss_rate::cpu1.data 0.244386 # miss rate for demand accesses
228system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for overall accesses
229system.l2c.overall_miss_rate::cpu0.itb.walker 0.000746 # miss rate for overall accesses
230system.l2c.overall_miss_rate::cpu0.inst 0.025897 # miss rate for overall accesses
231system.l2c.overall_miss_rate::cpu0.data 0.300557 # miss rate for overall accesses
232system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000447 # miss rate for overall accesses
233system.l2c.overall_miss_rate::cpu1.itb.walker 0.000934 # miss rate for overall accesses
234system.l2c.overall_miss_rate::cpu1.inst 0.012811 # miss rate for overall accesses
235system.l2c.overall_miss_rate::cpu1.data 0.244386 # miss rate for overall accesses
236system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52133.333333 # average ReadReq miss latency
237system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52500 # average ReadReq miss latency
238system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52292.295430 # average ReadReq miss latency
239system.l2c.ReadReq_avg_miss_latency::cpu0.data 52184.139202 # average ReadReq miss latency
240system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52086.538462 # average ReadReq miss latency
241system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52083.333333 # average ReadReq miss latency
242system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52309.665469 # average ReadReq miss latency
243system.l2c.ReadReq_avg_miss_latency::cpu1.data 52242.088347 # average ReadReq miss latency
244system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3418.931584 # average UpgradeReq miss latency
245system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6730.581647 # average UpgradeReq miss latency
246system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2664.052288 # average SCUpgradeReq miss latency
247system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9678.638941 # average SCUpgradeReq miss latency
248system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52434.586757 # average ReadExReq miss latency
249system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52533.757844 # average ReadExReq miss latency
250system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52133.333333 # average overall miss latency
251system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52500 # average overall miss latency
252system.l2c.demand_avg_miss_latency::cpu0.inst 52292.295430 # average overall miss latency
253system.l2c.demand_avg_miss_latency::cpu0.data 52403.987006 # average overall miss latency
254system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52086.538462 # average overall miss latency
255system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52083.333333 # average overall miss latency
256system.l2c.demand_avg_miss_latency::cpu1.inst 52309.665469 # average overall miss latency
257system.l2c.demand_avg_miss_latency::cpu1.data 52495.867415 # average overall miss latency
258system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52133.333333 # average overall miss latency
259system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52500 # average overall miss latency
260system.l2c.overall_avg_miss_latency::cpu0.inst 52292.295430 # average overall miss latency
261system.l2c.overall_avg_miss_latency::cpu0.data 52403.987006 # average overall miss latency
262system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52086.538462 # average overall miss latency
263system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52083.333333 # average overall miss latency
264system.l2c.overall_avg_miss_latency::cpu1.inst 52309.665469 # average overall miss latency
265system.l2c.overall_avg_miss_latency::cpu1.data 52495.867415 # average overall miss latency
266system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
267system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
268system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
269system.l2c.blocked::no_targets 0 # number of cycles access was blocked
270system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
271system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
272system.l2c.fast_writes 0 # number of fast writes performed
273system.l2c.cache_copies 0 # number of cache copies performed
274system.l2c.writebacks::writebacks 112135 # number of writebacks
275system.l2c.writebacks::total 112135 # number of writebacks
276system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits
277system.l2c.ReadReq_mshr_hits::cpu0.data 52 # number of ReadReq MSHR hits
278system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits
279system.l2c.ReadReq_mshr_hits::cpu1.inst 14 # number of ReadReq MSHR hits
280system.l2c.ReadReq_mshr_hits::cpu1.data 33 # number of ReadReq MSHR hits
281system.l2c.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits
282system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits
283system.l2c.demand_mshr_hits::cpu0.data 52 # number of demand (read+write) MSHR hits
284system.l2c.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits
285system.l2c.demand_mshr_hits::cpu1.inst 14 # number of demand (read+write) MSHR hits
286system.l2c.demand_mshr_hits::cpu1.data 33 # number of demand (read+write) MSHR hits
287system.l2c.demand_mshr_hits::total 102 # number of demand (read+write) MSHR hits
288system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits
289system.l2c.overall_mshr_hits::cpu0.data 52 # number of overall MSHR hits
290system.l2c.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits
291system.l2c.overall_mshr_hits::cpu1.inst 14 # number of overall MSHR hits
292system.l2c.overall_mshr_hits::cpu1.data 33 # number of overall MSHR hits
293system.l2c.overall_mshr_hits::total 102 # number of overall MSHR hits
294system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 75 # number of ReadReq MSHR misses
295system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 4 # number of ReadReq MSHR misses
296system.l2c.ReadReq_mshr_misses::cpu0.inst 9408 # number of ReadReq MSHR misses
297system.l2c.ReadReq_mshr_misses::cpu0.data 9172 # number of ReadReq MSHR misses
298system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 51 # number of ReadReq MSHR misses
299system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 6 # number of ReadReq MSHR misses
300system.l2c.ReadReq_mshr_misses::cpu1.inst 8894 # number of ReadReq MSHR misses
301system.l2c.ReadReq_mshr_misses::cpu1.data 12101 # number of ReadReq MSHR misses
302system.l2c.ReadReq_mshr_misses::total 39711 # number of ReadReq MSHR misses
303system.l2c.UpgradeReq_mshr_misses::cpu0.data 5335 # number of UpgradeReq MSHR misses
304system.l2c.UpgradeReq_mshr_misses::cpu1.data 5536 # number of UpgradeReq MSHR misses
305system.l2c.UpgradeReq_mshr_misses::total 10871 # number of UpgradeReq MSHR misses
306system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 765 # number of SCUpgradeReq MSHR misses
307system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 529 # number of SCUpgradeReq MSHR misses
308system.l2c.SCUpgradeReq_mshr_misses::total 1294 # number of SCUpgradeReq MSHR misses
309system.l2c.ReadExReq_mshr_misses::cpu0.data 66271 # number of ReadExReq MSHR misses
310system.l2c.ReadExReq_mshr_misses::cpu1.data 81270 # number of ReadExReq MSHR misses
311system.l2c.ReadExReq_mshr_misses::total 147541 # number of ReadExReq MSHR misses
312system.l2c.demand_mshr_misses::cpu0.dtb.walker 75 # number of demand (read+write) MSHR misses
313system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses
314system.l2c.demand_mshr_misses::cpu0.inst 9408 # number of demand (read+write) MSHR misses
315system.l2c.demand_mshr_misses::cpu0.data 75443 # number of demand (read+write) MSHR misses
316system.l2c.demand_mshr_misses::cpu1.dtb.walker 51 # number of demand (read+write) MSHR misses
317system.l2c.demand_mshr_misses::cpu1.itb.walker 6 # number of demand (read+write) MSHR misses
318system.l2c.demand_mshr_misses::cpu1.inst 8894 # number of demand (read+write) MSHR misses
319system.l2c.demand_mshr_misses::cpu1.data 93371 # number of demand (read+write) MSHR misses
320system.l2c.demand_mshr_misses::total 187252 # number of demand (read+write) MSHR misses
321system.l2c.overall_mshr_misses::cpu0.dtb.walker 75 # number of overall MSHR misses
322system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses
323system.l2c.overall_mshr_misses::cpu0.inst 9408 # number of overall MSHR misses
324system.l2c.overall_mshr_misses::cpu0.data 75443 # number of overall MSHR misses
325system.l2c.overall_mshr_misses::cpu1.dtb.walker 51 # number of overall MSHR misses
326system.l2c.overall_mshr_misses::cpu1.itb.walker 6 # number of overall MSHR misses
327system.l2c.overall_mshr_misses::cpu1.inst 8894 # number of overall MSHR misses
328system.l2c.overall_mshr_misses::cpu1.data 93371 # number of overall MSHR misses
329system.l2c.overall_mshr_misses::total 187252 # number of overall MSHR misses
330system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3001500 # number of ReadReq MSHR miss cycles
331system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 162000 # number of ReadReq MSHR miss cycles
332system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 377008500 # number of ReadReq MSHR miss cycles
333system.l2c.ReadReq_mshr_miss_latency::cpu0.data 367415500 # number of ReadReq MSHR miss cycles
334system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 2046500 # number of ReadReq MSHR miss cycles
335system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 240000 # number of ReadReq MSHR miss cycles
336system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 356843500 # number of ReadReq MSHR miss cycles
337system.l2c.ReadReq_mshr_miss_latency::cpu1.data 484732500 # number of ReadReq MSHR miss cycles
338system.l2c.ReadReq_mshr_miss_latency::total 1591450000 # number of ReadReq MSHR miss cycles
339system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 213651500 # number of UpgradeReq MSHR miss cycles
340system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 221567500 # number of UpgradeReq MSHR miss cycles
341system.l2c.UpgradeReq_mshr_miss_latency::total 435219000 # number of UpgradeReq MSHR miss cycles
342system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 30631000 # number of SCUpgradeReq MSHR miss cycles
343system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 21186500 # number of SCUpgradeReq MSHR miss cycles
344system.l2c.SCUpgradeReq_mshr_miss_latency::total 51817500 # number of SCUpgradeReq MSHR miss cycles
345system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2653011999 # number of ReadExReq MSHR miss cycles
346system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3258908000 # number of ReadExReq MSHR miss cycles
347system.l2c.ReadExReq_mshr_miss_latency::total 5911919999 # number of ReadExReq MSHR miss cycles
348system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3001500 # number of demand (read+write) MSHR miss cycles
349system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 162000 # number of demand (read+write) MSHR miss cycles
350system.l2c.demand_mshr_miss_latency::cpu0.inst 377008500 # number of demand (read+write) MSHR miss cycles
351system.l2c.demand_mshr_miss_latency::cpu0.data 3020427499 # number of demand (read+write) MSHR miss cycles
352system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 2046500 # number of demand (read+write) MSHR miss cycles
353system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 240000 # number of demand (read+write) MSHR miss cycles
354system.l2c.demand_mshr_miss_latency::cpu1.inst 356843500 # number of demand (read+write) MSHR miss cycles
355system.l2c.demand_mshr_miss_latency::cpu1.data 3743640500 # number of demand (read+write) MSHR miss cycles
356system.l2c.demand_mshr_miss_latency::total 7503369999 # number of demand (read+write) MSHR miss cycles
357system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3001500 # number of overall MSHR miss cycles
358system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 162000 # number of overall MSHR miss cycles
359system.l2c.overall_mshr_miss_latency::cpu0.inst 377008500 # number of overall MSHR miss cycles
360system.l2c.overall_mshr_miss_latency::cpu0.data 3020427499 # number of overall MSHR miss cycles
361system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2046500 # number of overall MSHR miss cycles
362system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 240000 # number of overall MSHR miss cycles
363system.l2c.overall_mshr_miss_latency::cpu1.inst 356843500 # number of overall MSHR miss cycles
364system.l2c.overall_mshr_miss_latency::cpu1.data 3743640500 # number of overall MSHR miss cycles
365system.l2c.overall_mshr_miss_latency::total 7503369999 # number of overall MSHR miss cycles
366system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5748500 # number of ReadReq MSHR uncacheable cycles
367system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 8468870500 # number of ReadReq MSHR uncacheable cycles
368system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1931000 # number of ReadReq MSHR uncacheable cycles
369system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 123493886000 # number of ReadReq MSHR uncacheable cycles
370system.l2c.ReadReq_mshr_uncacheable_latency::total 131970436000 # number of ReadReq MSHR uncacheable cycles
371system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 744869980 # number of WriteReq MSHR uncacheable cycles
372system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31777552693 # number of WriteReq MSHR uncacheable cycles
373system.l2c.WriteReq_mshr_uncacheable_latency::total 32522422673 # number of WriteReq MSHR uncacheable cycles
374system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5748500 # number of overall MSHR uncacheable cycles
375system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9213740480 # number of overall MSHR uncacheable cycles
376system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1931000 # number of overall MSHR uncacheable cycles
377system.l2c.overall_mshr_uncacheable_latency::cpu1.data 155271438693 # number of overall MSHR uncacheable cycles
378system.l2c.overall_mshr_uncacheable_latency::total 164492858673 # number of overall MSHR uncacheable cycles
379system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001342 # mshr miss rate for ReadReq accesses
380system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000746 # mshr miss rate for ReadReq accesses
381system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.025892 # mshr miss rate for ReadReq accesses
382system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.061886 # mshr miss rate for ReadReq accesses
383system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000438 # mshr miss rate for ReadReq accesses
384system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000934 # mshr miss rate for ReadReq accesses
385system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012791 # mshr miss rate for ReadReq accesses
386system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.051213 # mshr miss rate for ReadReq accesses
387system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.853463 # mshr miss rate for UpgradeReq accesses
388system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.860697 # mshr miss rate for UpgradeReq accesses
389system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784615 # mshr miss rate for SCUpgradeReq accesses
390system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.602506 # mshr miss rate for SCUpgradeReq accesses
391system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.643564 # mshr miss rate for ReadExReq accesses
392system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.556987 # mshr miss rate for ReadExReq accesses
393system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001342 # mshr miss rate for demand accesses
394system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000746 # mshr miss rate for demand accesses
395system.l2c.demand_mshr_miss_rate::cpu0.inst 0.025892 # mshr miss rate for demand accesses
396system.l2c.demand_mshr_miss_rate::cpu0.data 0.300350 # mshr miss rate for demand accesses
397system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000438 # mshr miss rate for demand accesses
398system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000934 # mshr miss rate for demand accesses
399system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012791 # mshr miss rate for demand accesses
400system.l2c.demand_mshr_miss_rate::cpu1.data 0.244300 # mshr miss rate for demand accesses
401system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001342 # mshr miss rate for overall accesses
402system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000746 # mshr miss rate for overall accesses
403system.l2c.overall_mshr_miss_rate::cpu0.inst 0.025892 # mshr miss rate for overall accesses
404system.l2c.overall_mshr_miss_rate::cpu0.data 0.300350 # mshr miss rate for overall accesses
405system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000438 # mshr miss rate for overall accesses
406system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000934 # mshr miss rate for overall accesses
407system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012791 # mshr miss rate for overall accesses
408system.l2c.overall_mshr_miss_rate::cpu1.data 0.244300 # mshr miss rate for overall accesses
409system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40020 # average ReadReq mshr miss latency
410system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40500 # average ReadReq mshr miss latency
411system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40073.182398 # average ReadReq mshr miss latency
412system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40058.384213 # average ReadReq mshr miss latency
413system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40127.450980 # average ReadReq mshr miss latency
414system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency
415system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40121.823701 # average ReadReq mshr miss latency
416system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40057.226675 # average ReadReq mshr miss latency
417system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40047.141518 # average UpgradeReq mshr miss latency
418system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40023.031069 # average UpgradeReq mshr miss latency
419system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.522876 # average SCUpgradeReq mshr miss latency
420system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40050.094518 # average SCUpgradeReq mshr miss latency
421system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.774502 # average ReadExReq mshr miss latency
422system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40099.766211 # average ReadExReq mshr miss latency
423system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40020 # average overall mshr miss latency
424system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40500 # average overall mshr miss latency
425system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40073.182398 # average overall mshr miss latency
426system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40035.888008 # average overall mshr miss latency
427system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40127.450980 # average overall mshr miss latency
428system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
429system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40121.823701 # average overall mshr miss latency
430system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40094.253034 # average overall mshr miss latency
431system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40020 # average overall mshr miss latency
432system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40500 # average overall mshr miss latency
433system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40073.182398 # average overall mshr miss latency
434system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40035.888008 # average overall mshr miss latency
435system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40127.450980 # average overall mshr miss latency
436system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
437system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40121.823701 # average overall mshr miss latency
438system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40094.253034 # average overall mshr miss latency
439system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
440system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
441system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
442system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
443system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
444system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
445system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
446system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
447system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
448system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
449system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
450system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
451system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
452system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
453system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
454system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
455system.cf0.dma_write_txs 0 # Number of DMA write transactions.
456system.cpu0.dtb.inst_hits 0 # ITB inst hits
457system.cpu0.dtb.inst_misses 0 # ITB inst misses
458system.cpu0.dtb.read_hits 7800657 # DTB read hits
459system.cpu0.dtb.read_misses 37871 # DTB read misses
460system.cpu0.dtb.write_hits 4594363 # DTB write hits
461system.cpu0.dtb.write_misses 6405 # DTB write misses
462system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
463system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
464system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
465system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
466system.cpu0.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB
467system.cpu0.dtb.align_faults 4617 # Number of TLB faults due to alignment restrictions
468system.cpu0.dtb.prefetch_faults 245 # Number of TLB faults due to prefetch
469system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
470system.cpu0.dtb.perms_faults 804 # Number of TLB faults due to permissions restrictions
471system.cpu0.dtb.read_accesses 7838528 # DTB read accesses
472system.cpu0.dtb.write_accesses 4600768 # DTB write accesses
473system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
474system.cpu0.dtb.hits 12395020 # DTB hits
475system.cpu0.dtb.misses 44276 # DTB misses
476system.cpu0.dtb.accesses 12439296 # DTB accesses
477system.cpu0.itb.inst_hits 4047811 # ITB inst hits
478system.cpu0.itb.inst_misses 4513 # ITB inst misses
479system.cpu0.itb.read_hits 0 # DTB read hits
480system.cpu0.itb.read_misses 0 # DTB read misses
481system.cpu0.itb.write_hits 0 # DTB write hits
482system.cpu0.itb.write_misses 0 # DTB write misses
483system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
484system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
485system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
486system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
487system.cpu0.itb.flush_entries 1377 # Number of entries that have been flushed from TLB
488system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
489system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
490system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
491system.cpu0.itb.perms_faults 1822 # Number of TLB faults due to permissions restrictions
492system.cpu0.itb.read_accesses 0 # DTB read accesses
493system.cpu0.itb.write_accesses 0 # DTB write accesses
494system.cpu0.itb.inst_accesses 4052324 # ITB inst accesses
495system.cpu0.itb.hits 4047811 # DTB hits
496system.cpu0.itb.misses 4513 # DTB misses
497system.cpu0.itb.accesses 4052324 # DTB accesses
498system.cpu0.numCycles 58217040 # number of cpu cycles simulated
499system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
500system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
501system.cpu0.BPredUnit.lookups 5494906 # Number of BP lookups
502system.cpu0.BPredUnit.condPredicted 4166450 # Number of conditional branches predicted
503system.cpu0.BPredUnit.condIncorrect 326433 # Number of conditional branches incorrect
504system.cpu0.BPredUnit.BTBLookups 3744504 # Number of BTB lookups
505system.cpu0.BPredUnit.BTBHits 2784648 # Number of BTB hits
506system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
507system.cpu0.BPredUnit.usedRAS 487236 # Number of times the RAS was used to get a target.
508system.cpu0.BPredUnit.RASInCorrect 65325 # Number of incorrect RAS predictions.
509system.cpu0.fetch.icacheStallCycles 11075516 # Number of cycles fetch is stalled on an Icache miss
510system.cpu0.fetch.Insts 28672475 # Number of instructions fetch has processed
511system.cpu0.fetch.Branches 5494906 # Number of branches that fetch encountered
512system.cpu0.fetch.predictedBranches 3271884 # Number of branches that fetch has predicted taken
513system.cpu0.fetch.Cycles 6845901 # Number of cycles fetch has run and was not squashing or blocked
514system.cpu0.fetch.SquashCycles 1471988 # Number of cycles fetch has spent squashing
515system.cpu0.fetch.TlbCycles 58967 # Number of cycles fetch has spent waiting for tlb
516system.cpu0.fetch.BlockedCycles 18678527 # Number of cycles fetch has spent blocked
517system.cpu0.fetch.MiscStallCycles 6609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
518system.cpu0.fetch.PendingTrapStallCycles 30991 # Number of stall cycles due to pending traps
519system.cpu0.fetch.PendingQuiesceStallCycles 80316 # Number of stall cycles due to pending quiesce instructions
520system.cpu0.fetch.IcacheWaitRetryStallCycles 217 # Number of stall cycles due to full MSHR
521system.cpu0.fetch.CacheLines 4045687 # Number of cache lines fetched
522system.cpu0.fetch.IcacheSquashes 176720 # Number of outstanding Icache misses that were squashed
523system.cpu0.fetch.ItlbSquashes 3125 # Number of outstanding ITLB misses that were squashed
524system.cpu0.fetch.rateDist::samples 37812790 # Number of instructions fetched each cycle (Total)
525system.cpu0.fetch.rateDist::mean 0.988034 # Number of instructions fetched each cycle (Total)
526system.cpu0.fetch.rateDist::stdev 2.366493 # Number of instructions fetched each cycle (Total)
527system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
528system.cpu0.fetch.rateDist::0 30973406 81.91% 81.91% # Number of instructions fetched each cycle (Total)
529system.cpu0.fetch.rateDist::1 543248 1.44% 83.35% # Number of instructions fetched each cycle (Total)
530system.cpu0.fetch.rateDist::2 812383 2.15% 85.50% # Number of instructions fetched each cycle (Total)
531system.cpu0.fetch.rateDist::3 623093 1.65% 87.15% # Number of instructions fetched each cycle (Total)
532system.cpu0.fetch.rateDist::4 608176 1.61% 88.75% # Number of instructions fetched each cycle (Total)
533system.cpu0.fetch.rateDist::5 518047 1.37% 90.12% # Number of instructions fetched each cycle (Total)
534system.cpu0.fetch.rateDist::6 610247 1.61% 91.74% # Number of instructions fetched each cycle (Total)
535system.cpu0.fetch.rateDist::7 354921 0.94% 92.68% # Number of instructions fetched each cycle (Total)
536system.cpu0.fetch.rateDist::8 2769269 7.32% 100.00% # Number of instructions fetched each cycle (Total)
537system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
538system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
539system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
540system.cpu0.fetch.rateDist::total 37812790 # Number of instructions fetched each cycle (Total)
541system.cpu0.fetch.branchRate 0.094387 # Number of branch fetches per cycle
542system.cpu0.fetch.rate 0.492510 # Number of inst fetches per cycle
543system.cpu0.decode.IdleCycles 11408065 # Number of cycles decode is idle
544system.cpu0.decode.BlockedCycles 18778956 # Number of cycles decode is blocked
545system.cpu0.decode.RunCycles 6151939 # Number of cycles decode is running
546system.cpu0.decode.UnblockCycles 496838 # Number of cycles decode is unblocking
547system.cpu0.decode.SquashCycles 976992 # Number of cycles decode is squashing
548system.cpu0.decode.BranchResolved 873407 # Number of times decode resolved a branch
549system.cpu0.decode.BranchMispred 60147 # Number of times decode detected a branch misprediction
550system.cpu0.decode.DecodedInsts 35984632 # Number of instructions handled by decode
551system.cpu0.decode.SquashedInsts 191719 # Number of squashed instructions handled by decode
552system.cpu0.rename.SquashCycles 976992 # Number of cycles rename is squashing
553system.cpu0.rename.IdleCycles 11949753 # Number of cycles rename is idle
554system.cpu0.rename.BlockCycles 4623091 # Number of cycles rename is blocking
555system.cpu0.rename.serializeStallCycles 12461431 # count of cycles rename stalled for serializing inst
556system.cpu0.rename.RunCycles 6096265 # Number of cycles rename is running
557system.cpu0.rename.UnblockCycles 1705258 # Number of cycles rename is unblocking
558system.cpu0.rename.RenamedInsts 34697309 # Number of instructions processed by rename
559system.cpu0.rename.ROBFullEvents 704 # Number of times rename has blocked due to ROB full
560system.cpu0.rename.IQFullEvents 354137 # Number of times rename has blocked due to IQ full
561system.cpu0.rename.LSQFullEvents 881144 # Number of times rename has blocked due to LSQ full
562system.cpu0.rename.FullRegisterEvents 56 # Number of times there has been no free registers
563system.cpu0.rename.RenamedOperands 34828806 # Number of destination operands rename has renamed
564system.cpu0.rename.RenameLookups 157685767 # Number of register rename lookups that rename has made
565system.cpu0.rename.int_rename_lookups 157645150 # Number of integer rename lookups
566system.cpu0.rename.fp_rename_lookups 40617 # Number of floating rename lookups
567system.cpu0.rename.CommittedMaps 26885345 # Number of HB maps that are committed
568system.cpu0.rename.UndoneMaps 7943461 # Number of HB maps that are undone due to squashing
569system.cpu0.rename.serializingInsts 453210 # count of serializing insts renamed
570system.cpu0.rename.tempSerializingInsts 414972 # count of temporary serializing insts renamed
571system.cpu0.rename.skidInsts 4454682 # count of insts added to the skid buffer
572system.cpu0.memDep0.insertedLoads 6732960 # Number of loads inserted to the mem dependence unit.
573system.cpu0.memDep0.insertedStores 5163615 # Number of stores inserted to the mem dependence unit.
574system.cpu0.memDep0.conflictingLoads 859688 # Number of conflicting loads.
575system.cpu0.memDep0.conflictingStores 866427 # Number of conflicting stores.
576system.cpu0.iq.iqInstsAdded 32711333 # Number of instructions added to the IQ (excludes non-spec)
577system.cpu0.iq.iqNonSpecInstsAdded 727944 # Number of non-speculative instructions added to the IQ
578system.cpu0.iq.iqInstsIssued 32879139 # Number of instructions issued
579system.cpu0.iq.iqSquashedInstsIssued 79039 # Number of squashed instructions issued
580system.cpu0.iq.iqSquashedInstsExamined 5868829 # Number of squashed instructions iterated over during squash; mainly for profiling
581system.cpu0.iq.iqSquashedOperandsExamined 13573267 # Number of squashed operands that are examined and possibly removed from graph
582system.cpu0.iq.iqSquashedNonSpecRemoved 126473 # Number of squashed non-spec instructions that were removed
583system.cpu0.iq.issued_per_cycle::samples 37812790 # Number of insts issued each cycle
584system.cpu0.iq.issued_per_cycle::mean 0.869524 # Number of insts issued each cycle
585system.cpu0.iq.issued_per_cycle::stdev 1.504625 # Number of insts issued each cycle
586system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
587system.cpu0.iq.issued_per_cycle::0 24425873 64.60% 64.60% # Number of insts issued each cycle
588system.cpu0.iq.issued_per_cycle::1 5253388 13.89% 78.49% # Number of insts issued each cycle
589system.cpu0.iq.issued_per_cycle::2 2719158 7.19% 85.68% # Number of insts issued each cycle
590system.cpu0.iq.issued_per_cycle::3 2012461 5.32% 91.00% # Number of insts issued each cycle
591system.cpu0.iq.issued_per_cycle::4 1865520 4.93% 95.94% # Number of insts issued each cycle
592system.cpu0.iq.issued_per_cycle::5 793449 2.10% 98.04% # Number of insts issued each cycle
593system.cpu0.iq.issued_per_cycle::6 530235 1.40% 99.44% # Number of insts issued each cycle
594system.cpu0.iq.issued_per_cycle::7 162331 0.43% 99.87% # Number of insts issued each cycle
595system.cpu0.iq.issued_per_cycle::8 50375 0.13% 100.00% # Number of insts issued each cycle
596system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
597system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
598system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
599system.cpu0.iq.issued_per_cycle::total 37812790 # Number of insts issued each cycle
600system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
601system.cpu0.iq.fu_full::IntAlu 17246 1.80% 1.80% # attempts to use FU when none available
602system.cpu0.iq.fu_full::IntMult 470 0.05% 1.85% # attempts to use FU when none available
603system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available
604system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available
605system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available
606system.cpu0.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available
607system.cpu0.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available
608system.cpu0.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available
609system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available
610system.cpu0.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available
611system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available
612system.cpu0.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available
613system.cpu0.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available
614system.cpu0.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available
615system.cpu0.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available
616system.cpu0.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available
617system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available
618system.cpu0.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available
619system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available
620system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available
621system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available
622system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available
623system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available
624system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available
625system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available
626system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available
627system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available
628system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available
629system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available
630system.cpu0.iq.fu_full::MemRead 745499 77.99% 79.84% # attempts to use FU when none available
631system.cpu0.iq.fu_full::MemWrite 192658 20.16% 100.00% # attempts to use FU when none available
632system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
633system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
634system.cpu0.iq.FU_type_0::No_OpClass 14281 0.04% 0.04% # Type of FU issued
635system.cpu0.iq.FU_type_0::IntAlu 19663366 59.80% 59.85% # Type of FU issued
636system.cpu0.iq.FU_type_0::IntMult 43374 0.13% 59.98% # Type of FU issued
637system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.98% # Type of FU issued
638system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.98% # Type of FU issued
639system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.98% # Type of FU issued
640system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.98% # Type of FU issued
641system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.98% # Type of FU issued
642system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.98% # Type of FU issued
643system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.98% # Type of FU issued
644system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.98% # Type of FU issued
645system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.98% # Type of FU issued
646system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 59.98% # Type of FU issued
647system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.98% # Type of FU issued
648system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.98% # Type of FU issued
649system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 59.98% # Type of FU issued
650system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.98% # Type of FU issued
651system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.98% # Type of FU issued
652system.cpu0.iq.FU_type_0::SimdShift 5 0.00% 59.98% # Type of FU issued
653system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 59.98% # Type of FU issued
654system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.98% # Type of FU issued
655system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.98% # Type of FU issued
656system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.98% # Type of FU issued
657system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.98% # Type of FU issued
658system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.98% # Type of FU issued
659system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.98% # Type of FU issued
660system.cpu0.iq.FU_type_0::SimdFloatMisc 1004 0.00% 59.98% # Type of FU issued
661system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.98% # Type of FU issued
662system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 59.98% # Type of FU issued
663system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.98% # Type of FU issued
664system.cpu0.iq.FU_type_0::MemRead 8245355 25.08% 85.06% # Type of FU issued
665system.cpu0.iq.FU_type_0::MemWrite 4911741 14.94% 100.00% # Type of FU issued
666system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
667system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
668system.cpu0.iq.FU_type_0::total 32879139 # Type of FU issued
669system.cpu0.iq.rate 0.564768 # Inst issue rate
670system.cpu0.iq.fu_busy_cnt 955873 # FU busy when requested
671system.cpu0.iq.fu_busy_rate 0.029072 # FU busy rate (busy events/executed inst)
672system.cpu0.iq.int_inst_queue_reads 104638650 # Number of integer instruction queue reads
673system.cpu0.iq.int_inst_queue_writes 39311978 # Number of integer instruction queue writes
674system.cpu0.iq.int_inst_queue_wakeup_accesses 30147071 # Number of integer instruction queue wakeup accesses
675system.cpu0.iq.fp_inst_queue_reads 10735 # Number of floating instruction queue reads
676system.cpu0.iq.fp_inst_queue_writes 5504 # Number of floating instruction queue writes
677system.cpu0.iq.fp_inst_queue_wakeup_accesses 4409 # Number of floating instruction queue wakeup accesses
678system.cpu0.iq.int_alu_accesses 33814871 # Number of integer alu accesses
679system.cpu0.iq.fp_alu_accesses 5860 # Number of floating point alu accesses
680system.cpu0.iew.lsq.thread0.forwLoads 258705 # Number of loads that had data forwarded from stores
681system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
682system.cpu0.iew.lsq.thread0.squashedLoads 1302867 # Number of loads squashed
683system.cpu0.iew.lsq.thread0.ignoredResponses 3913 # Number of memory responses ignored because the instruction is squashed
684system.cpu0.iew.lsq.thread0.memOrderViolation 9804 # Number of memory ordering violations
685system.cpu0.iew.lsq.thread0.squashedStores 555393 # Number of stores squashed
686system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
687system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
688system.cpu0.iew.lsq.thread0.rescheduledLoads 1948839 # Number of loads that were rescheduled
689system.cpu0.iew.lsq.thread0.cacheBlocked 5274 # Number of times an access to memory failed due to the cache being blocked
690system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
691system.cpu0.iew.iewSquashCycles 976992 # Number of cycles IEW is squashing
692system.cpu0.iew.iewBlockCycles 3526747 # Number of cycles IEW is blocking
693system.cpu0.iew.iewUnblockCycles 77009 # Number of cycles IEW is unblocking
694system.cpu0.iew.iewDispatchedInsts 33493958 # Number of instructions dispatched to IQ
695system.cpu0.iew.iewDispSquashedInsts 132151 # Number of squashed instructions skipped by dispatch
696system.cpu0.iew.iewDispLoadInsts 6732960 # Number of dispatched load instructions
697system.cpu0.iew.iewDispStoreInsts 5163615 # Number of dispatched store instructions
698system.cpu0.iew.iewDispNonSpecInsts 457776 # Number of dispatched non-speculative instructions
699system.cpu0.iew.iewIQFullEvents 36292 # Number of times the IQ has become full, causing a stall
700system.cpu0.iew.iewLSQFullEvents 4432 # Number of times the LSQ has become full, causing a stall
701system.cpu0.iew.memOrderViolationEvents 9804 # Number of memory order violations
702system.cpu0.iew.predictedTakenIncorrect 205792 # Number of branches that were predicted taken incorrectly
703system.cpu0.iew.predictedNotTakenIncorrect 118466 # Number of branches that were predicted not taken incorrectly
704system.cpu0.iew.branchMispredicts 324258 # Number of branch mispredicts detected at execute
705system.cpu0.iew.iewExecutedInsts 32446755 # Number of executed instructions
706system.cpu0.iew.iewExecLoadInsts 8074532 # Number of load instructions executed
707system.cpu0.iew.iewExecSquashedInsts 432384 # Number of squashed instructions skipped in execute
708system.cpu0.iew.exec_swp 0 # number of swp insts executed
709system.cpu0.iew.exec_nop 54681 # number of nop insts executed
710system.cpu0.iew.exec_refs 12932399 # number of memory reference insts executed
711system.cpu0.iew.exec_branches 4282280 # Number of branches executed
712system.cpu0.iew.exec_stores 4857867 # Number of stores executed
713system.cpu0.iew.exec_rate 0.557341 # Inst execution rate
714system.cpu0.iew.wb_sent 32234818 # cumulative count of insts sent to commit
715system.cpu0.iew.wb_count 30151480 # cumulative count of insts written-back
716system.cpu0.iew.wb_producers 16076835 # num instructions producing a value
717system.cpu0.iew.wb_consumers 31416355 # num instructions consuming a value
718system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
719system.cpu0.iew.wb_rate 0.517915 # insts written-back per cycle
720system.cpu0.iew.wb_fanout 0.511735 # average fanout of values written-back
721system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
722system.cpu0.commit.commitCommittedInsts 20629504 # The number of committed instructions
723system.cpu0.commit.commitCommittedOps 27347391 # The number of committed instructions
724system.cpu0.commit.commitSquashedInsts 5995379 # The number of squashed insts skipped by commit
725system.cpu0.commit.commitNonSpecStalls 601471 # The number of times commit has been forced to stall to communicate backwards
726system.cpu0.commit.branchMispredicts 285121 # The number of times a branch was mispredicted
727system.cpu0.commit.committed_per_cycle::samples 36866578 # Number of insts commited each cycle
728system.cpu0.commit.committed_per_cycle::mean 0.741794 # Number of insts commited each cycle
729system.cpu0.commit.committed_per_cycle::stdev 1.700144 # Number of insts commited each cycle
730system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
731system.cpu0.commit.committed_per_cycle::0 26502705 71.89% 71.89% # Number of insts commited each cycle
732system.cpu0.commit.committed_per_cycle::1 5217604 14.15% 86.04% # Number of insts commited each cycle
733system.cpu0.commit.committed_per_cycle::2 1684301 4.57% 90.61% # Number of insts commited each cycle
734system.cpu0.commit.committed_per_cycle::3 813710 2.21% 92.82% # Number of insts commited each cycle
735system.cpu0.commit.committed_per_cycle::4 652862 1.77% 94.59% # Number of insts commited each cycle
736system.cpu0.commit.committed_per_cycle::5 391356 1.06% 95.65% # Number of insts commited each cycle
737system.cpu0.commit.committed_per_cycle::6 444768 1.21% 96.86% # Number of insts commited each cycle
738system.cpu0.commit.committed_per_cycle::7 190957 0.52% 97.37% # Number of insts commited each cycle
739system.cpu0.commit.committed_per_cycle::8 968315 2.63% 100.00% # Number of insts commited each cycle
740system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
741system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
742system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
743system.cpu0.commit.committed_per_cycle::total 36866578 # Number of insts commited each cycle
744system.cpu0.commit.committedInsts 20629504 # Number of instructions committed
745system.cpu0.commit.committedOps 27347391 # Number of ops (including micro ops) committed
746system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
747system.cpu0.commit.refs 10038315 # Number of memory references committed
748system.cpu0.commit.loads 5430093 # Number of loads committed
749system.cpu0.commit.membars 201113 # Number of memory barriers committed
750system.cpu0.commit.branches 3777887 # Number of branches committed
751system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions.
752system.cpu0.commit.int_insts 24270652 # Number of committed integer instructions.
753system.cpu0.commit.function_calls 441072 # Number of function calls committed.
754system.cpu0.commit.bw_lim_events 968315 # number cycles where commit BW limit reached
755system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
756system.cpu0.rob.rob_reads 68594693 # The number of ROB reads
757system.cpu0.rob.rob_writes 67665332 # The number of ROB writes
758system.cpu0.timesIdled 379309 # Number of times that the entire CPU went into an idle state and unscheduled itself
759system.cpu0.idleCycles 20404250 # Total number of cycles that the CPU has spent unscheduled due to idling
760system.cpu0.quiesceCycles 5085681345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
761system.cpu0.committedInsts 20604950 # Number of Instructions Simulated
762system.cpu0.committedOps 27322837 # Number of Ops (including micro ops) Simulated
763system.cpu0.committedInsts_total 20604950 # Number of Instructions Simulated
764system.cpu0.cpi 2.825391 # CPI: Cycles Per Instruction
765system.cpu0.cpi_total 2.825391 # CPI: Total CPI of All Threads
766system.cpu0.ipc 0.353933 # IPC: Instructions Per Cycle
767system.cpu0.ipc_total 0.353933 # IPC: Total IPC of All Threads
768system.cpu0.int_regfile_reads 151241601 # number of integer regfile reads
769system.cpu0.int_regfile_writes 29619273 # number of integer regfile writes
770system.cpu0.fp_regfile_reads 4540 # number of floating regfile reads
771system.cpu0.fp_regfile_writes 420 # number of floating regfile writes
772system.cpu0.misc_regfile_reads 40596238 # number of misc regfile reads
773system.cpu0.misc_regfile_writes 457019 # number of misc regfile writes
774system.cpu0.icache.replacements 364224 # number of replacements
775system.cpu0.icache.tagsinuse 511.052791 # Cycle average of tags in use
776system.cpu0.icache.total_refs 3649617 # Total number of references to valid blocks.
777system.cpu0.icache.sampled_refs 364736 # Sample count of references to valid blocks.
778system.cpu0.icache.avg_refs 10.006188 # Average number of references to valid blocks.
779system.cpu0.icache.warmup_cycle 6333280000 # Cycle when the warmup percentage was hit.
780system.cpu0.icache.occ_blocks::cpu0.inst 511.052791 # Average occupied blocks per requestor
781system.cpu0.icache.occ_percent::cpu0.inst 0.998150 # Average percentage of cache occupancy
782system.cpu0.icache.occ_percent::total 0.998150 # Average percentage of cache occupancy
783system.cpu0.icache.ReadReq_hits::cpu0.inst 3649617 # number of ReadReq hits
784system.cpu0.icache.ReadReq_hits::total 3649617 # number of ReadReq hits
785system.cpu0.icache.demand_hits::cpu0.inst 3649617 # number of demand (read+write) hits
786system.cpu0.icache.demand_hits::total 3649617 # number of demand (read+write) hits
787system.cpu0.icache.overall_hits::cpu0.inst 3649617 # number of overall hits
788system.cpu0.icache.overall_hits::total 3649617 # number of overall hits
789system.cpu0.icache.ReadReq_misses::cpu0.inst 395923 # number of ReadReq misses
790system.cpu0.icache.ReadReq_misses::total 395923 # number of ReadReq misses
791system.cpu0.icache.demand_misses::cpu0.inst 395923 # number of demand (read+write) misses
792system.cpu0.icache.demand_misses::total 395923 # number of demand (read+write) misses
793system.cpu0.icache.overall_misses::cpu0.inst 395923 # number of overall misses
794system.cpu0.icache.overall_misses::total 395923 # number of overall misses
795system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6038304987 # number of ReadReq miss cycles
796system.cpu0.icache.ReadReq_miss_latency::total 6038304987 # number of ReadReq miss cycles
797system.cpu0.icache.demand_miss_latency::cpu0.inst 6038304987 # number of demand (read+write) miss cycles
798system.cpu0.icache.demand_miss_latency::total 6038304987 # number of demand (read+write) miss cycles
799system.cpu0.icache.overall_miss_latency::cpu0.inst 6038304987 # number of overall miss cycles
800system.cpu0.icache.overall_miss_latency::total 6038304987 # number of overall miss cycles
801system.cpu0.icache.ReadReq_accesses::cpu0.inst 4045540 # number of ReadReq accesses(hits+misses)
802system.cpu0.icache.ReadReq_accesses::total 4045540 # number of ReadReq accesses(hits+misses)
803system.cpu0.icache.demand_accesses::cpu0.inst 4045540 # number of demand (read+write) accesses
804system.cpu0.icache.demand_accesses::total 4045540 # number of demand (read+write) accesses
805system.cpu0.icache.overall_accesses::cpu0.inst 4045540 # number of overall (read+write) accesses
806system.cpu0.icache.overall_accesses::total 4045540 # number of overall (read+write) accesses
807system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097867 # miss rate for ReadReq accesses
808system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097867 # miss rate for demand accesses
809system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097867 # miss rate for overall accesses
810system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15251.210430 # average ReadReq miss latency
811system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15251.210430 # average overall miss latency
812system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15251.210430 # average overall miss latency
813system.cpu0.icache.blocked_cycles::no_mshrs 1459990 # number of cycles access was blocked
814system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
815system.cpu0.icache.blocked::no_mshrs 197 # number of cycles access was blocked
816system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
817system.cpu0.icache.avg_blocked_cycles::no_mshrs 7411.116751 # average number of cycles each access was blocked
818system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
819system.cpu0.icache.fast_writes 0 # number of fast writes performed
820system.cpu0.icache.cache_copies 0 # number of cache copies performed
821system.cpu0.icache.writebacks::writebacks 18468 # number of writebacks
822system.cpu0.icache.writebacks::total 18468 # number of writebacks
823system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31062 # number of ReadReq MSHR hits
824system.cpu0.icache.ReadReq_mshr_hits::total 31062 # number of ReadReq MSHR hits
825system.cpu0.icache.demand_mshr_hits::cpu0.inst 31062 # number of demand (read+write) MSHR hits
826system.cpu0.icache.demand_mshr_hits::total 31062 # number of demand (read+write) MSHR hits
827system.cpu0.icache.overall_mshr_hits::cpu0.inst 31062 # number of overall MSHR hits
828system.cpu0.icache.overall_mshr_hits::total 31062 # number of overall MSHR hits
829system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 364861 # number of ReadReq MSHR misses
830system.cpu0.icache.ReadReq_mshr_misses::total 364861 # number of ReadReq MSHR misses
831system.cpu0.icache.demand_mshr_misses::cpu0.inst 364861 # number of demand (read+write) MSHR misses
832system.cpu0.icache.demand_mshr_misses::total 364861 # number of demand (read+write) MSHR misses
833system.cpu0.icache.overall_mshr_misses::cpu0.inst 364861 # number of overall MSHR misses
834system.cpu0.icache.overall_mshr_misses::total 364861 # number of overall MSHR misses
835system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4524888490 # number of ReadReq MSHR miss cycles
836system.cpu0.icache.ReadReq_mshr_miss_latency::total 4524888490 # number of ReadReq MSHR miss cycles
837system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4524888490 # number of demand (read+write) MSHR miss cycles
838system.cpu0.icache.demand_mshr_miss_latency::total 4524888490 # number of demand (read+write) MSHR miss cycles
839system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4524888490 # number of overall MSHR miss cycles
840system.cpu0.icache.overall_mshr_miss_latency::total 4524888490 # number of overall MSHR miss cycles
841system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7723000 # number of ReadReq MSHR uncacheable cycles
842system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7723000 # number of ReadReq MSHR uncacheable cycles
843system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7723000 # number of overall MSHR uncacheable cycles
844system.cpu0.icache.overall_mshr_uncacheable_latency::total 7723000 # number of overall MSHR uncacheable cycles
845system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090188 # mshr miss rate for ReadReq accesses
846system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090188 # mshr miss rate for demand accesses
847system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090188 # mshr miss rate for overall accesses
848system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12401.677598 # average ReadReq mshr miss latency
849system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12401.677598 # average overall mshr miss latency
850system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12401.677598 # average overall mshr miss latency
851system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
852system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
853system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
854system.cpu0.dcache.replacements 240566 # number of replacements
855system.cpu0.dcache.tagsinuse 465.688994 # Cycle average of tags in use
856system.cpu0.dcache.total_refs 8072207 # Total number of references to valid blocks.
857system.cpu0.dcache.sampled_refs 240949 # Sample count of references to valid blocks.
858system.cpu0.dcache.avg_refs 33.501724 # Average number of references to valid blocks.
859system.cpu0.dcache.warmup_cycle 49733000 # Cycle when the warmup percentage was hit.
860system.cpu0.dcache.occ_blocks::cpu0.data 465.688994 # Average occupied blocks per requestor
861system.cpu0.dcache.occ_percent::cpu0.data 0.909549 # Average percentage of cache occupancy
862system.cpu0.dcache.occ_percent::total 0.909549 # Average percentage of cache occupancy
863system.cpu0.dcache.ReadReq_hits::cpu0.data 5008601 # number of ReadReq hits
864system.cpu0.dcache.ReadReq_hits::total 5008601 # number of ReadReq hits
865system.cpu0.dcache.WriteReq_hits::cpu0.data 2710702 # number of WriteReq hits
866system.cpu0.dcache.WriteReq_hits::total 2710702 # number of WriteReq hits
867system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 158809 # number of LoadLockedReq hits
868system.cpu0.dcache.LoadLockedReq_hits::total 158809 # number of LoadLockedReq hits
869system.cpu0.dcache.StoreCondReq_hits::cpu0.data 156314 # number of StoreCondReq hits
870system.cpu0.dcache.StoreCondReq_hits::total 156314 # number of StoreCondReq hits
871system.cpu0.dcache.demand_hits::cpu0.data 7719303 # number of demand (read+write) hits
872system.cpu0.dcache.demand_hits::total 7719303 # number of demand (read+write) hits
873system.cpu0.dcache.overall_hits::cpu0.data 7719303 # number of overall hits
874system.cpu0.dcache.overall_hits::total 7719303 # number of overall hits
875system.cpu0.dcache.ReadReq_misses::cpu0.data 337108 # number of ReadReq misses
876system.cpu0.dcache.ReadReq_misses::total 337108 # number of ReadReq misses
877system.cpu0.dcache.WriteReq_misses::cpu0.data 1466456 # number of WriteReq misses
878system.cpu0.dcache.WriteReq_misses::total 1466456 # number of WriteReq misses
879system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8650 # number of LoadLockedReq misses
880system.cpu0.dcache.LoadLockedReq_misses::total 8650 # number of LoadLockedReq misses
881system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7736 # number of StoreCondReq misses
882system.cpu0.dcache.StoreCondReq_misses::total 7736 # number of StoreCondReq misses
883system.cpu0.dcache.demand_misses::cpu0.data 1803564 # number of demand (read+write) misses
884system.cpu0.dcache.demand_misses::total 1803564 # number of demand (read+write) misses
885system.cpu0.dcache.overall_misses::cpu0.data 1803564 # number of overall misses
886system.cpu0.dcache.overall_misses::total 1803564 # number of overall misses
887system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4776619000 # number of ReadReq miss cycles
888system.cpu0.dcache.ReadReq_miss_latency::total 4776619000 # number of ReadReq miss cycles
889system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60194469903 # number of WriteReq miss cycles
890system.cpu0.dcache.WriteReq_miss_latency::total 60194469903 # number of WriteReq miss cycles
891system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98955000 # number of LoadLockedReq miss cycles
892system.cpu0.dcache.LoadLockedReq_miss_latency::total 98955000 # number of LoadLockedReq miss cycles
893system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 83321000 # number of StoreCondReq miss cycles
894system.cpu0.dcache.StoreCondReq_miss_latency::total 83321000 # number of StoreCondReq miss cycles
895system.cpu0.dcache.demand_miss_latency::cpu0.data 64971088903 # number of demand (read+write) miss cycles
896system.cpu0.dcache.demand_miss_latency::total 64971088903 # number of demand (read+write) miss cycles
897system.cpu0.dcache.overall_miss_latency::cpu0.data 64971088903 # number of overall miss cycles
898system.cpu0.dcache.overall_miss_latency::total 64971088903 # number of overall miss cycles
899system.cpu0.dcache.ReadReq_accesses::cpu0.data 5345709 # number of ReadReq accesses(hits+misses)
900system.cpu0.dcache.ReadReq_accesses::total 5345709 # number of ReadReq accesses(hits+misses)
901system.cpu0.dcache.WriteReq_accesses::cpu0.data 4177158 # number of WriteReq accesses(hits+misses)
902system.cpu0.dcache.WriteReq_accesses::total 4177158 # number of WriteReq accesses(hits+misses)
903system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 167459 # number of LoadLockedReq accesses(hits+misses)
904system.cpu0.dcache.LoadLockedReq_accesses::total 167459 # number of LoadLockedReq accesses(hits+misses)
905system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 164050 # number of StoreCondReq accesses(hits+misses)
906system.cpu0.dcache.StoreCondReq_accesses::total 164050 # number of StoreCondReq accesses(hits+misses)
907system.cpu0.dcache.demand_accesses::cpu0.data 9522867 # number of demand (read+write) accesses
908system.cpu0.dcache.demand_accesses::total 9522867 # number of demand (read+write) accesses
909system.cpu0.dcache.overall_accesses::cpu0.data 9522867 # number of overall (read+write) accesses
910system.cpu0.dcache.overall_accesses::total 9522867 # number of overall (read+write) accesses
911system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063061 # miss rate for ReadReq accesses
912system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.351065 # miss rate for WriteReq accesses
913system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051654 # miss rate for LoadLockedReq accesses
914system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047156 # miss rate for StoreCondReq accesses
915system.cpu0.dcache.demand_miss_rate::cpu0.data 0.189393 # miss rate for demand accesses
916system.cpu0.dcache.overall_miss_rate::cpu0.data 0.189393 # miss rate for overall accesses
917system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14169.402684 # average ReadReq miss latency
918system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41047.579950 # average WriteReq miss latency
919system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11439.884393 # average LoadLockedReq miss latency
920system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10770.553257 # average StoreCondReq miss latency
921system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36023.722420 # average overall miss latency
922system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36023.722420 # average overall miss latency
923system.cpu0.dcache.blocked_cycles::no_mshrs 4293490 # number of cycles access was blocked
924system.cpu0.dcache.blocked_cycles::no_targets 2319000 # number of cycles access was blocked
925system.cpu0.dcache.blocked::no_mshrs 358 # number of cycles access was blocked
926system.cpu0.dcache.blocked::no_targets 107 # number of cycles access was blocked
927system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11992.988827 # average number of cycles each access was blocked
928system.cpu0.dcache.avg_blocked_cycles::no_targets 21672.897196 # average number of cycles each access was blocked
929system.cpu0.dcache.fast_writes 0 # number of fast writes performed
930system.cpu0.dcache.cache_copies 0 # number of cache copies performed
931system.cpu0.dcache.writebacks::writebacks 213312 # number of writebacks
932system.cpu0.dcache.writebacks::total 213312 # number of writebacks
933system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 173688 # number of ReadReq MSHR hits
934system.cpu0.dcache.ReadReq_mshr_hits::total 173688 # number of ReadReq MSHR hits
935system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1346623 # number of WriteReq MSHR hits
936system.cpu0.dcache.WriteReq_mshr_hits::total 1346623 # number of WriteReq MSHR hits
937system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 614 # number of LoadLockedReq MSHR hits
938system.cpu0.dcache.LoadLockedReq_mshr_hits::total 614 # number of LoadLockedReq MSHR hits
939system.cpu0.dcache.demand_mshr_hits::cpu0.data 1520311 # number of demand (read+write) MSHR hits
940system.cpu0.dcache.demand_mshr_hits::total 1520311 # number of demand (read+write) MSHR hits
941system.cpu0.dcache.overall_mshr_hits::cpu0.data 1520311 # number of overall MSHR hits
942system.cpu0.dcache.overall_mshr_hits::total 1520311 # number of overall MSHR hits
943system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 163420 # number of ReadReq MSHR misses
944system.cpu0.dcache.ReadReq_mshr_misses::total 163420 # number of ReadReq MSHR misses
945system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119833 # number of WriteReq MSHR misses
946system.cpu0.dcache.WriteReq_mshr_misses::total 119833 # number of WriteReq MSHR misses
947system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8036 # number of LoadLockedReq MSHR misses
948system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8036 # number of LoadLockedReq MSHR misses
949system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7735 # number of StoreCondReq MSHR misses
950system.cpu0.dcache.StoreCondReq_mshr_misses::total 7735 # number of StoreCondReq MSHR misses
951system.cpu0.dcache.demand_mshr_misses::cpu0.data 283253 # number of demand (read+write) MSHR misses
952system.cpu0.dcache.demand_mshr_misses::total 283253 # number of demand (read+write) MSHR misses
953system.cpu0.dcache.overall_mshr_misses::cpu0.data 283253 # number of overall MSHR misses
954system.cpu0.dcache.overall_mshr_misses::total 283253 # number of overall MSHR misses
955system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2117873500 # number of ReadReq MSHR miss cycles
956system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2117873500 # number of ReadReq MSHR miss cycles
957system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4308779989 # number of WriteReq MSHR miss cycles
958system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4308779989 # number of WriteReq MSHR miss cycles
959system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66427000 # number of LoadLockedReq MSHR miss cycles
960system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66427000 # number of LoadLockedReq MSHR miss cycles
961system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 60070500 # number of StoreCondReq MSHR miss cycles
962system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 60070500 # number of StoreCondReq MSHR miss cycles
963system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
964system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
965system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6426653489 # number of demand (read+write) MSHR miss cycles
966system.cpu0.dcache.demand_mshr_miss_latency::total 6426653489 # number of demand (read+write) MSHR miss cycles
967system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6426653489 # number of overall MSHR miss cycles
968system.cpu0.dcache.overall_mshr_miss_latency::total 6426653489 # number of overall MSHR miss cycles
969system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9482117000 # number of ReadReq MSHR uncacheable cycles
970system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9482117000 # number of ReadReq MSHR uncacheable cycles
971system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 884866891 # number of WriteReq MSHR uncacheable cycles
972system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 884866891 # number of WriteReq MSHR uncacheable cycles
973system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10366983891 # number of overall MSHR uncacheable cycles
974system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10366983891 # number of overall MSHR uncacheable cycles
975system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030570 # mshr miss rate for ReadReq accesses
976system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028688 # mshr miss rate for WriteReq accesses
977system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.047988 # mshr miss rate for LoadLockedReq accesses
978system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047150 # mshr miss rate for StoreCondReq accesses
979system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029745 # mshr miss rate for demand accesses
980system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029745 # mshr miss rate for overall accesses
981system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12959.695876 # average ReadReq mshr miss latency
982system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35956.539426 # average WriteReq mshr miss latency
983system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8266.177203 # average LoadLockedReq mshr miss latency
984system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7766.063348 # average StoreCondReq mshr miss latency
985system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
986system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22688.739357 # average overall mshr miss latency
987system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22688.739357 # average overall mshr miss latency
988system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
989system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
990system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
991system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
992system.cpu1.dtb.inst_hits 0 # ITB inst hits
993system.cpu1.dtb.inst_misses 0 # ITB inst misses
994system.cpu1.dtb.read_hits 44928224 # DTB read hits
995system.cpu1.dtb.read_misses 73602 # DTB read misses
996system.cpu1.dtb.write_hits 7780505 # DTB write hits
997system.cpu1.dtb.write_misses 20150 # DTB write misses
998system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
999system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1000system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1001system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1002system.cpu1.dtb.flush_entries 2631 # Number of entries that have been flushed from TLB
1003system.cpu1.dtb.align_faults 7056 # Number of TLB faults due to alignment restrictions
1004system.cpu1.dtb.prefetch_faults 592 # Number of TLB faults due to prefetch
1005system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1006system.cpu1.dtb.perms_faults 1808 # Number of TLB faults due to permissions restrictions
1007system.cpu1.dtb.read_accesses 45001826 # DTB read accesses
1008system.cpu1.dtb.write_accesses 7800655 # DTB write accesses
1009system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1010system.cpu1.dtb.hits 52708729 # DTB hits
1011system.cpu1.dtb.misses 93752 # DTB misses
1012system.cpu1.dtb.accesses 52802481 # DTB accesses
1013system.cpu1.itb.inst_hits 10224529 # ITB inst hits
1014system.cpu1.itb.inst_misses 7346 # ITB inst misses
1015system.cpu1.itb.read_hits 0 # DTB read hits
1016system.cpu1.itb.read_misses 0 # DTB read misses
1017system.cpu1.itb.write_hits 0 # DTB write hits
1018system.cpu1.itb.write_misses 0 # DTB write misses
1019system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
1020system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1021system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1022system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1023system.cpu1.itb.flush_entries 1545 # Number of entries that have been flushed from TLB
1024system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1025system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1026system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1027system.cpu1.itb.perms_faults 4985 # Number of TLB faults due to permissions restrictions
1028system.cpu1.itb.read_accesses 0 # DTB read accesses
1029system.cpu1.itb.write_accesses 0 # DTB write accesses
1030system.cpu1.itb.inst_accesses 10231875 # ITB inst accesses
1031system.cpu1.itb.hits 10224529 # DTB hits
1032system.cpu1.itb.misses 7346 # DTB misses
1033system.cpu1.itb.accesses 10231875 # DTB accesses
1034system.cpu1.numCycles 361675233 # number of cpu cycles simulated
1035system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1036system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1037system.cpu1.BPredUnit.lookups 10827639 # Number of BP lookups
1038system.cpu1.BPredUnit.condPredicted 8483405 # Number of conditional branches predicted
1039system.cpu1.BPredUnit.condIncorrect 651414 # Number of conditional branches incorrect
1040system.cpu1.BPredUnit.BTBLookups 7693556 # Number of BTB lookups
1041system.cpu1.BPredUnit.BTBHits 6128118 # Number of BTB hits
1042system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1043system.cpu1.BPredUnit.usedRAS 880194 # Number of times the RAS was used to get a target.
1044system.cpu1.BPredUnit.RASInCorrect 140008 # Number of incorrect RAS predictions.
1045system.cpu1.fetch.icacheStallCycles 23684849 # Number of cycles fetch is stalled on an Icache miss
1046system.cpu1.fetch.Insts 77430542 # Number of instructions fetch has processed
1047system.cpu1.fetch.Branches 10827639 # Number of branches that fetch encountered
1048system.cpu1.fetch.predictedBranches 7008312 # Number of branches that fetch has predicted taken
1049system.cpu1.fetch.Cycles 16767403 # Number of cycles fetch has run and was not squashing or blocked
1050system.cpu1.fetch.SquashCycles 5372389 # Number of cycles fetch has spent squashing
1051system.cpu1.fetch.TlbCycles 95383 # Number of cycles fetch has spent waiting for tlb
1052system.cpu1.fetch.BlockedCycles 76264591 # Number of cycles fetch has spent blocked
1053system.cpu1.fetch.MiscStallCycles 5418 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1054system.cpu1.fetch.PendingTrapStallCycles 105344 # Number of stall cycles due to pending traps
1055system.cpu1.fetch.PendingQuiesceStallCycles 159017 # Number of stall cycles due to pending quiesce instructions
1056system.cpu1.fetch.IcacheWaitRetryStallCycles 209 # Number of stall cycles due to full MSHR
1057system.cpu1.fetch.CacheLines 10219281 # Number of cache lines fetched
1058system.cpu1.fetch.IcacheSquashes 840043 # Number of outstanding Icache misses that were squashed
1059system.cpu1.fetch.ItlbSquashes 3905 # Number of outstanding ITLB misses that were squashed
1060system.cpu1.fetch.rateDist::samples 120738841 # Number of instructions fetched each cycle (Total)
1061system.cpu1.fetch.rateDist::mean 0.782294 # Number of instructions fetched each cycle (Total)
1062system.cpu1.fetch.rateDist::stdev 2.150601 # Number of instructions fetched each cycle (Total)
1063system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1064system.cpu1.fetch.rateDist::0 103983967 86.12% 86.12% # Number of instructions fetched each cycle (Total)
1065system.cpu1.fetch.rateDist::1 1000458 0.83% 86.95% # Number of instructions fetched each cycle (Total)
1066system.cpu1.fetch.rateDist::2 1336299 1.11% 88.06% # Number of instructions fetched each cycle (Total)
1067system.cpu1.fetch.rateDist::3 2219256 1.84% 89.90% # Number of instructions fetched each cycle (Total)
1068system.cpu1.fetch.rateDist::4 1499731 1.24% 91.14% # Number of instructions fetched each cycle (Total)
1069system.cpu1.fetch.rateDist::5 782401 0.65% 91.79% # Number of instructions fetched each cycle (Total)
1070system.cpu1.fetch.rateDist::6 2303716 1.91% 93.69% # Number of instructions fetched each cycle (Total)
1071system.cpu1.fetch.rateDist::7 514923 0.43% 94.12% # Number of instructions fetched each cycle (Total)
1072system.cpu1.fetch.rateDist::8 7098090 5.88% 100.00% # Number of instructions fetched each cycle (Total)
1073system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1074system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1075system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1076system.cpu1.fetch.rateDist::total 120738841 # Number of instructions fetched each cycle (Total)
1077system.cpu1.fetch.branchRate 0.029937 # Number of branch fetches per cycle
1078system.cpu1.fetch.rate 0.214089 # Number of inst fetches per cycle
1079system.cpu1.decode.IdleCycles 25308158 # Number of cycles decode is idle
1080system.cpu1.decode.BlockedCycles 76213029 # Number of cycles decode is blocked
1081system.cpu1.decode.RunCycles 15039933 # Number of cycles decode is running
1082system.cpu1.decode.UnblockCycles 636285 # Number of cycles decode is unblocking
1083system.cpu1.decode.SquashCycles 3541436 # Number of cycles decode is squashing
1084system.cpu1.decode.BranchResolved 1506236 # Number of times decode resolved a branch
1085system.cpu1.decode.BranchMispred 117566 # Number of times decode detected a branch misprediction
1086system.cpu1.decode.DecodedInsts 87857465 # Number of instructions handled by decode
1087system.cpu1.decode.SquashedInsts 382082 # Number of squashed instructions handled by decode
1088system.cpu1.rename.SquashCycles 3541436 # Number of cycles rename is squashing
1089system.cpu1.rename.IdleCycles 26899042 # Number of cycles rename is idle
1090system.cpu1.rename.BlockCycles 32453857 # Number of cycles rename is blocking
1091system.cpu1.rename.serializeStallCycles 39247498 # count of cycles rename stalled for serializing inst
1092system.cpu1.rename.RunCycles 14094152 # Number of cycles rename is running
1093system.cpu1.rename.UnblockCycles 4502856 # Number of cycles rename is unblocking
1094system.cpu1.rename.RenamedInsts 81303435 # Number of instructions processed by rename
1095system.cpu1.rename.ROBFullEvents 2397 # Number of times rename has blocked due to ROB full
1096system.cpu1.rename.IQFullEvents 630313 # Number of times rename has blocked due to IQ full
1097system.cpu1.rename.LSQFullEvents 3163900 # Number of times rename has blocked due to LSQ full
1098system.cpu1.rename.FullRegisterEvents 46270 # Number of times there has been no free registers
1099system.cpu1.rename.RenamedOperands 85880003 # Number of destination operands rename has renamed
1100system.cpu1.rename.RenameLookups 375960450 # Number of register rename lookups that rename has made
1101system.cpu1.rename.int_rename_lookups 375911455 # Number of integer rename lookups
1102system.cpu1.rename.fp_rename_lookups 48995 # Number of floating rename lookups
1103system.cpu1.rename.CommittedMaps 53654703 # Number of HB maps that are committed
1104system.cpu1.rename.UndoneMaps 32225299 # Number of HB maps that are undone due to squashing
1105system.cpu1.rename.serializingInsts 777903 # count of serializing insts renamed
1106system.cpu1.rename.tempSerializingInsts 702371 # count of temporary serializing insts renamed
1107system.cpu1.rename.skidInsts 8742657 # count of insts added to the skid buffer
1108system.cpu1.memDep0.insertedLoads 15637648 # Number of loads inserted to the mem dependence unit.
1109system.cpu1.memDep0.insertedStores 9415892 # Number of stores inserted to the mem dependence unit.
1110system.cpu1.memDep0.conflictingLoads 1206366 # Number of conflicting loads.
1111system.cpu1.memDep0.conflictingStores 1577382 # Number of conflicting stores.
1112system.cpu1.iq.iqInstsAdded 72765269 # Number of instructions added to the IQ (excludes non-spec)
1113system.cpu1.iq.iqNonSpecInstsAdded 1195198 # Number of non-speculative instructions added to the IQ
1114system.cpu1.iq.iqInstsIssued 96700645 # Number of instructions issued
1115system.cpu1.iq.iqSquashedInstsIssued 136833 # Number of squashed instructions issued
1116system.cpu1.iq.iqSquashedInstsExamined 20828043 # Number of squashed instructions iterated over during squash; mainly for profiling
1117system.cpu1.iq.iqSquashedOperandsExamined 58949605 # Number of squashed operands that are examined and possibly removed from graph
1118system.cpu1.iq.iqSquashedNonSpecRemoved 235739 # Number of squashed non-spec instructions that were removed
1119system.cpu1.iq.issued_per_cycle::samples 120738841 # Number of insts issued each cycle
1120system.cpu1.iq.issued_per_cycle::mean 0.800908 # Number of insts issued each cycle
1121system.cpu1.iq.issued_per_cycle::stdev 1.525223 # Number of insts issued each cycle
1122system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1123system.cpu1.iq.issued_per_cycle::0 86966093 72.03% 72.03% # Number of insts issued each cycle
1124system.cpu1.iq.issued_per_cycle::1 10006677 8.29% 80.32% # Number of insts issued each cycle
1125system.cpu1.iq.issued_per_cycle::2 4983433 4.13% 84.44% # Number of insts issued each cycle
1126system.cpu1.iq.issued_per_cycle::3 4114228 3.41% 87.85% # Number of insts issued each cycle
1127system.cpu1.iq.issued_per_cycle::4 11017570 9.13% 96.98% # Number of insts issued each cycle
1128system.cpu1.iq.issued_per_cycle::5 2069642 1.71% 98.69% # Number of insts issued each cycle
1129system.cpu1.iq.issued_per_cycle::6 1195614 0.99% 99.68% # Number of insts issued each cycle
1130system.cpu1.iq.issued_per_cycle::7 292428 0.24% 99.92% # Number of insts issued each cycle
1131system.cpu1.iq.issued_per_cycle::8 93156 0.08% 100.00% # Number of insts issued each cycle
1132system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1133system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1134system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1135system.cpu1.iq.issued_per_cycle::total 120738841 # Number of insts issued each cycle
1136system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1137system.cpu1.iq.fu_full::IntAlu 40933 0.51% 0.51% # attempts to use FU when none available
1138system.cpu1.iq.fu_full::IntMult 999 0.01% 0.52% # attempts to use FU when none available
1139system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.52% # attempts to use FU when none available
1140system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.52% # attempts to use FU when none available
1141system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.52% # attempts to use FU when none available
1142system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.52% # attempts to use FU when none available
1143system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.52% # attempts to use FU when none available
1144system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.52% # attempts to use FU when none available
1145system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.52% # attempts to use FU when none available
1146system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.52% # attempts to use FU when none available
1147system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.52% # attempts to use FU when none available
1148system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.52% # attempts to use FU when none available
1149system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.52% # attempts to use FU when none available
1150system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.52% # attempts to use FU when none available
1151system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.52% # attempts to use FU when none available
1152system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.52% # attempts to use FU when none available
1153system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.52% # attempts to use FU when none available
1154system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.52% # attempts to use FU when none available
1155system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.52% # attempts to use FU when none available
1156system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.52% # attempts to use FU when none available
1157system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.52% # attempts to use FU when none available
1158system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.52% # attempts to use FU when none available
1159system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.52% # attempts to use FU when none available
1160system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.52% # attempts to use FU when none available
1161system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.52% # attempts to use FU when none available
1162system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.52% # attempts to use FU when none available
1163system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.52% # attempts to use FU when none available
1164system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.52% # attempts to use FU when none available
1165system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.52% # attempts to use FU when none available
1166system.cpu1.iq.fu_full::MemRead 7708137 95.31% 95.83% # attempts to use FU when none available
1167system.cpu1.iq.fu_full::MemWrite 337009 4.17% 100.00% # attempts to use FU when none available
1168system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1169system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1170system.cpu1.iq.FU_type_0::No_OpClass 92785 0.10% 0.10% # Type of FU issued
1171system.cpu1.iq.FU_type_0::IntAlu 42154384 43.59% 43.69% # Type of FU issued
1172system.cpu1.iq.FU_type_0::IntMult 68643 0.07% 43.76% # Type of FU issued
1173system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.76% # Type of FU issued
1174system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.76% # Type of FU issued
1175system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.76% # Type of FU issued
1176system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.76% # Type of FU issued
1177system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.76% # Type of FU issued
1178system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.76% # Type of FU issued
1179system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.76% # Type of FU issued
1180system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.76% # Type of FU issued
1181system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.76% # Type of FU issued
1182system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.76% # Type of FU issued
1183system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.76% # Type of FU issued
1184system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.76% # Type of FU issued
1185system.cpu1.iq.FU_type_0::SimdMisc 27 0.00% 43.76% # Type of FU issued
1186system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.76% # Type of FU issued
1187system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.76% # Type of FU issued
1188system.cpu1.iq.FU_type_0::SimdShift 32 0.00% 43.76% # Type of FU issued
1189system.cpu1.iq.FU_type_0::SimdShiftAcc 3 0.00% 43.76% # Type of FU issued
1190system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.76% # Type of FU issued
1191system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.76% # Type of FU issued
1192system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.76% # Type of FU issued
1193system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.76% # Type of FU issued
1194system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.76% # Type of FU issued
1195system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.76% # Type of FU issued
1196system.cpu1.iq.FU_type_0::SimdFloatMisc 1443 0.00% 43.76% # Type of FU issued
1197system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.76% # Type of FU issued
1198system.cpu1.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 43.76% # Type of FU issued
1199system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.76% # Type of FU issued
1200system.cpu1.iq.FU_type_0::MemRead 46199078 47.78% 91.54% # Type of FU issued
1201system.cpu1.iq.FU_type_0::MemWrite 8184247 8.46% 100.00% # Type of FU issued
1202system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1203system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1204system.cpu1.iq.FU_type_0::total 96700645 # Type of FU issued
1205system.cpu1.iq.rate 0.267369 # Inst issue rate
1206system.cpu1.iq.fu_busy_cnt 8087078 # FU busy when requested
1207system.cpu1.iq.fu_busy_rate 0.083630 # FU busy rate (busy events/executed inst)
1208system.cpu1.iq.int_inst_queue_reads 322445450 # Number of integer instruction queue reads
1209system.cpu1.iq.int_inst_queue_writes 94804325 # Number of integer instruction queue writes
1210system.cpu1.iq.int_inst_queue_wakeup_accesses 60018746 # Number of integer instruction queue wakeup accesses
1211system.cpu1.iq.fp_inst_queue_reads 12063 # Number of floating instruction queue reads
1212system.cpu1.iq.fp_inst_queue_writes 6724 # Number of floating instruction queue writes
1213system.cpu1.iq.fp_inst_queue_wakeup_accesses 5497 # Number of floating instruction queue wakeup accesses
1214system.cpu1.iq.int_alu_accesses 104688665 # Number of integer alu accesses
1215system.cpu1.iq.fp_alu_accesses 6273 # Number of floating point alu accesses
1216system.cpu1.iew.lsq.thread0.forwLoads 377137 # Number of loads that had data forwarded from stores
1217system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1218system.cpu1.iew.lsq.thread0.squashedLoads 4715368 # Number of loads squashed
1219system.cpu1.iew.lsq.thread0.ignoredResponses 6098 # Number of memory responses ignored because the instruction is squashed
1220system.cpu1.iew.lsq.thread0.memOrderViolation 23303 # Number of memory ordering violations
1221system.cpu1.iew.lsq.thread0.squashedStores 1781253 # Number of stores squashed
1222system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1223system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1224system.cpu1.iew.lsq.thread0.rescheduledLoads 32175806 # Number of loads that were rescheduled
1225system.cpu1.iew.lsq.thread0.cacheBlocked 1149693 # Number of times an access to memory failed due to the cache being blocked
1226system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1227system.cpu1.iew.iewSquashCycles 3541436 # Number of cycles IEW is squashing
1228system.cpu1.iew.iewBlockCycles 25051723 # Number of cycles IEW is blocking
1229system.cpu1.iew.iewUnblockCycles 357920 # Number of cycles IEW is unblocking
1230system.cpu1.iew.iewDispatchedInsts 74130311 # Number of instructions dispatched to IQ
1231system.cpu1.iew.iewDispSquashedInsts 221482 # Number of squashed instructions skipped by dispatch
1232system.cpu1.iew.iewDispLoadInsts 15637648 # Number of dispatched load instructions
1233system.cpu1.iew.iewDispStoreInsts 9415892 # Number of dispatched store instructions
1234system.cpu1.iew.iewDispNonSpecInsts 813116 # Number of dispatched non-speculative instructions
1235system.cpu1.iew.iewIQFullEvents 58494 # Number of times the IQ has become full, causing a stall
1236system.cpu1.iew.iewLSQFullEvents 8530 # Number of times the LSQ has become full, causing a stall
1237system.cpu1.iew.memOrderViolationEvents 23303 # Number of memory order violations
1238system.cpu1.iew.predictedTakenIncorrect 417083 # Number of branches that were predicted taken incorrectly
1239system.cpu1.iew.predictedNotTakenIncorrect 225221 # Number of branches that were predicted not taken incorrectly
1240system.cpu1.iew.branchMispredicts 642304 # Number of branch mispredicts detected at execute
1241system.cpu1.iew.iewExecutedInsts 93796024 # Number of executed instructions
1242system.cpu1.iew.iewExecLoadInsts 45359703 # Number of load instructions executed
1243system.cpu1.iew.iewExecSquashedInsts 2904621 # Number of squashed instructions skipped in execute
1244system.cpu1.iew.exec_swp 0 # number of swp insts executed
1245system.cpu1.iew.exec_nop 169844 # number of nop insts executed
1246system.cpu1.iew.exec_refs 53443268 # number of memory reference insts executed
1247system.cpu1.iew.exec_branches 7814764 # Number of branches executed
1248system.cpu1.iew.exec_stores 8083565 # Number of stores executed
1249system.cpu1.iew.exec_rate 0.259338 # Inst execution rate
1250system.cpu1.iew.wb_sent 92469231 # cumulative count of insts sent to commit
1251system.cpu1.iew.wb_count 60024243 # cumulative count of insts written-back
1252system.cpu1.iew.wb_producers 32803499 # num instructions producing a value
1253system.cpu1.iew.wb_consumers 59096106 # num instructions consuming a value
1254system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1255system.cpu1.iew.wb_rate 0.165962 # insts written-back per cycle
1256system.cpu1.iew.wb_fanout 0.555087 # average fanout of values written-back
1257system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1258system.cpu1.commit.commitCommittedInsts 41355133 # The number of committed instructions
1259system.cpu1.commit.commitCommittedOps 52673164 # The number of committed instructions
1260system.cpu1.commit.commitSquashedInsts 21398329 # The number of squashed insts skipped by commit
1261system.cpu1.commit.commitNonSpecStalls 959459 # The number of times commit has been forced to stall to communicate backwards
1262system.cpu1.commit.branchMispredicts 564799 # The number of times a branch was mispredicted
1263system.cpu1.commit.committed_per_cycle::samples 117251310 # Number of insts commited each cycle
1264system.cpu1.commit.committed_per_cycle::mean 0.449233 # Number of insts commited each cycle
1265system.cpu1.commit.committed_per_cycle::stdev 1.403225 # Number of insts commited each cycle
1266system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1267system.cpu1.commit.committed_per_cycle::0 98126146 83.69% 83.69% # Number of insts commited each cycle
1268system.cpu1.commit.committed_per_cycle::1 9730536 8.30% 91.99% # Number of insts commited each cycle
1269system.cpu1.commit.committed_per_cycle::2 2573774 2.20% 94.18% # Number of insts commited each cycle
1270system.cpu1.commit.committed_per_cycle::3 1441495 1.23% 95.41% # Number of insts commited each cycle
1271system.cpu1.commit.committed_per_cycle::4 1191073 1.02% 96.43% # Number of insts commited each cycle
1272system.cpu1.commit.committed_per_cycle::5 709985 0.61% 97.03% # Number of insts commited each cycle
1273system.cpu1.commit.committed_per_cycle::6 1084141 0.92% 97.96% # Number of insts commited each cycle
1274system.cpu1.commit.committed_per_cycle::7 501748 0.43% 98.39% # Number of insts commited each cycle
1275system.cpu1.commit.committed_per_cycle::8 1892412 1.61% 100.00% # Number of insts commited each cycle
1276system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1277system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1278system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1279system.cpu1.commit.committed_per_cycle::total 117251310 # Number of insts commited each cycle
1280system.cpu1.commit.committedInsts 41355133 # Number of instructions committed
1281system.cpu1.commit.committedOps 52673164 # Number of ops (including micro ops) committed
1282system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
1283system.cpu1.commit.refs 18556919 # Number of memory references committed
1284system.cpu1.commit.loads 10922280 # Number of loads committed
1285system.cpu1.commit.membars 235767 # Number of memory barriers committed
1286system.cpu1.commit.branches 6572492 # Number of branches committed
1287system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions.
1288system.cpu1.commit.int_insts 46935651 # Number of committed integer instructions.
1289system.cpu1.commit.function_calls 612387 # Number of function calls committed.
1290system.cpu1.commit.bw_lim_events 1892412 # number cycles where commit BW limit reached
1291system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
1292system.cpu1.rob.rob_reads 188242511 # The number of ROB reads
1293system.cpu1.rob.rob_writes 151809339 # The number of ROB writes
1294system.cpu1.timesIdled 1543775 # Number of times that the entire CPU went into an idle state and unscheduled itself
1295system.cpu1.idleCycles 240936392 # Total number of cycles that the CPU has spent unscheduled due to idling
1296system.cpu1.quiesceCycles 4782922080 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1297system.cpu1.committedInsts 41229306 # Number of Instructions Simulated
1298system.cpu1.committedOps 52547337 # Number of Ops (including micro ops) Simulated
1299system.cpu1.committedInsts_total 41229306 # Number of Instructions Simulated
1300system.cpu1.cpi 8.772285 # CPI: Cycles Per Instruction
1301system.cpu1.cpi_total 8.772285 # CPI: Total CPI of All Threads
1302system.cpu1.ipc 0.113995 # IPC: Instructions Per Cycle
1303system.cpu1.ipc_total 0.113995 # IPC: Total IPC of All Threads
1304system.cpu1.int_regfile_reads 421917398 # number of integer regfile reads
1305system.cpu1.int_regfile_writes 62840714 # number of integer regfile writes
1306system.cpu1.fp_regfile_reads 4256 # number of floating regfile reads
1307system.cpu1.fp_regfile_writes 1992 # number of floating regfile writes
1308system.cpu1.misc_regfile_reads 99685734 # number of misc regfile reads
1309system.cpu1.misc_regfile_writes 498572 # number of misc regfile writes
1310system.cpu1.icache.replacements 696666 # number of replacements
1311system.cpu1.icache.tagsinuse 498.774287 # Cycle average of tags in use
1312system.cpu1.icache.total_refs 9464320 # Total number of references to valid blocks.
1313system.cpu1.icache.sampled_refs 697178 # Sample count of references to valid blocks.
1314system.cpu1.icache.avg_refs 13.575185 # Average number of references to valid blocks.
1315system.cpu1.icache.warmup_cycle 74291126000 # Cycle when the warmup percentage was hit.
1316system.cpu1.icache.occ_blocks::cpu1.inst 498.774287 # Average occupied blocks per requestor
1317system.cpu1.icache.occ_percent::cpu1.inst 0.974169 # Average percentage of cache occupancy
1318system.cpu1.icache.occ_percent::total 0.974169 # Average percentage of cache occupancy
1319system.cpu1.icache.ReadReq_hits::cpu1.inst 9464320 # number of ReadReq hits
1320system.cpu1.icache.ReadReq_hits::total 9464320 # number of ReadReq hits
1321system.cpu1.icache.demand_hits::cpu1.inst 9464320 # number of demand (read+write) hits
1322system.cpu1.icache.demand_hits::total 9464320 # number of demand (read+write) hits
1323system.cpu1.icache.overall_hits::cpu1.inst 9464320 # number of overall hits
1324system.cpu1.icache.overall_hits::total 9464320 # number of overall hits
1325system.cpu1.icache.ReadReq_misses::cpu1.inst 754908 # number of ReadReq misses
1326system.cpu1.icache.ReadReq_misses::total 754908 # number of ReadReq misses
1327system.cpu1.icache.demand_misses::cpu1.inst 754908 # number of demand (read+write) misses
1328system.cpu1.icache.demand_misses::total 754908 # number of demand (read+write) misses
1329system.cpu1.icache.overall_misses::cpu1.inst 754908 # number of overall misses
1330system.cpu1.icache.overall_misses::total 754908 # number of overall misses
1331system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11029274493 # number of ReadReq miss cycles
1332system.cpu1.icache.ReadReq_miss_latency::total 11029274493 # number of ReadReq miss cycles
1333system.cpu1.icache.demand_miss_latency::cpu1.inst 11029274493 # number of demand (read+write) miss cycles
1334system.cpu1.icache.demand_miss_latency::total 11029274493 # number of demand (read+write) miss cycles
1335system.cpu1.icache.overall_miss_latency::cpu1.inst 11029274493 # number of overall miss cycles
1336system.cpu1.icache.overall_miss_latency::total 11029274493 # number of overall miss cycles
1337system.cpu1.icache.ReadReq_accesses::cpu1.inst 10219228 # number of ReadReq accesses(hits+misses)
1338system.cpu1.icache.ReadReq_accesses::total 10219228 # number of ReadReq accesses(hits+misses)
1339system.cpu1.icache.demand_accesses::cpu1.inst 10219228 # number of demand (read+write) accesses
1340system.cpu1.icache.demand_accesses::total 10219228 # number of demand (read+write) accesses
1341system.cpu1.icache.overall_accesses::cpu1.inst 10219228 # number of overall (read+write) accesses
1342system.cpu1.icache.overall_accesses::total 10219228 # number of overall (read+write) accesses
1343system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073871 # miss rate for ReadReq accesses
1344system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073871 # miss rate for demand accesses
1345system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073871 # miss rate for overall accesses
1346system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14610.090889 # average ReadReq miss latency
1347system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14610.090889 # average overall miss latency
1348system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14610.090889 # average overall miss latency
1349system.cpu1.icache.blocked_cycles::no_mshrs 1452995 # number of cycles access was blocked
1350system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1351system.cpu1.icache.blocked::no_mshrs 231 # number of cycles access was blocked
1352system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1353system.cpu1.icache.avg_blocked_cycles::no_mshrs 6290.021645 # average number of cycles each access was blocked
1354system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
1355system.cpu1.icache.fast_writes 0 # number of fast writes performed
1356system.cpu1.icache.cache_copies 0 # number of cache copies performed
1357system.cpu1.icache.writebacks::writebacks 33177 # number of writebacks
1358system.cpu1.icache.writebacks::total 33177 # number of writebacks
1359system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 57704 # number of ReadReq MSHR hits
1360system.cpu1.icache.ReadReq_mshr_hits::total 57704 # number of ReadReq MSHR hits
1361system.cpu1.icache.demand_mshr_hits::cpu1.inst 57704 # number of demand (read+write) MSHR hits
1362system.cpu1.icache.demand_mshr_hits::total 57704 # number of demand (read+write) MSHR hits
1363system.cpu1.icache.overall_mshr_hits::cpu1.inst 57704 # number of overall MSHR hits
1364system.cpu1.icache.overall_mshr_hits::total 57704 # number of overall MSHR hits
1365system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 697204 # number of ReadReq MSHR misses
1366system.cpu1.icache.ReadReq_mshr_misses::total 697204 # number of ReadReq MSHR misses
1367system.cpu1.icache.demand_mshr_misses::cpu1.inst 697204 # number of demand (read+write) MSHR misses
1368system.cpu1.icache.demand_mshr_misses::total 697204 # number of demand (read+write) MSHR misses
1369system.cpu1.icache.overall_mshr_misses::cpu1.inst 697204 # number of overall MSHR misses
1370system.cpu1.icache.overall_mshr_misses::total 697204 # number of overall MSHR misses
1371system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8247682495 # number of ReadReq MSHR miss cycles
1372system.cpu1.icache.ReadReq_mshr_miss_latency::total 8247682495 # number of ReadReq MSHR miss cycles
1373system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8247682495 # number of demand (read+write) MSHR miss cycles
1374system.cpu1.icache.demand_mshr_miss_latency::total 8247682495 # number of demand (read+write) MSHR miss cycles
1375system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8247682495 # number of overall MSHR miss cycles
1376system.cpu1.icache.overall_mshr_miss_latency::total 8247682495 # number of overall MSHR miss cycles
1377system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2572500 # number of ReadReq MSHR uncacheable cycles
1378system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2572500 # number of ReadReq MSHR uncacheable cycles
1379system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2572500 # number of overall MSHR uncacheable cycles
1380system.cpu1.icache.overall_mshr_uncacheable_latency::total 2572500 # number of overall MSHR uncacheable cycles
1381system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068225 # mshr miss rate for ReadReq accesses
1382system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068225 # mshr miss rate for demand accesses
1383system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068225 # mshr miss rate for overall accesses
1384system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11829.654585 # average ReadReq mshr miss latency
1385system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11829.654585 # average overall mshr miss latency
1386system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11829.654585 # average overall mshr miss latency
1387system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
1388system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
1389system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1390system.cpu1.dcache.replacements 407468 # number of replacements
1391system.cpu1.dcache.tagsinuse 452.466365 # Cycle average of tags in use
1392system.cpu1.dcache.total_refs 14808453 # Total number of references to valid blocks.
1393system.cpu1.dcache.sampled_refs 407980 # Sample count of references to valid blocks.
1394system.cpu1.dcache.avg_refs 36.297007 # Average number of references to valid blocks.
1395system.cpu1.dcache.warmup_cycle 72560362000 # Cycle when the warmup percentage was hit.
1396system.cpu1.dcache.occ_blocks::cpu1.data 452.466365 # Average occupied blocks per requestor
1397system.cpu1.dcache.occ_percent::cpu1.data 0.883723 # Average percentage of cache occupancy
1398system.cpu1.dcache.occ_percent::total 0.883723 # Average percentage of cache occupancy
1399system.cpu1.dcache.ReadReq_hits::cpu1.data 9771721 # number of ReadReq hits
1400system.cpu1.dcache.ReadReq_hits::total 9771721 # number of ReadReq hits
1401system.cpu1.dcache.WriteReq_hits::cpu1.data 4750886 # number of WriteReq hits
1402system.cpu1.dcache.WriteReq_hits::total 4750886 # number of WriteReq hits
1403system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 123631 # number of LoadLockedReq hits
1404system.cpu1.dcache.LoadLockedReq_hits::total 123631 # number of LoadLockedReq hits
1405system.cpu1.dcache.StoreCondReq_hits::cpu1.data 116540 # number of StoreCondReq hits
1406system.cpu1.dcache.StoreCondReq_hits::total 116540 # number of StoreCondReq hits
1407system.cpu1.dcache.demand_hits::cpu1.data 14522607 # number of demand (read+write) hits
1408system.cpu1.dcache.demand_hits::total 14522607 # number of demand (read+write) hits
1409system.cpu1.dcache.overall_hits::cpu1.data 14522607 # number of overall hits
1410system.cpu1.dcache.overall_hits::total 14522607 # number of overall hits
1411system.cpu1.dcache.ReadReq_misses::cpu1.data 451897 # number of ReadReq misses
1412system.cpu1.dcache.ReadReq_misses::total 451897 # number of ReadReq misses
1413system.cpu1.dcache.WriteReq_misses::cpu1.data 1700738 # number of WriteReq misses
1414system.cpu1.dcache.WriteReq_misses::total 1700738 # number of WriteReq misses
1415system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14109 # number of LoadLockedReq misses
1416system.cpu1.dcache.LoadLockedReq_misses::total 14109 # number of LoadLockedReq misses
1417system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10120 # number of StoreCondReq misses
1418system.cpu1.dcache.StoreCondReq_misses::total 10120 # number of StoreCondReq misses
1419system.cpu1.dcache.demand_misses::cpu1.data 2152635 # number of demand (read+write) misses
1420system.cpu1.dcache.demand_misses::total 2152635 # number of demand (read+write) misses
1421system.cpu1.dcache.overall_misses::cpu1.data 2152635 # number of overall misses
1422system.cpu1.dcache.overall_misses::total 2152635 # number of overall misses
1423system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6794357500 # number of ReadReq miss cycles
1424system.cpu1.dcache.ReadReq_miss_latency::total 6794357500 # number of ReadReq miss cycles
1425system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 56737247402 # number of WriteReq miss cycles
1426system.cpu1.dcache.WriteReq_miss_latency::total 56737247402 # number of WriteReq miss cycles
1427system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 169367000 # number of LoadLockedReq miss cycles
1428system.cpu1.dcache.LoadLockedReq_miss_latency::total 169367000 # number of LoadLockedReq miss cycles
1429system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 85782500 # number of StoreCondReq miss cycles
1430system.cpu1.dcache.StoreCondReq_miss_latency::total 85782500 # number of StoreCondReq miss cycles
1431system.cpu1.dcache.demand_miss_latency::cpu1.data 63531604902 # number of demand (read+write) miss cycles
1432system.cpu1.dcache.demand_miss_latency::total 63531604902 # number of demand (read+write) miss cycles
1433system.cpu1.dcache.overall_miss_latency::cpu1.data 63531604902 # number of overall miss cycles
1434system.cpu1.dcache.overall_miss_latency::total 63531604902 # number of overall miss cycles
1435system.cpu1.dcache.ReadReq_accesses::cpu1.data 10223618 # number of ReadReq accesses(hits+misses)
1436system.cpu1.dcache.ReadReq_accesses::total 10223618 # number of ReadReq accesses(hits+misses)
1437system.cpu1.dcache.WriteReq_accesses::cpu1.data 6451624 # number of WriteReq accesses(hits+misses)
1438system.cpu1.dcache.WriteReq_accesses::total 6451624 # number of WriteReq accesses(hits+misses)
1439system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 137740 # number of LoadLockedReq accesses(hits+misses)
1440system.cpu1.dcache.LoadLockedReq_accesses::total 137740 # number of LoadLockedReq accesses(hits+misses)
1441system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 126660 # number of StoreCondReq accesses(hits+misses)
1442system.cpu1.dcache.StoreCondReq_accesses::total 126660 # number of StoreCondReq accesses(hits+misses)
1443system.cpu1.dcache.demand_accesses::cpu1.data 16675242 # number of demand (read+write) accesses
1444system.cpu1.dcache.demand_accesses::total 16675242 # number of demand (read+write) accesses
1445system.cpu1.dcache.overall_accesses::cpu1.data 16675242 # number of overall (read+write) accesses
1446system.cpu1.dcache.overall_accesses::total 16675242 # number of overall (read+write) accesses
1447system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044201 # miss rate for ReadReq accesses
1448system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.263614 # miss rate for WriteReq accesses
1449system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.102432 # miss rate for LoadLockedReq accesses
1450system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.079899 # miss rate for StoreCondReq accesses
1451system.cpu1.dcache.demand_miss_rate::cpu1.data 0.129092 # miss rate for demand accesses
1452system.cpu1.dcache.overall_miss_rate::cpu1.data 0.129092 # miss rate for overall accesses
1453system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15035.190541 # average ReadReq miss latency
1454system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33360.369088 # average WriteReq miss latency
1455system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12004.181728 # average LoadLockedReq miss latency
1456system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8476.531621 # average StoreCondReq miss latency
1457system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29513.412586 # average overall miss latency
1458system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29513.412586 # average overall miss latency
1459system.cpu1.dcache.blocked_cycles::no_mshrs 14045059 # number of cycles access was blocked
1460system.cpu1.dcache.blocked_cycles::no_targets 5012000 # number of cycles access was blocked
1461system.cpu1.dcache.blocked::no_mshrs 3121 # number of cycles access was blocked
1462system.cpu1.dcache.blocked::no_targets 132 # number of cycles access was blocked
1463system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4500.179109 # average number of cycles each access was blocked
1464system.cpu1.dcache.avg_blocked_cycles::no_targets 37969.696970 # average number of cycles each access was blocked
1465system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1466system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1467system.cpu1.dcache.writebacks::writebacks 337861 # number of writebacks
1468system.cpu1.dcache.writebacks::total 337861 # number of writebacks
1469system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 189374 # number of ReadReq MSHR hits
1470system.cpu1.dcache.ReadReq_mshr_hits::total 189374 # number of ReadReq MSHR hits
1471system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1526129 # number of WriteReq MSHR hits
1472system.cpu1.dcache.WriteReq_mshr_hits::total 1526129 # number of WriteReq MSHR hits
1473system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1128 # number of LoadLockedReq MSHR hits
1474system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1128 # number of LoadLockedReq MSHR hits
1475system.cpu1.dcache.demand_mshr_hits::cpu1.data 1715503 # number of demand (read+write) MSHR hits
1476system.cpu1.dcache.demand_mshr_hits::total 1715503 # number of demand (read+write) MSHR hits
1477system.cpu1.dcache.overall_mshr_hits::cpu1.data 1715503 # number of overall MSHR hits
1478system.cpu1.dcache.overall_mshr_hits::total 1715503 # number of overall MSHR hits
1479system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 262523 # number of ReadReq MSHR misses
1480system.cpu1.dcache.ReadReq_mshr_misses::total 262523 # number of ReadReq MSHR misses
1481system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 174609 # number of WriteReq MSHR misses
1482system.cpu1.dcache.WriteReq_mshr_misses::total 174609 # number of WriteReq MSHR misses
1483system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12981 # number of LoadLockedReq MSHR misses
1484system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12981 # number of LoadLockedReq MSHR misses
1485system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10116 # number of StoreCondReq MSHR misses
1486system.cpu1.dcache.StoreCondReq_mshr_misses::total 10116 # number of StoreCondReq MSHR misses
1487system.cpu1.dcache.demand_mshr_misses::cpu1.data 437132 # number of demand (read+write) MSHR misses
1488system.cpu1.dcache.demand_mshr_misses::total 437132 # number of demand (read+write) MSHR misses
1489system.cpu1.dcache.overall_mshr_misses::cpu1.data 437132 # number of overall MSHR misses
1490system.cpu1.dcache.overall_mshr_misses::total 437132 # number of overall MSHR misses
1491system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3281013000 # number of ReadReq MSHR miss cycles
1492system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3281013000 # number of ReadReq MSHR miss cycles
1493system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5495017558 # number of WriteReq MSHR miss cycles
1494system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5495017558 # number of WriteReq MSHR miss cycles
1495system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 116690000 # number of LoadLockedReq MSHR miss cycles
1496system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 116690000 # number of LoadLockedReq MSHR miss cycles
1497system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55378500 # number of StoreCondReq MSHR miss cycles
1498system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 55378500 # number of StoreCondReq MSHR miss cycles
1499system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2501 # number of StoreCondFailReq MSHR miss cycles
1500system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2501 # number of StoreCondFailReq MSHR miss cycles
1501system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8776030558 # number of demand (read+write) MSHR miss cycles
1502system.cpu1.dcache.demand_mshr_miss_latency::total 8776030558 # number of demand (read+write) MSHR miss cycles
1503system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8776030558 # number of overall MSHR miss cycles
1504system.cpu1.dcache.overall_mshr_miss_latency::total 8776030558 # number of overall MSHR miss cycles
1505system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137933382500 # number of ReadReq MSHR uncacheable cycles
1506system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137933382500 # number of ReadReq MSHR uncacheable cycles
1507system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41618386548 # number of WriteReq MSHR uncacheable cycles
1508system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41618386548 # number of WriteReq MSHR uncacheable cycles
1509system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179551769048 # number of overall MSHR uncacheable cycles
1510system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179551769048 # number of overall MSHR uncacheable cycles
1511system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025678 # mshr miss rate for ReadReq accesses
1512system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027064 # mshr miss rate for WriteReq accesses
1513system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.094243 # mshr miss rate for LoadLockedReq accesses
1514system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.079867 # mshr miss rate for StoreCondReq accesses
1515system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026214 # mshr miss rate for demand accesses
1516system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026214 # mshr miss rate for overall accesses
1517system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12498.002080 # average ReadReq mshr miss latency
1518system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31470.414228 # average WriteReq mshr miss latency
1519system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8989.292042 # average LoadLockedReq mshr miss latency
1520system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5474.347568 # average StoreCondReq mshr miss latency
1521system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1522system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20076.385527 # average overall mshr miss latency
1523system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20076.385527 # average overall mshr miss latency
1524system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1525system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1526system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1527system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1528system.iocache.replacements 0 # number of replacements
1529system.iocache.tagsinuse 0 # Cycle average of tags in use
1530system.iocache.total_refs 0 # Total number of references to valid blocks.
1531system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
1532system.iocache.avg_refs no_value # Average number of references to valid blocks.
1533system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1534system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1535system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1536system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1537system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1538system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
1539system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
1540system.iocache.fast_writes 0 # number of fast writes performed
1541system.iocache.cache_copies 0 # number of cache copies performed
1542system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308182536142 # number of ReadReq MSHR uncacheable cycles
1543system.iocache.ReadReq_mshr_uncacheable_latency::total 1308182536142 # number of ReadReq MSHR uncacheable cycles
1544system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308182536142 # number of overall MSHR uncacheable cycles
1545system.iocache.overall_mshr_uncacheable_latency::total 1308182536142 # number of overall MSHR uncacheable cycles
1546system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
1547system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
1548system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1549system.cpu0.kern.inst.arm 0 # number of arm instructions executed
1550system.cpu0.kern.inst.quiesce 38025 # number of quiesce instructions executed
1551system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1552system.cpu1.kern.inst.quiesce 59433 # number of quiesce instructions executed
1553
1554---------- End Simulation Statistics ----------