1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.605246 # Number of seconds simulated
4sim_ticks 2605245500000 # Number of ticks simulated
5final_tick 2605245500000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 66179 # Simulator instruction rate (inst/s)
8host_op_rate 85203 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2745863070 # Simulator tick rate (ticks/s)
10host_mem_usage 426204 # Number of bytes of host memory used
11host_seconds 948.79 # Real time elapsed on the host
12sim_insts 62790043 # Number of instructions simulated
13sim_ops 80839298 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.inst 393536 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.data 4351548 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.inst 427968 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.data 5241528 # Number of bytes read from this memory
24system.physmem.bytes_read::total 131526900 # Number of bytes read from this memory
25system.physmem.bytes_inst_read::cpu0.inst 393536 # Number of instructions bytes read from this memory
26system.physmem.bytes_inst_read::cpu1.inst 427968 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::total 821504 # Number of instructions bytes read from this memory
28system.physmem.bytes_written::writebacks 4250944 # Number of bytes written to this memory
29system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
30system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
31system.physmem.bytes_written::total 7280080 # Number of bytes written to this memory
32system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.inst 6149 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.data 68067 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu1.inst 6687 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu1.data 81927 # Number of read requests responded to by this memory
40system.physmem.num_reads::total 15301674 # Number of read requests responded to by this memory
41system.physmem.num_writes::writebacks 66421 # Number of write requests responded to by this memory
42system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
43system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
44system.physmem.num_writes::total 823705 # Number of write requests responded to by this memory
45system.physmem.bw_read::realview.clcd 46487184 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu0.dtb.walker 344 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::cpu0.inst 151055 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_read::cpu0.data 1670302 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu1.dtb.walker 319 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu1.inst 164272 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu1.data 2011913 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::total 50485415 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_inst_read::cpu0.inst 151055 # Instruction read bandwidth from this memory (bytes/s)
55system.physmem.bw_inst_read::cpu1.inst 164272 # Instruction read bandwidth from this memory (bytes/s)
56system.physmem.bw_inst_read::total 315327 # Instruction read bandwidth from this memory (bytes/s)
57system.physmem.bw_write::writebacks 1631687 # Write bandwidth from this memory (bytes/s)
58system.physmem.bw_write::cpu0.data 6525 # Write bandwidth from this memory (bytes/s)
59system.physmem.bw_write::cpu1.data 1156181 # Write bandwidth from this memory (bytes/s)
60system.physmem.bw_write::total 2794393 # Write bandwidth from this memory (bytes/s)
61system.physmem.bw_total::writebacks 1631687 # Total bandwidth to/from this memory (bytes/s)
62system.physmem.bw_total::realview.clcd 46487184 # Total bandwidth to/from this memory (bytes/s)
63system.physmem.bw_total::cpu0.dtb.walker 344 # Total bandwidth to/from this memory (bytes/s)
64system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
65system.physmem.bw_total::cpu0.inst 151055 # Total bandwidth to/from this memory (bytes/s)
66system.physmem.bw_total::cpu0.data 1676828 # Total bandwidth to/from this memory (bytes/s)
67system.physmem.bw_total::cpu1.dtb.walker 319 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::cpu1.inst 164272 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu1.data 3168095 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::total 53279808 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.readReqs 15301674 # Number of read requests accepted
72system.physmem.writeReqs 823705 # Number of write requests accepted
73system.physmem.readBursts 15301674 # Number of DRAM read bursts, including those serviced by the write queue
74system.physmem.writeBursts 823705 # Number of DRAM write bursts, including those merged in the write queue
75system.physmem.bytesReadDRAM 974584832 # Total number of bytes read from DRAM
76system.physmem.bytesReadWrQ 4722304 # Total number of bytes read from write queue
77system.physmem.bytesWritten 7299840 # Total number of bytes written to DRAM
78system.physmem.bytesReadSys 131526900 # Total read bytes from the system interface side
79system.physmem.bytesWrittenSys 7280080 # Total written bytes from the system interface side
80system.physmem.servicedByWrQ 73786 # Number of DRAM read bursts serviced by the write queue
81system.physmem.mergedWrBursts 709619 # Number of DRAM write bursts merged with an existing one
82system.physmem.neitherReadNorWriteReqs 14174 # Number of requests that are neither read nor write
83system.physmem.perBankRdBursts::0 956301 # Per bank write bursts
84system.physmem.perBankRdBursts::1 950868 # Per bank write bursts
85system.physmem.perBankRdBursts::2 950386 # Per bank write bursts
86system.physmem.perBankRdBursts::3 950557 # Per bank write bursts
87system.physmem.perBankRdBursts::4 956616 # Per bank write bursts
88system.physmem.perBankRdBursts::5 950990 # Per bank write bursts
89system.physmem.perBankRdBursts::6 949776 # Per bank write bursts
90system.physmem.perBankRdBursts::7 949548 # Per bank write bursts
91system.physmem.perBankRdBursts::8 956645 # Per bank write bursts
92system.physmem.perBankRdBursts::9 951285 # Per bank write bursts
93system.physmem.perBankRdBursts::10 949982 # Per bank write bursts
94system.physmem.perBankRdBursts::11 948991 # Per bank write bursts
95system.physmem.perBankRdBursts::12 956228 # Per bank write bursts
96system.physmem.perBankRdBursts::13 950424 # Per bank write bursts
97system.physmem.perBankRdBursts::14 949846 # Per bank write bursts
98system.physmem.perBankRdBursts::15 949445 # Per bank write bursts
99system.physmem.perBankWrBursts::0 7049 # Per bank write bursts
100system.physmem.perBankWrBursts::1 6917 # Per bank write bursts
101system.physmem.perBankWrBursts::2 7321 # Per bank write bursts
102system.physmem.perBankWrBursts::3 7203 # Per bank write bursts
103system.physmem.perBankWrBursts::4 7749 # Per bank write bursts
104system.physmem.perBankWrBursts::5 7300 # Per bank write bursts
105system.physmem.perBankWrBursts::6 7008 # Per bank write bursts
106system.physmem.perBankWrBursts::7 6995 # Per bank write bursts
107system.physmem.perBankWrBursts::8 7363 # Per bank write bursts
108system.physmem.perBankWrBursts::9 7456 # Per bank write bursts
109system.physmem.perBankWrBursts::10 6910 # Per bank write bursts
110system.physmem.perBankWrBursts::11 6580 # Per bank write bursts
111system.physmem.perBankWrBursts::12 7092 # Per bank write bursts
112system.physmem.perBankWrBursts::13 7012 # Per bank write bursts
113system.physmem.perBankWrBursts::14 7131 # Per bank write bursts
114system.physmem.perBankWrBursts::15 6974 # Per bank write bursts
115system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
116system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
117system.physmem.totGap 2605244301000 # Total gap between requests
118system.physmem.readPktSize::0 0 # Read request sizes (log2)
119system.physmem.readPktSize::1 0 # Read request sizes (log2)
120system.physmem.readPktSize::2 109 # Read request sizes (log2)
121system.physmem.readPktSize::3 15138816 # Read request sizes (log2)
122system.physmem.readPktSize::4 0 # Read request sizes (log2)
123system.physmem.readPktSize::5 0 # Read request sizes (log2)
124system.physmem.readPktSize::6 162749 # Read request sizes (log2)
125system.physmem.writePktSize::0 0 # Write request sizes (log2)
126system.physmem.writePktSize::1 0 # Write request sizes (log2)
127system.physmem.writePktSize::2 757284 # Write request sizes (log2)
128system.physmem.writePktSize::3 0 # Write request sizes (log2)
129system.physmem.writePktSize::4 0 # Write request sizes (log2)
130system.physmem.writePktSize::5 0 # Write request sizes (log2)
131system.physmem.writePktSize::6 66421 # Write request sizes (log2)
132system.physmem.rdQLenPdf::0 1076672 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::1 1007796 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::2 966781 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::3 1073648 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::4 970528 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::5 1031139 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::6 2669789 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::7 2577083 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::8 3357471 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::9 128637 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::10 110466 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::11 102015 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::12 98116 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::13 19856 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::14 18946 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::15 18627 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::16 197 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::18 12 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::19 10 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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155system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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157system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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171system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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180system.physmem.wrQLenPdf::16 2986 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::17 4505 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::18 6717 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::19 6884 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::20 6834 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::21 6859 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::22 7222 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::23 6902 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::24 6949 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::25 6984 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::26 6828 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::27 6821 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::28 7238 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::29 6837 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::30 6807 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::31 6970 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::32 6705 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::33 126 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::34 79 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::35 43 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
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205system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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220system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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225system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
228system.physmem.bytesPerActivate::samples 1012037 # Bytes accessed per row activation
229system.physmem.bytesPerActivate::mean 970.206299 # Bytes accessed per row activation
230system.physmem.bytesPerActivate::gmean 901.657757 # Bytes accessed per row activation
231system.physmem.bytesPerActivate::stdev 207.022901 # Bytes accessed per row activation
232system.physmem.bytesPerActivate::0-127 24841 2.45% 2.45% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::128-255 20798 2.06% 4.51% # Bytes accessed per row activation
234system.physmem.bytesPerActivate::256-383 8822 0.87% 5.38% # Bytes accessed per row activation
235system.physmem.bytesPerActivate::384-511 2548 0.25% 5.63% # Bytes accessed per row activation
236system.physmem.bytesPerActivate::512-639 2540 0.25% 5.88% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::640-767 1879 0.19% 6.07% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::768-895 8798 0.87% 6.94% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::896-1023 1115 0.11% 7.05% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::1024-1151 940696 92.95% 100.00% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::total 1012037 # Bytes accessed per row activation
242system.physmem.rdPerTurnAround::samples 6684 # Reads before turning the bus around for writes
243system.physmem.rdPerTurnAround::mean 2278.257181 # Reads before turning the bus around for writes
244system.physmem.rdPerTurnAround::stdev 111148.889106 # Reads before turning the bus around for writes
245system.physmem.rdPerTurnAround::0-524287 6680 99.94% 99.94% # Reads before turning the bus around for writes
246system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes
247system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.01% 99.99% # Reads before turning the bus around for writes
248system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.01% 100.00% # Reads before turning the bus around for writes
249system.physmem.rdPerTurnAround::total 6684 # Reads before turning the bus around for writes
250system.physmem.wrPerTurnAround::samples 6684 # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::mean 17.064632 # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::gmean 17.010880 # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::stdev 1.396865 # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::16 3849 57.59% 57.59% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::17 42 0.63% 58.21% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::18 1749 26.17% 84.38% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::19 863 12.91% 97.29% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::20 73 1.09% 98.38% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::21 28 0.42% 98.80% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::22 31 0.46% 99.27% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::23 31 0.46% 99.73% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::24 14 0.21% 99.94% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::25 3 0.04% 99.99% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::total 6684 # Writes before turning the bus around for reads
266system.physmem.totQLat 394529621500 # Total ticks spent queuing
267system.physmem.totMemAccLat 680052521500 # Total ticks spent from burst creation until serviced by the DRAM
268system.physmem.totBusLat 76139440000 # Total ticks spent in databus transfers
269system.physmem.avgQLat 25908.36 # Average queueing delay per DRAM burst
270system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
271system.physmem.avgMemAccLat 44658.36 # Average memory access latency per DRAM burst
272system.physmem.avgRdBW 374.09 # Average DRAM read bandwidth in MiByte/s
273system.physmem.avgWrBW 2.80 # Average achieved write bandwidth in MiByte/s
274system.physmem.avgRdBWSys 50.49 # Average system read bandwidth in MiByte/s
275system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s
276system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
277system.physmem.busUtil 2.94 # Data bus utilization in percentage
278system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads
279system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
280system.physmem.avgRdQLen 6.23 # Average read queue length when enqueuing
281system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing
282system.physmem.readRowHits 14233868 # Number of row buffer hits during reads
283system.physmem.writeRowHits 96043 # Number of row buffer hits during writes
284system.physmem.readRowHitRate 93.47 # Row buffer hit rate for reads
285system.physmem.writeRowHitRate 84.18 # Row buffer hit rate for writes
286system.physmem.avgGap 161561.74 # Average gap between requests
287system.physmem.pageHitRate 93.40 # Row buffer hit rate, read and write combined
288system.physmem.memoryStateTime::IDLE 2261037204000 # Time in different power states
289system.physmem.memoryStateTime::REF 86994700000 # Time in different power states
290system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
291system.physmem.memoryStateTime::ACT 257208674750 # Time in different power states
292system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
293system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
294system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
295system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
296system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
297system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory
298system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
299system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
300system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
301system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
302system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
303system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s)
304system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s)
305system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
306system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s)
307system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s)
308system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
309system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s)
310system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s)
311system.membus.throughput 54210578 # Throughput (bytes/s)
312system.membus.trans_dist::ReadReq 16352619 # Transaction distribution
313system.membus.trans_dist::ReadResp 16352619 # Transaction distribution
314system.membus.trans_dist::WriteReq 769183 # Transaction distribution
315system.membus.trans_dist::WriteResp 769183 # Transaction distribution
316system.membus.trans_dist::Writeback 66421 # Transaction distribution
317system.membus.trans_dist::UpgradeReq 35773 # Transaction distribution
318system.membus.trans_dist::SCUpgradeReq 18321 # Transaction distribution
319system.membus.trans_dist::UpgradeResp 14174 # Transaction distribution
320system.membus.trans_dist::ReadExReq 137666 # Transaction distribution
321system.membus.trans_dist::ReadExResp 137285 # Transaction distribution
322system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384364 # Packet count per connected master and slave (bytes)
323system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
324system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13834 # Packet count per connected master and slave (bytes)
325system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
326system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2042 # Packet count per connected master and slave (bytes)
327system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1975354 # Packet count per connected master and slave (bytes)
328system.membus.pkt_count_system.l2c.mem_side::total 4375612 # Packet count per connected master and slave (bytes)
329system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
330system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
331system.membus.pkt_count::total 34653244 # Packet count per connected master and slave (bytes)
332system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392677 # Cumulative packet size per connected master and slave (bytes)
333system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
334system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27668 # Cumulative packet size per connected master and slave (bytes)
335system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
336system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4084 # Cumulative packet size per connected master and slave (bytes)
337system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17696452 # Cumulative packet size per connected master and slave (bytes)
338system.membus.tot_pkt_size_system.l2c.mem_side::total 20121337 # Cumulative packet size per connected master and slave (bytes)
339system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
340system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
341system.membus.tot_pkt_size::total 141231865 # Cumulative packet size per connected master and slave (bytes)
342system.membus.data_through_bus 141231865 # Total data (bytes)
343system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
344system.membus.reqLayer0.occupancy 1487709500 # Layer occupancy (ticks)
345system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
346system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks)
347system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
348system.membus.reqLayer2.occupancy 11701000 # Layer occupancy (ticks)
349system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
350system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks)
351system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
352system.membus.reqLayer5.occupancy 1799000 # Layer occupancy (ticks)
353system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
354system.membus.reqLayer6.occupancy 17608394498 # Layer occupancy (ticks)
355system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
356system.membus.respLayer1.occupancy 4825319244 # Layer occupancy (ticks)
357system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
358system.membus.respLayer2.occupancy 37398632151 # Layer occupancy (ticks)
359system.membus.respLayer2.utilization 1.4 # Layer utilization (%)
360system.cpu_clk_domain.clock 500 # Clock period in ticks
361system.l2c.tags.replacements 72458 # number of replacements
362system.l2c.tags.tagsinuse 53011.924457 # Cycle average of tags in use
363system.l2c.tags.total_refs 1875821 # Total number of references to valid blocks.
364system.l2c.tags.sampled_refs 137631 # Sample count of references to valid blocks.
365system.l2c.tags.avg_refs 13.629349 # Average number of references to valid blocks.
366system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
367system.l2c.tags.occ_blocks::writebacks 37713.505334 # Average occupied blocks per requestor
368system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.216539 # Average occupied blocks per requestor
369system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000245 # Average occupied blocks per requestor
370system.l2c.tags.occ_blocks::cpu0.inst 4181.052971 # Average occupied blocks per requestor
371system.l2c.tags.occ_blocks::cpu0.data 2965.825646 # Average occupied blocks per requestor
372system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.076579 # Average occupied blocks per requestor
373system.l2c.tags.occ_blocks::cpu1.inst 4028.442908 # Average occupied blocks per requestor
374system.l2c.tags.occ_blocks::cpu1.data 4106.804235 # Average occupied blocks per requestor
375system.l2c.tags.occ_percent::writebacks 0.575462 # Average percentage of cache occupancy
376system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000080 # Average percentage of cache occupancy
377system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
378system.l2c.tags.occ_percent::cpu0.inst 0.063798 # Average percentage of cache occupancy
379system.l2c.tags.occ_percent::cpu0.data 0.045255 # Average percentage of cache occupancy
380system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000169 # Average percentage of cache occupancy
381system.l2c.tags.occ_percent::cpu1.inst 0.061469 # Average percentage of cache occupancy
382system.l2c.tags.occ_percent::cpu1.data 0.062665 # Average percentage of cache occupancy
383system.l2c.tags.occ_percent::total 0.808898 # Average percentage of cache occupancy
384system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
385system.l2c.tags.occ_task_id_blocks::1024 65168 # Occupied blocks per task id
386system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
387system.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
388system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
389system.l2c.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id
390system.l2c.tags.age_task_id_blocks_1024::2 3104 # Occupied blocks per task id
391system.l2c.tags.age_task_id_blocks_1024::3 8671 # Occupied blocks per task id
392system.l2c.tags.age_task_id_blocks_1024::4 53043 # Occupied blocks per task id
393system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
394system.l2c.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id
395system.l2c.tags.tag_accesses 18870937 # Number of tag accesses
396system.l2c.tags.data_accesses 18870937 # Number of data accesses
397system.l2c.ReadReq_hits::cpu0.dtb.walker 23602 # number of ReadReq hits
398system.l2c.ReadReq_hits::cpu0.itb.walker 4624 # number of ReadReq hits
399system.l2c.ReadReq_hits::cpu0.inst 393472 # number of ReadReq hits
400system.l2c.ReadReq_hits::cpu0.data 166101 # number of ReadReq hits
401system.l2c.ReadReq_hits::cpu1.dtb.walker 33133 # number of ReadReq hits
402system.l2c.ReadReq_hits::cpu1.itb.walker 5623 # number of ReadReq hits
403system.l2c.ReadReq_hits::cpu1.inst 609766 # number of ReadReq hits
404system.l2c.ReadReq_hits::cpu1.data 201485 # number of ReadReq hits
405system.l2c.ReadReq_hits::total 1437806 # number of ReadReq hits
406system.l2c.Writeback_hits::writebacks 583097 # number of Writeback hits
407system.l2c.Writeback_hits::total 583097 # number of Writeback hits
408system.l2c.UpgradeReq_hits::cpu0.data 1009 # number of UpgradeReq hits
409system.l2c.UpgradeReq_hits::cpu1.data 849 # number of UpgradeReq hits
410system.l2c.UpgradeReq_hits::total 1858 # number of UpgradeReq hits
411system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits
412system.l2c.SCUpgradeReq_hits::cpu1.data 170 # number of SCUpgradeReq hits
413system.l2c.SCUpgradeReq_hits::total 380 # number of SCUpgradeReq hits
414system.l2c.ReadExReq_hits::cpu0.data 48094 # number of ReadExReq hits
415system.l2c.ReadExReq_hits::cpu1.data 59208 # number of ReadExReq hits
416system.l2c.ReadExReq_hits::total 107302 # number of ReadExReq hits
417system.l2c.demand_hits::cpu0.dtb.walker 23602 # number of demand (read+write) hits
418system.l2c.demand_hits::cpu0.itb.walker 4624 # number of demand (read+write) hits
419system.l2c.demand_hits::cpu0.inst 393472 # number of demand (read+write) hits
420system.l2c.demand_hits::cpu0.data 214195 # number of demand (read+write) hits
421system.l2c.demand_hits::cpu1.dtb.walker 33133 # number of demand (read+write) hits
422system.l2c.demand_hits::cpu1.itb.walker 5623 # number of demand (read+write) hits
423system.l2c.demand_hits::cpu1.inst 609766 # number of demand (read+write) hits
424system.l2c.demand_hits::cpu1.data 260693 # number of demand (read+write) hits
425system.l2c.demand_hits::total 1545108 # number of demand (read+write) hits
426system.l2c.overall_hits::cpu0.dtb.walker 23602 # number of overall hits
427system.l2c.overall_hits::cpu0.itb.walker 4624 # number of overall hits
428system.l2c.overall_hits::cpu0.inst 393472 # number of overall hits
429system.l2c.overall_hits::cpu0.data 214195 # number of overall hits
430system.l2c.overall_hits::cpu1.dtb.walker 33133 # number of overall hits
431system.l2c.overall_hits::cpu1.itb.walker 5623 # number of overall hits
432system.l2c.overall_hits::cpu1.inst 609766 # number of overall hits
433system.l2c.overall_hits::cpu1.data 260693 # number of overall hits
434system.l2c.overall_hits::total 1545108 # number of overall hits
435system.l2c.ReadReq_misses::cpu0.dtb.walker 14 # number of ReadReq misses
436system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
437system.l2c.ReadReq_misses::cpu0.inst 6027 # number of ReadReq misses
438system.l2c.ReadReq_misses::cpu0.data 6315 # number of ReadReq misses
439system.l2c.ReadReq_misses::cpu1.dtb.walker 13 # number of ReadReq misses
440system.l2c.ReadReq_misses::cpu1.inst 6652 # number of ReadReq misses
441system.l2c.ReadReq_misses::cpu1.data 6349 # number of ReadReq misses
442system.l2c.ReadReq_misses::total 25371 # number of ReadReq misses
443system.l2c.UpgradeReq_misses::cpu0.data 5736 # number of UpgradeReq misses
444system.l2c.UpgradeReq_misses::cpu1.data 4455 # number of UpgradeReq misses
445system.l2c.UpgradeReq_misses::total 10191 # number of UpgradeReq misses
446system.l2c.SCUpgradeReq_misses::cpu0.data 772 # number of SCUpgradeReq misses
447system.l2c.SCUpgradeReq_misses::cpu1.data 591 # number of SCUpgradeReq misses
448system.l2c.SCUpgradeReq_misses::total 1363 # number of SCUpgradeReq misses
449system.l2c.ReadExReq_misses::cpu0.data 63106 # number of ReadExReq misses
450system.l2c.ReadExReq_misses::cpu1.data 76799 # number of ReadExReq misses
451system.l2c.ReadExReq_misses::total 139905 # number of ReadExReq misses
452system.l2c.demand_misses::cpu0.dtb.walker 14 # number of demand (read+write) misses
453system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
454system.l2c.demand_misses::cpu0.inst 6027 # number of demand (read+write) misses
455system.l2c.demand_misses::cpu0.data 69421 # number of demand (read+write) misses
456system.l2c.demand_misses::cpu1.dtb.walker 13 # number of demand (read+write) misses
457system.l2c.demand_misses::cpu1.inst 6652 # number of demand (read+write) misses
458system.l2c.demand_misses::cpu1.data 83148 # number of demand (read+write) misses
459system.l2c.demand_misses::total 165276 # number of demand (read+write) misses
460system.l2c.overall_misses::cpu0.dtb.walker 14 # number of overall misses
461system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
462system.l2c.overall_misses::cpu0.inst 6027 # number of overall misses
463system.l2c.overall_misses::cpu0.data 69421 # number of overall misses
464system.l2c.overall_misses::cpu1.dtb.walker 13 # number of overall misses
465system.l2c.overall_misses::cpu1.inst 6652 # number of overall misses
466system.l2c.overall_misses::cpu1.data 83148 # number of overall misses
467system.l2c.overall_misses::total 165276 # number of overall misses
468system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1286000 # number of ReadReq miss cycles
469system.l2c.ReadReq_miss_latency::cpu0.itb.walker 293000 # number of ReadReq miss cycles
470system.l2c.ReadReq_miss_latency::cpu0.inst 437446500 # number of ReadReq miss cycles
471system.l2c.ReadReq_miss_latency::cpu0.data 469525749 # number of ReadReq miss cycles
472system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1020750 # number of ReadReq miss cycles
473system.l2c.ReadReq_miss_latency::cpu1.inst 484881000 # number of ReadReq miss cycles
474system.l2c.ReadReq_miss_latency::cpu1.data 483780000 # number of ReadReq miss cycles
475system.l2c.ReadReq_miss_latency::total 1878232999 # number of ReadReq miss cycles
476system.l2c.UpgradeReq_miss_latency::cpu0.data 9370079 # number of UpgradeReq miss cycles
477system.l2c.UpgradeReq_miss_latency::cpu1.data 12322478 # number of UpgradeReq miss cycles
478system.l2c.UpgradeReq_miss_latency::total 21692557 # number of UpgradeReq miss cycles
479system.l2c.SCUpgradeReq_miss_latency::cpu0.data 533977 # number of SCUpgradeReq miss cycles
480system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3118865 # number of SCUpgradeReq miss cycles
481system.l2c.SCUpgradeReq_miss_latency::total 3652842 # number of SCUpgradeReq miss cycles
482system.l2c.ReadExReq_miss_latency::cpu0.data 4338208852 # number of ReadExReq miss cycles
483system.l2c.ReadExReq_miss_latency::cpu1.data 5958244026 # number of ReadExReq miss cycles
484system.l2c.ReadExReq_miss_latency::total 10296452878 # number of ReadExReq miss cycles
485system.l2c.demand_miss_latency::cpu0.dtb.walker 1286000 # number of demand (read+write) miss cycles
486system.l2c.demand_miss_latency::cpu0.itb.walker 293000 # number of demand (read+write) miss cycles
487system.l2c.demand_miss_latency::cpu0.inst 437446500 # number of demand (read+write) miss cycles
488system.l2c.demand_miss_latency::cpu0.data 4807734601 # number of demand (read+write) miss cycles
489system.l2c.demand_miss_latency::cpu1.dtb.walker 1020750 # number of demand (read+write) miss cycles
490system.l2c.demand_miss_latency::cpu1.inst 484881000 # number of demand (read+write) miss cycles
491system.l2c.demand_miss_latency::cpu1.data 6442024026 # number of demand (read+write) miss cycles
492system.l2c.demand_miss_latency::total 12174685877 # number of demand (read+write) miss cycles
493system.l2c.overall_miss_latency::cpu0.dtb.walker 1286000 # number of overall miss cycles
494system.l2c.overall_miss_latency::cpu0.itb.walker 293000 # number of overall miss cycles
495system.l2c.overall_miss_latency::cpu0.inst 437446500 # number of overall miss cycles
496system.l2c.overall_miss_latency::cpu0.data 4807734601 # number of overall miss cycles
497system.l2c.overall_miss_latency::cpu1.dtb.walker 1020750 # number of overall miss cycles
498system.l2c.overall_miss_latency::cpu1.inst 484881000 # number of overall miss cycles
499system.l2c.overall_miss_latency::cpu1.data 6442024026 # number of overall miss cycles
500system.l2c.overall_miss_latency::total 12174685877 # number of overall miss cycles
501system.l2c.ReadReq_accesses::cpu0.dtb.walker 23616 # number of ReadReq accesses(hits+misses)
502system.l2c.ReadReq_accesses::cpu0.itb.walker 4625 # number of ReadReq accesses(hits+misses)
503system.l2c.ReadReq_accesses::cpu0.inst 399499 # number of ReadReq accesses(hits+misses)
504system.l2c.ReadReq_accesses::cpu0.data 172416 # number of ReadReq accesses(hits+misses)
505system.l2c.ReadReq_accesses::cpu1.dtb.walker 33146 # number of ReadReq accesses(hits+misses)
506system.l2c.ReadReq_accesses::cpu1.itb.walker 5623 # number of ReadReq accesses(hits+misses)
507system.l2c.ReadReq_accesses::cpu1.inst 616418 # number of ReadReq accesses(hits+misses)
508system.l2c.ReadReq_accesses::cpu1.data 207834 # number of ReadReq accesses(hits+misses)
509system.l2c.ReadReq_accesses::total 1463177 # number of ReadReq accesses(hits+misses)
510system.l2c.Writeback_accesses::writebacks 583097 # number of Writeback accesses(hits+misses)
511system.l2c.Writeback_accesses::total 583097 # number of Writeback accesses(hits+misses)
512system.l2c.UpgradeReq_accesses::cpu0.data 6745 # number of UpgradeReq accesses(hits+misses)
513system.l2c.UpgradeReq_accesses::cpu1.data 5304 # number of UpgradeReq accesses(hits+misses)
514system.l2c.UpgradeReq_accesses::total 12049 # number of UpgradeReq accesses(hits+misses)
515system.l2c.SCUpgradeReq_accesses::cpu0.data 982 # number of SCUpgradeReq accesses(hits+misses)
516system.l2c.SCUpgradeReq_accesses::cpu1.data 761 # number of SCUpgradeReq accesses(hits+misses)
517system.l2c.SCUpgradeReq_accesses::total 1743 # number of SCUpgradeReq accesses(hits+misses)
518system.l2c.ReadExReq_accesses::cpu0.data 111200 # number of ReadExReq accesses(hits+misses)
519system.l2c.ReadExReq_accesses::cpu1.data 136007 # number of ReadExReq accesses(hits+misses)
520system.l2c.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses)
521system.l2c.demand_accesses::cpu0.dtb.walker 23616 # number of demand (read+write) accesses
522system.l2c.demand_accesses::cpu0.itb.walker 4625 # number of demand (read+write) accesses
523system.l2c.demand_accesses::cpu0.inst 399499 # number of demand (read+write) accesses
524system.l2c.demand_accesses::cpu0.data 283616 # number of demand (read+write) accesses
525system.l2c.demand_accesses::cpu1.dtb.walker 33146 # number of demand (read+write) accesses
526system.l2c.demand_accesses::cpu1.itb.walker 5623 # number of demand (read+write) accesses
527system.l2c.demand_accesses::cpu1.inst 616418 # number of demand (read+write) accesses
528system.l2c.demand_accesses::cpu1.data 343841 # number of demand (read+write) accesses
529system.l2c.demand_accesses::total 1710384 # number of demand (read+write) accesses
530system.l2c.overall_accesses::cpu0.dtb.walker 23616 # number of overall (read+write) accesses
531system.l2c.overall_accesses::cpu0.itb.walker 4625 # number of overall (read+write) accesses
532system.l2c.overall_accesses::cpu0.inst 399499 # number of overall (read+write) accesses
533system.l2c.overall_accesses::cpu0.data 283616 # number of overall (read+write) accesses
534system.l2c.overall_accesses::cpu1.dtb.walker 33146 # number of overall (read+write) accesses
535system.l2c.overall_accesses::cpu1.itb.walker 5623 # number of overall (read+write) accesses
536system.l2c.overall_accesses::cpu1.inst 616418 # number of overall (read+write) accesses
537system.l2c.overall_accesses::cpu1.data 343841 # number of overall (read+write) accesses
538system.l2c.overall_accesses::total 1710384 # number of overall (read+write) accesses
539system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000593 # miss rate for ReadReq accesses
540system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000216 # miss rate for ReadReq accesses
541system.l2c.ReadReq_miss_rate::cpu0.inst 0.015086 # miss rate for ReadReq accesses
542system.l2c.ReadReq_miss_rate::cpu0.data 0.036627 # miss rate for ReadReq accesses
543system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000392 # miss rate for ReadReq accesses
544system.l2c.ReadReq_miss_rate::cpu1.inst 0.010791 # miss rate for ReadReq accesses
545system.l2c.ReadReq_miss_rate::cpu1.data 0.030548 # miss rate for ReadReq accesses
546system.l2c.ReadReq_miss_rate::total 0.017340 # miss rate for ReadReq accesses
547system.l2c.UpgradeReq_miss_rate::cpu0.data 0.850408 # miss rate for UpgradeReq accesses
548system.l2c.UpgradeReq_miss_rate::cpu1.data 0.839932 # miss rate for UpgradeReq accesses
549system.l2c.UpgradeReq_miss_rate::total 0.845796 # miss rate for UpgradeReq accesses
550system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.786151 # miss rate for SCUpgradeReq accesses
551system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.776610 # miss rate for SCUpgradeReq accesses
552system.l2c.SCUpgradeReq_miss_rate::total 0.781985 # miss rate for SCUpgradeReq accesses
553system.l2c.ReadExReq_miss_rate::cpu0.data 0.567500 # miss rate for ReadExReq accesses
554system.l2c.ReadExReq_miss_rate::cpu1.data 0.564669 # miss rate for ReadExReq accesses
555system.l2c.ReadExReq_miss_rate::total 0.565943 # miss rate for ReadExReq accesses
556system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000593 # miss rate for demand accesses
557system.l2c.demand_miss_rate::cpu0.itb.walker 0.000216 # miss rate for demand accesses
558system.l2c.demand_miss_rate::cpu0.inst 0.015086 # miss rate for demand accesses
559system.l2c.demand_miss_rate::cpu0.data 0.244771 # miss rate for demand accesses
560system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000392 # miss rate for demand accesses
561system.l2c.demand_miss_rate::cpu1.inst 0.010791 # miss rate for demand accesses
562system.l2c.demand_miss_rate::cpu1.data 0.241821 # miss rate for demand accesses
563system.l2c.demand_miss_rate::total 0.096631 # miss rate for demand accesses
564system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000593 # miss rate for overall accesses
565system.l2c.overall_miss_rate::cpu0.itb.walker 0.000216 # miss rate for overall accesses
566system.l2c.overall_miss_rate::cpu0.inst 0.015086 # miss rate for overall accesses
567system.l2c.overall_miss_rate::cpu0.data 0.244771 # miss rate for overall accesses
568system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000392 # miss rate for overall accesses
569system.l2c.overall_miss_rate::cpu1.inst 0.010791 # miss rate for overall accesses
570system.l2c.overall_miss_rate::cpu1.data 0.241821 # miss rate for overall accesses
571system.l2c.overall_miss_rate::total 0.096631 # miss rate for overall accesses
572system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 91857.142857 # average ReadReq miss latency
573system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 293000 # average ReadReq miss latency
574system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72581.134893 # average ReadReq miss latency
575system.l2c.ReadReq_avg_miss_latency::cpu0.data 74350.870784 # average ReadReq miss latency
576system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 78519.230769 # average ReadReq miss latency
577system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72892.513530 # average ReadReq miss latency
578system.l2c.ReadReq_avg_miss_latency::cpu1.data 76197.826429 # average ReadReq miss latency
579system.l2c.ReadReq_avg_miss_latency::total 74030.704308 # average ReadReq miss latency
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702system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16534155943 # number of WriteReq MSHR uncacheable cycles
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715system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030423 # mshr miss rate for ReadReq accesses
716system.l2c.ReadReq_mshr_miss_rate::total 0.017287 # mshr miss rate for ReadReq accesses
717system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.850408 # mshr miss rate for UpgradeReq accesses
718system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.839932 # mshr miss rate for UpgradeReq accesses
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720system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.786151 # mshr miss rate for SCUpgradeReq accesses
721system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.776610 # mshr miss rate for SCUpgradeReq accesses
722system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.781985 # mshr miss rate for SCUpgradeReq accesses
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727system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000216 # mshr miss rate for demand accesses
728system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015074 # mshr miss rate for demand accesses
729system.l2c.demand_mshr_miss_rate::cpu0.data 0.244637 # mshr miss rate for demand accesses
730system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000392 # mshr miss rate for demand accesses
731system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010778 # mshr miss rate for demand accesses
732system.l2c.demand_mshr_miss_rate::cpu1.data 0.241745 # mshr miss rate for demand accesses
733system.l2c.demand_mshr_miss_rate::total 0.096586 # mshr miss rate for demand accesses
734system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000593 # mshr miss rate for overall accesses
735system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000216 # mshr miss rate for overall accesses
736system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015074 # mshr miss rate for overall accesses
737system.l2c.overall_mshr_miss_rate::cpu0.data 0.244637 # mshr miss rate for overall accesses
738system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000392 # mshr miss rate for overall accesses
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740system.l2c.overall_mshr_miss_rate::cpu1.data 0.241745 # mshr miss rate for overall accesses
741system.l2c.overall_mshr_miss_rate::total 0.096586 # mshr miss rate for overall accesses
742system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79500 # average ReadReq mshr miss latency
743system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average ReadReq mshr miss latency
744system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59992.112255 # average ReadReq mshr miss latency
745system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61855.663374 # average ReadReq mshr miss latency
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747system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60343.354907 # average ReadReq mshr miss latency
748system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63802.981180 # average ReadReq mshr miss latency
749system.l2c.ReadReq_avg_mshr_miss_latency::total 61522.208785 # average ReadReq mshr miss latency
750system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10032.540098 # average UpgradeReq mshr miss latency
751system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10079.993939 # average UpgradeReq mshr miss latency
752system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10053.284565 # average UpgradeReq mshr miss latency
753system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10013.950777 # average SCUpgradeReq mshr miss latency
754system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10011.994924 # average SCUpgradeReq mshr miss latency
755system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10013.102715 # average SCUpgradeReq mshr miss latency
756system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56401.421988 # average ReadExReq mshr miss latency
757system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65247.633042 # average ReadExReq mshr miss latency
758system.l2c.ReadExReq_avg_mshr_miss_latency::total 61257.432586 # average ReadExReq mshr miss latency
759system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79500 # average overall mshr miss latency
760system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average overall mshr miss latency
761system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59992.112255 # average overall mshr miss latency
762system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56894.860917 # average overall mshr miss latency
763system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462 # average overall mshr miss latency
764system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60343.354907 # average overall mshr miss latency
765system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65137.739949 # average overall mshr miss latency
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768system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average overall mshr miss latency
769system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59992.112255 # average overall mshr miss latency
770system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56894.860917 # average overall mshr miss latency
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773system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65137.739949 # average overall mshr miss latency
774system.l2c.overall_avg_mshr_miss_latency::total 61297.973081 # average overall mshr miss latency
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776system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
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778system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
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780system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
781system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
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787system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
788system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
789system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
790system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
791system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
792system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
793system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
794system.cf0.dma_write_txs 0 # Number of DMA write transactions.
795system.toL2Bus.throughput 58770672 # Throughput (bytes/s)
796system.toL2Bus.trans_dist::ReadReq 2743232 # Transaction distribution
797system.toL2Bus.trans_dist::ReadResp 2743231 # Transaction distribution
798system.toL2Bus.trans_dist::WriteReq 769183 # Transaction distribution
799system.toL2Bus.trans_dist::WriteResp 769183 # Transaction distribution
800system.toL2Bus.trans_dist::Writeback 583097 # Transaction distribution
801system.toL2Bus.trans_dist::UpgradeReq 35011 # Transaction distribution
802system.toL2Bus.trans_dist::SCUpgradeReq 18701 # Transaction distribution
803system.toL2Bus.trans_dist::UpgradeResp 53712 # Transaction distribution
804system.toL2Bus.trans_dist::ReadExReq 259154 # Transaction distribution
805system.toL2Bus.trans_dist::ReadExResp 259154 # Transaction distribution
806system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 799809 # Packet count per connected master and slave (bytes)
807system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073837 # Packet count per connected master and slave (bytes)
808system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 14034 # Packet count per connected master and slave (bytes)
809system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 57985 # Packet count per connected master and slave (bytes)
810system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1233533 # Packet count per connected master and slave (bytes)
811system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4820063 # Packet count per connected master and slave (bytes)
812system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 15283 # Packet count per connected master and slave (bytes)
813system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 75701 # Packet count per connected master and slave (bytes)
814system.toL2Bus.pkt_count::total 8090245 # Packet count per connected master and slave (bytes)
815system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25576064 # Cumulative packet size per connected master and slave (bytes)
816system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34728353 # Cumulative packet size per connected master and slave (bytes)
817system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18500 # Cumulative packet size per connected master and slave (bytes)
818system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 94464 # Cumulative packet size per connected master and slave (bytes)
819system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39453888 # Cumulative packet size per connected master and slave (bytes)
820system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 48201112 # Cumulative packet size per connected master and slave (bytes)
821system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 22492 # Cumulative packet size per connected master and slave (bytes)
822system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132584 # Cumulative packet size per connected master and slave (bytes)
823system.toL2Bus.tot_pkt_size::total 148227457 # Cumulative packet size per connected master and slave (bytes)
824system.toL2Bus.data_through_bus 148227457 # Total data (bytes)
825system.toL2Bus.snoop_data_through_bus 4884572 # Total snoop data (bytes)
826system.toL2Bus.reqLayer0.occupancy 4922251450 # Layer occupancy (ticks)
827system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
828system.toL2Bus.respLayer0.occupancy 1802620121 # Layer occupancy (ticks)
829system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
830system.toL2Bus.respLayer1.occupancy 1515652575 # Layer occupancy (ticks)
831system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
832system.toL2Bus.respLayer2.occupancy 9436941 # Layer occupancy (ticks)
833system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
834system.toL2Bus.respLayer3.occupancy 34537141 # Layer occupancy (ticks)
835system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
836system.toL2Bus.respLayer6.occupancy 2778792830 # Layer occupancy (ticks)
837system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%)
838system.toL2Bus.respLayer7.occupancy 3257203486 # Layer occupancy (ticks)
839system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%)
840system.toL2Bus.respLayer8.occupancy 9681453 # Layer occupancy (ticks)
841system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%)
842system.toL2Bus.respLayer9.occupancy 42845398 # Layer occupancy (ticks)
843system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%)
844system.iobus.throughput 47405592 # Throughput (bytes/s)
845system.iobus.trans_dist::ReadReq 16322915 # Transaction distribution
846system.iobus.trans_dist::ReadResp 16322915 # Transaction distribution
847system.iobus.trans_dist::WriteReq 8083 # Transaction distribution
848system.iobus.trans_dist::WriteResp 8083 # Transaction distribution
849system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30944 # Packet count per connected master and slave (bytes)
850system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8836 # Packet count per connected master and slave (bytes)
851system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
852system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes)

--- 93 unchanged lines hidden (view full) ---

946system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
947system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
948system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
949system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
950system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
951system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
952system.iobus.respLayer0.occupancy 2376281000 # Layer occupancy (ticks)
953system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
954system.iobus.respLayer1.occupancy 38152801849 # Layer occupancy (ticks)
955system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
956system.cpu0.branchPred.lookups 6193187 # Number of BP lookups
957system.cpu0.branchPred.condPredicted 4738042 # Number of conditional branches predicted
958system.cpu0.branchPred.condIncorrect 296192 # Number of conditional branches incorrect
959system.cpu0.branchPred.BTBLookups 3876930 # Number of BTB lookups
960system.cpu0.branchPred.BTBHits 2986045 # Number of BTB hits
961system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
962system.cpu0.branchPred.BTBHitPct 77.020864 # BTB Hit Percentage
963system.cpu0.branchPred.usedRAS 687525 # Number of times the RAS was used to get a target.
964system.cpu0.branchPred.RASInCorrect 28310 # Number of incorrect RAS predictions.
965system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
966system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
967system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
968system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
969system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
970system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
971system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
972system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 7 unchanged lines hidden (view full) ---

980system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
981system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
982system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
983system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
984system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
985system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
986system.cpu0.dtb.inst_hits 0 # ITB inst hits
987system.cpu0.dtb.inst_misses 0 # ITB inst misses
988system.cpu0.dtb.read_hits 8977307 # DTB read hits
989system.cpu0.dtb.read_misses 29619 # DTB read misses
990system.cpu0.dtb.write_hits 5215302 # DTB write hits
991system.cpu0.dtb.write_misses 5680 # DTB write misses
992system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
993system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
994system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
995system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
996system.cpu0.dtb.flush_entries 1732 # Number of entries that have been flushed from TLB
997system.cpu0.dtb.align_faults 993 # Number of TLB faults due to alignment restrictions
998system.cpu0.dtb.prefetch_faults 285 # Number of TLB faults due to prefetch
999system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1000system.cpu0.dtb.perms_faults 620 # Number of TLB faults due to permissions restrictions
1001system.cpu0.dtb.read_accesses 9006926 # DTB read accesses
1002system.cpu0.dtb.write_accesses 5220982 # DTB write accesses
1003system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
1004system.cpu0.dtb.hits 14192609 # DTB hits
1005system.cpu0.dtb.misses 35299 # DTB misses
1006system.cpu0.dtb.accesses 14227908 # DTB accesses
1007system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1008system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1009system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1010system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1011system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1012system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1013system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1014system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

1020system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1021system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1022system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1023system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1024system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1025system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1026system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1027system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1028system.cpu0.itb.inst_hits 4299863 # ITB inst hits
1029system.cpu0.itb.inst_misses 5195 # ITB inst misses
1030system.cpu0.itb.read_hits 0 # DTB read hits
1031system.cpu0.itb.read_misses 0 # DTB read misses
1032system.cpu0.itb.write_hits 0 # DTB write hits
1033system.cpu0.itb.write_misses 0 # DTB write misses
1034system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
1035system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1036system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1037system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1038system.cpu0.itb.flush_entries 1219 # Number of entries that have been flushed from TLB
1039system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1040system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1041system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1042system.cpu0.itb.perms_faults 1331 # Number of TLB faults due to permissions restrictions
1043system.cpu0.itb.read_accesses 0 # DTB read accesses
1044system.cpu0.itb.write_accesses 0 # DTB write accesses
1045system.cpu0.itb.inst_accesses 4305058 # ITB inst accesses
1046system.cpu0.itb.hits 4299863 # DTB hits
1047system.cpu0.itb.misses 5195 # DTB misses
1048system.cpu0.itb.accesses 4305058 # DTB accesses
1049system.cpu0.numCycles 69478980 # number of cpu cycles simulated
1050system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
1051system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
1052system.cpu0.fetch.icacheStallCycles 11944453 # Number of cycles fetch is stalled on an Icache miss
1053system.cpu0.fetch.Insts 32774113 # Number of instructions fetch has processed
1054system.cpu0.fetch.Branches 6193187 # Number of branches that fetch encountered
1055system.cpu0.fetch.predictedBranches 3673570 # Number of branches that fetch has predicted taken
1056system.cpu0.fetch.Cycles 7678957 # Number of cycles fetch has run and was not squashing or blocked
1057system.cpu0.fetch.SquashCycles 1502530 # Number of cycles fetch has spent squashing
1058system.cpu0.fetch.TlbCycles 63317 # Number of cycles fetch has spent waiting for tlb
1059system.cpu0.fetch.BlockedCycles 19508655 # Number of cycles fetch has spent blocked
1060system.cpu0.fetch.MiscStallCycles 6049 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1061system.cpu0.fetch.PendingTrapStallCycles 47760 # Number of stall cycles due to pending traps
1062system.cpu0.fetch.PendingQuiesceStallCycles 1413705 # Number of stall cycles due to pending quiesce instructions
1063system.cpu0.fetch.IcacheWaitRetryStallCycles 248 # Number of stall cycles due to full MSHR
1064system.cpu0.fetch.CacheLines 4298413 # Number of cache lines fetched
1065system.cpu0.fetch.IcacheSquashes 159366 # Number of outstanding Icache misses that were squashed
1066system.cpu0.fetch.ItlbSquashes 2185 # Number of outstanding ITLB misses that were squashed
1067system.cpu0.fetch.rateDist::samples 41753011 # Number of instructions fetched each cycle (Total)
1068system.cpu0.fetch.rateDist::mean 1.013655 # Number of instructions fetched each cycle (Total)
1069system.cpu0.fetch.rateDist::stdev 2.394447 # Number of instructions fetched each cycle (Total)
1070system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1071system.cpu0.fetch.rateDist::0 34081524 81.63% 81.63% # Number of instructions fetched each cycle (Total)
1072system.cpu0.fetch.rateDist::1 576095 1.38% 83.01% # Number of instructions fetched each cycle (Total)
1073system.cpu0.fetch.rateDist::2 828597 1.98% 84.99% # Number of instructions fetched each cycle (Total)
1074system.cpu0.fetch.rateDist::3 688423 1.65% 86.64% # Number of instructions fetched each cycle (Total)
1075system.cpu0.fetch.rateDist::4 783359 1.88% 88.52% # Number of instructions fetched each cycle (Total)
1076system.cpu0.fetch.rateDist::5 570610 1.37% 89.88% # Number of instructions fetched each cycle (Total)
1077system.cpu0.fetch.rateDist::6 698382 1.67% 91.56% # Number of instructions fetched each cycle (Total)
1078system.cpu0.fetch.rateDist::7 360373 0.86% 92.42% # Number of instructions fetched each cycle (Total)
1079system.cpu0.fetch.rateDist::8 3165648 7.58% 100.00% # Number of instructions fetched each cycle (Total)
1080system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1081system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1082system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1083system.cpu0.fetch.rateDist::total 41753011 # Number of instructions fetched each cycle (Total)
1084system.cpu0.fetch.branchRate 0.089138 # Number of branch fetches per cycle
1085system.cpu0.fetch.rate 0.471713 # Number of inst fetches per cycle
1086system.cpu0.decode.IdleCycles 12274082 # Number of cycles decode is idle
1087system.cpu0.decode.BlockedCycles 20961054 # Number of cycles decode is blocked
1088system.cpu0.decode.RunCycles 7066192 # Number of cycles decode is running
1089system.cpu0.decode.UnblockCycles 425731 # Number of cycles decode is unblocking
1090system.cpu0.decode.SquashCycles 1025952 # Number of cycles decode is squashing
1091system.cpu0.decode.BranchResolved 955706 # Number of times decode resolved a branch
1092system.cpu0.decode.BranchMispred 65065 # Number of times decode detected a branch misprediction
1093system.cpu0.decode.DecodedInsts 40945366 # Number of instructions handled by decode
1094system.cpu0.decode.SquashedInsts 213036 # Number of squashed instructions handled by decode
1095system.cpu0.rename.SquashCycles 1025952 # Number of cycles rename is squashing
1096system.cpu0.rename.IdleCycles 12760478 # Number of cycles rename is idle
1097system.cpu0.rename.BlockCycles 3004976 # Number of cycles rename is blocking
1098system.cpu0.rename.serializeStallCycles 13648632 # count of cycles rename stalled for serializing inst
1099system.cpu0.rename.RunCycles 7041602 # Number of cycles rename is running
1100system.cpu0.rename.UnblockCycles 4271371 # Number of cycles rename is unblocking
1101system.cpu0.rename.RenamedInsts 39802599 # Number of instructions processed by rename
1102system.cpu0.rename.ROBFullEvents 1199 # Number of times rename has blocked due to ROB full
1103system.cpu0.rename.IQFullEvents 1526731 # Number of times rename has blocked due to IQ full
1104system.cpu0.rename.LQFullEvents 1438820 # Number of times rename has blocked due to LQ full
1105system.cpu0.rename.SQFullEvents 1837389 # Number of times rename has blocked due to SQ full
1106system.cpu0.rename.FullRegisterEvents 522 # Number of times there has been no free registers
1107system.cpu0.rename.RenamedOperands 40279465 # Number of destination operands rename has renamed
1108system.cpu0.rename.RenameLookups 182145305 # Number of register rename lookups that rename has made
1109system.cpu0.rename.int_rename_lookups 165318292 # Number of integer rename lookups
1110system.cpu0.rename.fp_rename_lookups 4116 # Number of floating rename lookups
1111system.cpu0.rename.CommittedMaps 31479900 # Number of HB maps that are committed
1112system.cpu0.rename.UndoneMaps 8799564 # Number of HB maps that are undone due to squashing
1113system.cpu0.rename.serializingInsts 460456 # count of serializing insts renamed
1114system.cpu0.rename.tempSerializingInsts 417031 # count of temporary serializing insts renamed
1115system.cpu0.rename.skidInsts 4293085 # count of insts added to the skid buffer
1116system.cpu0.memDep0.insertedLoads 7837564 # Number of loads inserted to the mem dependence unit.
1117system.cpu0.memDep0.insertedStores 5796369 # Number of stores inserted to the mem dependence unit.
1118system.cpu0.memDep0.conflictingLoads 1159621 # Number of conflicting loads.
1119system.cpu0.memDep0.conflictingStores 1213862 # Number of conflicting stores.
1120system.cpu0.iq.iqInstsAdded 37649045 # Number of instructions added to the IQ (excludes non-spec)
1121system.cpu0.iq.iqNonSpecInstsAdded 906994 # Number of non-speculative instructions added to the IQ
1122system.cpu0.iq.iqInstsIssued 37770468 # Number of instructions issued
1123system.cpu0.iq.iqSquashedInstsIssued 93887 # Number of squashed instructions issued
1124system.cpu0.iq.iqSquashedInstsExamined 6620221 # Number of squashed instructions iterated over during squash; mainly for profiling
1125system.cpu0.iq.iqSquashedOperandsExamined 14342287 # Number of squashed operands that are examined and possibly removed from graph
1126system.cpu0.iq.iqSquashedNonSpecRemoved 258409 # Number of squashed non-spec instructions that were removed
1127system.cpu0.iq.issued_per_cycle::samples 41753011 # Number of insts issued each cycle
1128system.cpu0.iq.issued_per_cycle::mean 0.904617 # Number of insts issued each cycle
1129system.cpu0.iq.issued_per_cycle::stdev 1.539726 # Number of insts issued each cycle
1130system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1131system.cpu0.iq.issued_per_cycle::0 26686839 63.92% 63.92% # Number of insts issued each cycle
1132system.cpu0.iq.issued_per_cycle::1 5690671 13.63% 77.55% # Number of insts issued each cycle
1133system.cpu0.iq.issued_per_cycle::2 3035101 7.27% 84.81% # Number of insts issued each cycle
1134system.cpu0.iq.issued_per_cycle::3 2408430 5.77% 90.58% # Number of insts issued each cycle
1135system.cpu0.iq.issued_per_cycle::4 2094356 5.02% 95.60% # Number of insts issued each cycle
1136system.cpu0.iq.issued_per_cycle::5 953036 2.28% 97.88% # Number of insts issued each cycle
1137system.cpu0.iq.issued_per_cycle::6 611124 1.46% 99.35% # Number of insts issued each cycle
1138system.cpu0.iq.issued_per_cycle::7 212675 0.51% 99.85% # Number of insts issued each cycle
1139system.cpu0.iq.issued_per_cycle::8 60779 0.15% 100.00% # Number of insts issued each cycle
1140system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1141system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1142system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1143system.cpu0.iq.issued_per_cycle::total 41753011 # Number of insts issued each cycle
1144system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1145system.cpu0.iq.fu_full::IntAlu 29050 2.58% 2.58% # attempts to use FU when none available
1146system.cpu0.iq.fu_full::IntMult 460 0.04% 2.62% # attempts to use FU when none available
1147system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.62% # attempts to use FU when none available
1148system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.62% # attempts to use FU when none available
1149system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.62% # attempts to use FU when none available
1150system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.62% # attempts to use FU when none available
1151system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.62% # attempts to use FU when none available
1152system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.62% # attempts to use FU when none available
1153system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.62% # attempts to use FU when none available
1154system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.62% # attempts to use FU when none available
1155system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.62% # attempts to use FU when none available
1156system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.62% # attempts to use FU when none available
1157system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.62% # attempts to use FU when none available
1158system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.62% # attempts to use FU when none available
1159system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.62% # attempts to use FU when none available
1160system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.62% # attempts to use FU when none available
1161system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.62% # attempts to use FU when none available
1162system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.62% # attempts to use FU when none available
1163system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.62% # attempts to use FU when none available
1164system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.62% # attempts to use FU when none available
1165system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.62% # attempts to use FU when none available
1166system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.62% # attempts to use FU when none available
1167system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.62% # attempts to use FU when none available
1168system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.62% # attempts to use FU when none available
1169system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.62% # attempts to use FU when none available
1170system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.62% # attempts to use FU when none available
1171system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.62% # attempts to use FU when none available
1172system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.62% # attempts to use FU when none available
1173system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.62% # attempts to use FU when none available
1174system.cpu0.iq.fu_full::MemRead 862862 76.64% 79.26% # attempts to use FU when none available
1175system.cpu0.iq.fu_full::MemWrite 233562 20.74% 100.00% # attempts to use FU when none available
1176system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1177system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1178system.cpu0.iq.FU_type_0::No_OpClass 14549 0.04% 0.04% # Type of FU issued
1179system.cpu0.iq.FU_type_0::IntAlu 22728130 60.17% 60.21% # Type of FU issued
1180system.cpu0.iq.FU_type_0::IntMult 48220 0.13% 60.34% # Type of FU issued
1181system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued
1182system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued
1183system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued
1184system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued
1185system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued
1186system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued
1187system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued
1188system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued
1189system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued
1190system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.34% # Type of FU issued
1191system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued
1192system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued
1193system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.34% # Type of FU issued
1194system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued
1195system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued
1196system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.34% # Type of FU issued
1197system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.34% # Type of FU issued
1198system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued
1199system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued
1200system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued
1201system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued
1202system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued
1203system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued
1204system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.34% # Type of FU issued
1205system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued
1206system.cpu0.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 60.34% # Type of FU issued
1207system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued
1208system.cpu0.iq.FU_type_0::MemRead 9442602 25.00% 85.34% # Type of FU issued
1209system.cpu0.iq.FU_type_0::MemWrite 5536256 14.66% 100.00% # Type of FU issued
1210system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1211system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1212system.cpu0.iq.FU_type_0::total 37770468 # Type of FU issued
1213system.cpu0.iq.rate 0.543624 # Inst issue rate
1214system.cpu0.iq.fu_busy_cnt 1125934 # FU busy when requested
1215system.cpu0.iq.fu_busy_rate 0.029810 # FU busy rate (busy events/executed inst)
1216system.cpu0.iq.int_inst_queue_reads 118540397 # Number of integer instruction queue reads
1217system.cpu0.iq.int_inst_queue_writes 45184408 # Number of integer instruction queue writes
1218system.cpu0.iq.int_inst_queue_wakeup_accesses 34905571 # Number of integer instruction queue wakeup accesses
1219system.cpu0.iq.fp_inst_queue_reads 8382 # Number of floating instruction queue reads
1220system.cpu0.iq.fp_inst_queue_writes 4748 # Number of floating instruction queue writes
1221system.cpu0.iq.fp_inst_queue_wakeup_accesses 3872 # Number of floating instruction queue wakeup accesses
1222system.cpu0.iq.int_alu_accesses 38877516 # Number of integer alu accesses
1223system.cpu0.iq.fp_alu_accesses 4337 # Number of floating point alu accesses
1224system.cpu0.iew.lsq.thread0.forwLoads 330330 # Number of loads that had data forwarded from stores
1225system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1226system.cpu0.iew.lsq.thread0.squashedLoads 1458060 # Number of loads squashed
1227system.cpu0.iew.lsq.thread0.ignoredResponses 2363 # Number of memory responses ignored because the instruction is squashed
1228system.cpu0.iew.lsq.thread0.memOrderViolation 13414 # Number of memory ordering violations
1229system.cpu0.iew.lsq.thread0.squashedStores 565962 # Number of stores squashed
1230system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1231system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1232system.cpu0.iew.lsq.thread0.rescheduledLoads 2141820 # Number of loads that were rescheduled
1233system.cpu0.iew.lsq.thread0.cacheBlocked 5981 # Number of times an access to memory failed due to the cache being blocked
1234system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1235system.cpu0.iew.iewSquashCycles 1025952 # Number of cycles IEW is squashing
1236system.cpu0.iew.iewBlockCycles 2385802 # Number of cycles IEW is blocking
1237system.cpu0.iew.iewUnblockCycles 275075 # Number of cycles IEW is unblocking
1238system.cpu0.iew.iewDispatchedInsts 38676599 # Number of instructions dispatched to IQ
1239system.cpu0.iew.iewDispSquashedInsts 76106 # Number of squashed instructions skipped by dispatch
1240system.cpu0.iew.iewDispLoadInsts 7837564 # Number of dispatched load instructions
1241system.cpu0.iew.iewDispStoreInsts 5796369 # Number of dispatched store instructions
1242system.cpu0.iew.iewDispNonSpecInsts 579111 # Number of dispatched non-speculative instructions
1243system.cpu0.iew.iewIQFullEvents 58653 # Number of times the IQ has become full, causing a stall
1244system.cpu0.iew.iewLSQFullEvents 199282 # Number of times the LSQ has become full, causing a stall
1245system.cpu0.iew.memOrderViolationEvents 13414 # Number of memory order violations
1246system.cpu0.iew.predictedTakenIncorrect 149919 # Number of branches that were predicted taken incorrectly
1247system.cpu0.iew.predictedNotTakenIncorrect 118426 # Number of branches that were predicted not taken incorrectly
1248system.cpu0.iew.branchMispredicts 268345 # Number of branch mispredicts detected at execute
1249system.cpu0.iew.iewExecutedInsts 37387044 # Number of executed instructions
1250system.cpu0.iew.iewExecLoadInsts 9294285 # Number of load instructions executed
1251system.cpu0.iew.iewExecSquashedInsts 383424 # Number of squashed instructions skipped in execute
1252system.cpu0.iew.exec_swp 0 # number of swp insts executed
1253system.cpu0.iew.exec_nop 120560 # number of nop insts executed
1254system.cpu0.iew.exec_refs 14782259 # number of memory reference insts executed
1255system.cpu0.iew.exec_branches 4971290 # Number of branches executed
1256system.cpu0.iew.exec_stores 5487974 # Number of stores executed
1257system.cpu0.iew.exec_rate 0.538106 # Inst execution rate
1258system.cpu0.iew.wb_sent 37190474 # cumulative count of insts sent to commit
1259system.cpu0.iew.wb_count 34909443 # cumulative count of insts written-back
1260system.cpu0.iew.wb_producers 18996365 # num instructions producing a value
1261system.cpu0.iew.wb_consumers 36943291 # num instructions consuming a value
1262system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1263system.cpu0.iew.wb_rate 0.502446 # insts written-back per cycle
1264system.cpu0.iew.wb_fanout 0.514203 # average fanout of values written-back
1265system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1266system.cpu0.commit.commitSquashedInsts 6443412 # The number of squashed insts skipped by commit
1267system.cpu0.commit.commitNonSpecStalls 648585 # The number of times commit has been forced to stall to communicate backwards
1268system.cpu0.commit.branchMispredicts 232277 # The number of times a branch was mispredicted
1269system.cpu0.commit.committed_per_cycle::samples 40727059 # Number of insts commited each cycle
1270system.cpu0.commit.committed_per_cycle::mean 0.780301 # Number of insts commited each cycle
1271system.cpu0.commit.committed_per_cycle::stdev 1.748318 # Number of insts commited each cycle
1272system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1273system.cpu0.commit.committed_per_cycle::0 28935599 71.05% 71.05% # Number of insts commited each cycle
1274system.cpu0.commit.committed_per_cycle::1 5796697 14.23% 85.28% # Number of insts commited each cycle
1275system.cpu0.commit.committed_per_cycle::2 1842943 4.53% 89.81% # Number of insts commited each cycle
1276system.cpu0.commit.committed_per_cycle::3 1067095 2.62% 92.43% # Number of insts commited each cycle
1277system.cpu0.commit.committed_per_cycle::4 737891 1.81% 94.24% # Number of insts commited each cycle
1278system.cpu0.commit.committed_per_cycle::5 511993 1.26% 95.49% # Number of insts commited each cycle
1279system.cpu0.commit.committed_per_cycle::6 448684 1.10% 96.60% # Number of insts commited each cycle
1280system.cpu0.commit.committed_per_cycle::7 197374 0.48% 97.08% # Number of insts commited each cycle
1281system.cpu0.commit.committed_per_cycle::8 1188783 2.92% 100.00% # Number of insts commited each cycle
1282system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1283system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1284system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1285system.cpu0.commit.committed_per_cycle::total 40727059 # Number of insts commited each cycle
1286system.cpu0.commit.committedInsts 24067678 # Number of instructions committed
1287system.cpu0.commit.committedOps 31779383 # Number of ops (including micro ops) committed
1288system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
1289system.cpu0.commit.refs 11609911 # Number of memory references committed
1290system.cpu0.commit.loads 6379504 # Number of loads committed
1291system.cpu0.commit.membars 231786 # Number of memory barriers committed
1292system.cpu0.commit.branches 4350837 # Number of branches committed
1293system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
1294system.cpu0.commit.int_insts 28125415 # Number of committed integer instructions.
1295system.cpu0.commit.function_calls 498912 # Number of function calls committed.
1296system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
1297system.cpu0.commit.op_class_0::IntAlu 20129006 63.34% 63.34% # Class of committed instruction
1298system.cpu0.commit.op_class_0::IntMult 39786 0.13% 63.47% # Class of committed instruction
1299system.cpu0.commit.op_class_0::IntDiv 0 0.00% 63.47% # Class of committed instruction
1300system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 63.47% # Class of committed instruction
1301system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 63.47% # Class of committed instruction
1302system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 63.47% # Class of committed instruction
1303system.cpu0.commit.op_class_0::FloatMult 0 0.00% 63.47% # Class of committed instruction
1304system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 63.47% # Class of committed instruction
1305system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 63.47% # Class of committed instruction
1306system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 63.47% # Class of committed instruction
1307system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 63.47% # Class of committed instruction
1308system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 63.47% # Class of committed instruction
1309system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 63.47% # Class of committed instruction
1310system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 63.47% # Class of committed instruction
1311system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 63.47% # Class of committed instruction
1312system.cpu0.commit.op_class_0::SimdMult 0 0.00% 63.47% # Class of committed instruction
1313system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 63.47% # Class of committed instruction
1314system.cpu0.commit.op_class_0::SimdShift 0 0.00% 63.47% # Class of committed instruction
1315system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 63.47% # Class of committed instruction
1316system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 63.47% # Class of committed instruction
1317system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 63.47% # Class of committed instruction
1318system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 63.47% # Class of committed instruction
1319system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 63.47% # Class of committed instruction
1320system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 63.47% # Class of committed instruction
1321system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 63.47% # Class of committed instruction
1322system.cpu0.commit.op_class_0::SimdFloatMisc 680 0.00% 63.47% # Class of committed instruction
1323system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 63.47% # Class of committed instruction
1324system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.47% # Class of committed instruction
1325system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.47% # Class of committed instruction
1326system.cpu0.commit.op_class_0::MemRead 6379504 20.07% 83.54% # Class of committed instruction
1327system.cpu0.commit.op_class_0::MemWrite 5230407 16.46% 100.00% # Class of committed instruction
1328system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1329system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
1330system.cpu0.commit.op_class_0::total 31779383 # Class of committed instruction
1331system.cpu0.commit.bw_lim_events 1188783 # number cycles where commit BW limit reached
1332system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
1333system.cpu0.rob.rob_reads 76892389 # The number of ROB reads
1334system.cpu0.rob.rob_writes 77473478 # The number of ROB writes
1335system.cpu0.timesIdled 368167 # Number of times that the entire CPU went into an idle state and unscheduled itself
1336system.cpu0.idleCycles 27725969 # Total number of cycles that the CPU has spent unscheduled due to idling
1337system.cpu0.quiesceCycles 5140969387 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1338system.cpu0.committedInsts 23986936 # Number of Instructions Simulated
1339system.cpu0.committedOps 31698641 # Number of Ops (including micro ops) Simulated
1340system.cpu0.cpi 2.896534 # CPI: Cycles Per Instruction
1341system.cpu0.cpi_total 2.896534 # CPI: Total CPI of All Threads
1342system.cpu0.ipc 0.345240 # IPC: Instructions Per Cycle
1343system.cpu0.ipc_total 0.345240 # IPC: Total IPC of All Threads
1344system.cpu0.int_regfile_reads 174527841 # number of integer regfile reads
1345system.cpu0.int_regfile_writes 34672219 # number of integer regfile writes
1346system.cpu0.fp_regfile_reads 3319 # number of floating regfile reads
1347system.cpu0.fp_regfile_writes 920 # number of floating regfile writes
1348system.cpu0.misc_regfile_reads 78617689 # number of misc regfile reads
1349system.cpu0.misc_regfile_writes 500675 # number of misc regfile writes
1350system.cpu0.icache.tags.replacements 399525 # number of replacements
1351system.cpu0.icache.tags.tagsinuse 511.581560 # Cycle average of tags in use
1352system.cpu0.icache.tags.total_refs 3866760 # Total number of references to valid blocks.
1353system.cpu0.icache.tags.sampled_refs 400037 # Sample count of references to valid blocks.
1354system.cpu0.icache.tags.avg_refs 9.666006 # Average number of references to valid blocks.
1355system.cpu0.icache.tags.warmup_cycle 6951542250 # Cycle when the warmup percentage was hit.
1356system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.581560 # Average occupied blocks per requestor
1357system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999183 # Average percentage of cache occupancy
1358system.cpu0.icache.tags.occ_percent::total 0.999183 # Average percentage of cache occupancy
1359system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1360system.cpu0.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
1361system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id
1362system.cpu0.icache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id
1363system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
1364system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1365system.cpu0.icache.tags.tag_accesses 4698333 # Number of tag accesses
1366system.cpu0.icache.tags.data_accesses 4698333 # Number of data accesses
1367system.cpu0.icache.ReadReq_hits::cpu0.inst 3866760 # number of ReadReq hits
1368system.cpu0.icache.ReadReq_hits::total 3866760 # number of ReadReq hits
1369system.cpu0.icache.demand_hits::cpu0.inst 3866760 # number of demand (read+write) hits
1370system.cpu0.icache.demand_hits::total 3866760 # number of demand (read+write) hits
1371system.cpu0.icache.overall_hits::cpu0.inst 3866760 # number of overall hits
1372system.cpu0.icache.overall_hits::total 3866760 # number of overall hits
1373system.cpu0.icache.ReadReq_misses::cpu0.inst 431519 # number of ReadReq misses
1374system.cpu0.icache.ReadReq_misses::total 431519 # number of ReadReq misses
1375system.cpu0.icache.demand_misses::cpu0.inst 431519 # number of demand (read+write) misses
1376system.cpu0.icache.demand_misses::total 431519 # number of demand (read+write) misses
1377system.cpu0.icache.overall_misses::cpu0.inst 431519 # number of overall misses
1378system.cpu0.icache.overall_misses::total 431519 # number of overall misses
1379system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5963742706 # number of ReadReq miss cycles
1380system.cpu0.icache.ReadReq_miss_latency::total 5963742706 # number of ReadReq miss cycles
1381system.cpu0.icache.demand_miss_latency::cpu0.inst 5963742706 # number of demand (read+write) miss cycles
1382system.cpu0.icache.demand_miss_latency::total 5963742706 # number of demand (read+write) miss cycles
1383system.cpu0.icache.overall_miss_latency::cpu0.inst 5963742706 # number of overall miss cycles
1384system.cpu0.icache.overall_miss_latency::total 5963742706 # number of overall miss cycles
1385system.cpu0.icache.ReadReq_accesses::cpu0.inst 4298279 # number of ReadReq accesses(hits+misses)
1386system.cpu0.icache.ReadReq_accesses::total 4298279 # number of ReadReq accesses(hits+misses)
1387system.cpu0.icache.demand_accesses::cpu0.inst 4298279 # number of demand (read+write) accesses
1388system.cpu0.icache.demand_accesses::total 4298279 # number of demand (read+write) accesses
1389system.cpu0.icache.overall_accesses::cpu0.inst 4298279 # number of overall (read+write) accesses
1390system.cpu0.icache.overall_accesses::total 4298279 # number of overall (read+write) accesses
1391system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100393 # miss rate for ReadReq accesses
1392system.cpu0.icache.ReadReq_miss_rate::total 0.100393 # miss rate for ReadReq accesses
1393system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100393 # miss rate for demand accesses
1394system.cpu0.icache.demand_miss_rate::total 0.100393 # miss rate for demand accesses
1395system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100393 # miss rate for overall accesses
1396system.cpu0.icache.overall_miss_rate::total 0.100393 # miss rate for overall accesses
1397system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13820.347901 # average ReadReq miss latency
1398system.cpu0.icache.ReadReq_avg_miss_latency::total 13820.347901 # average ReadReq miss latency
1399system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13820.347901 # average overall miss latency
1400system.cpu0.icache.demand_avg_miss_latency::total 13820.347901 # average overall miss latency
1401system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13820.347901 # average overall miss latency
1402system.cpu0.icache.overall_avg_miss_latency::total 13820.347901 # average overall miss latency
1403system.cpu0.icache.blocked_cycles::no_mshrs 4778 # number of cycles access was blocked
1404system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1405system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked
1406system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
1407system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.493827 # average number of cycles each access was blocked
1408system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1409system.cpu0.icache.fast_writes 0 # number of fast writes performed
1410system.cpu0.icache.cache_copies 0 # number of cache copies performed
1411system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31464 # number of ReadReq MSHR hits
1412system.cpu0.icache.ReadReq_mshr_hits::total 31464 # number of ReadReq MSHR hits
1413system.cpu0.icache.demand_mshr_hits::cpu0.inst 31464 # number of demand (read+write) MSHR hits
1414system.cpu0.icache.demand_mshr_hits::total 31464 # number of demand (read+write) MSHR hits
1415system.cpu0.icache.overall_mshr_hits::cpu0.inst 31464 # number of overall MSHR hits
1416system.cpu0.icache.overall_mshr_hits::total 31464 # number of overall MSHR hits
1417system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400055 # number of ReadReq MSHR misses
1418system.cpu0.icache.ReadReq_mshr_misses::total 400055 # number of ReadReq MSHR misses
1419system.cpu0.icache.demand_mshr_misses::cpu0.inst 400055 # number of demand (read+write) MSHR misses
1420system.cpu0.icache.demand_mshr_misses::total 400055 # number of demand (read+write) MSHR misses
1421system.cpu0.icache.overall_mshr_misses::cpu0.inst 400055 # number of overall MSHR misses
1422system.cpu0.icache.overall_mshr_misses::total 400055 # number of overall MSHR misses
1423system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4860147872 # number of ReadReq MSHR miss cycles
1424system.cpu0.icache.ReadReq_mshr_miss_latency::total 4860147872 # number of ReadReq MSHR miss cycles
1425system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4860147872 # number of demand (read+write) MSHR miss cycles
1426system.cpu0.icache.demand_mshr_miss_latency::total 4860147872 # number of demand (read+write) MSHR miss cycles
1427system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4860147872 # number of overall MSHR miss cycles
1428system.cpu0.icache.overall_mshr_miss_latency::total 4860147872 # number of overall MSHR miss cycles
1429system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9713500 # number of ReadReq MSHR uncacheable cycles
1430system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9713500 # number of ReadReq MSHR uncacheable cycles
1431system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9713500 # number of overall MSHR uncacheable cycles
1432system.cpu0.icache.overall_mshr_uncacheable_latency::total 9713500 # number of overall MSHR uncacheable cycles
1433system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093073 # mshr miss rate for ReadReq accesses
1434system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093073 # mshr miss rate for ReadReq accesses
1435system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093073 # mshr miss rate for demand accesses
1436system.cpu0.icache.demand_mshr_miss_rate::total 0.093073 # mshr miss rate for demand accesses
1437system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093073 # mshr miss rate for overall accesses
1438system.cpu0.icache.overall_mshr_miss_rate::total 0.093073 # mshr miss rate for overall accesses
1439system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12148.699234 # average ReadReq mshr miss latency
1440system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12148.699234 # average ReadReq mshr miss latency
1441system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12148.699234 # average overall mshr miss latency
1442system.cpu0.icache.demand_avg_mshr_miss_latency::total 12148.699234 # average overall mshr miss latency
1443system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12148.699234 # average overall mshr miss latency
1444system.cpu0.icache.overall_avg_mshr_miss_latency::total 12148.699234 # average overall mshr miss latency
1445system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1446system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1447system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1448system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1449system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1450system.cpu0.dcache.tags.replacements 275167 # number of replacements
1451system.cpu0.dcache.tags.tagsinuse 480.361699 # Cycle average of tags in use
1452system.cpu0.dcache.tags.total_refs 9408418 # Total number of references to valid blocks.
1453system.cpu0.dcache.tags.sampled_refs 275679 # Sample count of references to valid blocks.
1454system.cpu0.dcache.tags.avg_refs 34.128164 # Average number of references to valid blocks.
1455system.cpu0.dcache.tags.warmup_cycle 42907250 # Cycle when the warmup percentage was hit.
1456system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.361699 # Average occupied blocks per requestor
1457system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938206 # Average percentage of cache occupancy
1458system.cpu0.dcache.tags.occ_percent::total 0.938206 # Average percentage of cache occupancy
1459system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1460system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id
1461system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id
1462system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
1463system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1464system.cpu0.dcache.tags.tag_accesses 45804428 # Number of tag accesses
1465system.cpu0.dcache.tags.data_accesses 45804428 # Number of data accesses
1466system.cpu0.dcache.ReadReq_hits::cpu0.data 5867272 # number of ReadReq hits
1467system.cpu0.dcache.ReadReq_hits::total 5867272 # number of ReadReq hits
1468system.cpu0.dcache.WriteReq_hits::cpu0.data 3220606 # number of WriteReq hits
1469system.cpu0.dcache.WriteReq_hits::total 3220606 # number of WriteReq hits
1470system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139465 # number of LoadLockedReq hits
1471system.cpu0.dcache.LoadLockedReq_hits::total 139465 # number of LoadLockedReq hits
1472system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137168 # number of StoreCondReq hits
1473system.cpu0.dcache.StoreCondReq_hits::total 137168 # number of StoreCondReq hits
1474system.cpu0.dcache.demand_hits::cpu0.data 9087878 # number of demand (read+write) hits
1475system.cpu0.dcache.demand_hits::total 9087878 # number of demand (read+write) hits
1476system.cpu0.dcache.overall_hits::cpu0.data 9087878 # number of overall hits
1477system.cpu0.dcache.overall_hits::total 9087878 # number of overall hits
1478system.cpu0.dcache.ReadReq_misses::cpu0.data 403110 # number of ReadReq misses
1479system.cpu0.dcache.ReadReq_misses::total 403110 # number of ReadReq misses
1480system.cpu0.dcache.WriteReq_misses::cpu0.data 1588797 # number of WriteReq misses
1481system.cpu0.dcache.WriteReq_misses::total 1588797 # number of WriteReq misses
1482system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8920 # number of LoadLockedReq misses
1483system.cpu0.dcache.LoadLockedReq_misses::total 8920 # number of LoadLockedReq misses
1484system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7758 # number of StoreCondReq misses
1485system.cpu0.dcache.StoreCondReq_misses::total 7758 # number of StoreCondReq misses
1486system.cpu0.dcache.demand_misses::cpu0.data 1991907 # number of demand (read+write) misses
1487system.cpu0.dcache.demand_misses::total 1991907 # number of demand (read+write) misses
1488system.cpu0.dcache.overall_misses::cpu0.data 1991907 # number of overall misses
1489system.cpu0.dcache.overall_misses::total 1991907 # number of overall misses
1490system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5653636758 # number of ReadReq miss cycles
1491system.cpu0.dcache.ReadReq_miss_latency::total 5653636758 # number of ReadReq miss cycles
1492system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74855868606 # number of WriteReq miss cycles
1493system.cpu0.dcache.WriteReq_miss_latency::total 74855868606 # number of WriteReq miss cycles
1494system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91362982 # number of LoadLockedReq miss cycles
1495system.cpu0.dcache.LoadLockedReq_miss_latency::total 91362982 # number of LoadLockedReq miss cycles
1496system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50049767 # number of StoreCondReq miss cycles
1497system.cpu0.dcache.StoreCondReq_miss_latency::total 50049767 # number of StoreCondReq miss cycles
1498system.cpu0.dcache.demand_miss_latency::cpu0.data 80509505364 # number of demand (read+write) miss cycles
1499system.cpu0.dcache.demand_miss_latency::total 80509505364 # number of demand (read+write) miss cycles
1500system.cpu0.dcache.overall_miss_latency::cpu0.data 80509505364 # number of overall miss cycles
1501system.cpu0.dcache.overall_miss_latency::total 80509505364 # number of overall miss cycles
1502system.cpu0.dcache.ReadReq_accesses::cpu0.data 6270382 # number of ReadReq accesses(hits+misses)
1503system.cpu0.dcache.ReadReq_accesses::total 6270382 # number of ReadReq accesses(hits+misses)
1504system.cpu0.dcache.WriteReq_accesses::cpu0.data 4809403 # number of WriteReq accesses(hits+misses)
1505system.cpu0.dcache.WriteReq_accesses::total 4809403 # number of WriteReq accesses(hits+misses)
1506system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148385 # number of LoadLockedReq accesses(hits+misses)
1507system.cpu0.dcache.LoadLockedReq_accesses::total 148385 # number of LoadLockedReq accesses(hits+misses)
1508system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144926 # number of StoreCondReq accesses(hits+misses)
1509system.cpu0.dcache.StoreCondReq_accesses::total 144926 # number of StoreCondReq accesses(hits+misses)
1510system.cpu0.dcache.demand_accesses::cpu0.data 11079785 # number of demand (read+write) accesses
1511system.cpu0.dcache.demand_accesses::total 11079785 # number of demand (read+write) accesses
1512system.cpu0.dcache.overall_accesses::cpu0.data 11079785 # number of overall (read+write) accesses
1513system.cpu0.dcache.overall_accesses::total 11079785 # number of overall (read+write) accesses
1514system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.064288 # miss rate for ReadReq accesses
1515system.cpu0.dcache.ReadReq_miss_rate::total 0.064288 # miss rate for ReadReq accesses
1516system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330352 # miss rate for WriteReq accesses
1517system.cpu0.dcache.WriteReq_miss_rate::total 0.330352 # miss rate for WriteReq accesses
1518system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060114 # miss rate for LoadLockedReq accesses
1519system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.060114 # miss rate for LoadLockedReq accesses
1520system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053531 # miss rate for StoreCondReq accesses
1521system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053531 # miss rate for StoreCondReq accesses
1522system.cpu0.dcache.demand_miss_rate::cpu0.data 0.179778 # miss rate for demand accesses
1523system.cpu0.dcache.demand_miss_rate::total 0.179778 # miss rate for demand accesses
1524system.cpu0.dcache.overall_miss_rate::cpu0.data 0.179778 # miss rate for overall accesses
1525system.cpu0.dcache.overall_miss_rate::total 0.179778 # miss rate for overall accesses
1526system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14025.047153 # average ReadReq miss latency
1527system.cpu0.dcache.ReadReq_avg_miss_latency::total 14025.047153 # average ReadReq miss latency
1528system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 47114.809888 # average WriteReq miss latency
1529system.cpu0.dcache.WriteReq_avg_miss_latency::total 47114.809888 # average WriteReq miss latency
1530system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10242.486771 # average LoadLockedReq miss latency
1531system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10242.486771 # average LoadLockedReq miss latency
1532system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6451.374968 # average StoreCondReq miss latency
1533system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6451.374968 # average StoreCondReq miss latency
1534system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 40418.305355 # average overall miss latency
1535system.cpu0.dcache.demand_avg_miss_latency::total 40418.305355 # average overall miss latency
1536system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 40418.305355 # average overall miss latency
1537system.cpu0.dcache.overall_avg_miss_latency::total 40418.305355 # average overall miss latency
1538system.cpu0.dcache.blocked_cycles::no_mshrs 9294 # number of cycles access was blocked
1539system.cpu0.dcache.blocked_cycles::no_targets 6492 # number of cycles access was blocked
1540system.cpu0.dcache.blocked::no_mshrs 635 # number of cycles access was blocked
1541system.cpu0.dcache.blocked::no_targets 113 # number of cycles access was blocked
1542system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.636220 # average number of cycles each access was blocked
1543system.cpu0.dcache.avg_blocked_cycles::no_targets 57.451327 # average number of cycles each access was blocked
1544system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1545system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1546system.cpu0.dcache.writebacks::writebacks 255545 # number of writebacks
1547system.cpu0.dcache.writebacks::total 255545 # number of writebacks
1548system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 213826 # number of ReadReq MSHR hits
1549system.cpu0.dcache.ReadReq_mshr_hits::total 213826 # number of ReadReq MSHR hits
1550system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1457949 # number of WriteReq MSHR hits
1551system.cpu0.dcache.WriteReq_mshr_hits::total 1457949 # number of WriteReq MSHR hits
1552system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 469 # number of LoadLockedReq MSHR hits
1553system.cpu0.dcache.LoadLockedReq_mshr_hits::total 469 # number of LoadLockedReq MSHR hits
1554system.cpu0.dcache.demand_mshr_hits::cpu0.data 1671775 # number of demand (read+write) MSHR hits
1555system.cpu0.dcache.demand_mshr_hits::total 1671775 # number of demand (read+write) MSHR hits
1556system.cpu0.dcache.overall_mshr_hits::cpu0.data 1671775 # number of overall MSHR hits
1557system.cpu0.dcache.overall_mshr_hits::total 1671775 # number of overall MSHR hits
1558system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189284 # number of ReadReq MSHR misses
1559system.cpu0.dcache.ReadReq_mshr_misses::total 189284 # number of ReadReq MSHR misses
1560system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130848 # number of WriteReq MSHR misses
1561system.cpu0.dcache.WriteReq_mshr_misses::total 130848 # number of WriteReq MSHR misses
1562system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8451 # number of LoadLockedReq MSHR misses
1563system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8451 # number of LoadLockedReq MSHR misses
1564system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7758 # number of StoreCondReq MSHR misses
1565system.cpu0.dcache.StoreCondReq_mshr_misses::total 7758 # number of StoreCondReq MSHR misses
1566system.cpu0.dcache.demand_mshr_misses::cpu0.data 320132 # number of demand (read+write) MSHR misses
1567system.cpu0.dcache.demand_mshr_misses::total 320132 # number of demand (read+write) MSHR misses
1568system.cpu0.dcache.overall_mshr_misses::cpu0.data 320132 # number of overall MSHR misses
1569system.cpu0.dcache.overall_mshr_misses::total 320132 # number of overall MSHR misses
1570system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2416725188 # number of ReadReq MSHR miss cycles
1571system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2416725188 # number of ReadReq MSHR miss cycles
1572system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5154000431 # number of WriteReq MSHR miss cycles
1573system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5154000431 # number of WriteReq MSHR miss cycles
1574system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69605516 # number of LoadLockedReq MSHR miss cycles
1575system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69605516 # number of LoadLockedReq MSHR miss cycles
1576system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34529233 # number of StoreCondReq MSHR miss cycles
1577system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34529233 # number of StoreCondReq MSHR miss cycles
1578system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7570725619 # number of demand (read+write) MSHR miss cycles
1579system.cpu0.dcache.demand_mshr_miss_latency::total 7570725619 # number of demand (read+write) MSHR miss cycles
1580system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7570725619 # number of overall MSHR miss cycles
1581system.cpu0.dcache.overall_mshr_miss_latency::total 7570725619 # number of overall MSHR miss cycles
1582system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13434660545 # number of ReadReq MSHR uncacheable cycles
1583system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13434660545 # number of ReadReq MSHR uncacheable cycles
1584system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1206058380 # number of WriteReq MSHR uncacheable cycles
1585system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1206058380 # number of WriteReq MSHR uncacheable cycles
1586system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14640718925 # number of overall MSHR uncacheable cycles
1587system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14640718925 # number of overall MSHR uncacheable cycles
1588system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030187 # mshr miss rate for ReadReq accesses
1589system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030187 # mshr miss rate for ReadReq accesses
1590system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027207 # mshr miss rate for WriteReq accesses
1591system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027207 # mshr miss rate for WriteReq accesses
1592system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056953 # mshr miss rate for LoadLockedReq accesses
1593system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056953 # mshr miss rate for LoadLockedReq accesses
1594system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053531 # mshr miss rate for StoreCondReq accesses
1595system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053531 # mshr miss rate for StoreCondReq accesses
1596system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028893 # mshr miss rate for demand accesses
1597system.cpu0.dcache.demand_mshr_miss_rate::total 0.028893 # mshr miss rate for demand accesses
1598system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028893 # mshr miss rate for overall accesses
1599system.cpu0.dcache.overall_mshr_miss_rate::total 0.028893 # mshr miss rate for overall accesses
1600system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12767.720399 # average ReadReq mshr miss latency
1601system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12767.720399 # average ReadReq mshr miss latency
1602system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39389.218261 # average WriteReq mshr miss latency
1603system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39389.218261 # average WriteReq mshr miss latency
1604system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8236.364454 # average LoadLockedReq mshr miss latency
1605system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8236.364454 # average LoadLockedReq mshr miss latency
1606system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4450.790539 # average StoreCondReq mshr miss latency
1607system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4450.790539 # average StoreCondReq mshr miss latency
1608system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23648.762445 # average overall mshr miss latency
1609system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23648.762445 # average overall mshr miss latency
1610system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23648.762445 # average overall mshr miss latency
1611system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23648.762445 # average overall mshr miss latency
1612system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1613system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1614system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1615system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1616system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1617system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1618system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1619system.cpu1.branchPred.lookups 9402679 # Number of BP lookups
1620system.cpu1.branchPred.condPredicted 7728805 # Number of conditional branches predicted
1621system.cpu1.branchPred.condIncorrect 418099 # Number of conditional branches incorrect
1622system.cpu1.branchPred.BTBLookups 6037829 # Number of BTB lookups
1623system.cpu1.branchPred.BTBHits 5108046 # Number of BTB hits
1624system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1625system.cpu1.branchPred.BTBHitPct 84.600707 # BTB Hit Percentage
1626system.cpu1.branchPred.usedRAS 802186 # Number of times the RAS was used to get a target.
1627system.cpu1.branchPred.RASInCorrect 44176 # Number of incorrect RAS predictions.
1628system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1629system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1630system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1631system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1632system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1633system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1634system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1635system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 7 unchanged lines hidden (view full) ---

1643system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1644system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1645system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1646system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1647system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1648system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1649system.cpu1.dtb.inst_hits 0 # ITB inst hits
1650system.cpu1.dtb.inst_misses 0 # ITB inst misses
1651system.cpu1.dtb.read_hits 42878527 # DTB read hits
1652system.cpu1.dtb.read_misses 38253 # DTB read misses
1653system.cpu1.dtb.write_hits 6985734 # DTB write hits
1654system.cpu1.dtb.write_misses 10793 # DTB write misses
1655system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
1656system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1657system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1658system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1659system.cpu1.dtb.flush_entries 1922 # Number of entries that have been flushed from TLB
1660system.cpu1.dtb.align_faults 2963 # Number of TLB faults due to alignment restrictions
1661system.cpu1.dtb.prefetch_faults 279 # Number of TLB faults due to prefetch
1662system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1663system.cpu1.dtb.perms_faults 687 # Number of TLB faults due to permissions restrictions
1664system.cpu1.dtb.read_accesses 42916780 # DTB read accesses
1665system.cpu1.dtb.write_accesses 6996527 # DTB write accesses
1666system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1667system.cpu1.dtb.hits 49864261 # DTB hits
1668system.cpu1.dtb.misses 49046 # DTB misses
1669system.cpu1.dtb.accesses 49913307 # DTB accesses
1670system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1671system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1672system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1673system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1674system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1675system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1676system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1677system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

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1683system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1684system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1685system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1686system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1687system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1688system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1689system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1690system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1691system.cpu1.itb.inst_hits 7755980 # ITB inst hits
1692system.cpu1.itb.inst_misses 5491 # ITB inst misses
1693system.cpu1.itb.read_hits 0 # DTB read hits
1694system.cpu1.itb.read_misses 0 # DTB read misses
1695system.cpu1.itb.write_hits 0 # DTB write hits
1696system.cpu1.itb.write_misses 0 # DTB write misses
1697system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
1698system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1699system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1700system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1701system.cpu1.itb.flush_entries 1362 # Number of entries that have been flushed from TLB
1702system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1703system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1704system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1705system.cpu1.itb.perms_faults 1507 # Number of TLB faults due to permissions restrictions
1706system.cpu1.itb.read_accesses 0 # DTB read accesses
1707system.cpu1.itb.write_accesses 0 # DTB write accesses
1708system.cpu1.itb.inst_accesses 7761471 # ITB inst accesses
1709system.cpu1.itb.hits 7755980 # DTB hits
1710system.cpu1.itb.misses 5491 # DTB misses
1711system.cpu1.itb.accesses 7761471 # DTB accesses
1712system.cpu1.numCycles 413132210 # number of cpu cycles simulated
1713system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1714system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1715system.cpu1.fetch.icacheStallCycles 19420388 # Number of cycles fetch is stalled on an Icache miss
1716system.cpu1.fetch.Insts 61788688 # Number of instructions fetch has processed
1717system.cpu1.fetch.Branches 9402679 # Number of branches that fetch encountered
1718system.cpu1.fetch.predictedBranches 5910232 # Number of branches that fetch has predicted taken
1719system.cpu1.fetch.Cycles 13466568 # Number of cycles fetch has run and was not squashing or blocked
1720system.cpu1.fetch.SquashCycles 3411318 # Number of cycles fetch has spent squashing
1721system.cpu1.fetch.TlbCycles 67616 # Number of cycles fetch has spent waiting for tlb
1722system.cpu1.fetch.BlockedCycles 77041165 # Number of cycles fetch has spent blocked
1723system.cpu1.fetch.MiscStallCycles 5941 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1724system.cpu1.fetch.PendingTrapStallCycles 42813 # Number of stall cycles due to pending traps
1725system.cpu1.fetch.PendingQuiesceStallCycles 1523639 # Number of stall cycles due to pending quiesce instructions
1726system.cpu1.fetch.IcacheWaitRetryStallCycles 257 # Number of stall cycles due to full MSHR
1727system.cpu1.fetch.CacheLines 7754163 # Number of cache lines fetched
1728system.cpu1.fetch.IcacheSquashes 555305 # Number of outstanding Icache misses that were squashed
1729system.cpu1.fetch.ItlbSquashes 2851 # Number of outstanding ITLB misses that were squashed
1730system.cpu1.fetch.rateDist::samples 113918823 # Number of instructions fetched each cycle (Total)
1731system.cpu1.fetch.rateDist::mean 0.663934 # Number of instructions fetched each cycle (Total)
1732system.cpu1.fetch.rateDist::stdev 1.994464 # Number of instructions fetched each cycle (Total)
1733system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1734system.cpu1.fetch.rateDist::0 100459727 88.19% 88.19% # Number of instructions fetched each cycle (Total)
1735system.cpu1.fetch.rateDist::1 820479 0.72% 88.91% # Number of instructions fetched each cycle (Total)
1736system.cpu1.fetch.rateDist::2 969052 0.85% 89.76% # Number of instructions fetched each cycle (Total)
1737system.cpu1.fetch.rateDist::3 1718827 1.51% 91.27% # Number of instructions fetched each cycle (Total)
1738system.cpu1.fetch.rateDist::4 1427854 1.25% 92.52% # Number of instructions fetched each cycle (Total)
1739system.cpu1.fetch.rateDist::5 590556 0.52% 93.04% # Number of instructions fetched each cycle (Total)
1740system.cpu1.fetch.rateDist::6 1988498 1.75% 94.78% # Number of instructions fetched each cycle (Total)
1741system.cpu1.fetch.rateDist::7 426289 0.37% 95.16% # Number of instructions fetched each cycle (Total)
1742system.cpu1.fetch.rateDist::8 5517541 4.84% 100.00% # Number of instructions fetched each cycle (Total)
1743system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1744system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1745system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1746system.cpu1.fetch.rateDist::total 113918823 # Number of instructions fetched each cycle (Total)
1747system.cpu1.fetch.branchRate 0.022759 # Number of branch fetches per cycle
1748system.cpu1.fetch.rate 0.149562 # Number of inst fetches per cycle
1749system.cpu1.decode.IdleCycles 20573629 # Number of cycles decode is idle
1750system.cpu1.decode.BlockedCycles 78271180 # Number of cycles decode is blocked
1751system.cpu1.decode.RunCycles 12141436 # Number of cycles decode is running
1752system.cpu1.decode.UnblockCycles 681674 # Number of cycles decode is unblocking
1753system.cpu1.decode.SquashCycles 2250904 # Number of cycles decode is squashing
1754system.cpu1.decode.BranchResolved 1146333 # Number of times decode resolved a branch
1755system.cpu1.decode.BranchMispred 101070 # Number of times decode detected a branch misprediction
1756system.cpu1.decode.DecodedInsts 71648546 # Number of instructions handled by decode
1757system.cpu1.decode.SquashedInsts 337709 # Number of squashed instructions handled by decode
1758system.cpu1.rename.SquashCycles 2250904 # Number of cycles rename is squashing
1759system.cpu1.rename.IdleCycles 21753755 # Number of cycles rename is idle
1760system.cpu1.rename.BlockCycles 11785871 # Number of cycles rename is blocking
1761system.cpu1.rename.serializeStallCycles 44839476 # count of cycles rename stalled for serializing inst
1762system.cpu1.rename.RunCycles 11758144 # Number of cycles rename is running
1763system.cpu1.rename.UnblockCycles 21530673 # Number of cycles rename is unblocking
1764system.cpu1.rename.RenamedInsts 67615561 # Number of instructions processed by rename
1765system.cpu1.rename.ROBFullEvents 613 # Number of times rename has blocked due to ROB full
1766system.cpu1.rename.IQFullEvents 15671923 # Number of times rename has blocked due to IQ full
1767system.cpu1.rename.LQFullEvents 18336953 # Number of times rename has blocked due to LQ full
1768system.cpu1.rename.SQFullEvents 1545811 # Number of times rename has blocked due to SQ full
1769system.cpu1.rename.FullRegisterEvents 1295 # Number of times there has been no free registers
1770system.cpu1.rename.RenamedOperands 71310682 # Number of destination operands rename has renamed
1771system.cpu1.rename.RenameLookups 315205355 # Number of register rename lookups that rename has made
1772system.cpu1.rename.int_rename_lookups 288681323 # Number of integer rename lookups
1773system.cpu1.rename.fp_rename_lookups 6622 # Number of floating rename lookups
1774system.cpu1.rename.CommittedMaps 50413608 # Number of HB maps that are committed
1775system.cpu1.rename.UndoneMaps 20897074 # Number of HB maps that are undone due to squashing
1776system.cpu1.rename.serializingInsts 766814 # count of serializing insts renamed
1777system.cpu1.rename.tempSerializingInsts 706637 # count of temporary serializing insts renamed
1778system.cpu1.rename.skidInsts 7207016 # count of insts added to the skid buffer
1779system.cpu1.memDep0.insertedLoads 12951593 # Number of loads inserted to the mem dependence unit.
1780system.cpu1.memDep0.insertedStores 8155935 # Number of stores inserted to the mem dependence unit.
1781system.cpu1.memDep0.conflictingLoads 1106689 # Number of conflicting loads.
1782system.cpu1.memDep0.conflictingStores 1533453 # Number of conflicting stores.
1783system.cpu1.iq.iqInstsAdded 62295252 # Number of instructions added to the IQ (excludes non-spec)
1784system.cpu1.iq.iqNonSpecInstsAdded 1184366 # Number of non-speculative instructions added to the IQ
1785system.cpu1.iq.iqInstsIssued 88905891 # Number of instructions issued
1786system.cpu1.iq.iqSquashedInstsIssued 106644 # Number of squashed instructions issued
1787system.cpu1.iq.iqSquashedInstsExamined 13983630 # Number of squashed instructions iterated over during squash; mainly for profiling
1788system.cpu1.iq.iqSquashedOperandsExamined 37714490 # Number of squashed operands that are examined and possibly removed from graph
1789system.cpu1.iq.iqSquashedNonSpecRemoved 285025 # Number of squashed non-spec instructions that were removed
1790system.cpu1.iq.issued_per_cycle::samples 113918823 # Number of insts issued each cycle
1791system.cpu1.iq.issued_per_cycle::mean 0.780432 # Number of insts issued each cycle
1792system.cpu1.iq.issued_per_cycle::stdev 1.530885 # Number of insts issued each cycle
1793system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1794system.cpu1.iq.issued_per_cycle::0 83813472 73.57% 73.57% # Number of insts issued each cycle
1795system.cpu1.iq.issued_per_cycle::1 8528665 7.49% 81.06% # Number of insts issued each cycle
1796system.cpu1.iq.issued_per_cycle::2 3988574 3.50% 84.56% # Number of insts issued each cycle
1797system.cpu1.iq.issued_per_cycle::3 3433815 3.01% 87.58% # Number of insts issued each cycle
1798system.cpu1.iq.issued_per_cycle::4 10704573 9.40% 96.97% # Number of insts issued each cycle
1799system.cpu1.iq.issued_per_cycle::5 1891022 1.66% 98.63% # Number of insts issued each cycle
1800system.cpu1.iq.issued_per_cycle::6 1169449 1.03% 99.66% # Number of insts issued each cycle
1801system.cpu1.iq.issued_per_cycle::7 305487 0.27% 99.93% # Number of insts issued each cycle
1802system.cpu1.iq.issued_per_cycle::8 83766 0.07% 100.00% # Number of insts issued each cycle
1803system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1804system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1805system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1806system.cpu1.iq.issued_per_cycle::total 113918823 # Number of insts issued each cycle
1807system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1808system.cpu1.iq.fu_full::IntAlu 34951 0.44% 0.44% # attempts to use FU when none available
1809system.cpu1.iq.fu_full::IntMult 989 0.01% 0.45% # attempts to use FU when none available
1810system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.45% # attempts to use FU when none available
1811system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.45% # attempts to use FU when none available
1812system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.45% # attempts to use FU when none available
1813system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.45% # attempts to use FU when none available
1814system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.45% # attempts to use FU when none available
1815system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.45% # attempts to use FU when none available
1816system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.45% # attempts to use FU when none available
1817system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.45% # attempts to use FU when none available
1818system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.45% # attempts to use FU when none available
1819system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.45% # attempts to use FU when none available
1820system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.45% # attempts to use FU when none available
1821system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.45% # attempts to use FU when none available
1822system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.45% # attempts to use FU when none available
1823system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.45% # attempts to use FU when none available
1824system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.45% # attempts to use FU when none available
1825system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.45% # attempts to use FU when none available
1826system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.45% # attempts to use FU when none available
1827system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.45% # attempts to use FU when none available
1828system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.45% # attempts to use FU when none available
1829system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.45% # attempts to use FU when none available
1830system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.45% # attempts to use FU when none available
1831system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.45% # attempts to use FU when none available
1832system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.45% # attempts to use FU when none available
1833system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.45% # attempts to use FU when none available
1834system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.45% # attempts to use FU when none available
1835system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.45% # attempts to use FU when none available
1836system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.45% # attempts to use FU when none available
1837system.cpu1.iq.fu_full::MemRead 7593663 95.44% 95.90% # attempts to use FU when none available
1838system.cpu1.iq.fu_full::MemWrite 326577 4.10% 100.00% # attempts to use FU when none available
1839system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1840system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1841system.cpu1.iq.FU_type_0::No_OpClass 14267 0.02% 0.02% # Type of FU issued
1842system.cpu1.iq.FU_type_0::IntAlu 37698483 42.40% 42.42% # Type of FU issued
1843system.cpu1.iq.FU_type_0::IntMult 61348 0.07% 42.49% # Type of FU issued
1844system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.49% # Type of FU issued
1845system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.49% # Type of FU issued
1846system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.49% # Type of FU issued
1847system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.49% # Type of FU issued
1848system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.49% # Type of FU issued
1849system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.49% # Type of FU issued
1850system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.49% # Type of FU issued
1851system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.49% # Type of FU issued
1852system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.49% # Type of FU issued
1853system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.49% # Type of FU issued
1854system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.49% # Type of FU issued
1855system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.49% # Type of FU issued
1856system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.49% # Type of FU issued
1857system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.49% # Type of FU issued
1858system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.49% # Type of FU issued
1859system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.49% # Type of FU issued
1860system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.49% # Type of FU issued
1861system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.49% # Type of FU issued
1862system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.49% # Type of FU issued
1863system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.49% # Type of FU issued
1864system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.49% # Type of FU issued
1865system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.49% # Type of FU issued
1866system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.49% # Type of FU issued
1867system.cpu1.iq.FU_type_0::SimdFloatMisc 1706 0.00% 42.49% # Type of FU issued
1868system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.49% # Type of FU issued
1869system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.49% # Type of FU issued
1870system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.49% # Type of FU issued
1871system.cpu1.iq.FU_type_0::MemRead 43772925 49.24% 91.72% # Type of FU issued
1872system.cpu1.iq.FU_type_0::MemWrite 7357130 8.28% 100.00% # Type of FU issued
1873system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1874system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1875system.cpu1.iq.FU_type_0::total 88905891 # Type of FU issued
1876system.cpu1.iq.rate 0.215200 # Inst issue rate
1877system.cpu1.iq.fu_busy_cnt 7956180 # FU busy when requested
1878system.cpu1.iq.fu_busy_rate 0.089490 # FU busy rate (busy events/executed inst)
1879system.cpu1.iq.int_inst_queue_reads 299826864 # Number of integer instruction queue reads
1880system.cpu1.iq.int_inst_queue_writes 77472999 # Number of integer instruction queue writes
1881system.cpu1.iq.int_inst_queue_wakeup_accesses 54370047 # Number of integer instruction queue wakeup accesses
1882system.cpu1.iq.fp_inst_queue_reads 15424 # Number of floating instruction queue reads
1883system.cpu1.iq.fp_inst_queue_writes 8128 # Number of floating instruction queue writes
1884system.cpu1.iq.fp_inst_queue_wakeup_accesses 6867 # Number of floating instruction queue wakeup accesses
1885system.cpu1.iq.int_alu_accesses 96839621 # Number of integer alu accesses
1886system.cpu1.iq.fp_alu_accesses 8183 # Number of floating point alu accesses
1887system.cpu1.iew.lsq.thread0.forwLoads 371805 # Number of loads that had data forwarded from stores
1888system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1889system.cpu1.iew.lsq.thread0.squashedLoads 2971595 # Number of loads squashed
1890system.cpu1.iew.lsq.thread0.ignoredResponses 3826 # Number of memory responses ignored because the instruction is squashed
1891system.cpu1.iew.lsq.thread0.memOrderViolation 18443 # Number of memory ordering violations
1892system.cpu1.iew.lsq.thread0.squashedStores 1153168 # Number of stores squashed
1893system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1894system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1895system.cpu1.iew.lsq.thread0.rescheduledLoads 31846626 # Number of loads that were rescheduled
1896system.cpu1.iew.lsq.thread0.cacheBlocked 675699 # Number of times an access to memory failed due to the cache being blocked
1897system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1898system.cpu1.iew.iewSquashCycles 2250904 # Number of cycles IEW is squashing
1899system.cpu1.iew.iewBlockCycles 9489416 # Number of cycles IEW is blocking
1900system.cpu1.iew.iewUnblockCycles 1235015 # Number of cycles IEW is unblocking
1901system.cpu1.iew.iewDispatchedInsts 63585663 # Number of instructions dispatched to IQ
1902system.cpu1.iew.iewDispSquashedInsts 104803 # Number of squashed instructions skipped by dispatch
1903system.cpu1.iew.iewDispLoadInsts 12951593 # Number of dispatched load instructions
1904system.cpu1.iew.iewDispStoreInsts 8155935 # Number of dispatched store instructions
1905system.cpu1.iew.iewDispNonSpecInsts 886916 # Number of dispatched non-speculative instructions
1906system.cpu1.iew.iewIQFullEvents 232294 # Number of times the IQ has become full, causing a stall
1907system.cpu1.iew.iewLSQFullEvents 885959 # Number of times the LSQ has become full, causing a stall
1908system.cpu1.iew.memOrderViolationEvents 18443 # Number of memory order violations
1909system.cpu1.iew.predictedTakenIncorrect 206591 # Number of branches that were predicted taken incorrectly
1910system.cpu1.iew.predictedNotTakenIncorrect 158855 # Number of branches that were predicted not taken incorrectly
1911system.cpu1.iew.branchMispredicts 365446 # Number of branch mispredicts detected at execute
1912system.cpu1.iew.iewExecutedInsts 87166570 # Number of executed instructions
1913system.cpu1.iew.iewExecLoadInsts 43262018 # Number of load instructions executed
1914system.cpu1.iew.iewExecSquashedInsts 1739321 # Number of squashed instructions skipped in execute
1915system.cpu1.iew.exec_swp 0 # number of swp insts executed
1916system.cpu1.iew.exec_nop 106045 # number of nop insts executed
1917system.cpu1.iew.exec_refs 50553896 # number of memory reference insts executed
1918system.cpu1.iew.exec_branches 7398817 # Number of branches executed
1919system.cpu1.iew.exec_stores 7291878 # Number of stores executed
1920system.cpu1.iew.exec_rate 0.210990 # Inst execution rate
1921system.cpu1.iew.wb_sent 86399299 # cumulative count of insts sent to commit
1922system.cpu1.iew.wb_count 54376914 # cumulative count of insts written-back
1923system.cpu1.iew.wb_producers 30829889 # num instructions producing a value
1924system.cpu1.iew.wb_consumers 55266228 # num instructions consuming a value
1925system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1926system.cpu1.iew.wb_rate 0.131621 # insts written-back per cycle
1927system.cpu1.iew.wb_fanout 0.557843 # average fanout of values written-back
1928system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1929system.cpu1.commit.commitSquashedInsts 13879712 # The number of squashed insts skipped by commit
1930system.cpu1.commit.commitNonSpecStalls 899341 # The number of times commit has been forced to stall to communicate backwards
1931system.cpu1.commit.branchMispredicts 318567 # The number of times a branch was mispredicted
1932system.cpu1.commit.committed_per_cycle::samples 111667919 # Number of insts commited each cycle
1933system.cpu1.commit.committed_per_cycle::mean 0.440684 # Number of insts commited each cycle
1934system.cpu1.commit.committed_per_cycle::stdev 1.404622 # Number of insts commited each cycle
1935system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1936system.cpu1.commit.committed_per_cycle::0 93786179 83.99% 83.99% # Number of insts commited each cycle
1937system.cpu1.commit.committed_per_cycle::1 9487781 8.50% 92.48% # Number of insts commited each cycle
1938system.cpu1.commit.committed_per_cycle::2 2098555 1.88% 94.36% # Number of insts commited each cycle
1939system.cpu1.commit.committed_per_cycle::3 1338170 1.20% 95.56% # Number of insts commited each cycle
1940system.cpu1.commit.committed_per_cycle::4 960614 0.86% 96.42% # Number of insts commited each cycle
1941system.cpu1.commit.committed_per_cycle::5 571645 0.51% 96.93% # Number of insts commited each cycle
1942system.cpu1.commit.committed_per_cycle::6 1030883 0.92% 97.86% # Number of insts commited each cycle
1943system.cpu1.commit.committed_per_cycle::7 527820 0.47% 98.33% # Number of insts commited each cycle
1944system.cpu1.commit.committed_per_cycle::8 1866272 1.67% 100.00% # Number of insts commited each cycle
1945system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1946system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1947system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1948system.cpu1.commit.committed_per_cycle::total 111667919 # Number of insts commited each cycle
1949system.cpu1.commit.committedInsts 38872746 # Number of instructions committed
1950system.cpu1.commit.committedOps 49210296 # Number of ops (including micro ops) committed
1951system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
1952system.cpu1.commit.refs 16982765 # Number of memory references committed
1953system.cpu1.commit.loads 9979998 # Number of loads committed
1954system.cpu1.commit.membars 195533 # Number of memory barriers committed
1955system.cpu1.commit.branches 6424967 # Number of branches committed
1956system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions.
1957system.cpu1.commit.int_insts 43922606 # Number of committed integer instructions.
1958system.cpu1.commit.function_calls 553368 # Number of function calls committed.
1959system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
1960system.cpu1.commit.op_class_0::IntAlu 32167564 65.37% 65.37% # Class of committed instruction
1961system.cpu1.commit.op_class_0::IntMult 58261 0.12% 65.49% # Class of committed instruction
1962system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.49% # Class of committed instruction
1963system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.49% # Class of committed instruction
1964system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.49% # Class of committed instruction
1965system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.49% # Class of committed instruction
1966system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.49% # Class of committed instruction
1967system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.49% # Class of committed instruction
1968system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.49% # Class of committed instruction
1969system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.49% # Class of committed instruction
1970system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.49% # Class of committed instruction
1971system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.49% # Class of committed instruction
1972system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.49% # Class of committed instruction
1973system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.49% # Class of committed instruction
1974system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.49% # Class of committed instruction
1975system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.49% # Class of committed instruction
1976system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.49% # Class of committed instruction
1977system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.49% # Class of committed instruction
1978system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.49% # Class of committed instruction
1979system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.49% # Class of committed instruction
1980system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.49% # Class of committed instruction
1981system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.49% # Class of committed instruction
1982system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.49% # Class of committed instruction
1983system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.49% # Class of committed instruction
1984system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.49% # Class of committed instruction
1985system.cpu1.commit.op_class_0::SimdFloatMisc 1706 0.00% 65.49% # Class of committed instruction
1986system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.49% # Class of committed instruction
1987system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.49% # Class of committed instruction
1988system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.49% # Class of committed instruction
1989system.cpu1.commit.op_class_0::MemRead 9979998 20.28% 85.77% # Class of committed instruction
1990system.cpu1.commit.op_class_0::MemWrite 7002767 14.23% 100.00% # Class of committed instruction
1991system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1992system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
1993system.cpu1.commit.op_class_0::total 49210296 # Class of committed instruction
1994system.cpu1.commit.bw_lim_events 1866272 # number cycles where commit BW limit reached
1995system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
1996system.cpu1.rob.rob_reads 171825162 # The number of ROB reads
1997system.cpu1.rob.rob_writes 128514038 # The number of ROB writes
1998system.cpu1.timesIdled 1427088 # Number of times that the entire CPU went into an idle state and unscheduled itself
1999system.cpu1.idleCycles 299213387 # Total number of cycles that the CPU has spent unscheduled due to idling
2000system.cpu1.quiesceCycles 4796716848 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2001system.cpu1.committedInsts 38803107 # Number of Instructions Simulated
2002system.cpu1.committedOps 49140657 # Number of Ops (including micro ops) Simulated
2003system.cpu1.cpi 10.646885 # CPI: Cycles Per Instruction
2004system.cpu1.cpi_total 10.646885 # CPI: Total CPI of All Threads
2005system.cpu1.ipc 0.093924 # IPC: Instructions Per Cycle
2006system.cpu1.ipc_total 0.093924 # IPC: Total IPC of All Threads
2007system.cpu1.int_regfile_reads 391718305 # number of integer regfile reads
2008system.cpu1.int_regfile_writes 56505033 # number of integer regfile writes
2009system.cpu1.fp_regfile_reads 5108 # number of floating regfile reads
2010system.cpu1.fp_regfile_writes 2336 # number of floating regfile writes
2011system.cpu1.misc_regfile_reads 199117817 # number of misc regfile reads
2012system.cpu1.misc_regfile_writes 722972 # number of misc regfile writes
2013system.cpu1.icache.tags.replacements 616464 # number of replacements
2014system.cpu1.icache.tags.tagsinuse 498.721065 # Cycle average of tags in use
2015system.cpu1.icache.tags.total_refs 7090163 # Total number of references to valid blocks.
2016system.cpu1.icache.tags.sampled_refs 616976 # Sample count of references to valid blocks.
2017system.cpu1.icache.tags.avg_refs 11.491797 # Average number of references to valid blocks.
2018system.cpu1.icache.tags.warmup_cycle 74744507500 # Cycle when the warmup percentage was hit.
2019system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.721065 # Average occupied blocks per requestor
2020system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974065 # Average percentage of cache occupancy
2021system.cpu1.icache.tags.occ_percent::total 0.974065 # Average percentage of cache occupancy
2022system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2023system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
2024system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2025system.cpu1.icache.tags.tag_accesses 8371129 # Number of tag accesses
2026system.cpu1.icache.tags.data_accesses 8371129 # Number of data accesses
2027system.cpu1.icache.ReadReq_hits::cpu1.inst 7090163 # number of ReadReq hits
2028system.cpu1.icache.ReadReq_hits::total 7090163 # number of ReadReq hits
2029system.cpu1.icache.demand_hits::cpu1.inst 7090163 # number of demand (read+write) hits
2030system.cpu1.icache.demand_hits::total 7090163 # number of demand (read+write) hits
2031system.cpu1.icache.overall_hits::cpu1.inst 7090163 # number of overall hits
2032system.cpu1.icache.overall_hits::total 7090163 # number of overall hits
2033system.cpu1.icache.ReadReq_misses::cpu1.inst 663949 # number of ReadReq misses
2034system.cpu1.icache.ReadReq_misses::total 663949 # number of ReadReq misses
2035system.cpu1.icache.demand_misses::cpu1.inst 663949 # number of demand (read+write) misses
2036system.cpu1.icache.demand_misses::total 663949 # number of demand (read+write) misses
2037system.cpu1.icache.overall_misses::cpu1.inst 663949 # number of overall misses
2038system.cpu1.icache.overall_misses::total 663949 # number of overall misses
2039system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9003300184 # number of ReadReq miss cycles
2040system.cpu1.icache.ReadReq_miss_latency::total 9003300184 # number of ReadReq miss cycles
2041system.cpu1.icache.demand_miss_latency::cpu1.inst 9003300184 # number of demand (read+write) miss cycles
2042system.cpu1.icache.demand_miss_latency::total 9003300184 # number of demand (read+write) miss cycles
2043system.cpu1.icache.overall_miss_latency::cpu1.inst 9003300184 # number of overall miss cycles
2044system.cpu1.icache.overall_miss_latency::total 9003300184 # number of overall miss cycles
2045system.cpu1.icache.ReadReq_accesses::cpu1.inst 7754112 # number of ReadReq accesses(hits+misses)
2046system.cpu1.icache.ReadReq_accesses::total 7754112 # number of ReadReq accesses(hits+misses)
2047system.cpu1.icache.demand_accesses::cpu1.inst 7754112 # number of demand (read+write) accesses
2048system.cpu1.icache.demand_accesses::total 7754112 # number of demand (read+write) accesses
2049system.cpu1.icache.overall_accesses::cpu1.inst 7754112 # number of overall (read+write) accesses
2050system.cpu1.icache.overall_accesses::total 7754112 # number of overall (read+write) accesses
2051system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085625 # miss rate for ReadReq accesses
2052system.cpu1.icache.ReadReq_miss_rate::total 0.085625 # miss rate for ReadReq accesses
2053system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085625 # miss rate for demand accesses
2054system.cpu1.icache.demand_miss_rate::total 0.085625 # miss rate for demand accesses
2055system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085625 # miss rate for overall accesses
2056system.cpu1.icache.overall_miss_rate::total 0.085625 # miss rate for overall accesses
2057system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13560.228548 # average ReadReq miss latency
2058system.cpu1.icache.ReadReq_avg_miss_latency::total 13560.228548 # average ReadReq miss latency
2059system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13560.228548 # average overall miss latency
2060system.cpu1.icache.demand_avg_miss_latency::total 13560.228548 # average overall miss latency
2061system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13560.228548 # average overall miss latency
2062system.cpu1.icache.overall_avg_miss_latency::total 13560.228548 # average overall miss latency
2063system.cpu1.icache.blocked_cycles::no_mshrs 3101 # number of cycles access was blocked
2064system.cpu1.icache.blocked_cycles::no_targets 648 # number of cycles access was blocked
2065system.cpu1.icache.blocked::no_mshrs 217 # number of cycles access was blocked
2066system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
2067system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.290323 # average number of cycles each access was blocked
2068system.cpu1.icache.avg_blocked_cycles::no_targets 648 # average number of cycles each access was blocked
2069system.cpu1.icache.fast_writes 0 # number of fast writes performed
2070system.cpu1.icache.cache_copies 0 # number of cache copies performed
2071system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46932 # number of ReadReq MSHR hits
2072system.cpu1.icache.ReadReq_mshr_hits::total 46932 # number of ReadReq MSHR hits
2073system.cpu1.icache.demand_mshr_hits::cpu1.inst 46932 # number of demand (read+write) MSHR hits
2074system.cpu1.icache.demand_mshr_hits::total 46932 # number of demand (read+write) MSHR hits
2075system.cpu1.icache.overall_mshr_hits::cpu1.inst 46932 # number of overall MSHR hits
2076system.cpu1.icache.overall_mshr_hits::total 46932 # number of overall MSHR hits
2077system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 617017 # number of ReadReq MSHR misses
2078system.cpu1.icache.ReadReq_mshr_misses::total 617017 # number of ReadReq MSHR misses
2079system.cpu1.icache.demand_mshr_misses::cpu1.inst 617017 # number of demand (read+write) MSHR misses
2080system.cpu1.icache.demand_mshr_misses::total 617017 # number of demand (read+write) MSHR misses
2081system.cpu1.icache.overall_mshr_misses::cpu1.inst 617017 # number of overall MSHR misses
2082system.cpu1.icache.overall_mshr_misses::total 617017 # number of overall MSHR misses
2083system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7343865656 # number of ReadReq MSHR miss cycles
2084system.cpu1.icache.ReadReq_mshr_miss_latency::total 7343865656 # number of ReadReq MSHR miss cycles
2085system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7343865656 # number of demand (read+write) MSHR miss cycles
2086system.cpu1.icache.demand_mshr_miss_latency::total 7343865656 # number of demand (read+write) MSHR miss cycles
2087system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7343865656 # number of overall MSHR miss cycles
2088system.cpu1.icache.overall_mshr_miss_latency::total 7343865656 # number of overall MSHR miss cycles
2089system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4135000 # number of ReadReq MSHR uncacheable cycles
2090system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4135000 # number of ReadReq MSHR uncacheable cycles
2091system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4135000 # number of overall MSHR uncacheable cycles
2092system.cpu1.icache.overall_mshr_uncacheable_latency::total 4135000 # number of overall MSHR uncacheable cycles
2093system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079573 # mshr miss rate for ReadReq accesses
2094system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079573 # mshr miss rate for ReadReq accesses
2095system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079573 # mshr miss rate for demand accesses
2096system.cpu1.icache.demand_mshr_miss_rate::total 0.079573 # mshr miss rate for demand accesses
2097system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079573 # mshr miss rate for overall accesses
2098system.cpu1.icache.overall_mshr_miss_rate::total 0.079573 # mshr miss rate for overall accesses
2099system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11902.209592 # average ReadReq mshr miss latency
2100system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11902.209592 # average ReadReq mshr miss latency
2101system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11902.209592 # average overall mshr miss latency
2102system.cpu1.icache.demand_avg_mshr_miss_latency::total 11902.209592 # average overall mshr miss latency
2103system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11902.209592 # average overall mshr miss latency
2104system.cpu1.icache.overall_avg_mshr_miss_latency::total 11902.209592 # average overall mshr miss latency
2105system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
2106system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2107system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
2108system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2109system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2110system.cpu1.dcache.tags.replacements 363234 # number of replacements
2111system.cpu1.dcache.tags.tagsinuse 485.053035 # Cycle average of tags in use
2112system.cpu1.dcache.tags.total_refs 13011922 # Total number of references to valid blocks.
2113system.cpu1.dcache.tags.sampled_refs 363603 # Sample count of references to valid blocks.
2114system.cpu1.dcache.tags.avg_refs 35.786069 # Average number of references to valid blocks.
2115system.cpu1.dcache.tags.warmup_cycle 70837218250 # Cycle when the warmup percentage was hit.
2116system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.053035 # Average occupied blocks per requestor
2117system.cpu1.dcache.tags.occ_percent::cpu1.data 0.947369 # Average percentage of cache occupancy
2118system.cpu1.dcache.tags.occ_percent::total 0.947369 # Average percentage of cache occupancy
2119system.cpu1.dcache.tags.occ_task_id_blocks::1024 369 # Occupied blocks per task id
2120system.cpu1.dcache.tags.age_task_id_blocks_1024::2 369 # Occupied blocks per task id
2121system.cpu1.dcache.tags.occ_task_id_percent::1024 0.720703 # Percentage of cache occupancy per task id
2122system.cpu1.dcache.tags.tag_accesses 60324528 # Number of tag accesses
2123system.cpu1.dcache.tags.data_accesses 60324528 # Number of data accesses
2124system.cpu1.dcache.ReadReq_hits::cpu1.data 8516413 # number of ReadReq hits
2125system.cpu1.dcache.ReadReq_hits::total 8516413 # number of ReadReq hits
2126system.cpu1.dcache.WriteReq_hits::cpu1.data 4259216 # number of WriteReq hits
2127system.cpu1.dcache.WriteReq_hits::total 4259216 # number of WriteReq hits
2128system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99616 # number of LoadLockedReq hits
2129system.cpu1.dcache.LoadLockedReq_hits::total 99616 # number of LoadLockedReq hits
2130system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97058 # number of StoreCondReq hits
2131system.cpu1.dcache.StoreCondReq_hits::total 97058 # number of StoreCondReq hits
2132system.cpu1.dcache.demand_hits::cpu1.data 12775629 # number of demand (read+write) hits
2133system.cpu1.dcache.demand_hits::total 12775629 # number of demand (read+write) hits
2134system.cpu1.dcache.overall_hits::cpu1.data 12775629 # number of overall hits
2135system.cpu1.dcache.overall_hits::total 12775629 # number of overall hits
2136system.cpu1.dcache.ReadReq_misses::cpu1.data 409488 # number of ReadReq misses
2137system.cpu1.dcache.ReadReq_misses::total 409488 # number of ReadReq misses
2138system.cpu1.dcache.WriteReq_misses::cpu1.data 1576995 # number of WriteReq misses
2139system.cpu1.dcache.WriteReq_misses::total 1576995 # number of WriteReq misses
2140system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14210 # number of LoadLockedReq misses
2141system.cpu1.dcache.LoadLockedReq_misses::total 14210 # number of LoadLockedReq misses
2142system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10944 # number of StoreCondReq misses
2143system.cpu1.dcache.StoreCondReq_misses::total 10944 # number of StoreCondReq misses
2144system.cpu1.dcache.demand_misses::cpu1.data 1986483 # number of demand (read+write) misses
2145system.cpu1.dcache.demand_misses::total 1986483 # number of demand (read+write) misses
2146system.cpu1.dcache.overall_misses::cpu1.data 1986483 # number of overall misses
2147system.cpu1.dcache.overall_misses::total 1986483 # number of overall misses
2148system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6227092173 # number of ReadReq miss cycles
2149system.cpu1.dcache.ReadReq_miss_latency::total 6227092173 # number of ReadReq miss cycles
2150system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 74233295889 # number of WriteReq miss cycles
2151system.cpu1.dcache.WriteReq_miss_latency::total 74233295889 # number of WriteReq miss cycles
2152system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131030244 # number of LoadLockedReq miss cycles
2153system.cpu1.dcache.LoadLockedReq_miss_latency::total 131030244 # number of LoadLockedReq miss cycles
2154system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58441088 # number of StoreCondReq miss cycles
2155system.cpu1.dcache.StoreCondReq_miss_latency::total 58441088 # number of StoreCondReq miss cycles
2156system.cpu1.dcache.demand_miss_latency::cpu1.data 80460388062 # number of demand (read+write) miss cycles
2157system.cpu1.dcache.demand_miss_latency::total 80460388062 # number of demand (read+write) miss cycles
2158system.cpu1.dcache.overall_miss_latency::cpu1.data 80460388062 # number of overall miss cycles
2159system.cpu1.dcache.overall_miss_latency::total 80460388062 # number of overall miss cycles
2160system.cpu1.dcache.ReadReq_accesses::cpu1.data 8925901 # number of ReadReq accesses(hits+misses)
2161system.cpu1.dcache.ReadReq_accesses::total 8925901 # number of ReadReq accesses(hits+misses)
2162system.cpu1.dcache.WriteReq_accesses::cpu1.data 5836211 # number of WriteReq accesses(hits+misses)
2163system.cpu1.dcache.WriteReq_accesses::total 5836211 # number of WriteReq accesses(hits+misses)
2164system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 113826 # number of LoadLockedReq accesses(hits+misses)
2165system.cpu1.dcache.LoadLockedReq_accesses::total 113826 # number of LoadLockedReq accesses(hits+misses)
2166system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 108002 # number of StoreCondReq accesses(hits+misses)
2167system.cpu1.dcache.StoreCondReq_accesses::total 108002 # number of StoreCondReq accesses(hits+misses)
2168system.cpu1.dcache.demand_accesses::cpu1.data 14762112 # number of demand (read+write) accesses
2169system.cpu1.dcache.demand_accesses::total 14762112 # number of demand (read+write) accesses
2170system.cpu1.dcache.overall_accesses::cpu1.data 14762112 # number of overall (read+write) accesses
2171system.cpu1.dcache.overall_accesses::total 14762112 # number of overall (read+write) accesses
2172system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045876 # miss rate for ReadReq accesses
2173system.cpu1.dcache.ReadReq_miss_rate::total 0.045876 # miss rate for ReadReq accesses
2174system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.270209 # miss rate for WriteReq accesses
2175system.cpu1.dcache.WriteReq_miss_rate::total 0.270209 # miss rate for WriteReq accesses
2176system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124840 # miss rate for LoadLockedReq accesses
2177system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124840 # miss rate for LoadLockedReq accesses
2178system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101331 # miss rate for StoreCondReq accesses
2179system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101331 # miss rate for StoreCondReq accesses
2180system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134566 # miss rate for demand accesses
2181system.cpu1.dcache.demand_miss_rate::total 0.134566 # miss rate for demand accesses
2182system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134566 # miss rate for overall accesses
2183system.cpu1.dcache.overall_miss_rate::total 0.134566 # miss rate for overall accesses
2184system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15207.019920 # average ReadReq miss latency
2185system.cpu1.dcache.ReadReq_avg_miss_latency::total 15207.019920 # average ReadReq miss latency
2186system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 47072.626032 # average WriteReq miss latency
2187system.cpu1.dcache.WriteReq_avg_miss_latency::total 47072.626032 # average WriteReq miss latency
2188system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9220.988318 # average LoadLockedReq miss latency
2189system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9220.988318 # average LoadLockedReq miss latency
2190system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5340.011696 # average StoreCondReq miss latency
2191system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5340.011696 # average StoreCondReq miss latency
2192system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 40503.939909 # average overall miss latency
2193system.cpu1.dcache.demand_avg_miss_latency::total 40503.939909 # average overall miss latency
2194system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 40503.939909 # average overall miss latency
2195system.cpu1.dcache.overall_avg_miss_latency::total 40503.939909 # average overall miss latency
2196system.cpu1.dcache.blocked_cycles::no_mshrs 30714 # number of cycles access was blocked
2197system.cpu1.dcache.blocked_cycles::no_targets 17665 # number of cycles access was blocked
2198system.cpu1.dcache.blocked::no_mshrs 3287 # number of cycles access was blocked
2199system.cpu1.dcache.blocked::no_targets 190 # number of cycles access was blocked
2200system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.344083 # average number of cycles each access was blocked
2201system.cpu1.dcache.avg_blocked_cycles::no_targets 92.973684 # average number of cycles each access was blocked
2202system.cpu1.dcache.fast_writes 0 # number of fast writes performed
2203system.cpu1.dcache.cache_copies 0 # number of cache copies performed
2204system.cpu1.dcache.writebacks::writebacks 327552 # number of writebacks
2205system.cpu1.dcache.writebacks::total 327552 # number of writebacks
2206system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 178171 # number of ReadReq MSHR hits
2207system.cpu1.dcache.ReadReq_mshr_hits::total 178171 # number of ReadReq MSHR hits
2208system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1413840 # number of WriteReq MSHR hits
2209system.cpu1.dcache.WriteReq_mshr_hits::total 1413840 # number of WriteReq MSHR hits
2210system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1455 # number of LoadLockedReq MSHR hits
2211system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1455 # number of LoadLockedReq MSHR hits
2212system.cpu1.dcache.demand_mshr_hits::cpu1.data 1592011 # number of demand (read+write) MSHR hits
2213system.cpu1.dcache.demand_mshr_hits::total 1592011 # number of demand (read+write) MSHR hits
2214system.cpu1.dcache.overall_mshr_hits::cpu1.data 1592011 # number of overall MSHR hits
2215system.cpu1.dcache.overall_mshr_hits::total 1592011 # number of overall MSHR hits
2216system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231317 # number of ReadReq MSHR misses
2217system.cpu1.dcache.ReadReq_mshr_misses::total 231317 # number of ReadReq MSHR misses
2218system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163155 # number of WriteReq MSHR misses
2219system.cpu1.dcache.WriteReq_mshr_misses::total 163155 # number of WriteReq MSHR misses
2220system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12755 # number of LoadLockedReq MSHR misses
2221system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12755 # number of LoadLockedReq MSHR misses
2222system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10944 # number of StoreCondReq MSHR misses
2223system.cpu1.dcache.StoreCondReq_mshr_misses::total 10944 # number of StoreCondReq MSHR misses
2224system.cpu1.dcache.demand_mshr_misses::cpu1.data 394472 # number of demand (read+write) MSHR misses
2225system.cpu1.dcache.demand_mshr_misses::total 394472 # number of demand (read+write) MSHR misses
2226system.cpu1.dcache.overall_mshr_misses::cpu1.data 394472 # number of overall MSHR misses
2227system.cpu1.dcache.overall_mshr_misses::total 394472 # number of overall MSHR misses
2228system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2894401946 # number of ReadReq MSHR miss cycles
2229system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2894401946 # number of ReadReq MSHR miss cycles
2230system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6921941032 # number of WriteReq MSHR miss cycles
2231system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6921941032 # number of WriteReq MSHR miss cycles
2232system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89586755 # number of LoadLockedReq MSHR miss cycles
2233system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89586755 # number of LoadLockedReq MSHR miss cycles
2234system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36550912 # number of StoreCondReq MSHR miss cycles
2235system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36550912 # number of StoreCondReq MSHR miss cycles
2236system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
2237system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
2238system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9816342978 # number of demand (read+write) MSHR miss cycles
2239system.cpu1.dcache.demand_mshr_miss_latency::total 9816342978 # number of demand (read+write) MSHR miss cycles
2240system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9816342978 # number of overall MSHR miss cycles
2241system.cpu1.dcache.overall_mshr_miss_latency::total 9816342978 # number of overall MSHR miss cycles
2242system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231628259 # number of ReadReq MSHR uncacheable cycles
2243system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231628259 # number of ReadReq MSHR uncacheable cycles
2244system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25874415734 # number of WriteReq MSHR uncacheable cycles
2245system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25874415734 # number of WriteReq MSHR uncacheable cycles
2246system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195106043993 # number of overall MSHR uncacheable cycles
2247system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195106043993 # number of overall MSHR uncacheable cycles
2248system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025915 # mshr miss rate for ReadReq accesses
2249system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025915 # mshr miss rate for ReadReq accesses
2250system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027956 # mshr miss rate for WriteReq accesses
2251system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027956 # mshr miss rate for WriteReq accesses
2252system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112057 # mshr miss rate for LoadLockedReq accesses
2253system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112057 # mshr miss rate for LoadLockedReq accesses
2254system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101331 # mshr miss rate for StoreCondReq accesses
2255system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101331 # mshr miss rate for StoreCondReq accesses
2256system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026722 # mshr miss rate for demand accesses
2257system.cpu1.dcache.demand_mshr_miss_rate::total 0.026722 # mshr miss rate for demand accesses
2258system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026722 # mshr miss rate for overall accesses
2259system.cpu1.dcache.overall_mshr_miss_rate::total 0.026722 # mshr miss rate for overall accesses
2260system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.707436 # average ReadReq mshr miss latency
2261system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.707436 # average ReadReq mshr miss latency
2262system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42425.552585 # average WriteReq mshr miss latency
2263system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 42425.552585 # average WriteReq mshr miss latency
2264system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7023.657781 # average LoadLockedReq mshr miss latency
2265system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7023.657781 # average LoadLockedReq mshr miss latency
2266system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3339.812865 # average StoreCondReq mshr miss latency
2267system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3339.812865 # average StoreCondReq mshr miss latency
2268system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
2269system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2270system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24884.764896 # average overall mshr miss latency
2271system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24884.764896 # average overall mshr miss latency
2272system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24884.764896 # average overall mshr miss latency
2273system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24884.764896 # average overall mshr miss latency
2274system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
2275system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2276system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
2277system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
2278system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
2279system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2280system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2281system.iocache.tags.replacements 0 # number of replacements

--- 7 unchanged lines hidden (view full) ---

2289system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2290system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2291system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2292system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2293system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2294system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2295system.iocache.fast_writes 0 # number of fast writes performed
2296system.iocache.cache_copies 0 # number of cache copies performed
2297system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734300149849 # number of ReadReq MSHR uncacheable cycles
2298system.iocache.ReadReq_mshr_uncacheable_latency::total 1734300149849 # number of ReadReq MSHR uncacheable cycles
2299system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734300149849 # number of overall MSHR uncacheable cycles
2300system.iocache.overall_mshr_uncacheable_latency::total 1734300149849 # number of overall MSHR uncacheable cycles
2301system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
2302system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2303system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
2304system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2305system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2306system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2307system.cpu0.kern.inst.quiesce 42635 # number of quiesce instructions executed
2308system.cpu1.kern.inst.arm 0 # number of arm instructions executed
2309system.cpu1.kern.inst.quiesce 50404 # number of quiesce instructions executed
2310
2311---------- End Simulation Statistics ----------