3sim_seconds 2.854944 # Number of seconds simulated
4sim_ticks 2854944380500 # Number of ticks simulated
5final_tick 2854944380500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 264512 # Simulator instruction rate (inst/s)
8host_op_rate 319813 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 6754449586 # Simulator tick rate (ticks/s)
10host_mem_usage 588784 # Number of bytes of host memory used
11host_seconds 422.68 # Real time elapsed on the host
12sim_insts 111803105 # Number of instructions simulated
13sim_ops 135177203 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.dtb.walker 6784 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.inst 1665024 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu.data 9168492 # Number of bytes read from this memory
21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
22system.physmem.bytes_read::total 10841388 # Number of bytes read from this memory
23system.physmem.bytes_inst_read::cpu.inst 1665024 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::total 1665024 # Number of instructions bytes read from this memory
25system.physmem.bytes_written::writebacks 7956736 # Number of bytes written to this memory
26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
27system.physmem.bytes_written::total 7974260 # Number of bytes written to this memory
28system.physmem.num_reads::cpu.dtb.walker 106 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.inst 26016 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu.data 143779 # Number of read requests responded to by this memory
32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
33system.physmem.num_reads::total 169918 # Number of read requests responded to by this memory
34system.physmem.num_writes::writebacks 124324 # Number of write requests responded to by this memory
35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
36system.physmem.num_writes::total 128705 # Number of write requests responded to by this memory
37system.physmem.bw_read::cpu.dtb.walker 2376 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.inst 583207 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu.data 3211443 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::total 3797408 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::cpu.inst 583207 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_inst_read::total 583207 # Instruction read bandwidth from this memory (bytes/s)
45system.physmem.bw_write::writebacks 2787002 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::cpu.data 6138 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_write::total 2793140 # Write bandwidth from this memory (bytes/s)
48system.physmem.bw_total::writebacks 2787002 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.dtb.walker 2376 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.inst 583207 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::cpu.data 3217581 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.bw_total::total 6590548 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.readReqs 169918 # Number of read requests accepted
56system.physmem.writeReqs 128705 # Number of write requests accepted
57system.physmem.readBursts 169918 # Number of DRAM read bursts, including those serviced by the write queue
58system.physmem.writeBursts 128705 # Number of DRAM write bursts, including those merged in the write queue
59system.physmem.bytesReadDRAM 10866560 # Total number of bytes read from DRAM
60system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue
61system.physmem.bytesWritten 7986688 # Total number of bytes written to DRAM
62system.physmem.bytesReadSys 10841388 # Total read bytes from the system interface side
63system.physmem.bytesWrittenSys 7974260 # Total written bytes from the system interface side
64system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue
65system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one
66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
67system.physmem.perBankRdBursts::0 10675 # Per bank write bursts
68system.physmem.perBankRdBursts::1 10444 # Per bank write bursts
69system.physmem.perBankRdBursts::2 10743 # Per bank write bursts
70system.physmem.perBankRdBursts::3 10387 # Per bank write bursts
71system.physmem.perBankRdBursts::4 13022 # Per bank write bursts
72system.physmem.perBankRdBursts::5 10182 # Per bank write bursts
73system.physmem.perBankRdBursts::6 10267 # Per bank write bursts
74system.physmem.perBankRdBursts::7 10712 # Per bank write bursts
75system.physmem.perBankRdBursts::8 10430 # Per bank write bursts
76system.physmem.perBankRdBursts::9 10642 # Per bank write bursts
77system.physmem.perBankRdBursts::10 10231 # Per bank write bursts
78system.physmem.perBankRdBursts::11 9545 # Per bank write bursts
79system.physmem.perBankRdBursts::12 10746 # Per bank write bursts
80system.physmem.perBankRdBursts::13 11530 # Per bank write bursts
81system.physmem.perBankRdBursts::14 10184 # Per bank write bursts
82system.physmem.perBankRdBursts::15 10050 # Per bank write bursts
83system.physmem.perBankWrBursts::0 7937 # Per bank write bursts
84system.physmem.perBankWrBursts::1 7870 # Per bank write bursts
85system.physmem.perBankWrBursts::2 8420 # Per bank write bursts
86system.physmem.perBankWrBursts::3 7905 # Per bank write bursts
87system.physmem.perBankWrBursts::4 7296 # Per bank write bursts
88system.physmem.perBankWrBursts::5 7361 # Per bank write bursts
89system.physmem.perBankWrBursts::6 7425 # Per bank write bursts
90system.physmem.perBankWrBursts::7 7903 # Per bank write bursts
91system.physmem.perBankWrBursts::8 7956 # Per bank write bursts
92system.physmem.perBankWrBursts::9 8136 # Per bank write bursts
93system.physmem.perBankWrBursts::10 7613 # Per bank write bursts
94system.physmem.perBankWrBursts::11 7341 # Per bank write bursts
95system.physmem.perBankWrBursts::12 8127 # Per bank write bursts
96system.physmem.perBankWrBursts::13 8673 # Per bank write bursts
97system.physmem.perBankWrBursts::14 7491 # Per bank write bursts
98system.physmem.perBankWrBursts::15 7338 # Per bank write bursts
99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
100system.physmem.numWrRetry 64 # Number of times write queue was full causing retry
101system.physmem.totGap 2854943930000 # Total gap between requests
102system.physmem.readPktSize::0 0 # Read request sizes (log2)
103system.physmem.readPktSize::1 0 # Read request sizes (log2)
104system.physmem.readPktSize::2 543 # Read request sizes (log2)
105system.physmem.readPktSize::3 14 # Read request sizes (log2)
106system.physmem.readPktSize::4 0 # Read request sizes (log2)
107system.physmem.readPktSize::5 0 # Read request sizes (log2)
108system.physmem.readPktSize::6 169361 # Read request sizes (log2)
109system.physmem.writePktSize::0 0 # Write request sizes (log2)
110system.physmem.writePktSize::1 0 # Write request sizes (log2)
111system.physmem.writePktSize::2 4381 # Write request sizes (log2)
112system.physmem.writePktSize::3 0 # Write request sizes (log2)
113system.physmem.writePktSize::4 0 # Write request sizes (log2)
114system.physmem.writePktSize::5 0 # Write request sizes (log2)
115system.physmem.writePktSize::6 124324 # Write request sizes (log2)
116system.physmem.rdQLenPdf::0 159846 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::1 9630 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::2 301 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
148system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::15 1816 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::16 2607 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::17 5988 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::18 6261 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::19 6563 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::20 6237 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::21 6589 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::22 6896 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::23 7686 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::24 7433 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::25 8575 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::26 9015 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::27 7444 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::28 6965 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::29 7063 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::30 6763 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::31 6551 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::32 6616 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::33 505 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::34 478 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::35 459 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::36 344 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::37 255 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::38 298 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::39 296 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::40 266 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::41 262 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::42 267 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::43 278 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::44 351 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::45 215 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::47 210 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::48 195 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::49 213 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::50 220 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::51 178 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::52 208 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::53 189 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::54 164 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::55 179 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::56 244 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::57 265 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::58 124 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::59 201 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::60 238 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::61 159 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::62 74 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::63 166 # What write queue length does an incoming req see
212system.physmem.bytesPerActivate::samples 60346 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::mean 312.418122 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::gmean 185.510807 # Bytes accessed per row activation
215system.physmem.bytesPerActivate::stdev 328.995418 # Bytes accessed per row activation
216system.physmem.bytesPerActivate::0-127 21664 35.90% 35.90% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::128-255 14701 24.36% 60.26% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::256-383 6745 11.18% 71.44% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::384-511 3562 5.90% 77.34% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::512-639 2510 4.16% 81.50% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::640-767 1679 2.78% 84.28% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::768-895 1014 1.68% 85.96% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::896-1023 1006 1.67% 87.63% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::1024-1151 7465 12.37% 100.00% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::total 60346 # Bytes accessed per row activation
226system.physmem.rdPerTurnAround::samples 6177 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::mean 27.486158 # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::stdev 583.334644 # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::0-2047 6176 99.98% 99.98% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::total 6177 # Reads before turning the bus around for writes
232system.physmem.wrPerTurnAround::samples 6177 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::mean 20.202687 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::gmean 18.306581 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::stdev 15.265718 # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::16-19 5466 88.49% 88.49% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::20-23 67 1.08% 89.57% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::24-27 30 0.49% 90.06% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::28-31 47 0.76% 90.82% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::32-35 264 4.27% 95.09% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::36-39 28 0.45% 95.55% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::40-43 18 0.29% 95.84% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::44-47 6 0.10% 95.94% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::48-51 9 0.15% 96.08% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::52-55 7 0.11% 96.20% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::56-59 4 0.06% 96.26% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::60-63 7 0.11% 96.37% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::64-67 143 2.32% 98.69% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::68-71 4 0.06% 98.75% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::72-75 1 0.02% 98.77% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::76-79 7 0.11% 98.88% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::80-83 5 0.08% 98.96% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::84-87 1 0.02% 98.98% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::88-91 1 0.02% 99.00% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::96-99 1 0.02% 99.01% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::108-111 11 0.18% 99.19% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::112-115 2 0.03% 99.22% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::120-123 3 0.05% 99.27% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::124-127 3 0.05% 99.32% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::128-131 14 0.23% 99.55% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::132-135 3 0.05% 99.60% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::136-139 4 0.06% 99.66% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::140-143 4 0.06% 99.72% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::144-147 1 0.02% 99.74% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::152-155 1 0.02% 99.76% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::164-167 1 0.02% 99.77% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::168-171 1 0.02% 99.79% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::172-175 5 0.08% 99.87% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::180-183 1 0.02% 99.89% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::188-191 2 0.03% 99.92% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::192-195 4 0.06% 99.98% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::196-199 1 0.02% 100.00% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::total 6177 # Writes before turning the bus around for reads
274system.physmem.totQLat 4574555750 # Total ticks spent queuing
275system.physmem.totMemAccLat 7758118250 # Total ticks spent from burst creation until serviced by the DRAM
276system.physmem.totBusLat 848950000 # Total ticks spent in databus transfers
277system.physmem.avgQLat 26942.43 # Average queueing delay per DRAM burst
278system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
279system.physmem.avgMemAccLat 45692.43 # Average memory access latency per DRAM burst
280system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s
281system.physmem.avgWrBW 2.80 # Average achieved write bandwidth in MiByte/s
282system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s
283system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s
284system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
285system.physmem.busUtil 0.05 # Data bus utilization in percentage
286system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
287system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
288system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
289system.physmem.avgWrQLen 25.37 # Average write queue length when enqueuing
290system.physmem.readRowHits 140247 # Number of row buffer hits during reads
291system.physmem.writeRowHits 93988 # Number of row buffer hits during writes
292system.physmem.readRowHitRate 82.60 # Row buffer hit rate for reads
293system.physmem.writeRowHitRate 75.30 # Row buffer hit rate for writes
294system.physmem.avgGap 9560361.83 # Average gap between requests
295system.physmem.pageHitRate 79.51 # Row buffer hit rate, read and write combined
296system.physmem_0.actEnergy 217834260 # Energy for activate commands per rank (pJ)
297system.physmem_0.preEnergy 115781655 # Energy for precharge commands per rank (pJ)
298system.physmem_0.readEnergy 617124480 # Energy for read commands per rank (pJ)
299system.physmem_0.writeEnergy 324250740 # Energy for write commands per rank (pJ)
300system.physmem_0.refreshEnergy 6010564560.000001 # Energy for refresh commands per rank (pJ)
301system.physmem_0.actBackEnergy 4580096490 # Energy for active background per rank (pJ)
302system.physmem_0.preBackEnergy 375795840 # Energy for precharge background per rank (pJ)
303system.physmem_0.actPowerDownEnergy 12507827490 # Energy for active power-down per rank (pJ)
304system.physmem_0.prePowerDownEnergy 8401113600 # Energy for precharge power-down per rank (pJ)
305system.physmem_0.selfRefreshEnergy 671912403285 # Energy for self refresh per rank (pJ)
306system.physmem_0.totalEnergy 705065679060 # Total energy per rank (pJ)
307system.physmem_0.averagePower 246.963017 # Core power per rank (mW)
308system.physmem_0.totalIdleTime 2843582682250 # Total Idle time Per DRAM Rank
309system.physmem_0.memoryStateTime::IDLE 706056250 # Time in different power states
310system.physmem_0.memoryStateTime::REF 2555890000 # Time in different power states
311system.physmem_0.memoryStateTime::SREF 2794607920750 # Time in different power states
312system.physmem_0.memoryStateTime::PRE_PDN 21877952250 # Time in different power states
313system.physmem_0.memoryStateTime::ACT 7767045000 # Time in different power states
314system.physmem_0.memoryStateTime::ACT_PDN 27429516250 # Time in different power states
315system.physmem_1.actEnergy 213043320 # Energy for activate commands per rank (pJ)
316system.physmem_1.preEnergy 113231415 # Energy for precharge commands per rank (pJ)
317system.physmem_1.readEnergy 595176120 # Energy for read commands per rank (pJ)
318system.physmem_1.writeEnergy 327163500 # Energy for write commands per rank (pJ)
319system.physmem_1.refreshEnergy 6093540960.000001 # Energy for refresh commands per rank (pJ)
320system.physmem_1.actBackEnergy 4507043580 # Energy for active background per rank (pJ)
321system.physmem_1.preBackEnergy 367350240 # Energy for precharge background per rank (pJ)
322system.physmem_1.actPowerDownEnergy 12209497470 # Energy for active power-down per rank (pJ)
323system.physmem_1.prePowerDownEnergy 8677272480 # Energy for precharge power-down per rank (pJ)
324system.physmem_1.selfRefreshEnergy 672029778480 # Energy for self refresh per rank (pJ)
325system.physmem_1.totalEnergy 705136507095 # Total energy per rank (pJ)
326system.physmem_1.averagePower 246.987826 # Core power per rank (mW)
327system.physmem_1.totalIdleTime 2844096160000 # Total Idle time Per DRAM Rank
328system.physmem_1.memoryStateTime::IDLE 691055750 # Time in different power states
329system.physmem_1.memoryStateTime::REF 2591938000 # Time in different power states
330system.physmem_1.memoryStateTime::SREF 2794723975250 # Time in different power states
331system.physmem_1.memoryStateTime::PRE_PDN 22596980000 # Time in different power states
332system.physmem_1.memoryStateTime::ACT 7565161250 # Time in different power states
333system.physmem_1.memoryStateTime::ACT_PDN 26775270250 # Time in different power states
334system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
335system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory
336system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory
337system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory
338system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory
339system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
340system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
341system.realview.nvmem.bw_read::cpu.inst 179 # Total read bandwidth from this memory (bytes/s)
342system.realview.nvmem.bw_read::total 179 # Total read bandwidth from this memory (bytes/s)
343system.realview.nvmem.bw_inst_read::cpu.inst 179 # Instruction read bandwidth from this memory (bytes/s)
344system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s)
345system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s)
346system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s)
347system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
348system.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
349system.bridge.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
350system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
351system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
352system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
353system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
354system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
355system.cf0.dma_write_txs 631 # Number of DMA write transactions.
356system.cpu.branchPred.lookups 31068063 # Number of BP lookups
357system.cpu.branchPred.condPredicted 16834819 # Number of conditional branches predicted
358system.cpu.branchPred.condIncorrect 2474290 # Number of conditional branches incorrect
359system.cpu.branchPred.BTBLookups 18684214 # Number of BTB lookups
360system.cpu.branchPred.BTBHits 10413110 # Number of BTB hits
361system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
362system.cpu.branchPred.BTBHitPct 55.732128 # BTB Hit Percentage
363system.cpu.branchPred.usedRAS 7904720 # Number of times the RAS was used to get a target.
364system.cpu.branchPred.RASInCorrect 1504932 # Number of incorrect RAS predictions.
365system.cpu.branchPred.indirectLookups 3038151 # Number of indirect predictor lookups.
366system.cpu.branchPred.indirectHits 2849063 # Number of indirect target hits.
367system.cpu.branchPred.indirectMisses 189088 # Number of indirect misses.
368system.cpu.branchPredindirectMispredicted 109706 # Number of mispredicted indirect branches.
369system.cpu_clk_domain.clock 500 # Clock period in ticks
370system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
371system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
372system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
373system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
374system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
375system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
376system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
377system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
378system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
379system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
380system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
381system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
382system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
383system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
384system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
385system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
386system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
387system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
388system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
389system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
390system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
391system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
392system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
393system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
394system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
395system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
396system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
397system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
398system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
399system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
400system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
401system.cpu.dtb.walker.walks 67808 # Table walker walks requested
402system.cpu.dtb.walker.walksShort 67808 # Table walker walks initiated with short descriptors
403system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44545 # Level at which table walker walks with short descriptors terminate
404system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23263 # Level at which table walker walks with short descriptors terminate
405system.cpu.dtb.walker.walkWaitTime::samples 67808 # Table walker wait (enqueue to first request) latency
406system.cpu.dtb.walker.walkWaitTime::0 67808 100.00% 100.00% # Table walker wait (enqueue to first request) latency
407system.cpu.dtb.walker.walkWaitTime::total 67808 # Table walker wait (enqueue to first request) latency
408system.cpu.dtb.walker.walkCompletionTime::samples 7897 # Table walker service (enqueue to completion) latency
409system.cpu.dtb.walker.walkCompletionTime::mean 10074.838546 # Table walker service (enqueue to completion) latency
410system.cpu.dtb.walker.walkCompletionTime::gmean 8443.809763 # Table walker service (enqueue to completion) latency
411system.cpu.dtb.walker.walkCompletionTime::stdev 7240.808120 # Table walker service (enqueue to completion) latency
412system.cpu.dtb.walker.walkCompletionTime::0-16383 7014 88.82% 88.82% # Table walker service (enqueue to completion) latency
413system.cpu.dtb.walker.walkCompletionTime::16384-32767 876 11.09% 99.91% # Table walker service (enqueue to completion) latency
414system.cpu.dtb.walker.walkCompletionTime::81920-98303 5 0.06% 99.97% # Table walker service (enqueue to completion) latency
415system.cpu.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
416system.cpu.dtb.walker.walkCompletionTime::245760-262143 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
417system.cpu.dtb.walker.walkCompletionTime::total 7897 # Table walker service (enqueue to completion) latency
418system.cpu.dtb.walker.walksPending::samples 276581000 # Table walker pending requests distribution
419system.cpu.dtb.walker.walksPending::0 276581000 100.00% 100.00% # Table walker pending requests distribution
420system.cpu.dtb.walker.walksPending::total 276581000 # Table walker pending requests distribution
421system.cpu.dtb.walker.walkPageSizes::4K 6507 82.40% 82.40% # Table walker page sizes translated
422system.cpu.dtb.walker.walkPageSizes::1M 1390 17.60% 100.00% # Table walker page sizes translated
423system.cpu.dtb.walker.walkPageSizes::total 7897 # Table walker page sizes translated
424system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 67808 # Table walker requests started/completed, data/inst
425system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
426system.cpu.dtb.walker.walkRequestOrigin_Requested::total 67808 # Table walker requests started/completed, data/inst
427system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7897 # Table walker requests started/completed, data/inst
428system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
429system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7897 # Table walker requests started/completed, data/inst
430system.cpu.dtb.walker.walkRequestOrigin::total 75705 # Table walker requests started/completed, data/inst
431system.cpu.dtb.inst_hits 0 # ITB inst hits
432system.cpu.dtb.inst_misses 0 # ITB inst misses
433system.cpu.dtb.read_hits 24693754 # DTB read hits
434system.cpu.dtb.read_misses 60831 # DTB read misses
435system.cpu.dtb.write_hits 19411318 # DTB write hits
436system.cpu.dtb.write_misses 6977 # DTB write misses
437system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
438system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
439system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
440system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
441system.cpu.dtb.flush_entries 4277 # Number of entries that have been flushed from TLB
442system.cpu.dtb.align_faults 1491 # Number of TLB faults due to alignment restrictions
443system.cpu.dtb.prefetch_faults 1775 # Number of TLB faults due to prefetch
444system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
445system.cpu.dtb.perms_faults 779 # Number of TLB faults due to permissions restrictions
446system.cpu.dtb.read_accesses 24754585 # DTB read accesses
447system.cpu.dtb.write_accesses 19418295 # DTB write accesses
448system.cpu.dtb.inst_accesses 0 # ITB inst accesses
449system.cpu.dtb.hits 44105072 # DTB hits
450system.cpu.dtb.misses 67808 # DTB misses
451system.cpu.dtb.accesses 44172880 # DTB accesses
452system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
453system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
454system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
455system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
456system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
457system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
458system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
459system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
460system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
461system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
462system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
463system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
464system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
465system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
466system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
467system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
468system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
469system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
470system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
471system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
472system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
473system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
474system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
475system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
476system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
477system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
478system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
479system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
480system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
481system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
482system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
483system.cpu.itb.walker.walks 5860 # Table walker walks requested
484system.cpu.itb.walker.walksShort 5860 # Table walker walks initiated with short descriptors
485system.cpu.itb.walker.walksShortTerminationLevel::Level1 319 # Level at which table walker walks with short descriptors terminate
486system.cpu.itb.walker.walksShortTerminationLevel::Level2 5541 # Level at which table walker walks with short descriptors terminate
487system.cpu.itb.walker.walkWaitTime::samples 5860 # Table walker wait (enqueue to first request) latency
488system.cpu.itb.walker.walkWaitTime::0 5860 100.00% 100.00% # Table walker wait (enqueue to first request) latency
489system.cpu.itb.walker.walkWaitTime::total 5860 # Table walker wait (enqueue to first request) latency
490system.cpu.itb.walker.walkCompletionTime::samples 3216 # Table walker service (enqueue to completion) latency
491system.cpu.itb.walker.walkCompletionTime::mean 10484.452736 # Table walker service (enqueue to completion) latency
492system.cpu.itb.walker.walkCompletionTime::gmean 8664.992606 # Table walker service (enqueue to completion) latency
493system.cpu.itb.walker.walkCompletionTime::stdev 6927.635793 # Table walker service (enqueue to completion) latency
494system.cpu.itb.walker.walkCompletionTime::0-8191 1845 57.37% 57.37% # Table walker service (enqueue to completion) latency
495system.cpu.itb.walker.walkCompletionTime::8192-16383 815 25.34% 82.71% # Table walker service (enqueue to completion) latency
496system.cpu.itb.walker.walkCompletionTime::16384-24575 549 17.07% 99.78% # Table walker service (enqueue to completion) latency
497system.cpu.itb.walker.walkCompletionTime::24576-32767 6 0.19% 99.97% # Table walker service (enqueue to completion) latency
498system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
499system.cpu.itb.walker.walkCompletionTime::total 3216 # Table walker service (enqueue to completion) latency
500system.cpu.itb.walker.walksPending::samples 276141500 # Table walker pending requests distribution
501system.cpu.itb.walker.walksPending::0 276141500 100.00% 100.00% # Table walker pending requests distribution
502system.cpu.itb.walker.walksPending::total 276141500 # Table walker pending requests distribution
503system.cpu.itb.walker.walkPageSizes::4K 2906 90.36% 90.36% # Table walker page sizes translated
504system.cpu.itb.walker.walkPageSizes::1M 310 9.64% 100.00% # Table walker page sizes translated
505system.cpu.itb.walker.walkPageSizes::total 3216 # Table walker page sizes translated
506system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
507system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5860 # Table walker requests started/completed, data/inst
508system.cpu.itb.walker.walkRequestOrigin_Requested::total 5860 # Table walker requests started/completed, data/inst
509system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
510system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3216 # Table walker requests started/completed, data/inst
511system.cpu.itb.walker.walkRequestOrigin_Completed::total 3216 # Table walker requests started/completed, data/inst
512system.cpu.itb.walker.walkRequestOrigin::total 9076 # Table walker requests started/completed, data/inst
513system.cpu.itb.inst_hits 57505769 # ITB inst hits
514system.cpu.itb.inst_misses 5860 # ITB inst misses
515system.cpu.itb.read_hits 0 # DTB read hits
516system.cpu.itb.read_misses 0 # DTB read misses
517system.cpu.itb.write_hits 0 # DTB write hits
518system.cpu.itb.write_misses 0 # DTB write misses
519system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
520system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
521system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
522system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
523system.cpu.itb.flush_entries 2934 # Number of entries that have been flushed from TLB
524system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
525system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
526system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
527system.cpu.itb.perms_faults 8328 # Number of TLB faults due to permissions restrictions
528system.cpu.itb.read_accesses 0 # DTB read accesses
529system.cpu.itb.write_accesses 0 # DTB write accesses
530system.cpu.itb.inst_accesses 57511629 # ITB inst accesses
531system.cpu.itb.hits 57505769 # DTB hits
532system.cpu.itb.misses 5860 # DTB misses
533system.cpu.itb.accesses 57511629 # DTB accesses
534system.cpu.numPwrStateTransitions 6066 # Number of power state transitions
535system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state
536system.cpu.pwrStateClkGateDist::mean 887942089.664688 # Distribution of time spent in the clock gated state
537system.cpu.pwrStateClkGateDist::stdev 17437807884.014717 # Distribution of time spent in the clock gated state
538system.cpu.pwrStateClkGateDist::underflows 2969 97.89% 97.89% # Distribution of time spent in the clock gated state
539system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% # Distribution of time spent in the clock gated state
540system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
541system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state
542system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state
543system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
544system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
545system.cpu.pwrStateClkGateDist::max_value 499966671100 # Distribution of time spent in the clock gated state
546system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state
547system.cpu.pwrStateResidencyTicks::ON 161816022547 # Cumulative time (in ticks) in various power states
548system.cpu.pwrStateResidencyTicks::CLK_GATED 2693128357953 # Cumulative time (in ticks) in various power states
549system.cpu.numCycles 323634999 # number of cpu cycles simulated
550system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
551system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
552system.cpu.committedInsts 111803105 # Number of instructions committed
553system.cpu.committedOps 135177203 # Number of ops (including micro ops) committed
554system.cpu.discardedOps 7783284 # Number of ops (including micro ops) which were discarded before commit
555system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching
556system.cpu.quiesceCycles 5386318328 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
557system.cpu.cpi 2.894687 # CPI: cycles per instruction
558system.cpu.ipc 0.345460 # IPC: instructions per cycle
559system.cpu.op_class_0::No_OpClass 2337 0.00% 0.00% # Class of committed instruction
560system.cpu.op_class_0::IntAlu 90612203 67.03% 67.03% # Class of committed instruction
561system.cpu.op_class_0::IntMult 113141 0.08% 67.12% # Class of committed instruction
562system.cpu.op_class_0::IntDiv 0 0.00% 67.12% # Class of committed instruction
563system.cpu.op_class_0::FloatAdd 0 0.00% 67.12% # Class of committed instruction
564system.cpu.op_class_0::FloatCmp 0 0.00% 67.12% # Class of committed instruction
565system.cpu.op_class_0::FloatCvt 0 0.00% 67.12% # Class of committed instruction
566system.cpu.op_class_0::FloatMult 0 0.00% 67.12% # Class of committed instruction
567system.cpu.op_class_0::FloatMultAcc 0 0.00% 67.12% # Class of committed instruction
568system.cpu.op_class_0::FloatDiv 0 0.00% 67.12% # Class of committed instruction
569system.cpu.op_class_0::FloatMisc 0 0.00% 67.12% # Class of committed instruction
570system.cpu.op_class_0::FloatSqrt 0 0.00% 67.12% # Class of committed instruction
571system.cpu.op_class_0::SimdAdd 0 0.00% 67.12% # Class of committed instruction
572system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.12% # Class of committed instruction
573system.cpu.op_class_0::SimdAlu 0 0.00% 67.12% # Class of committed instruction
574system.cpu.op_class_0::SimdCmp 0 0.00% 67.12% # Class of committed instruction
575system.cpu.op_class_0::SimdCvt 0 0.00% 67.12% # Class of committed instruction
576system.cpu.op_class_0::SimdMisc 0 0.00% 67.12% # Class of committed instruction
577system.cpu.op_class_0::SimdMult 0 0.00% 67.12% # Class of committed instruction
578system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.12% # Class of committed instruction
579system.cpu.op_class_0::SimdShift 0 0.00% 67.12% # Class of committed instruction
580system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.12% # Class of committed instruction
581system.cpu.op_class_0::SimdSqrt 0 0.00% 67.12% # Class of committed instruction
582system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.12% # Class of committed instruction
583system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.12% # Class of committed instruction
584system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.12% # Class of committed instruction
585system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.12% # Class of committed instruction
586system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.12% # Class of committed instruction
587system.cpu.op_class_0::SimdFloatMisc 8473 0.01% 67.12% # Class of committed instruction
588system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.12% # Class of committed instruction
589system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.12% # Class of committed instruction
590system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.12% # Class of committed instruction
591system.cpu.op_class_0::MemRead 24199534 17.90% 85.03% # Class of committed instruction
592system.cpu.op_class_0::MemWrite 20230283 14.97% 99.99% # Class of committed instruction
593system.cpu.op_class_0::FloatMemRead 2708 0.00% 99.99% # Class of committed instruction
594system.cpu.op_class_0::FloatMemWrite 8524 0.01% 100.00% # Class of committed instruction
595system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
596system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
597system.cpu.op_class_0::total 135177203 # Class of committed instruction
598system.cpu.kern.inst.arm 0 # number of arm instructions executed
599system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed
600system.cpu.tickCycles 217984467 # Number of cycles that the object actually ticked
601system.cpu.idleCycles 105650532 # Total number of cycles that the object has spent stopped
602system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
603system.cpu.dcache.tags.replacements 844606 # number of replacements
604system.cpu.dcache.tags.tagsinuse 511.945154 # Cycle average of tags in use
605system.cpu.dcache.tags.total_refs 42562338 # Total number of references to valid blocks.
606system.cpu.dcache.tags.sampled_refs 845118 # Sample count of references to valid blocks.
607system.cpu.dcache.tags.avg_refs 50.362598 # Average number of references to valid blocks.
608system.cpu.dcache.tags.warmup_cycle 330588500 # Cycle when the warmup percentage was hit.
609system.cpu.dcache.tags.occ_blocks::cpu.data 511.945154 # Average occupied blocks per requestor
610system.cpu.dcache.tags.occ_percent::cpu.data 0.999893 # Average percentage of cache occupancy
611system.cpu.dcache.tags.occ_percent::total 0.999893 # Average percentage of cache occupancy
612system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
613system.cpu.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
614system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id
615system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id
616system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
617system.cpu.dcache.tags.tag_accesses 175904316 # Number of tag accesses
618system.cpu.dcache.tags.data_accesses 175904316 # Number of data accesses
619system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
620system.cpu.dcache.ReadReq_hits::cpu.data 23049763 # number of ReadReq hits
621system.cpu.dcache.ReadReq_hits::total 23049763 # number of ReadReq hits
622system.cpu.dcache.WriteReq_hits::cpu.data 18249075 # number of WriteReq hits
623system.cpu.dcache.WriteReq_hits::total 18249075 # number of WriteReq hits
624system.cpu.dcache.SoftPFReq_hits::cpu.data 357182 # number of SoftPFReq hits
625system.cpu.dcache.SoftPFReq_hits::total 357182 # number of SoftPFReq hits
626system.cpu.dcache.LoadLockedReq_hits::cpu.data 443419 # number of LoadLockedReq hits
627system.cpu.dcache.LoadLockedReq_hits::total 443419 # number of LoadLockedReq hits
628system.cpu.dcache.StoreCondReq_hits::cpu.data 460030 # number of StoreCondReq hits
629system.cpu.dcache.StoreCondReq_hits::total 460030 # number of StoreCondReq hits
630system.cpu.dcache.demand_hits::cpu.data 41298838 # number of demand (read+write) hits
631system.cpu.dcache.demand_hits::total 41298838 # number of demand (read+write) hits
632system.cpu.dcache.overall_hits::cpu.data 41656020 # number of overall hits
633system.cpu.dcache.overall_hits::total 41656020 # number of overall hits
634system.cpu.dcache.ReadReq_misses::cpu.data 464983 # number of ReadReq misses
635system.cpu.dcache.ReadReq_misses::total 464983 # number of ReadReq misses
636system.cpu.dcache.WriteReq_misses::cpu.data 548530 # number of WriteReq misses
637system.cpu.dcache.WriteReq_misses::total 548530 # number of WriteReq misses
638system.cpu.dcache.SoftPFReq_misses::cpu.data 169407 # number of SoftPFReq misses
639system.cpu.dcache.SoftPFReq_misses::total 169407 # number of SoftPFReq misses
640system.cpu.dcache.LoadLockedReq_misses::cpu.data 22402 # number of LoadLockedReq misses
641system.cpu.dcache.LoadLockedReq_misses::total 22402 # number of LoadLockedReq misses
642system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
643system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
644system.cpu.dcache.demand_misses::cpu.data 1013513 # number of demand (read+write) misses
645system.cpu.dcache.demand_misses::total 1013513 # number of demand (read+write) misses
646system.cpu.dcache.overall_misses::cpu.data 1182920 # number of overall misses
647system.cpu.dcache.overall_misses::total 1182920 # number of overall misses
648system.cpu.dcache.ReadReq_miss_latency::cpu.data 7335235000 # number of ReadReq miss cycles
649system.cpu.dcache.ReadReq_miss_latency::total 7335235000 # number of ReadReq miss cycles
650system.cpu.dcache.WriteReq_miss_latency::cpu.data 26749219979 # number of WriteReq miss cycles
651system.cpu.dcache.WriteReq_miss_latency::total 26749219979 # number of WriteReq miss cycles
652system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 303724500 # number of LoadLockedReq miss cycles
653system.cpu.dcache.LoadLockedReq_miss_latency::total 303724500 # number of LoadLockedReq miss cycles
654system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 169000 # number of StoreCondReq miss cycles
655system.cpu.dcache.StoreCondReq_miss_latency::total 169000 # number of StoreCondReq miss cycles
656system.cpu.dcache.demand_miss_latency::cpu.data 34084454979 # number of demand (read+write) miss cycles
657system.cpu.dcache.demand_miss_latency::total 34084454979 # number of demand (read+write) miss cycles
658system.cpu.dcache.overall_miss_latency::cpu.data 34084454979 # number of overall miss cycles
659system.cpu.dcache.overall_miss_latency::total 34084454979 # number of overall miss cycles
660system.cpu.dcache.ReadReq_accesses::cpu.data 23514746 # number of ReadReq accesses(hits+misses)
661system.cpu.dcache.ReadReq_accesses::total 23514746 # number of ReadReq accesses(hits+misses)
662system.cpu.dcache.WriteReq_accesses::cpu.data 18797605 # number of WriteReq accesses(hits+misses)
663system.cpu.dcache.WriteReq_accesses::total 18797605 # number of WriteReq accesses(hits+misses)
664system.cpu.dcache.SoftPFReq_accesses::cpu.data 526589 # number of SoftPFReq accesses(hits+misses)
665system.cpu.dcache.SoftPFReq_accesses::total 526589 # number of SoftPFReq accesses(hits+misses)
666system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465821 # number of LoadLockedReq accesses(hits+misses)
667system.cpu.dcache.LoadLockedReq_accesses::total 465821 # number of LoadLockedReq accesses(hits+misses)
668system.cpu.dcache.StoreCondReq_accesses::cpu.data 460032 # number of StoreCondReq accesses(hits+misses)
669system.cpu.dcache.StoreCondReq_accesses::total 460032 # number of StoreCondReq accesses(hits+misses)
670system.cpu.dcache.demand_accesses::cpu.data 42312351 # number of demand (read+write) accesses
671system.cpu.dcache.demand_accesses::total 42312351 # number of demand (read+write) accesses
672system.cpu.dcache.overall_accesses::cpu.data 42838940 # number of overall (read+write) accesses
673system.cpu.dcache.overall_accesses::total 42838940 # number of overall (read+write) accesses
674system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019774 # miss rate for ReadReq accesses
675system.cpu.dcache.ReadReq_miss_rate::total 0.019774 # miss rate for ReadReq accesses
676system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029181 # miss rate for WriteReq accesses
677system.cpu.dcache.WriteReq_miss_rate::total 0.029181 # miss rate for WriteReq accesses
678system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.321706 # miss rate for SoftPFReq accesses
679system.cpu.dcache.SoftPFReq_miss_rate::total 0.321706 # miss rate for SoftPFReq accesses
680system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048091 # miss rate for LoadLockedReq accesses
681system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048091 # miss rate for LoadLockedReq accesses
682system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
683system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
684system.cpu.dcache.demand_miss_rate::cpu.data 0.023953 # miss rate for demand accesses
685system.cpu.dcache.demand_miss_rate::total 0.023953 # miss rate for demand accesses
686system.cpu.dcache.overall_miss_rate::cpu.data 0.027613 # miss rate for overall accesses
687system.cpu.dcache.overall_miss_rate::total 0.027613 # miss rate for overall accesses
688system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15775.275655 # average ReadReq miss latency
689system.cpu.dcache.ReadReq_avg_miss_latency::total 15775.275655 # average ReadReq miss latency
690system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48765.281715 # average WriteReq miss latency
691system.cpu.dcache.WriteReq_avg_miss_latency::total 48765.281715 # average WriteReq miss latency
692system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13557.918936 # average LoadLockedReq miss latency
693system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13557.918936 # average LoadLockedReq miss latency
694system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 84500 # average StoreCondReq miss latency
695system.cpu.dcache.StoreCondReq_avg_miss_latency::total 84500 # average StoreCondReq miss latency
696system.cpu.dcache.demand_avg_miss_latency::cpu.data 33630.012618 # average overall miss latency
697system.cpu.dcache.demand_avg_miss_latency::total 33630.012618 # average overall miss latency
698system.cpu.dcache.overall_avg_miss_latency::cpu.data 28813.829320 # average overall miss latency
699system.cpu.dcache.overall_avg_miss_latency::total 28813.829320 # average overall miss latency
700system.cpu.dcache.blocked_cycles::no_mshrs 813 # number of cycles access was blocked
701system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
702system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked
703system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
704system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.954545 # average number of cycles each access was blocked
705system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
706system.cpu.dcache.writebacks::writebacks 701993 # number of writebacks
707system.cpu.dcache.writebacks::total 701993 # number of writebacks
708system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45638 # number of ReadReq MSHR hits
709system.cpu.dcache.ReadReq_mshr_hits::total 45638 # number of ReadReq MSHR hits
710system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249404 # number of WriteReq MSHR hits
711system.cpu.dcache.WriteReq_mshr_hits::total 249404 # number of WriteReq MSHR hits
712system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14200 # number of LoadLockedReq MSHR hits
713system.cpu.dcache.LoadLockedReq_mshr_hits::total 14200 # number of LoadLockedReq MSHR hits
714system.cpu.dcache.demand_mshr_hits::cpu.data 295042 # number of demand (read+write) MSHR hits
715system.cpu.dcache.demand_mshr_hits::total 295042 # number of demand (read+write) MSHR hits
716system.cpu.dcache.overall_mshr_hits::cpu.data 295042 # number of overall MSHR hits
717system.cpu.dcache.overall_mshr_hits::total 295042 # number of overall MSHR hits
718system.cpu.dcache.ReadReq_mshr_misses::cpu.data 419345 # number of ReadReq MSHR misses
719system.cpu.dcache.ReadReq_mshr_misses::total 419345 # number of ReadReq MSHR misses
720system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299126 # number of WriteReq MSHR misses
721system.cpu.dcache.WriteReq_mshr_misses::total 299126 # number of WriteReq MSHR misses
722system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121262 # number of SoftPFReq MSHR misses
723system.cpu.dcache.SoftPFReq_mshr_misses::total 121262 # number of SoftPFReq MSHR misses
724system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8202 # number of LoadLockedReq MSHR misses
725system.cpu.dcache.LoadLockedReq_mshr_misses::total 8202 # number of LoadLockedReq MSHR misses
726system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
727system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
728system.cpu.dcache.demand_mshr_misses::cpu.data 718471 # number of demand (read+write) MSHR misses
729system.cpu.dcache.demand_mshr_misses::total 718471 # number of demand (read+write) MSHR misses
730system.cpu.dcache.overall_mshr_misses::cpu.data 839733 # number of overall MSHR misses
731system.cpu.dcache.overall_mshr_misses::total 839733 # number of overall MSHR misses
732system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable
733system.cpu.dcache.ReadReq_mshr_uncacheable::total 31130 # number of ReadReq MSHR uncacheable
734system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
735system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
736system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses
737system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses
738system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6449852500 # number of ReadReq MSHR miss cycles
739system.cpu.dcache.ReadReq_mshr_miss_latency::total 6449852500 # number of ReadReq MSHR miss cycles
740system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14240256000 # number of WriteReq MSHR miss cycles
741system.cpu.dcache.WriteReq_mshr_miss_latency::total 14240256000 # number of WriteReq MSHR miss cycles
742system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1658671000 # number of SoftPFReq MSHR miss cycles
743system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1658671000 # number of SoftPFReq MSHR miss cycles
744system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 118600500 # number of LoadLockedReq MSHR miss cycles
745system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 118600500 # number of LoadLockedReq MSHR miss cycles
746system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 167000 # number of StoreCondReq MSHR miss cycles
747system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 167000 # number of StoreCondReq MSHR miss cycles
748system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20690108500 # number of demand (read+write) MSHR miss cycles
749system.cpu.dcache.demand_mshr_miss_latency::total 20690108500 # number of demand (read+write) MSHR miss cycles
750system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22348779500 # number of overall MSHR miss cycles
751system.cpu.dcache.overall_mshr_miss_latency::total 22348779500 # number of overall MSHR miss cycles
752system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6305317500 # number of ReadReq MSHR uncacheable cycles
753system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6305317500 # number of ReadReq MSHR uncacheable cycles
754system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6305317500 # number of overall MSHR uncacheable cycles
755system.cpu.dcache.overall_mshr_uncacheable_latency::total 6305317500 # number of overall MSHR uncacheable cycles
756system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017833 # mshr miss rate for ReadReq accesses
757system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017833 # mshr miss rate for ReadReq accesses
758system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015913 # mshr miss rate for WriteReq accesses
759system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015913 # mshr miss rate for WriteReq accesses
760system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230278 # mshr miss rate for SoftPFReq accesses
761system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230278 # mshr miss rate for SoftPFReq accesses
762system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017608 # mshr miss rate for LoadLockedReq accesses
763system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017608 # mshr miss rate for LoadLockedReq accesses
764system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
765system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
766system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016980 # mshr miss rate for demand accesses
767system.cpu.dcache.demand_mshr_miss_rate::total 0.016980 # mshr miss rate for demand accesses
768system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019602 # mshr miss rate for overall accesses
769system.cpu.dcache.overall_mshr_miss_rate::total 0.019602 # mshr miss rate for overall accesses
770system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15380.778357 # average ReadReq mshr miss latency
771system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15380.778357 # average ReadReq mshr miss latency
772system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47606.212767 # average WriteReq mshr miss latency
773system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47606.212767 # average WriteReq mshr miss latency
774system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13678.407085 # average SoftPFReq mshr miss latency
775system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13678.407085 # average SoftPFReq mshr miss latency
776system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14459.948793 # average LoadLockedReq mshr miss latency
777system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14459.948793 # average LoadLockedReq mshr miss latency
778system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 83500 # average StoreCondReq mshr miss latency
779system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 83500 # average StoreCondReq mshr miss latency
780system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28797.416319 # average overall mshr miss latency
781system.cpu.dcache.demand_avg_mshr_miss_latency::total 28797.416319 # average overall mshr miss latency
782system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26614.149378 # average overall mshr miss latency
783system.cpu.dcache.overall_avg_mshr_miss_latency::total 26614.149378 # average overall mshr miss latency
784system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202547.944105 # average ReadReq mshr uncacheable latency
785system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202547.944105 # average ReadReq mshr uncacheable latency
786system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107390.358347 # average overall mshr uncacheable latency
787system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107390.358347 # average overall mshr uncacheable latency
788system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
789system.cpu.icache.tags.replacements 2890432 # number of replacements
790system.cpu.icache.tags.tagsinuse 511.371135 # Cycle average of tags in use
791system.cpu.icache.tags.total_refs 54606166 # Total number of references to valid blocks.
792system.cpu.icache.tags.sampled_refs 2890944 # Sample count of references to valid blocks.
793system.cpu.icache.tags.avg_refs 18.888697 # Average number of references to valid blocks.
794system.cpu.icache.tags.warmup_cycle 16096310500 # Cycle when the warmup percentage was hit.
795system.cpu.icache.tags.occ_blocks::cpu.inst 511.371135 # Average occupied blocks per requestor
796system.cpu.icache.tags.occ_percent::cpu.inst 0.998772 # Average percentage of cache occupancy
797system.cpu.icache.tags.occ_percent::total 0.998772 # Average percentage of cache occupancy
798system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
799system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
800system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
801system.cpu.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id
802system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
803system.cpu.icache.tags.tag_accesses 60388077 # Number of tag accesses
804system.cpu.icache.tags.data_accesses 60388077 # Number of data accesses
805system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
806system.cpu.icache.ReadReq_hits::cpu.inst 54606166 # number of ReadReq hits
807system.cpu.icache.ReadReq_hits::total 54606166 # number of ReadReq hits
808system.cpu.icache.demand_hits::cpu.inst 54606166 # number of demand (read+write) hits
809system.cpu.icache.demand_hits::total 54606166 # number of demand (read+write) hits
810system.cpu.icache.overall_hits::cpu.inst 54606166 # number of overall hits
811system.cpu.icache.overall_hits::total 54606166 # number of overall hits
812system.cpu.icache.ReadReq_misses::cpu.inst 2890956 # number of ReadReq misses
813system.cpu.icache.ReadReq_misses::total 2890956 # number of ReadReq misses
814system.cpu.icache.demand_misses::cpu.inst 2890956 # number of demand (read+write) misses
815system.cpu.icache.demand_misses::total 2890956 # number of demand (read+write) misses
816system.cpu.icache.overall_misses::cpu.inst 2890956 # number of overall misses
817system.cpu.icache.overall_misses::total 2890956 # number of overall misses
818system.cpu.icache.ReadReq_miss_latency::cpu.inst 39801907000 # number of ReadReq miss cycles
819system.cpu.icache.ReadReq_miss_latency::total 39801907000 # number of ReadReq miss cycles
820system.cpu.icache.demand_miss_latency::cpu.inst 39801907000 # number of demand (read+write) miss cycles
821system.cpu.icache.demand_miss_latency::total 39801907000 # number of demand (read+write) miss cycles
822system.cpu.icache.overall_miss_latency::cpu.inst 39801907000 # number of overall miss cycles
823system.cpu.icache.overall_miss_latency::total 39801907000 # number of overall miss cycles
824system.cpu.icache.ReadReq_accesses::cpu.inst 57497122 # number of ReadReq accesses(hits+misses)
825system.cpu.icache.ReadReq_accesses::total 57497122 # number of ReadReq accesses(hits+misses)
826system.cpu.icache.demand_accesses::cpu.inst 57497122 # number of demand (read+write) accesses
827system.cpu.icache.demand_accesses::total 57497122 # number of demand (read+write) accesses
828system.cpu.icache.overall_accesses::cpu.inst 57497122 # number of overall (read+write) accesses
829system.cpu.icache.overall_accesses::total 57497122 # number of overall (read+write) accesses
830system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050280 # miss rate for ReadReq accesses
831system.cpu.icache.ReadReq_miss_rate::total 0.050280 # miss rate for ReadReq accesses
832system.cpu.icache.demand_miss_rate::cpu.inst 0.050280 # miss rate for demand accesses
833system.cpu.icache.demand_miss_rate::total 0.050280 # miss rate for demand accesses
834system.cpu.icache.overall_miss_rate::cpu.inst 0.050280 # miss rate for overall accesses
835system.cpu.icache.overall_miss_rate::total 0.050280 # miss rate for overall accesses
836system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13767.731851 # average ReadReq miss latency
837system.cpu.icache.ReadReq_avg_miss_latency::total 13767.731851 # average ReadReq miss latency
838system.cpu.icache.demand_avg_miss_latency::cpu.inst 13767.731851 # average overall miss latency
839system.cpu.icache.demand_avg_miss_latency::total 13767.731851 # average overall miss latency
840system.cpu.icache.overall_avg_miss_latency::cpu.inst 13767.731851 # average overall miss latency
841system.cpu.icache.overall_avg_miss_latency::total 13767.731851 # average overall miss latency
842system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
843system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
844system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
845system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
846system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
847system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
848system.cpu.icache.writebacks::writebacks 2890432 # number of writebacks
849system.cpu.icache.writebacks::total 2890432 # number of writebacks
850system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2890956 # number of ReadReq MSHR misses
851system.cpu.icache.ReadReq_mshr_misses::total 2890956 # number of ReadReq MSHR misses
852system.cpu.icache.demand_mshr_misses::cpu.inst 2890956 # number of demand (read+write) MSHR misses
853system.cpu.icache.demand_mshr_misses::total 2890956 # number of demand (read+write) MSHR misses
854system.cpu.icache.overall_mshr_misses::cpu.inst 2890956 # number of overall MSHR misses
855system.cpu.icache.overall_mshr_misses::total 2890956 # number of overall MSHR misses
856system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3119 # number of ReadReq MSHR uncacheable
857system.cpu.icache.ReadReq_mshr_uncacheable::total 3119 # number of ReadReq MSHR uncacheable
858system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3119 # number of overall MSHR uncacheable misses
859system.cpu.icache.overall_mshr_uncacheable_misses::total 3119 # number of overall MSHR uncacheable misses
860system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36910952000 # number of ReadReq MSHR miss cycles
861system.cpu.icache.ReadReq_mshr_miss_latency::total 36910952000 # number of ReadReq MSHR miss cycles
862system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36910952000 # number of demand (read+write) MSHR miss cycles
863system.cpu.icache.demand_mshr_miss_latency::total 36910952000 # number of demand (read+write) MSHR miss cycles
864system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36910952000 # number of overall MSHR miss cycles
865system.cpu.icache.overall_mshr_miss_latency::total 36910952000 # number of overall MSHR miss cycles
866system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 265216500 # number of ReadReq MSHR uncacheable cycles
867system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 265216500 # number of ReadReq MSHR uncacheable cycles
868system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 265216500 # number of overall MSHR uncacheable cycles
869system.cpu.icache.overall_mshr_uncacheable_latency::total 265216500 # number of overall MSHR uncacheable cycles
870system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050280 # mshr miss rate for ReadReq accesses
871system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050280 # mshr miss rate for ReadReq accesses
872system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050280 # mshr miss rate for demand accesses
873system.cpu.icache.demand_mshr_miss_rate::total 0.050280 # mshr miss rate for demand accesses
874system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050280 # mshr miss rate for overall accesses
875system.cpu.icache.overall_mshr_miss_rate::total 0.050280 # mshr miss rate for overall accesses
876system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12767.732197 # average ReadReq mshr miss latency
877system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12767.732197 # average ReadReq mshr miss latency
878system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12767.732197 # average overall mshr miss latency
879system.cpu.icache.demand_avg_mshr_miss_latency::total 12767.732197 # average overall mshr miss latency
880system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12767.732197 # average overall mshr miss latency
881system.cpu.icache.overall_avg_mshr_miss_latency::total 12767.732197 # average overall mshr miss latency
882system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 85032.542482 # average ReadReq mshr uncacheable latency
883system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 85032.542482 # average ReadReq mshr uncacheable latency
884system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 85032.542482 # average overall mshr uncacheable latency
885system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 85032.542482 # average overall mshr uncacheable latency
886system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
887system.cpu.l2cache.tags.replacements 96713 # number of replacements
888system.cpu.l2cache.tags.tagsinuse 65145.108369 # Cycle average of tags in use
889system.cpu.l2cache.tags.total_refs 7318914 # Total number of references to valid blocks.
890system.cpu.l2cache.tags.sampled_refs 162108 # Sample count of references to valid blocks.
891system.cpu.l2cache.tags.avg_refs 45.148383 # Average number of references to valid blocks.
892system.cpu.l2cache.tags.warmup_cycle 100163301000 # Cycle when the warmup percentage was hit.
893system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 70.225039 # Average occupied blocks per requestor
894system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.032952 # Average occupied blocks per requestor
895system.cpu.l2cache.tags.occ_blocks::cpu.inst 12109.105789 # Average occupied blocks per requestor
896system.cpu.l2cache.tags.occ_blocks::cpu.data 52965.744589 # Average occupied blocks per requestor
897system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001072 # Average percentage of cache occupancy
898system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy
899system.cpu.l2cache.tags.occ_percent::cpu.inst 0.184770 # Average percentage of cache occupancy
900system.cpu.l2cache.tags.occ_percent::cpu.data 0.808193 # Average percentage of cache occupancy
901system.cpu.l2cache.tags.occ_percent::total 0.994035 # Average percentage of cache occupancy
902system.cpu.l2cache.tags.occ_task_id_blocks::1023 46 # Occupied blocks per task id
903system.cpu.l2cache.tags.occ_task_id_blocks::1024 65349 # Occupied blocks per task id
904system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
905system.cpu.l2cache.tags.age_task_id_blocks_1023::4 45 # Occupied blocks per task id
906system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
907system.cpu.l2cache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id
908system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4579 # Occupied blocks per task id
909system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60686 # Occupied blocks per task id
910system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000702 # Percentage of cache occupancy per task id
911system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997147 # Percentage of cache occupancy per task id
912system.cpu.l2cache.tags.tag_accesses 60066606 # Number of tag accesses
913system.cpu.l2cache.tags.data_accesses 60066606 # Number of data accesses
914system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
915system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68164 # number of ReadReq hits
916system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3376 # number of ReadReq hits
917system.cpu.l2cache.ReadReq_hits::total 71540 # number of ReadReq hits
918system.cpu.l2cache.WritebackDirty_hits::writebacks 701993 # number of WritebackDirty hits
919system.cpu.l2cache.WritebackDirty_hits::total 701993 # number of WritebackDirty hits
920system.cpu.l2cache.WritebackClean_hits::writebacks 2839731 # number of WritebackClean hits
921system.cpu.l2cache.WritebackClean_hits::total 2839731 # number of WritebackClean hits
922system.cpu.l2cache.UpgradeReq_hits::cpu.data 2785 # number of UpgradeReq hits
923system.cpu.l2cache.UpgradeReq_hits::total 2785 # number of UpgradeReq hits
924system.cpu.l2cache.ReadExReq_hits::cpu.data 167030 # number of ReadExReq hits
925system.cpu.l2cache.ReadExReq_hits::total 167030 # number of ReadExReq hits
926system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2867992 # number of ReadCleanReq hits
927system.cpu.l2cache.ReadCleanReq_hits::total 2867992 # number of ReadCleanReq hits
928system.cpu.l2cache.ReadSharedReq_hits::cpu.data 534347 # number of ReadSharedReq hits
929system.cpu.l2cache.ReadSharedReq_hits::total 534347 # number of ReadSharedReq hits
930system.cpu.l2cache.demand_hits::cpu.dtb.walker 68164 # number of demand (read+write) hits
931system.cpu.l2cache.demand_hits::cpu.itb.walker 3376 # number of demand (read+write) hits
932system.cpu.l2cache.demand_hits::cpu.inst 2867992 # number of demand (read+write) hits
933system.cpu.l2cache.demand_hits::cpu.data 701377 # number of demand (read+write) hits
934system.cpu.l2cache.demand_hits::total 3640909 # number of demand (read+write) hits
935system.cpu.l2cache.overall_hits::cpu.dtb.walker 68164 # number of overall hits
936system.cpu.l2cache.overall_hits::cpu.itb.walker 3376 # number of overall hits
937system.cpu.l2cache.overall_hits::cpu.inst 2867992 # number of overall hits
938system.cpu.l2cache.overall_hits::cpu.data 701377 # number of overall hits
939system.cpu.l2cache.overall_hits::total 3640909 # number of overall hits
940system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 106 # number of ReadReq misses
941system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
942system.cpu.l2cache.ReadReq_misses::total 108 # number of ReadReq misses
943system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses
944system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses
945system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
946system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
947system.cpu.l2cache.ReadExReq_misses::cpu.data 129309 # number of ReadExReq misses
948system.cpu.l2cache.ReadExReq_misses::total 129309 # number of ReadExReq misses
949system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22923 # number of ReadCleanReq misses
950system.cpu.l2cache.ReadCleanReq_misses::total 22923 # number of ReadCleanReq misses
951system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14458 # number of ReadSharedReq misses
952system.cpu.l2cache.ReadSharedReq_misses::total 14458 # number of ReadSharedReq misses
953system.cpu.l2cache.demand_misses::cpu.dtb.walker 106 # number of demand (read+write) misses
954system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
955system.cpu.l2cache.demand_misses::cpu.inst 22923 # number of demand (read+write) misses
956system.cpu.l2cache.demand_misses::cpu.data 143767 # number of demand (read+write) misses
957system.cpu.l2cache.demand_misses::total 166798 # number of demand (read+write) misses
958system.cpu.l2cache.overall_misses::cpu.dtb.walker 106 # number of overall misses
959system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
960system.cpu.l2cache.overall_misses::cpu.inst 22923 # number of overall misses
961system.cpu.l2cache.overall_misses::cpu.data 143767 # number of overall misses
962system.cpu.l2cache.overall_misses::total 166798 # number of overall misses
963system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 35537000 # number of ReadReq miss cycles
964system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 193500 # number of ReadReq miss cycles
965system.cpu.l2cache.ReadReq_miss_latency::total 35730500 # number of ReadReq miss cycles
966system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 172000 # number of UpgradeReq miss cycles
967system.cpu.l2cache.UpgradeReq_miss_latency::total 172000 # number of UpgradeReq miss cycles
968system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 164000 # number of SCUpgradeReq miss cycles
969system.cpu.l2cache.SCUpgradeReq_miss_latency::total 164000 # number of SCUpgradeReq miss cycles
970system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12000174000 # number of ReadExReq miss cycles
971system.cpu.l2cache.ReadExReq_miss_latency::total 12000174000 # number of ReadExReq miss cycles
972system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2393515000 # number of ReadCleanReq miss cycles
973system.cpu.l2cache.ReadCleanReq_miss_latency::total 2393515000 # number of ReadCleanReq miss cycles
974system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1752753500 # number of ReadSharedReq miss cycles
975system.cpu.l2cache.ReadSharedReq_miss_latency::total 1752753500 # number of ReadSharedReq miss cycles
976system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 35537000 # number of demand (read+write) miss cycles
977system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 193500 # number of demand (read+write) miss cycles
978system.cpu.l2cache.demand_miss_latency::cpu.inst 2393515000 # number of demand (read+write) miss cycles
979system.cpu.l2cache.demand_miss_latency::cpu.data 13752927500 # number of demand (read+write) miss cycles
980system.cpu.l2cache.demand_miss_latency::total 16182173000 # number of demand (read+write) miss cycles
981system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 35537000 # number of overall miss cycles
982system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 193500 # number of overall miss cycles
983system.cpu.l2cache.overall_miss_latency::cpu.inst 2393515000 # number of overall miss cycles
984system.cpu.l2cache.overall_miss_latency::cpu.data 13752927500 # number of overall miss cycles
985system.cpu.l2cache.overall_miss_latency::total 16182173000 # number of overall miss cycles
986system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68270 # number of ReadReq accesses(hits+misses)
987system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3378 # number of ReadReq accesses(hits+misses)
988system.cpu.l2cache.ReadReq_accesses::total 71648 # number of ReadReq accesses(hits+misses)
989system.cpu.l2cache.WritebackDirty_accesses::writebacks 701993 # number of WritebackDirty accesses(hits+misses)
990system.cpu.l2cache.WritebackDirty_accesses::total 701993 # number of WritebackDirty accesses(hits+misses)
991system.cpu.l2cache.WritebackClean_accesses::writebacks 2839731 # number of WritebackClean accesses(hits+misses)
992system.cpu.l2cache.WritebackClean_accesses::total 2839731 # number of WritebackClean accesses(hits+misses)
993system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2791 # number of UpgradeReq accesses(hits+misses)
994system.cpu.l2cache.UpgradeReq_accesses::total 2791 # number of UpgradeReq accesses(hits+misses)
995system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
996system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
997system.cpu.l2cache.ReadExReq_accesses::cpu.data 296339 # number of ReadExReq accesses(hits+misses)
998system.cpu.l2cache.ReadExReq_accesses::total 296339 # number of ReadExReq accesses(hits+misses)
999system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2890915 # number of ReadCleanReq accesses(hits+misses)
1000system.cpu.l2cache.ReadCleanReq_accesses::total 2890915 # number of ReadCleanReq accesses(hits+misses)
1001system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 548805 # number of ReadSharedReq accesses(hits+misses)
1002system.cpu.l2cache.ReadSharedReq_accesses::total 548805 # number of ReadSharedReq accesses(hits+misses)
1003system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68270 # number of demand (read+write) accesses
1004system.cpu.l2cache.demand_accesses::cpu.itb.walker 3378 # number of demand (read+write) accesses
1005system.cpu.l2cache.demand_accesses::cpu.inst 2890915 # number of demand (read+write) accesses
1006system.cpu.l2cache.demand_accesses::cpu.data 845144 # number of demand (read+write) accesses
1007system.cpu.l2cache.demand_accesses::total 3807707 # number of demand (read+write) accesses
1008system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68270 # number of overall (read+write) accesses
1009system.cpu.l2cache.overall_accesses::cpu.itb.walker 3378 # number of overall (read+write) accesses
1010system.cpu.l2cache.overall_accesses::cpu.inst 2890915 # number of overall (read+write) accesses
1011system.cpu.l2cache.overall_accesses::cpu.data 845144 # number of overall (read+write) accesses
1012system.cpu.l2cache.overall_accesses::total 3807707 # number of overall (read+write) accesses
1013system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001553 # miss rate for ReadReq accesses
1014system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000592 # miss rate for ReadReq accesses
1015system.cpu.l2cache.ReadReq_miss_rate::total 0.001507 # miss rate for ReadReq accesses
1016system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.002150 # miss rate for UpgradeReq accesses
1017system.cpu.l2cache.UpgradeReq_miss_rate::total 0.002150 # miss rate for UpgradeReq accesses
1018system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
1019system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1020system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436355 # miss rate for ReadExReq accesses
1021system.cpu.l2cache.ReadExReq_miss_rate::total 0.436355 # miss rate for ReadExReq accesses
1022system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007929 # miss rate for ReadCleanReq accesses
1023system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007929 # miss rate for ReadCleanReq accesses
1024system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026345 # miss rate for ReadSharedReq accesses
1025system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026345 # miss rate for ReadSharedReq accesses
1026system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001553 # miss rate for demand accesses
1027system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000592 # miss rate for demand accesses
1028system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007929 # miss rate for demand accesses
1029system.cpu.l2cache.demand_miss_rate::cpu.data 0.170109 # miss rate for demand accesses
1030system.cpu.l2cache.demand_miss_rate::total 0.043805 # miss rate for demand accesses
1031system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001553 # miss rate for overall accesses
1032system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000592 # miss rate for overall accesses
1033system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007929 # miss rate for overall accesses
1034system.cpu.l2cache.overall_miss_rate::cpu.data 0.170109 # miss rate for overall accesses
1035system.cpu.l2cache.overall_miss_rate::total 0.043805 # miss rate for overall accesses
1036system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 335254.716981 # average ReadReq miss latency
1037system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 96750 # average ReadReq miss latency
1038system.cpu.l2cache.ReadReq_avg_miss_latency::total 330837.962963 # average ReadReq miss latency
1039system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 28666.666667 # average UpgradeReq miss latency
1040system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 28666.666667 # average UpgradeReq miss latency
1041system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82000 # average SCUpgradeReq miss latency
1042system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82000 # average SCUpgradeReq miss latency
1043system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92802.310744 # average ReadExReq miss latency
1044system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92802.310744 # average ReadExReq miss latency
1045system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 104415.434280 # average ReadCleanReq miss latency
1046system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 104415.434280 # average ReadCleanReq miss latency
1047system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 121230.702725 # average ReadSharedReq miss latency
1048system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 121230.702725 # average ReadSharedReq miss latency
1049system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 335254.716981 # average overall miss latency
1050system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 96750 # average overall miss latency
1051system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 104415.434280 # average overall miss latency
1052system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95661.226151 # average overall miss latency
1053system.cpu.l2cache.demand_avg_miss_latency::total 97016.588928 # average overall miss latency
1054system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 335254.716981 # average overall miss latency
1055system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 96750 # average overall miss latency
1056system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 104415.434280 # average overall miss latency
1057system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95661.226151 # average overall miss latency
1058system.cpu.l2cache.overall_avg_miss_latency::total 97016.588928 # average overall miss latency
1059system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1060system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1061system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1062system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1063system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1064system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1065system.cpu.l2cache.writebacks::writebacks 88134 # number of writebacks
1066system.cpu.l2cache.writebacks::total 88134 # number of writebacks
1067system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 15 # number of ReadCleanReq MSHR hits
1068system.cpu.l2cache.ReadCleanReq_mshr_hits::total 15 # number of ReadCleanReq MSHR hits
1069system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 143 # number of ReadSharedReq MSHR hits
1070system.cpu.l2cache.ReadSharedReq_mshr_hits::total 143 # number of ReadSharedReq MSHR hits
1071system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits
1072system.cpu.l2cache.demand_mshr_hits::cpu.data 143 # number of demand (read+write) MSHR hits
1073system.cpu.l2cache.demand_mshr_hits::total 158 # number of demand (read+write) MSHR hits
1074system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits
1075system.cpu.l2cache.overall_mshr_hits::cpu.data 143 # number of overall MSHR hits
1076system.cpu.l2cache.overall_mshr_hits::total 158 # number of overall MSHR hits
1077system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 106 # number of ReadReq MSHR misses
1078system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
1079system.cpu.l2cache.ReadReq_mshr_misses::total 108 # number of ReadReq MSHR misses
1080system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses
1081system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses
1082system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
1083system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
1084system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 129309 # number of ReadExReq MSHR misses
1085system.cpu.l2cache.ReadExReq_mshr_misses::total 129309 # number of ReadExReq MSHR misses
1086system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22908 # number of ReadCleanReq MSHR misses
1087system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22908 # number of ReadCleanReq MSHR misses
1088system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14315 # number of ReadSharedReq MSHR misses
1089system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14315 # number of ReadSharedReq MSHR misses
1090system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 106 # number of demand (read+write) MSHR misses
1091system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
1092system.cpu.l2cache.demand_mshr_misses::cpu.inst 22908 # number of demand (read+write) MSHR misses
1093system.cpu.l2cache.demand_mshr_misses::cpu.data 143624 # number of demand (read+write) MSHR misses
1094system.cpu.l2cache.demand_mshr_misses::total 166640 # number of demand (read+write) MSHR misses
1095system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 106 # number of overall MSHR misses
1096system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
1097system.cpu.l2cache.overall_mshr_misses::cpu.inst 22908 # number of overall MSHR misses
1098system.cpu.l2cache.overall_mshr_misses::cpu.data 143624 # number of overall MSHR misses
1099system.cpu.l2cache.overall_mshr_misses::total 166640 # number of overall MSHR misses
1100system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3119 # number of ReadReq MSHR uncacheable
1101system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable
1102system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34249 # number of ReadReq MSHR uncacheable
1103system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
1104system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
1105system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3119 # number of overall MSHR uncacheable misses
1106system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses
1107system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61833 # number of overall MSHR uncacheable misses
1108system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 34477000 # number of ReadReq MSHR miss cycles
1109system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 173500 # number of ReadReq MSHR miss cycles
1110system.cpu.l2cache.ReadReq_mshr_miss_latency::total 34650500 # number of ReadReq MSHR miss cycles
1111system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 112000 # number of UpgradeReq MSHR miss cycles
1112system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 112000 # number of UpgradeReq MSHR miss cycles
1113system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 144000 # number of SCUpgradeReq MSHR miss cycles
1114system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 144000 # number of SCUpgradeReq MSHR miss cycles
1115system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10707084000 # number of ReadExReq MSHR miss cycles
1116system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10707084000 # number of ReadExReq MSHR miss cycles
1117system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2162492500 # number of ReadCleanReq MSHR miss cycles
1118system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2162492500 # number of ReadCleanReq MSHR miss cycles
1119system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1597831000 # number of ReadSharedReq MSHR miss cycles
1120system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1597831000 # number of ReadSharedReq MSHR miss cycles
1121system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 34477000 # number of demand (read+write) MSHR miss cycles
1122system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 173500 # number of demand (read+write) MSHR miss cycles
1123system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2162492500 # number of demand (read+write) MSHR miss cycles
1124system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12304915000 # number of demand (read+write) MSHR miss cycles
1125system.cpu.l2cache.demand_mshr_miss_latency::total 14502058000 # number of demand (read+write) MSHR miss cycles
1126system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 34477000 # number of overall MSHR miss cycles
1127system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 173500 # number of overall MSHR miss cycles
1128system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2162492500 # number of overall MSHR miss cycles
1129system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12304915000 # number of overall MSHR miss cycles
1130system.cpu.l2cache.overall_mshr_miss_latency::total 14502058000 # number of overall MSHR miss cycles
1131system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 216819500 # number of ReadReq MSHR uncacheable cycles
1132system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5916117000 # number of ReadReq MSHR uncacheable cycles
1133system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6132936500 # number of ReadReq MSHR uncacheable cycles
1134system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 216819500 # number of overall MSHR uncacheable cycles
1135system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5916117000 # number of overall MSHR uncacheable cycles
1136system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6132936500 # number of overall MSHR uncacheable cycles
1137system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001553 # mshr miss rate for ReadReq accesses
1138system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000592 # mshr miss rate for ReadReq accesses
1139system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001507 # mshr miss rate for ReadReq accesses
1140system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.002150 # mshr miss rate for UpgradeReq accesses
1141system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.002150 # mshr miss rate for UpgradeReq accesses
1142system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
1143system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1144system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436355 # mshr miss rate for ReadExReq accesses
1145system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436355 # mshr miss rate for ReadExReq accesses
1146system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007924 # mshr miss rate for ReadCleanReq accesses
1147system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007924 # mshr miss rate for ReadCleanReq accesses
1148system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026084 # mshr miss rate for ReadSharedReq accesses
1149system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026084 # mshr miss rate for ReadSharedReq accesses
1150system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001553 # mshr miss rate for demand accesses
1151system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000592 # mshr miss rate for demand accesses
1152system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007924 # mshr miss rate for demand accesses
1153system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.169940 # mshr miss rate for demand accesses
1154system.cpu.l2cache.demand_mshr_miss_rate::total 0.043764 # mshr miss rate for demand accesses
1155system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001553 # mshr miss rate for overall accesses
1156system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000592 # mshr miss rate for overall accesses
1157system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007924 # mshr miss rate for overall accesses
1158system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.169940 # mshr miss rate for overall accesses
1159system.cpu.l2cache.overall_mshr_miss_rate::total 0.043764 # mshr miss rate for overall accesses
1160system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 325254.716981 # average ReadReq mshr miss latency
1161system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 86750 # average ReadReq mshr miss latency
1162system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 320837.962963 # average ReadReq mshr miss latency
1163system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18666.666667 # average UpgradeReq mshr miss latency
1164system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18666.666667 # average UpgradeReq mshr miss latency
1165system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72000 # average SCUpgradeReq mshr miss latency
1166system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency
1167system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82802.310744 # average ReadExReq mshr miss latency
1168system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82802.310744 # average ReadExReq mshr miss latency
1169system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 94399.009080 # average ReadCleanReq mshr miss latency
1170system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 94399.009080 # average ReadCleanReq mshr miss latency
1171system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 111619.350332 # average ReadSharedReq mshr miss latency
1172system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 111619.350332 # average ReadSharedReq mshr miss latency
1173system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 325254.716981 # average overall mshr miss latency
1174system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 86750 # average overall mshr miss latency
1175system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 94399.009080 # average overall mshr miss latency
1176system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85674.504261 # average overall mshr miss latency
1177system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87026.272204 # average overall mshr miss latency
1178system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 325254.716981 # average overall mshr miss latency
1179system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 86750 # average overall mshr miss latency
1180system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 94399.009080 # average overall mshr miss latency
1181system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85674.504261 # average overall mshr miss latency
1182system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87026.272204 # average overall mshr miss latency
1183system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69515.710164 # average ReadReq mshr uncacheable latency
1184system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190045.518792 # average ReadReq mshr uncacheable latency
1185system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 179069.067710 # average ReadReq mshr uncacheable latency
1186system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69515.710164 # average overall mshr uncacheable latency
1187system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100761.607112 # average overall mshr uncacheable latency
1188system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 99185.491566 # average overall mshr uncacheable latency
1189system.cpu.toL2Bus.snoop_filter.tot_requests 7504755 # Total number of requests made to the snoop filter.
1190system.cpu.toL2Bus.snoop_filter.hit_single_requests 3768676 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1191system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58052 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1192system.cpu.toL2Bus.snoop_filter.tot_snoops 184 # Total number of snoops made to the snoop filter.
1193system.cpu.toL2Bus.snoop_filter.hit_single_snoops 184 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1194system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1195system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1196system.cpu.toL2Bus.trans_dist::ReadReq 136721 # Transaction distribution
1197system.cpu.toL2Bus.trans_dist::ReadResp 3576628 # Transaction distribution
1198system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
1199system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution
1200system.cpu.toL2Bus.trans_dist::WritebackDirty 790127 # Transaction distribution
1201system.cpu.toL2Bus.trans_dist::WritebackClean 2890432 # Transaction distribution
1202system.cpu.toL2Bus.trans_dist::CleanEvict 151192 # Transaction distribution
1203system.cpu.toL2Bus.trans_dist::UpgradeReq 2791 # Transaction distribution
1204system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1205system.cpu.toL2Bus.trans_dist::UpgradeResp 2793 # Transaction distribution
1206system.cpu.toL2Bus.trans_dist::ReadExReq 296339 # Transaction distribution
1207system.cpu.toL2Bus.trans_dist::ReadExResp 296339 # Transaction distribution
1208system.cpu.toL2Bus.trans_dist::ReadCleanReq 2890956 # Transaction distribution
1209system.cpu.toL2Bus.trans_dist::ReadSharedReq 549028 # Transaction distribution
1210system.cpu.toL2Bus.trans_dist::InvalidateReq 4410 # Transaction distribution
1211system.cpu.toL2Bus.trans_dist::InvalidateResp 13 # Transaction distribution
1212system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8678540 # Packet count per connected master and slave (bytes)
1213system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2658068 # Packet count per connected master and slave (bytes)
1214system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14779 # Packet count per connected master and slave (bytes)
1215system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159341 # Packet count per connected master and slave (bytes)
1216system.cpu.toL2Bus.pkt_count::total 11510728 # Packet count per connected master and slave (bytes)
1217system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370205760 # Cumulative packet size per connected master and slave (bytes)
1218system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99209257 # Cumulative packet size per connected master and slave (bytes)
1219system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13512 # Cumulative packet size per connected master and slave (bytes)
1220system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 273080 # Cumulative packet size per connected master and slave (bytes)
1221system.cpu.toL2Bus.pkt_size::total 469701609 # Cumulative packet size per connected master and slave (bytes)
1222system.cpu.toL2Bus.snoops 132371 # Total snoops (count)
1223system.cpu.toL2Bus.snoopTraffic 5775904 # Total snoop traffic (bytes)
1224system.cpu.toL2Bus.snoop_fanout::samples 4004544 # Request fanout histogram
1225system.cpu.toL2Bus.snoop_fanout::mean 0.022245 # Request fanout histogram
1226system.cpu.toL2Bus.snoop_fanout::stdev 0.147479 # Request fanout histogram
1227system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1228system.cpu.toL2Bus.snoop_fanout::0 3915463 97.78% 97.78% # Request fanout histogram
1229system.cpu.toL2Bus.snoop_fanout::1 89081 2.22% 100.00% # Request fanout histogram
1230system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1231system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1232system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1233system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
1234system.cpu.toL2Bus.snoop_fanout::total 4004544 # Request fanout histogram
1235system.cpu.toL2Bus.reqLayer0.occupancy 7425335000 # Layer occupancy (ticks)
1236system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
1237system.cpu.toL2Bus.snoopLayer0.occupancy 287877 # Layer occupancy (ticks)
1238system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1239system.cpu.toL2Bus.respLayer0.occupancy 4341709800 # Layer occupancy (ticks)
1240system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
1241system.cpu.toL2Bus.respLayer1.occupancy 1314266535 # Layer occupancy (ticks)
1242system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1243system.cpu.toL2Bus.respLayer2.occupancy 11403994 # Layer occupancy (ticks)
1244system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1245system.cpu.toL2Bus.respLayer3.occupancy 91100441 # Layer occupancy (ticks)
1246system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1247system.iobus.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1248system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
1249system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
1250system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
1251system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
1252system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
1253system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
1254system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
1255system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
1256system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
1257system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
1258system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
1259system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
1260system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1261system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1262system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1263system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
1264system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1265system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
1266system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
1267system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
1268system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
1269system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
1270system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
1271system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
1272system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
1273system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
1274system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes)
1275system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
1276system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
1277system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
1278system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
1279system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
1280system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
1281system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
1282system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
1283system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1284system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1285system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1286system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
1287system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1288system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1289system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
1290system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
1291system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1292system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
1293system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
1294system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
1295system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
1296system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
1297system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes)
1298system.iobus.reqLayer0.occupancy 46325500 # Layer occupancy (ticks)
1299system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1300system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks)
1301system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1302system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks)
1303system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1304system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks)
1305system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1306system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks)
1307system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1308system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks)
1309system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1310system.iobus.reqLayer8.occupancy 623000 # Layer occupancy (ticks)
1311system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
1312system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks)
1313system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1314system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks)
1315system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1316system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
1317system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1318system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks)
1319system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1320system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks)
1321system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1322system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks)
1323system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1324system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
1325system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1326system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
1327system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1328system.iobus.reqLayer20.occupancy 10000 # Layer occupancy (ticks)
1329system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1330system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks)
1331system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
1332system.iobus.reqLayer23.occupancy 6084500 # Layer occupancy (ticks)
1333system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1334system.iobus.reqLayer24.occupancy 39097500 # Layer occupancy (ticks)
1335system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1336system.iobus.reqLayer25.occupancy 187729822 # Layer occupancy (ticks)
1337system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1338system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
1339system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1340system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks)
1341system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1342system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1343system.iocache.tags.replacements 36424 # number of replacements
1344system.iocache.tags.tagsinuse 1.033985 # Cycle average of tags in use
1345system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1346system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
1347system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1348system.iocache.tags.warmup_cycle 272037045000 # Cycle when the warmup percentage was hit.
1349system.iocache.tags.occ_blocks::realview.ide 1.033985 # Average occupied blocks per requestor
1350system.iocache.tags.occ_percent::realview.ide 0.064624 # Average percentage of cache occupancy
1351system.iocache.tags.occ_percent::total 0.064624 # Average percentage of cache occupancy
1352system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1353system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1354system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1355system.iocache.tags.tag_accesses 328122 # Number of tag accesses
1356system.iocache.tags.data_accesses 328122 # Number of data accesses
1357system.iocache.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1358system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
1359system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
1360system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
1361system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
1362system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses
1363system.iocache.demand_misses::total 36458 # number of demand (read+write) misses
1364system.iocache.overall_misses::realview.ide 36458 # number of overall misses
1365system.iocache.overall_misses::total 36458 # number of overall misses
1366system.iocache.ReadReq_miss_latency::realview.ide 37405377 # number of ReadReq miss cycles
1367system.iocache.ReadReq_miss_latency::total 37405377 # number of ReadReq miss cycles
1368system.iocache.WriteLineReq_miss_latency::realview.ide 4361655445 # number of WriteLineReq miss cycles
1369system.iocache.WriteLineReq_miss_latency::total 4361655445 # number of WriteLineReq miss cycles
1370system.iocache.demand_miss_latency::realview.ide 4399060822 # number of demand (read+write) miss cycles
1371system.iocache.demand_miss_latency::total 4399060822 # number of demand (read+write) miss cycles
1372system.iocache.overall_miss_latency::realview.ide 4399060822 # number of overall miss cycles
1373system.iocache.overall_miss_latency::total 4399060822 # number of overall miss cycles
1374system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
1375system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
1376system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
1377system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
1378system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses
1379system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses
1380system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses
1381system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses
1382system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1383system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1384system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
1385system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1386system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1387system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1388system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1389system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1390system.iocache.ReadReq_avg_miss_latency::realview.ide 159852.038462 # average ReadReq miss latency
1391system.iocache.ReadReq_avg_miss_latency::total 159852.038462 # average ReadReq miss latency
1392system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120407.891039 # average WriteLineReq miss latency
1393system.iocache.WriteLineReq_avg_miss_latency::total 120407.891039 # average WriteLineReq miss latency
1394system.iocache.demand_avg_miss_latency::realview.ide 120661.057162 # average overall miss latency
1395system.iocache.demand_avg_miss_latency::total 120661.057162 # average overall miss latency
1396system.iocache.overall_avg_miss_latency::realview.ide 120661.057162 # average overall miss latency
1397system.iocache.overall_avg_miss_latency::total 120661.057162 # average overall miss latency
1398system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1399system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1400system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1401system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1402system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1403system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1404system.iocache.writebacks::writebacks 36190 # number of writebacks
1405system.iocache.writebacks::total 36190 # number of writebacks
1406system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses
1407system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses
1408system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
1409system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
1410system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses
1411system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses
1412system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses
1413system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses
1414system.iocache.ReadReq_mshr_miss_latency::realview.ide 25705377 # number of ReadReq MSHR miss cycles
1415system.iocache.ReadReq_mshr_miss_latency::total 25705377 # number of ReadReq MSHR miss cycles
1416system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2548589823 # number of WriteLineReq MSHR miss cycles
1417system.iocache.WriteLineReq_mshr_miss_latency::total 2548589823 # number of WriteLineReq MSHR miss cycles
1418system.iocache.demand_mshr_miss_latency::realview.ide 2574295200 # number of demand (read+write) MSHR miss cycles
1419system.iocache.demand_mshr_miss_latency::total 2574295200 # number of demand (read+write) MSHR miss cycles
1420system.iocache.overall_mshr_miss_latency::realview.ide 2574295200 # number of overall MSHR miss cycles
1421system.iocache.overall_mshr_miss_latency::total 2574295200 # number of overall MSHR miss cycles
1422system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1423system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1424system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
1425system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1426system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1427system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1428system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1429system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1430system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 109852.038462 # average ReadReq mshr miss latency
1431system.iocache.ReadReq_avg_mshr_miss_latency::total 109852.038462 # average ReadReq mshr miss latency
1432system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70356.388665 # average WriteLineReq mshr miss latency
1433system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70356.388665 # average WriteLineReq mshr miss latency
1434system.iocache.demand_avg_mshr_miss_latency::realview.ide 70609.885348 # average overall mshr miss latency
1435system.iocache.demand_avg_mshr_miss_latency::total 70609.885348 # average overall mshr miss latency
1436system.iocache.overall_avg_mshr_miss_latency::realview.ide 70609.885348 # average overall mshr miss latency
1437system.iocache.overall_avg_mshr_miss_latency::total 70609.885348 # average overall mshr miss latency
1438system.membus.snoop_filter.tot_requests 336307 # Total number of requests made to the snoop filter.
1439system.membus.snoop_filter.hit_single_requests 137733 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1440system.membus.snoop_filter.hit_multi_requests 538 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1441system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1442system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1443system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1444system.membus.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1445system.membus.trans_dist::ReadReq 34249 # Transaction distribution
1446system.membus.trans_dist::ReadResp 71814 # Transaction distribution
1447system.membus.trans_dist::WriteReq 27584 # Transaction distribution
1448system.membus.trans_dist::WriteResp 27584 # Transaction distribution
1449system.membus.trans_dist::WritebackDirty 124324 # Transaction distribution
1450system.membus.trans_dist::CleanEvict 8813 # Transaction distribution
1451system.membus.trans_dist::UpgradeReq 128 # Transaction distribution
1452system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1453system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
1454system.membus.trans_dist::ReadExReq 129187 # Transaction distribution
1455system.membus.trans_dist::ReadExResp 129187 # Transaction distribution
1456system.membus.trans_dist::ReadSharedReq 37565 # Transaction distribution
1457system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
1458system.membus.trans_dist::InvalidateResp 4361 # Transaction distribution
1459system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
1460system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
1461system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes)
1462system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445694 # Packet count per connected master and slave (bytes)
1463system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553262 # Packet count per connected master and slave (bytes)
1464system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes)
1465system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes)
1466system.membus.pkt_count::total 626159 # Packet count per connected master and slave (bytes)
1467system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
1468system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes)
1469system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes)
1470system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16498528 # Cumulative packet size per connected master and slave (bytes)
1471system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16662313 # Cumulative packet size per connected master and slave (bytes)
1472system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
1473system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
1474system.membus.pkt_size::total 18979433 # Cumulative packet size per connected master and slave (bytes)
1475system.membus.snoops 4865 # Total snoops (count)
1476system.membus.snoopTraffic 32128 # Total snoop traffic (bytes)
1477system.membus.snoop_fanout::samples 264939 # Request fanout histogram
1478system.membus.snoop_fanout::mean 0.018563 # Request fanout histogram
1479system.membus.snoop_fanout::stdev 0.134975 # Request fanout histogram
1480system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1481system.membus.snoop_fanout::0 260021 98.14% 98.14% # Request fanout histogram
1482system.membus.snoop_fanout::1 4918 1.86% 100.00% # Request fanout histogram
1483system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1484system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1485system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1486system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1487system.membus.snoop_fanout::total 264939 # Request fanout histogram
1488system.membus.reqLayer0.occupancy 92843000 # Layer occupancy (ticks)
1489system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1490system.membus.reqLayer1.occupancy 8000 # Layer occupancy (ticks)
1491system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1492system.membus.reqLayer2.occupancy 1694500 # Layer occupancy (ticks)
1493system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1494system.membus.reqLayer5.occupancy 903707925 # Layer occupancy (ticks)
1495system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1496system.membus.respLayer2.occupancy 987836250 # Layer occupancy (ticks)
1497system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1498system.membus.respLayer3.occupancy 5807414 # Layer occupancy (ticks)
1499system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1500system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1501system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1502system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1503system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1504system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1505system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1506system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1507system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
1508system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
1509system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
1510system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
1511system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
1512system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
1513system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1514system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1515system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1516system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1517system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1518system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1519system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1520system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1521system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
1522system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
1523system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
1524system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
1525system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
1526system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
1527system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
1528system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
1529system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
1530system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
1531system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
1532system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
1533system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
1534system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
1535system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
1536system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
1537system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
1538system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1539system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1540system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1541system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1542system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1543system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1544system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
1545system.realview.ethernet.droppedPackets 0 # number of packets dropped
1546system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1547system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1548system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1549system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1550system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1551system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1552system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1553system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
1554system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
1555system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
1556system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
1557system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1558system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1559system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1560system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1561system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1562system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1563system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1564system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1565system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1566system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1567system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
1568system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states
| 3sim_seconds 2.854928
4sim_ticks 2854927627500
5final_tick 2854927627500
6sim_freq 1000000000000
7host_inst_rate 259896
8host_op_rate 314233
9host_tick_rate 6638397944
10host_mem_usage 597276
11host_seconds 430.06
12sim_insts 111771703
13sim_ops 135139786
14system.voltage_domain.voltage 1
15system.clk_domain.clock 1000
16system.physmem.pwrStateResidencyTicks::UNDEFINED 2854927627500
17system.physmem.bytes_read::cpu.dtb.walker 6976
18system.physmem.bytes_read::cpu.itb.walker 128
19system.physmem.bytes_read::cpu.inst 1665856
20system.physmem.bytes_read::cpu.data 9168876
21system.physmem.bytes_read::realview.ide 960
22system.physmem.bytes_read::total 10842796
23system.physmem.bytes_inst_read::cpu.inst 1665856
24system.physmem.bytes_inst_read::total 1665856
25system.physmem.bytes_written::writebacks 7956992
26system.physmem.bytes_written::cpu.data 17524
27system.physmem.bytes_written::total 7974516
28system.physmem.num_reads::cpu.dtb.walker 109
29system.physmem.num_reads::cpu.itb.walker 2
30system.physmem.num_reads::cpu.inst 26029
31system.physmem.num_reads::cpu.data 143785
32system.physmem.num_reads::realview.ide 15
33system.physmem.num_reads::total 169940
34system.physmem.num_writes::writebacks 124328
35system.physmem.num_writes::cpu.data 4381
36system.physmem.num_writes::total 128709
37system.physmem.bw_read::cpu.dtb.walker 2443
38system.physmem.bw_read::cpu.itb.walker 45
39system.physmem.bw_read::cpu.inst 583502
40system.physmem.bw_read::cpu.data 3211597
41system.physmem.bw_read::realview.ide 336
42system.physmem.bw_read::total 3797923
43system.physmem.bw_inst_read::cpu.inst 583502
44system.physmem.bw_inst_read::total 583502
45system.physmem.bw_write::writebacks 2787108
46system.physmem.bw_write::cpu.data 6138
47system.physmem.bw_write::total 2793246
48system.physmem.bw_total::writebacks 2787108
49system.physmem.bw_total::cpu.dtb.walker 2443
50system.physmem.bw_total::cpu.itb.walker 45
51system.physmem.bw_total::cpu.inst 583502
52system.physmem.bw_total::cpu.data 3217735
53system.physmem.bw_total::realview.ide 336
54system.physmem.bw_total::total 6591170
55system.physmem.readReqs 169940
56system.physmem.writeReqs 128709
57system.physmem.readBursts 169940
58system.physmem.writeBursts 128709
59system.physmem.bytesReadDRAM 10867392
60system.physmem.bytesReadWrQ 8768
61system.physmem.bytesWritten 7987136
62system.physmem.bytesReadSys 10842796
63system.physmem.bytesWrittenSys 7974516
64system.physmem.servicedByWrQ 137
65system.physmem.mergedWrBursts 3888
66system.physmem.neitherReadNorWriteReqs 0
67system.physmem.perBankRdBursts::0 10681
68system.physmem.perBankRdBursts::1 10442
69system.physmem.perBankRdBursts::2 10751
70system.physmem.perBankRdBursts::3 10388
71system.physmem.perBankRdBursts::4 13039
72system.physmem.perBankRdBursts::5 10185
73system.physmem.perBankRdBursts::6 10269
74system.physmem.perBankRdBursts::7 10713
75system.physmem.perBankRdBursts::8 10427
76system.physmem.perBankRdBursts::9 10646
77system.physmem.perBankRdBursts::10 10209
78system.physmem.perBankRdBursts::11 9539
79system.physmem.perBankRdBursts::12 10748
80system.physmem.perBankRdBursts::13 11527
81system.physmem.perBankRdBursts::14 10187
82system.physmem.perBankRdBursts::15 10052
83system.physmem.perBankWrBursts::0 7942
84system.physmem.perBankWrBursts::1 7866
85system.physmem.perBankWrBursts::2 8424
86system.physmem.perBankWrBursts::3 7907
87system.physmem.perBankWrBursts::4 7304
88system.physmem.perBankWrBursts::5 7363
89system.physmem.perBankWrBursts::6 7424
90system.physmem.perBankWrBursts::7 7906
91system.physmem.perBankWrBursts::8 7951
92system.physmem.perBankWrBursts::9 8140
93system.physmem.perBankWrBursts::10 7603
94system.physmem.perBankWrBursts::11 7336
95system.physmem.perBankWrBursts::12 8128
96system.physmem.perBankWrBursts::13 8674
97system.physmem.perBankWrBursts::14 7494
98system.physmem.perBankWrBursts::15 7337
99system.physmem.numRdRetry 0
100system.physmem.numWrRetry 63
101system.physmem.totGap 2854927178000
102system.physmem.readPktSize::0 0
103system.physmem.readPktSize::1 0
104system.physmem.readPktSize::2 543
105system.physmem.readPktSize::3 14
106system.physmem.readPktSize::4 0
107system.physmem.readPktSize::5 0
108system.physmem.readPktSize::6 169383
109system.physmem.writePktSize::0 0
110system.physmem.writePktSize::1 0
111system.physmem.writePktSize::2 4381
112system.physmem.writePktSize::3 0
113system.physmem.writePktSize::4 0
114system.physmem.writePktSize::5 0
115system.physmem.writePktSize::6 124328
116system.physmem.rdQLenPdf::0 159867
117system.physmem.rdQLenPdf::1 9622
118system.physmem.rdQLenPdf::2 302
119system.physmem.rdQLenPdf::3 1
120system.physmem.rdQLenPdf::4 1
121system.physmem.rdQLenPdf::5 1
122system.physmem.rdQLenPdf::6 1
123system.physmem.rdQLenPdf::7 1
124system.physmem.rdQLenPdf::8 1
125system.physmem.rdQLenPdf::9 1
126system.physmem.rdQLenPdf::10 1
127system.physmem.rdQLenPdf::11 1
128system.physmem.rdQLenPdf::12 1
129system.physmem.rdQLenPdf::13 1
130system.physmem.rdQLenPdf::14 1
131system.physmem.rdQLenPdf::15 0
132system.physmem.rdQLenPdf::16 0
133system.physmem.rdQLenPdf::17 0
134system.physmem.rdQLenPdf::18 0
135system.physmem.rdQLenPdf::19 0
136system.physmem.rdQLenPdf::20 0
137system.physmem.rdQLenPdf::21 0
138system.physmem.rdQLenPdf::22 0
139system.physmem.rdQLenPdf::23 0
140system.physmem.rdQLenPdf::24 0
141system.physmem.rdQLenPdf::25 0
142system.physmem.rdQLenPdf::26 0
143system.physmem.rdQLenPdf::27 0
144system.physmem.rdQLenPdf::28 0
145system.physmem.rdQLenPdf::29 0
146system.physmem.rdQLenPdf::30 0
147system.physmem.rdQLenPdf::31 0
148system.physmem.wrQLenPdf::0 1
149system.physmem.wrQLenPdf::1 1
150system.physmem.wrQLenPdf::2 1
151system.physmem.wrQLenPdf::3 1
152system.physmem.wrQLenPdf::4 1
153system.physmem.wrQLenPdf::5 1
154system.physmem.wrQLenPdf::6 1
155system.physmem.wrQLenPdf::7 1
156system.physmem.wrQLenPdf::8 1
157system.physmem.wrQLenPdf::9 1
158system.physmem.wrQLenPdf::10 1
159system.physmem.wrQLenPdf::11 1
160system.physmem.wrQLenPdf::12 1
161system.physmem.wrQLenPdf::13 1
162system.physmem.wrQLenPdf::14 1
163system.physmem.wrQLenPdf::15 1807
164system.physmem.wrQLenPdf::16 2634
165system.physmem.wrQLenPdf::17 5993
166system.physmem.wrQLenPdf::18 6240
167system.physmem.wrQLenPdf::19 6528
168system.physmem.wrQLenPdf::20 6224
169system.physmem.wrQLenPdf::21 6599
170system.physmem.wrQLenPdf::22 6844
171system.physmem.wrQLenPdf::23 7638
172system.physmem.wrQLenPdf::24 7446
173system.physmem.wrQLenPdf::25 8542
174system.physmem.wrQLenPdf::26 8952
175system.physmem.wrQLenPdf::27 7381
176system.physmem.wrQLenPdf::28 7006
177system.physmem.wrQLenPdf::29 7076
178system.physmem.wrQLenPdf::30 6795
179system.physmem.wrQLenPdf::31 6597
180system.physmem.wrQLenPdf::32 6634
181system.physmem.wrQLenPdf::33 523
182system.physmem.wrQLenPdf::34 519
183system.physmem.wrQLenPdf::35 465
184system.physmem.wrQLenPdf::36 320
185system.physmem.wrQLenPdf::37 323
186system.physmem.wrQLenPdf::38 337
187system.physmem.wrQLenPdf::39 278
188system.physmem.wrQLenPdf::40 262
189system.physmem.wrQLenPdf::41 254
190system.physmem.wrQLenPdf::42 262
191system.physmem.wrQLenPdf::43 262
192system.physmem.wrQLenPdf::44 318
193system.physmem.wrQLenPdf::45 228
194system.physmem.wrQLenPdf::46 233
195system.physmem.wrQLenPdf::47 215
196system.physmem.wrQLenPdf::48 201
197system.physmem.wrQLenPdf::49 203
198system.physmem.wrQLenPdf::50 208
199system.physmem.wrQLenPdf::51 161
200system.physmem.wrQLenPdf::52 244
201system.physmem.wrQLenPdf::53 193
202system.physmem.wrQLenPdf::54 194
203system.physmem.wrQLenPdf::55 175
204system.physmem.wrQLenPdf::56 236
205system.physmem.wrQLenPdf::57 244
206system.physmem.wrQLenPdf::58 125
207system.physmem.wrQLenPdf::59 254
208system.physmem.wrQLenPdf::60 211
209system.physmem.wrQLenPdf::61 185
210system.physmem.wrQLenPdf::62 90
211system.physmem.wrQLenPdf::63 147
212system.physmem.bytesPerActivate::samples 60375
213system.physmem.bytesPerActivate::mean 312.289259
214system.physmem.bytesPerActivate::gmean 185.250729
215system.physmem.bytesPerActivate::stdev 329.192831
216system.physmem.bytesPerActivate::0-127 21750 36.02% 36.02%
217system.physmem.bytesPerActivate::128-255 14686 24.32% 60.35%
218system.physmem.bytesPerActivate::256-383 6697 11.09% 71.44%
219system.physmem.bytesPerActivate::384-511 3542 5.87% 77.31%
220system.physmem.bytesPerActivate::512-639 2540 4.21% 81.52%
221system.physmem.bytesPerActivate::640-767 1648 2.73% 84.25%
222system.physmem.bytesPerActivate::768-895 1031 1.71% 85.95%
223system.physmem.bytesPerActivate::896-1023 1005 1.66% 87.62%
224system.physmem.bytesPerActivate::1024-1151 7476 12.38% 100.00%
225system.physmem.bytesPerActivate::total 60375
226system.physmem.rdPerTurnAround::samples 6174
227system.physmem.rdPerTurnAround::mean 27.501944
228system.physmem.rdPerTurnAround::stdev 583.476919
229system.physmem.rdPerTurnAround::0-2047 6173 99.98% 99.98%
230system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00%
231system.physmem.rdPerTurnAround::total 6174
232system.physmem.wrPerTurnAround::samples 6174
233system.physmem.wrPerTurnAround::mean 20.213638
234system.physmem.wrPerTurnAround::gmean 18.315719
235system.physmem.wrPerTurnAround::stdev 15.257991
236system.physmem.wrPerTurnAround::16-19 5458 88.40% 88.40%
237system.physmem.wrPerTurnAround::20-23 62 1.00% 89.41%
238system.physmem.wrPerTurnAround::24-27 37 0.60% 90.01%
239system.physmem.wrPerTurnAround::28-31 45 0.73% 90.74%
240system.physmem.wrPerTurnAround::32-35 268 4.34% 95.08%
241system.physmem.wrPerTurnAround::36-39 28 0.45% 95.53%
242system.physmem.wrPerTurnAround::40-43 16 0.26% 95.79%
243system.physmem.wrPerTurnAround::44-47 14 0.23% 96.02%
244system.physmem.wrPerTurnAround::48-51 9 0.15% 96.16%
245system.physmem.wrPerTurnAround::52-55 2 0.03% 96.19%
246system.physmem.wrPerTurnAround::56-59 2 0.03% 96.23%
247system.physmem.wrPerTurnAround::60-63 4 0.06% 96.29%
248system.physmem.wrPerTurnAround::64-67 146 2.36% 98.66%
249system.physmem.wrPerTurnAround::68-71 7 0.11% 98.77%
250system.physmem.wrPerTurnAround::76-79 8 0.13% 98.90%
251system.physmem.wrPerTurnAround::80-83 6 0.10% 99.00%
252system.physmem.wrPerTurnAround::84-87 1 0.02% 99.01%
253system.physmem.wrPerTurnAround::92-95 1 0.02% 99.03%
254system.physmem.wrPerTurnAround::104-107 3 0.05% 99.08%
255system.physmem.wrPerTurnAround::108-111 8 0.13% 99.21%
256system.physmem.wrPerTurnAround::112-115 1 0.02% 99.22%
257system.physmem.wrPerTurnAround::120-123 1 0.02% 99.24%
258system.physmem.wrPerTurnAround::124-127 1 0.02% 99.25%
259system.physmem.wrPerTurnAround::128-131 10 0.16% 99.42%
260system.physmem.wrPerTurnAround::132-135 7 0.11% 99.53%
261system.physmem.wrPerTurnAround::136-139 7 0.11% 99.64%
262system.physmem.wrPerTurnAround::140-143 4 0.06% 99.71%
263system.physmem.wrPerTurnAround::144-147 3 0.05% 99.76%
264system.physmem.wrPerTurnAround::152-155 1 0.02% 99.77%
265system.physmem.wrPerTurnAround::156-159 2 0.03% 99.81%
266system.physmem.wrPerTurnAround::168-171 1 0.02% 99.82%
267system.physmem.wrPerTurnAround::172-175 2 0.03% 99.85%
268system.physmem.wrPerTurnAround::176-179 1 0.02% 99.87%
269system.physmem.wrPerTurnAround::180-183 1 0.02% 99.89%
270system.physmem.wrPerTurnAround::188-191 1 0.02% 99.90%
271system.physmem.wrPerTurnAround::192-195 5 0.08% 99.98%
272system.physmem.wrPerTurnAround::196-199 1 0.02% 100.00%
273system.physmem.wrPerTurnAround::total 6174
274system.physmem.totQLat 4595611500
275system.physmem.totMemAccLat 7779417750
276system.physmem.totBusLat 849015000
277system.physmem.avgQLat 27064.37
278system.physmem.avgBusLat 5000.00
279system.physmem.avgMemAccLat 45814.37
280system.physmem.avgRdBW 3.81
281system.physmem.avgWrBW 2.80
282system.physmem.avgRdBWSys 3.80
283system.physmem.avgWrBWSys 2.79
284system.physmem.peakBW 12800.00
285system.physmem.busUtil 0.05
286system.physmem.busUtilRead 0.03
287system.physmem.busUtilWrite 0.02
288system.physmem.avgRdQLen 1.01
289system.physmem.avgWrQLen 27.80
290system.physmem.readRowHits 140227
291system.physmem.writeRowHits 93999
292system.physmem.readRowHitRate 82.58
293system.physmem.writeRowHitRate 75.31
294system.physmem.avgGap 9559473.42
295system.physmem.pageHitRate 79.50
296system.physmem_0.actEnergy 217969920
297system.physmem_0.preEnergy 115853760
298system.physmem_0.readEnergy 617381520
299system.physmem_0.writeEnergy 324349920
300system.physmem_0.refreshEnergy 6032076960.000001
301system.physmem_0.actBackEnergy 4594766580
302system.physmem_0.preBackEnergy 373267680
303system.physmem_0.actPowerDownEnergy 12534119310
304system.physmem_0.prePowerDownEnergy 8428819680
305system.physmem_0.selfRefreshEnergy 671880069150
306system.physmem_0.totalEnergy 705122067060
307system.physmem_0.averagePower 246.984218
308system.physmem_0.totalIdleTime 2843538521500
309system.physmem_0.memoryStateTime::IDLE 699213750
310system.physmem_0.memoryStateTime::REF 2565056000
311system.physmem_0.memoryStateTime::SREF 2794434653000
312system.physmem_0.memoryStateTime::PRE_PDN 21950094250
313system.physmem_0.memoryStateTime::ACT 7791322250
314system.physmem_0.memoryStateTime::ACT_PDN 27487288250
315system.physmem_1.actEnergy 213114720
316system.physmem_1.preEnergy 113269365
317system.physmem_1.readEnergy 595011900
318system.physmem_1.writeEnergy 327100860
319system.physmem_1.refreshEnergy 6107677680.000001
320system.physmem_1.actBackEnergy 4499395890
321system.physmem_1.preBackEnergy 364524960
322system.physmem_1.actPowerDownEnergy 12239824890
323system.physmem_1.prePowerDownEnergy 8713020000
324system.physmem_1.selfRefreshEnergy 671996557920
325system.physmem_1.totalEnergy 705172962825
326system.physmem_1.averagePower 247.002045
327system.physmem_1.totalIdleTime 2844103397000
328system.physmem_1.memoryStateTime::IDLE 682111750
329system.physmem_1.memoryStateTime::REF 2597942000
330system.physmem_1.memoryStateTime::SREF 2794571640750
331system.physmem_1.memoryStateTime::PRE_PDN 22690140250
332system.physmem_1.memoryStateTime::ACT 7544112250
333system.physmem_1.memoryStateTime::ACT_PDN 26841680500
334system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2854927627500
335system.realview.nvmem.bytes_read::cpu.inst 512
336system.realview.nvmem.bytes_read::total 512
337system.realview.nvmem.bytes_inst_read::cpu.inst 512
338system.realview.nvmem.bytes_inst_read::total 512
339system.realview.nvmem.num_reads::cpu.inst 8
340system.realview.nvmem.num_reads::total 8
341system.realview.nvmem.bw_read::cpu.inst 179
342system.realview.nvmem.bw_read::total 179
343system.realview.nvmem.bw_inst_read::cpu.inst 179
344system.realview.nvmem.bw_inst_read::total 179
345system.realview.nvmem.bw_total::cpu.inst 179
346system.realview.nvmem.bw_total::total 179
347system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2854927627500
348system.pwrStateResidencyTicks::UNDEFINED 2854927627500
349system.bridge.pwrStateResidencyTicks::UNDEFINED 2854927627500
350system.cf0.dma_read_full_pages 0
351system.cf0.dma_read_bytes 1024
352system.cf0.dma_read_txs 1
353system.cf0.dma_write_full_pages 540
354system.cf0.dma_write_bytes 2318336
355system.cf0.dma_write_txs 631
356system.cpu.branchPred.lookups 31061880
357system.cpu.branchPred.condPredicted 16830353
358system.cpu.branchPred.condIncorrect 2474418
359system.cpu.branchPred.BTBLookups 18693305
360system.cpu.branchPred.BTBHits 10411167
361system.cpu.branchPred.BTBCorrect 0
362system.cpu.branchPred.BTBHitPct 55.694630
363system.cpu.branchPred.usedRAS 7903109
364system.cpu.branchPred.RASInCorrect 1504989
365system.cpu.branchPred.indirectLookups 3038231
366system.cpu.branchPred.indirectHits 2848867
367system.cpu.branchPred.indirectMisses 189364
368system.cpu.branchPredindirectMispredicted 109645
369system.cpu_clk_domain.clock 500
370system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854927627500
371system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
372system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
373system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
374system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
375system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
376system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
377system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
378system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
379system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
380system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
381system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
382system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
383system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
384system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
385system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
386system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
387system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
388system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
389system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
390system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
391system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
392system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
393system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
394system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
395system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
396system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
397system.cpu.dstage2_mmu.stage2_tlb.hits 0
398system.cpu.dstage2_mmu.stage2_tlb.misses 0
399system.cpu.dstage2_mmu.stage2_tlb.accesses 0
400system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2854927627500
401system.cpu.dtb.walker.walks 67659
402system.cpu.dtb.walker.walksShort 67659
403system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44567
404system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23092
405system.cpu.dtb.walker.walkWaitTime::samples 67659
406system.cpu.dtb.walker.walkWaitTime::0 67659 100.00% 100.00%
407system.cpu.dtb.walker.walkWaitTime::total 67659
408system.cpu.dtb.walker.walkCompletionTime::samples 7871
409system.cpu.dtb.walker.walkCompletionTime::mean 10125.206454
410system.cpu.dtb.walker.walkCompletionTime::gmean 8429.942657
411system.cpu.dtb.walker.walkCompletionTime::stdev 9907.051248
412system.cpu.dtb.walker.walkCompletionTime::0-65535 7864 99.91% 99.91%
413system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.05% 99.96%
414system.cpu.dtb.walker.walkCompletionTime::196608-262143 2 0.03% 99.99%
415system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00%
416system.cpu.dtb.walker.walkCompletionTime::total 7871
417system.cpu.dtb.walker.walksPending::samples 276581000
418system.cpu.dtb.walker.walksPending::0 276581000 100.00% 100.00%
419system.cpu.dtb.walker.walksPending::total 276581000
420system.cpu.dtb.walker.walkPageSizes::4K 6485 82.39% 82.39%
421system.cpu.dtb.walker.walkPageSizes::1M 1386 17.61% 100.00%
422system.cpu.dtb.walker.walkPageSizes::total 7871
423system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 67659
424system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
425system.cpu.dtb.walker.walkRequestOrigin_Requested::total 67659
426system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7871
427system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
428system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7871
429system.cpu.dtb.walker.walkRequestOrigin::total 75530
430system.cpu.dtb.inst_hits 0
431system.cpu.dtb.inst_misses 0
432system.cpu.dtb.read_hits 24684864
433system.cpu.dtb.read_misses 60689
434system.cpu.dtb.write_hits 19405463
435system.cpu.dtb.write_misses 6970
436system.cpu.dtb.flush_tlb 64
437system.cpu.dtb.flush_tlb_mva 917
438system.cpu.dtb.flush_tlb_mva_asid 0
439system.cpu.dtb.flush_tlb_asid 0
440system.cpu.dtb.flush_entries 4278
441system.cpu.dtb.align_faults 1498
442system.cpu.dtb.prefetch_faults 1782
443system.cpu.dtb.domain_faults 0
444system.cpu.dtb.perms_faults 765
445system.cpu.dtb.read_accesses 24745553
446system.cpu.dtb.write_accesses 19412433
447system.cpu.dtb.inst_accesses 0
448system.cpu.dtb.hits 44090327
449system.cpu.dtb.misses 67659
450system.cpu.dtb.accesses 44157986
451system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854927627500
452system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
453system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
454system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
455system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
456system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
457system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
458system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
459system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
460system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
461system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
462system.cpu.istage2_mmu.stage2_tlb.read_hits 0
463system.cpu.istage2_mmu.stage2_tlb.read_misses 0
464system.cpu.istage2_mmu.stage2_tlb.write_hits 0
465system.cpu.istage2_mmu.stage2_tlb.write_misses 0
466system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
467system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
468system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
469system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
470system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
471system.cpu.istage2_mmu.stage2_tlb.align_faults 0
472system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
473system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
474system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
475system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
476system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
477system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
478system.cpu.istage2_mmu.stage2_tlb.hits 0
479system.cpu.istage2_mmu.stage2_tlb.misses 0
480system.cpu.istage2_mmu.stage2_tlb.accesses 0
481system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2854927627500
482system.cpu.itb.walker.walks 5834
483system.cpu.itb.walker.walksShort 5834
484system.cpu.itb.walker.walksShortTerminationLevel::Level1 322
485system.cpu.itb.walker.walksShortTerminationLevel::Level2 5512
486system.cpu.itb.walker.walkWaitTime::samples 5834
487system.cpu.itb.walker.walkWaitTime::0 5834 100.00% 100.00%
488system.cpu.itb.walker.walkWaitTime::total 5834
489system.cpu.itb.walker.walkCompletionTime::samples 3212
490system.cpu.itb.walker.walkCompletionTime::mean 10503.424658
491system.cpu.itb.walker.walkCompletionTime::gmean 8675.185995
492system.cpu.itb.walker.walkCompletionTime::stdev 6953.542108
493system.cpu.itb.walker.walkCompletionTime::0-8191 1846 57.47% 57.47%
494system.cpu.itb.walker.walkCompletionTime::8192-16383 802 24.97% 82.44%
495system.cpu.itb.walker.walkCompletionTime::16384-24575 556 17.31% 99.75%
496system.cpu.itb.walker.walkCompletionTime::24576-32767 7 0.22% 99.97%
497system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00%
498system.cpu.itb.walker.walkCompletionTime::total 3212
499system.cpu.itb.walker.walksPending::samples 276141500
500system.cpu.itb.walker.walksPending::0 276141500 100.00% 100.00%
501system.cpu.itb.walker.walksPending::total 276141500
502system.cpu.itb.walker.walkPageSizes::4K 2902 90.35% 90.35%
503system.cpu.itb.walker.walkPageSizes::1M 310 9.65% 100.00%
504system.cpu.itb.walker.walkPageSizes::total 3212
505system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
506system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5834
507system.cpu.itb.walker.walkRequestOrigin_Requested::total 5834
508system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
509system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3212
510system.cpu.itb.walker.walkRequestOrigin_Completed::total 3212
511system.cpu.itb.walker.walkRequestOrigin::total 9046
512system.cpu.itb.inst_hits 57493677
513system.cpu.itb.inst_misses 5834
514system.cpu.itb.read_hits 0
515system.cpu.itb.read_misses 0
516system.cpu.itb.write_hits 0
517system.cpu.itb.write_misses 0
518system.cpu.itb.flush_tlb 64
519system.cpu.itb.flush_tlb_mva 917
520system.cpu.itb.flush_tlb_mva_asid 0
521system.cpu.itb.flush_tlb_asid 0
522system.cpu.itb.flush_entries 2927
523system.cpu.itb.align_faults 0
524system.cpu.itb.prefetch_faults 0
525system.cpu.itb.domain_faults 0
526system.cpu.itb.perms_faults 8355
527system.cpu.itb.read_accesses 0
528system.cpu.itb.write_accesses 0
529system.cpu.itb.inst_accesses 57499511
530system.cpu.itb.hits 57493677
531system.cpu.itb.misses 5834
532system.cpu.itb.accesses 57499511
533system.cpu.numPwrStateTransitions 6066
534system.cpu.pwrStateClkGateDist::samples 3033
535system.cpu.pwrStateClkGateDist::mean 887944417.634355
536system.cpu.pwrStateClkGateDist::stdev 17437789844.803165
537system.cpu.pwrStateClkGateDist::underflows 2969 97.89% 97.89%
538system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80%
539system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84%
540system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87%
541system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90%
542system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00%
543system.cpu.pwrStateClkGateDist::min_value 501
544system.cpu.pwrStateClkGateDist::max_value 499967984888
545system.cpu.pwrStateClkGateDist::total 3033
546system.cpu.pwrStateResidencyTicks::ON 161792208815
547system.cpu.pwrStateResidencyTicks::CLK_GATED 2693135418685
548system.cpu.numCycles 323587374
549system.cpu.numWorkItemsStarted 0
550system.cpu.numWorkItemsCompleted 0
551system.cpu.committedInsts 111771703
552system.cpu.committedOps 135139786
553system.cpu.discardedOps 7780501
554system.cpu.numFetchSuspends 3033
555system.cpu.quiesceCycles 5386332607
556system.cpu.cpi 2.895074
557system.cpu.ipc 0.345414
558system.cpu.op_class_0::No_OpClass 2337 0.00% 0.00%
559system.cpu.op_class_0::IntAlu 90588447 67.03% 67.03%
560system.cpu.op_class_0::IntMult 113124 0.08% 67.12%
561system.cpu.op_class_0::IntDiv 0 0.00% 67.12%
562system.cpu.op_class_0::FloatAdd 0 0.00% 67.12%
563system.cpu.op_class_0::FloatCmp 0 0.00% 67.12%
564system.cpu.op_class_0::FloatCvt 0 0.00% 67.12%
565system.cpu.op_class_0::FloatMult 0 0.00% 67.12%
566system.cpu.op_class_0::FloatMultAcc 0 0.00% 67.12%
567system.cpu.op_class_0::FloatDiv 0 0.00% 67.12%
568system.cpu.op_class_0::FloatMisc 0 0.00% 67.12%
569system.cpu.op_class_0::FloatSqrt 0 0.00% 67.12%
570system.cpu.op_class_0::SimdAdd 0 0.00% 67.12%
571system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.12%
572system.cpu.op_class_0::SimdAlu 0 0.00% 67.12%
573system.cpu.op_class_0::SimdCmp 0 0.00% 67.12%
574system.cpu.op_class_0::SimdCvt 0 0.00% 67.12%
575system.cpu.op_class_0::SimdMisc 0 0.00% 67.12%
576system.cpu.op_class_0::SimdMult 0 0.00% 67.12%
577system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.12%
578system.cpu.op_class_0::SimdShift 0 0.00% 67.12%
579system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.12%
580system.cpu.op_class_0::SimdSqrt 0 0.00% 67.12%
581system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.12%
582system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.12%
583system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.12%
584system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.12%
585system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.12%
586system.cpu.op_class_0::SimdFloatMisc 8479 0.01% 67.12%
587system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.12%
588system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.12%
589system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.12%
590system.cpu.op_class_0::MemRead 24191569 17.90% 85.03%
591system.cpu.op_class_0::MemWrite 20224534 14.97% 99.99%
592system.cpu.op_class_0::FloatMemRead 2708 0.00% 99.99%
593system.cpu.op_class_0::FloatMemWrite 8588 0.01% 100.00%
594system.cpu.op_class_0::IprAccess 0 0.00% 100.00%
595system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00%
596system.cpu.op_class_0::total 135139786
597system.cpu.kern.inst.arm 0
598system.cpu.kern.inst.quiesce 3033
599system.cpu.tickCycles 217929622
600system.cpu.idleCycles 105657752
601system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2854927627500
602system.cpu.dcache.tags.replacements 844447
603system.cpu.dcache.tags.tagsinuse 511.945153
604system.cpu.dcache.tags.total_refs 42548483
605system.cpu.dcache.tags.sampled_refs 844959
606system.cpu.dcache.tags.avg_refs 50.355678
607system.cpu.dcache.tags.warmup_cycle 330588500
608system.cpu.dcache.tags.occ_blocks::cpu.data 511.945153
609system.cpu.dcache.tags.occ_percent::cpu.data 0.999893
610system.cpu.dcache.tags.occ_percent::total 0.999893
611system.cpu.dcache.tags.occ_task_id_blocks::1024 512
612system.cpu.dcache.tags.age_task_id_blocks_1024::0 94
613system.cpu.dcache.tags.age_task_id_blocks_1024::1 360
614system.cpu.dcache.tags.age_task_id_blocks_1024::2 58
615system.cpu.dcache.tags.occ_task_id_percent::1024 1
616system.cpu.dcache.tags.tag_accesses 175848001
617system.cpu.dcache.tags.data_accesses 175848001
618system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2854927627500
619system.cpu.dcache.ReadReq_hits::cpu.data 23041668
620system.cpu.dcache.ReadReq_hits::total 23041668
621system.cpu.dcache.WriteReq_hits::cpu.data 18243760
622system.cpu.dcache.WriteReq_hits::total 18243760
623system.cpu.dcache.SoftPFReq_hits::cpu.data 357146
624system.cpu.dcache.SoftPFReq_hits::total 357146
625system.cpu.dcache.LoadLockedReq_hits::cpu.data 443213
626system.cpu.dcache.LoadLockedReq_hits::total 443213
627system.cpu.dcache.StoreCondReq_hits::cpu.data 459828
628system.cpu.dcache.StoreCondReq_hits::total 459828
629system.cpu.dcache.demand_hits::cpu.data 41285428
630system.cpu.dcache.demand_hits::total 41285428
631system.cpu.dcache.overall_hits::cpu.data 41642574
632system.cpu.dcache.overall_hits::total 41642574
633system.cpu.dcache.ReadReq_misses::cpu.data 464854
634system.cpu.dcache.ReadReq_misses::total 464854
635system.cpu.dcache.WriteReq_misses::cpu.data 548525
636system.cpu.dcache.WriteReq_misses::total 548525
637system.cpu.dcache.SoftPFReq_misses::cpu.data 169352
638system.cpu.dcache.SoftPFReq_misses::total 169352
639system.cpu.dcache.LoadLockedReq_misses::cpu.data 22406
640system.cpu.dcache.LoadLockedReq_misses::total 22406
641system.cpu.dcache.StoreCondReq_misses::cpu.data 2
642system.cpu.dcache.StoreCondReq_misses::total 2
643system.cpu.dcache.demand_misses::cpu.data 1013379
644system.cpu.dcache.demand_misses::total 1013379
645system.cpu.dcache.overall_misses::cpu.data 1182731
646system.cpu.dcache.overall_misses::total 1182731
647system.cpu.dcache.ReadReq_miss_latency::cpu.data 7330473500
648system.cpu.dcache.ReadReq_miss_latency::total 7330473500
649system.cpu.dcache.WriteReq_miss_latency::cpu.data 26773562480
650system.cpu.dcache.WriteReq_miss_latency::total 26773562480
651system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304848500
652system.cpu.dcache.LoadLockedReq_miss_latency::total 304848500
653system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 171000
654system.cpu.dcache.StoreCondReq_miss_latency::total 171000
655system.cpu.dcache.demand_miss_latency::cpu.data 34104035980
656system.cpu.dcache.demand_miss_latency::total 34104035980
657system.cpu.dcache.overall_miss_latency::cpu.data 34104035980
658system.cpu.dcache.overall_miss_latency::total 34104035980
659system.cpu.dcache.ReadReq_accesses::cpu.data 23506522
660system.cpu.dcache.ReadReq_accesses::total 23506522
661system.cpu.dcache.WriteReq_accesses::cpu.data 18792285
662system.cpu.dcache.WriteReq_accesses::total 18792285
663system.cpu.dcache.SoftPFReq_accesses::cpu.data 526498
664system.cpu.dcache.SoftPFReq_accesses::total 526498
665system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465619
666system.cpu.dcache.LoadLockedReq_accesses::total 465619
667system.cpu.dcache.StoreCondReq_accesses::cpu.data 459830
668system.cpu.dcache.StoreCondReq_accesses::total 459830
669system.cpu.dcache.demand_accesses::cpu.data 42298807
670system.cpu.dcache.demand_accesses::total 42298807
671system.cpu.dcache.overall_accesses::cpu.data 42825305
672system.cpu.dcache.overall_accesses::total 42825305
673system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019776
674system.cpu.dcache.ReadReq_miss_rate::total 0.019776
675system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029189
676system.cpu.dcache.WriteReq_miss_rate::total 0.029189
677system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.321657
678system.cpu.dcache.SoftPFReq_miss_rate::total 0.321657
679system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048121
680system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048121
681system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004
682system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004
683system.cpu.dcache.demand_miss_rate::cpu.data 0.023958
684system.cpu.dcache.demand_miss_rate::total 0.023958
685system.cpu.dcache.overall_miss_rate::cpu.data 0.027618
686system.cpu.dcache.overall_miss_rate::total 0.027618
687system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15769.410396
688system.cpu.dcache.ReadReq_avg_miss_latency::total 15769.410396
689system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48810.104334
690system.cpu.dcache.WriteReq_avg_miss_latency::total 48810.104334
691system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13605.663662
692system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13605.663662
693system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 85500
694system.cpu.dcache.StoreCondReq_avg_miss_latency::total 85500
695system.cpu.dcache.demand_avg_miss_latency::cpu.data 33653.782030
696system.cpu.dcache.demand_avg_miss_latency::total 33653.782030
697system.cpu.dcache.overall_avg_miss_latency::cpu.data 28834.989512
698system.cpu.dcache.overall_avg_miss_latency::total 28834.989512
699system.cpu.dcache.blocked_cycles::no_mshrs 210
700system.cpu.dcache.blocked_cycles::no_targets 0
701system.cpu.dcache.blocked::no_mshrs 21
702system.cpu.dcache.blocked::no_targets 0
703system.cpu.dcache.avg_blocked_cycles::no_mshrs 10
704system.cpu.dcache.avg_blocked_cycles::no_targets nan
705system.cpu.dcache.writebacks::writebacks 701832
706system.cpu.dcache.writebacks::total 701832
707system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45599
708system.cpu.dcache.ReadReq_mshr_hits::total 45599
709system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249413
710system.cpu.dcache.WriteReq_mshr_hits::total 249413
711system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14207
712system.cpu.dcache.LoadLockedReq_mshr_hits::total 14207
713system.cpu.dcache.demand_mshr_hits::cpu.data 295012
714system.cpu.dcache.demand_mshr_hits::total 295012
715system.cpu.dcache.overall_mshr_hits::cpu.data 295012
716system.cpu.dcache.overall_mshr_hits::total 295012
717system.cpu.dcache.ReadReq_mshr_misses::cpu.data 419255
718system.cpu.dcache.ReadReq_mshr_misses::total 419255
719system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299112
720system.cpu.dcache.WriteReq_mshr_misses::total 299112
721system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121209
722system.cpu.dcache.SoftPFReq_mshr_misses::total 121209
723system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8199
724system.cpu.dcache.LoadLockedReq_mshr_misses::total 8199
725system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2
726system.cpu.dcache.StoreCondReq_mshr_misses::total 2
727system.cpu.dcache.demand_mshr_misses::cpu.data 718367
728system.cpu.dcache.demand_mshr_misses::total 718367
729system.cpu.dcache.overall_mshr_misses::cpu.data 839576
730system.cpu.dcache.overall_mshr_misses::total 839576
731system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31110
732system.cpu.dcache.ReadReq_mshr_uncacheable::total 31110
733system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27574
734system.cpu.dcache.WriteReq_mshr_uncacheable::total 27574
735system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58684
736system.cpu.dcache.overall_mshr_uncacheable_misses::total 58684
737system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6445053500
738system.cpu.dcache.ReadReq_mshr_miss_latency::total 6445053500
739system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14252180000
740system.cpu.dcache.WriteReq_mshr_miss_latency::total 14252180000
741system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1665054500
742system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1665054500
743system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 118677000
744system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 118677000
745system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169000
746system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169000
747system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20697233500
748system.cpu.dcache.demand_mshr_miss_latency::total 20697233500
749system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22362288000
750system.cpu.dcache.overall_mshr_miss_latency::total 22362288000
751system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6302505000
752system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6302505000
753system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6302505000
754system.cpu.dcache.overall_mshr_uncacheable_latency::total 6302505000
755system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017836
756system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017836
757system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015917
758system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015917
759system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230217
760system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230217
761system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017609
762system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017609
763system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004
764system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004
765system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016983
766system.cpu.dcache.demand_mshr_miss_rate::total 0.016983
767system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019605
768system.cpu.dcache.overall_mshr_miss_rate::total 0.019605
769system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15372.633600
770system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15372.633600
771system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47648.305651
772system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47648.305651
773system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13737.053354
774system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13737.053354
775system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14474.570070
776system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14474.570070
777system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 84500
778system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 84500
779system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28811.503730
780system.cpu.dcache.demand_avg_mshr_miss_latency::total 28811.503730
781system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26635.215871
782system.cpu.dcache.overall_avg_mshr_miss_latency::total 26635.215871
783system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202587.753134
784system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202587.753134
785system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107397.331470
786system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107397.331470
787system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2854927627500
788system.cpu.icache.tags.replacements 2889221
789system.cpu.icache.tags.tagsinuse 511.371129
790system.cpu.icache.tags.total_refs 54595271
791system.cpu.icache.tags.sampled_refs 2889733
792system.cpu.icache.tags.avg_refs 18.892843
793system.cpu.icache.tags.warmup_cycle 16096310500
794system.cpu.icache.tags.occ_blocks::cpu.inst 511.371129
795system.cpu.icache.tags.occ_percent::cpu.inst 0.998772
796system.cpu.icache.tags.occ_percent::total 0.998772
797system.cpu.icache.tags.occ_task_id_blocks::1024 512
798system.cpu.icache.tags.age_task_id_blocks_1024::0 101
799system.cpu.icache.tags.age_task_id_blocks_1024::1 214
800system.cpu.icache.tags.age_task_id_blocks_1024::2 197
801system.cpu.icache.tags.occ_task_id_percent::1024 1
802system.cpu.icache.tags.tag_accesses 60374760
803system.cpu.icache.tags.data_accesses 60374760
804system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2854927627500
805system.cpu.icache.ReadReq_hits::cpu.inst 54595271
806system.cpu.icache.ReadReq_hits::total 54595271
807system.cpu.icache.demand_hits::cpu.inst 54595271
808system.cpu.icache.demand_hits::total 54595271
809system.cpu.icache.overall_hits::cpu.inst 54595271
810system.cpu.icache.overall_hits::total 54595271
811system.cpu.icache.ReadReq_misses::cpu.inst 2889745
812system.cpu.icache.ReadReq_misses::total 2889745
813system.cpu.icache.demand_misses::cpu.inst 2889745
814system.cpu.icache.demand_misses::total 2889745
815system.cpu.icache.overall_misses::cpu.inst 2889745
816system.cpu.icache.overall_misses::total 2889745
817system.cpu.icache.ReadReq_miss_latency::cpu.inst 39793127500
818system.cpu.icache.ReadReq_miss_latency::total 39793127500
819system.cpu.icache.demand_miss_latency::cpu.inst 39793127500
820system.cpu.icache.demand_miss_latency::total 39793127500
821system.cpu.icache.overall_miss_latency::cpu.inst 39793127500
822system.cpu.icache.overall_miss_latency::total 39793127500
823system.cpu.icache.ReadReq_accesses::cpu.inst 57485016
824system.cpu.icache.ReadReq_accesses::total 57485016
825system.cpu.icache.demand_accesses::cpu.inst 57485016
826system.cpu.icache.demand_accesses::total 57485016
827system.cpu.icache.overall_accesses::cpu.inst 57485016
828system.cpu.icache.overall_accesses::total 57485016
829system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050270
830system.cpu.icache.ReadReq_miss_rate::total 0.050270
831system.cpu.icache.demand_miss_rate::cpu.inst 0.050270
832system.cpu.icache.demand_miss_rate::total 0.050270
833system.cpu.icache.overall_miss_rate::cpu.inst 0.050270
834system.cpu.icache.overall_miss_rate::total 0.050270
835system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13770.463311
836system.cpu.icache.ReadReq_avg_miss_latency::total 13770.463311
837system.cpu.icache.demand_avg_miss_latency::cpu.inst 13770.463311
838system.cpu.icache.demand_avg_miss_latency::total 13770.463311
839system.cpu.icache.overall_avg_miss_latency::cpu.inst 13770.463311
840system.cpu.icache.overall_avg_miss_latency::total 13770.463311
841system.cpu.icache.blocked_cycles::no_mshrs 0
842system.cpu.icache.blocked_cycles::no_targets 0
843system.cpu.icache.blocked::no_mshrs 0
844system.cpu.icache.blocked::no_targets 0
845system.cpu.icache.avg_blocked_cycles::no_mshrs nan
846system.cpu.icache.avg_blocked_cycles::no_targets nan
847system.cpu.icache.writebacks::writebacks 2889221
848system.cpu.icache.writebacks::total 2889221
849system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2889745
850system.cpu.icache.ReadReq_mshr_misses::total 2889745
851system.cpu.icache.demand_mshr_misses::cpu.inst 2889745
852system.cpu.icache.demand_mshr_misses::total 2889745
853system.cpu.icache.overall_mshr_misses::cpu.inst 2889745
854system.cpu.icache.overall_mshr_misses::total 2889745
855system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3119
856system.cpu.icache.ReadReq_mshr_uncacheable::total 3119
857system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3119
858system.cpu.icache.overall_mshr_uncacheable_misses::total 3119
859system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36903383500
860system.cpu.icache.ReadReq_mshr_miss_latency::total 36903383500
861system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36903383500
862system.cpu.icache.demand_mshr_miss_latency::total 36903383500
863system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36903383500
864system.cpu.icache.overall_mshr_miss_latency::total 36903383500
865system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 265216500
866system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 265216500
867system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 265216500
868system.cpu.icache.overall_mshr_uncacheable_latency::total 265216500
869system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050270
870system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050270
871system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050270
872system.cpu.icache.demand_mshr_miss_rate::total 0.050270
873system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050270
874system.cpu.icache.overall_mshr_miss_rate::total 0.050270
875system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12770.463657
876system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12770.463657
877system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12770.463657
878system.cpu.icache.demand_avg_mshr_miss_latency::total 12770.463657
879system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12770.463657
880system.cpu.icache.overall_avg_mshr_miss_latency::total 12770.463657
881system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 85032.542482
882system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 85032.542482
883system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 85032.542482
884system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 85032.542482
885system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2854927627500
886system.cpu.l2cache.tags.replacements 96735
887system.cpu.l2cache.tags.tagsinuse 65145.168684
888system.cpu.l2cache.tags.total_refs 7316055
889system.cpu.l2cache.tags.sampled_refs 162131
890system.cpu.l2cache.tags.avg_refs 45.124344
891system.cpu.l2cache.tags.warmup_cycle 100163301000
892system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 70.099174
893system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.032946
894system.cpu.l2cache.tags.occ_blocks::cpu.inst 12110.066628
895system.cpu.l2cache.tags.occ_blocks::cpu.data 52964.969936
896system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001070
897system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001
898system.cpu.l2cache.tags.occ_percent::cpu.inst 0.184785
899system.cpu.l2cache.tags.occ_percent::cpu.data 0.808181
900system.cpu.l2cache.tags.occ_percent::total 0.994036
901system.cpu.l2cache.tags.occ_task_id_blocks::1023 46
902system.cpu.l2cache.tags.occ_task_id_blocks::1024 65350
903system.cpu.l2cache.tags.age_task_id_blocks_1023::4 46
904system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1
905system.cpu.l2cache.tags.age_task_id_blocks_1024::2 89
906system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4574
907system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60686
908system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000702
909system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997162
910system.cpu.l2cache.tags.tag_accesses 60043597
911system.cpu.l2cache.tags.data_accesses 60043597
912system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2854927627500
913system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 67906
914system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3398
915system.cpu.l2cache.ReadReq_hits::total 71304
916system.cpu.l2cache.WritebackDirty_hits::writebacks 701832
917system.cpu.l2cache.WritebackDirty_hits::total 701832
918system.cpu.l2cache.WritebackClean_hits::writebacks 2838620
919system.cpu.l2cache.WritebackClean_hits::total 2838620
920system.cpu.l2cache.UpgradeReq_hits::cpu.data 2784
921system.cpu.l2cache.UpgradeReq_hits::total 2784
922system.cpu.l2cache.ReadExReq_hits::cpu.data 167004
923system.cpu.l2cache.ReadExReq_hits::total 167004
924system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2866770
925system.cpu.l2cache.ReadCleanReq_hits::total 2866770
926system.cpu.l2cache.ReadSharedReq_hits::cpu.data 534209
927system.cpu.l2cache.ReadSharedReq_hits::total 534209
928system.cpu.l2cache.demand_hits::cpu.dtb.walker 67906
929system.cpu.l2cache.demand_hits::cpu.itb.walker 3398
930system.cpu.l2cache.demand_hits::cpu.inst 2866770
931system.cpu.l2cache.demand_hits::cpu.data 701213
932system.cpu.l2cache.demand_hits::total 3639287
933system.cpu.l2cache.overall_hits::cpu.dtb.walker 67906
934system.cpu.l2cache.overall_hits::cpu.itb.walker 3398
935system.cpu.l2cache.overall_hits::cpu.inst 2866770
936system.cpu.l2cache.overall_hits::cpu.data 701213
937system.cpu.l2cache.overall_hits::total 3639287
938system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 109
939system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2
940system.cpu.l2cache.ReadReq_misses::total 111
941system.cpu.l2cache.UpgradeReq_misses::cpu.data 6
942system.cpu.l2cache.UpgradeReq_misses::total 6
943system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2
944system.cpu.l2cache.SCUpgradeReq_misses::total 2
945system.cpu.l2cache.ReadExReq_misses::cpu.data 129322
946system.cpu.l2cache.ReadExReq_misses::total 129322
947system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22936
948system.cpu.l2cache.ReadCleanReq_misses::total 22936
949system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14450
950system.cpu.l2cache.ReadSharedReq_misses::total 14450
951system.cpu.l2cache.demand_misses::cpu.dtb.walker 109
952system.cpu.l2cache.demand_misses::cpu.itb.walker 2
953system.cpu.l2cache.demand_misses::cpu.inst 22936
954system.cpu.l2cache.demand_misses::cpu.data 143772
955system.cpu.l2cache.demand_misses::total 166819
956system.cpu.l2cache.overall_misses::cpu.dtb.walker 109
957system.cpu.l2cache.overall_misses::cpu.itb.walker 2
958system.cpu.l2cache.overall_misses::cpu.inst 22936
959system.cpu.l2cache.overall_misses::cpu.data 143772
960system.cpu.l2cache.overall_misses::total 166819
961system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 35817000
962system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 193000
963system.cpu.l2cache.ReadReq_miss_latency::total 36010000
964system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 174000
965system.cpu.l2cache.UpgradeReq_miss_latency::total 174000
966system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 166000
967system.cpu.l2cache.SCUpgradeReq_miss_latency::total 166000
968system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12012379500
969system.cpu.l2cache.ReadExReq_miss_latency::total 12012379500
970system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2400764000
971system.cpu.l2cache.ReadCleanReq_miss_latency::total 2400764000
972system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1756081500
973system.cpu.l2cache.ReadSharedReq_miss_latency::total 1756081500
974system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 35817000
975system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 193000
976system.cpu.l2cache.demand_miss_latency::cpu.inst 2400764000
977system.cpu.l2cache.demand_miss_latency::cpu.data 13768461000
978system.cpu.l2cache.demand_miss_latency::total 16205235000
979system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 35817000
980system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 193000
981system.cpu.l2cache.overall_miss_latency::cpu.inst 2400764000
982system.cpu.l2cache.overall_miss_latency::cpu.data 13768461000
983system.cpu.l2cache.overall_miss_latency::total 16205235000
984system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68015
985system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3400
986system.cpu.l2cache.ReadReq_accesses::total 71415
987system.cpu.l2cache.WritebackDirty_accesses::writebacks 701832
988system.cpu.l2cache.WritebackDirty_accesses::total 701832
989system.cpu.l2cache.WritebackClean_accesses::writebacks 2838620
990system.cpu.l2cache.WritebackClean_accesses::total 2838620
991system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2790
992system.cpu.l2cache.UpgradeReq_accesses::total 2790
993system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2
994system.cpu.l2cache.SCUpgradeReq_accesses::total 2
995system.cpu.l2cache.ReadExReq_accesses::cpu.data 296326
996system.cpu.l2cache.ReadExReq_accesses::total 296326
997system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2889706
998system.cpu.l2cache.ReadCleanReq_accesses::total 2889706
999system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 548659
1000system.cpu.l2cache.ReadSharedReq_accesses::total 548659
1001system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68015
1002system.cpu.l2cache.demand_accesses::cpu.itb.walker 3400
1003system.cpu.l2cache.demand_accesses::cpu.inst 2889706
1004system.cpu.l2cache.demand_accesses::cpu.data 844985
1005system.cpu.l2cache.demand_accesses::total 3806106
1006system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68015
1007system.cpu.l2cache.overall_accesses::cpu.itb.walker 3400
1008system.cpu.l2cache.overall_accesses::cpu.inst 2889706
1009system.cpu.l2cache.overall_accesses::cpu.data 844985
1010system.cpu.l2cache.overall_accesses::total 3806106
1011system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001603
1012system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000588
1013system.cpu.l2cache.ReadReq_miss_rate::total 0.001554
1014system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.002151
1015system.cpu.l2cache.UpgradeReq_miss_rate::total 0.002151
1016system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1
1017system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1
1018system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436418
1019system.cpu.l2cache.ReadExReq_miss_rate::total 0.436418
1020system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007937
1021system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007937
1022system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026337
1023system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026337
1024system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001603
1025system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000588
1026system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007937
1027system.cpu.l2cache.demand_miss_rate::cpu.data 0.170147
1028system.cpu.l2cache.demand_miss_rate::total 0.043829
1029system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001603
1030system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000588
1031system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007937
1032system.cpu.l2cache.overall_miss_rate::cpu.data 0.170147
1033system.cpu.l2cache.overall_miss_rate::total 0.043829
1034system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 328596.330275
1035system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 96500
1036system.cpu.l2cache.ReadReq_avg_miss_latency::total 324414.414414
1037system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29000
1038system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29000
1039system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 83000
1040system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 83000
1041system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92887.362552
1042system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92887.362552
1043system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 104672.305546
1044system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 104672.305546
1045system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 121528.131488
1046system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 121528.131488
1047system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 328596.330275
1048system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 96500
1049system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 104672.305546
1050system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95765.941908
1051system.cpu.l2cache.demand_avg_miss_latency::total 97142.621644
1052system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 328596.330275
1053system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 96500
1054system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 104672.305546
1055system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95765.941908
1056system.cpu.l2cache.overall_avg_miss_latency::total 97142.621644
1057system.cpu.l2cache.blocked_cycles::no_mshrs 0
1058system.cpu.l2cache.blocked_cycles::no_targets 0
1059system.cpu.l2cache.blocked::no_mshrs 0
1060system.cpu.l2cache.blocked::no_targets 0
1061system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
1062system.cpu.l2cache.avg_blocked_cycles::no_targets nan
1063system.cpu.l2cache.writebacks::writebacks 88138
1064system.cpu.l2cache.writebacks::total 88138
1065system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 15
1066system.cpu.l2cache.ReadCleanReq_mshr_hits::total 15
1067system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 141
1068system.cpu.l2cache.ReadSharedReq_mshr_hits::total 141
1069system.cpu.l2cache.demand_mshr_hits::cpu.inst 15
1070system.cpu.l2cache.demand_mshr_hits::cpu.data 141
1071system.cpu.l2cache.demand_mshr_hits::total 156
1072system.cpu.l2cache.overall_mshr_hits::cpu.inst 15
1073system.cpu.l2cache.overall_mshr_hits::cpu.data 141
1074system.cpu.l2cache.overall_mshr_hits::total 156
1075system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 109
1076system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2
1077system.cpu.l2cache.ReadReq_mshr_misses::total 111
1078system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6
1079system.cpu.l2cache.UpgradeReq_mshr_misses::total 6
1080system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2
1081system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2
1082system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 129322
1083system.cpu.l2cache.ReadExReq_mshr_misses::total 129322
1084system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22921
1085system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22921
1086system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14309
1087system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14309
1088system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 109
1089system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2
1090system.cpu.l2cache.demand_mshr_misses::cpu.inst 22921
1091system.cpu.l2cache.demand_mshr_misses::cpu.data 143631
1092system.cpu.l2cache.demand_mshr_misses::total 166663
1093system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 109
1094system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2
1095system.cpu.l2cache.overall_mshr_misses::cpu.inst 22921
1096system.cpu.l2cache.overall_mshr_misses::cpu.data 143631
1097system.cpu.l2cache.overall_mshr_misses::total 166663
1098system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3119
1099system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31110
1100system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34229
1101system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27574
1102system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27574
1103system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3119
1104system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58684
1105system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61803
1106system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 34727000
1107system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 173000
1108system.cpu.l2cache.ReadReq_mshr_miss_latency::total 34900000
1109system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 114000
1110system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 114000
1111system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 146000
1112system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 146000
1113system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10719159500
1114system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10719159500
1115system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2169633500
1116system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2169633500
1117system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1600506000
1118system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1600506000
1119system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 34727000
1120system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 173000
1121system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2169633500
1122system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12319665500
1123system.cpu.l2cache.demand_mshr_miss_latency::total 14524199000
1124system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 34727000
1125system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 173000
1126system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2169633500
1127system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12319665500
1128system.cpu.l2cache.overall_mshr_miss_latency::total 14524199000
1129system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 216819500
1130system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5913550000
1131system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6130369500
1132system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 216819500
1133system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5913550000
1134system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6130369500
1135system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001603
1136system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000588
1137system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001554
1138system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.002151
1139system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.002151
1140system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1
1141system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1
1142system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436418
1143system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436418
1144system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007932
1145system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007932
1146system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026080
1147system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026080
1148system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001603
1149system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000588
1150system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007932
1151system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.169981
1152system.cpu.l2cache.demand_mshr_miss_rate::total 0.043788
1153system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001603
1154system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000588
1155system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007932
1156system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.169981
1157system.cpu.l2cache.overall_mshr_miss_rate::total 0.043788
1158system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 318596.330275
1159system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 86500
1160system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 314414.414414
1161system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19000
1162system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19000
1163system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 73000
1164system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 73000
1165system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82887.362552
1166system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82887.362552
1167system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 94657.017582
1168system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 94657.017582
1169system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 111853.099448
1170system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 111853.099448
1171system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 318596.330275
1172system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 86500
1173system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 94657.017582
1174system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85773.026018
1175system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87147.111236
1176system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 318596.330275
1177system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 86500
1178system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 94657.017582
1179system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85773.026018
1180system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87147.111236
1181system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69515.710164
1182system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190085.181614
1183system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 179098.702854
1184system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69515.710164
1185system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100769.374957
1186system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 99192.102325
1187system.cpu.toL2Bus.snoop_filter.tot_requests 7501872
1188system.cpu.toL2Bus.snoop_filter.hit_single_requests 3767165
1189system.cpu.toL2Bus.snoop_filter.hit_multi_requests 57954
1190system.cpu.toL2Bus.snoop_filter.tot_snoops 184
1191system.cpu.toL2Bus.snoop_filter.hit_single_snoops 184
1192system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
1193system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2854927627500
1194system.cpu.toL2Bus.trans_dist::ReadReq 136326
1195system.cpu.toL2Bus.trans_dist::ReadResp 3574876
1196system.cpu.toL2Bus.trans_dist::WriteReq 27574
1197system.cpu.toL2Bus.trans_dist::WriteResp 27574
1198system.cpu.toL2Bus.trans_dist::WritebackDirty 789970
1199system.cpu.toL2Bus.trans_dist::WritebackClean 2889221
1200system.cpu.toL2Bus.trans_dist::CleanEvict 151212
1201system.cpu.toL2Bus.trans_dist::UpgradeReq 2790
1202system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2
1203system.cpu.toL2Bus.trans_dist::UpgradeResp 2792
1204system.cpu.toL2Bus.trans_dist::ReadExReq 296326
1205system.cpu.toL2Bus.trans_dist::ReadExResp 296326
1206system.cpu.toL2Bus.trans_dist::ReadCleanReq 2889745
1207system.cpu.toL2Bus.trans_dist::ReadSharedReq 548882
1208system.cpu.toL2Bus.trans_dist::InvalidateReq 4410
1209system.cpu.toL2Bus.trans_dist::InvalidateResp 13
1210system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8674909
1211system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2657529
1212system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14746
1213system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158766
1214system.cpu.toL2Bus.pkt_count::total 11505950
1215system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370050880
1216system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99188687
1217system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13600
1218system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 272060
1219system.cpu.toL2Bus.pkt_size::total 469525227
1220system.cpu.toL2Bus.snoops 132249
1221system.cpu.toL2Bus.snoopTraffic 5775464
1222system.cpu.toL2Bus.snoop_fanout::samples 4002790
1223system.cpu.toL2Bus.snoop_fanout::mean 0.022195
1224system.cpu.toL2Bus.snoop_fanout::stdev 0.147318
1225system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
1226system.cpu.toL2Bus.snoop_fanout::0 3913947 97.78% 97.78%
1227system.cpu.toL2Bus.snoop_fanout::1 88843 2.22% 100.00%
1228system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
1229system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
1230system.cpu.toL2Bus.snoop_fanout::min_value 0
1231system.cpu.toL2Bus.snoop_fanout::max_value 1
1232system.cpu.toL2Bus.snoop_fanout::total 4002790
1233system.cpu.toL2Bus.reqLayer0.occupancy 7422385000
1234system.cpu.toL2Bus.reqLayer0.utilization 0.3
1235system.cpu.toL2Bus.snoopLayer0.occupancy 287877
1236system.cpu.toL2Bus.snoopLayer0.utilization 0.0
1237system.cpu.toL2Bus.respLayer0.occupancy 4339897791
1238system.cpu.toL2Bus.respLayer0.utilization 0.2
1239system.cpu.toL2Bus.respLayer1.occupancy 1314003533
1240system.cpu.toL2Bus.respLayer1.utilization 0.0
1241system.cpu.toL2Bus.respLayer2.occupancy 11348994
1242system.cpu.toL2Bus.respLayer2.utilization 0.0
1243system.cpu.toL2Bus.respLayer3.occupancy 90782437
1244system.cpu.toL2Bus.respLayer3.utilization 0.0
1245system.iobus.pwrStateResidencyTicks::UNDEFINED 2854927627500
1246system.iobus.trans_dist::ReadReq 30173
1247system.iobus.trans_dist::ReadResp 30173
1248system.iobus.trans_dist::WriteReq 59014
1249system.iobus.trans_dist::WriteResp 59014
1250system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170
1251system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116
1252system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434
1253system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34
1254system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20
1255system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120
1256system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834
1257system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32
1258system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16
1259system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16
1260system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16
1261system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76
1262system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16
1263system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16
1264system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4
1265system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10
1266system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16
1267system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244
1268system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268
1269system.iobus.pkt_count_system.bridge.master::total 105458
1270system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916
1271system.iobus.pkt_count_system.realview.ide.dma::total 72916
1272system.iobus.pkt_count::total 178374
1273system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887
1274system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232
1275system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638
1276system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68
1277system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40
1278system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84
1279system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441
1280system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64
1281system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32
1282system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32
1283system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32
1284system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152
1285system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32
1286system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32
1287system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8
1288system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20
1289system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32
1290system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753
1291system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536
1292system.iobus.pkt_size_system.bridge.master::total 159115
1293system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104
1294system.iobus.pkt_size_system.realview.ide.dma::total 2321104
1295system.iobus.pkt_size::total 2480219
1296system.iobus.reqLayer0.occupancy 46330500
1297system.iobus.reqLayer0.utilization 0.0
1298system.iobus.reqLayer1.occupancy 106500
1299system.iobus.reqLayer1.utilization 0.0
1300system.iobus.reqLayer2.occupancy 322500
1301system.iobus.reqLayer2.utilization 0.0
1302system.iobus.reqLayer3.occupancy 30000
1303system.iobus.reqLayer3.utilization 0.0
1304system.iobus.reqLayer4.occupancy 14500
1305system.iobus.reqLayer4.utilization 0.0
1306system.iobus.reqLayer7.occupancy 85500
1307system.iobus.reqLayer7.utilization 0.0
1308system.iobus.reqLayer8.occupancy 606500
1309system.iobus.reqLayer8.utilization 0.0
1310system.iobus.reqLayer10.occupancy 22000
1311system.iobus.reqLayer10.utilization 0.0
1312system.iobus.reqLayer13.occupancy 11000
1313system.iobus.reqLayer13.utilization 0.0
1314system.iobus.reqLayer14.occupancy 11000
1315system.iobus.reqLayer14.utilization 0.0
1316system.iobus.reqLayer15.occupancy 10500
1317system.iobus.reqLayer15.utilization 0.0
1318system.iobus.reqLayer16.occupancy 51500
1319system.iobus.reqLayer16.utilization 0.0
1320system.iobus.reqLayer17.occupancy 9500
1321system.iobus.reqLayer17.utilization 0.0
1322system.iobus.reqLayer18.occupancy 10000
1323system.iobus.reqLayer18.utilization 0.0
1324system.iobus.reqLayer19.occupancy 2500
1325system.iobus.reqLayer19.utilization 0.0
1326system.iobus.reqLayer20.occupancy 10000
1327system.iobus.reqLayer20.utilization 0.0
1328system.iobus.reqLayer21.occupancy 9000
1329system.iobus.reqLayer21.utilization 0.0
1330system.iobus.reqLayer23.occupancy 6091500
1331system.iobus.reqLayer23.utilization 0.0
1332system.iobus.reqLayer24.occupancy 39097500
1333system.iobus.reqLayer24.utilization 0.0
1334system.iobus.reqLayer25.occupancy 187695840
1335system.iobus.reqLayer25.utilization 0.0
1336system.iobus.respLayer0.occupancy 82668000
1337system.iobus.respLayer0.utilization 0.0
1338system.iobus.respLayer3.occupancy 36740000
1339system.iobus.respLayer3.utilization 0.0
1340system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2854927627500
1341system.iocache.tags.replacements 36424
1342system.iocache.tags.tagsinuse 1.033903
1343system.iocache.tags.total_refs 0
1344system.iocache.tags.sampled_refs 36440
1345system.iocache.tags.avg_refs 0
1346system.iocache.tags.warmup_cycle 272037045000
1347system.iocache.tags.occ_blocks::realview.ide 1.033903
1348system.iocache.tags.occ_percent::realview.ide 0.064619
1349system.iocache.tags.occ_percent::total 0.064619
1350system.iocache.tags.occ_task_id_blocks::1023 16
1351system.iocache.tags.age_task_id_blocks_1023::3 16
1352system.iocache.tags.occ_task_id_percent::1023 1
1353system.iocache.tags.tag_accesses 328122
1354system.iocache.tags.data_accesses 328122
1355system.iocache.pwrStateResidencyTicks::UNDEFINED 2854927627500
1356system.iocache.ReadReq_misses::realview.ide 234
1357system.iocache.ReadReq_misses::total 234
1358system.iocache.WriteLineReq_misses::realview.ide 36224
1359system.iocache.WriteLineReq_misses::total 36224
1360system.iocache.demand_misses::realview.ide 36458
1361system.iocache.demand_misses::total 36458
1362system.iocache.overall_misses::realview.ide 36458
1363system.iocache.overall_misses::total 36458
1364system.iocache.ReadReq_miss_latency::realview.ide 37408377
1365system.iocache.ReadReq_miss_latency::total 37408377
1366system.iocache.WriteLineReq_miss_latency::realview.ide 4382403463
1367system.iocache.WriteLineReq_miss_latency::total 4382403463
1368system.iocache.demand_miss_latency::realview.ide 4419811840
1369system.iocache.demand_miss_latency::total 4419811840
1370system.iocache.overall_miss_latency::realview.ide 4419811840
1371system.iocache.overall_miss_latency::total 4419811840
1372system.iocache.ReadReq_accesses::realview.ide 234
1373system.iocache.ReadReq_accesses::total 234
1374system.iocache.WriteLineReq_accesses::realview.ide 36224
1375system.iocache.WriteLineReq_accesses::total 36224
1376system.iocache.demand_accesses::realview.ide 36458
1377system.iocache.demand_accesses::total 36458
1378system.iocache.overall_accesses::realview.ide 36458
1379system.iocache.overall_accesses::total 36458
1380system.iocache.ReadReq_miss_rate::realview.ide 1
1381system.iocache.ReadReq_miss_rate::total 1
1382system.iocache.WriteLineReq_miss_rate::realview.ide 1
1383system.iocache.WriteLineReq_miss_rate::total 1
1384system.iocache.demand_miss_rate::realview.ide 1
1385system.iocache.demand_miss_rate::total 1
1386system.iocache.overall_miss_rate::realview.ide 1
1387system.iocache.overall_miss_rate::total 1
1388system.iocache.ReadReq_avg_miss_latency::realview.ide 159864.858974
1389system.iocache.ReadReq_avg_miss_latency::total 159864.858974
1390system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120980.660971
1391system.iocache.WriteLineReq_avg_miss_latency::total 120980.660971
1392system.iocache.demand_avg_miss_latency::realview.ide 121230.233145
1393system.iocache.demand_avg_miss_latency::total 121230.233145
1394system.iocache.overall_avg_miss_latency::realview.ide 121230.233145
1395system.iocache.overall_avg_miss_latency::total 121230.233145
1396system.iocache.blocked_cycles::no_mshrs 31
1397system.iocache.blocked_cycles::no_targets 0
1398system.iocache.blocked::no_mshrs 2
1399system.iocache.blocked::no_targets 0
1400system.iocache.avg_blocked_cycles::no_mshrs 15.500000
1401system.iocache.avg_blocked_cycles::no_targets nan
1402system.iocache.writebacks::writebacks 36190
1403system.iocache.writebacks::total 36190
1404system.iocache.ReadReq_mshr_misses::realview.ide 234
1405system.iocache.ReadReq_mshr_misses::total 234
1406system.iocache.WriteLineReq_mshr_misses::realview.ide 36224
1407system.iocache.WriteLineReq_mshr_misses::total 36224
1408system.iocache.demand_mshr_misses::realview.ide 36458
1409system.iocache.demand_mshr_misses::total 36458
1410system.iocache.overall_mshr_misses::realview.ide 36458
1411system.iocache.overall_mshr_misses::total 36458
1412system.iocache.ReadReq_mshr_miss_latency::realview.ide 25708377
1413system.iocache.ReadReq_mshr_miss_latency::total 25708377
1414system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2569352147
1415system.iocache.WriteLineReq_mshr_miss_latency::total 2569352147
1416system.iocache.demand_mshr_miss_latency::realview.ide 2595060524
1417system.iocache.demand_mshr_miss_latency::total 2595060524
1418system.iocache.overall_mshr_miss_latency::realview.ide 2595060524
1419system.iocache.overall_mshr_miss_latency::total 2595060524
1420system.iocache.ReadReq_mshr_miss_rate::realview.ide 1
1421system.iocache.ReadReq_mshr_miss_rate::total 1
1422system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1
1423system.iocache.WriteLineReq_mshr_miss_rate::total 1
1424system.iocache.demand_mshr_miss_rate::realview.ide 1
1425system.iocache.demand_mshr_miss_rate::total 1
1426system.iocache.overall_mshr_miss_rate::realview.ide 1
1427system.iocache.overall_mshr_miss_rate::total 1
1428system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 109864.858974
1429system.iocache.ReadReq_avg_mshr_miss_latency::total 109864.858974
1430system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70929.553528
1431system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70929.553528
1432system.iocache.demand_avg_mshr_miss_latency::realview.ide 71179.453728
1433system.iocache.demand_avg_mshr_miss_latency::total 71179.453728
1434system.iocache.overall_avg_mshr_miss_latency::realview.ide 71179.453728
1435system.iocache.overall_avg_mshr_miss_latency::total 71179.453728
1436system.membus.snoop_filter.tot_requests 336351
1437system.membus.snoop_filter.hit_single_requests 137754
1438system.membus.snoop_filter.hit_multi_requests 539
1439system.membus.snoop_filter.tot_snoops 0
1440system.membus.snoop_filter.hit_single_snoops 0
1441system.membus.snoop_filter.hit_multi_snoops 0
1442system.membus.pwrStateResidencyTicks::UNDEFINED 2854927627500
1443system.membus.trans_dist::ReadReq 34229
1444system.membus.trans_dist::ReadResp 71804
1445system.membus.trans_dist::WriteReq 27574
1446system.membus.trans_dist::WriteResp 27574
1447system.membus.trans_dist::WritebackDirty 124328
1448system.membus.trans_dist::CleanEvict 8831
1449system.membus.trans_dist::UpgradeReq 128
1450system.membus.trans_dist::SCUpgradeReq 2
1451system.membus.trans_dist::UpgradeResp 2
1452system.membus.trans_dist::ReadExReq 129200
1453system.membus.trans_dist::ReadExResp 129200
1454system.membus.trans_dist::ReadSharedReq 37575
1455system.membus.trans_dist::InvalidateReq 36224
1456system.membus.trans_dist::InvalidateResp 4361
1457system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105458
1458system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16
1459system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2034
1460system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445761
1461system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553269
1462system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897
1463system.membus.pkt_count_system.iocache.mem_side::total 72897
1464system.membus.pkt_count::total 626166
1465system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159115
1466system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512
1467system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4068
1468system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16500192
1469system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16663887
1470system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120
1471system.membus.pkt_size_system.iocache.mem_side::total 2317120
1472system.membus.pkt_size::total 18981007
1473system.membus.snoops 4866
1474system.membus.snoopTraffic 32192
1475system.membus.snoop_fanout::samples 264932
1476system.membus.snoop_fanout::mean 0.018567
1477system.membus.snoop_fanout::stdev 0.134990
1478system.membus.snoop_fanout::underflows 0 0.00% 0.00%
1479system.membus.snoop_fanout::0 260013 98.14% 98.14%
1480system.membus.snoop_fanout::1 4919 1.86% 100.00%
1481system.membus.snoop_fanout::2 0 0.00% 100.00%
1482system.membus.snoop_fanout::overflows 0 0.00% 100.00%
1483system.membus.snoop_fanout::min_value 0
1484system.membus.snoop_fanout::max_value 1
1485system.membus.snoop_fanout::total 264932
1486system.membus.reqLayer0.occupancy 92832000
1487system.membus.reqLayer0.utilization 0.0
1488system.membus.reqLayer1.occupancy 8000
1489system.membus.reqLayer1.utilization 0.0
1490system.membus.reqLayer2.occupancy 1658500
1491system.membus.reqLayer2.utilization 0.0
1492system.membus.reqLayer5.occupancy 903719482
1493system.membus.reqLayer5.utilization 0.0
1494system.membus.respLayer2.occupancy 987883000
1495system.membus.respLayer2.utilization 0.0
1496system.membus.respLayer3.occupancy 5809413
1497system.membus.respLayer3.utilization 0.0
1498system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2854927627500
1499system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
1500system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2854927627500
1501system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2854927627500
1502system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2854927627500
1503system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2854927627500
1504system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2854927627500
1505system.realview.dcc.osc_cpu.clock 16667
1506system.realview.dcc.osc_ddr.clock 25000
1507system.realview.dcc.osc_hsbm.clock 25000
1508system.realview.dcc.osc_pxl.clock 42105
1509system.realview.dcc.osc_smb.clock 20000
1510system.realview.dcc.osc_sys.clock 16667
1511system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2854927627500
1512system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2854927627500
1513system.realview.ethernet.descDMAReads 0
1514system.realview.ethernet.descDMAWrites 0
1515system.realview.ethernet.descDmaReadBytes 0
1516system.realview.ethernet.descDmaWriteBytes 0
1517system.realview.ethernet.postedSwi 0
1518system.realview.ethernet.coalescedSwi nan
1519system.realview.ethernet.totalSwi 0
1520system.realview.ethernet.postedRxIdle 0
1521system.realview.ethernet.coalescedRxIdle nan
1522system.realview.ethernet.totalRxIdle 0
1523system.realview.ethernet.postedRxOk 0
1524system.realview.ethernet.coalescedRxOk nan
1525system.realview.ethernet.totalRxOk 0
1526system.realview.ethernet.postedRxDesc 0
1527system.realview.ethernet.coalescedRxDesc nan
1528system.realview.ethernet.totalRxDesc 0
1529system.realview.ethernet.postedTxOk 0
1530system.realview.ethernet.coalescedTxOk nan
1531system.realview.ethernet.totalTxOk 0
1532system.realview.ethernet.postedTxIdle 0
1533system.realview.ethernet.coalescedTxIdle nan
1534system.realview.ethernet.totalTxIdle 0
1535system.realview.ethernet.postedTxDesc 0
1536system.realview.ethernet.coalescedTxDesc nan
1537system.realview.ethernet.totalTxDesc 0
1538system.realview.ethernet.postedRxOrn 0
1539system.realview.ethernet.coalescedRxOrn nan
1540system.realview.ethernet.totalRxOrn 0
1541system.realview.ethernet.coalescedTotal nan
1542system.realview.ethernet.postedInterrupts 0
1543system.realview.ethernet.droppedPackets 0
1544system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2854927627500
1545system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2854927627500
1546system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2854927627500
1547system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2854927627500
1548system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
1549system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
1550system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2854927627500
1551system.realview.mcc.osc_clcd.clock 42105
1552system.realview.mcc.osc_mcc.clock 20000
1553system.realview.mcc.osc_peripheral.clock 41667
1554system.realview.mcc.osc_system_bus.clock 41667
1555system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
1556system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2854927627500
1557system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
1558system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2854927627500
1559system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2854927627500
1560system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2854927627500
1561system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
1562system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
1563system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
1564system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
1565system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854927627500
1566system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854927627500
|