| stats.txt (11687:b3d5f0e9e258) | stats.txt (11754:c209cb86278a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.854926 # Number of seconds simulated 4sim_ticks 2854925996500 # Number of ticks simulated 5final_tick 2854925996500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.854886 # Number of seconds simulated 4sim_ticks 2854886132500 # Number of ticks simulated 5final_tick 2854886132500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 259837 # Simulator instruction rate (inst/s) 8host_op_rate 314167 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6622138542 # Simulator tick rate (ticks/s) 10host_mem_usage 588096 # Number of bytes of host memory used 11host_seconds 431.12 # Real time elapsed on the host 12sim_insts 112020669 # Number of instructions simulated 13sim_ops 135443008 # Number of ops (including micro ops) simulated | 7host_inst_rate 259825 # Simulator instruction rate (inst/s) 8host_op_rate 314145 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6635713455 # Simulator tick rate (ticks/s) 10host_mem_usage 588360 # Number of bytes of host memory used 11host_seconds 430.23 # Real time elapsed on the host 12sim_insts 111784531 # Number of instructions simulated 13sim_ops 135154718 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 7040 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1667200 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9190572 # Number of bytes read from this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 7232 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1667840 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9176172 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 22system.physmem.bytes_read::total 10865900 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1667200 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1667200 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7979712 # Number of bytes written to this memory | 22system.physmem.bytes_read::total 10852268 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1667840 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1667840 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7959296 # Number of bytes written to this memory |
| 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory | 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory |
| 27system.physmem.bytes_written::total 7997236 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 110 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 26050 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 144124 # Number of read requests responded to by this memory | 27system.physmem.bytes_written::total 7976820 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 113 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 26060 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 143899 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 33system.physmem.num_reads::total 170301 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 124683 # Number of write requests responded to by this memory | 33system.physmem.num_reads::total 170088 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 124364 # Number of write requests responded to by this memory |
| 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory | 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory |
| 36system.physmem.num_writes::total 129064 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 2466 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 583973 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3219198 # Total read bandwidth from this memory (bytes/s) | 36system.physmem.num_writes::total 128745 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 2533 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 584205 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3214199 # Total read bandwidth from this memory (bytes/s) |
| 41system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) | 41system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) |
| 42system.physmem.bw_read::total 3806018 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 583973 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 583973 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2795068 # Write bandwidth from this memory (bytes/s) | 42system.physmem.bw_read::total 3801296 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 584205 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 584205 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2787956 # Write bandwidth from this memory (bytes/s) |
| 46system.physmem.bw_write::cpu.data 6138 # Write bandwidth from this memory (bytes/s) | 46system.physmem.bw_write::cpu.data 6138 # Write bandwidth from this memory (bytes/s) |
| 47system.physmem.bw_write::total 2801206 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2795068 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 2466 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 583973 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 3225336 # Total bandwidth to/from this memory (bytes/s) | 47system.physmem.bw_write::total 2794094 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2787956 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 2533 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 584205 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 3220337 # Total bandwidth to/from this memory (bytes/s) |
| 53system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) | 53system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) |
| 54system.physmem.bw_total::total 6607224 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 170301 # Number of read requests accepted 56system.physmem.writeReqs 129064 # Number of write requests accepted 57system.physmem.readBursts 170301 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 129064 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 10890496 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue 61system.physmem.bytesWritten 8010048 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 10865900 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 7997236 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue | 54system.physmem.bw_total::total 6595390 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 170088 # Number of read requests accepted 56system.physmem.writeReqs 128745 # Number of write requests accepted 57system.physmem.readBursts 170088 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 128745 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 10876160 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue 61system.physmem.bytesWritten 7989120 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 10852268 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 7976820 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue |
| 65system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 65system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 67system.physmem.perBankRdBursts::0 10638 # Per bank write bursts 68system.physmem.perBankRdBursts::1 10529 # Per bank write bursts 69system.physmem.perBankRdBursts::2 10665 # Per bank write bursts 70system.physmem.perBankRdBursts::3 10242 # Per bank write bursts 71system.physmem.perBankRdBursts::4 13390 # Per bank write bursts 72system.physmem.perBankRdBursts::5 10196 # Per bank write bursts 73system.physmem.perBankRdBursts::6 10392 # Per bank write bursts 74system.physmem.perBankRdBursts::7 10920 # Per bank write bursts 75system.physmem.perBankRdBursts::8 10199 # Per bank write bursts 76system.physmem.perBankRdBursts::9 10416 # Per bank write bursts 77system.physmem.perBankRdBursts::10 10277 # Per bank write bursts 78system.physmem.perBankRdBursts::11 9652 # Per bank write bursts 79system.physmem.perBankRdBursts::12 10777 # Per bank write bursts 80system.physmem.perBankRdBursts::13 11476 # Per bank write bursts 81system.physmem.perBankRdBursts::14 10256 # Per bank write bursts 82system.physmem.perBankRdBursts::15 10139 # Per bank write bursts 83system.physmem.perBankWrBursts::0 7926 # Per bank write bursts 84system.physmem.perBankWrBursts::1 7916 # Per bank write bursts 85system.physmem.perBankWrBursts::2 8341 # Per bank write bursts 86system.physmem.perBankWrBursts::3 7830 # Per bank write bursts 87system.physmem.perBankWrBursts::4 7635 # Per bank write bursts 88system.physmem.perBankWrBursts::5 7427 # Per bank write bursts 89system.physmem.perBankWrBursts::6 7524 # Per bank write bursts 90system.physmem.perBankWrBursts::7 8090 # Per bank write bursts 91system.physmem.perBankWrBursts::8 7812 # Per bank write bursts 92system.physmem.perBankWrBursts::9 7846 # Per bank write bursts 93system.physmem.perBankWrBursts::10 7622 # Per bank write bursts 94system.physmem.perBankWrBursts::11 7450 # Per bank write bursts 95system.physmem.perBankWrBursts::12 8154 # Per bank write bursts 96system.physmem.perBankWrBursts::13 8593 # Per bank write bursts 97system.physmem.perBankWrBursts::14 7575 # Per bank write bursts 98system.physmem.perBankWrBursts::15 7416 # Per bank write bursts | 67system.physmem.perBankRdBursts::0 10602 # Per bank write bursts 68system.physmem.perBankRdBursts::1 10348 # Per bank write bursts 69system.physmem.perBankRdBursts::2 10682 # Per bank write bursts 70system.physmem.perBankRdBursts::3 10189 # Per bank write bursts 71system.physmem.perBankRdBursts::4 13369 # Per bank write bursts 72system.physmem.perBankRdBursts::5 10294 # Per bank write bursts 73system.physmem.perBankRdBursts::6 10368 # Per bank write bursts 74system.physmem.perBankRdBursts::7 10838 # Per bank write bursts 75system.physmem.perBankRdBursts::8 10130 # Per bank write bursts 76system.physmem.perBankRdBursts::9 10489 # Per bank write bursts 77system.physmem.perBankRdBursts::10 10055 # Per bank write bursts 78system.physmem.perBankRdBursts::11 9592 # Per bank write bursts 79system.physmem.perBankRdBursts::12 10755 # Per bank write bursts 80system.physmem.perBankRdBursts::13 11804 # Per bank write bursts 81system.physmem.perBankRdBursts::14 10513 # Per bank write bursts 82system.physmem.perBankRdBursts::15 9912 # Per bank write bursts 83system.physmem.perBankWrBursts::0 7846 # Per bank write bursts 84system.physmem.perBankWrBursts::1 7741 # Per bank write bursts 85system.physmem.perBankWrBursts::2 8334 # Per bank write bursts 86system.physmem.perBankWrBursts::3 7790 # Per bank write bursts 87system.physmem.perBankWrBursts::4 7606 # Per bank write bursts 88system.physmem.perBankWrBursts::5 7522 # Per bank write bursts 89system.physmem.perBankWrBursts::6 7517 # Per bank write bursts 90system.physmem.perBankWrBursts::7 7997 # Per bank write bursts 91system.physmem.perBankWrBursts::8 7756 # Per bank write bursts 92system.physmem.perBankWrBursts::9 7896 # Per bank write bursts 93system.physmem.perBankWrBursts::10 7435 # Per bank write bursts 94system.physmem.perBankWrBursts::11 7391 # Per bank write bursts 95system.physmem.perBankWrBursts::12 8149 # Per bank write bursts 96system.physmem.perBankWrBursts::13 8812 # Per bank write bursts 97system.physmem.perBankWrBursts::14 7798 # Per bank write bursts 98system.physmem.perBankWrBursts::15 7240 # Per bank write bursts |
| 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 100system.physmem.numWrRetry 56 # Number of times write queue was full causing retry 101system.physmem.totGap 2854925546000 # Total gap between requests | 100system.physmem.numWrRetry 69 # Number of times write queue was full causing retry 101system.physmem.totGap 2854885682000 # Total gap between requests |
| 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 543 # Read request sizes (log2) 105system.physmem.readPktSize::3 14 # Read request sizes (log2) 106system.physmem.readPktSize::4 0 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) | 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 543 # Read request sizes (log2) 105system.physmem.readPktSize::3 14 # Read request sizes (log2) 106system.physmem.readPktSize::4 0 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 108system.physmem.readPktSize::6 169744 # Read request sizes (log2) | 108system.physmem.readPktSize::6 169531 # Read request sizes (log2) |
| 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 4381 # Write request sizes (log2) 112system.physmem.writePktSize::3 0 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) | 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 4381 # Write request sizes (log2) 112system.physmem.writePktSize::3 0 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 115system.physmem.writePktSize::6 124683 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 160221 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 9636 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 294 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see | 115system.physmem.writePktSize::6 124364 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 160094 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 9538 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 296 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see |
| 120system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see --- 27 unchanged lines hidden (view full) --- 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 120system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see --- 27 unchanged lines hidden (view full) --- 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 163system.physmem.wrQLenPdf::15 1833 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 2641 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 5947 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 6248 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 6539 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 6191 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 6635 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 6984 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 7561 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 7557 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 8594 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 9006 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 7531 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 7120 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 7083 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 6851 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 6591 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 6684 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 453 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 463 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 366 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 298 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 246 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 263 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 286 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 255 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 211 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 230 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 270 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 254 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 268 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 280 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 200 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 256 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 235 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 219 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 209 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 188 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 208 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 231 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 203 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 214 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 246 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 160 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 98 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 138 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 60414 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 312.849340 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 185.889118 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 328.883375 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 21657 35.85% 35.85% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 14616 24.19% 60.04% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 6864 11.36% 71.40% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 3516 5.82% 77.22% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 2636 4.36% 81.59% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 1611 2.67% 84.25% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 1067 1.77% 86.02% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 953 1.58% 87.60% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 7494 12.40% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 60414 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 6196 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 27.463041 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 582.417033 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-2047 6195 99.98% 99.98% # Reads before turning the bus around for writes | 163system.physmem.wrQLenPdf::15 1848 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 2664 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 5925 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 6226 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 6598 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 6259 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 6588 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 6880 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 7703 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 7446 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 8538 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 9004 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 7391 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 7010 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 7044 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 6699 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 6588 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 6615 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 419 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 445 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 410 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 300 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 298 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 326 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 266 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 257 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 249 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 277 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 297 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 322 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 214 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 255 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 286 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 243 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 219 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 232 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 207 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 222 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 175 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 195 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 255 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 242 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 116 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 248 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 189 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 190 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 111 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 60347 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 312.612325 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 185.506399 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 329.136235 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 21716 35.99% 35.99% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 14599 24.19% 60.18% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 6802 11.27% 71.45% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 3528 5.85% 77.29% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 2551 4.23% 81.52% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 1581 2.62% 84.14% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 1111 1.84% 85.98% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 1010 1.67% 87.66% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 7449 12.34% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 60347 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 6172 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 27.532242 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 583.546907 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-2047 6171 99.98% 99.98% # Reads before turning the bus around for writes |
| 230system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes | 230system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 231system.physmem.rdPerTurnAround::total 6196 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 6196 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 20.199645 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.300177 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 15.412164 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 5485 88.52% 88.52% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 67 1.08% 89.61% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 43 0.69% 90.30% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 35 0.56% 90.87% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 272 4.39% 95.26% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 29 0.47% 95.72% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 8 0.13% 95.85% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 11 0.18% 96.03% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 11 0.18% 96.21% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 3 0.05% 96.26% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 4 0.06% 96.32% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 7 0.11% 96.43% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 138 2.23% 98.66% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 3 0.05% 98.71% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 2 0.03% 98.74% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 7 0.11% 98.85% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 6 0.10% 98.95% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::88-91 1 0.02% 98.97% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::100-103 1 0.02% 98.98% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::104-107 1 0.02% 99.00% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::108-111 13 0.21% 99.21% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::120-123 2 0.03% 99.24% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::124-127 3 0.05% 99.29% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::128-131 12 0.19% 99.48% # Writes before turning the bus around for reads | 231system.physmem.rdPerTurnAround::total 6172 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 6172 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 20.225211 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.326492 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 15.268498 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 5463 88.51% 88.51% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 63 1.02% 89.53% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 33 0.53% 90.07% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 41 0.66% 90.73% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 274 4.44% 95.17% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 26 0.42% 95.59% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 14 0.23% 95.82% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 8 0.13% 95.95% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 10 0.16% 96.11% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 4 0.06% 96.18% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 5 0.08% 96.26% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 7 0.11% 96.37% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 140 2.27% 98.64% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 5 0.08% 98.72% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 4 0.06% 98.78% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 6 0.10% 98.88% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 3 0.05% 98.93% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::84-87 2 0.03% 98.96% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::96-99 3 0.05% 99.01% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::104-107 1 0.02% 99.03% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::108-111 11 0.18% 99.21% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::124-127 3 0.05% 99.25% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::128-131 14 0.23% 99.48% # Writes before turning the bus around for reads |
| 260system.physmem.wrPerTurnAround::132-135 6 0.10% 99.58% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::136-139 4 0.06% 99.64% # Writes before turning the bus around for reads | 259system.physmem.wrPerTurnAround::132-135 6 0.10% 99.58% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::136-139 4 0.06% 99.64% # Writes before turning the bus around for reads |
| 262system.physmem.wrPerTurnAround::140-143 3 0.05% 99.69% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::144-147 2 0.03% 99.73% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::148-151 1 0.02% 99.74% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::156-159 1 0.02% 99.76% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::164-167 1 0.02% 99.77% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::172-175 3 0.05% 99.82% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::180-183 1 0.02% 99.84% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::184-187 1 0.02% 99.85% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::188-191 4 0.06% 99.92% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::192-195 4 0.06% 99.98% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::total 6196 # Writes before turning the bus around for reads 274system.physmem.totQLat 4595967000 # Total ticks spent queuing 275system.physmem.totMemAccLat 7786542000 # Total ticks spent from burst creation until serviced by the DRAM 276system.physmem.totBusLat 850820000 # Total ticks spent in databus transfers 277system.physmem.avgQLat 27009.04 # Average queueing delay per DRAM burst | 261system.physmem.wrPerTurnAround::140-143 6 0.10% 99.74% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::144-147 2 0.03% 99.77% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::156-159 2 0.03% 99.81% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::160-163 1 0.02% 99.82% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::172-175 2 0.03% 99.85% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::176-179 1 0.02% 99.87% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::184-187 1 0.02% 99.89% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::188-191 2 0.03% 99.92% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::192-195 3 0.05% 99.97% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::196-199 2 0.03% 100.00% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::total 6172 # Writes before turning the bus around for reads 272system.physmem.totQLat 4562123250 # Total ticks spent queuing 273system.physmem.totMemAccLat 7748498250 # Total ticks spent from burst creation until serviced by the DRAM 274system.physmem.totBusLat 849700000 # Total ticks spent in databus transfers 275system.physmem.avgQLat 26845.49 # Average queueing delay per DRAM burst |
| 278system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 276system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 279system.physmem.avgMemAccLat 45759.04 # Average memory access latency per DRAM burst | 277system.physmem.avgMemAccLat 45595.49 # Average memory access latency per DRAM burst |
| 280system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s | 278system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s |
| 281system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s 282system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s 283system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s | 279system.physmem.avgWrBW 2.80 # Average achieved write bandwidth in MiByte/s 280system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s 281system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s |
| 284system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 285system.physmem.busUtil 0.05 # Data bus utilization in percentage 286system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 287system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 288system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing | 282system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 283system.physmem.busUtil 0.05 # Data bus utilization in percentage 284system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 285system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 286system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing |
| 289system.physmem.avgWrQLen 23.01 # Average write queue length when enqueuing 290system.physmem.readRowHits 140583 # Number of row buffer hits during reads 291system.physmem.writeRowHits 94323 # Number of row buffer hits during writes 292system.physmem.readRowHitRate 82.62 # Row buffer hit rate for reads 293system.physmem.writeRowHitRate 75.35 # Row buffer hit rate for writes 294system.physmem.avgGap 9536604.30 # Average gap between requests 295system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined 296system.physmem_0.actEnergy 218405460 # Energy for activate commands per rank (pJ) 297system.physmem_0.preEnergy 116085255 # Energy for precharge commands per rank (pJ) 298system.physmem_0.readEnergy 620980080 # Energy for read commands per rank (pJ) 299system.physmem_0.writeEnergy 327236580 # Energy for write commands per rank (pJ) 300system.physmem_0.refreshEnergy 6016710960.000001 # Energy for refresh commands per rank (pJ) 301system.physmem_0.actBackEnergy 4587085260 # Energy for active background per rank (pJ) 302system.physmem_0.preBackEnergy 376629120 # Energy for precharge background per rank (pJ) 303system.physmem_0.actPowerDownEnergy 12457025670 # Energy for active power-down per rank (pJ) 304system.physmem_0.prePowerDownEnergy 8414413920 # Energy for precharge power-down per rank (pJ) 305system.physmem_0.selfRefreshEnergy 671932680540 # Energy for self refresh per rank (pJ) 306system.physmem_0.totalEnergy 705069857835 # Total energy per rank (pJ) 307system.physmem_0.averagePower 246.966071 # Core power per rank (mW) 308system.physmem_0.totalIdleTime 2843548486750 # Total Idle time Per DRAM Rank 309system.physmem_0.memoryStateTime::IDLE 708499000 # Time in different power states 310system.physmem_0.memoryStateTime::REF 2558586000 # Time in different power states 311system.physmem_0.memoryStateTime::SREF 2794649429000 # Time in different power states 312system.physmem_0.memoryStateTime::PRE_PDN 21912527500 # Time in different power states 313system.physmem_0.memoryStateTime::ACT 7778804250 # Time in different power states 314system.physmem_0.memoryStateTime::ACT_PDN 27318150750 # Time in different power states 315system.physmem_1.actEnergy 212957640 # Energy for activate commands per rank (pJ) 316system.physmem_1.preEnergy 113185875 # Energy for precharge commands per rank (pJ) 317system.physmem_1.readEnergy 593990880 # Energy for read commands per rank (pJ) 318system.physmem_1.writeEnergy 326082960 # Energy for write commands per rank (pJ) 319system.physmem_1.refreshEnergy 6113824080.000001 # Energy for refresh commands per rank (pJ) 320system.physmem_1.actBackEnergy 4455367380 # Energy for active background per rank (pJ) 321system.physmem_1.preBackEnergy 374460480 # Energy for precharge background per rank (pJ) 322system.physmem_1.actPowerDownEnergy 12365716800 # Energy for active power-down per rank (pJ) 323system.physmem_1.prePowerDownEnergy 8661645120 # Energy for precharge power-down per rank (pJ) 324system.physmem_1.selfRefreshEnergy 671979444945 # Energy for self refresh per rank (pJ) 325system.physmem_1.totalEnergy 705199696980 # Total energy per rank (pJ) 326system.physmem_1.averagePower 247.011550 # Core power per rank (mW) 327system.physmem_1.totalIdleTime 2844173514000 # Total Idle time Per DRAM Rank 328system.physmem_1.memoryStateTime::IDLE 705782750 # Time in different power states 329system.physmem_1.memoryStateTime::REF 2600572000 # Time in different power states 330system.physmem_1.memoryStateTime::SREF 2794499397250 # Time in different power states 331system.physmem_1.memoryStateTime::PRE_PDN 22556418250 # Time in different power states 332system.physmem_1.memoryStateTime::ACT 7446062750 # Time in different power states 333system.physmem_1.memoryStateTime::ACT_PDN 27117763500 # Time in different power states 334system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states | 287system.physmem.avgWrQLen 25.21 # Average write queue length when enqueuing 288system.physmem.readRowHits 140395 # Number of row buffer hits during reads 289system.physmem.writeRowHits 94027 # Number of row buffer hits during writes 290system.physmem.readRowHitRate 82.61 # Row buffer hit rate for reads 291system.physmem.writeRowHitRate 75.31 # Row buffer hit rate for writes 292system.physmem.avgGap 9553448.52 # Average gap between requests 293system.physmem.pageHitRate 79.52 # Row buffer hit rate, read and write combined 294system.physmem_0.actEnergy 217784280 # Energy for activate commands per rank (pJ) 295system.physmem_0.preEnergy 115755090 # Energy for precharge commands per rank (pJ) 296system.physmem_0.readEnergy 618966600 # Energy for read commands per rank (pJ) 297system.physmem_0.writeEnergy 325482660 # Energy for write commands per rank (pJ) 298system.physmem_0.refreshEnergy 6028389120.000001 # Energy for refresh commands per rank (pJ) 299system.physmem_0.actBackEnergy 4546972650 # Energy for active background per rank (pJ) 300system.physmem_0.preBackEnergy 380659200 # Energy for precharge background per rank (pJ) 301system.physmem_0.actPowerDownEnergy 12537712590 # Energy for active power-down per rank (pJ) 302system.physmem_0.prePowerDownEnergy 8446773120 # Energy for precharge power-down per rank (pJ) 303system.physmem_0.selfRefreshEnergy 671876398965 # Energy for self refresh per rank (pJ) 304system.physmem_0.totalEnergy 705097688865 # Total energy per rank (pJ) 305system.physmem_0.averagePower 246.979269 # Core power per rank (mW) 306system.physmem_0.totalIdleTime 2843583812750 # Total Idle time Per DRAM Rank 307system.physmem_0.memoryStateTime::IDLE 720868250 # Time in different power states 308system.physmem_0.memoryStateTime::REF 2563490000 # Time in different power states 309system.physmem_0.memoryStateTime::SREF 2794425375000 # Time in different power states 310system.physmem_0.memoryStateTime::PRE_PDN 21996678750 # Time in different power states 311system.physmem_0.memoryStateTime::ACT 7684667500 # Time in different power states 312system.physmem_0.memoryStateTime::ACT_PDN 27495053000 # Time in different power states 313system.physmem_1.actEnergy 213100440 # Energy for activate commands per rank (pJ) 314system.physmem_1.preEnergy 113261775 # Energy for precharge commands per rank (pJ) 315system.physmem_1.readEnergy 594405000 # Energy for read commands per rank (pJ) 316system.physmem_1.writeEnergy 326129940 # Energy for write commands per rank (pJ) 317system.physmem_1.refreshEnergy 6103375200.000001 # Energy for refresh commands per rank (pJ) 318system.physmem_1.actBackEnergy 4480349340 # Energy for active background per rank (pJ) 319system.physmem_1.preBackEnergy 365416320 # Energy for precharge background per rank (pJ) 320system.physmem_1.actPowerDownEnergy 12364122510 # Energy for active power-down per rank (pJ) 321system.physmem_1.prePowerDownEnergy 8637319200 # Energy for precharge power-down per rank (pJ) 322system.physmem_1.selfRefreshEnergy 671971041390 # Energy for self refresh per rank (pJ) 323system.physmem_1.totalEnergy 705171178185 # Total energy per rank (pJ) 324system.physmem_1.averagePower 247.005010 # Core power per rank (mW) 325system.physmem_1.totalIdleTime 2844103138750 # Total Idle time Per DRAM Rank 326system.physmem_1.memoryStateTime::IDLE 682770250 # Time in different power states 327system.physmem_1.memoryStateTime::REF 2596086000 # Time in different power states 328system.physmem_1.memoryStateTime::SREF 2794495958000 # Time in different power states 329system.physmem_1.memoryStateTime::PRE_PDN 22493040000 # Time in different power states 330system.physmem_1.memoryStateTime::ACT 7504072000 # Time in different power states 331system.physmem_1.memoryStateTime::ACT_PDN 27114206250 # Time in different power states 332system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states |
| 335system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory 336system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory 337system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory 338system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory 339system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 340system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 341system.realview.nvmem.bw_read::cpu.inst 179 # Total read bandwidth from this memory (bytes/s) 342system.realview.nvmem.bw_read::total 179 # Total read bandwidth from this memory (bytes/s) 343system.realview.nvmem.bw_inst_read::cpu.inst 179 # Instruction read bandwidth from this memory (bytes/s) 344system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s) 345system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s) 346system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s) | 333system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory 334system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory 335system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory 336system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory 337system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 338system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 339system.realview.nvmem.bw_read::cpu.inst 179 # Total read bandwidth from this memory (bytes/s) 340system.realview.nvmem.bw_read::total 179 # Total read bandwidth from this memory (bytes/s) 341system.realview.nvmem.bw_inst_read::cpu.inst 179 # Instruction read bandwidth from this memory (bytes/s) 342system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s) 343system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s) 344system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s) |
| 347system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 348system.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 349system.bridge.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states | 345system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 346system.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 347system.bridge.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states |
| 350system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 351system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 352system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 353system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 354system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 355system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 348system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 349system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 350system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 351system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 352system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 353system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 356system.cpu.branchPred.lookups 31074836 # Number of BP lookups 357system.cpu.branchPred.condPredicted 16867509 # Number of conditional branches predicted 358system.cpu.branchPred.condIncorrect 2481345 # Number of conditional branches incorrect 359system.cpu.branchPred.BTBLookups 18655029 # Number of BTB lookups 360system.cpu.branchPred.BTBHits 10408802 # Number of BTB hits | 354system.cpu.branchPred.lookups 31050902 # Number of BP lookups 355system.cpu.branchPred.condPredicted 16823011 # Number of conditional branches predicted 356system.cpu.branchPred.condIncorrect 2467385 # Number of conditional branches incorrect 357system.cpu.branchPred.BTBLookups 18598277 # Number of BTB lookups 358system.cpu.branchPred.BTBHits 10398347 # Number of BTB hits |
| 361system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 359system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 362system.cpu.branchPred.BTBHitPct 55.796225 # BTB Hit Percentage 363system.cpu.branchPred.usedRAS 7856601 # Number of times the RAS was used to get a target. 364system.cpu.branchPred.RASInCorrect 1514233 # Number of incorrect RAS predictions. 365system.cpu.branchPred.indirectLookups 3068747 # Number of indirect predictor lookups. 366system.cpu.branchPred.indirectHits 2872226 # Number of indirect target hits. 367system.cpu.branchPred.indirectMisses 196521 # Number of indirect misses. 368system.cpu.branchPredindirectMispredicted 109392 # Number of mispredicted indirect branches. | 360system.cpu.branchPred.BTBHitPct 55.910271 # BTB Hit Percentage 361system.cpu.branchPred.usedRAS 7909634 # Number of times the RAS was used to get a target. 362system.cpu.branchPred.RASInCorrect 1502216 # Number of incorrect RAS predictions. 363system.cpu.branchPred.indirectLookups 3035557 # Number of indirect predictor lookups. 364system.cpu.branchPred.indirectHits 2846976 # Number of indirect target hits. 365system.cpu.branchPred.indirectMisses 188581 # Number of indirect misses. 366system.cpu.branchPredindirectMispredicted 109207 # Number of mispredicted indirect branches. |
| 369system.cpu_clk_domain.clock 500 # Clock period in ticks | 367system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 370system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states | 368system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states |
| 371system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 372system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 373system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 374system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 375system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 376system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 377system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 378system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 392system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 393system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 394system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 395system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 396system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 397system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 398system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 399system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 369system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 370system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 371system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 372system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 373system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 374system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 375system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 376system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 390system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 391system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 392system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 393system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 394system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 395system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 396system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 397system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 400system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 401system.cpu.dtb.walker.walks 68070 # Table walker walks requested 402system.cpu.dtb.walker.walksShort 68070 # Table walker walks initiated with short descriptors 403system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44787 # Level at which table walker walks with short descriptors terminate 404system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23283 # Level at which table walker walks with short descriptors terminate 405system.cpu.dtb.walker.walkWaitTime::samples 68070 # Table walker wait (enqueue to first request) latency 406system.cpu.dtb.walker.walkWaitTime::0 68070 100.00% 100.00% # Table walker wait (enqueue to first request) latency 407system.cpu.dtb.walker.walkWaitTime::total 68070 # Table walker wait (enqueue to first request) latency 408system.cpu.dtb.walker.walkCompletionTime::samples 7877 # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walkCompletionTime::mean 10134.378571 # Table walker service (enqueue to completion) latency 410system.cpu.dtb.walker.walkCompletionTime::gmean 8445.879455 # Table walker service (enqueue to completion) latency 411system.cpu.dtb.walker.walkCompletionTime::stdev 9567.630419 # Table walker service (enqueue to completion) latency 412system.cpu.dtb.walker.walkCompletionTime::0-65535 7869 99.90% 99.90% # Table walker service (enqueue to completion) latency 413system.cpu.dtb.walker.walkCompletionTime::65536-131071 6 0.08% 99.97% # Table walker service (enqueue to completion) latency 414system.cpu.dtb.walker.walkCompletionTime::131072-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency | 398system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 399system.cpu.dtb.walker.walks 67916 # Table walker walks requested 400system.cpu.dtb.walker.walksShort 67916 # Table walker walks initiated with short descriptors 401system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44853 # Level at which table walker walks with short descriptors terminate 402system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23063 # Level at which table walker walks with short descriptors terminate 403system.cpu.dtb.walker.walkWaitTime::samples 67916 # Table walker wait (enqueue to first request) latency 404system.cpu.dtb.walker.walkWaitTime::0 67916 100.00% 100.00% # Table walker wait (enqueue to first request) latency 405system.cpu.dtb.walker.walkWaitTime::total 67916 # Table walker wait (enqueue to first request) latency 406system.cpu.dtb.walker.walkCompletionTime::samples 7871 # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walkCompletionTime::mean 10132.638801 # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walkCompletionTime::gmean 8470.700593 # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walkCompletionTime::stdev 9365.136659 # Table walker service (enqueue to completion) latency 410system.cpu.dtb.walker.walkCompletionTime::0-65535 7864 99.91% 99.91% # Table walker service (enqueue to completion) latency 411system.cpu.dtb.walker.walkCompletionTime::65536-131071 6 0.08% 99.99% # Table walker service (enqueue to completion) latency |
| 415system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00% # Table walker service (enqueue to completion) latency | 412system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00% # Table walker service (enqueue to completion) latency |
| 416system.cpu.dtb.walker.walkCompletionTime::total 7877 # Table walker service (enqueue to completion) latency | 413system.cpu.dtb.walker.walkCompletionTime::total 7871 # Table walker service (enqueue to completion) latency |
| 417system.cpu.dtb.walker.walksPending::samples 276581000 # Table walker pending requests distribution 418system.cpu.dtb.walker.walksPending::0 276581000 100.00% 100.00% # Table walker pending requests distribution 419system.cpu.dtb.walker.walksPending::total 276581000 # Table walker pending requests distribution | 414system.cpu.dtb.walker.walksPending::samples 276581000 # Table walker pending requests distribution 415system.cpu.dtb.walker.walksPending::0 276581000 100.00% 100.00% # Table walker pending requests distribution 416system.cpu.dtb.walker.walksPending::total 276581000 # Table walker pending requests distribution |
| 420system.cpu.dtb.walker.walkPageSizes::4K 6513 82.68% 82.68% # Table walker page sizes translated 421system.cpu.dtb.walker.walkPageSizes::1M 1364 17.32% 100.00% # Table walker page sizes translated 422system.cpu.dtb.walker.walkPageSizes::total 7877 # Table walker page sizes translated 423system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 68070 # Table walker requests started/completed, data/inst | 417system.cpu.dtb.walker.walkPageSizes::4K 6482 82.35% 82.35% # Table walker page sizes translated 418system.cpu.dtb.walker.walkPageSizes::1M 1389 17.65% 100.00% # Table walker page sizes translated 419system.cpu.dtb.walker.walkPageSizes::total 7871 # Table walker page sizes translated 420system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 67916 # Table walker requests started/completed, data/inst |
| 424system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 421system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 425system.cpu.dtb.walker.walkRequestOrigin_Requested::total 68070 # Table walker requests started/completed, data/inst 426system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7877 # Table walker requests started/completed, data/inst | 422system.cpu.dtb.walker.walkRequestOrigin_Requested::total 67916 # Table walker requests started/completed, data/inst 423system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7871 # Table walker requests started/completed, data/inst |
| 427system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 424system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 428system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7877 # Table walker requests started/completed, data/inst 429system.cpu.dtb.walker.walkRequestOrigin::total 75947 # Table walker requests started/completed, data/inst | 425system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7871 # Table walker requests started/completed, data/inst 426system.cpu.dtb.walker.walkRequestOrigin::total 75787 # Table walker requests started/completed, data/inst |
| 430system.cpu.dtb.inst_hits 0 # ITB inst hits 431system.cpu.dtb.inst_misses 0 # ITB inst misses | 427system.cpu.dtb.inst_hits 0 # ITB inst hits 428system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 432system.cpu.dtb.read_hits 24743648 # DTB read hits 433system.cpu.dtb.read_misses 61017 # DTB read misses 434system.cpu.dtb.write_hits 19435570 # DTB write hits 435system.cpu.dtb.write_misses 7053 # DTB write misses | 429system.cpu.dtb.read_hits 24685993 # DTB read hits 430system.cpu.dtb.read_misses 61030 # DTB read misses 431system.cpu.dtb.write_hits 19409907 # DTB write hits 432system.cpu.dtb.write_misses 6886 # DTB write misses |
| 436system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 437system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 438system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 439system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 433system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 434system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 435system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 436system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 440system.cpu.dtb.flush_entries 4279 # Number of entries that have been flushed from TLB 441system.cpu.dtb.align_faults 1461 # Number of TLB faults due to alignment restrictions 442system.cpu.dtb.prefetch_faults 1806 # Number of TLB faults due to prefetch | 437system.cpu.dtb.flush_entries 4276 # Number of entries that have been flushed from TLB 438system.cpu.dtb.align_faults 1444 # Number of TLB faults due to alignment restrictions 439system.cpu.dtb.prefetch_faults 1826 # Number of TLB faults due to prefetch |
| 443system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 444system.cpu.dtb.perms_faults 755 # Number of TLB faults due to permissions restrictions | 440system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 441system.cpu.dtb.perms_faults 755 # Number of TLB faults due to permissions restrictions |
| 445system.cpu.dtb.read_accesses 24804665 # DTB read accesses 446system.cpu.dtb.write_accesses 19442623 # DTB write accesses | 442system.cpu.dtb.read_accesses 24747023 # DTB read accesses 443system.cpu.dtb.write_accesses 19416793 # DTB write accesses |
| 447system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 444system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 448system.cpu.dtb.hits 44179218 # DTB hits 449system.cpu.dtb.misses 68070 # DTB misses 450system.cpu.dtb.accesses 44247288 # DTB accesses 451system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states | 445system.cpu.dtb.hits 44095900 # DTB hits 446system.cpu.dtb.misses 67916 # DTB misses 447system.cpu.dtb.accesses 44163816 # DTB accesses 448system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states |
| 452system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 453system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 454system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 455system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 456system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 457system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 458system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 459system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 473system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 474system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 475system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 476system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 477system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 478system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 479system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 480system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 449system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 450system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 451system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 452system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 453system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 454system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 455system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 456system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 470system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 471system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 472system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 473system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 474system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 475system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 476system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 477system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 481system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 482system.cpu.itb.walker.walks 5855 # Table walker walks requested 483system.cpu.itb.walker.walksShort 5855 # Table walker walks initiated with short descriptors 484system.cpu.itb.walker.walksShortTerminationLevel::Level1 322 # Level at which table walker walks with short descriptors terminate 485system.cpu.itb.walker.walksShortTerminationLevel::Level2 5533 # Level at which table walker walks with short descriptors terminate 486system.cpu.itb.walker.walkWaitTime::samples 5855 # Table walker wait (enqueue to first request) latency 487system.cpu.itb.walker.walkWaitTime::0 5855 100.00% 100.00% # Table walker wait (enqueue to first request) latency 488system.cpu.itb.walker.walkWaitTime::total 5855 # Table walker wait (enqueue to first request) latency 489system.cpu.itb.walker.walkCompletionTime::samples 3194 # Table walker service (enqueue to completion) latency 490system.cpu.itb.walker.walkCompletionTime::mean 10424.389480 # Table walker service (enqueue to completion) latency 491system.cpu.itb.walker.walkCompletionTime::gmean 8603.860466 # Table walker service (enqueue to completion) latency 492system.cpu.itb.walker.walkCompletionTime::stdev 6932.586443 # Table walker service (enqueue to completion) latency 493system.cpu.itb.walker.walkCompletionTime::0-8191 1846 57.80% 57.80% # Table walker service (enqueue to completion) latency 494system.cpu.itb.walker.walkCompletionTime::8192-16383 798 24.98% 82.78% # Table walker service (enqueue to completion) latency 495system.cpu.itb.walker.walkCompletionTime::16384-24575 544 17.03% 99.81% # Table walker service (enqueue to completion) latency | 478system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 479system.cpu.itb.walker.walks 5836 # Table walker walks requested 480system.cpu.itb.walker.walksShort 5836 # Table walker walks initiated with short descriptors 481system.cpu.itb.walker.walksShortTerminationLevel::Level1 323 # Level at which table walker walks with short descriptors terminate 482system.cpu.itb.walker.walksShortTerminationLevel::Level2 5513 # Level at which table walker walks with short descriptors terminate 483system.cpu.itb.walker.walkWaitTime::samples 5836 # Table walker wait (enqueue to first request) latency 484system.cpu.itb.walker.walkWaitTime::0 5836 100.00% 100.00% # Table walker wait (enqueue to first request) latency 485system.cpu.itb.walker.walkWaitTime::total 5836 # Table walker wait (enqueue to first request) latency 486system.cpu.itb.walker.walkCompletionTime::samples 3199 # Table walker service (enqueue to completion) latency 487system.cpu.itb.walker.walkCompletionTime::mean 10502.500781 # Table walker service (enqueue to completion) latency 488system.cpu.itb.walker.walkCompletionTime::gmean 8663.235820 # Table walker service (enqueue to completion) latency 489system.cpu.itb.walker.walkCompletionTime::stdev 6980.719897 # Table walker service (enqueue to completion) latency 490system.cpu.itb.walker.walkCompletionTime::0-8191 1845 57.67% 57.67% # Table walker service (enqueue to completion) latency 491system.cpu.itb.walker.walkCompletionTime::8192-16383 784 24.51% 82.18% # Table walker service (enqueue to completion) latency 492system.cpu.itb.walker.walkCompletionTime::16384-24575 564 17.63% 99.81% # Table walker service (enqueue to completion) latency |
| 496system.cpu.itb.walker.walkCompletionTime::24576-32767 5 0.16% 99.97% # Table walker service (enqueue to completion) latency 497system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency | 493system.cpu.itb.walker.walkCompletionTime::24576-32767 5 0.16% 99.97% # Table walker service (enqueue to completion) latency 494system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency |
| 498system.cpu.itb.walker.walkCompletionTime::total 3194 # Table walker service (enqueue to completion) latency | 495system.cpu.itb.walker.walkCompletionTime::total 3199 # Table walker service (enqueue to completion) latency |
| 499system.cpu.itb.walker.walksPending::samples 276141500 # Table walker pending requests distribution 500system.cpu.itb.walker.walksPending::0 276141500 100.00% 100.00% # Table walker pending requests distribution 501system.cpu.itb.walker.walksPending::total 276141500 # Table walker pending requests distribution | 496system.cpu.itb.walker.walksPending::samples 276141500 # Table walker pending requests distribution 497system.cpu.itb.walker.walksPending::0 276141500 100.00% 100.00% # Table walker pending requests distribution 498system.cpu.itb.walker.walksPending::total 276141500 # Table walker pending requests distribution |
| 502system.cpu.itb.walker.walkPageSizes::4K 2884 90.29% 90.29% # Table walker page sizes translated 503system.cpu.itb.walker.walkPageSizes::1M 310 9.71% 100.00% # Table walker page sizes translated 504system.cpu.itb.walker.walkPageSizes::total 3194 # Table walker page sizes translated | 499system.cpu.itb.walker.walkPageSizes::4K 2889 90.31% 90.31% # Table walker page sizes translated 500system.cpu.itb.walker.walkPageSizes::1M 310 9.69% 100.00% # Table walker page sizes translated 501system.cpu.itb.walker.walkPageSizes::total 3199 # Table walker page sizes translated |
| 505system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 502system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 506system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5855 # Table walker requests started/completed, data/inst 507system.cpu.itb.walker.walkRequestOrigin_Requested::total 5855 # Table walker requests started/completed, data/inst | 503system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5836 # Table walker requests started/completed, data/inst 504system.cpu.itb.walker.walkRequestOrigin_Requested::total 5836 # Table walker requests started/completed, data/inst |
| 508system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 505system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 509system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3194 # Table walker requests started/completed, data/inst 510system.cpu.itb.walker.walkRequestOrigin_Completed::total 3194 # Table walker requests started/completed, data/inst 511system.cpu.itb.walker.walkRequestOrigin::total 9049 # Table walker requests started/completed, data/inst 512system.cpu.itb.inst_hits 57481594 # ITB inst hits 513system.cpu.itb.inst_misses 5855 # ITB inst misses | 506system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3199 # Table walker requests started/completed, data/inst 507system.cpu.itb.walker.walkRequestOrigin_Completed::total 3199 # Table walker requests started/completed, data/inst 508system.cpu.itb.walker.walkRequestOrigin::total 9035 # Table walker requests started/completed, data/inst 509system.cpu.itb.inst_hits 57468050 # ITB inst hits 510system.cpu.itb.inst_misses 5836 # ITB inst misses |
| 514system.cpu.itb.read_hits 0 # DTB read hits 515system.cpu.itb.read_misses 0 # DTB read misses 516system.cpu.itb.write_hits 0 # DTB write hits 517system.cpu.itb.write_misses 0 # DTB write misses 518system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 519system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 520system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 521system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 511system.cpu.itb.read_hits 0 # DTB read hits 512system.cpu.itb.read_misses 0 # DTB read misses 513system.cpu.itb.write_hits 0 # DTB write hits 514system.cpu.itb.write_misses 0 # DTB write misses 515system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 516system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 517system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 518system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 522system.cpu.itb.flush_entries 2915 # Number of entries that have been flushed from TLB | 519system.cpu.itb.flush_entries 2922 # Number of entries that have been flushed from TLB |
| 523system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 524system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 525system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 520system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 521system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 522system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 526system.cpu.itb.perms_faults 8308 # Number of TLB faults due to permissions restrictions | 523system.cpu.itb.perms_faults 8340 # Number of TLB faults due to permissions restrictions |
| 527system.cpu.itb.read_accesses 0 # DTB read accesses 528system.cpu.itb.write_accesses 0 # DTB write accesses | 524system.cpu.itb.read_accesses 0 # DTB read accesses 525system.cpu.itb.write_accesses 0 # DTB write accesses |
| 529system.cpu.itb.inst_accesses 57487449 # ITB inst accesses 530system.cpu.itb.hits 57481594 # DTB hits 531system.cpu.itb.misses 5855 # DTB misses 532system.cpu.itb.accesses 57487449 # DTB accesses | 526system.cpu.itb.inst_accesses 57473886 # ITB inst accesses 527system.cpu.itb.hits 57468050 # DTB hits 528system.cpu.itb.misses 5836 # DTB misses 529system.cpu.itb.accesses 57473886 # DTB accesses |
| 533system.cpu.numPwrStateTransitions 6066 # Number of power state transitions 534system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state | 530system.cpu.numPwrStateTransitions 6066 # Number of power state transitions 531system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state |
| 535system.cpu.pwrStateClkGateDist::mean 887934091.386746 # Distribution of time spent in the clock gated state 536system.cpu.pwrStateClkGateDist::stdev 17437787888.707882 # Distribution of time spent in the clock gated state | 532system.cpu.pwrStateClkGateDist::mean 887944293.276624 # Distribution of time spent in the clock gated state 533system.cpu.pwrStateClkGateDist::stdev 17437791477.805088 # Distribution of time spent in the clock gated state |
| 537system.cpu.pwrStateClkGateDist::underflows 2968 97.86% 97.86% # Distribution of time spent in the clock gated state 538system.cpu.pwrStateClkGateDist::1000-5e+10 59 1.95% 99.80% # Distribution of time spent in the clock gated state 539system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 540system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state 541system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state 542system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 543system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state | 534system.cpu.pwrStateClkGateDist::underflows 2968 97.86% 97.86% # Distribution of time spent in the clock gated state 535system.cpu.pwrStateClkGateDist::1000-5e+10 59 1.95% 99.80% # Distribution of time spent in the clock gated state 536system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 537system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state 538system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state 539system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 540system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state |
| 544system.cpu.pwrStateClkGateDist::max_value 499966196768 # Distribution of time spent in the clock gated state | 541system.cpu.pwrStateClkGateDist::max_value 499966835544 # Distribution of time spent in the clock gated state |
| 545system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state | 542system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state |
| 546system.cpu.pwrStateResidencyTicks::ON 161821897324 # Cumulative time (in ticks) in various power states 547system.cpu.pwrStateResidencyTicks::CLK_GATED 2693104099176 # Cumulative time (in ticks) in various power states 548system.cpu.numCycles 323646748 # number of cpu cycles simulated | 543system.cpu.pwrStateResidencyTicks::ON 161751090992 # Cumulative time (in ticks) in various power states 544system.cpu.pwrStateResidencyTicks::CLK_GATED 2693135041508 # Cumulative time (in ticks) in various power states 545system.cpu.numCycles 323505132 # number of cpu cycles simulated |
| 549system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 550system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 546system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 547system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 551system.cpu.committedInsts 112020669 # Number of instructions committed 552system.cpu.committedOps 135443008 # Number of ops (including micro ops) committed 553system.cpu.discardedOps 7814596 # Number of ops (including micro ops) which were discarded before commit | 548system.cpu.committedInsts 111784531 # Number of instructions committed 549system.cpu.committedOps 135154718 # Number of ops (including micro ops) committed 550system.cpu.discardedOps 7776689 # Number of ops (including micro ops) which were discarded before commit |
| 554system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching | 551system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching |
| 555system.cpu.quiesceCycles 5386269471 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 556system.cpu.cpi 2.889170 # CPI: cycles per instruction 557system.cpu.ipc 0.346120 # IPC: instructions per cycle | 552system.cpu.quiesceCycles 5386331427 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 553system.cpu.cpi 2.894006 # CPI: cycles per instruction 554system.cpu.ipc 0.345542 # IPC: instructions per cycle |
| 558system.cpu.op_class_0::No_OpClass 2337 0.00% 0.00% # Class of committed instruction | 555system.cpu.op_class_0::No_OpClass 2337 0.00% 0.00% # Class of committed instruction |
| 559system.cpu.op_class_0::IntAlu 90804901 67.04% 67.04% # Class of committed instruction 560system.cpu.op_class_0::IntMult 113201 0.08% 67.13% # Class of committed instruction 561system.cpu.op_class_0::IntDiv 0 0.00% 67.13% # Class of committed instruction 562system.cpu.op_class_0::FloatAdd 0 0.00% 67.13% # Class of committed instruction 563system.cpu.op_class_0::FloatCmp 0 0.00% 67.13% # Class of committed instruction 564system.cpu.op_class_0::FloatCvt 0 0.00% 67.13% # Class of committed instruction 565system.cpu.op_class_0::FloatMult 0 0.00% 67.13% # Class of committed instruction 566system.cpu.op_class_0::FloatMultAcc 0 0.00% 67.13% # Class of committed instruction 567system.cpu.op_class_0::FloatDiv 0 0.00% 67.13% # Class of committed instruction 568system.cpu.op_class_0::FloatMisc 0 0.00% 67.13% # Class of committed instruction 569system.cpu.op_class_0::FloatSqrt 0 0.00% 67.13% # Class of committed instruction 570system.cpu.op_class_0::SimdAdd 0 0.00% 67.13% # Class of committed instruction 571system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.13% # Class of committed instruction 572system.cpu.op_class_0::SimdAlu 0 0.00% 67.13% # Class of committed instruction 573system.cpu.op_class_0::SimdCmp 0 0.00% 67.13% # Class of committed instruction 574system.cpu.op_class_0::SimdCvt 0 0.00% 67.13% # Class of committed instruction 575system.cpu.op_class_0::SimdMisc 0 0.00% 67.13% # Class of committed instruction 576system.cpu.op_class_0::SimdMult 0 0.00% 67.13% # Class of committed instruction 577system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.13% # Class of committed instruction 578system.cpu.op_class_0::SimdShift 0 0.00% 67.13% # Class of committed instruction 579system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.13% # Class of committed instruction 580system.cpu.op_class_0::SimdSqrt 0 0.00% 67.13% # Class of committed instruction 581system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.13% # Class of committed instruction 582system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.13% # Class of committed instruction 583system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.13% # Class of committed instruction 584system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.13% # Class of committed instruction 585system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.13% # Class of committed instruction 586system.cpu.op_class_0::SimdFloatMisc 8481 0.01% 67.13% # Class of committed instruction 587system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.13% # Class of committed instruction 588system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.13% # Class of committed instruction 589system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.13% # Class of committed instruction 590system.cpu.op_class_0::MemRead 24247912 17.90% 85.04% # Class of committed instruction 591system.cpu.op_class_0::MemWrite 20254880 14.95% 99.99% # Class of committed instruction | 556system.cpu.op_class_0::IntAlu 90595549 67.03% 67.03% # Class of committed instruction 557system.cpu.op_class_0::IntMult 113150 0.08% 67.12% # Class of committed instruction 558system.cpu.op_class_0::IntDiv 0 0.00% 67.12% # Class of committed instruction 559system.cpu.op_class_0::FloatAdd 0 0.00% 67.12% # Class of committed instruction 560system.cpu.op_class_0::FloatCmp 0 0.00% 67.12% # Class of committed instruction 561system.cpu.op_class_0::FloatCvt 0 0.00% 67.12% # Class of committed instruction 562system.cpu.op_class_0::FloatMult 0 0.00% 67.12% # Class of committed instruction 563system.cpu.op_class_0::FloatMultAcc 0 0.00% 67.12% # Class of committed instruction 564system.cpu.op_class_0::FloatDiv 0 0.00% 67.12% # Class of committed instruction 565system.cpu.op_class_0::FloatMisc 0 0.00% 67.12% # Class of committed instruction 566system.cpu.op_class_0::FloatSqrt 0 0.00% 67.12% # Class of committed instruction 567system.cpu.op_class_0::SimdAdd 0 0.00% 67.12% # Class of committed instruction 568system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.12% # Class of committed instruction 569system.cpu.op_class_0::SimdAlu 0 0.00% 67.12% # Class of committed instruction 570system.cpu.op_class_0::SimdCmp 0 0.00% 67.12% # Class of committed instruction 571system.cpu.op_class_0::SimdCvt 0 0.00% 67.12% # Class of committed instruction 572system.cpu.op_class_0::SimdMisc 0 0.00% 67.12% # Class of committed instruction 573system.cpu.op_class_0::SimdMult 0 0.00% 67.12% # Class of committed instruction 574system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.12% # Class of committed instruction 575system.cpu.op_class_0::SimdShift 0 0.00% 67.12% # Class of committed instruction 576system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.12% # Class of committed instruction 577system.cpu.op_class_0::SimdSqrt 0 0.00% 67.12% # Class of committed instruction 578system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.12% # Class of committed instruction 579system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.12% # Class of committed instruction 580system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.12% # Class of committed instruction 581system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.12% # Class of committed instruction 582system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.12% # Class of committed instruction 583system.cpu.op_class_0::SimdFloatMisc 8471 0.01% 67.12% # Class of committed instruction 584system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.12% # Class of committed instruction 585system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.12% # Class of committed instruction 586system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.12% # Class of committed instruction 587system.cpu.op_class_0::MemRead 24195627 17.90% 85.02% # Class of committed instruction 588system.cpu.op_class_0::MemWrite 20228352 14.97% 99.99% # Class of committed instruction |
| 592system.cpu.op_class_0::FloatMemRead 2708 0.00% 99.99% # Class of committed instruction | 589system.cpu.op_class_0::FloatMemRead 2708 0.00% 99.99% # Class of committed instruction |
| 593system.cpu.op_class_0::FloatMemWrite 8588 0.01% 100.00% # Class of committed instruction | 590system.cpu.op_class_0::FloatMemWrite 8524 0.01% 100.00% # Class of committed instruction |
| 594system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 595system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 591system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 592system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 596system.cpu.op_class_0::total 135443008 # Class of committed instruction | 593system.cpu.op_class_0::total 135154718 # Class of committed instruction |
| 597system.cpu.kern.inst.arm 0 # number of arm instructions executed 598system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed | 594system.cpu.kern.inst.arm 0 # number of arm instructions executed 595system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed |
| 599system.cpu.tickCycles 217947056 # Number of cycles that the object actually ticked 600system.cpu.idleCycles 105699692 # Total number of cycles that the object has spent stopped 601system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 602system.cpu.dcache.tags.replacements 844723 # number of replacements 603system.cpu.dcache.tags.tagsinuse 511.945160 # Cycle average of tags in use 604system.cpu.dcache.tags.total_refs 42637807 # Total number of references to valid blocks. 605system.cpu.dcache.tags.sampled_refs 845235 # Sample count of references to valid blocks. 606system.cpu.dcache.tags.avg_refs 50.444914 # Average number of references to valid blocks. | 596system.cpu.tickCycles 217865051 # Number of cycles that the object actually ticked 597system.cpu.idleCycles 105640081 # Total number of cycles that the object has spent stopped 598system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 599system.cpu.dcache.tags.replacements 843791 # number of replacements 600system.cpu.dcache.tags.tagsinuse 511.945118 # Cycle average of tags in use 601system.cpu.dcache.tags.total_refs 42554576 # Total number of references to valid blocks. 602system.cpu.dcache.tags.sampled_refs 844303 # Sample count of references to valid blocks. 603system.cpu.dcache.tags.avg_refs 50.402019 # Average number of references to valid blocks. |
| 607system.cpu.dcache.tags.warmup_cycle 330588500 # Cycle when the warmup percentage was hit. | 604system.cpu.dcache.tags.warmup_cycle 330588500 # Cycle when the warmup percentage was hit. |
| 608system.cpu.dcache.tags.occ_blocks::cpu.data 511.945160 # Average occupied blocks per requestor | 605system.cpu.dcache.tags.occ_blocks::cpu.data 511.945118 # Average occupied blocks per requestor |
| 609system.cpu.dcache.tags.occ_percent::cpu.data 0.999893 # Average percentage of cache occupancy 610system.cpu.dcache.tags.occ_percent::total 0.999893 # Average percentage of cache occupancy 611system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 606system.cpu.dcache.tags.occ_percent::cpu.data 0.999893 # Average percentage of cache occupancy 607system.cpu.dcache.tags.occ_percent::total 0.999893 # Average percentage of cache occupancy 608system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 612system.cpu.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 613system.cpu.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id 614system.cpu.dcache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id | 609system.cpu.dcache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 610system.cpu.dcache.tags.age_task_id_blocks_1024::1 364 # Occupied blocks per task id 611system.cpu.dcache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id |
| 615system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 612system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 616system.cpu.dcache.tags.tag_accesses 176206878 # Number of tag accesses 617system.cpu.dcache.tags.data_accesses 176206878 # Number of data accesses 618system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 619system.cpu.dcache.ReadReq_hits::cpu.data 23101260 # number of ReadReq hits 620system.cpu.dcache.ReadReq_hits::total 23101260 # number of ReadReq hits 621system.cpu.dcache.WriteReq_hits::cpu.data 18273431 # number of WriteReq hits 622system.cpu.dcache.WriteReq_hits::total 18273431 # number of WriteReq hits 623system.cpu.dcache.SoftPFReq_hits::cpu.data 356861 # number of SoftPFReq hits 624system.cpu.dcache.SoftPFReq_hits::total 356861 # number of SoftPFReq hits 625system.cpu.dcache.LoadLockedReq_hits::cpu.data 443340 # number of LoadLockedReq hits 626system.cpu.dcache.LoadLockedReq_hits::total 443340 # number of LoadLockedReq hits 627system.cpu.dcache.StoreCondReq_hits::cpu.data 460050 # number of StoreCondReq hits 628system.cpu.dcache.StoreCondReq_hits::total 460050 # number of StoreCondReq hits 629system.cpu.dcache.demand_hits::cpu.data 41374691 # number of demand (read+write) hits 630system.cpu.dcache.demand_hits::total 41374691 # number of demand (read+write) hits 631system.cpu.dcache.overall_hits::cpu.data 41731552 # number of overall hits 632system.cpu.dcache.overall_hits::total 41731552 # number of overall hits 633system.cpu.dcache.ReadReq_misses::cpu.data 465078 # number of ReadReq misses 634system.cpu.dcache.ReadReq_misses::total 465078 # number of ReadReq misses 635system.cpu.dcache.WriteReq_misses::cpu.data 548776 # number of WriteReq misses 636system.cpu.dcache.WriteReq_misses::total 548776 # number of WriteReq misses 637system.cpu.dcache.SoftPFReq_misses::cpu.data 169103 # number of SoftPFReq misses 638system.cpu.dcache.SoftPFReq_misses::total 169103 # number of SoftPFReq misses 639system.cpu.dcache.LoadLockedReq_misses::cpu.data 22503 # number of LoadLockedReq misses 640system.cpu.dcache.LoadLockedReq_misses::total 22503 # number of LoadLockedReq misses | 613system.cpu.dcache.tags.tag_accesses 175868835 # Number of tag accesses 614system.cpu.dcache.tags.data_accesses 175868835 # Number of data accesses 615system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 616system.cpu.dcache.ReadReq_hits::cpu.data 23043762 # number of ReadReq hits 617system.cpu.dcache.ReadReq_hits::total 23043762 # number of ReadReq hits 618system.cpu.dcache.WriteReq_hits::cpu.data 18247268 # number of WriteReq hits 619system.cpu.dcache.WriteReq_hits::total 18247268 # number of WriteReq hits 620system.cpu.dcache.SoftPFReq_hits::cpu.data 357174 # number of SoftPFReq hits 621system.cpu.dcache.SoftPFReq_hits::total 357174 # number of SoftPFReq hits 622system.cpu.dcache.LoadLockedReq_hits::cpu.data 443432 # number of LoadLockedReq hits 623system.cpu.dcache.LoadLockedReq_hits::total 443432 # number of LoadLockedReq hits 624system.cpu.dcache.StoreCondReq_hits::cpu.data 460038 # number of StoreCondReq hits 625system.cpu.dcache.StoreCondReq_hits::total 460038 # number of StoreCondReq hits 626system.cpu.dcache.demand_hits::cpu.data 41291030 # number of demand (read+write) hits 627system.cpu.dcache.demand_hits::total 41291030 # number of demand (read+write) hits 628system.cpu.dcache.overall_hits::cpu.data 41648204 # number of overall hits 629system.cpu.dcache.overall_hits::total 41648204 # number of overall hits 630system.cpu.dcache.ReadReq_misses::cpu.data 465012 # number of ReadReq misses 631system.cpu.dcache.ReadReq_misses::total 465012 # number of ReadReq misses 632system.cpu.dcache.WriteReq_misses::cpu.data 548381 # number of WriteReq misses 633system.cpu.dcache.WriteReq_misses::total 548381 # number of WriteReq misses 634system.cpu.dcache.SoftPFReq_misses::cpu.data 168658 # number of SoftPFReq misses 635system.cpu.dcache.SoftPFReq_misses::total 168658 # number of SoftPFReq misses 636system.cpu.dcache.LoadLockedReq_misses::cpu.data 22398 # number of LoadLockedReq misses 637system.cpu.dcache.LoadLockedReq_misses::total 22398 # number of LoadLockedReq misses |
| 641system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 642system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses | 638system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 639system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses |
| 643system.cpu.dcache.demand_misses::cpu.data 1013854 # number of demand (read+write) misses 644system.cpu.dcache.demand_misses::total 1013854 # number of demand (read+write) misses 645system.cpu.dcache.overall_misses::cpu.data 1182957 # number of overall misses 646system.cpu.dcache.overall_misses::total 1182957 # number of overall misses 647system.cpu.dcache.ReadReq_miss_latency::cpu.data 7334484000 # number of ReadReq miss cycles 648system.cpu.dcache.ReadReq_miss_latency::total 7334484000 # number of ReadReq miss cycles 649system.cpu.dcache.WriteReq_miss_latency::cpu.data 26875060480 # number of WriteReq miss cycles 650system.cpu.dcache.WriteReq_miss_latency::total 26875060480 # number of WriteReq miss cycles 651system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306737000 # number of LoadLockedReq miss cycles 652system.cpu.dcache.LoadLockedReq_miss_latency::total 306737000 # number of LoadLockedReq miss cycles | 640system.cpu.dcache.demand_misses::cpu.data 1013393 # number of demand (read+write) misses 641system.cpu.dcache.demand_misses::total 1013393 # number of demand (read+write) misses 642system.cpu.dcache.overall_misses::cpu.data 1182051 # number of overall misses 643system.cpu.dcache.overall_misses::total 1182051 # number of overall misses 644system.cpu.dcache.ReadReq_miss_latency::cpu.data 7327923000 # number of ReadReq miss cycles 645system.cpu.dcache.ReadReq_miss_latency::total 7327923000 # number of ReadReq miss cycles 646system.cpu.dcache.WriteReq_miss_latency::cpu.data 26756956980 # number of WriteReq miss cycles 647system.cpu.dcache.WriteReq_miss_latency::total 26756956980 # number of WriteReq miss cycles 648system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306920500 # number of LoadLockedReq miss cycles 649system.cpu.dcache.LoadLockedReq_miss_latency::total 306920500 # number of LoadLockedReq miss cycles |
| 653system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 171000 # number of StoreCondReq miss cycles 654system.cpu.dcache.StoreCondReq_miss_latency::total 171000 # number of StoreCondReq miss cycles | 650system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 171000 # number of StoreCondReq miss cycles 651system.cpu.dcache.StoreCondReq_miss_latency::total 171000 # number of StoreCondReq miss cycles |
| 655system.cpu.dcache.demand_miss_latency::cpu.data 34209544480 # number of demand (read+write) miss cycles 656system.cpu.dcache.demand_miss_latency::total 34209544480 # number of demand (read+write) miss cycles 657system.cpu.dcache.overall_miss_latency::cpu.data 34209544480 # number of overall miss cycles 658system.cpu.dcache.overall_miss_latency::total 34209544480 # number of overall miss cycles 659system.cpu.dcache.ReadReq_accesses::cpu.data 23566338 # number of ReadReq accesses(hits+misses) 660system.cpu.dcache.ReadReq_accesses::total 23566338 # number of ReadReq accesses(hits+misses) 661system.cpu.dcache.WriteReq_accesses::cpu.data 18822207 # number of WriteReq accesses(hits+misses) 662system.cpu.dcache.WriteReq_accesses::total 18822207 # number of WriteReq accesses(hits+misses) 663system.cpu.dcache.SoftPFReq_accesses::cpu.data 525964 # number of SoftPFReq accesses(hits+misses) 664system.cpu.dcache.SoftPFReq_accesses::total 525964 # number of SoftPFReq accesses(hits+misses) 665system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465843 # number of LoadLockedReq accesses(hits+misses) 666system.cpu.dcache.LoadLockedReq_accesses::total 465843 # number of LoadLockedReq accesses(hits+misses) 667system.cpu.dcache.StoreCondReq_accesses::cpu.data 460052 # number of StoreCondReq accesses(hits+misses) 668system.cpu.dcache.StoreCondReq_accesses::total 460052 # number of StoreCondReq accesses(hits+misses) 669system.cpu.dcache.demand_accesses::cpu.data 42388545 # number of demand (read+write) accesses 670system.cpu.dcache.demand_accesses::total 42388545 # number of demand (read+write) accesses 671system.cpu.dcache.overall_accesses::cpu.data 42914509 # number of overall (read+write) accesses 672system.cpu.dcache.overall_accesses::total 42914509 # number of overall (read+write) accesses 673system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019735 # miss rate for ReadReq accesses 674system.cpu.dcache.ReadReq_miss_rate::total 0.019735 # miss rate for ReadReq accesses 675system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029156 # miss rate for WriteReq accesses 676system.cpu.dcache.WriteReq_miss_rate::total 0.029156 # miss rate for WriteReq accesses 677system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.321511 # miss rate for SoftPFReq accesses 678system.cpu.dcache.SoftPFReq_miss_rate::total 0.321511 # miss rate for SoftPFReq accesses 679system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048306 # miss rate for LoadLockedReq accesses 680system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048306 # miss rate for LoadLockedReq accesses | 652system.cpu.dcache.demand_miss_latency::cpu.data 34084879980 # number of demand (read+write) miss cycles 653system.cpu.dcache.demand_miss_latency::total 34084879980 # number of demand (read+write) miss cycles 654system.cpu.dcache.overall_miss_latency::cpu.data 34084879980 # number of overall miss cycles 655system.cpu.dcache.overall_miss_latency::total 34084879980 # number of overall miss cycles 656system.cpu.dcache.ReadReq_accesses::cpu.data 23508774 # number of ReadReq accesses(hits+misses) 657system.cpu.dcache.ReadReq_accesses::total 23508774 # number of ReadReq accesses(hits+misses) 658system.cpu.dcache.WriteReq_accesses::cpu.data 18795649 # number of WriteReq accesses(hits+misses) 659system.cpu.dcache.WriteReq_accesses::total 18795649 # number of WriteReq accesses(hits+misses) 660system.cpu.dcache.SoftPFReq_accesses::cpu.data 525832 # number of SoftPFReq accesses(hits+misses) 661system.cpu.dcache.SoftPFReq_accesses::total 525832 # number of SoftPFReq accesses(hits+misses) 662system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465830 # number of LoadLockedReq accesses(hits+misses) 663system.cpu.dcache.LoadLockedReq_accesses::total 465830 # number of LoadLockedReq accesses(hits+misses) 664system.cpu.dcache.StoreCondReq_accesses::cpu.data 460040 # number of StoreCondReq accesses(hits+misses) 665system.cpu.dcache.StoreCondReq_accesses::total 460040 # number of StoreCondReq accesses(hits+misses) 666system.cpu.dcache.demand_accesses::cpu.data 42304423 # number of demand (read+write) accesses 667system.cpu.dcache.demand_accesses::total 42304423 # number of demand (read+write) accesses 668system.cpu.dcache.overall_accesses::cpu.data 42830255 # number of overall (read+write) accesses 669system.cpu.dcache.overall_accesses::total 42830255 # number of overall (read+write) accesses 670system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019780 # miss rate for ReadReq accesses 671system.cpu.dcache.ReadReq_miss_rate::total 0.019780 # miss rate for ReadReq accesses 672system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029176 # miss rate for WriteReq accesses 673system.cpu.dcache.WriteReq_miss_rate::total 0.029176 # miss rate for WriteReq accesses 674system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.320745 # miss rate for SoftPFReq accesses 675system.cpu.dcache.SoftPFReq_miss_rate::total 0.320745 # miss rate for SoftPFReq accesses 676system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048082 # miss rate for LoadLockedReq accesses 677system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048082 # miss rate for LoadLockedReq accesses |
| 681system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 682system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses | 678system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 679system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses |
| 683system.cpu.dcache.demand_miss_rate::cpu.data 0.023918 # miss rate for demand accesses 684system.cpu.dcache.demand_miss_rate::total 0.023918 # miss rate for demand accesses 685system.cpu.dcache.overall_miss_rate::cpu.data 0.027565 # miss rate for overall accesses 686system.cpu.dcache.overall_miss_rate::total 0.027565 # miss rate for overall accesses 687system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15770.438507 # average ReadReq miss latency 688system.cpu.dcache.ReadReq_avg_miss_latency::total 15770.438507 # average ReadReq miss latency 689system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48972.732918 # average WriteReq miss latency 690system.cpu.dcache.WriteReq_avg_miss_latency::total 48972.732918 # average WriteReq miss latency 691system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13630.938097 # average LoadLockedReq miss latency 692system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13630.938097 # average LoadLockedReq miss latency | 680system.cpu.dcache.demand_miss_rate::cpu.data 0.023955 # miss rate for demand accesses 681system.cpu.dcache.demand_miss_rate::total 0.023955 # miss rate for demand accesses 682system.cpu.dcache.overall_miss_rate::cpu.data 0.027599 # miss rate for overall accesses 683system.cpu.dcache.overall_miss_rate::total 0.027599 # miss rate for overall accesses 684system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15758.567521 # average ReadReq miss latency 685system.cpu.dcache.ReadReq_avg_miss_latency::total 15758.567521 # average ReadReq miss latency 686system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48792.640482 # average WriteReq miss latency 687system.cpu.dcache.WriteReq_avg_miss_latency::total 48792.640482 # average WriteReq miss latency 688system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13703.031521 # average LoadLockedReq miss latency 689system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13703.031521 # average LoadLockedReq miss latency |
| 693system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 85500 # average StoreCondReq miss latency 694system.cpu.dcache.StoreCondReq_avg_miss_latency::total 85500 # average StoreCondReq miss latency | 690system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 85500 # average StoreCondReq miss latency 691system.cpu.dcache.StoreCondReq_avg_miss_latency::total 85500 # average StoreCondReq miss latency |
| 695system.cpu.dcache.demand_avg_miss_latency::cpu.data 33742.081680 # average overall miss latency 696system.cpu.dcache.demand_avg_miss_latency::total 33742.081680 # average overall miss latency 697system.cpu.dcache.overall_avg_miss_latency::cpu.data 28918.671160 # average overall miss latency 698system.cpu.dcache.overall_avg_miss_latency::total 28918.671160 # average overall miss latency 699system.cpu.dcache.blocked_cycles::no_mshrs 224 # number of cycles access was blocked | 692system.cpu.dcache.demand_avg_miss_latency::cpu.data 33634.414270 # average overall miss latency 693system.cpu.dcache.demand_avg_miss_latency::total 33634.414270 # average overall miss latency 694system.cpu.dcache.overall_avg_miss_latency::cpu.data 28835.371723 # average overall miss latency 695system.cpu.dcache.overall_avg_miss_latency::total 28835.371723 # average overall miss latency 696system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked |
| 700system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 701system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked 702system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 697system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 698system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked 699system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 703system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.666667 # average number of cycles each access was blocked | 700system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.571429 # average number of cycles each access was blocked |
| 704system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 701system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 705system.cpu.dcache.writebacks::writebacks 702249 # number of writebacks 706system.cpu.dcache.writebacks::total 702249 # number of writebacks 707system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45641 # number of ReadReq MSHR hits 708system.cpu.dcache.ReadReq_mshr_hits::total 45641 # number of ReadReq MSHR hits 709system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249535 # number of WriteReq MSHR hits 710system.cpu.dcache.WriteReq_mshr_hits::total 249535 # number of WriteReq MSHR hits 711system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14278 # number of LoadLockedReq MSHR hits 712system.cpu.dcache.LoadLockedReq_mshr_hits::total 14278 # number of LoadLockedReq MSHR hits 713system.cpu.dcache.demand_mshr_hits::cpu.data 295176 # number of demand (read+write) MSHR hits 714system.cpu.dcache.demand_mshr_hits::total 295176 # number of demand (read+write) MSHR hits 715system.cpu.dcache.overall_mshr_hits::cpu.data 295176 # number of overall MSHR hits 716system.cpu.dcache.overall_mshr_hits::total 295176 # number of overall MSHR hits 717system.cpu.dcache.ReadReq_mshr_misses::cpu.data 419437 # number of ReadReq MSHR misses 718system.cpu.dcache.ReadReq_mshr_misses::total 419437 # number of ReadReq MSHR misses 719system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299241 # number of WriteReq MSHR misses 720system.cpu.dcache.WriteReq_mshr_misses::total 299241 # number of WriteReq MSHR misses 721system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121149 # number of SoftPFReq MSHR misses 722system.cpu.dcache.SoftPFReq_mshr_misses::total 121149 # number of SoftPFReq MSHR misses 723system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8225 # number of LoadLockedReq MSHR misses 724system.cpu.dcache.LoadLockedReq_mshr_misses::total 8225 # number of LoadLockedReq MSHR misses | 702system.cpu.dcache.writebacks::writebacks 701301 # number of writebacks 703system.cpu.dcache.writebacks::total 701301 # number of writebacks 704system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45802 # number of ReadReq MSHR hits 705system.cpu.dcache.ReadReq_mshr_hits::total 45802 # number of ReadReq MSHR hits 706system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249489 # number of WriteReq MSHR hits 707system.cpu.dcache.WriteReq_mshr_hits::total 249489 # number of WriteReq MSHR hits 708system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14157 # number of LoadLockedReq MSHR hits 709system.cpu.dcache.LoadLockedReq_mshr_hits::total 14157 # number of LoadLockedReq MSHR hits 710system.cpu.dcache.demand_mshr_hits::cpu.data 295291 # number of demand (read+write) MSHR hits 711system.cpu.dcache.demand_mshr_hits::total 295291 # number of demand (read+write) MSHR hits 712system.cpu.dcache.overall_mshr_hits::cpu.data 295291 # number of overall MSHR hits 713system.cpu.dcache.overall_mshr_hits::total 295291 # number of overall MSHR hits 714system.cpu.dcache.ReadReq_mshr_misses::cpu.data 419210 # number of ReadReq MSHR misses 715system.cpu.dcache.ReadReq_mshr_misses::total 419210 # number of ReadReq MSHR misses 716system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298892 # number of WriteReq MSHR misses 717system.cpu.dcache.WriteReq_mshr_misses::total 298892 # number of WriteReq MSHR misses 718system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 120813 # number of SoftPFReq MSHR misses 719system.cpu.dcache.SoftPFReq_mshr_misses::total 120813 # number of SoftPFReq MSHR misses 720system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8241 # number of LoadLockedReq MSHR misses 721system.cpu.dcache.LoadLockedReq_mshr_misses::total 8241 # number of LoadLockedReq MSHR misses |
| 725system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 726system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses | 722system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 723system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses |
| 727system.cpu.dcache.demand_mshr_misses::cpu.data 718678 # number of demand (read+write) MSHR misses 728system.cpu.dcache.demand_mshr_misses::total 718678 # number of demand (read+write) MSHR misses 729system.cpu.dcache.overall_mshr_misses::cpu.data 839827 # number of overall MSHR misses 730system.cpu.dcache.overall_mshr_misses::total 839827 # number of overall MSHR misses | 724system.cpu.dcache.demand_mshr_misses::cpu.data 718102 # number of demand (read+write) MSHR misses 725system.cpu.dcache.demand_mshr_misses::total 718102 # number of demand (read+write) MSHR misses 726system.cpu.dcache.overall_mshr_misses::cpu.data 838915 # number of overall MSHR misses 727system.cpu.dcache.overall_mshr_misses::total 838915 # number of overall MSHR misses |
| 731system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable 732system.cpu.dcache.ReadReq_mshr_uncacheable::total 31130 # number of ReadReq MSHR uncacheable 733system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable 734system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable 735system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 736system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses | 728system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable 729system.cpu.dcache.ReadReq_mshr_uncacheable::total 31130 # number of ReadReq MSHR uncacheable 730system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable 731system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable 732system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 733system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses |
| 737system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447841000 # number of ReadReq MSHR miss cycles 738system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447841000 # number of ReadReq MSHR miss cycles 739system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14303453000 # number of WriteReq MSHR miss cycles 740system.cpu.dcache.WriteReq_mshr_miss_latency::total 14303453000 # number of WriteReq MSHR miss cycles 741system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1653166500 # number of SoftPFReq MSHR miss cycles 742system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1653166500 # number of SoftPFReq MSHR miss cycles 743system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 121747500 # number of LoadLockedReq MSHR miss cycles 744system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 121747500 # number of LoadLockedReq MSHR miss cycles | 734system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6438741500 # number of ReadReq MSHR miss cycles 735system.cpu.dcache.ReadReq_mshr_miss_latency::total 6438741500 # number of ReadReq MSHR miss cycles 736system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14235579000 # number of WriteReq MSHR miss cycles 737system.cpu.dcache.WriteReq_mshr_miss_latency::total 14235579000 # number of WriteReq MSHR miss cycles 738system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1652909500 # number of SoftPFReq MSHR miss cycles 739system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1652909500 # number of SoftPFReq MSHR miss cycles 740system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 122323000 # number of LoadLockedReq MSHR miss cycles 741system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 122323000 # number of LoadLockedReq MSHR miss cycles |
| 745system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169000 # number of StoreCondReq MSHR miss cycles 746system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169000 # number of StoreCondReq MSHR miss cycles | 742system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169000 # number of StoreCondReq MSHR miss cycles 743system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169000 # number of StoreCondReq MSHR miss cycles |
| 747system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20751294000 # number of demand (read+write) MSHR miss cycles 748system.cpu.dcache.demand_mshr_miss_latency::total 20751294000 # number of demand (read+write) MSHR miss cycles 749system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22404460500 # number of overall MSHR miss cycles 750system.cpu.dcache.overall_mshr_miss_latency::total 22404460500 # number of overall MSHR miss cycles 751system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6305636000 # number of ReadReq MSHR uncacheable cycles 752system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6305636000 # number of ReadReq MSHR uncacheable cycles 753system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6305636000 # number of overall MSHR uncacheable cycles 754system.cpu.dcache.overall_mshr_uncacheable_latency::total 6305636000 # number of overall MSHR uncacheable cycles 755system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017798 # mshr miss rate for ReadReq accesses 756system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017798 # mshr miss rate for ReadReq accesses 757system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015898 # mshr miss rate for WriteReq accesses 758system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015898 # mshr miss rate for WriteReq accesses 759system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230337 # mshr miss rate for SoftPFReq accesses 760system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230337 # mshr miss rate for SoftPFReq accesses 761system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017656 # mshr miss rate for LoadLockedReq accesses 762system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017656 # mshr miss rate for LoadLockedReq accesses | 744system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20674320500 # number of demand (read+write) MSHR miss cycles 745system.cpu.dcache.demand_mshr_miss_latency::total 20674320500 # number of demand (read+write) MSHR miss cycles 746system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22327230000 # number of overall MSHR miss cycles 747system.cpu.dcache.overall_mshr_miss_latency::total 22327230000 # number of overall MSHR miss cycles 748system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6305432000 # number of ReadReq MSHR uncacheable cycles 749system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6305432000 # number of ReadReq MSHR uncacheable cycles 750system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6305432000 # number of overall MSHR uncacheable cycles 751system.cpu.dcache.overall_mshr_uncacheable_latency::total 6305432000 # number of overall MSHR uncacheable cycles 752system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017832 # mshr miss rate for ReadReq accesses 753system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017832 # mshr miss rate for ReadReq accesses 754system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for WriteReq accesses 755system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015902 # mshr miss rate for WriteReq accesses 756system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.229756 # mshr miss rate for SoftPFReq accesses 757system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.229756 # mshr miss rate for SoftPFReq accesses 758system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017691 # mshr miss rate for LoadLockedReq accesses 759system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017691 # mshr miss rate for LoadLockedReq accesses |
| 763system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 764system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses | 760system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 761system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses |
| 765system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016955 # mshr miss rate for demand accesses 766system.cpu.dcache.demand_mshr_miss_rate::total 0.016955 # mshr miss rate for demand accesses 767system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019570 # mshr miss rate for overall accesses 768system.cpu.dcache.overall_mshr_miss_rate::total 0.019570 # mshr miss rate for overall accesses 769system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15372.608997 # average ReadReq mshr miss latency 770system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15372.608997 # average ReadReq mshr miss latency 771system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47799.108411 # average WriteReq mshr miss latency 772system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47799.108411 # average WriteReq mshr miss latency 773system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13645.729639 # average SoftPFReq mshr miss latency 774system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13645.729639 # average SoftPFReq mshr miss latency 775system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14802.127660 # average LoadLockedReq mshr miss latency 776system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14802.127660 # average LoadLockedReq mshr miss latency | 762system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016975 # mshr miss rate for demand accesses 763system.cpu.dcache.demand_mshr_miss_rate::total 0.016975 # mshr miss rate for demand accesses 764system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019587 # mshr miss rate for overall accesses 765system.cpu.dcache.overall_mshr_miss_rate::total 0.019587 # mshr miss rate for overall accesses 766system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15359.226879 # average ReadReq mshr miss latency 767system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15359.226879 # average ReadReq mshr miss latency 768system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47627.835472 # average WriteReq mshr miss latency 769system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47627.835472 # average WriteReq mshr miss latency 770system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13681.553310 # average SoftPFReq mshr miss latency 771system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13681.553310 # average SoftPFReq mshr miss latency 772system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14843.222910 # average LoadLockedReq mshr miss latency 773system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14843.222910 # average LoadLockedReq mshr miss latency |
| 777system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 84500 # average StoreCondReq mshr miss latency 778system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 84500 # average StoreCondReq mshr miss latency | 774system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 84500 # average StoreCondReq mshr miss latency 775system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 84500 # average StoreCondReq mshr miss latency |
| 779system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28874.258013 # average overall mshr miss latency 780system.cpu.dcache.demand_avg_mshr_miss_latency::total 28874.258013 # average overall mshr miss latency 781system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26677.471074 # average overall mshr miss latency 782system.cpu.dcache.overall_avg_mshr_miss_latency::total 26677.471074 # average overall mshr miss latency 783system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202558.175394 # average ReadReq mshr uncacheable latency 784system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202558.175394 # average ReadReq mshr uncacheable latency 785system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107395.782948 # average overall mshr uncacheable latency 786system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107395.782948 # average overall mshr uncacheable latency 787system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 788system.cpu.icache.tags.replacements 2891615 # number of replacements 789system.cpu.icache.tags.tagsinuse 511.370867 # Cycle average of tags in use 790system.cpu.icache.tags.total_refs 54580851 # Total number of references to valid blocks. 791system.cpu.icache.tags.sampled_refs 2892127 # Sample count of references to valid blocks. 792system.cpu.icache.tags.avg_refs 18.872218 # Average number of references to valid blocks. 793system.cpu.icache.tags.warmup_cycle 16116545500 # Cycle when the warmup percentage was hit. 794system.cpu.icache.tags.occ_blocks::cpu.inst 511.370867 # Average occupied blocks per requestor | 776system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28790.228268 # average overall mshr miss latency 777system.cpu.dcache.demand_avg_mshr_miss_latency::total 28790.228268 # average overall mshr miss latency 778system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26614.412664 # average overall mshr miss latency 779system.cpu.dcache.overall_avg_mshr_miss_latency::total 26614.412664 # average overall mshr miss latency 780system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202551.622229 # average ReadReq mshr uncacheable latency 781system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202551.622229 # average ReadReq mshr uncacheable latency 782system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107392.308478 # average overall mshr uncacheable latency 783system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107392.308478 # average overall mshr uncacheable latency 784system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 785system.cpu.icache.tags.replacements 2889413 # number of replacements 786system.cpu.icache.tags.tagsinuse 511.370681 # Cycle average of tags in use 787system.cpu.icache.tags.total_refs 54569461 # Total number of references to valid blocks. 788system.cpu.icache.tags.sampled_refs 2889925 # Sample count of references to valid blocks. 789system.cpu.icache.tags.avg_refs 18.882656 # Average number of references to valid blocks. 790system.cpu.icache.tags.warmup_cycle 16116553500 # Cycle when the warmup percentage was hit. 791system.cpu.icache.tags.occ_blocks::cpu.inst 511.370681 # Average occupied blocks per requestor |
| 795system.cpu.icache.tags.occ_percent::cpu.inst 0.998771 # Average percentage of cache occupancy 796system.cpu.icache.tags.occ_percent::total 0.998771 # Average percentage of cache occupancy 797system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 792system.cpu.icache.tags.occ_percent::cpu.inst 0.998771 # Average percentage of cache occupancy 793system.cpu.icache.tags.occ_percent::total 0.998771 # Average percentage of cache occupancy 794system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 798system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id 799system.cpu.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id 800system.cpu.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id | 795system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 796system.cpu.icache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id 797system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id |
| 801system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 798system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 802system.cpu.icache.tags.tag_accesses 60365128 # Number of tag accesses 803system.cpu.icache.tags.data_accesses 60365128 # Number of data accesses 804system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 805system.cpu.icache.ReadReq_hits::cpu.inst 54580851 # number of ReadReq hits 806system.cpu.icache.ReadReq_hits::total 54580851 # number of ReadReq hits 807system.cpu.icache.demand_hits::cpu.inst 54580851 # number of demand (read+write) hits 808system.cpu.icache.demand_hits::total 54580851 # number of demand (read+write) hits 809system.cpu.icache.overall_hits::cpu.inst 54580851 # number of overall hits 810system.cpu.icache.overall_hits::total 54580851 # number of overall hits 811system.cpu.icache.ReadReq_misses::cpu.inst 2892139 # number of ReadReq misses 812system.cpu.icache.ReadReq_misses::total 2892139 # number of ReadReq misses 813system.cpu.icache.demand_misses::cpu.inst 2892139 # number of demand (read+write) misses 814system.cpu.icache.demand_misses::total 2892139 # number of demand (read+write) misses 815system.cpu.icache.overall_misses::cpu.inst 2892139 # number of overall misses 816system.cpu.icache.overall_misses::total 2892139 # number of overall misses 817system.cpu.icache.ReadReq_miss_latency::cpu.inst 39804335500 # number of ReadReq miss cycles 818system.cpu.icache.ReadReq_miss_latency::total 39804335500 # number of ReadReq miss cycles 819system.cpu.icache.demand_miss_latency::cpu.inst 39804335500 # number of demand (read+write) miss cycles 820system.cpu.icache.demand_miss_latency::total 39804335500 # number of demand (read+write) miss cycles 821system.cpu.icache.overall_miss_latency::cpu.inst 39804335500 # number of overall miss cycles 822system.cpu.icache.overall_miss_latency::total 39804335500 # number of overall miss cycles 823system.cpu.icache.ReadReq_accesses::cpu.inst 57472990 # number of ReadReq accesses(hits+misses) 824system.cpu.icache.ReadReq_accesses::total 57472990 # number of ReadReq accesses(hits+misses) 825system.cpu.icache.demand_accesses::cpu.inst 57472990 # number of demand (read+write) accesses 826system.cpu.icache.demand_accesses::total 57472990 # number of demand (read+write) accesses 827system.cpu.icache.overall_accesses::cpu.inst 57472990 # number of overall (read+write) accesses 828system.cpu.icache.overall_accesses::total 57472990 # number of overall (read+write) accesses 829system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050322 # miss rate for ReadReq accesses 830system.cpu.icache.ReadReq_miss_rate::total 0.050322 # miss rate for ReadReq accesses 831system.cpu.icache.demand_miss_rate::cpu.inst 0.050322 # miss rate for demand accesses 832system.cpu.icache.demand_miss_rate::total 0.050322 # miss rate for demand accesses 833system.cpu.icache.overall_miss_rate::cpu.inst 0.050322 # miss rate for overall accesses 834system.cpu.icache.overall_miss_rate::total 0.050322 # miss rate for overall accesses 835system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13762.939990 # average ReadReq miss latency 836system.cpu.icache.ReadReq_avg_miss_latency::total 13762.939990 # average ReadReq miss latency 837system.cpu.icache.demand_avg_miss_latency::cpu.inst 13762.939990 # average overall miss latency 838system.cpu.icache.demand_avg_miss_latency::total 13762.939990 # average overall miss latency 839system.cpu.icache.overall_avg_miss_latency::cpu.inst 13762.939990 # average overall miss latency 840system.cpu.icache.overall_avg_miss_latency::total 13762.939990 # average overall miss latency | 799system.cpu.icache.tags.tag_accesses 60349332 # Number of tag accesses 800system.cpu.icache.tags.data_accesses 60349332 # Number of data accesses 801system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 802system.cpu.icache.ReadReq_hits::cpu.inst 54569461 # number of ReadReq hits 803system.cpu.icache.ReadReq_hits::total 54569461 # number of ReadReq hits 804system.cpu.icache.demand_hits::cpu.inst 54569461 # number of demand (read+write) hits 805system.cpu.icache.demand_hits::total 54569461 # number of demand (read+write) hits 806system.cpu.icache.overall_hits::cpu.inst 54569461 # number of overall hits 807system.cpu.icache.overall_hits::total 54569461 # number of overall hits 808system.cpu.icache.ReadReq_misses::cpu.inst 2889936 # number of ReadReq misses 809system.cpu.icache.ReadReq_misses::total 2889936 # number of ReadReq misses 810system.cpu.icache.demand_misses::cpu.inst 2889936 # number of demand (read+write) misses 811system.cpu.icache.demand_misses::total 2889936 # number of demand (read+write) misses 812system.cpu.icache.overall_misses::cpu.inst 2889936 # number of overall misses 813system.cpu.icache.overall_misses::total 2889936 # number of overall misses 814system.cpu.icache.ReadReq_miss_latency::cpu.inst 39799359500 # number of ReadReq miss cycles 815system.cpu.icache.ReadReq_miss_latency::total 39799359500 # number of ReadReq miss cycles 816system.cpu.icache.demand_miss_latency::cpu.inst 39799359500 # number of demand (read+write) miss cycles 817system.cpu.icache.demand_miss_latency::total 39799359500 # number of demand (read+write) miss cycles 818system.cpu.icache.overall_miss_latency::cpu.inst 39799359500 # number of overall miss cycles 819system.cpu.icache.overall_miss_latency::total 39799359500 # number of overall miss cycles 820system.cpu.icache.ReadReq_accesses::cpu.inst 57459397 # number of ReadReq accesses(hits+misses) 821system.cpu.icache.ReadReq_accesses::total 57459397 # number of ReadReq accesses(hits+misses) 822system.cpu.icache.demand_accesses::cpu.inst 57459397 # number of demand (read+write) accesses 823system.cpu.icache.demand_accesses::total 57459397 # number of demand (read+write) accesses 824system.cpu.icache.overall_accesses::cpu.inst 57459397 # number of overall (read+write) accesses 825system.cpu.icache.overall_accesses::total 57459397 # number of overall (read+write) accesses 826system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050295 # miss rate for ReadReq accesses 827system.cpu.icache.ReadReq_miss_rate::total 0.050295 # miss rate for ReadReq accesses 828system.cpu.icache.demand_miss_rate::cpu.inst 0.050295 # miss rate for demand accesses 829system.cpu.icache.demand_miss_rate::total 0.050295 # miss rate for demand accesses 830system.cpu.icache.overall_miss_rate::cpu.inst 0.050295 # miss rate for overall accesses 831system.cpu.icache.overall_miss_rate::total 0.050295 # miss rate for overall accesses 832system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13771.709650 # average ReadReq miss latency 833system.cpu.icache.ReadReq_avg_miss_latency::total 13771.709650 # average ReadReq miss latency 834system.cpu.icache.demand_avg_miss_latency::cpu.inst 13771.709650 # average overall miss latency 835system.cpu.icache.demand_avg_miss_latency::total 13771.709650 # average overall miss latency 836system.cpu.icache.overall_avg_miss_latency::cpu.inst 13771.709650 # average overall miss latency 837system.cpu.icache.overall_avg_miss_latency::total 13771.709650 # average overall miss latency |
| 841system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 842system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 843system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 844system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 845system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 846system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 838system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 839system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 840system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 841system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 842system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 843system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 847system.cpu.icache.writebacks::writebacks 2891615 # number of writebacks 848system.cpu.icache.writebacks::total 2891615 # number of writebacks 849system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2892139 # number of ReadReq MSHR misses 850system.cpu.icache.ReadReq_mshr_misses::total 2892139 # number of ReadReq MSHR misses 851system.cpu.icache.demand_mshr_misses::cpu.inst 2892139 # number of demand (read+write) MSHR misses 852system.cpu.icache.demand_mshr_misses::total 2892139 # number of demand (read+write) MSHR misses 853system.cpu.icache.overall_mshr_misses::cpu.inst 2892139 # number of overall MSHR misses 854system.cpu.icache.overall_mshr_misses::total 2892139 # number of overall MSHR misses | 844system.cpu.icache.writebacks::writebacks 2889413 # number of writebacks 845system.cpu.icache.writebacks::total 2889413 # number of writebacks 846system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2889936 # number of ReadReq MSHR misses 847system.cpu.icache.ReadReq_mshr_misses::total 2889936 # number of ReadReq MSHR misses 848system.cpu.icache.demand_mshr_misses::cpu.inst 2889936 # number of demand (read+write) MSHR misses 849system.cpu.icache.demand_mshr_misses::total 2889936 # number of demand (read+write) MSHR misses 850system.cpu.icache.overall_mshr_misses::cpu.inst 2889936 # number of overall MSHR misses 851system.cpu.icache.overall_mshr_misses::total 2889936 # number of overall MSHR misses |
| 855system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3119 # number of ReadReq MSHR uncacheable 856system.cpu.icache.ReadReq_mshr_uncacheable::total 3119 # number of ReadReq MSHR uncacheable 857system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3119 # number of overall MSHR uncacheable misses 858system.cpu.icache.overall_mshr_uncacheable_misses::total 3119 # number of overall MSHR uncacheable misses | 852system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3119 # number of ReadReq MSHR uncacheable 853system.cpu.icache.ReadReq_mshr_uncacheable::total 3119 # number of ReadReq MSHR uncacheable 854system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3119 # number of overall MSHR uncacheable misses 855system.cpu.icache.overall_mshr_uncacheable_misses::total 3119 # number of overall MSHR uncacheable misses |
| 859system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36912197500 # number of ReadReq MSHR miss cycles 860system.cpu.icache.ReadReq_mshr_miss_latency::total 36912197500 # number of ReadReq MSHR miss cycles 861system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36912197500 # number of demand (read+write) MSHR miss cycles 862system.cpu.icache.demand_mshr_miss_latency::total 36912197500 # number of demand (read+write) MSHR miss cycles 863system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36912197500 # number of overall MSHR miss cycles 864system.cpu.icache.overall_mshr_miss_latency::total 36912197500 # number of overall MSHR miss cycles | 856system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36909424500 # number of ReadReq MSHR miss cycles 857system.cpu.icache.ReadReq_mshr_miss_latency::total 36909424500 # number of ReadReq MSHR miss cycles 858system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36909424500 # number of demand (read+write) MSHR miss cycles 859system.cpu.icache.demand_mshr_miss_latency::total 36909424500 # number of demand (read+write) MSHR miss cycles 860system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36909424500 # number of overall MSHR miss cycles 861system.cpu.icache.overall_mshr_miss_latency::total 36909424500 # number of overall MSHR miss cycles |
| 865system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 265216500 # number of ReadReq MSHR uncacheable cycles 866system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 265216500 # number of ReadReq MSHR uncacheable cycles 867system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 265216500 # number of overall MSHR uncacheable cycles 868system.cpu.icache.overall_mshr_uncacheable_latency::total 265216500 # number of overall MSHR uncacheable cycles | 862system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 265216500 # number of ReadReq MSHR uncacheable cycles 863system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 265216500 # number of ReadReq MSHR uncacheable cycles 864system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 265216500 # number of overall MSHR uncacheable cycles 865system.cpu.icache.overall_mshr_uncacheable_latency::total 265216500 # number of overall MSHR uncacheable cycles |
| 869system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050322 # mshr miss rate for ReadReq accesses 870system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050322 # mshr miss rate for ReadReq accesses 871system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050322 # mshr miss rate for demand accesses 872system.cpu.icache.demand_mshr_miss_rate::total 0.050322 # mshr miss rate for demand accesses 873system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050322 # mshr miss rate for overall accesses 874system.cpu.icache.overall_mshr_miss_rate::total 0.050322 # mshr miss rate for overall accesses 875system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12762.940336 # average ReadReq mshr miss latency 876system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12762.940336 # average ReadReq mshr miss latency 877system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12762.940336 # average overall mshr miss latency 878system.cpu.icache.demand_avg_mshr_miss_latency::total 12762.940336 # average overall mshr miss latency 879system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12762.940336 # average overall mshr miss latency 880system.cpu.icache.overall_avg_mshr_miss_latency::total 12762.940336 # average overall mshr miss latency | 866system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050295 # mshr miss rate for ReadReq accesses 867system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050295 # mshr miss rate for ReadReq accesses 868system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050295 # mshr miss rate for demand accesses 869system.cpu.icache.demand_mshr_miss_rate::total 0.050295 # mshr miss rate for demand accesses 870system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050295 # mshr miss rate for overall accesses 871system.cpu.icache.overall_mshr_miss_rate::total 0.050295 # mshr miss rate for overall accesses 872system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12771.709996 # average ReadReq mshr miss latency 873system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12771.709996 # average ReadReq mshr miss latency 874system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12771.709996 # average overall mshr miss latency 875system.cpu.icache.demand_avg_mshr_miss_latency::total 12771.709996 # average overall mshr miss latency 876system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12771.709996 # average overall mshr miss latency 877system.cpu.icache.overall_avg_mshr_miss_latency::total 12771.709996 # average overall mshr miss latency |
| 881system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 85032.542482 # average ReadReq mshr uncacheable latency 882system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 85032.542482 # average ReadReq mshr uncacheable latency 883system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 85032.542482 # average overall mshr uncacheable latency 884system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 85032.542482 # average overall mshr uncacheable latency | 878system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 85032.542482 # average ReadReq mshr uncacheable latency 879system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 85032.542482 # average ReadReq mshr uncacheable latency 880system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 85032.542482 # average overall mshr uncacheable latency 881system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 85032.542482 # average overall mshr uncacheable latency |
| 885system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 886system.cpu.l2cache.tags.replacements 97098 # number of replacements 887system.cpu.l2cache.tags.tagsinuse 65145.315179 # Cycle average of tags in use 888system.cpu.l2cache.tags.total_refs 7321379 # Total number of references to valid blocks. 889system.cpu.l2cache.tags.sampled_refs 162490 # Sample count of references to valid blocks. 890system.cpu.l2cache.tags.avg_refs 45.057413 # Average number of references to valid blocks. 891system.cpu.l2cache.tags.warmup_cycle 271905816000 # Cycle when the warmup percentage was hit. 892system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 69.248317 # Average occupied blocks per requestor 893system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.032949 # Average occupied blocks per requestor 894system.cpu.l2cache.tags.occ_blocks::cpu.inst 12118.407979 # Average occupied blocks per requestor 895system.cpu.l2cache.tags.occ_blocks::cpu.data 52957.625933 # Average occupied blocks per requestor 896system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001057 # Average percentage of cache occupancy 897system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy 898system.cpu.l2cache.tags.occ_percent::cpu.inst 0.184912 # Average percentage of cache occupancy 899system.cpu.l2cache.tags.occ_percent::cpu.data 0.808069 # Average percentage of cache occupancy 900system.cpu.l2cache.tags.occ_percent::total 0.994039 # Average percentage of cache occupancy 901system.cpu.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id 902system.cpu.l2cache.tags.occ_task_id_blocks::1024 65342 # Occupied blocks per task id 903system.cpu.l2cache.tags.age_task_id_blocks_1023::4 50 # Occupied blocks per task id 904system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 905system.cpu.l2cache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id 906system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4586 # Occupied blocks per task id 907system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60692 # Occupied blocks per task id 908system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000763 # Percentage of cache occupancy per task id 909system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997040 # Percentage of cache occupancy per task id 910system.cpu.l2cache.tags.tag_accesses 60089878 # Number of tag accesses 911system.cpu.l2cache.tags.data_accesses 60089878 # Number of data accesses 912system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 913system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68391 # number of ReadReq hits 914system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3372 # number of ReadReq hits 915system.cpu.l2cache.ReadReq_hits::total 71763 # number of ReadReq hits 916system.cpu.l2cache.WritebackDirty_hits::writebacks 702249 # number of WritebackDirty hits 917system.cpu.l2cache.WritebackDirty_hits::total 702249 # number of WritebackDirty hits 918system.cpu.l2cache.WritebackClean_hits::writebacks 2840964 # number of WritebackClean hits 919system.cpu.l2cache.WritebackClean_hits::total 2840964 # number of WritebackClean hits 920system.cpu.l2cache.UpgradeReq_hits::cpu.data 2784 # number of UpgradeReq hits 921system.cpu.l2cache.UpgradeReq_hits::total 2784 # number of UpgradeReq hits 922system.cpu.l2cache.ReadExReq_hits::cpu.data 166689 # number of ReadExReq hits 923system.cpu.l2cache.ReadExReq_hits::total 166689 # number of ReadExReq hits 924system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2869145 # number of ReadCleanReq hits 925system.cpu.l2cache.ReadCleanReq_hits::total 2869145 # number of ReadCleanReq hits 926system.cpu.l2cache.ReadSharedReq_hits::cpu.data 534458 # number of ReadSharedReq hits 927system.cpu.l2cache.ReadSharedReq_hits::total 534458 # number of ReadSharedReq hits 928system.cpu.l2cache.demand_hits::cpu.dtb.walker 68391 # number of demand (read+write) hits 929system.cpu.l2cache.demand_hits::cpu.itb.walker 3372 # number of demand (read+write) hits 930system.cpu.l2cache.demand_hits::cpu.inst 2869145 # number of demand (read+write) hits 931system.cpu.l2cache.demand_hits::cpu.data 701147 # number of demand (read+write) hits 932system.cpu.l2cache.demand_hits::total 3642055 # number of demand (read+write) hits 933system.cpu.l2cache.overall_hits::cpu.dtb.walker 68391 # number of overall hits 934system.cpu.l2cache.overall_hits::cpu.itb.walker 3372 # number of overall hits 935system.cpu.l2cache.overall_hits::cpu.inst 2869145 # number of overall hits 936system.cpu.l2cache.overall_hits::cpu.data 701147 # number of overall hits 937system.cpu.l2cache.overall_hits::total 3642055 # number of overall hits 938system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 110 # number of ReadReq misses 939system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 940system.cpu.l2cache.ReadReq_misses::total 112 # number of ReadReq misses | 882system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 883system.cpu.l2cache.tags.replacements 96873 # number of replacements 884system.cpu.l2cache.tags.tagsinuse 65145.709178 # Cycle average of tags in use 885system.cpu.l2cache.tags.total_refs 7314750 # Total number of references to valid blocks. 886system.cpu.l2cache.tags.sampled_refs 162275 # Sample count of references to valid blocks. 887system.cpu.l2cache.tags.avg_refs 45.076259 # Average number of references to valid blocks. 888system.cpu.l2cache.tags.warmup_cycle 99924187000 # Cycle when the warmup percentage was hit. 889system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 73.512854 # Average occupied blocks per requestor 890system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023684 # Average occupied blocks per requestor 891system.cpu.l2cache.tags.occ_blocks::cpu.inst 12110.922280 # Average occupied blocks per requestor 892system.cpu.l2cache.tags.occ_blocks::cpu.data 52961.250360 # Average occupied blocks per requestor 893system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001122 # Average percentage of cache occupancy 894system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 895system.cpu.l2cache.tags.occ_percent::cpu.inst 0.184798 # Average percentage of cache occupancy 896system.cpu.l2cache.tags.occ_percent::cpu.data 0.808125 # Average percentage of cache occupancy 897system.cpu.l2cache.tags.occ_percent::total 0.994045 # Average percentage of cache occupancy 898system.cpu.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id 899system.cpu.l2cache.tags.occ_task_id_blocks::1024 65344 # Occupied blocks per task id 900system.cpu.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 901system.cpu.l2cache.tags.age_task_id_blocks_1023::4 57 # Occupied blocks per task id 902system.cpu.l2cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id 903system.cpu.l2cache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id 904system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4564 # Occupied blocks per task id 905system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60694 # Occupied blocks per task id 906system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000885 # Percentage of cache occupancy per task id 907system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id 908system.cpu.l2cache.tags.tag_accesses 60034528 # Number of tag accesses 909system.cpu.l2cache.tags.data_accesses 60034528 # Number of data accesses 910system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 911system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 67803 # number of ReadReq hits 912system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3361 # number of ReadReq hits 913system.cpu.l2cache.ReadReq_hits::total 71164 # number of ReadReq hits 914system.cpu.l2cache.WritebackDirty_hits::writebacks 701301 # number of WritebackDirty hits 915system.cpu.l2cache.WritebackDirty_hits::total 701301 # number of WritebackDirty hits 916system.cpu.l2cache.WritebackClean_hits::writebacks 2838672 # number of WritebackClean hits 917system.cpu.l2cache.WritebackClean_hits::total 2838672 # number of WritebackClean hits 918system.cpu.l2cache.UpgradeReq_hits::cpu.data 2815 # number of UpgradeReq hits 919system.cpu.l2cache.UpgradeReq_hits::total 2815 # number of UpgradeReq hits 920system.cpu.l2cache.ReadExReq_hits::cpu.data 166503 # number of ReadExReq hits 921system.cpu.l2cache.ReadExReq_hits::total 166503 # number of ReadExReq hits 922system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2866935 # number of ReadCleanReq hits 923system.cpu.l2cache.ReadCleanReq_hits::total 2866935 # number of ReadCleanReq hits 924system.cpu.l2cache.ReadSharedReq_hits::cpu.data 533944 # number of ReadSharedReq hits 925system.cpu.l2cache.ReadSharedReq_hits::total 533944 # number of ReadSharedReq hits 926system.cpu.l2cache.demand_hits::cpu.dtb.walker 67803 # number of demand (read+write) hits 927system.cpu.l2cache.demand_hits::cpu.itb.walker 3361 # number of demand (read+write) hits 928system.cpu.l2cache.demand_hits::cpu.inst 2866935 # number of demand (read+write) hits 929system.cpu.l2cache.demand_hits::cpu.data 700447 # number of demand (read+write) hits 930system.cpu.l2cache.demand_hits::total 3638546 # number of demand (read+write) hits 931system.cpu.l2cache.overall_hits::cpu.dtb.walker 67803 # number of overall hits 932system.cpu.l2cache.overall_hits::cpu.itb.walker 3361 # number of overall hits 933system.cpu.l2cache.overall_hits::cpu.inst 2866935 # number of overall hits 934system.cpu.l2cache.overall_hits::cpu.data 700447 # number of overall hits 935system.cpu.l2cache.overall_hits::total 3638546 # number of overall hits 936system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 113 # number of ReadReq misses 937system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses 938system.cpu.l2cache.ReadReq_misses::total 114 # number of ReadReq misses |
| 941system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses 942system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses 943system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 944system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses | 939system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses 940system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses 941system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 942system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses |
| 945system.cpu.l2cache.ReadExReq_misses::cpu.data 129768 # number of ReadExReq misses 946system.cpu.l2cache.ReadExReq_misses::total 129768 # number of ReadExReq misses 947system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22956 # number of ReadCleanReq misses 948system.cpu.l2cache.ReadCleanReq_misses::total 22956 # number of ReadCleanReq misses 949system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14347 # number of ReadSharedReq misses 950system.cpu.l2cache.ReadSharedReq_misses::total 14347 # number of ReadSharedReq misses 951system.cpu.l2cache.demand_misses::cpu.dtb.walker 110 # number of demand (read+write) misses 952system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 953system.cpu.l2cache.demand_misses::cpu.inst 22956 # number of demand (read+write) misses 954system.cpu.l2cache.demand_misses::cpu.data 144115 # number of demand (read+write) misses 955system.cpu.l2cache.demand_misses::total 167183 # number of demand (read+write) misses 956system.cpu.l2cache.overall_misses::cpu.dtb.walker 110 # number of overall misses 957system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 958system.cpu.l2cache.overall_misses::cpu.inst 22956 # number of overall misses 959system.cpu.l2cache.overall_misses::cpu.data 144115 # number of overall misses 960system.cpu.l2cache.overall_misses::total 167183 # number of overall misses 961system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 35753500 # number of ReadReq miss cycles 962system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 193000 # number of ReadReq miss cycles 963system.cpu.l2cache.ReadReq_miss_latency::total 35946500 # number of ReadReq miss cycles | 943system.cpu.l2cache.ReadExReq_misses::cpu.data 129573 # number of ReadExReq misses 944system.cpu.l2cache.ReadExReq_misses::total 129573 # number of ReadExReq misses 945system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22965 # number of ReadCleanReq misses 946system.cpu.l2cache.ReadCleanReq_misses::total 22965 # number of ReadCleanReq misses 947system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14315 # number of ReadSharedReq misses 948system.cpu.l2cache.ReadSharedReq_misses::total 14315 # number of ReadSharedReq misses 949system.cpu.l2cache.demand_misses::cpu.dtb.walker 113 # number of demand (read+write) misses 950system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses 951system.cpu.l2cache.demand_misses::cpu.inst 22965 # number of demand (read+write) misses 952system.cpu.l2cache.demand_misses::cpu.data 143888 # number of demand (read+write) misses 953system.cpu.l2cache.demand_misses::total 166967 # number of demand (read+write) misses 954system.cpu.l2cache.overall_misses::cpu.dtb.walker 113 # number of overall misses 955system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses 956system.cpu.l2cache.overall_misses::cpu.inst 22965 # number of overall misses 957system.cpu.l2cache.overall_misses::cpu.data 143888 # number of overall misses 958system.cpu.l2cache.overall_misses::total 166967 # number of overall misses 959system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 38662500 # number of ReadReq miss cycles 960system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 89500 # number of ReadReq miss cycles 961system.cpu.l2cache.ReadReq_miss_latency::total 38752000 # number of ReadReq miss cycles |
| 964system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 174000 # number of UpgradeReq miss cycles 965system.cpu.l2cache.UpgradeReq_miss_latency::total 174000 # number of UpgradeReq miss cycles 966system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 166000 # number of SCUpgradeReq miss cycles 967system.cpu.l2cache.SCUpgradeReq_miss_latency::total 166000 # number of SCUpgradeReq miss cycles | 962system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 174000 # number of UpgradeReq miss cycles 963system.cpu.l2cache.UpgradeReq_miss_latency::total 174000 # number of UpgradeReq miss cycles 964system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 166000 # number of SCUpgradeReq miss cycles 965system.cpu.l2cache.SCUpgradeReq_miss_latency::total 166000 # number of SCUpgradeReq miss cycles |
| 968system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12066822500 # number of ReadExReq miss cycles 969system.cpu.l2cache.ReadExReq_miss_latency::total 12066822500 # number of ReadExReq miss cycles 970system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2380927500 # number of ReadCleanReq miss cycles 971system.cpu.l2cache.ReadCleanReq_miss_latency::total 2380927500 # number of ReadCleanReq miss cycles 972system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1746972000 # number of ReadSharedReq miss cycles 973system.cpu.l2cache.ReadSharedReq_miss_latency::total 1746972000 # number of ReadSharedReq miss cycles 974system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 35753500 # number of demand (read+write) miss cycles 975system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 193000 # number of demand (read+write) miss cycles 976system.cpu.l2cache.demand_miss_latency::cpu.inst 2380927500 # number of demand (read+write) miss cycles 977system.cpu.l2cache.demand_miss_latency::cpu.data 13813794500 # number of demand (read+write) miss cycles 978system.cpu.l2cache.demand_miss_latency::total 16230668500 # number of demand (read+write) miss cycles 979system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 35753500 # number of overall miss cycles 980system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 193000 # number of overall miss cycles 981system.cpu.l2cache.overall_miss_latency::cpu.inst 2380927500 # number of overall miss cycles 982system.cpu.l2cache.overall_miss_latency::cpu.data 13813794500 # number of overall miss cycles 983system.cpu.l2cache.overall_miss_latency::total 16230668500 # number of overall miss cycles 984system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68501 # number of ReadReq accesses(hits+misses) 985system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3374 # number of ReadReq accesses(hits+misses) 986system.cpu.l2cache.ReadReq_accesses::total 71875 # number of ReadReq accesses(hits+misses) 987system.cpu.l2cache.WritebackDirty_accesses::writebacks 702249 # number of WritebackDirty accesses(hits+misses) 988system.cpu.l2cache.WritebackDirty_accesses::total 702249 # number of WritebackDirty accesses(hits+misses) 989system.cpu.l2cache.WritebackClean_accesses::writebacks 2840964 # number of WritebackClean accesses(hits+misses) 990system.cpu.l2cache.WritebackClean_accesses::total 2840964 # number of WritebackClean accesses(hits+misses) 991system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2790 # number of UpgradeReq accesses(hits+misses) 992system.cpu.l2cache.UpgradeReq_accesses::total 2790 # number of UpgradeReq accesses(hits+misses) | 966system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12000990500 # number of ReadExReq miss cycles 967system.cpu.l2cache.ReadExReq_miss_latency::total 12000990500 # number of ReadExReq miss cycles 968system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2404531500 # number of ReadCleanReq miss cycles 969system.cpu.l2cache.ReadCleanReq_miss_latency::total 2404531500 # number of ReadCleanReq miss cycles 970system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1744805500 # number of ReadSharedReq miss cycles 971system.cpu.l2cache.ReadSharedReq_miss_latency::total 1744805500 # number of ReadSharedReq miss cycles 972system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 38662500 # number of demand (read+write) miss cycles 973system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 89500 # number of demand (read+write) miss cycles 974system.cpu.l2cache.demand_miss_latency::cpu.inst 2404531500 # number of demand (read+write) miss cycles 975system.cpu.l2cache.demand_miss_latency::cpu.data 13745796000 # number of demand (read+write) miss cycles 976system.cpu.l2cache.demand_miss_latency::total 16189079500 # number of demand (read+write) miss cycles 977system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 38662500 # number of overall miss cycles 978system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 89500 # number of overall miss cycles 979system.cpu.l2cache.overall_miss_latency::cpu.inst 2404531500 # number of overall miss cycles 980system.cpu.l2cache.overall_miss_latency::cpu.data 13745796000 # number of overall miss cycles 981system.cpu.l2cache.overall_miss_latency::total 16189079500 # number of overall miss cycles 982system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 67916 # number of ReadReq accesses(hits+misses) 983system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3362 # number of ReadReq accesses(hits+misses) 984system.cpu.l2cache.ReadReq_accesses::total 71278 # number of ReadReq accesses(hits+misses) 985system.cpu.l2cache.WritebackDirty_accesses::writebacks 701301 # number of WritebackDirty accesses(hits+misses) 986system.cpu.l2cache.WritebackDirty_accesses::total 701301 # number of WritebackDirty accesses(hits+misses) 987system.cpu.l2cache.WritebackClean_accesses::writebacks 2838672 # number of WritebackClean accesses(hits+misses) 988system.cpu.l2cache.WritebackClean_accesses::total 2838672 # number of WritebackClean accesses(hits+misses) 989system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2821 # number of UpgradeReq accesses(hits+misses) 990system.cpu.l2cache.UpgradeReq_accesses::total 2821 # number of UpgradeReq accesses(hits+misses) |
| 993system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 994system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) | 991system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 992system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) |
| 995system.cpu.l2cache.ReadExReq_accesses::cpu.data 296457 # number of ReadExReq accesses(hits+misses) 996system.cpu.l2cache.ReadExReq_accesses::total 296457 # number of ReadExReq accesses(hits+misses) 997system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2892101 # number of ReadCleanReq accesses(hits+misses) 998system.cpu.l2cache.ReadCleanReq_accesses::total 2892101 # number of ReadCleanReq accesses(hits+misses) 999system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 548805 # number of ReadSharedReq accesses(hits+misses) 1000system.cpu.l2cache.ReadSharedReq_accesses::total 548805 # number of ReadSharedReq accesses(hits+misses) 1001system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68501 # number of demand (read+write) accesses 1002system.cpu.l2cache.demand_accesses::cpu.itb.walker 3374 # number of demand (read+write) accesses 1003system.cpu.l2cache.demand_accesses::cpu.inst 2892101 # number of demand (read+write) accesses 1004system.cpu.l2cache.demand_accesses::cpu.data 845262 # number of demand (read+write) accesses 1005system.cpu.l2cache.demand_accesses::total 3809238 # number of demand (read+write) accesses 1006system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68501 # number of overall (read+write) accesses 1007system.cpu.l2cache.overall_accesses::cpu.itb.walker 3374 # number of overall (read+write) accesses 1008system.cpu.l2cache.overall_accesses::cpu.inst 2892101 # number of overall (read+write) accesses 1009system.cpu.l2cache.overall_accesses::cpu.data 845262 # number of overall (read+write) accesses 1010system.cpu.l2cache.overall_accesses::total 3809238 # number of overall (read+write) accesses 1011system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001606 # miss rate for ReadReq accesses 1012system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000593 # miss rate for ReadReq accesses 1013system.cpu.l2cache.ReadReq_miss_rate::total 0.001558 # miss rate for ReadReq accesses 1014system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.002151 # miss rate for UpgradeReq accesses 1015system.cpu.l2cache.UpgradeReq_miss_rate::total 0.002151 # miss rate for UpgradeReq accesses | 993system.cpu.l2cache.ReadExReq_accesses::cpu.data 296076 # number of ReadExReq accesses(hits+misses) 994system.cpu.l2cache.ReadExReq_accesses::total 296076 # number of ReadExReq accesses(hits+misses) 995system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2889900 # number of ReadCleanReq accesses(hits+misses) 996system.cpu.l2cache.ReadCleanReq_accesses::total 2889900 # number of ReadCleanReq accesses(hits+misses) 997system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 548259 # number of ReadSharedReq accesses(hits+misses) 998system.cpu.l2cache.ReadSharedReq_accesses::total 548259 # number of ReadSharedReq accesses(hits+misses) 999system.cpu.l2cache.demand_accesses::cpu.dtb.walker 67916 # number of demand (read+write) accesses 1000system.cpu.l2cache.demand_accesses::cpu.itb.walker 3362 # number of demand (read+write) accesses 1001system.cpu.l2cache.demand_accesses::cpu.inst 2889900 # number of demand (read+write) accesses 1002system.cpu.l2cache.demand_accesses::cpu.data 844335 # number of demand (read+write) accesses 1003system.cpu.l2cache.demand_accesses::total 3805513 # number of demand (read+write) accesses 1004system.cpu.l2cache.overall_accesses::cpu.dtb.walker 67916 # number of overall (read+write) accesses 1005system.cpu.l2cache.overall_accesses::cpu.itb.walker 3362 # number of overall (read+write) accesses 1006system.cpu.l2cache.overall_accesses::cpu.inst 2889900 # number of overall (read+write) accesses 1007system.cpu.l2cache.overall_accesses::cpu.data 844335 # number of overall (read+write) accesses 1008system.cpu.l2cache.overall_accesses::total 3805513 # number of overall (read+write) accesses 1009system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001664 # miss rate for ReadReq accesses 1010system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000297 # miss rate for ReadReq accesses 1011system.cpu.l2cache.ReadReq_miss_rate::total 0.001599 # miss rate for ReadReq accesses 1012system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.002127 # miss rate for UpgradeReq accesses 1013system.cpu.l2cache.UpgradeReq_miss_rate::total 0.002127 # miss rate for UpgradeReq accesses |
| 1016system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 1017system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 1014system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 1015system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 1018system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437730 # miss rate for ReadExReq accesses 1019system.cpu.l2cache.ReadExReq_miss_rate::total 0.437730 # miss rate for ReadExReq accesses 1020system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007937 # miss rate for ReadCleanReq accesses 1021system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007937 # miss rate for ReadCleanReq accesses 1022system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026142 # miss rate for ReadSharedReq accesses 1023system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026142 # miss rate for ReadSharedReq accesses 1024system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001606 # miss rate for demand accesses 1025system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000593 # miss rate for demand accesses 1026system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007937 # miss rate for demand accesses 1027system.cpu.l2cache.demand_miss_rate::cpu.data 0.170497 # miss rate for demand accesses 1028system.cpu.l2cache.demand_miss_rate::total 0.043889 # miss rate for demand accesses 1029system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001606 # miss rate for overall accesses 1030system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000593 # miss rate for overall accesses 1031system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007937 # miss rate for overall accesses 1032system.cpu.l2cache.overall_miss_rate::cpu.data 0.170497 # miss rate for overall accesses 1033system.cpu.l2cache.overall_miss_rate::total 0.043889 # miss rate for overall accesses 1034system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 325031.818182 # average ReadReq miss latency 1035system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 96500 # average ReadReq miss latency 1036system.cpu.l2cache.ReadReq_avg_miss_latency::total 320950.892857 # average ReadReq miss latency | 1016system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437634 # miss rate for ReadExReq accesses 1017system.cpu.l2cache.ReadExReq_miss_rate::total 0.437634 # miss rate for ReadExReq accesses 1018system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007947 # miss rate for ReadCleanReq accesses 1019system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007947 # miss rate for ReadCleanReq accesses 1020system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026110 # miss rate for ReadSharedReq accesses 1021system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026110 # miss rate for ReadSharedReq accesses 1022system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001664 # miss rate for demand accesses 1023system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000297 # miss rate for demand accesses 1024system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007947 # miss rate for demand accesses 1025system.cpu.l2cache.demand_miss_rate::cpu.data 0.170416 # miss rate for demand accesses 1026system.cpu.l2cache.demand_miss_rate::total 0.043875 # miss rate for demand accesses 1027system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001664 # miss rate for overall accesses 1028system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000297 # miss rate for overall accesses 1029system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007947 # miss rate for overall accesses 1030system.cpu.l2cache.overall_miss_rate::cpu.data 0.170416 # miss rate for overall accesses 1031system.cpu.l2cache.overall_miss_rate::total 0.043875 # miss rate for overall accesses 1032system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 342146.017699 # average ReadReq miss latency 1033system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89500 # average ReadReq miss latency 1034system.cpu.l2cache.ReadReq_avg_miss_latency::total 339929.824561 # average ReadReq miss latency |
| 1037system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29000 # average UpgradeReq miss latency 1038system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29000 # average UpgradeReq miss latency 1039system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 83000 # average SCUpgradeReq miss latency 1040system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 83000 # average SCUpgradeReq miss latency | 1035system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29000 # average UpgradeReq miss latency 1036system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29000 # average UpgradeReq miss latency 1037system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 83000 # average SCUpgradeReq miss latency 1038system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 83000 # average SCUpgradeReq miss latency |
| 1041system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92987.658745 # average ReadExReq miss latency 1042system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92987.658745 # average ReadExReq miss latency 1043system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103717.002091 # average ReadCleanReq miss latency 1044system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103717.002091 # average ReadCleanReq miss latency 1045system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 121765.665296 # average ReadSharedReq miss latency 1046system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 121765.665296 # average ReadSharedReq miss latency 1047system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 325031.818182 # average overall miss latency 1048system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 96500 # average overall miss latency 1049system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103717.002091 # average overall miss latency 1050system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95852.579537 # average overall miss latency 1051system.cpu.l2cache.demand_avg_miss_latency::total 97083.247100 # average overall miss latency 1052system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 325031.818182 # average overall miss latency 1053system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 96500 # average overall miss latency 1054system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103717.002091 # average overall miss latency 1055system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95852.579537 # average overall miss latency 1056system.cpu.l2cache.overall_avg_miss_latency::total 97083.247100 # average overall miss latency | 1039system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92619.531075 # average ReadExReq miss latency 1040system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92619.531075 # average ReadExReq miss latency 1041system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 104704.180274 # average ReadCleanReq miss latency 1042system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 104704.180274 # average ReadCleanReq miss latency 1043system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 121886.517639 # average ReadSharedReq miss latency 1044system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 121886.517639 # average ReadSharedReq miss latency 1045system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 342146.017699 # average overall miss latency 1046system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89500 # average overall miss latency 1047system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 104704.180274 # average overall miss latency 1048system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95531.218726 # average overall miss latency 1049system.cpu.l2cache.demand_avg_miss_latency::total 96959.755521 # average overall miss latency 1050system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 342146.017699 # average overall miss latency 1051system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89500 # average overall miss latency 1052system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 104704.180274 # average overall miss latency 1053system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95531.218726 # average overall miss latency 1054system.cpu.l2cache.overall_avg_miss_latency::total 96959.755521 # average overall miss latency |
| 1057system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1058system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1059system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1060system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1061system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1062system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1055system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1056system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1057system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1058system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1059system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1060system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1063system.cpu.l2cache.writebacks::writebacks 88493 # number of writebacks 1064system.cpu.l2cache.writebacks::total 88493 # number of writebacks 1065system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 14 # number of ReadCleanReq MSHR hits 1066system.cpu.l2cache.ReadCleanReq_mshr_hits::total 14 # number of ReadCleanReq MSHR hits 1067system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 145 # number of ReadSharedReq MSHR hits 1068system.cpu.l2cache.ReadSharedReq_mshr_hits::total 145 # number of ReadSharedReq MSHR hits 1069system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits 1070system.cpu.l2cache.demand_mshr_hits::cpu.data 145 # number of demand (read+write) MSHR hits 1071system.cpu.l2cache.demand_mshr_hits::total 159 # number of demand (read+write) MSHR hits 1072system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits 1073system.cpu.l2cache.overall_mshr_hits::cpu.data 145 # number of overall MSHR hits 1074system.cpu.l2cache.overall_mshr_hits::total 159 # number of overall MSHR hits 1075system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 110 # number of ReadReq MSHR misses 1076system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 1077system.cpu.l2cache.ReadReq_mshr_misses::total 112 # number of ReadReq MSHR misses | 1061system.cpu.l2cache.writebacks::writebacks 88174 # number of writebacks 1062system.cpu.l2cache.writebacks::total 88174 # number of writebacks 1063system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits 1064system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits 1065system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 144 # number of ReadSharedReq MSHR hits 1066system.cpu.l2cache.ReadSharedReq_mshr_hits::total 144 # number of ReadSharedReq MSHR hits 1067system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits 1068system.cpu.l2cache.demand_mshr_hits::cpu.data 144 # number of demand (read+write) MSHR hits 1069system.cpu.l2cache.demand_mshr_hits::total 157 # number of demand (read+write) MSHR hits 1070system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits 1071system.cpu.l2cache.overall_mshr_hits::cpu.data 144 # number of overall MSHR hits 1072system.cpu.l2cache.overall_mshr_hits::total 157 # number of overall MSHR hits 1073system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 113 # number of ReadReq MSHR misses 1074system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses 1075system.cpu.l2cache.ReadReq_mshr_misses::total 114 # number of ReadReq MSHR misses |
| 1078system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses 1079system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses 1080system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1081system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses | 1076system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses 1077system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses 1078system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1079system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses |
| 1082system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 129768 # number of ReadExReq MSHR misses 1083system.cpu.l2cache.ReadExReq_mshr_misses::total 129768 # number of ReadExReq MSHR misses 1084system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22942 # number of ReadCleanReq MSHR misses 1085system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22942 # number of ReadCleanReq MSHR misses 1086system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14202 # number of ReadSharedReq MSHR misses 1087system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14202 # number of ReadSharedReq MSHR misses 1088system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 110 # number of demand (read+write) MSHR misses 1089system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 1090system.cpu.l2cache.demand_mshr_misses::cpu.inst 22942 # number of demand (read+write) MSHR misses 1091system.cpu.l2cache.demand_mshr_misses::cpu.data 143970 # number of demand (read+write) MSHR misses 1092system.cpu.l2cache.demand_mshr_misses::total 167024 # number of demand (read+write) MSHR misses 1093system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 110 # number of overall MSHR misses 1094system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 1095system.cpu.l2cache.overall_mshr_misses::cpu.inst 22942 # number of overall MSHR misses 1096system.cpu.l2cache.overall_mshr_misses::cpu.data 143970 # number of overall MSHR misses 1097system.cpu.l2cache.overall_mshr_misses::total 167024 # number of overall MSHR misses | 1080system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 129573 # number of ReadExReq MSHR misses 1081system.cpu.l2cache.ReadExReq_mshr_misses::total 129573 # number of ReadExReq MSHR misses 1082system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22952 # number of ReadCleanReq MSHR misses 1083system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22952 # number of ReadCleanReq MSHR misses 1084system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14171 # number of ReadSharedReq MSHR misses 1085system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14171 # number of ReadSharedReq MSHR misses 1086system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 113 # number of demand (read+write) MSHR misses 1087system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses 1088system.cpu.l2cache.demand_mshr_misses::cpu.inst 22952 # number of demand (read+write) MSHR misses 1089system.cpu.l2cache.demand_mshr_misses::cpu.data 143744 # number of demand (read+write) MSHR misses 1090system.cpu.l2cache.demand_mshr_misses::total 166810 # number of demand (read+write) MSHR misses 1091system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 113 # number of overall MSHR misses 1092system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses 1093system.cpu.l2cache.overall_mshr_misses::cpu.inst 22952 # number of overall MSHR misses 1094system.cpu.l2cache.overall_mshr_misses::cpu.data 143744 # number of overall MSHR misses 1095system.cpu.l2cache.overall_mshr_misses::total 166810 # number of overall MSHR misses |
| 1098system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3119 # number of ReadReq MSHR uncacheable 1099system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable 1100system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34249 # number of ReadReq MSHR uncacheable 1101system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable 1102system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable 1103system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3119 # number of overall MSHR uncacheable misses 1104system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 1105system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61833 # number of overall MSHR uncacheable misses | 1096system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3119 # number of ReadReq MSHR uncacheable 1097system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable 1098system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34249 # number of ReadReq MSHR uncacheable 1099system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable 1100system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable 1101system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3119 # number of overall MSHR uncacheable misses 1102system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 1103system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61833 # number of overall MSHR uncacheable misses |
| 1106system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 34653500 # number of ReadReq MSHR miss cycles 1107system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 173000 # number of ReadReq MSHR miss cycles 1108system.cpu.l2cache.ReadReq_mshr_miss_latency::total 34826500 # number of ReadReq MSHR miss cycles | 1104system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 37532500 # number of ReadReq MSHR miss cycles 1105system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 79500 # number of ReadReq MSHR miss cycles 1106system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37612000 # number of ReadReq MSHR miss cycles |
| 1109system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 114000 # number of UpgradeReq MSHR miss cycles 1110system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 114000 # number of UpgradeReq MSHR miss cycles 1111system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 146000 # number of SCUpgradeReq MSHR miss cycles 1112system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 146000 # number of SCUpgradeReq MSHR miss cycles | 1107system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 114000 # number of UpgradeReq MSHR miss cycles 1108system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 114000 # number of UpgradeReq MSHR miss cycles 1109system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 146000 # number of SCUpgradeReq MSHR miss cycles 1110system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 146000 # number of SCUpgradeReq MSHR miss cycles |
| 1113system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10769142500 # number of ReadExReq MSHR miss cycles 1114system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10769142500 # number of ReadExReq MSHR miss cycles 1115system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2149471500 # number of ReadCleanReq MSHR miss cycles 1116system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2149471500 # number of ReadCleanReq MSHR miss cycles 1117system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1592398000 # number of ReadSharedReq MSHR miss cycles 1118system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1592398000 # number of ReadSharedReq MSHR miss cycles 1119system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 34653500 # number of demand (read+write) MSHR miss cycles 1120system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 173000 # number of demand (read+write) MSHR miss cycles 1121system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2149471500 # number of demand (read+write) MSHR miss cycles 1122system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12361540500 # number of demand (read+write) MSHR miss cycles 1123system.cpu.l2cache.demand_mshr_miss_latency::total 14545838500 # number of demand (read+write) MSHR miss cycles 1124system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 34653500 # number of overall MSHR miss cycles 1125system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 173000 # number of overall MSHR miss cycles 1126system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2149471500 # number of overall MSHR miss cycles 1127system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12361540500 # number of overall MSHR miss cycles 1128system.cpu.l2cache.overall_mshr_miss_latency::total 14545838500 # number of overall MSHR miss cycles | 1111system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10705260500 # number of ReadExReq MSHR miss cycles 1112system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10705260500 # number of ReadExReq MSHR miss cycles 1113system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2173786500 # number of ReadCleanReq MSHR miss cycles 1114system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2173786500 # number of ReadCleanReq MSHR miss cycles 1115system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1590255500 # number of ReadSharedReq MSHR miss cycles 1116system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1590255500 # number of ReadSharedReq MSHR miss cycles 1117system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 37532500 # number of demand (read+write) MSHR miss cycles 1118system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 79500 # number of demand (read+write) MSHR miss cycles 1119system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2173786500 # number of demand (read+write) MSHR miss cycles 1120system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12295516000 # number of demand (read+write) MSHR miss cycles 1121system.cpu.l2cache.demand_mshr_miss_latency::total 14506914500 # number of demand (read+write) MSHR miss cycles 1122system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 37532500 # number of overall MSHR miss cycles 1123system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 79500 # number of overall MSHR miss cycles 1124system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2173786500 # number of overall MSHR miss cycles 1125system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12295516000 # number of overall MSHR miss cycles 1126system.cpu.l2cache.overall_mshr_miss_latency::total 14506914500 # number of overall MSHR miss cycles |
| 1129system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 216819500 # number of ReadReq MSHR uncacheable cycles | 1127system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 216819500 # number of ReadReq MSHR uncacheable cycles |
| 1130system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5916431500 # number of ReadReq MSHR uncacheable cycles 1131system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6133251000 # number of ReadReq MSHR uncacheable cycles | 1128system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5916233500 # number of ReadReq MSHR uncacheable cycles 1129system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6133053000 # number of ReadReq MSHR uncacheable cycles |
| 1132system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 216819500 # number of overall MSHR uncacheable cycles | 1130system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 216819500 # number of overall MSHR uncacheable cycles |
| 1133system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5916431500 # number of overall MSHR uncacheable cycles 1134system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6133251000 # number of overall MSHR uncacheable cycles 1135system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001606 # mshr miss rate for ReadReq accesses 1136system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000593 # mshr miss rate for ReadReq accesses 1137system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001558 # mshr miss rate for ReadReq accesses 1138system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.002151 # mshr miss rate for UpgradeReq accesses 1139system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.002151 # mshr miss rate for UpgradeReq accesses | 1131system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5916233500 # number of overall MSHR uncacheable cycles 1132system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6133053000 # number of overall MSHR uncacheable cycles 1133system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001664 # mshr miss rate for ReadReq accesses 1134system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000297 # mshr miss rate for ReadReq accesses 1135system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001599 # mshr miss rate for ReadReq accesses 1136system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.002127 # mshr miss rate for UpgradeReq accesses 1137system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.002127 # mshr miss rate for UpgradeReq accesses |
| 1140system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1141system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses | 1138system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1139system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses |
| 1142system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437730 # mshr miss rate for ReadExReq accesses 1143system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437730 # mshr miss rate for ReadExReq accesses 1144system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007933 # mshr miss rate for ReadCleanReq accesses 1145system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007933 # mshr miss rate for ReadCleanReq accesses 1146system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025878 # mshr miss rate for ReadSharedReq accesses 1147system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025878 # mshr miss rate for ReadSharedReq accesses 1148system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001606 # mshr miss rate for demand accesses 1149system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000593 # mshr miss rate for demand accesses 1150system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007933 # mshr miss rate for demand accesses 1151system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170326 # mshr miss rate for demand accesses 1152system.cpu.l2cache.demand_mshr_miss_rate::total 0.043847 # mshr miss rate for demand accesses 1153system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001606 # mshr miss rate for overall accesses 1154system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000593 # mshr miss rate for overall accesses 1155system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007933 # mshr miss rate for overall accesses 1156system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170326 # mshr miss rate for overall accesses 1157system.cpu.l2cache.overall_mshr_miss_rate::total 0.043847 # mshr miss rate for overall accesses 1158system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182 # average ReadReq mshr miss latency 1159system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 86500 # average ReadReq mshr miss latency 1160system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 310950.892857 # average ReadReq mshr miss latency | 1140system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437634 # mshr miss rate for ReadExReq accesses 1141system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437634 # mshr miss rate for ReadExReq accesses 1142system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007942 # mshr miss rate for ReadCleanReq accesses 1143system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007942 # mshr miss rate for ReadCleanReq accesses 1144system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025847 # mshr miss rate for ReadSharedReq accesses 1145system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025847 # mshr miss rate for ReadSharedReq accesses 1146system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001664 # mshr miss rate for demand accesses 1147system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000297 # mshr miss rate for demand accesses 1148system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007942 # mshr miss rate for demand accesses 1149system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170245 # mshr miss rate for demand accesses 1150system.cpu.l2cache.demand_mshr_miss_rate::total 0.043834 # mshr miss rate for demand accesses 1151system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001664 # mshr miss rate for overall accesses 1152system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000297 # mshr miss rate for overall accesses 1153system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007942 # mshr miss rate for overall accesses 1154system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170245 # mshr miss rate for overall accesses 1155system.cpu.l2cache.overall_mshr_miss_rate::total 0.043834 # mshr miss rate for overall accesses 1156system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 332146.017699 # average ReadReq mshr miss latency 1157system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79500 # average ReadReq mshr miss latency 1158system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 329929.824561 # average ReadReq mshr miss latency |
| 1161system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19000 # average UpgradeReq mshr miss latency 1162system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19000 # average UpgradeReq mshr miss latency 1163system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 73000 # average SCUpgradeReq mshr miss latency 1164system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 73000 # average SCUpgradeReq mshr miss latency | 1159system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19000 # average UpgradeReq mshr miss latency 1160system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19000 # average UpgradeReq mshr miss latency 1161system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 73000 # average SCUpgradeReq mshr miss latency 1162system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 73000 # average SCUpgradeReq mshr miss latency |
| 1165system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82987.658745 # average ReadExReq mshr miss latency 1166system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82987.658745 # average ReadExReq mshr miss latency 1167system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93691.548252 # average ReadCleanReq mshr miss latency 1168system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93691.548252 # average ReadCleanReq mshr miss latency 1169system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 112124.911984 # average ReadSharedReq mshr miss latency 1170system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 112124.911984 # average ReadSharedReq mshr miss latency 1171system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182 # average overall mshr miss latency 1172system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 86500 # average overall mshr miss latency 1173system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93691.548252 # average overall mshr miss latency 1174system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85861.919150 # average overall mshr miss latency 1175system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87088.313656 # average overall mshr miss latency 1176system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182 # average overall mshr miss latency 1177system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 86500 # average overall mshr miss latency 1178system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93691.548252 # average overall mshr miss latency 1179system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85861.919150 # average overall mshr miss latency 1180system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87088.313656 # average overall mshr miss latency | 1163system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82619.531075 # average ReadExReq mshr miss latency 1164system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82619.531075 # average ReadExReq mshr miss latency 1165system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 94710.112409 # average ReadCleanReq mshr miss latency 1166system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 94710.112409 # average ReadCleanReq mshr miss latency 1167system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 112219.003599 # average ReadSharedReq mshr miss latency 1168system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 112219.003599 # average ReadSharedReq mshr miss latency 1169system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 332146.017699 # average overall mshr miss latency 1170system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79500 # average overall mshr miss latency 1171system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 94710.112409 # average overall mshr miss latency 1172system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85537.594613 # average overall mshr miss latency 1173system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86966.695642 # average overall mshr miss latency 1174system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 332146.017699 # average overall mshr miss latency 1175system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79500 # average overall mshr miss latency 1176system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 94710.112409 # average overall mshr miss latency 1177system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85537.594613 # average overall mshr miss latency 1178system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86966.695642 # average overall mshr miss latency |
| 1181system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69515.710164 # average ReadReq mshr uncacheable latency | 1179system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69515.710164 # average ReadReq mshr uncacheable latency |
| 1182system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190055.621587 # average ReadReq mshr uncacheable latency 1183system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 179078.250460 # average ReadReq mshr uncacheable latency | 1180system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190049.261163 # average ReadReq mshr uncacheable latency 1181system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 179072.469269 # average ReadReq mshr uncacheable latency |
| 1184system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69515.710164 # average overall mshr uncacheable latency | 1182system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69515.710164 # average overall mshr uncacheable latency |
| 1185system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100766.963586 # average overall mshr uncacheable latency 1186system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 99190.577847 # average overall mshr uncacheable latency 1187system.cpu.toL2Bus.snoop_filter.tot_requests 7507397 # Total number of requests made to the snoop filter. 1188system.cpu.toL2Bus.snoop_filter.hit_single_requests 3770030 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1189system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58003 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1190system.cpu.toL2Bus.snoop_filter.tot_snoops 175 # Total number of snoops made to the snoop filter. 1191system.cpu.toL2Bus.snoop_filter.hit_single_snoops 175 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 1183system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100763.591307 # average overall mshr uncacheable latency 1184system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 99187.375673 # average overall mshr uncacheable latency 1185system.cpu.toL2Bus.snoop_filter.tot_requests 7501348 # Total number of requests made to the snoop filter. 1186system.cpu.toL2Bus.snoop_filter.hit_single_requests 3767098 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1187system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58079 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1188system.cpu.toL2Bus.snoop_filter.tot_snoops 189 # Total number of snoops made to the snoop filter. 1189system.cpu.toL2Bus.snoop_filter.hit_single_snoops 189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 1192system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1190system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1193system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1194system.cpu.toL2Bus.trans_dist::ReadReq 136990 # Transaction distribution 1195system.cpu.toL2Bus.trans_dist::ReadResp 3578080 # Transaction distribution | 1191system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1192system.cpu.toL2Bus.trans_dist::ReadReq 136577 # Transaction distribution 1193system.cpu.toL2Bus.trans_dist::ReadResp 3574918 # Transaction distribution |
| 1196system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution 1197system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution | 1194system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution 1195system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution |
| 1198system.cpu.toL2Bus.trans_dist::WritebackDirty 790742 # Transaction distribution 1199system.cpu.toL2Bus.trans_dist::WritebackClean 2891615 # Transaction distribution 1200system.cpu.toL2Bus.trans_dist::CleanEvict 151079 # Transaction distribution 1201system.cpu.toL2Bus.trans_dist::UpgradeReq 2790 # Transaction distribution | 1196system.cpu.toL2Bus.trans_dist::WritebackDirty 789475 # Transaction distribution 1197system.cpu.toL2Bus.trans_dist::WritebackClean 2889413 # Transaction distribution 1198system.cpu.toL2Bus.trans_dist::CleanEvict 151189 # Transaction distribution 1199system.cpu.toL2Bus.trans_dist::UpgradeReq 2821 # Transaction distribution |
| 1202system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution | 1200system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution |
| 1203system.cpu.toL2Bus.trans_dist::UpgradeResp 2792 # Transaction distribution 1204system.cpu.toL2Bus.trans_dist::ReadExReq 296457 # Transaction distribution 1205system.cpu.toL2Bus.trans_dist::ReadExResp 296457 # Transaction distribution 1206system.cpu.toL2Bus.trans_dist::ReadCleanReq 2892139 # Transaction distribution 1207system.cpu.toL2Bus.trans_dist::ReadSharedReq 549026 # Transaction distribution 1208system.cpu.toL2Bus.trans_dist::InvalidateReq 4412 # Transaction distribution 1209system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8682092 # Packet count per connected master and slave (bytes) 1210system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2658406 # Packet count per connected master and slave (bytes) 1211system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14762 # Packet count per connected master and slave (bytes) 1212system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159854 # Packet count per connected master and slave (bytes) 1213system.cpu.toL2Bus.pkt_count::total 11515114 # Packet count per connected master and slave (bytes) 1214system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370357376 # Cumulative packet size per connected master and slave (bytes) 1215system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99233193 # Cumulative packet size per connected master and slave (bytes) 1216system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13496 # Cumulative packet size per connected master and slave (bytes) 1217system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 274004 # Cumulative packet size per connected master and slave (bytes) 1218system.cpu.toL2Bus.pkt_size::total 469878069 # Cumulative packet size per connected master and slave (bytes) 1219system.cpu.toL2Bus.snoops 132782 # Total snoops (count) 1220system.cpu.toL2Bus.snoopTraffic 5798856 # Total snoop traffic (bytes) 1221system.cpu.toL2Bus.snoop_fanout::samples 4006498 # Request fanout histogram 1222system.cpu.toL2Bus.snoop_fanout::mean 0.022233 # Request fanout histogram 1223system.cpu.toL2Bus.snoop_fanout::stdev 0.147442 # Request fanout histogram | 1201system.cpu.toL2Bus.trans_dist::UpgradeResp 2823 # Transaction distribution 1202system.cpu.toL2Bus.trans_dist::ReadExReq 296076 # Transaction distribution 1203system.cpu.toL2Bus.trans_dist::ReadExResp 296076 # Transaction distribution 1204system.cpu.toL2Bus.trans_dist::ReadCleanReq 2889936 # Transaction distribution 1205system.cpu.toL2Bus.trans_dist::ReadSharedReq 548482 # Transaction distribution 1206system.cpu.toL2Bus.trans_dist::InvalidateReq 4413 # Transaction distribution 1207system.cpu.toL2Bus.trans_dist::InvalidateResp 16 # Transaction distribution 1208system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8675486 # Packet count per connected master and slave (bytes) 1209system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2655698 # Packet count per connected master and slave (bytes) 1210system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14711 # Packet count per connected master and slave (bytes) 1211system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158895 # Packet count per connected master and slave (bytes) 1212system.cpu.toL2Bus.pkt_count::total 11504790 # Packet count per connected master and slave (bytes) 1213system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370075584 # Cumulative packet size per connected master and slave (bytes) 1214system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99113193 # Cumulative packet size per connected master and slave (bytes) 1215system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13448 # Cumulative packet size per connected master and slave (bytes) 1216system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 271664 # Cumulative packet size per connected master and slave (bytes) 1217system.cpu.toL2Bus.pkt_size::total 469473889 # Cumulative packet size per connected master and slave (bytes) 1218system.cpu.toL2Bus.snoops 132758 # Total snoops (count) 1219system.cpu.toL2Bus.snoopTraffic 5779048 # Total snoop traffic (bytes) 1220system.cpu.toL2Bus.snoop_fanout::samples 4002764 # Request fanout histogram 1221system.cpu.toL2Bus.snoop_fanout::mean 0.022319 # Request fanout histogram 1222system.cpu.toL2Bus.snoop_fanout::stdev 0.147720 # Request fanout histogram |
| 1224system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1223system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1225system.cpu.toL2Bus.snoop_fanout::0 3917420 97.78% 97.78% # Request fanout histogram 1226system.cpu.toL2Bus.snoop_fanout::1 89078 2.22% 100.00% # Request fanout histogram | 1224system.cpu.toL2Bus.snoop_fanout::0 3913425 97.77% 97.77% # Request fanout histogram 1225system.cpu.toL2Bus.snoop_fanout::1 89339 2.23% 100.00% # Request fanout histogram |
| 1227system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1228system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1229system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1230system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 1226system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1227system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1228system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1229system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1231system.cpu.toL2Bus.snoop_fanout::total 4006498 # Request fanout histogram 1232system.cpu.toL2Bus.reqLayer0.occupancy 7428208500 # Layer occupancy (ticks) | 1230system.cpu.toL2Bus.snoop_fanout::total 4002764 # Request fanout histogram 1231system.cpu.toL2Bus.reqLayer0.occupancy 7421735500 # Layer occupancy (ticks) |
| 1233system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) | 1232system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) |
| 1234system.cpu.toL2Bus.snoopLayer0.occupancy 281377 # Layer occupancy (ticks) | 1233system.cpu.toL2Bus.snoopLayer0.occupancy 289875 # Layer occupancy (ticks) |
| 1235system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1234system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1236system.cpu.toL2Bus.respLayer0.occupancy 4343459350 # Layer occupancy (ticks) | 1235system.cpu.toL2Bus.respLayer0.occupancy 4340119421 # Layer occupancy (ticks) |
| 1237system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) | 1236system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) |
| 1238system.cpu.toL2Bus.respLayer1.occupancy 1314433554 # Layer occupancy (ticks) | 1237system.cpu.toL2Bus.respLayer1.occupancy 1313068534 # Layer occupancy (ticks) |
| 1239system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1238system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1240system.cpu.toL2Bus.respLayer2.occupancy 11390994 # Layer occupancy (ticks) | 1239system.cpu.toL2Bus.respLayer2.occupancy 11352493 # Layer occupancy (ticks) |
| 1241system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1240system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1242system.cpu.toL2Bus.respLayer3.occupancy 91384437 # Layer occupancy (ticks) | 1241system.cpu.toL2Bus.respLayer3.occupancy 91007942 # Layer occupancy (ticks) |
| 1243system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1242system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1244system.iobus.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states | 1243system.iobus.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states |
| 1245system.iobus.trans_dist::ReadReq 30183 # Transaction distribution 1246system.iobus.trans_dist::ReadResp 30183 # Transaction distribution 1247system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1248system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1249system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1250system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1251system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1252system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 34 unchanged lines hidden (view full) --- 1287system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1288system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1289system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1290system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1291system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) 1292system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 1293system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 1294system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) | 1244system.iobus.trans_dist::ReadReq 30183 # Transaction distribution 1245system.iobus.trans_dist::ReadResp 30183 # Transaction distribution 1246system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1247system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1248system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1249system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1250system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1251system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 34 unchanged lines hidden (view full) --- 1286system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1287system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1288system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1289system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1290system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) 1291system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 1292system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 1293system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) |
| 1295system.iobus.reqLayer0.occupancy 46308000 # Layer occupancy (ticks) | 1294system.iobus.reqLayer0.occupancy 46393500 # Layer occupancy (ticks) |
| 1296system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1297system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) 1298system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1295system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1296system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) 1297system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1299system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks) | 1298system.iobus.reqLayer2.occupancy 333000 # Layer occupancy (ticks) |
| 1300system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1301system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks) 1302system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1303system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) 1304system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) | 1299system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1300system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks) 1301system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1302system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) 1303system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 1305system.iobus.reqLayer7.occupancy 88500 # Layer occupancy (ticks) | 1304system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks) |
| 1306system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) | 1305system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) |
| 1307system.iobus.reqLayer8.occupancy 618500 # Layer occupancy (ticks) | 1306system.iobus.reqLayer8.occupancy 613000 # Layer occupancy (ticks) |
| 1308system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) | 1307system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) |
| 1309system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks) | 1308system.iobus.reqLayer10.occupancy 21500 # Layer occupancy (ticks) |
| 1310system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1311system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) 1312system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1313system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) 1314system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1315system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) 1316system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1317system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks) 1318system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1319system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) 1320system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1321system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 1322system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1323system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 1324system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1325system.iobus.reqLayer20.occupancy 10000 # Layer occupancy (ticks) 1326system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1327system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) 1328system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) | 1309system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1310system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) 1311system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1312system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) 1313system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1314system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) 1315system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1316system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks) 1317system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1318system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) 1319system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1320system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 1321system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1322system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 1323system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1324system.iobus.reqLayer20.occupancy 10000 # Layer occupancy (ticks) 1325system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1326system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) 1327system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) |
| 1329system.iobus.reqLayer23.occupancy 6088500 # Layer occupancy (ticks) | 1328system.iobus.reqLayer23.occupancy 6090000 # Layer occupancy (ticks) |
| 1330system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 1329system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| 1331system.iobus.reqLayer24.occupancy 39091500 # Layer occupancy (ticks) | 1330system.iobus.reqLayer24.occupancy 39095500 # Layer occupancy (ticks) |
| 1332system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 1331system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 1333system.iobus.reqLayer25.occupancy 187755828 # Layer occupancy (ticks) | 1332system.iobus.reqLayer25.occupancy 187683346 # Layer occupancy (ticks) |
| 1334system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1335system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1336system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1337system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) 1338system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 1333system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1334system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1335system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1336system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) 1337system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1339system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states | 1338system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states |
| 1340system.iocache.tags.replacements 36424 # number of replacements | 1339system.iocache.tags.replacements 36424 # number of replacements |
| 1341system.iocache.tags.tagsinuse 1.033906 # Cycle average of tags in use | 1340system.iocache.tags.tagsinuse 1.033754 # Cycle average of tags in use |
| 1342system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1343system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1344system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1341system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1342system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1343system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1345system.iocache.tags.warmup_cycle 272036495000 # Cycle when the warmup percentage was hit. 1346system.iocache.tags.occ_blocks::realview.ide 1.033906 # Average occupied blocks per requestor 1347system.iocache.tags.occ_percent::realview.ide 0.064619 # Average percentage of cache occupancy 1348system.iocache.tags.occ_percent::total 0.064619 # Average percentage of cache occupancy | 1344system.iocache.tags.warmup_cycle 272028370000 # Cycle when the warmup percentage was hit. 1345system.iocache.tags.occ_blocks::realview.ide 1.033754 # Average occupied blocks per requestor 1346system.iocache.tags.occ_percent::realview.ide 0.064610 # Average percentage of cache occupancy 1347system.iocache.tags.occ_percent::total 0.064610 # Average percentage of cache occupancy |
| 1349system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1350system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1351system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1352system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1353system.iocache.tags.data_accesses 328122 # Number of data accesses | 1348system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1349system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1350system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1351system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1352system.iocache.tags.data_accesses 328122 # Number of data accesses |
| 1354system.iocache.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states | 1353system.iocache.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states |
| 1355system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1356system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1357system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1358system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1359system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses 1360system.iocache.demand_misses::total 36458 # number of demand (read+write) misses 1361system.iocache.overall_misses::realview.ide 36458 # number of overall misses 1362system.iocache.overall_misses::total 36458 # number of overall misses | 1354system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1355system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1356system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1357system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1358system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses 1359system.iocache.demand_misses::total 36458 # number of demand (read+write) misses 1360system.iocache.overall_misses::realview.ide 36458 # number of overall misses 1361system.iocache.overall_misses::total 36458 # number of overall misses |
| 1363system.iocache.ReadReq_miss_latency::realview.ide 37411877 # number of ReadReq miss cycles 1364system.iocache.ReadReq_miss_latency::total 37411877 # number of ReadReq miss cycles 1365system.iocache.WriteLineReq_miss_latency::realview.ide 4363182951 # number of WriteLineReq miss cycles 1366system.iocache.WriteLineReq_miss_latency::total 4363182951 # number of WriteLineReq miss cycles 1367system.iocache.demand_miss_latency::realview.ide 4400594828 # number of demand (read+write) miss cycles 1368system.iocache.demand_miss_latency::total 4400594828 # number of demand (read+write) miss cycles 1369system.iocache.overall_miss_latency::realview.ide 4400594828 # number of overall miss cycles 1370system.iocache.overall_miss_latency::total 4400594828 # number of overall miss cycles | 1362system.iocache.ReadReq_miss_latency::realview.ide 29456377 # number of ReadReq miss cycles 1363system.iocache.ReadReq_miss_latency::total 29456377 # number of ReadReq miss cycles 1364system.iocache.WriteLineReq_miss_latency::realview.ide 4371874969 # number of WriteLineReq miss cycles 1365system.iocache.WriteLineReq_miss_latency::total 4371874969 # number of WriteLineReq miss cycles 1366system.iocache.demand_miss_latency::realview.ide 4401331346 # number of demand (read+write) miss cycles 1367system.iocache.demand_miss_latency::total 4401331346 # number of demand (read+write) miss cycles 1368system.iocache.overall_miss_latency::realview.ide 4401331346 # number of overall miss cycles 1369system.iocache.overall_miss_latency::total 4401331346 # number of overall miss cycles |
| 1371system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1372system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1373system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1374system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1375system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses 1376system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses 1377system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses 1378system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses 1379system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1380system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1381system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1382system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1383system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1384system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1385system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1386system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1370system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1371system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1372system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1373system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1374system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses 1375system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses 1376system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses 1377system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses 1378system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1379system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1380system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1381system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1382system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1383system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1384system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1385system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1387system.iocache.ReadReq_avg_miss_latency::realview.ide 159879.816239 # average ReadReq miss latency 1388system.iocache.ReadReq_avg_miss_latency::total 159879.816239 # average ReadReq miss latency 1389system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120450.059381 # average WriteLineReq miss latency 1390system.iocache.WriteLineReq_avg_miss_latency::total 120450.059381 # average WriteLineReq miss latency 1391system.iocache.demand_avg_miss_latency::realview.ide 120703.133140 # average overall miss latency 1392system.iocache.demand_avg_miss_latency::total 120703.133140 # average overall miss latency 1393system.iocache.overall_avg_miss_latency::realview.ide 120703.133140 # average overall miss latency 1394system.iocache.overall_avg_miss_latency::total 120703.133140 # average overall miss latency | 1386system.iocache.ReadReq_avg_miss_latency::realview.ide 125881.952991 # average ReadReq miss latency 1387system.iocache.ReadReq_avg_miss_latency::total 125881.952991 # average ReadReq miss latency 1388system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120690.011291 # average WriteLineReq miss latency 1389system.iocache.WriteLineReq_avg_miss_latency::total 120690.011291 # average WriteLineReq miss latency 1390system.iocache.demand_avg_miss_latency::realview.ide 120723.334961 # average overall miss latency 1391system.iocache.demand_avg_miss_latency::total 120723.334961 # average overall miss latency 1392system.iocache.overall_avg_miss_latency::realview.ide 120723.334961 # average overall miss latency 1393system.iocache.overall_avg_miss_latency::total 120723.334961 # average overall miss latency |
| 1395system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1396system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1397system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1398system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1399system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1400system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1401system.iocache.writebacks::writebacks 36190 # number of writebacks 1402system.iocache.writebacks::total 36190 # number of writebacks 1403system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1404system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1405system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1406system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 1407system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses 1408system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses 1409system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses 1410system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses | 1394system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1395system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1396system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1397system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1398system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1399system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1400system.iocache.writebacks::writebacks 36190 # number of writebacks 1401system.iocache.writebacks::total 36190 # number of writebacks 1402system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1403system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1404system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1405system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 1406system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses 1407system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses 1408system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses 1409system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses |
| 1411system.iocache.ReadReq_mshr_miss_latency::realview.ide 25711877 # number of ReadReq MSHR miss cycles 1412system.iocache.ReadReq_mshr_miss_latency::total 25711877 # number of ReadReq MSHR miss cycles 1413system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2549871160 # number of WriteLineReq MSHR miss cycles 1414system.iocache.WriteLineReq_mshr_miss_latency::total 2549871160 # number of WriteLineReq MSHR miss cycles 1415system.iocache.demand_mshr_miss_latency::realview.ide 2575583037 # number of demand (read+write) MSHR miss cycles 1416system.iocache.demand_mshr_miss_latency::total 2575583037 # number of demand (read+write) MSHR miss cycles 1417system.iocache.overall_mshr_miss_latency::realview.ide 2575583037 # number of overall MSHR miss cycles 1418system.iocache.overall_mshr_miss_latency::total 2575583037 # number of overall MSHR miss cycles | 1410system.iocache.ReadReq_mshr_miss_latency::realview.ide 17756377 # number of ReadReq MSHR miss cycles 1411system.iocache.ReadReq_mshr_miss_latency::total 17756377 # number of ReadReq MSHR miss cycles 1412system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2558822831 # number of WriteLineReq MSHR miss cycles 1413system.iocache.WriteLineReq_mshr_miss_latency::total 2558822831 # number of WriteLineReq MSHR miss cycles 1414system.iocache.demand_mshr_miss_latency::realview.ide 2576579208 # number of demand (read+write) MSHR miss cycles 1415system.iocache.demand_mshr_miss_latency::total 2576579208 # number of demand (read+write) MSHR miss cycles 1416system.iocache.overall_mshr_miss_latency::realview.ide 2576579208 # number of overall MSHR miss cycles 1417system.iocache.overall_mshr_miss_latency::total 2576579208 # number of overall MSHR miss cycles |
| 1419system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1420system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1421system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1422system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1423system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1424system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1425system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1426system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1418system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1419system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1420system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1421system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1422system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1423system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1424system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1425system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1427system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 109879.816239 # average ReadReq mshr miss latency 1428system.iocache.ReadReq_avg_mshr_miss_latency::total 109879.816239 # average ReadReq mshr miss latency 1429system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70391.761263 # average WriteLineReq mshr miss latency 1430system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70391.761263 # average WriteLineReq mshr miss latency 1431system.iocache.demand_avg_mshr_miss_latency::realview.ide 70645.209200 # average overall mshr miss latency 1432system.iocache.demand_avg_mshr_miss_latency::total 70645.209200 # average overall mshr miss latency 1433system.iocache.overall_avg_mshr_miss_latency::realview.ide 70645.209200 # average overall mshr miss latency 1434system.iocache.overall_avg_mshr_miss_latency::total 70645.209200 # average overall mshr miss latency 1435system.membus.snoop_filter.tot_requests 337068 # Total number of requests made to the snoop filter. 1436system.membus.snoop_filter.hit_single_requests 138136 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1437system.membus.snoop_filter.hit_multi_requests 489 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 1426system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75881.952991 # average ReadReq mshr miss latency 1427system.iocache.ReadReq_avg_mshr_miss_latency::total 75881.952991 # average ReadReq mshr miss latency 1428system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70638.881156 # average WriteLineReq mshr miss latency 1429system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70638.881156 # average WriteLineReq mshr miss latency 1430system.iocache.demand_avg_mshr_miss_latency::realview.ide 70672.532997 # average overall mshr miss latency 1431system.iocache.demand_avg_mshr_miss_latency::total 70672.532997 # average overall mshr miss latency 1432system.iocache.overall_avg_mshr_miss_latency::realview.ide 70672.532997 # average overall mshr miss latency 1433system.iocache.overall_avg_mshr_miss_latency::total 70672.532997 # average overall mshr miss latency 1434system.membus.snoop_filter.tot_requests 336642 # Total number of requests made to the snoop filter. 1435system.membus.snoop_filter.hit_single_requests 137901 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1436system.membus.snoop_filter.hit_multi_requests 539 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1438system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1439system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1440system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1437system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1438system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1439system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1441system.membus.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states | 1440system.membus.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states |
| 1442system.membus.trans_dist::ReadReq 34249 # Transaction distribution | 1441system.membus.trans_dist::ReadReq 34249 # Transaction distribution |
| 1443system.membus.trans_dist::ReadResp 71739 # Transaction distribution | 1442system.membus.trans_dist::ReadResp 71720 # Transaction distribution |
| 1444system.membus.trans_dist::WriteReq 27584 # Transaction distribution 1445system.membus.trans_dist::WriteResp 27584 # Transaction distribution | 1443system.membus.trans_dist::WriteReq 27584 # Transaction distribution 1444system.membus.trans_dist::WriteResp 27584 # Transaction distribution |
| 1446system.membus.trans_dist::WritebackDirty 124683 # Transaction distribution 1447system.membus.trans_dist::CleanEvict 8839 # Transaction distribution | 1445system.membus.trans_dist::WritebackDirty 124364 # Transaction distribution 1446system.membus.trans_dist::CleanEvict 8933 # Transaction distribution |
| 1448system.membus.trans_dist::UpgradeReq 128 # Transaction distribution 1449system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1450system.membus.trans_dist::UpgradeResp 2 # Transaction distribution | 1447system.membus.trans_dist::UpgradeReq 128 # Transaction distribution 1448system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1449system.membus.trans_dist::UpgradeResp 2 # Transaction distribution |
| 1451system.membus.trans_dist::ReadExReq 129646 # Transaction distribution 1452system.membus.trans_dist::ReadExResp 129646 # Transaction distribution 1453system.membus.trans_dist::ReadSharedReq 37490 # Transaction distribution | 1450system.membus.trans_dist::ReadExReq 129451 # Transaction distribution 1451system.membus.trans_dist::ReadExResp 129451 # Transaction distribution 1452system.membus.trans_dist::ReadSharedReq 37471 # Transaction distribution |
| 1454system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution | 1453system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution |
| 1454system.membus.trans_dist::InvalidateResp 4363 # Transaction distribution |
|
| 1455system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1456system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) 1457system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes) | 1455system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1456system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) 1457system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes) |
| 1458system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446846 # Packet count per connected master and slave (bytes) 1459system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554414 # Packet count per connected master and slave (bytes) | 1458system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446194 # Packet count per connected master and slave (bytes) 1459system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553762 # Packet count per connected master and slave (bytes) |
| 1460system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) 1461system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) | 1460system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) 1461system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) |
| 1462system.membus.pkt_count::total 627311 # Packet count per connected master and slave (bytes) | 1462system.membus.pkt_count::total 626659 # Packet count per connected master and slave (bytes) |
| 1463system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1464system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) 1465system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes) | 1463system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1464system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) 1465system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes) |
| 1466system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16546016 # Cumulative packet size per connected master and slave (bytes) 1467system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16709801 # Cumulative packet size per connected master and slave (bytes) | 1466system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16511968 # Cumulative packet size per connected master and slave (bytes) 1467system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16675753 # Cumulative packet size per connected master and slave (bytes) |
| 1468system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1469system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) | 1468system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1469system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) |
| 1470system.membus.pkt_size::total 19026921 # Cumulative packet size per connected master and slave (bytes) 1471system.membus.snoops 505 # Total snoops (count) 1472system.membus.snoopTraffic 32192 # Total snoop traffic (bytes) 1473system.membus.snoop_fanout::samples 265323 # Request fanout histogram 1474system.membus.snoop_fanout::mean 0.018540 # Request fanout histogram 1475system.membus.snoop_fanout::stdev 0.134893 # Request fanout histogram | 1470system.membus.pkt_size::total 18992873 # Cumulative packet size per connected master and slave (bytes) 1471system.membus.snoops 4867 # Total snoops (count) 1472system.membus.snoopTraffic 32128 # Total snoop traffic (bytes) 1473system.membus.snoop_fanout::samples 265109 # Request fanout histogram 1474system.membus.snoop_fanout::mean 0.018562 # Request fanout histogram 1475system.membus.snoop_fanout::stdev 0.134973 # Request fanout histogram |
| 1476system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1476system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1477system.membus.snoop_fanout::0 260404 98.15% 98.15% # Request fanout histogram 1478system.membus.snoop_fanout::1 4919 1.85% 100.00% # Request fanout histogram | 1477system.membus.snoop_fanout::0 260188 98.14% 98.14% # Request fanout histogram 1478system.membus.snoop_fanout::1 4921 1.86% 100.00% # Request fanout histogram |
| 1479system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1480system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1481system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1482system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1479system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1480system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1481system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1482system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1483system.membus.snoop_fanout::total 265323 # Request fanout histogram 1484system.membus.reqLayer0.occupancy 92820000 # Layer occupancy (ticks) | 1483system.membus.snoop_fanout::total 265109 # Request fanout histogram 1484system.membus.reqLayer0.occupancy 92913500 # Layer occupancy (ticks) |
| 1485system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1486system.membus.reqLayer1.occupancy 8000 # Layer occupancy (ticks) 1487system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1485system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1486system.membus.reqLayer1.occupancy 8000 # Layer occupancy (ticks) 1487system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1488system.membus.reqLayer2.occupancy 1700500 # Layer occupancy (ticks) | 1488system.membus.reqLayer2.occupancy 1698000 # Layer occupancy (ticks) |
| 1489system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1489system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1490system.membus.reqLayer5.occupancy 905922529 # Layer occupancy (ticks) | 1490system.membus.reqLayer5.occupancy 904283412 # Layer occupancy (ticks) |
| 1491system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 1491system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 1492system.membus.respLayer2.occupancy 989794500 # Layer occupancy (ticks) | 1492system.membus.respLayer2.occupancy 988660500 # Layer occupancy (ticks) |
| 1493system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1493system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1494system.membus.respLayer3.occupancy 1230123 # Layer occupancy (ticks) | 1494system.membus.respLayer3.occupancy 5813415 # Layer occupancy (ticks) |
| 1495system.membus.respLayer3.utilization 0.0 # Layer utilization (%) | 1495system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1496system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1497system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1498system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1499system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1500system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1501system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1502system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states | 1496system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1497system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1498system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1499system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1500system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1501system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1502system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states |
| 1503system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1504system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1505system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1506system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1507system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1508system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 1503system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1504system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1505system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1506system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1507system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1508system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 1509system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1510system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states | 1509system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1510system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states |
| 1511system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1512system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1513system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1514system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1515system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1516system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1517system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1518system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1534system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1535system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1536system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1537system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1538system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1539system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1540system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1541system.realview.ethernet.droppedPackets 0 # number of packets dropped | 1511system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1512system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1513system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1514system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1515system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1516system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1517system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1518system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1534system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1535system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1536system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1537system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1538system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1539system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1540system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1541system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 1542system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1543system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1544system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1545system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1546system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1547system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1548system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states | 1542system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1543system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1544system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1545system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1546system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1547system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1548system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states |
| 1549system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1550system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1551system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1552system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 1549system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1550system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1551system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1552system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 1553system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1554system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1555system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1556system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1557system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1558system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1559system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1560system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1561system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1562system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1563system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states 1564system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states | 1553system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1554system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1555system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1556system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1557system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1558system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1559system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1560system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1561system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1562system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1563system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states 1564system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states |
| 1565 1566---------- End Simulation Statistics ---------- | 1565 1566---------- End Simulation Statistics ---------- |