| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.858997 # Number of seconds simulated 4sim_ticks 2858997339500 # Number of ticks simulated 5final_tick 2858997339500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.853344 # Number of seconds simulated 4sim_ticks 2853343899500 # Number of ticks simulated 5final_tick 2853343899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 120078 # Simulator instruction rate (inst/s) 8host_op_rate 145187 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3059253370 # Simulator tick rate (ticks/s) 10host_mem_usage 579060 # Number of bytes of host memory used 11host_seconds 934.54 # Real time elapsed on the host 12sim_insts 112217626 # Number of instructions simulated 13sim_ops 135683579 # Number of ops (including micro ops) simulated | 7host_inst_rate 139312 # Simulator instruction rate (inst/s) 8host_op_rate 168444 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3544495637 # Simulator tick rate (ticks/s) 10host_mem_usage 589148 # Number of bytes of host memory used 11host_seconds 805.01 # Real time elapsed on the host 12sim_insts 112146750 # Number of instructions simulated 13sim_ops 135598813 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 8000 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1706880 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9150764 # Number of bytes read from this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 7680 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1675712 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9177004 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 22system.physmem.bytes_read::total 10866732 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1706880 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1706880 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7954240 # Number of bytes written to this memory | 22system.physmem.bytes_read::total 10861420 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1675712 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1675712 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7976832 # Number of bytes written to this memory |
| 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory | 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory |
| 27system.physmem.bytes_written::total 7971764 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 125 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 26670 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 143502 # Number of read requests responded to by this memory | 27system.physmem.bytes_written::total 7994356 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 120 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 26183 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 143912 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 33system.physmem.num_reads::total 170314 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 124285 # Number of write requests responded to by this memory | 33system.physmem.num_reads::total 170231 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 124638 # Number of write requests responded to by this memory |
| 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory | 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory |
| 36system.physmem.num_writes::total 128666 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 2798 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 597020 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3200690 # Total read bandwidth from this memory (bytes/s) | 36system.physmem.num_writes::total 129019 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 2692 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 587280 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3216228 # Total read bandwidth from this memory (bytes/s) |
| 41system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) | 41system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) |
| 42system.physmem.bw_read::total 3800889 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 597020 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 597020 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2782178 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 6129 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 2788308 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2782178 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 2798 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 597020 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 3206819 # Total bandwidth to/from this memory (bytes/s) | 42system.physmem.bw_read::total 3806558 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 587280 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 587280 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2795608 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 6142 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 2801750 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2795608 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 2692 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 587280 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 3222369 # Total bandwidth to/from this memory (bytes/s) |
| 53system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) | 53system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) |
| 54system.physmem.bw_total::total 6589197 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 170314 # Number of read requests accepted 56system.physmem.writeReqs 128666 # Number of write requests accepted 57system.physmem.readBursts 170314 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 128666 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 10892160 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 7936 # Total number of bytes read from write queue 61system.physmem.bytesWritten 7984576 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 10866732 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 7971764 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 124 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one | 54system.physmem.bw_total::total 6608308 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 170231 # Number of read requests accepted 56system.physmem.writeReqs 129019 # Number of write requests accepted 57system.physmem.readBursts 170231 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 129019 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 10886144 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue 61system.physmem.bytesWritten 8006976 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 10861420 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 7994356 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one |
| 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 67system.physmem.perBankRdBursts::0 10846 # Per bank write bursts 68system.physmem.perBankRdBursts::1 10861 # Per bank write bursts 69system.physmem.perBankRdBursts::2 10970 # Per bank write bursts 70system.physmem.perBankRdBursts::3 10944 # Per bank write bursts 71system.physmem.perBankRdBursts::4 13948 # Per bank write bursts 72system.physmem.perBankRdBursts::5 10354 # Per bank write bursts 73system.physmem.perBankRdBursts::6 10606 # Per bank write bursts 74system.physmem.perBankRdBursts::7 10917 # Per bank write bursts 75system.physmem.perBankRdBursts::8 10091 # Per bank write bursts 76system.physmem.perBankRdBursts::9 10226 # Per bank write bursts 77system.physmem.perBankRdBursts::10 9938 # Per bank write bursts 78system.physmem.perBankRdBursts::11 9330 # Per bank write bursts 79system.physmem.perBankRdBursts::12 10171 # Per bank write bursts 80system.physmem.perBankRdBursts::13 10932 # Per bank write bursts 81system.physmem.perBankRdBursts::14 10237 # Per bank write bursts 82system.physmem.perBankRdBursts::15 9819 # Per bank write bursts 83system.physmem.perBankWrBursts::0 8179 # Per bank write bursts 84system.physmem.perBankWrBursts::1 8215 # Per bank write bursts 85system.physmem.perBankWrBursts::2 8623 # Per bank write bursts 86system.physmem.perBankWrBursts::3 8456 # Per bank write bursts 87system.physmem.perBankWrBursts::4 7543 # Per bank write bursts 88system.physmem.perBankWrBursts::5 7549 # Per bank write bursts 89system.physmem.perBankWrBursts::6 7648 # Per bank write bursts 90system.physmem.perBankWrBursts::7 8016 # Per bank write bursts 91system.physmem.perBankWrBursts::8 7706 # Per bank write bursts 92system.physmem.perBankWrBursts::9 7733 # Per bank write bursts 93system.physmem.perBankWrBursts::10 7506 # Per bank write bursts 94system.physmem.perBankWrBursts::11 7211 # Per bank write bursts 95system.physmem.perBankWrBursts::12 7604 # Per bank write bursts 96system.physmem.perBankWrBursts::13 8124 # Per bank write bursts 97system.physmem.perBankWrBursts::14 7522 # Per bank write bursts 98system.physmem.perBankWrBursts::15 7124 # Per bank write bursts | 67system.physmem.perBankRdBursts::0 10508 # Per bank write bursts 68system.physmem.perBankRdBursts::1 10518 # Per bank write bursts 69system.physmem.perBankRdBursts::2 10699 # Per bank write bursts 70system.physmem.perBankRdBursts::3 10590 # Per bank write bursts 71system.physmem.perBankRdBursts::4 13367 # Per bank write bursts 72system.physmem.perBankRdBursts::5 10649 # Per bank write bursts 73system.physmem.perBankRdBursts::6 10947 # Per bank write bursts 74system.physmem.perBankRdBursts::7 11320 # Per bank write bursts 75system.physmem.perBankRdBursts::8 10289 # Per bank write bursts 76system.physmem.perBankRdBursts::9 10353 # Per bank write bursts 77system.physmem.perBankRdBursts::10 10214 # Per bank write bursts 78system.physmem.perBankRdBursts::11 9210 # Per bank write bursts 79system.physmem.perBankRdBursts::12 10497 # Per bank write bursts 80system.physmem.perBankRdBursts::13 11112 # Per bank write bursts 81system.physmem.perBankRdBursts::14 10041 # Per bank write bursts 82system.physmem.perBankRdBursts::15 9782 # Per bank write bursts 83system.physmem.perBankWrBursts::0 7781 # Per bank write bursts 84system.physmem.perBankWrBursts::1 7920 # Per bank write bursts 85system.physmem.perBankWrBursts::2 8383 # Per bank write bursts 86system.physmem.perBankWrBursts::3 8149 # Per bank write bursts 87system.physmem.perBankWrBursts::4 7457 # Per bank write bursts 88system.physmem.perBankWrBursts::5 7755 # Per bank write bursts 89system.physmem.perBankWrBursts::6 7974 # Per bank write bursts 90system.physmem.perBankWrBursts::7 8419 # Per bank write bursts 91system.physmem.perBankWrBursts::8 7882 # Per bank write bursts 92system.physmem.perBankWrBursts::9 7909 # Per bank write bursts 93system.physmem.perBankWrBursts::10 7627 # Per bank write bursts 94system.physmem.perBankWrBursts::11 7117 # Per bank write bursts 95system.physmem.perBankWrBursts::12 7926 # Per bank write bursts 96system.physmem.perBankWrBursts::13 8274 # Per bank write bursts 97system.physmem.perBankWrBursts::14 7391 # Per bank write bursts 98system.physmem.perBankWrBursts::15 7145 # Per bank write bursts |
| 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 100system.physmem.numWrRetry 12 # Number of times write queue was full causing retry 101system.physmem.totGap 2858996896000 # Total gap between requests | 100system.physmem.numWrRetry 4 # Number of times write queue was full causing retry 101system.physmem.totGap 2853343449000 # Total gap between requests |
| 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 543 # Read request sizes (log2) 105system.physmem.readPktSize::3 14 # Read request sizes (log2) 106system.physmem.readPktSize::4 0 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) | 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 543 # Read request sizes (log2) 105system.physmem.readPktSize::3 14 # Read request sizes (log2) 106system.physmem.readPktSize::4 0 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 108system.physmem.readPktSize::6 169757 # Read request sizes (log2) | 108system.physmem.readPktSize::6 169674 # Read request sizes (log2) |
| 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 4381 # Write request sizes (log2) 112system.physmem.writePktSize::3 0 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) | 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 4381 # Write request sizes (log2) 112system.physmem.writePktSize::3 0 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 115system.physmem.writePktSize::6 124285 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 162889 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 7005 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 284 # What read queue length does an incoming req see | 115system.physmem.writePktSize::6 124638 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 162184 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 7619 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 281 # What read queue length does an incoming req see |
| 119system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 119system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 163system.physmem.wrQLenPdf::15 1874 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 2917 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 7032 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 6365 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 7124 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 6452 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 6411 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 6488 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 7149 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 6917 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 7499 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 8410 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 7380 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 7541 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 8938 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 7440 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 7263 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 7210 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 1257 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 273 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 223 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 162 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 114 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 134 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 110 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 158 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 121 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 156 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 136 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 172 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 92 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 100 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 79 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 59 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 91 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 79 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 84 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 75 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 62 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 67 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 48 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 39 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 61663 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 306.126397 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 182.384465 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 323.388642 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 22560 36.59% 36.59% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 14992 24.31% 60.90% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 6700 10.87% 71.76% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 3651 5.92% 77.69% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 2898 4.70% 82.38% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 1667 2.70% 85.09% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 1045 1.69% 86.78% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 1093 1.77% 88.56% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 7057 11.44% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 61663 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 6083 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 27.977314 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 575.322656 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-2047 6082 99.98% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 6083 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 6083 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 20.509453 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.487861 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 14.653648 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 5420 89.10% 89.10% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 90 1.48% 90.58% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 39 0.64% 91.22% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 27 0.44% 91.67% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 35 0.58% 92.24% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 16 0.26% 92.50% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 41 0.67% 93.18% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 7 0.12% 93.29% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 151 2.48% 95.78% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 6 0.10% 95.87% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 8 0.13% 96.01% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 13 0.21% 96.22% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 69 1.13% 97.35% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 4 0.07% 97.42% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 3 0.05% 97.47% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 36 0.59% 98.06% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 90 1.48% 99.54% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::84-87 2 0.03% 99.57% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::92-95 1 0.02% 99.59% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::112-115 1 0.02% 99.61% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::128-131 10 0.16% 99.77% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::136-139 1 0.02% 99.79% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::140-143 2 0.03% 99.82% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::144-147 3 0.05% 99.87% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::152-155 1 0.02% 99.88% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::156-159 1 0.02% 99.90% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::176-179 2 0.03% 99.93% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::188-191 3 0.05% 99.98% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::208-211 1 0.02% 100.00% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::total 6083 # Writes before turning the bus around for reads 266system.physmem.totQLat 1877618250 # Total ticks spent queuing 267system.physmem.totMemAccLat 5068680750 # Total ticks spent from burst creation until serviced by the DRAM 268system.physmem.totBusLat 850950000 # Total ticks spent in databus transfers 269system.physmem.avgQLat 11032.48 # Average queueing delay per DRAM burst | 163system.physmem.wrQLenPdf::15 1927 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 2883 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 6085 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 6461 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 6753 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 6440 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 6861 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 7240 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 7833 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 7817 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 8977 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 9286 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 7605 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 7322 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 7382 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 6746 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 6645 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 6645 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 340 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 300 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 278 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 175 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 200 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 165 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 179 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 135 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 160 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 124 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 165 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 130 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 171 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 175 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 126 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 185 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 158 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 107 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 92 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 118 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 89 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 85 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 86 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 87 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 58 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 49 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 32 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 60538 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 312.085896 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 184.679507 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 329.366687 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 22012 36.36% 36.36% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 14640 24.18% 60.54% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 6552 10.82% 71.37% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 3435 5.67% 77.04% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 2639 4.36% 81.40% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 1745 2.88% 84.28% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 1057 1.75% 86.03% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 1062 1.75% 87.78% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 7396 12.22% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 60538 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 6241 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 27.253805 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 580.495916 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-2047 6239 99.97% 99.97% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 6241 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 6241 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 20.046307 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 18.379346 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 13.281323 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-19 5473 87.69% 87.69% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::20-23 55 0.88% 88.58% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24-27 66 1.06% 89.63% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::28-31 37 0.59% 90.23% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::32-35 284 4.55% 94.78% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::36-39 48 0.77% 95.55% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::40-43 17 0.27% 95.82% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::44-47 11 0.18% 95.99% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::48-51 9 0.14% 96.14% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::52-55 6 0.10% 96.23% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::56-59 4 0.06% 96.30% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::60-63 13 0.21% 96.51% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::64-67 157 2.52% 99.02% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::68-71 4 0.06% 99.09% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::72-75 3 0.05% 99.13% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::76-79 5 0.08% 99.21% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::80-83 5 0.08% 99.29% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::84-87 2 0.03% 99.33% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::92-95 1 0.02% 99.34% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::96-99 4 0.06% 99.41% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::100-103 1 0.02% 99.42% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::104-107 1 0.02% 99.44% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::108-111 8 0.13% 99.57% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::128-131 15 0.24% 99.81% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::140-143 2 0.03% 99.84% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::148-151 1 0.02% 99.86% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::156-159 1 0.02% 99.87% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::160-163 2 0.03% 99.90% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::164-167 1 0.02% 99.92% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::172-175 3 0.05% 99.97% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::184-187 1 0.02% 99.98% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::total 6241 # Writes before turning the bus around for reads 270system.physmem.totQLat 1691091750 # Total ticks spent queuing 271system.physmem.totMemAccLat 4880391750 # Total ticks spent from burst creation until serviced by the DRAM 272system.physmem.totBusLat 850480000 # Total ticks spent in databus transfers 273system.physmem.avgQLat 9941.98 # Average queueing delay per DRAM burst |
| 270system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 274system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 271system.physmem.avgMemAccLat 29782.48 # Average memory access latency per DRAM burst 272system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s 273system.physmem.avgWrBW 2.79 # Average achieved write bandwidth in MiByte/s 274system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s 275system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s | 275system.physmem.avgMemAccLat 28691.98 # Average memory access latency per DRAM burst 276system.physmem.avgRdBW 3.82 # Average DRAM read bandwidth in MiByte/s 277system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s 278system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s 279system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s |
| 276system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 277system.physmem.busUtil 0.05 # Data bus utilization in percentage 278system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 279system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes | 280system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 281system.physmem.busUtil 0.05 # Data bus utilization in percentage 282system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 283system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes |
| 280system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 281system.physmem.avgWrQLen 24.79 # Average write queue length when enqueuing 282system.physmem.readRowHits 139443 # Number of row buffer hits during reads 283system.physmem.writeRowHits 93842 # Number of row buffer hits during writes 284system.physmem.readRowHitRate 81.93 # Row buffer hit rate for reads 285system.physmem.writeRowHitRate 75.21 # Row buffer hit rate for writes 286system.physmem.avgGap 9562502.16 # Average gap between requests 287system.physmem.pageHitRate 79.09 # Row buffer hit rate, read and write combined 288system.physmem_0.actEnergy 244104840 # Energy for activate commands per rank (pJ) 289system.physmem_0.preEnergy 133192125 # Energy for precharge commands per rank (pJ) 290system.physmem_0.readEnergy 697678800 # Energy for read commands per rank (pJ) 291system.physmem_0.writeEnergy 416203920 # Energy for write commands per rank (pJ) 292system.physmem_0.refreshEnergy 186735603600 # Energy for refresh commands per rank (pJ) 293system.physmem_0.actBackEnergy 86851227465 # Energy for active background per rank (pJ) 294system.physmem_0.preBackEnergy 1639211384250 # Energy for precharge background per rank (pJ) 295system.physmem_0.totalEnergy 1914289395000 # Total energy per rank (pJ) 296system.physmem_0.averagePower 669.567370 # Core power per rank (mW) 297system.physmem_0.memoryStateTime::IDLE 2726812979000 # Time in different power states 298system.physmem_0.memoryStateTime::REF 95468100000 # Time in different power states | 284system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 285system.physmem.avgWrQLen 26.93 # Average write queue length when enqueuing 286system.physmem.readRowHits 140142 # Number of row buffer hits during reads 287system.physmem.writeRowHits 94524 # Number of row buffer hits during writes 288system.physmem.readRowHitRate 82.39 # Row buffer hit rate for reads 289system.physmem.writeRowHitRate 75.54 # Row buffer hit rate for writes 290system.physmem.avgGap 9534982.29 # Average gap between requests 291system.physmem.pageHitRate 79.49 # Row buffer hit rate, read and write combined 292system.physmem_0.actEnergy 235894680 # Energy for activate commands per rank (pJ) 293system.physmem_0.preEnergy 128712375 # Energy for precharge commands per rank (pJ) 294system.physmem_0.readEnergy 691064400 # Energy for read commands per rank (pJ) 295system.physmem_0.writeEnergy 413670240 # Energy for write commands per rank (pJ) 296system.physmem_0.refreshEnergy 186366389040 # Energy for refresh commands per rank (pJ) 297system.physmem_0.actBackEnergy 83561921055 # Energy for active background per rank (pJ) 298system.physmem_0.preBackEnergy 1638705050250 # Energy for precharge background per rank (pJ) 299system.physmem_0.totalEnergy 1910102702040 # Total energy per rank (pJ) 300system.physmem_0.averagePower 669.426569 # Core power per rank (mW) 301system.physmem_0.memoryStateTime::IDLE 2725994839000 # Time in different power states 302system.physmem_0.memoryStateTime::REF 95279340000 # Time in different power states |
| 299system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 303system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 300system.physmem_0.memoryStateTime::ACT 36713387250 # Time in different power states | 304system.physmem_0.memoryStateTime::ACT 32067469750 # Time in different power states |
| 301system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 305system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 302system.physmem_1.actEnergy 222067440 # Energy for activate commands per rank (pJ) 303system.physmem_1.preEnergy 121167750 # Energy for precharge commands per rank (pJ) 304system.physmem_1.readEnergy 629795400 # Energy for read commands per rank (pJ) 305system.physmem_1.writeEnergy 392234400 # Energy for write commands per rank (pJ) 306system.physmem_1.refreshEnergy 186735603600 # Energy for refresh commands per rank (pJ) 307system.physmem_1.actBackEnergy 85246386480 # Energy for active background per rank (pJ) 308system.physmem_1.preBackEnergy 1640619139500 # Energy for precharge background per rank (pJ) 309system.physmem_1.totalEnergy 1913966394570 # Total energy per rank (pJ) 310system.physmem_1.averagePower 669.454393 # Core power per rank (mW) 311system.physmem_1.memoryStateTime::IDLE 2729170897750 # Time in different power states 312system.physmem_1.memoryStateTime::REF 95468100000 # Time in different power states | 306system.physmem_1.actEnergy 221772600 # Energy for activate commands per rank (pJ) 307system.physmem_1.preEnergy 121006875 # Energy for precharge commands per rank (pJ) 308system.physmem_1.readEnergy 635676600 # Energy for read commands per rank (pJ) 309system.physmem_1.writeEnergy 397036080 # Energy for write commands per rank (pJ) 310system.physmem_1.refreshEnergy 186366389040 # Energy for refresh commands per rank (pJ) 311system.physmem_1.actBackEnergy 82367679285 # Energy for active background per rank (pJ) 312system.physmem_1.preBackEnergy 1639752630750 # Energy for precharge background per rank (pJ) 313system.physmem_1.totalEnergy 1909862191230 # Total energy per rank (pJ) 314system.physmem_1.averagePower 669.342278 # Core power per rank (mW) 315system.physmem_1.memoryStateTime::IDLE 2727746913750 # Time in different power states 316system.physmem_1.memoryStateTime::REF 95279340000 # Time in different power states |
| 313system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 317system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 314system.physmem_1.memoryStateTime::ACT 34358196250 # Time in different power states | 318system.physmem_1.memoryStateTime::ACT 30317548250 # Time in different power states |
| 315system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 319system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 316system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states | 320system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states |
| 317system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory 318system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory 319system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory 320system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory 321system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 322system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 323system.realview.nvmem.bw_read::cpu.inst 179 # Total read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_read::total 179 # Total read bandwidth from this memory (bytes/s) 325system.realview.nvmem.bw_inst_read::cpu.inst 179 # Instruction read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s) 327system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s) 328system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s) | 321system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory 322system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory 323system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory 324system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory 325system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 326system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 327system.realview.nvmem.bw_read::cpu.inst 179 # Total read bandwidth from this memory (bytes/s) 328system.realview.nvmem.bw_read::total 179 # Total read bandwidth from this memory (bytes/s) 329system.realview.nvmem.bw_inst_read::cpu.inst 179 # Instruction read bandwidth from this memory (bytes/s) 330system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s) 331system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s) 332system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s) |
| 329system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 330system.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 331system.bridge.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states | 333system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 334system.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 335system.bridge.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states |
| 332system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 333system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 334system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 335system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 336system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 337system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 336system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 337system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 338system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 339system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 340system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 341system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 338system.cpu.branchPred.lookups 31086887 # Number of BP lookups 339system.cpu.branchPred.condPredicted 16880230 # Number of conditional branches predicted 340system.cpu.branchPred.condIncorrect 2489626 # Number of conditional branches incorrect 341system.cpu.branchPred.BTBLookups 18671153 # Number of BTB lookups 342system.cpu.branchPred.BTBHits 10424859 # Number of BTB hits | 342system.cpu.branchPred.lookups 31062999 # Number of BP lookups 343system.cpu.branchPred.condPredicted 16869066 # Number of conditional branches predicted 344system.cpu.branchPred.condIncorrect 2486744 # Number of conditional branches incorrect 345system.cpu.branchPred.BTBLookups 18728785 # Number of BTB lookups 346system.cpu.branchPred.BTBHits 10415318 # Number of BTB hits |
| 343system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 347system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 344system.cpu.branchPred.BTBHitPct 55.834040 # BTB Hit Percentage 345system.cpu.branchPred.usedRAS 7822517 # Number of times the RAS was used to get a target. 346system.cpu.branchPred.RASInCorrect 1524102 # Number of incorrect RAS predictions. 347system.cpu.branchPred.indirectLookups 3081262 # Number of indirect predictor lookups. 348system.cpu.branchPred.indirectHits 2891722 # Number of indirect target hits. 349system.cpu.branchPred.indirectMisses 189540 # Number of indirect misses. 350system.cpu.branchPredindirectMispredicted 109414 # Number of mispredicted indirect branches. | 348system.cpu.branchPred.BTBHitPct 55.611285 # BTB Hit Percentage 349system.cpu.branchPred.usedRAS 7833584 # Number of times the RAS was used to get a target. 350system.cpu.branchPred.RASInCorrect 1520957 # Number of incorrect RAS predictions. 351system.cpu.branchPred.indirectLookups 3075291 # Number of indirect predictor lookups. 352system.cpu.branchPred.indirectHits 2886933 # Number of indirect target hits. 353system.cpu.branchPred.indirectMisses 188358 # Number of indirect misses. 354system.cpu.branchPredindirectMispredicted 109527 # Number of mispredicted indirect branches. |
| 351system.cpu_clk_domain.clock 500 # Clock period in ticks | 355system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 352system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states | 356system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states |
| 353system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 354system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 355system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 356system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 357system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 374system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 375system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 376system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 377system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 378system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 379system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 380system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 381system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 357system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 361system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 364system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 378system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 379system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 380system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 381system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 382system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 383system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 384system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 385system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 382system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 383system.cpu.dtb.walker.walks 67741 # Table walker walks requested 384system.cpu.dtb.walker.walksShort 67741 # Table walker walks initiated with short descriptors 385system.cpu.dtb.walker.walksShortTerminationLevel::Level1 45017 # Level at which table walker walks with short descriptors terminate 386system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22724 # Level at which table walker walks with short descriptors terminate 387system.cpu.dtb.walker.walkWaitTime::samples 67741 # Table walker wait (enqueue to first request) latency 388system.cpu.dtb.walker.walkWaitTime::0 67741 100.00% 100.00% # Table walker wait (enqueue to first request) latency 389system.cpu.dtb.walker.walkWaitTime::total 67741 # Table walker wait (enqueue to first request) latency 390system.cpu.dtb.walker.walkCompletionTime::samples 7842 # Table walker service (enqueue to completion) latency 391system.cpu.dtb.walker.walkCompletionTime::mean 12675.784239 # Table walker service (enqueue to completion) latency 392system.cpu.dtb.walker.walkCompletionTime::gmean 10493.995103 # Table walker service (enqueue to completion) latency 393system.cpu.dtb.walker.walkCompletionTime::stdev 8407.754568 # Table walker service (enqueue to completion) latency 394system.cpu.dtb.walker.walkCompletionTime::0-32767 7835 99.91% 99.91% # Table walker service (enqueue to completion) latency 395system.cpu.dtb.walker.walkCompletionTime::131072-163839 6 0.08% 99.99% # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::total 7842 # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walksPending::samples 517795000 # Table walker pending requests distribution 399system.cpu.dtb.walker.walksPending::0 517795000 100.00% 100.00% # Table walker pending requests distribution 400system.cpu.dtb.walker.walksPending::total 517795000 # Table walker pending requests distribution 401system.cpu.dtb.walker.walkPageSizes::4K 6453 82.29% 82.29% # Table walker page sizes translated 402system.cpu.dtb.walker.walkPageSizes::1M 1389 17.71% 100.00% # Table walker page sizes translated 403system.cpu.dtb.walker.walkPageSizes::total 7842 # Table walker page sizes translated 404system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 67741 # Table walker requests started/completed, data/inst | 386system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 387system.cpu.dtb.walker.walks 68003 # Table walker walks requested 388system.cpu.dtb.walker.walksShort 68003 # Table walker walks initiated with short descriptors 389system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44606 # Level at which table walker walks with short descriptors terminate 390system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23397 # Level at which table walker walks with short descriptors terminate 391system.cpu.dtb.walker.walkWaitTime::samples 68003 # Table walker wait (enqueue to first request) latency 392system.cpu.dtb.walker.walkWaitTime::0 68003 100.00% 100.00% # Table walker wait (enqueue to first request) latency 393system.cpu.dtb.walker.walkWaitTime::total 68003 # Table walker wait (enqueue to first request) latency 394system.cpu.dtb.walker.walkCompletionTime::samples 7897 # Table walker service (enqueue to completion) latency 395system.cpu.dtb.walker.walkCompletionTime::mean 10035.266557 # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::gmean 8419.099443 # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::stdev 6813.200210 # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walkCompletionTime::0-16383 7021 88.91% 88.91% # Table walker service (enqueue to completion) latency 399system.cpu.dtb.walker.walkCompletionTime::16384-32767 869 11.00% 99.91% # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walkCompletionTime::81920-98303 5 0.06% 99.97% # Table walker service (enqueue to completion) latency 401system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 402system.cpu.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 403system.cpu.dtb.walker.walkCompletionTime::total 7897 # Table walker service (enqueue to completion) latency 404system.cpu.dtb.walker.walksPending::samples 271390000 # Table walker pending requests distribution 405system.cpu.dtb.walker.walksPending::0 271390000 100.00% 100.00% # Table walker pending requests distribution 406system.cpu.dtb.walker.walksPending::total 271390000 # Table walker pending requests distribution 407system.cpu.dtb.walker.walkPageSizes::4K 6503 82.35% 82.35% # Table walker page sizes translated 408system.cpu.dtb.walker.walkPageSizes::1M 1394 17.65% 100.00% # Table walker page sizes translated 409system.cpu.dtb.walker.walkPageSizes::total 7897 # Table walker page sizes translated 410system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 68003 # Table walker requests started/completed, data/inst |
| 405system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 411system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 406system.cpu.dtb.walker.walkRequestOrigin_Requested::total 67741 # Table walker requests started/completed, data/inst 407system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7842 # Table walker requests started/completed, data/inst | 412system.cpu.dtb.walker.walkRequestOrigin_Requested::total 68003 # Table walker requests started/completed, data/inst 413system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7897 # Table walker requests started/completed, data/inst |
| 408system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 414system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 409system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7842 # Table walker requests started/completed, data/inst 410system.cpu.dtb.walker.walkRequestOrigin::total 75583 # Table walker requests started/completed, data/inst | 415system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7897 # Table walker requests started/completed, data/inst 416system.cpu.dtb.walker.walkRequestOrigin::total 75900 # Table walker requests started/completed, data/inst |
| 411system.cpu.dtb.inst_hits 0 # ITB inst hits 412system.cpu.dtb.inst_misses 0 # ITB inst misses | 417system.cpu.dtb.inst_hits 0 # ITB inst hits 418system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 413system.cpu.dtb.read_hits 24787454 # DTB read hits 414system.cpu.dtb.read_misses 60877 # DTB read misses 415system.cpu.dtb.write_hits 19460962 # DTB write hits 416system.cpu.dtb.write_misses 6864 # DTB write misses | 419system.cpu.dtb.read_hits 24771188 # DTB read hits 420system.cpu.dtb.read_misses 61134 # DTB read misses 421system.cpu.dtb.write_hits 19449290 # DTB write hits 422system.cpu.dtb.write_misses 6869 # DTB write misses |
| 417system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 418system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 419system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 420system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 423system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 424system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 425system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 426system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 421system.cpu.dtb.flush_entries 4270 # Number of entries that have been flushed from TLB 422system.cpu.dtb.align_faults 1452 # Number of TLB faults due to alignment restrictions 423system.cpu.dtb.prefetch_faults 1793 # Number of TLB faults due to prefetch | 427system.cpu.dtb.flush_entries 4279 # Number of entries that have been flushed from TLB 428system.cpu.dtb.align_faults 1418 # Number of TLB faults due to alignment restrictions 429system.cpu.dtb.prefetch_faults 1775 # Number of TLB faults due to prefetch |
| 424system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 430system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 425system.cpu.dtb.perms_faults 741 # Number of TLB faults due to permissions restrictions 426system.cpu.dtb.read_accesses 24848331 # DTB read accesses 427system.cpu.dtb.write_accesses 19467826 # DTB write accesses | 431system.cpu.dtb.perms_faults 770 # Number of TLB faults due to permissions restrictions 432system.cpu.dtb.read_accesses 24832322 # DTB read accesses 433system.cpu.dtb.write_accesses 19456159 # DTB write accesses |
| 428system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 434system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 429system.cpu.dtb.hits 44248416 # DTB hits 430system.cpu.dtb.misses 67741 # DTB misses 431system.cpu.dtb.accesses 44316157 # DTB accesses 432system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states | 435system.cpu.dtb.hits 44220478 # DTB hits 436system.cpu.dtb.misses 68003 # DTB misses 437system.cpu.dtb.accesses 44288481 # DTB accesses 438system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states |
| 433system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 434system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 435system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 436system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 437system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 438system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 439system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 440system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 454system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 455system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 456system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 457system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 458system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 459system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 460system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 461system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 439system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 440system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 441system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 442system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 444system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 445system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 460system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 461system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 462system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 463system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 464system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 465system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 466system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 467system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 462system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 463system.cpu.itb.walker.walks 5895 # Table walker walks requested 464system.cpu.itb.walker.walksShort 5895 # Table walker walks initiated with short descriptors 465system.cpu.itb.walker.walksShortTerminationLevel::Level1 321 # Level at which table walker walks with short descriptors terminate 466system.cpu.itb.walker.walksShortTerminationLevel::Level2 5574 # Level at which table walker walks with short descriptors terminate 467system.cpu.itb.walker.walkWaitTime::samples 5895 # Table walker wait (enqueue to first request) latency 468system.cpu.itb.walker.walkWaitTime::0 5895 100.00% 100.00% # Table walker wait (enqueue to first request) latency 469system.cpu.itb.walker.walkWaitTime::total 5895 # Table walker wait (enqueue to first request) latency 470system.cpu.itb.walker.walkCompletionTime::samples 3205 # Table walker service (enqueue to completion) latency 471system.cpu.itb.walker.walkCompletionTime::mean 12907.644306 # Table walker service (enqueue to completion) latency 472system.cpu.itb.walker.walkCompletionTime::gmean 10876.938214 # Table walker service (enqueue to completion) latency 473system.cpu.itb.walker.walkCompletionTime::stdev 7322.763550 # Table walker service (enqueue to completion) latency 474system.cpu.itb.walker.walkCompletionTime::0-16383 2473 77.16% 77.16% # Table walker service (enqueue to completion) latency 475system.cpu.itb.walker.walkCompletionTime::16384-32767 731 22.81% 99.97% # Table walker service (enqueue to completion) latency 476system.cpu.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 477system.cpu.itb.walker.walkCompletionTime::total 3205 # Table walker service (enqueue to completion) latency 478system.cpu.itb.walker.walksPending::samples 517140500 # Table walker pending requests distribution 479system.cpu.itb.walker.walksPending::0 517140500 100.00% 100.00% # Table walker pending requests distribution 480system.cpu.itb.walker.walksPending::total 517140500 # Table walker pending requests distribution 481system.cpu.itb.walker.walkPageSizes::4K 2896 90.36% 90.36% # Table walker page sizes translated 482system.cpu.itb.walker.walkPageSizes::1M 309 9.64% 100.00% # Table walker page sizes translated 483system.cpu.itb.walker.walkPageSizes::total 3205 # Table walker page sizes translated | 468system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 469system.cpu.itb.walker.walks 5856 # Table walker walks requested 470system.cpu.itb.walker.walksShort 5856 # Table walker walks initiated with short descriptors 471system.cpu.itb.walker.walksShortTerminationLevel::Level1 325 # Level at which table walker walks with short descriptors terminate 472system.cpu.itb.walker.walksShortTerminationLevel::Level2 5531 # Level at which table walker walks with short descriptors terminate 473system.cpu.itb.walker.walkWaitTime::samples 5856 # Table walker wait (enqueue to first request) latency 474system.cpu.itb.walker.walkWaitTime::0 5856 100.00% 100.00% # Table walker wait (enqueue to first request) latency 475system.cpu.itb.walker.walkWaitTime::total 5856 # Table walker wait (enqueue to first request) latency 476system.cpu.itb.walker.walkCompletionTime::samples 3193 # Table walker service (enqueue to completion) latency 477system.cpu.itb.walker.walkCompletionTime::mean 10411.838396 # Table walker service (enqueue to completion) latency 478system.cpu.itb.walker.walkCompletionTime::gmean 8598.635311 # Table walker service (enqueue to completion) latency 479system.cpu.itb.walker.walkCompletionTime::stdev 6896.589649 # Table walker service (enqueue to completion) latency 480system.cpu.itb.walker.walkCompletionTime::0-8191 1843 57.72% 57.72% # Table walker service (enqueue to completion) latency 481system.cpu.itb.walker.walkCompletionTime::8192-16383 807 25.27% 82.99% # Table walker service (enqueue to completion) latency 482system.cpu.itb.walker.walkCompletionTime::16384-24575 535 16.76% 99.75% # Table walker service (enqueue to completion) latency 483system.cpu.itb.walker.walkCompletionTime::24576-32767 7 0.22% 99.97% # Table walker service (enqueue to completion) latency 484system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 485system.cpu.itb.walker.walkCompletionTime::total 3193 # Table walker service (enqueue to completion) latency 486system.cpu.itb.walker.walksPending::samples 270980500 # Table walker pending requests distribution 487system.cpu.itb.walker.walksPending::0 270980500 100.00% 100.00% # Table walker pending requests distribution 488system.cpu.itb.walker.walksPending::total 270980500 # Table walker pending requests distribution 489system.cpu.itb.walker.walkPageSizes::4K 2883 90.29% 90.29% # Table walker page sizes translated 490system.cpu.itb.walker.walkPageSizes::1M 310 9.71% 100.00% # Table walker page sizes translated 491system.cpu.itb.walker.walkPageSizes::total 3193 # Table walker page sizes translated |
| 484system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 492system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 485system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5895 # Table walker requests started/completed, data/inst 486system.cpu.itb.walker.walkRequestOrigin_Requested::total 5895 # Table walker requests started/completed, data/inst | 493system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5856 # Table walker requests started/completed, data/inst 494system.cpu.itb.walker.walkRequestOrigin_Requested::total 5856 # Table walker requests started/completed, data/inst |
| 487system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 495system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 488system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3205 # Table walker requests started/completed, data/inst 489system.cpu.itb.walker.walkRequestOrigin_Completed::total 3205 # Table walker requests started/completed, data/inst 490system.cpu.itb.walker.walkRequestOrigin::total 9100 # Table walker requests started/completed, data/inst 491system.cpu.itb.inst_hits 57517109 # ITB inst hits 492system.cpu.itb.inst_misses 5895 # ITB inst misses | 496system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3193 # Table walker requests started/completed, data/inst 497system.cpu.itb.walker.walkRequestOrigin_Completed::total 3193 # Table walker requests started/completed, data/inst 498system.cpu.itb.walker.walkRequestOrigin::total 9049 # Table walker requests started/completed, data/inst 499system.cpu.itb.inst_hits 57483193 # ITB inst hits 500system.cpu.itb.inst_misses 5856 # ITB inst misses |
| 493system.cpu.itb.read_hits 0 # DTB read hits 494system.cpu.itb.read_misses 0 # DTB read misses 495system.cpu.itb.write_hits 0 # DTB write hits 496system.cpu.itb.write_misses 0 # DTB write misses 497system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 498system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 499system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 500system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 501system.cpu.itb.read_hits 0 # DTB read hits 502system.cpu.itb.read_misses 0 # DTB read misses 503system.cpu.itb.write_hits 0 # DTB write hits 504system.cpu.itb.write_misses 0 # DTB write misses 505system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 506system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 507system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 508system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 501system.cpu.itb.flush_entries 2926 # Number of entries that have been flushed from TLB | 509system.cpu.itb.flush_entries 2912 # Number of entries that have been flushed from TLB |
| 502system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 503system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 504system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 510system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 511system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 512system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 505system.cpu.itb.perms_faults 8405 # Number of TLB faults due to permissions restrictions | 513system.cpu.itb.perms_faults 8279 # Number of TLB faults due to permissions restrictions |
| 506system.cpu.itb.read_accesses 0 # DTB read accesses 507system.cpu.itb.write_accesses 0 # DTB write accesses | 514system.cpu.itb.read_accesses 0 # DTB read accesses 515system.cpu.itb.write_accesses 0 # DTB write accesses |
| 508system.cpu.itb.inst_accesses 57523004 # ITB inst accesses 509system.cpu.itb.hits 57517109 # DTB hits 510system.cpu.itb.misses 5895 # DTB misses 511system.cpu.itb.accesses 57523004 # DTB accesses 512system.cpu.numPwrStateTransitions 6068 # Number of power state transitions 513system.cpu.pwrStateClkGateDist::samples 3034 # Distribution of time spent in the clock gated state 514system.cpu.pwrStateClkGateDist::mean 887205873.057680 # Distribution of time spent in the clock gated state 515system.cpu.pwrStateClkGateDist::stdev 17434832353.062756 # Distribution of time spent in the clock gated state 516system.cpu.pwrStateClkGateDist::underflows 2969 97.86% 97.86% # Distribution of time spent in the clock gated state 517system.cpu.pwrStateClkGateDist::1000-5e+10 59 1.94% 99.80% # Distribution of time spent in the clock gated state | 516system.cpu.itb.inst_accesses 57489049 # ITB inst accesses 517system.cpu.itb.hits 57483193 # DTB hits 518system.cpu.itb.misses 5856 # DTB misses 519system.cpu.itb.accesses 57489049 # DTB accesses 520system.cpu.numPwrStateTransitions 6066 # Number of power state transitions 521system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state 522system.cpu.pwrStateClkGateDist::mean 888351102.639301 # Distribution of time spent in the clock gated state 523system.cpu.pwrStateClkGateDist::stdev 17445509399.919735 # Distribution of time spent in the clock gated state 524system.cpu.pwrStateClkGateDist::underflows 2969 97.89% 97.89% # Distribution of time spent in the clock gated state 525system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% # Distribution of time spent in the clock gated state |
| 518system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 519system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state 520system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state 521system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 522system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state | 526system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 527system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state 528system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state 529system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 530system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state |
| 523system.cpu.pwrStateClkGateDist::max_value 499967463084 # Distribution of time spent in the clock gated state 524system.cpu.pwrStateClkGateDist::total 3034 # Distribution of time spent in the clock gated state 525system.cpu.pwrStateResidencyTicks::ON 167214720643 # Cumulative time (in ticks) in various power states 526system.cpu.pwrStateResidencyTicks::CLK_GATED 2691782618857 # Cumulative time (in ticks) in various power states 527system.cpu.numCycles 334432391 # number of cpu cycles simulated | 531system.cpu.pwrStateClkGateDist::max_value 499967553028 # Distribution of time spent in the clock gated state 532system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state 533system.cpu.pwrStateResidencyTicks::ON 158975005195 # Cumulative time (in ticks) in various power states 534system.cpu.pwrStateResidencyTicks::CLK_GATED 2694368894305 # Cumulative time (in ticks) in various power states 535system.cpu.numCycles 317952965 # number of cpu cycles simulated |
| 528system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 529system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 536system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 537system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 530system.cpu.committedInsts 112217626 # Number of instructions committed 531system.cpu.committedOps 135683579 # Number of ops (including micro ops) committed 532system.cpu.discardedOps 7838903 # Number of ops (including micro ops) which were discarded before commit 533system.cpu.numFetchSuspends 3034 # Number of times Execute suspended instruction fetching 534system.cpu.quiesceCycles 5383627132 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 535system.cpu.cpi 2.980213 # CPI: cycles per instruction 536system.cpu.ipc 0.335547 # IPC: instructions per cycle | 538system.cpu.committedInsts 112146750 # Number of instructions committed 539system.cpu.committedOps 135598813 # Number of ops (including micro ops) committed 540system.cpu.discardedOps 7821624 # Number of ops (including micro ops) which were discarded before commit 541system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching 542system.cpu.quiesceCycles 5388799101 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 543system.cpu.cpi 2.835151 # CPI: cycles per instruction 544system.cpu.ipc 0.352715 # IPC: instructions per cycle |
| 537system.cpu.op_class_0::No_OpClass 2337 0.00% 0.00% # Class of committed instruction | 545system.cpu.op_class_0::No_OpClass 2337 0.00% 0.00% # Class of committed instruction |
| 538system.cpu.op_class_0::IntAlu 90974393 67.05% 67.05% # Class of committed instruction 539system.cpu.op_class_0::IntMult 113069 0.08% 67.13% # Class of committed instruction | 546system.cpu.op_class_0::IntAlu 90918529 67.05% 67.05% # Class of committed instruction 547system.cpu.op_class_0::IntMult 113133 0.08% 67.13% # Class of committed instruction |
| 540system.cpu.op_class_0::IntDiv 0 0.00% 67.13% # Class of committed instruction 541system.cpu.op_class_0::FloatAdd 0 0.00% 67.13% # Class of committed instruction 542system.cpu.op_class_0::FloatCmp 0 0.00% 67.13% # Class of committed instruction 543system.cpu.op_class_0::FloatCvt 0 0.00% 67.13% # Class of committed instruction 544system.cpu.op_class_0::FloatMult 0 0.00% 67.13% # Class of committed instruction 545system.cpu.op_class_0::FloatDiv 0 0.00% 67.13% # Class of committed instruction 546system.cpu.op_class_0::FloatSqrt 0 0.00% 67.13% # Class of committed instruction 547system.cpu.op_class_0::SimdAdd 0 0.00% 67.13% # Class of committed instruction --- 7 unchanged lines hidden (view full) --- 555system.cpu.op_class_0::SimdShift 0 0.00% 67.13% # Class of committed instruction 556system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.13% # Class of committed instruction 557system.cpu.op_class_0::SimdSqrt 0 0.00% 67.13% # Class of committed instruction 558system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.13% # Class of committed instruction 559system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.13% # Class of committed instruction 560system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.13% # Class of committed instruction 561system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.13% # Class of committed instruction 562system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.13% # Class of committed instruction | 548system.cpu.op_class_0::IntDiv 0 0.00% 67.13% # Class of committed instruction 549system.cpu.op_class_0::FloatAdd 0 0.00% 67.13% # Class of committed instruction 550system.cpu.op_class_0::FloatCmp 0 0.00% 67.13% # Class of committed instruction 551system.cpu.op_class_0::FloatCvt 0 0.00% 67.13% # Class of committed instruction 552system.cpu.op_class_0::FloatMult 0 0.00% 67.13% # Class of committed instruction 553system.cpu.op_class_0::FloatDiv 0 0.00% 67.13% # Class of committed instruction 554system.cpu.op_class_0::FloatSqrt 0 0.00% 67.13% # Class of committed instruction 555system.cpu.op_class_0::SimdAdd 0 0.00% 67.13% # Class of committed instruction --- 7 unchanged lines hidden (view full) --- 563system.cpu.op_class_0::SimdShift 0 0.00% 67.13% # Class of committed instruction 564system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.13% # Class of committed instruction 565system.cpu.op_class_0::SimdSqrt 0 0.00% 67.13% # Class of committed instruction 566system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.13% # Class of committed instruction 567system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.13% # Class of committed instruction 568system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.13% # Class of committed instruction 569system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.13% # Class of committed instruction 570system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.13% # Class of committed instruction |
| 563system.cpu.op_class_0::SimdFloatMisc 8525 0.01% 67.14% # Class of committed instruction | 571system.cpu.op_class_0::SimdFloatMisc 8487 0.01% 67.14% # Class of committed instruction |
| 564system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.14% # Class of committed instruction 565system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.14% # Class of committed instruction 566system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.14% # Class of committed instruction | 572system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.14% # Class of committed instruction 573system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.14% # Class of committed instruction 574system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.14% # Class of committed instruction |
| 567system.cpu.op_class_0::MemRead 24296976 17.91% 85.05% # Class of committed instruction 568system.cpu.op_class_0::MemWrite 20288279 14.95% 100.00% # Class of committed instruction | 575system.cpu.op_class_0::MemRead 24279497 17.91% 85.05% # Class of committed instruction 576system.cpu.op_class_0::MemWrite 20276830 14.95% 100.00% # Class of committed instruction |
| 569system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 570system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 577system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 578system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 571system.cpu.op_class_0::total 135683579 # Class of committed instruction | 579system.cpu.op_class_0::total 135598813 # Class of committed instruction |
| 572system.cpu.kern.inst.arm 0 # number of arm instructions executed | 580system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 573system.cpu.kern.inst.quiesce 3034 # number of quiesce instructions executed 574system.cpu.tickCycles 218593350 # Number of cycles that the object actually ticked 575system.cpu.idleCycles 115839041 # Total number of cycles that the object has spent stopped 576system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 577system.cpu.dcache.tags.replacements 844257 # number of replacements 578system.cpu.dcache.tags.tagsinuse 511.899744 # Cycle average of tags in use 579system.cpu.dcache.tags.total_refs 42705909 # Total number of references to valid blocks. 580system.cpu.dcache.tags.sampled_refs 844769 # Sample count of references to valid blocks. 581system.cpu.dcache.tags.avg_refs 50.553357 # Average number of references to valid blocks. 582system.cpu.dcache.tags.warmup_cycle 594757500 # Cycle when the warmup percentage was hit. 583system.cpu.dcache.tags.occ_blocks::cpu.data 511.899744 # Average occupied blocks per requestor 584system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy 585system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy | 581system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed 582system.cpu.tickCycles 217828985 # Number of cycles that the object actually ticked 583system.cpu.idleCycles 100123980 # Total number of cycles that the object has spent stopped 584system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 585system.cpu.dcache.tags.replacements 845168 # number of replacements 586system.cpu.dcache.tags.tagsinuse 511.946266 # Cycle average of tags in use 587system.cpu.dcache.tags.total_refs 42678256 # Total number of references to valid blocks. 588system.cpu.dcache.tags.sampled_refs 845680 # Sample count of references to valid blocks. 589system.cpu.dcache.tags.avg_refs 50.466200 # Average number of references to valid blocks. 590system.cpu.dcache.tags.warmup_cycle 322165500 # Cycle when the warmup percentage was hit. 591system.cpu.dcache.tags.occ_blocks::cpu.data 511.946266 # Average occupied blocks per requestor 592system.cpu.dcache.tags.occ_percent::cpu.data 0.999895 # Average percentage of cache occupancy 593system.cpu.dcache.tags.occ_percent::total 0.999895 # Average percentage of cache occupancy |
| 586system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 594system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 587system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id 588system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id 589system.cpu.dcache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id | 595system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 596system.cpu.dcache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id 597system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id |
| 590system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 598system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 591system.cpu.dcache.tags.tag_accesses 176476854 # Number of tag accesses 592system.cpu.dcache.tags.data_accesses 176476854 # Number of data accesses 593system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 594system.cpu.dcache.ReadReq_hits::cpu.data 23143905 # number of ReadReq hits 595system.cpu.dcache.ReadReq_hits::total 23143905 # number of ReadReq hits 596system.cpu.dcache.WriteReq_hits::cpu.data 18298058 # number of WriteReq hits 597system.cpu.dcache.WriteReq_hits::total 18298058 # number of WriteReq hits 598system.cpu.dcache.SoftPFReq_hits::cpu.data 356964 # number of SoftPFReq hits 599system.cpu.dcache.SoftPFReq_hits::total 356964 # number of SoftPFReq hits 600system.cpu.dcache.LoadLockedReq_hits::cpu.data 443845 # number of LoadLockedReq hits 601system.cpu.dcache.LoadLockedReq_hits::total 443845 # number of LoadLockedReq hits 602system.cpu.dcache.StoreCondReq_hits::cpu.data 460247 # number of StoreCondReq hits 603system.cpu.dcache.StoreCondReq_hits::total 460247 # number of StoreCondReq hits 604system.cpu.dcache.demand_hits::cpu.data 41441963 # number of demand (read+write) hits 605system.cpu.dcache.demand_hits::total 41441963 # number of demand (read+write) hits 606system.cpu.dcache.overall_hits::cpu.data 41798927 # number of overall hits 607system.cpu.dcache.overall_hits::total 41798927 # number of overall hits 608system.cpu.dcache.ReadReq_misses::cpu.data 464900 # number of ReadReq misses 609system.cpu.dcache.ReadReq_misses::total 464900 # number of ReadReq misses 610system.cpu.dcache.WriteReq_misses::cpu.data 548479 # number of WriteReq misses 611system.cpu.dcache.WriteReq_misses::total 548479 # number of WriteReq misses 612system.cpu.dcache.SoftPFReq_misses::cpu.data 169396 # number of SoftPFReq misses 613system.cpu.dcache.SoftPFReq_misses::total 169396 # number of SoftPFReq misses 614system.cpu.dcache.LoadLockedReq_misses::cpu.data 22217 # number of LoadLockedReq misses 615system.cpu.dcache.LoadLockedReq_misses::total 22217 # number of LoadLockedReq misses | 599system.cpu.dcache.tags.tag_accesses 176368054 # Number of tag accesses 600system.cpu.dcache.tags.data_accesses 176368054 # Number of data accesses 601system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 602system.cpu.dcache.ReadReq_hits::cpu.data 23126363 # number of ReadReq hits 603system.cpu.dcache.ReadReq_hits::total 23126363 # number of ReadReq hits 604system.cpu.dcache.WriteReq_hits::cpu.data 18288488 # number of WriteReq hits 605system.cpu.dcache.WriteReq_hits::total 18288488 # number of WriteReq hits 606system.cpu.dcache.SoftPFReq_hits::cpu.data 357151 # number of SoftPFReq hits 607system.cpu.dcache.SoftPFReq_hits::total 357151 # number of SoftPFReq hits 608system.cpu.dcache.LoadLockedReq_hits::cpu.data 443374 # number of LoadLockedReq hits 609system.cpu.dcache.LoadLockedReq_hits::total 443374 # number of LoadLockedReq hits 610system.cpu.dcache.StoreCondReq_hits::cpu.data 459996 # number of StoreCondReq hits 611system.cpu.dcache.StoreCondReq_hits::total 459996 # number of StoreCondReq hits 612system.cpu.dcache.demand_hits::cpu.data 41414851 # number of demand (read+write) hits 613system.cpu.dcache.demand_hits::total 41414851 # number of demand (read+write) hits 614system.cpu.dcache.overall_hits::cpu.data 41772002 # number of overall hits 615system.cpu.dcache.overall_hits::total 41772002 # number of overall hits 616system.cpu.dcache.ReadReq_misses::cpu.data 466466 # number of ReadReq misses 617system.cpu.dcache.ReadReq_misses::total 466466 # number of ReadReq misses 618system.cpu.dcache.WriteReq_misses::cpu.data 547177 # number of WriteReq misses 619system.cpu.dcache.WriteReq_misses::total 547177 # number of WriteReq misses 620system.cpu.dcache.SoftPFReq_misses::cpu.data 169147 # number of SoftPFReq misses 621system.cpu.dcache.SoftPFReq_misses::total 169147 # number of SoftPFReq misses 622system.cpu.dcache.LoadLockedReq_misses::cpu.data 22423 # number of LoadLockedReq misses 623system.cpu.dcache.LoadLockedReq_misses::total 22423 # number of LoadLockedReq misses |
| 616system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 617system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses | 624system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 625system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses |
| 618system.cpu.dcache.demand_misses::cpu.data 1013379 # number of demand (read+write) misses 619system.cpu.dcache.demand_misses::total 1013379 # number of demand (read+write) misses 620system.cpu.dcache.overall_misses::cpu.data 1182775 # number of overall misses 621system.cpu.dcache.overall_misses::total 1182775 # number of overall misses 622system.cpu.dcache.ReadReq_miss_latency::cpu.data 7474682000 # number of ReadReq miss cycles 623system.cpu.dcache.ReadReq_miss_latency::total 7474682000 # number of ReadReq miss cycles 624system.cpu.dcache.WriteReq_miss_latency::cpu.data 35725670480 # number of WriteReq miss cycles 625system.cpu.dcache.WriteReq_miss_latency::total 35725670480 # number of WriteReq miss cycles 626system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 298069500 # number of LoadLockedReq miss cycles 627system.cpu.dcache.LoadLockedReq_miss_latency::total 298069500 # number of LoadLockedReq miss cycles 628system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles 629system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles 630system.cpu.dcache.demand_miss_latency::cpu.data 43200352480 # number of demand (read+write) miss cycles 631system.cpu.dcache.demand_miss_latency::total 43200352480 # number of demand (read+write) miss cycles 632system.cpu.dcache.overall_miss_latency::cpu.data 43200352480 # number of overall miss cycles 633system.cpu.dcache.overall_miss_latency::total 43200352480 # number of overall miss cycles 634system.cpu.dcache.ReadReq_accesses::cpu.data 23608805 # number of ReadReq accesses(hits+misses) 635system.cpu.dcache.ReadReq_accesses::total 23608805 # number of ReadReq accesses(hits+misses) 636system.cpu.dcache.WriteReq_accesses::cpu.data 18846537 # number of WriteReq accesses(hits+misses) 637system.cpu.dcache.WriteReq_accesses::total 18846537 # number of WriteReq accesses(hits+misses) 638system.cpu.dcache.SoftPFReq_accesses::cpu.data 526360 # number of SoftPFReq accesses(hits+misses) 639system.cpu.dcache.SoftPFReq_accesses::total 526360 # number of SoftPFReq accesses(hits+misses) 640system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466062 # number of LoadLockedReq accesses(hits+misses) 641system.cpu.dcache.LoadLockedReq_accesses::total 466062 # number of LoadLockedReq accesses(hits+misses) 642system.cpu.dcache.StoreCondReq_accesses::cpu.data 460249 # number of StoreCondReq accesses(hits+misses) 643system.cpu.dcache.StoreCondReq_accesses::total 460249 # number of StoreCondReq accesses(hits+misses) 644system.cpu.dcache.demand_accesses::cpu.data 42455342 # number of demand (read+write) accesses 645system.cpu.dcache.demand_accesses::total 42455342 # number of demand (read+write) accesses 646system.cpu.dcache.overall_accesses::cpu.data 42981702 # number of overall (read+write) accesses 647system.cpu.dcache.overall_accesses::total 42981702 # number of overall (read+write) accesses 648system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019692 # miss rate for ReadReq accesses 649system.cpu.dcache.ReadReq_miss_rate::total 0.019692 # miss rate for ReadReq accesses 650system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029102 # miss rate for WriteReq accesses 651system.cpu.dcache.WriteReq_miss_rate::total 0.029102 # miss rate for WriteReq accesses 652system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.321825 # miss rate for SoftPFReq accesses 653system.cpu.dcache.SoftPFReq_miss_rate::total 0.321825 # miss rate for SoftPFReq accesses 654system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047670 # miss rate for LoadLockedReq accesses 655system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047670 # miss rate for LoadLockedReq accesses | 626system.cpu.dcache.demand_misses::cpu.data 1013643 # number of demand (read+write) misses 627system.cpu.dcache.demand_misses::total 1013643 # number of demand (read+write) misses 628system.cpu.dcache.overall_misses::cpu.data 1182790 # number of overall misses 629system.cpu.dcache.overall_misses::total 1182790 # number of overall misses 630system.cpu.dcache.ReadReq_miss_latency::cpu.data 6859105500 # number of ReadReq miss cycles 631system.cpu.dcache.ReadReq_miss_latency::total 6859105500 # number of ReadReq miss cycles 632system.cpu.dcache.WriteReq_miss_latency::cpu.data 23368526480 # number of WriteReq miss cycles 633system.cpu.dcache.WriteReq_miss_latency::total 23368526480 # number of WriteReq miss cycles 634system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 290513500 # number of LoadLockedReq miss cycles 635system.cpu.dcache.LoadLockedReq_miss_latency::total 290513500 # number of LoadLockedReq miss cycles 636system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 169000 # number of StoreCondReq miss cycles 637system.cpu.dcache.StoreCondReq_miss_latency::total 169000 # number of StoreCondReq miss cycles 638system.cpu.dcache.demand_miss_latency::cpu.data 30227631980 # number of demand (read+write) miss cycles 639system.cpu.dcache.demand_miss_latency::total 30227631980 # number of demand (read+write) miss cycles 640system.cpu.dcache.overall_miss_latency::cpu.data 30227631980 # number of overall miss cycles 641system.cpu.dcache.overall_miss_latency::total 30227631980 # number of overall miss cycles 642system.cpu.dcache.ReadReq_accesses::cpu.data 23592829 # number of ReadReq accesses(hits+misses) 643system.cpu.dcache.ReadReq_accesses::total 23592829 # number of ReadReq accesses(hits+misses) 644system.cpu.dcache.WriteReq_accesses::cpu.data 18835665 # number of WriteReq accesses(hits+misses) 645system.cpu.dcache.WriteReq_accesses::total 18835665 # number of WriteReq accesses(hits+misses) 646system.cpu.dcache.SoftPFReq_accesses::cpu.data 526298 # number of SoftPFReq accesses(hits+misses) 647system.cpu.dcache.SoftPFReq_accesses::total 526298 # number of SoftPFReq accesses(hits+misses) 648system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465797 # number of LoadLockedReq accesses(hits+misses) 649system.cpu.dcache.LoadLockedReq_accesses::total 465797 # number of LoadLockedReq accesses(hits+misses) 650system.cpu.dcache.StoreCondReq_accesses::cpu.data 459998 # number of StoreCondReq accesses(hits+misses) 651system.cpu.dcache.StoreCondReq_accesses::total 459998 # number of StoreCondReq accesses(hits+misses) 652system.cpu.dcache.demand_accesses::cpu.data 42428494 # number of demand (read+write) accesses 653system.cpu.dcache.demand_accesses::total 42428494 # number of demand (read+write) accesses 654system.cpu.dcache.overall_accesses::cpu.data 42954792 # number of overall (read+write) accesses 655system.cpu.dcache.overall_accesses::total 42954792 # number of overall (read+write) accesses 656system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019772 # miss rate for ReadReq accesses 657system.cpu.dcache.ReadReq_miss_rate::total 0.019772 # miss rate for ReadReq accesses 658system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029050 # miss rate for WriteReq accesses 659system.cpu.dcache.WriteReq_miss_rate::total 0.029050 # miss rate for WriteReq accesses 660system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.321390 # miss rate for SoftPFReq accesses 661system.cpu.dcache.SoftPFReq_miss_rate::total 0.321390 # miss rate for SoftPFReq accesses 662system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048139 # miss rate for LoadLockedReq accesses 663system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048139 # miss rate for LoadLockedReq accesses |
| 656system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 657system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses | 664system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 665system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses |
| 658system.cpu.dcache.demand_miss_rate::cpu.data 0.023869 # miss rate for demand accesses 659system.cpu.dcache.demand_miss_rate::total 0.023869 # miss rate for demand accesses 660system.cpu.dcache.overall_miss_rate::cpu.data 0.027518 # miss rate for overall accesses 661system.cpu.dcache.overall_miss_rate::total 0.027518 # miss rate for overall accesses 662system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16078.042590 # average ReadReq miss latency 663system.cpu.dcache.ReadReq_avg_miss_latency::total 16078.042590 # average ReadReq miss latency 664system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65135.894866 # average WriteReq miss latency 665system.cpu.dcache.WriteReq_avg_miss_latency::total 65135.894866 # average WriteReq miss latency 666system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13416.280326 # average LoadLockedReq miss latency 667system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13416.280326 # average LoadLockedReq miss latency 668system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83500 # average StoreCondReq miss latency 669system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83500 # average StoreCondReq miss latency 670system.cpu.dcache.demand_avg_miss_latency::cpu.data 42630.005635 # average overall miss latency 671system.cpu.dcache.demand_avg_miss_latency::total 42630.005635 # average overall miss latency 672system.cpu.dcache.overall_avg_miss_latency::cpu.data 36524.573549 # average overall miss latency 673system.cpu.dcache.overall_avg_miss_latency::total 36524.573549 # average overall miss latency 674system.cpu.dcache.blocked_cycles::no_mshrs 235 # number of cycles access was blocked | 666system.cpu.dcache.demand_miss_rate::cpu.data 0.023891 # miss rate for demand accesses 667system.cpu.dcache.demand_miss_rate::total 0.023891 # miss rate for demand accesses 668system.cpu.dcache.overall_miss_rate::cpu.data 0.027536 # miss rate for overall accesses 669system.cpu.dcache.overall_miss_rate::total 0.027536 # miss rate for overall accesses 670system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14704.406109 # average ReadReq miss latency 671system.cpu.dcache.ReadReq_avg_miss_latency::total 14704.406109 # average ReadReq miss latency 672system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42707.435583 # average WriteReq miss latency 673system.cpu.dcache.WriteReq_avg_miss_latency::total 42707.435583 # average WriteReq miss latency 674system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12956.049592 # average LoadLockedReq miss latency 675system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12956.049592 # average LoadLockedReq miss latency 676system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 84500 # average StoreCondReq miss latency 677system.cpu.dcache.StoreCondReq_avg_miss_latency::total 84500 # average StoreCondReq miss latency 678system.cpu.dcache.demand_avg_miss_latency::cpu.data 29820.786983 # average overall miss latency 679system.cpu.dcache.demand_avg_miss_latency::total 29820.786983 # average overall miss latency 680system.cpu.dcache.overall_avg_miss_latency::cpu.data 25556.211990 # average overall miss latency 681system.cpu.dcache.overall_avg_miss_latency::total 25556.211990 # average overall miss latency 682system.cpu.dcache.blocked_cycles::no_mshrs 210 # number of cycles access was blocked |
| 675system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 683system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 676system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked | 684system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked |
| 677system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 685system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 678system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.681818 # average number of cycles each access was blocked | 686system.cpu.dcache.avg_blocked_cycles::no_mshrs 10 # average number of cycles each access was blocked |
| 679system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 687system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 680system.cpu.dcache.writebacks::writebacks 701092 # number of writebacks 681system.cpu.dcache.writebacks::total 701092 # number of writebacks 682system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45747 # number of ReadReq MSHR hits 683system.cpu.dcache.ReadReq_mshr_hits::total 45747 # number of ReadReq MSHR hits 684system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249493 # number of WriteReq MSHR hits 685system.cpu.dcache.WriteReq_mshr_hits::total 249493 # number of WriteReq MSHR hits 686system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 13970 # number of LoadLockedReq MSHR hits 687system.cpu.dcache.LoadLockedReq_mshr_hits::total 13970 # number of LoadLockedReq MSHR hits 688system.cpu.dcache.demand_mshr_hits::cpu.data 295240 # number of demand (read+write) MSHR hits 689system.cpu.dcache.demand_mshr_hits::total 295240 # number of demand (read+write) MSHR hits 690system.cpu.dcache.overall_mshr_hits::cpu.data 295240 # number of overall MSHR hits 691system.cpu.dcache.overall_mshr_hits::total 295240 # number of overall MSHR hits 692system.cpu.dcache.ReadReq_mshr_misses::cpu.data 419153 # number of ReadReq MSHR misses 693system.cpu.dcache.ReadReq_mshr_misses::total 419153 # number of ReadReq MSHR misses 694system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298986 # number of WriteReq MSHR misses 695system.cpu.dcache.WriteReq_mshr_misses::total 298986 # number of WriteReq MSHR misses 696system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121200 # number of SoftPFReq MSHR misses 697system.cpu.dcache.SoftPFReq_mshr_misses::total 121200 # number of SoftPFReq MSHR misses 698system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8247 # number of LoadLockedReq MSHR misses 699system.cpu.dcache.LoadLockedReq_mshr_misses::total 8247 # number of LoadLockedReq MSHR misses | 688system.cpu.dcache.writebacks::writebacks 700399 # number of writebacks 689system.cpu.dcache.writebacks::total 700399 # number of writebacks 690system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45619 # number of ReadReq MSHR hits 691system.cpu.dcache.ReadReq_mshr_hits::total 45619 # number of ReadReq MSHR hits 692system.cpu.dcache.WriteReq_mshr_hits::cpu.data 248851 # number of WriteReq MSHR hits 693system.cpu.dcache.WriteReq_mshr_hits::total 248851 # number of WriteReq MSHR hits 694system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14095 # number of LoadLockedReq MSHR hits 695system.cpu.dcache.LoadLockedReq_mshr_hits::total 14095 # number of LoadLockedReq MSHR hits 696system.cpu.dcache.demand_mshr_hits::cpu.data 294470 # number of demand (read+write) MSHR hits 697system.cpu.dcache.demand_mshr_hits::total 294470 # number of demand (read+write) MSHR hits 698system.cpu.dcache.overall_mshr_hits::cpu.data 294470 # number of overall MSHR hits 699system.cpu.dcache.overall_mshr_hits::total 294470 # number of overall MSHR hits 700system.cpu.dcache.ReadReq_mshr_misses::cpu.data 420847 # number of ReadReq MSHR misses 701system.cpu.dcache.ReadReq_mshr_misses::total 420847 # number of ReadReq MSHR misses 702system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298326 # number of WriteReq MSHR misses 703system.cpu.dcache.WriteReq_mshr_misses::total 298326 # number of WriteReq MSHR misses 704system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121014 # number of SoftPFReq MSHR misses 705system.cpu.dcache.SoftPFReq_mshr_misses::total 121014 # number of SoftPFReq MSHR misses 706system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8328 # number of LoadLockedReq MSHR misses 707system.cpu.dcache.LoadLockedReq_mshr_misses::total 8328 # number of LoadLockedReq MSHR misses |
| 700system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 701system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses | 708system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 709system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses |
| 702system.cpu.dcache.demand_mshr_misses::cpu.data 718139 # number of demand (read+write) MSHR misses 703system.cpu.dcache.demand_mshr_misses::total 718139 # number of demand (read+write) MSHR misses 704system.cpu.dcache.overall_mshr_misses::cpu.data 839339 # number of overall MSHR misses 705system.cpu.dcache.overall_mshr_misses::total 839339 # number of overall MSHR misses 706system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable 707system.cpu.dcache.ReadReq_mshr_uncacheable::total 31130 # number of ReadReq MSHR uncacheable 708system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable 709system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable 710system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 711system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses 712system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6559792500 # number of ReadReq MSHR miss cycles 713system.cpu.dcache.ReadReq_mshr_miss_latency::total 6559792500 # number of ReadReq MSHR miss cycles 714system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19260233000 # number of WriteReq MSHR miss cycles 715system.cpu.dcache.WriteReq_mshr_miss_latency::total 19260233000 # number of WriteReq MSHR miss cycles 716system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1701865000 # number of SoftPFReq MSHR miss cycles 717system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1701865000 # number of SoftPFReq MSHR miss cycles 718system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115452000 # number of LoadLockedReq MSHR miss cycles 719system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115452000 # number of LoadLockedReq MSHR miss cycles 720system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165000 # number of StoreCondReq MSHR miss cycles 721system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165000 # number of StoreCondReq MSHR miss cycles 722system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25820025500 # number of demand (read+write) MSHR miss cycles 723system.cpu.dcache.demand_mshr_miss_latency::total 25820025500 # number of demand (read+write) MSHR miss cycles 724system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27521890500 # number of overall MSHR miss cycles 725system.cpu.dcache.overall_mshr_miss_latency::total 27521890500 # number of overall MSHR miss cycles 726system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6298878000 # number of ReadReq MSHR uncacheable cycles 727system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6298878000 # number of ReadReq MSHR uncacheable cycles 728system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6298878000 # number of overall MSHR uncacheable cycles 729system.cpu.dcache.overall_mshr_uncacheable_latency::total 6298878000 # number of overall MSHR uncacheable cycles 730system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017754 # mshr miss rate for ReadReq accesses 731system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017754 # mshr miss rate for ReadReq accesses 732system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015864 # mshr miss rate for WriteReq accesses 733system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015864 # mshr miss rate for WriteReq accesses 734system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230261 # mshr miss rate for SoftPFReq accesses 735system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230261 # mshr miss rate for SoftPFReq accesses 736system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017695 # mshr miss rate for LoadLockedReq accesses 737system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017695 # mshr miss rate for LoadLockedReq accesses | 710system.cpu.dcache.demand_mshr_misses::cpu.data 719173 # number of demand (read+write) MSHR misses 711system.cpu.dcache.demand_mshr_misses::total 719173 # number of demand (read+write) MSHR misses 712system.cpu.dcache.overall_mshr_misses::cpu.data 840187 # number of overall MSHR misses 713system.cpu.dcache.overall_mshr_misses::total 840187 # number of overall MSHR misses 714system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable 715system.cpu.dcache.ReadReq_mshr_uncacheable::total 31128 # number of ReadReq MSHR uncacheable 716system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable 717system.cpu.dcache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable 718system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses 719system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses 720system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6004353500 # number of ReadReq MSHR miss cycles 721system.cpu.dcache.ReadReq_mshr_miss_latency::total 6004353500 # number of ReadReq MSHR miss cycles 722system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12472700000 # number of WriteReq MSHR miss cycles 723system.cpu.dcache.WriteReq_mshr_miss_latency::total 12472700000 # number of WriteReq MSHR miss cycles 724system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1605906500 # number of SoftPFReq MSHR miss cycles 725system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1605906500 # number of SoftPFReq MSHR miss cycles 726system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 111255000 # number of LoadLockedReq MSHR miss cycles 727system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 111255000 # number of LoadLockedReq MSHR miss cycles 728system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 167000 # number of StoreCondReq MSHR miss cycles 729system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 167000 # number of StoreCondReq MSHR miss cycles 730system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18477053500 # number of demand (read+write) MSHR miss cycles 731system.cpu.dcache.demand_mshr_miss_latency::total 18477053500 # number of demand (read+write) MSHR miss cycles 732system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20082960000 # number of overall MSHR miss cycles 733system.cpu.dcache.overall_mshr_miss_latency::total 20082960000 # number of overall MSHR miss cycles 734system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6301797000 # number of ReadReq MSHR uncacheable cycles 735system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6301797000 # number of ReadReq MSHR uncacheable cycles 736system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6301797000 # number of overall MSHR uncacheable cycles 737system.cpu.dcache.overall_mshr_uncacheable_latency::total 6301797000 # number of overall MSHR uncacheable cycles 738system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017838 # mshr miss rate for ReadReq accesses 739system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017838 # mshr miss rate for ReadReq accesses 740system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015838 # mshr miss rate for WriteReq accesses 741system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015838 # mshr miss rate for WriteReq accesses 742system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.229934 # mshr miss rate for SoftPFReq accesses 743system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.229934 # mshr miss rate for SoftPFReq accesses 744system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017879 # mshr miss rate for LoadLockedReq accesses 745system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017879 # mshr miss rate for LoadLockedReq accesses |
| 738system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 739system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses | 746system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 747system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses |
| 740system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016915 # mshr miss rate for demand accesses 741system.cpu.dcache.demand_mshr_miss_rate::total 0.016915 # mshr miss rate for demand accesses 742system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019528 # mshr miss rate for overall accesses 743system.cpu.dcache.overall_mshr_miss_rate::total 0.019528 # mshr miss rate for overall accesses 744system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15650.114636 # average ReadReq mshr miss latency 745system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15650.114636 # average ReadReq mshr miss latency 746system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64418.511235 # average WriteReq mshr miss latency 747system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64418.511235 # average WriteReq mshr miss latency 748system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14041.790429 # average SoftPFReq mshr miss latency 749system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14041.790429 # average SoftPFReq mshr miss latency 750system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13999.272463 # average LoadLockedReq mshr miss latency 751system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13999.272463 # average LoadLockedReq mshr miss latency 752system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82500 # average StoreCondReq mshr miss latency 753system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82500 # average StoreCondReq mshr miss latency 754system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35954.077832 # average overall mshr miss latency 755system.cpu.dcache.demand_avg_mshr_miss_latency::total 35954.077832 # average overall mshr miss latency 756system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32789.957931 # average overall mshr miss latency 757system.cpu.dcache.overall_avg_mshr_miss_latency::total 32789.957931 # average overall mshr miss latency 758system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202341.085769 # average ReadReq mshr uncacheable latency 759system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202341.085769 # average ReadReq mshr uncacheable latency 760system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107280.682631 # average overall mshr uncacheable latency 761system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107280.682631 # average overall mshr uncacheable latency 762system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 763system.cpu.icache.tags.replacements 2894242 # number of replacements 764system.cpu.icache.tags.tagsinuse 511.201941 # Cycle average of tags in use 765system.cpu.icache.tags.total_refs 54613603 # Total number of references to valid blocks. 766system.cpu.icache.tags.sampled_refs 2894754 # Sample count of references to valid blocks. 767system.cpu.icache.tags.avg_refs 18.866406 # Average number of references to valid blocks. 768system.cpu.icache.tags.warmup_cycle 18510731500 # Cycle when the warmup percentage was hit. 769system.cpu.icache.tags.occ_blocks::cpu.inst 511.201941 # Average occupied blocks per requestor 770system.cpu.icache.tags.occ_percent::cpu.inst 0.998441 # Average percentage of cache occupancy 771system.cpu.icache.tags.occ_percent::total 0.998441 # Average percentage of cache occupancy | 748system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016950 # mshr miss rate for demand accesses 749system.cpu.dcache.demand_mshr_miss_rate::total 0.016950 # mshr miss rate for demand accesses 750system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019560 # mshr miss rate for overall accesses 751system.cpu.dcache.overall_mshr_miss_rate::total 0.019560 # mshr miss rate for overall accesses 752system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14267.307359 # average ReadReq mshr miss latency 753system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14267.307359 # average ReadReq mshr miss latency 754system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41808.960667 # average WriteReq mshr miss latency 755system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41808.960667 # average WriteReq mshr miss latency 756system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13270.419125 # average SoftPFReq mshr miss latency 757system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13270.419125 # average SoftPFReq mshr miss latency 758system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13359.149856 # average LoadLockedReq mshr miss latency 759system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13359.149856 # average LoadLockedReq mshr miss latency 760system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 83500 # average StoreCondReq mshr miss latency 761system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 83500 # average StoreCondReq mshr miss latency 762system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25692.084519 # average overall mshr miss latency 763system.cpu.dcache.demand_avg_mshr_miss_latency::total 25692.084519 # average overall mshr miss latency 764system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23902.964459 # average overall mshr miss latency 765system.cpu.dcache.overall_avg_mshr_miss_latency::total 23902.964459 # average overall mshr miss latency 766system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202447.860447 # average ReadReq mshr uncacheable latency 767system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202447.860447 # average ReadReq mshr uncacheable latency 768system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107335.882543 # average overall mshr uncacheable latency 769system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107335.882543 # average overall mshr uncacheable latency 770system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 771system.cpu.icache.tags.replacements 2889133 # number of replacements 772system.cpu.icache.tags.tagsinuse 511.392140 # Cycle average of tags in use 773system.cpu.icache.tags.total_refs 54584955 # Total number of references to valid blocks. 774system.cpu.icache.tags.sampled_refs 2889645 # Sample count of references to valid blocks. 775system.cpu.icache.tags.avg_refs 18.889848 # Average number of references to valid blocks. 776system.cpu.icache.tags.warmup_cycle 15688442500 # Cycle when the warmup percentage was hit. 777system.cpu.icache.tags.occ_blocks::cpu.inst 511.392140 # Average occupied blocks per requestor 778system.cpu.icache.tags.occ_percent::cpu.inst 0.998813 # Average percentage of cache occupancy 779system.cpu.icache.tags.occ_percent::total 0.998813 # Average percentage of cache occupancy |
| 772system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 780system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 773system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 774system.cpu.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 775system.cpu.icache.tags.age_task_id_blocks_1024::2 200 # Occupied blocks per task id | 781system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 782system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id 783system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id |
| 776system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 784system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 777system.cpu.icache.tags.tag_accesses 60403134 # Number of tag accesses 778system.cpu.icache.tags.data_accesses 60403134 # Number of data accesses 779system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 780system.cpu.icache.ReadReq_hits::cpu.inst 54613603 # number of ReadReq hits 781system.cpu.icache.ReadReq_hits::total 54613603 # number of ReadReq hits 782system.cpu.icache.demand_hits::cpu.inst 54613603 # number of demand (read+write) hits 783system.cpu.icache.demand_hits::total 54613603 # number of demand (read+write) hits 784system.cpu.icache.overall_hits::cpu.inst 54613603 # number of overall hits 785system.cpu.icache.overall_hits::total 54613603 # number of overall hits 786system.cpu.icache.ReadReq_misses::cpu.inst 2894766 # number of ReadReq misses 787system.cpu.icache.ReadReq_misses::total 2894766 # number of ReadReq misses 788system.cpu.icache.demand_misses::cpu.inst 2894766 # number of demand (read+write) misses 789system.cpu.icache.demand_misses::total 2894766 # number of demand (read+write) misses 790system.cpu.icache.overall_misses::cpu.inst 2894766 # number of overall misses 791system.cpu.icache.overall_misses::total 2894766 # number of overall misses 792system.cpu.icache.ReadReq_miss_latency::cpu.inst 40456280000 # number of ReadReq miss cycles 793system.cpu.icache.ReadReq_miss_latency::total 40456280000 # number of ReadReq miss cycles 794system.cpu.icache.demand_miss_latency::cpu.inst 40456280000 # number of demand (read+write) miss cycles 795system.cpu.icache.demand_miss_latency::total 40456280000 # number of demand (read+write) miss cycles 796system.cpu.icache.overall_miss_latency::cpu.inst 40456280000 # number of overall miss cycles 797system.cpu.icache.overall_miss_latency::total 40456280000 # number of overall miss cycles 798system.cpu.icache.ReadReq_accesses::cpu.inst 57508369 # number of ReadReq accesses(hits+misses) 799system.cpu.icache.ReadReq_accesses::total 57508369 # number of ReadReq accesses(hits+misses) 800system.cpu.icache.demand_accesses::cpu.inst 57508369 # number of demand (read+write) accesses 801system.cpu.icache.demand_accesses::total 57508369 # number of demand (read+write) accesses 802system.cpu.icache.overall_accesses::cpu.inst 57508369 # number of overall (read+write) accesses 803system.cpu.icache.overall_accesses::total 57508369 # number of overall (read+write) accesses 804system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050336 # miss rate for ReadReq accesses 805system.cpu.icache.ReadReq_miss_rate::total 0.050336 # miss rate for ReadReq accesses 806system.cpu.icache.demand_miss_rate::cpu.inst 0.050336 # miss rate for demand accesses 807system.cpu.icache.demand_miss_rate::total 0.050336 # miss rate for demand accesses 808system.cpu.icache.overall_miss_rate::cpu.inst 0.050336 # miss rate for overall accesses 809system.cpu.icache.overall_miss_rate::total 0.050336 # miss rate for overall accesses 810system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13975.665045 # average ReadReq miss latency 811system.cpu.icache.ReadReq_avg_miss_latency::total 13975.665045 # average ReadReq miss latency 812system.cpu.icache.demand_avg_miss_latency::cpu.inst 13975.665045 # average overall miss latency 813system.cpu.icache.demand_avg_miss_latency::total 13975.665045 # average overall miss latency 814system.cpu.icache.overall_avg_miss_latency::cpu.inst 13975.665045 # average overall miss latency 815system.cpu.icache.overall_avg_miss_latency::total 13975.665045 # average overall miss latency | 785system.cpu.icache.tags.tag_accesses 60364268 # Number of tag accesses 786system.cpu.icache.tags.data_accesses 60364268 # Number of data accesses 787system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 788system.cpu.icache.ReadReq_hits::cpu.inst 54584955 # number of ReadReq hits 789system.cpu.icache.ReadReq_hits::total 54584955 # number of ReadReq hits 790system.cpu.icache.demand_hits::cpu.inst 54584955 # number of demand (read+write) hits 791system.cpu.icache.demand_hits::total 54584955 # number of demand (read+write) hits 792system.cpu.icache.overall_hits::cpu.inst 54584955 # number of overall hits 793system.cpu.icache.overall_hits::total 54584955 # number of overall hits 794system.cpu.icache.ReadReq_misses::cpu.inst 2889657 # number of ReadReq misses 795system.cpu.icache.ReadReq_misses::total 2889657 # number of ReadReq misses 796system.cpu.icache.demand_misses::cpu.inst 2889657 # number of demand (read+write) misses 797system.cpu.icache.demand_misses::total 2889657 # number of demand (read+write) misses 798system.cpu.icache.overall_misses::cpu.inst 2889657 # number of overall misses 799system.cpu.icache.overall_misses::total 2889657 # number of overall misses 800system.cpu.icache.ReadReq_miss_latency::cpu.inst 39245614500 # number of ReadReq miss cycles 801system.cpu.icache.ReadReq_miss_latency::total 39245614500 # number of ReadReq miss cycles 802system.cpu.icache.demand_miss_latency::cpu.inst 39245614500 # number of demand (read+write) miss cycles 803system.cpu.icache.demand_miss_latency::total 39245614500 # number of demand (read+write) miss cycles 804system.cpu.icache.overall_miss_latency::cpu.inst 39245614500 # number of overall miss cycles 805system.cpu.icache.overall_miss_latency::total 39245614500 # number of overall miss cycles 806system.cpu.icache.ReadReq_accesses::cpu.inst 57474612 # number of ReadReq accesses(hits+misses) 807system.cpu.icache.ReadReq_accesses::total 57474612 # number of ReadReq accesses(hits+misses) 808system.cpu.icache.demand_accesses::cpu.inst 57474612 # number of demand (read+write) accesses 809system.cpu.icache.demand_accesses::total 57474612 # number of demand (read+write) accesses 810system.cpu.icache.overall_accesses::cpu.inst 57474612 # number of overall (read+write) accesses 811system.cpu.icache.overall_accesses::total 57474612 # number of overall (read+write) accesses 812system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050277 # miss rate for ReadReq accesses 813system.cpu.icache.ReadReq_miss_rate::total 0.050277 # miss rate for ReadReq accesses 814system.cpu.icache.demand_miss_rate::cpu.inst 0.050277 # miss rate for demand accesses 815system.cpu.icache.demand_miss_rate::total 0.050277 # miss rate for demand accesses 816system.cpu.icache.overall_miss_rate::cpu.inst 0.050277 # miss rate for overall accesses 817system.cpu.icache.overall_miss_rate::total 0.050277 # miss rate for overall accesses 818system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13581.409316 # average ReadReq miss latency 819system.cpu.icache.ReadReq_avg_miss_latency::total 13581.409316 # average ReadReq miss latency 820system.cpu.icache.demand_avg_miss_latency::cpu.inst 13581.409316 # average overall miss latency 821system.cpu.icache.demand_avg_miss_latency::total 13581.409316 # average overall miss latency 822system.cpu.icache.overall_avg_miss_latency::cpu.inst 13581.409316 # average overall miss latency 823system.cpu.icache.overall_avg_miss_latency::total 13581.409316 # average overall miss latency |
| 816system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 817system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 818system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 819system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 820system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 821system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 824system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 825system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 826system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 827system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 828system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 829system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 822system.cpu.icache.writebacks::writebacks 2894242 # number of writebacks 823system.cpu.icache.writebacks::total 2894242 # number of writebacks 824system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2894766 # number of ReadReq MSHR misses 825system.cpu.icache.ReadReq_mshr_misses::total 2894766 # number of ReadReq MSHR misses 826system.cpu.icache.demand_mshr_misses::cpu.inst 2894766 # number of demand (read+write) MSHR misses 827system.cpu.icache.demand_mshr_misses::total 2894766 # number of demand (read+write) MSHR misses 828system.cpu.icache.overall_mshr_misses::cpu.inst 2894766 # number of overall MSHR misses 829system.cpu.icache.overall_mshr_misses::total 2894766 # number of overall MSHR misses 830system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3758 # number of ReadReq MSHR uncacheable 831system.cpu.icache.ReadReq_mshr_uncacheable::total 3758 # number of ReadReq MSHR uncacheable 832system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3758 # number of overall MSHR uncacheable misses 833system.cpu.icache.overall_mshr_uncacheable_misses::total 3758 # number of overall MSHR uncacheable misses 834system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37561515000 # number of ReadReq MSHR miss cycles 835system.cpu.icache.ReadReq_mshr_miss_latency::total 37561515000 # number of ReadReq MSHR miss cycles 836system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37561515000 # number of demand (read+write) MSHR miss cycles 837system.cpu.icache.demand_mshr_miss_latency::total 37561515000 # number of demand (read+write) MSHR miss cycles 838system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37561515000 # number of overall MSHR miss cycles 839system.cpu.icache.overall_mshr_miss_latency::total 37561515000 # number of overall MSHR miss cycles 840system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 485617000 # number of ReadReq MSHR uncacheable cycles 841system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 485617000 # number of ReadReq MSHR uncacheable cycles 842system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 485617000 # number of overall MSHR uncacheable cycles 843system.cpu.icache.overall_mshr_uncacheable_latency::total 485617000 # number of overall MSHR uncacheable cycles 844system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050336 # mshr miss rate for ReadReq accesses 845system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050336 # mshr miss rate for ReadReq accesses 846system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050336 # mshr miss rate for demand accesses 847system.cpu.icache.demand_mshr_miss_rate::total 0.050336 # mshr miss rate for demand accesses 848system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050336 # mshr miss rate for overall accesses 849system.cpu.icache.overall_mshr_miss_rate::total 0.050336 # mshr miss rate for overall accesses 850system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12975.665391 # average ReadReq mshr miss latency 851system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12975.665391 # average ReadReq mshr miss latency 852system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12975.665391 # average overall mshr miss latency 853system.cpu.icache.demand_avg_mshr_miss_latency::total 12975.665391 # average overall mshr miss latency 854system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12975.665391 # average overall mshr miss latency 855system.cpu.icache.overall_avg_mshr_miss_latency::total 12975.665391 # average overall mshr miss latency 856system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129222.192656 # average ReadReq mshr uncacheable latency 857system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129222.192656 # average ReadReq mshr uncacheable latency 858system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129222.192656 # average overall mshr uncacheable latency 859system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129222.192656 # average overall mshr uncacheable latency 860system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 861system.cpu.l2cache.tags.replacements 96413 # number of replacements 862system.cpu.l2cache.tags.tagsinuse 65014.111647 # Cycle average of tags in use 863system.cpu.l2cache.tags.total_refs 7029815 # Total number of references to valid blocks. 864system.cpu.l2cache.tags.sampled_refs 161656 # Sample count of references to valid blocks. 865system.cpu.l2cache.tags.avg_refs 43.486261 # Average number of references to valid blocks. 866system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 867system.cpu.l2cache.tags.occ_blocks::writebacks 47147.953940 # Average occupied blocks per requestor 868system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 65.794382 # Average occupied blocks per requestor 869system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.010019 # Average occupied blocks per requestor 870system.cpu.l2cache.tags.occ_blocks::cpu.inst 12263.315434 # Average occupied blocks per requestor 871system.cpu.l2cache.tags.occ_blocks::cpu.data 5537.037871 # Average occupied blocks per requestor 872system.cpu.l2cache.tags.occ_percent::writebacks 0.719421 # Average percentage of cache occupancy 873system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001004 # Average percentage of cache occupancy | 830system.cpu.icache.writebacks::writebacks 2889133 # number of writebacks 831system.cpu.icache.writebacks::total 2889133 # number of writebacks 832system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2889657 # number of ReadReq MSHR misses 833system.cpu.icache.ReadReq_mshr_misses::total 2889657 # number of ReadReq MSHR misses 834system.cpu.icache.demand_mshr_misses::cpu.inst 2889657 # number of demand (read+write) MSHR misses 835system.cpu.icache.demand_mshr_misses::total 2889657 # number of demand (read+write) MSHR misses 836system.cpu.icache.overall_mshr_misses::cpu.inst 2889657 # number of overall MSHR misses 837system.cpu.icache.overall_mshr_misses::total 2889657 # number of overall MSHR misses 838system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3267 # number of ReadReq MSHR uncacheable 839system.cpu.icache.ReadReq_mshr_uncacheable::total 3267 # number of ReadReq MSHR uncacheable 840system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3267 # number of overall MSHR uncacheable misses 841system.cpu.icache.overall_mshr_uncacheable_misses::total 3267 # number of overall MSHR uncacheable misses 842system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36355958500 # number of ReadReq MSHR miss cycles 843system.cpu.icache.ReadReq_mshr_miss_latency::total 36355958500 # number of ReadReq MSHR miss cycles 844system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36355958500 # number of demand (read+write) MSHR miss cycles 845system.cpu.icache.demand_mshr_miss_latency::total 36355958500 # number of demand (read+write) MSHR miss cycles 846system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36355958500 # number of overall MSHR miss cycles 847system.cpu.icache.overall_mshr_miss_latency::total 36355958500 # number of overall MSHR miss cycles 848system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 258265000 # number of ReadReq MSHR uncacheable cycles 849system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 258265000 # number of ReadReq MSHR uncacheable cycles 850system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 258265000 # number of overall MSHR uncacheable cycles 851system.cpu.icache.overall_mshr_uncacheable_latency::total 258265000 # number of overall MSHR uncacheable cycles 852system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050277 # mshr miss rate for ReadReq accesses 853system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050277 # mshr miss rate for ReadReq accesses 854system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050277 # mshr miss rate for demand accesses 855system.cpu.icache.demand_mshr_miss_rate::total 0.050277 # mshr miss rate for demand accesses 856system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050277 # mshr miss rate for overall accesses 857system.cpu.icache.overall_mshr_miss_rate::total 0.050277 # mshr miss rate for overall accesses 858system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12581.409662 # average ReadReq mshr miss latency 859system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12581.409662 # average ReadReq mshr miss latency 860system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12581.409662 # average overall mshr miss latency 861system.cpu.icache.demand_avg_mshr_miss_latency::total 12581.409662 # average overall mshr miss latency 862system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12581.409662 # average overall mshr miss latency 863system.cpu.icache.overall_avg_mshr_miss_latency::total 12581.409662 # average overall mshr miss latency 864system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 79052.647689 # average ReadReq mshr uncacheable latency 865system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 79052.647689 # average ReadReq mshr uncacheable latency 866system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 79052.647689 # average overall mshr uncacheable latency 867system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 79052.647689 # average overall mshr uncacheable latency 868system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 869system.cpu.l2cache.tags.replacements 96859 # number of replacements 870system.cpu.l2cache.tags.tagsinuse 65151.144064 # Cycle average of tags in use 871system.cpu.l2cache.tags.total_refs 7317028 # Total number of references to valid blocks. 872system.cpu.l2cache.tags.sampled_refs 162271 # Sample count of references to valid blocks. 873system.cpu.l2cache.tags.avg_refs 45.091409 # Average number of references to valid blocks. 874system.cpu.l2cache.tags.warmup_cycle 94922732000 # Cycle when the warmup percentage was hit. 875system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 70.044406 # Average occupied blocks per requestor 876system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023437 # Average occupied blocks per requestor 877system.cpu.l2cache.tags.occ_blocks::cpu.inst 12290.016649 # Average occupied blocks per requestor 878system.cpu.l2cache.tags.occ_blocks::cpu.data 52791.059572 # Average occupied blocks per requestor 879system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001069 # Average percentage of cache occupancy |
| 874system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy | 880system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy |
| 875system.cpu.l2cache.tags.occ_percent::cpu.inst 0.187123 # Average percentage of cache occupancy 876system.cpu.l2cache.tags.occ_percent::cpu.data 0.084488 # Average percentage of cache occupancy 877system.cpu.l2cache.tags.occ_percent::total 0.992037 # Average percentage of cache occupancy 878system.cpu.l2cache.tags.occ_task_id_blocks::1023 54 # Occupied blocks per task id 879system.cpu.l2cache.tags.occ_task_id_blocks::1024 65189 # Occupied blocks per task id 880system.cpu.l2cache.tags.age_task_id_blocks_1023::4 54 # Occupied blocks per task id 881system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 882system.cpu.l2cache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id 883system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2263 # Occupied blocks per task id 884system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6860 # Occupied blocks per task id 885system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55955 # Occupied blocks per task id 886system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000824 # Percentage of cache occupancy per task id 887system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994705 # Percentage of cache occupancy per task id 888system.cpu.l2cache.tags.tag_accesses 60474648 # Number of tag accesses 889system.cpu.l2cache.tags.data_accesses 60474648 # Number of data accesses 890system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 891system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 73812 # number of ReadReq hits 892system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4869 # number of ReadReq hits 893system.cpu.l2cache.ReadReq_hits::total 78681 # number of ReadReq hits 894system.cpu.l2cache.WritebackDirty_hits::writebacks 701092 # number of WritebackDirty hits 895system.cpu.l2cache.WritebackDirty_hits::total 701092 # number of WritebackDirty hits 896system.cpu.l2cache.WritebackClean_hits::writebacks 2843365 # number of WritebackClean hits 897system.cpu.l2cache.WritebackClean_hits::total 2843365 # number of WritebackClean hits 898system.cpu.l2cache.UpgradeReq_hits::cpu.data 49 # number of UpgradeReq hits 899system.cpu.l2cache.UpgradeReq_hits::total 49 # number of UpgradeReq hits 900system.cpu.l2cache.ReadExReq_hits::cpu.data 165406 # number of ReadExReq hits 901system.cpu.l2cache.ReadExReq_hits::total 165406 # number of ReadExReq hits 902system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2871798 # number of ReadCleanReq hits 903system.cpu.l2cache.ReadCleanReq_hits::total 2871798 # number of ReadCleanReq hits 904system.cpu.l2cache.ReadSharedReq_hits::cpu.data 534162 # number of ReadSharedReq hits 905system.cpu.l2cache.ReadSharedReq_hits::total 534162 # number of ReadSharedReq hits 906system.cpu.l2cache.demand_hits::cpu.dtb.walker 73812 # number of demand (read+write) hits 907system.cpu.l2cache.demand_hits::cpu.itb.walker 4869 # number of demand (read+write) hits 908system.cpu.l2cache.demand_hits::cpu.inst 2871798 # number of demand (read+write) hits 909system.cpu.l2cache.demand_hits::cpu.data 699568 # number of demand (read+write) hits 910system.cpu.l2cache.demand_hits::total 3650047 # number of demand (read+write) hits 911system.cpu.l2cache.overall_hits::cpu.dtb.walker 73812 # number of overall hits 912system.cpu.l2cache.overall_hits::cpu.itb.walker 4869 # number of overall hits 913system.cpu.l2cache.overall_hits::cpu.inst 2871798 # number of overall hits 914system.cpu.l2cache.overall_hits::cpu.data 699568 # number of overall hits 915system.cpu.l2cache.overall_hits::total 3650047 # number of overall hits 916system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 125 # number of ReadReq misses 917system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 918system.cpu.l2cache.ReadReq_misses::total 127 # number of ReadReq misses 919system.cpu.l2cache.UpgradeReq_misses::cpu.data 2735 # number of UpgradeReq misses 920system.cpu.l2cache.UpgradeReq_misses::total 2735 # number of UpgradeReq misses | 881system.cpu.l2cache.tags.occ_percent::cpu.inst 0.187531 # Average percentage of cache occupancy 882system.cpu.l2cache.tags.occ_percent::cpu.data 0.805528 # Average percentage of cache occupancy 883system.cpu.l2cache.tags.occ_percent::total 0.994128 # Average percentage of cache occupancy 884system.cpu.l2cache.tags.occ_task_id_blocks::1023 63 # Occupied blocks per task id 885system.cpu.l2cache.tags.occ_task_id_blocks::1024 65349 # Occupied blocks per task id 886system.cpu.l2cache.tags.age_task_id_blocks_1023::4 63 # Occupied blocks per task id 887system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 888system.cpu.l2cache.tags.age_task_id_blocks_1024::2 80 # Occupied blocks per task id 889system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4600 # Occupied blocks per task id 890system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60668 # Occupied blocks per task id 891system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000961 # Percentage of cache occupancy per task id 892system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997147 # Percentage of cache occupancy per task id 893system.cpu.l2cache.tags.tag_accesses 60051875 # Number of tag accesses 894system.cpu.l2cache.tags.data_accesses 60051875 # Number of data accesses 895system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 896system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 67793 # number of ReadReq hits 897system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3314 # number of ReadReq hits 898system.cpu.l2cache.ReadReq_hits::total 71107 # number of ReadReq hits 899system.cpu.l2cache.WritebackDirty_hits::writebacks 700399 # number of WritebackDirty hits 900system.cpu.l2cache.WritebackDirty_hits::total 700399 # number of WritebackDirty hits 901system.cpu.l2cache.WritebackClean_hits::writebacks 2838445 # number of WritebackClean hits 902system.cpu.l2cache.WritebackClean_hits::total 2838445 # number of WritebackClean hits 903system.cpu.l2cache.UpgradeReq_hits::cpu.data 2804 # number of UpgradeReq hits 904system.cpu.l2cache.UpgradeReq_hits::total 2804 # number of UpgradeReq hits 905system.cpu.l2cache.ReadExReq_hits::cpu.data 166282 # number of ReadExReq hits 906system.cpu.l2cache.ReadExReq_hits::total 166282 # number of ReadExReq hits 907system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2866680 # number of ReadCleanReq hits 908system.cpu.l2cache.ReadCleanReq_hits::total 2866680 # number of ReadCleanReq hits 909system.cpu.l2cache.ReadSharedReq_hits::cpu.data 535530 # number of ReadSharedReq hits 910system.cpu.l2cache.ReadSharedReq_hits::total 535530 # number of ReadSharedReq hits 911system.cpu.l2cache.demand_hits::cpu.dtb.walker 67793 # number of demand (read+write) hits 912system.cpu.l2cache.demand_hits::cpu.itb.walker 3314 # number of demand (read+write) hits 913system.cpu.l2cache.demand_hits::cpu.inst 2866680 # number of demand (read+write) hits 914system.cpu.l2cache.demand_hits::cpu.data 701812 # number of demand (read+write) hits 915system.cpu.l2cache.demand_hits::total 3639599 # number of demand (read+write) hits 916system.cpu.l2cache.overall_hits::cpu.dtb.walker 67793 # number of overall hits 917system.cpu.l2cache.overall_hits::cpu.itb.walker 3314 # number of overall hits 918system.cpu.l2cache.overall_hits::cpu.inst 2866680 # number of overall hits 919system.cpu.l2cache.overall_hits::cpu.data 701812 # number of overall hits 920system.cpu.l2cache.overall_hits::total 3639599 # number of overall hits 921system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 120 # number of ReadReq misses 922system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses 923system.cpu.l2cache.ReadReq_misses::total 121 # number of ReadReq misses 924system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses 925system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses |
| 921system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 922system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses | 926system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 927system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses |
| 923system.cpu.l2cache.ReadExReq_misses::cpu.data 130801 # number of ReadExReq misses 924system.cpu.l2cache.ReadExReq_misses::total 130801 # number of ReadExReq misses 925system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22943 # number of ReadCleanReq misses 926system.cpu.l2cache.ReadCleanReq_misses::total 22943 # number of ReadCleanReq misses 927system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14433 # number of ReadSharedReq misses 928system.cpu.l2cache.ReadSharedReq_misses::total 14433 # number of ReadSharedReq misses 929system.cpu.l2cache.demand_misses::cpu.dtb.walker 125 # number of demand (read+write) misses 930system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 931system.cpu.l2cache.demand_misses::cpu.inst 22943 # number of demand (read+write) misses 932system.cpu.l2cache.demand_misses::cpu.data 145234 # number of demand (read+write) misses 933system.cpu.l2cache.demand_misses::total 168304 # number of demand (read+write) misses 934system.cpu.l2cache.overall_misses::cpu.dtb.walker 125 # number of overall misses 935system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 936system.cpu.l2cache.overall_misses::cpu.inst 22943 # number of overall misses 937system.cpu.l2cache.overall_misses::cpu.data 145234 # number of overall misses 938system.cpu.l2cache.overall_misses::total 168304 # number of overall misses 939system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 17568500 # number of ReadReq miss cycles 940system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 265500 # number of ReadReq miss cycles 941system.cpu.l2cache.ReadReq_miss_latency::total 17834000 # number of ReadReq miss cycles 942system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2884500 # number of UpgradeReq miss cycles 943system.cpu.l2cache.UpgradeReq_miss_latency::total 2884500 # number of UpgradeReq miss cycles 944system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles 945system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles 946system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16851679500 # number of ReadExReq miss cycles 947system.cpu.l2cache.ReadExReq_miss_latency::total 16851679500 # number of ReadExReq miss cycles 948system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2998117000 # number of ReadCleanReq miss cycles 949system.cpu.l2cache.ReadCleanReq_miss_latency::total 2998117000 # number of ReadCleanReq miss cycles 950system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1905130500 # number of ReadSharedReq miss cycles 951system.cpu.l2cache.ReadSharedReq_miss_latency::total 1905130500 # number of ReadSharedReq miss cycles 952system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 17568500 # number of demand (read+write) miss cycles 953system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 265500 # number of demand (read+write) miss cycles 954system.cpu.l2cache.demand_miss_latency::cpu.inst 2998117000 # number of demand (read+write) miss cycles 955system.cpu.l2cache.demand_miss_latency::cpu.data 18756810000 # number of demand (read+write) miss cycles 956system.cpu.l2cache.demand_miss_latency::total 21772761000 # number of demand (read+write) miss cycles 957system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 17568500 # number of overall miss cycles 958system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 265500 # number of overall miss cycles 959system.cpu.l2cache.overall_miss_latency::cpu.inst 2998117000 # number of overall miss cycles 960system.cpu.l2cache.overall_miss_latency::cpu.data 18756810000 # number of overall miss cycles 961system.cpu.l2cache.overall_miss_latency::total 21772761000 # number of overall miss cycles 962system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 73937 # number of ReadReq accesses(hits+misses) 963system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4871 # number of ReadReq accesses(hits+misses) 964system.cpu.l2cache.ReadReq_accesses::total 78808 # number of ReadReq accesses(hits+misses) 965system.cpu.l2cache.WritebackDirty_accesses::writebacks 701092 # number of WritebackDirty accesses(hits+misses) 966system.cpu.l2cache.WritebackDirty_accesses::total 701092 # number of WritebackDirty accesses(hits+misses) 967system.cpu.l2cache.WritebackClean_accesses::writebacks 2843365 # number of WritebackClean accesses(hits+misses) 968system.cpu.l2cache.WritebackClean_accesses::total 2843365 # number of WritebackClean accesses(hits+misses) 969system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2784 # number of UpgradeReq accesses(hits+misses) 970system.cpu.l2cache.UpgradeReq_accesses::total 2784 # number of UpgradeReq accesses(hits+misses) | 928system.cpu.l2cache.ReadExReq_misses::cpu.data 129240 # number of ReadExReq misses 929system.cpu.l2cache.ReadExReq_misses::total 129240 # number of ReadExReq misses 930system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22945 # number of ReadCleanReq misses 931system.cpu.l2cache.ReadCleanReq_misses::total 22945 # number of ReadCleanReq misses 932system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14654 # number of ReadSharedReq misses 933system.cpu.l2cache.ReadSharedReq_misses::total 14654 # number of ReadSharedReq misses 934system.cpu.l2cache.demand_misses::cpu.dtb.walker 120 # number of demand (read+write) misses 935system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses 936system.cpu.l2cache.demand_misses::cpu.inst 22945 # number of demand (read+write) misses 937system.cpu.l2cache.demand_misses::cpu.data 143894 # number of demand (read+write) misses 938system.cpu.l2cache.demand_misses::total 166960 # number of demand (read+write) misses 939system.cpu.l2cache.overall_misses::cpu.dtb.walker 120 # number of overall misses 940system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses 941system.cpu.l2cache.overall_misses::cpu.inst 22945 # number of overall misses 942system.cpu.l2cache.overall_misses::cpu.data 143894 # number of overall misses 943system.cpu.l2cache.overall_misses::total 166960 # number of overall misses 944system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 10289000 # number of ReadReq miss cycles 945system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 83500 # number of ReadReq miss cycles 946system.cpu.l2cache.ReadReq_miss_latency::total 10372500 # number of ReadReq miss cycles 947system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 145500 # number of UpgradeReq miss cycles 948system.cpu.l2cache.UpgradeReq_miss_latency::total 145500 # number of UpgradeReq miss cycles 949system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 164000 # number of SCUpgradeReq miss cycles 950system.cpu.l2cache.SCUpgradeReq_miss_latency::total 164000 # number of SCUpgradeReq miss cycles 951system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10239764000 # number of ReadExReq miss cycles 952system.cpu.l2cache.ReadExReq_miss_latency::total 10239764000 # number of ReadExReq miss cycles 953system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1854577500 # number of ReadCleanReq miss cycles 954system.cpu.l2cache.ReadCleanReq_miss_latency::total 1854577500 # number of ReadCleanReq miss cycles 955system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1232673000 # number of ReadSharedReq miss cycles 956system.cpu.l2cache.ReadSharedReq_miss_latency::total 1232673000 # number of ReadSharedReq miss cycles 957system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 10289000 # number of demand (read+write) miss cycles 958system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 83500 # number of demand (read+write) miss cycles 959system.cpu.l2cache.demand_miss_latency::cpu.inst 1854577500 # number of demand (read+write) miss cycles 960system.cpu.l2cache.demand_miss_latency::cpu.data 11472437000 # number of demand (read+write) miss cycles 961system.cpu.l2cache.demand_miss_latency::total 13337387000 # number of demand (read+write) miss cycles 962system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 10289000 # number of overall miss cycles 963system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 83500 # number of overall miss cycles 964system.cpu.l2cache.overall_miss_latency::cpu.inst 1854577500 # number of overall miss cycles 965system.cpu.l2cache.overall_miss_latency::cpu.data 11472437000 # number of overall miss cycles 966system.cpu.l2cache.overall_miss_latency::total 13337387000 # number of overall miss cycles 967system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 67913 # number of ReadReq accesses(hits+misses) 968system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3315 # number of ReadReq accesses(hits+misses) 969system.cpu.l2cache.ReadReq_accesses::total 71228 # number of ReadReq accesses(hits+misses) 970system.cpu.l2cache.WritebackDirty_accesses::writebacks 700399 # number of WritebackDirty accesses(hits+misses) 971system.cpu.l2cache.WritebackDirty_accesses::total 700399 # number of WritebackDirty accesses(hits+misses) 972system.cpu.l2cache.WritebackClean_accesses::writebacks 2838445 # number of WritebackClean accesses(hits+misses) 973system.cpu.l2cache.WritebackClean_accesses::total 2838445 # number of WritebackClean accesses(hits+misses) 974system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2809 # number of UpgradeReq accesses(hits+misses) 975system.cpu.l2cache.UpgradeReq_accesses::total 2809 # number of UpgradeReq accesses(hits+misses) |
| 971system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 972system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) | 976system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 977system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) |
| 973system.cpu.l2cache.ReadExReq_accesses::cpu.data 296207 # number of ReadExReq accesses(hits+misses) 974system.cpu.l2cache.ReadExReq_accesses::total 296207 # number of ReadExReq accesses(hits+misses) 975system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2894741 # number of ReadCleanReq accesses(hits+misses) 976system.cpu.l2cache.ReadCleanReq_accesses::total 2894741 # number of ReadCleanReq accesses(hits+misses) 977system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 548595 # number of ReadSharedReq accesses(hits+misses) 978system.cpu.l2cache.ReadSharedReq_accesses::total 548595 # number of ReadSharedReq accesses(hits+misses) 979system.cpu.l2cache.demand_accesses::cpu.dtb.walker 73937 # number of demand (read+write) accesses 980system.cpu.l2cache.demand_accesses::cpu.itb.walker 4871 # number of demand (read+write) accesses 981system.cpu.l2cache.demand_accesses::cpu.inst 2894741 # number of demand (read+write) accesses 982system.cpu.l2cache.demand_accesses::cpu.data 844802 # number of demand (read+write) accesses 983system.cpu.l2cache.demand_accesses::total 3818351 # number of demand (read+write) accesses 984system.cpu.l2cache.overall_accesses::cpu.dtb.walker 73937 # number of overall (read+write) accesses 985system.cpu.l2cache.overall_accesses::cpu.itb.walker 4871 # number of overall (read+write) accesses 986system.cpu.l2cache.overall_accesses::cpu.inst 2894741 # number of overall (read+write) accesses 987system.cpu.l2cache.overall_accesses::cpu.data 844802 # number of overall (read+write) accesses 988system.cpu.l2cache.overall_accesses::total 3818351 # number of overall (read+write) accesses 989system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001691 # miss rate for ReadReq accesses 990system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000411 # miss rate for ReadReq accesses 991system.cpu.l2cache.ReadReq_miss_rate::total 0.001612 # miss rate for ReadReq accesses 992system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.982399 # miss rate for UpgradeReq accesses 993system.cpu.l2cache.UpgradeReq_miss_rate::total 0.982399 # miss rate for UpgradeReq accesses | 978system.cpu.l2cache.ReadExReq_accesses::cpu.data 295522 # number of ReadExReq accesses(hits+misses) 979system.cpu.l2cache.ReadExReq_accesses::total 295522 # number of ReadExReq accesses(hits+misses) 980system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2889625 # number of ReadCleanReq accesses(hits+misses) 981system.cpu.l2cache.ReadCleanReq_accesses::total 2889625 # number of ReadCleanReq accesses(hits+misses) 982system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 550184 # number of ReadSharedReq accesses(hits+misses) 983system.cpu.l2cache.ReadSharedReq_accesses::total 550184 # number of ReadSharedReq accesses(hits+misses) 984system.cpu.l2cache.demand_accesses::cpu.dtb.walker 67913 # number of demand (read+write) accesses 985system.cpu.l2cache.demand_accesses::cpu.itb.walker 3315 # number of demand (read+write) accesses 986system.cpu.l2cache.demand_accesses::cpu.inst 2889625 # number of demand (read+write) accesses 987system.cpu.l2cache.demand_accesses::cpu.data 845706 # number of demand (read+write) accesses 988system.cpu.l2cache.demand_accesses::total 3806559 # number of demand (read+write) accesses 989system.cpu.l2cache.overall_accesses::cpu.dtb.walker 67913 # number of overall (read+write) accesses 990system.cpu.l2cache.overall_accesses::cpu.itb.walker 3315 # number of overall (read+write) accesses 991system.cpu.l2cache.overall_accesses::cpu.inst 2889625 # number of overall (read+write) accesses 992system.cpu.l2cache.overall_accesses::cpu.data 845706 # number of overall (read+write) accesses 993system.cpu.l2cache.overall_accesses::total 3806559 # number of overall (read+write) accesses 994system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001767 # miss rate for ReadReq accesses 995system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000302 # miss rate for ReadReq accesses 996system.cpu.l2cache.ReadReq_miss_rate::total 0.001699 # miss rate for ReadReq accesses 997system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.001780 # miss rate for UpgradeReq accesses 998system.cpu.l2cache.UpgradeReq_miss_rate::total 0.001780 # miss rate for UpgradeReq accesses |
| 994system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 995system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 999system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 1000system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 996system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.441586 # miss rate for ReadExReq accesses 997system.cpu.l2cache.ReadExReq_miss_rate::total 0.441586 # miss rate for ReadExReq accesses 998system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007926 # miss rate for ReadCleanReq accesses 999system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007926 # miss rate for ReadCleanReq accesses 1000system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026309 # miss rate for ReadSharedReq accesses 1001system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026309 # miss rate for ReadSharedReq accesses 1002system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001691 # miss rate for demand accesses 1003system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000411 # miss rate for demand accesses 1004system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007926 # miss rate for demand accesses 1005system.cpu.l2cache.demand_miss_rate::cpu.data 0.171915 # miss rate for demand accesses 1006system.cpu.l2cache.demand_miss_rate::total 0.044078 # miss rate for demand accesses 1007system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001691 # miss rate for overall accesses 1008system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000411 # miss rate for overall accesses 1009system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007926 # miss rate for overall accesses 1010system.cpu.l2cache.overall_miss_rate::cpu.data 0.171915 # miss rate for overall accesses 1011system.cpu.l2cache.overall_miss_rate::total 0.044078 # miss rate for overall accesses 1012system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 140548 # average ReadReq miss latency 1013system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132750 # average ReadReq miss latency 1014system.cpu.l2cache.ReadReq_avg_miss_latency::total 140425.196850 # average ReadReq miss latency 1015system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1054.661792 # average UpgradeReq miss latency 1016system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1054.661792 # average UpgradeReq miss latency 1017system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 81000 # average SCUpgradeReq miss latency 1018system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 81000 # average SCUpgradeReq miss latency 1019system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 128834.485210 # average ReadExReq miss latency 1020system.cpu.l2cache.ReadExReq_avg_miss_latency::total 128834.485210 # average ReadExReq miss latency 1021system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130676.764155 # average ReadCleanReq miss latency 1022system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130676.764155 # average ReadCleanReq miss latency 1023system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 131998.233216 # average ReadSharedReq miss latency 1024system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 131998.233216 # average ReadSharedReq miss latency 1025system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 140548 # average overall miss latency 1026system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 132750 # average overall miss latency 1027system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130676.764155 # average overall miss latency 1028system.cpu.l2cache.demand_avg_miss_latency::cpu.data 129148.890756 # average overall miss latency 1029system.cpu.l2cache.demand_avg_miss_latency::total 129365.677583 # average overall miss latency 1030system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 140548 # average overall miss latency 1031system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 132750 # average overall miss latency 1032system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130676.764155 # average overall miss latency 1033system.cpu.l2cache.overall_avg_miss_latency::cpu.data 129148.890756 # average overall miss latency 1034system.cpu.l2cache.overall_avg_miss_latency::total 129365.677583 # average overall miss latency | 1001system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437328 # miss rate for ReadExReq accesses 1002system.cpu.l2cache.ReadExReq_miss_rate::total 0.437328 # miss rate for ReadExReq accesses 1003system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007940 # miss rate for ReadCleanReq accesses 1004system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007940 # miss rate for ReadCleanReq accesses 1005system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026635 # miss rate for ReadSharedReq accesses 1006system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026635 # miss rate for ReadSharedReq accesses 1007system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001767 # miss rate for demand accesses 1008system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000302 # miss rate for demand accesses 1009system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007940 # miss rate for demand accesses 1010system.cpu.l2cache.demand_miss_rate::cpu.data 0.170147 # miss rate for demand accesses 1011system.cpu.l2cache.demand_miss_rate::total 0.043861 # miss rate for demand accesses 1012system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001767 # miss rate for overall accesses 1013system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000302 # miss rate for overall accesses 1014system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007940 # miss rate for overall accesses 1015system.cpu.l2cache.overall_miss_rate::cpu.data 0.170147 # miss rate for overall accesses 1016system.cpu.l2cache.overall_miss_rate::total 0.043861 # miss rate for overall accesses 1017system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85741.666667 # average ReadReq miss latency 1018system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83500 # average ReadReq miss latency 1019system.cpu.l2cache.ReadReq_avg_miss_latency::total 85723.140496 # average ReadReq miss latency 1020system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29100 # average UpgradeReq miss latency 1021system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29100 # average UpgradeReq miss latency 1022system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82000 # average SCUpgradeReq miss latency 1023system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82000 # average SCUpgradeReq miss latency 1024system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79230.609718 # average ReadExReq miss latency 1025system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79230.609718 # average ReadExReq miss latency 1026system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80827.086511 # average ReadCleanReq miss latency 1027system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80827.086511 # average ReadCleanReq miss latency 1028system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84118.534189 # average ReadSharedReq miss latency 1029system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84118.534189 # average ReadSharedReq miss latency 1030system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85741.666667 # average overall miss latency 1031system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83500 # average overall miss latency 1032system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80827.086511 # average overall miss latency 1033system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79728.390343 # average overall miss latency 1034system.cpu.l2cache.demand_avg_miss_latency::total 79883.726641 # average overall miss latency 1035system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85741.666667 # average overall miss latency 1036system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83500 # average overall miss latency 1037system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80827.086511 # average overall miss latency 1038system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79728.390343 # average overall miss latency 1039system.cpu.l2cache.overall_avg_miss_latency::total 79883.726641 # average overall miss latency |
| 1035system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1036system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1037system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1038system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1039system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1040system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1040system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1041system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1042system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1043system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1044system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1045system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1041system.cpu.l2cache.writebacks::writebacks 88095 # number of writebacks 1042system.cpu.l2cache.writebacks::total 88095 # number of writebacks 1043system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 20 # number of ReadCleanReq MSHR hits 1044system.cpu.l2cache.ReadCleanReq_mshr_hits::total 20 # number of ReadCleanReq MSHR hits 1045system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 141 # number of ReadSharedReq MSHR hits 1046system.cpu.l2cache.ReadSharedReq_mshr_hits::total 141 # number of ReadSharedReq MSHR hits 1047system.cpu.l2cache.demand_mshr_hits::cpu.inst 20 # number of demand (read+write) MSHR hits 1048system.cpu.l2cache.demand_mshr_hits::cpu.data 141 # number of demand (read+write) MSHR hits 1049system.cpu.l2cache.demand_mshr_hits::total 161 # number of demand (read+write) MSHR hits 1050system.cpu.l2cache.overall_mshr_hits::cpu.inst 20 # number of overall MSHR hits 1051system.cpu.l2cache.overall_mshr_hits::cpu.data 141 # number of overall MSHR hits 1052system.cpu.l2cache.overall_mshr_hits::total 161 # number of overall MSHR hits 1053system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 125 # number of ReadReq MSHR misses 1054system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 1055system.cpu.l2cache.ReadReq_mshr_misses::total 127 # number of ReadReq MSHR misses 1056system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2735 # number of UpgradeReq MSHR misses 1057system.cpu.l2cache.UpgradeReq_mshr_misses::total 2735 # number of UpgradeReq MSHR misses | 1046system.cpu.l2cache.writebacks::writebacks 88448 # number of writebacks 1047system.cpu.l2cache.writebacks::total 88448 # number of writebacks 1048system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 18 # number of ReadCleanReq MSHR hits 1049system.cpu.l2cache.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits 1050system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 136 # number of ReadSharedReq MSHR hits 1051system.cpu.l2cache.ReadSharedReq_mshr_hits::total 136 # number of ReadSharedReq MSHR hits 1052system.cpu.l2cache.demand_mshr_hits::cpu.inst 18 # number of demand (read+write) MSHR hits 1053system.cpu.l2cache.demand_mshr_hits::cpu.data 136 # number of demand (read+write) MSHR hits 1054system.cpu.l2cache.demand_mshr_hits::total 154 # number of demand (read+write) MSHR hits 1055system.cpu.l2cache.overall_mshr_hits::cpu.inst 18 # number of overall MSHR hits 1056system.cpu.l2cache.overall_mshr_hits::cpu.data 136 # number of overall MSHR hits 1057system.cpu.l2cache.overall_mshr_hits::total 154 # number of overall MSHR hits 1058system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 120 # number of ReadReq MSHR misses 1059system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses 1060system.cpu.l2cache.ReadReq_mshr_misses::total 121 # number of ReadReq MSHR misses 1061system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses 1062system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses |
| 1058system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1059system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses | 1063system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1064system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses |
| 1060system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130801 # number of ReadExReq MSHR misses 1061system.cpu.l2cache.ReadExReq_mshr_misses::total 130801 # number of ReadExReq MSHR misses 1062system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22923 # number of ReadCleanReq MSHR misses 1063system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22923 # number of ReadCleanReq MSHR misses 1064system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14292 # number of ReadSharedReq MSHR misses 1065system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14292 # number of ReadSharedReq MSHR misses 1066system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 125 # number of demand (read+write) MSHR misses 1067system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 1068system.cpu.l2cache.demand_mshr_misses::cpu.inst 22923 # number of demand (read+write) MSHR misses 1069system.cpu.l2cache.demand_mshr_misses::cpu.data 145093 # number of demand (read+write) MSHR misses 1070system.cpu.l2cache.demand_mshr_misses::total 168143 # number of demand (read+write) MSHR misses 1071system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 125 # number of overall MSHR misses 1072system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 1073system.cpu.l2cache.overall_mshr_misses::cpu.inst 22923 # number of overall MSHR misses 1074system.cpu.l2cache.overall_mshr_misses::cpu.data 145093 # number of overall MSHR misses 1075system.cpu.l2cache.overall_mshr_misses::total 168143 # number of overall MSHR misses 1076system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3758 # number of ReadReq MSHR uncacheable 1077system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable 1078system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34888 # number of ReadReq MSHR uncacheable 1079system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable 1080system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable 1081system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3758 # number of overall MSHR uncacheable misses 1082system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 1083system.cpu.l2cache.overall_mshr_uncacheable_misses::total 62472 # number of overall MSHR uncacheable misses 1084system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 16318500 # number of ReadReq MSHR miss cycles 1085system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 245500 # number of ReadReq MSHR miss cycles 1086system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16564000 # number of ReadReq MSHR miss cycles 1087system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 186014500 # number of UpgradeReq MSHR miss cycles 1088system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 186014500 # number of UpgradeReq MSHR miss cycles 1089system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 142000 # number of SCUpgradeReq MSHR miss cycles 1090system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 142000 # number of SCUpgradeReq MSHR miss cycles 1091system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15543669500 # number of ReadExReq MSHR miss cycles 1092system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15543669500 # number of ReadExReq MSHR miss cycles 1093system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2767321000 # number of ReadCleanReq MSHR miss cycles 1094system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2767321000 # number of ReadCleanReq MSHR miss cycles 1095system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1745198500 # number of ReadSharedReq MSHR miss cycles 1096system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1745198500 # number of ReadSharedReq MSHR miss cycles 1097system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 16318500 # number of demand (read+write) MSHR miss cycles 1098system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 245500 # number of demand (read+write) MSHR miss cycles 1099system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2767321000 # number of demand (read+write) MSHR miss cycles 1100system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17288868000 # number of demand (read+write) MSHR miss cycles 1101system.cpu.l2cache.demand_mshr_miss_latency::total 20072753000 # number of demand (read+write) MSHR miss cycles 1102system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 16318500 # number of overall MSHR miss cycles 1103system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 245500 # number of overall MSHR miss cycles 1104system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2767321000 # number of overall MSHR miss cycles 1105system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17288868000 # number of overall MSHR miss cycles 1106system.cpu.l2cache.overall_mshr_miss_latency::total 20072753000 # number of overall MSHR miss cycles 1107system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 426993000 # number of ReadReq MSHR uncacheable cycles 1108system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5909675000 # number of ReadReq MSHR uncacheable cycles 1109system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6336668000 # number of ReadReq MSHR uncacheable cycles 1110system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 426993000 # number of overall MSHR uncacheable cycles 1111system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5909675000 # number of overall MSHR uncacheable cycles 1112system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6336668000 # number of overall MSHR uncacheable cycles 1113system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001691 # mshr miss rate for ReadReq accesses 1114system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000411 # mshr miss rate for ReadReq accesses 1115system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001612 # mshr miss rate for ReadReq accesses 1116system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982399 # mshr miss rate for UpgradeReq accesses 1117system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982399 # mshr miss rate for UpgradeReq accesses | 1065system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 129240 # number of ReadExReq MSHR misses 1066system.cpu.l2cache.ReadExReq_mshr_misses::total 129240 # number of ReadExReq MSHR misses 1067system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22927 # number of ReadCleanReq MSHR misses 1068system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22927 # number of ReadCleanReq MSHR misses 1069system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14518 # number of ReadSharedReq MSHR misses 1070system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14518 # number of ReadSharedReq MSHR misses 1071system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 120 # number of demand (read+write) MSHR misses 1072system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses 1073system.cpu.l2cache.demand_mshr_misses::cpu.inst 22927 # number of demand (read+write) MSHR misses 1074system.cpu.l2cache.demand_mshr_misses::cpu.data 143758 # number of demand (read+write) MSHR misses 1075system.cpu.l2cache.demand_mshr_misses::total 166806 # number of demand (read+write) MSHR misses 1076system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 120 # number of overall MSHR misses 1077system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses 1078system.cpu.l2cache.overall_mshr_misses::cpu.inst 22927 # number of overall MSHR misses 1079system.cpu.l2cache.overall_mshr_misses::cpu.data 143758 # number of overall MSHR misses 1080system.cpu.l2cache.overall_mshr_misses::total 166806 # number of overall MSHR misses 1081system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3267 # number of ReadReq MSHR uncacheable 1082system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable 1083system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34395 # number of ReadReq MSHR uncacheable 1084system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable 1085system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable 1086system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3267 # number of overall MSHR uncacheable misses 1087system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses 1088system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61978 # number of overall MSHR uncacheable misses 1089system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 9089000 # number of ReadReq MSHR miss cycles 1090system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 73500 # number of ReadReq MSHR miss cycles 1091system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9162500 # number of ReadReq MSHR miss cycles 1092system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 95500 # number of UpgradeReq MSHR miss cycles 1093system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 95500 # number of UpgradeReq MSHR miss cycles 1094system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 144000 # number of SCUpgradeReq MSHR miss cycles 1095system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 144000 # number of SCUpgradeReq MSHR miss cycles 1096system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8947364000 # number of ReadExReq MSHR miss cycles 1097system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8947364000 # number of ReadExReq MSHR miss cycles 1098system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1624414500 # number of ReadCleanReq MSHR miss cycles 1099system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1624414500 # number of ReadCleanReq MSHR miss cycles 1100system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1078119000 # number of ReadSharedReq MSHR miss cycles 1101system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1078119000 # number of ReadSharedReq MSHR miss cycles 1102system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 9089000 # number of demand (read+write) MSHR miss cycles 1103system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 73500 # number of demand (read+write) MSHR miss cycles 1104system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1624414500 # number of demand (read+write) MSHR miss cycles 1105system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10025483000 # number of demand (read+write) MSHR miss cycles 1106system.cpu.l2cache.demand_mshr_miss_latency::total 11659060000 # number of demand (read+write) MSHR miss cycles 1107system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 9089000 # number of overall MSHR miss cycles 1108system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 73500 # number of overall MSHR miss cycles 1109system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1624414500 # number of overall MSHR miss cycles 1110system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10025483000 # number of overall MSHR miss cycles 1111system.cpu.l2cache.overall_mshr_miss_latency::total 11659060000 # number of overall MSHR miss cycles 1112system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 207499500 # number of ReadReq MSHR uncacheable cycles 1113system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5912622000 # number of ReadReq MSHR uncacheable cycles 1114system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6120121500 # number of ReadReq MSHR uncacheable cycles 1115system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 207499500 # number of overall MSHR uncacheable cycles 1116system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5912622000 # number of overall MSHR uncacheable cycles 1117system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6120121500 # number of overall MSHR uncacheable cycles 1118system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001767 # mshr miss rate for ReadReq accesses 1119system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000302 # mshr miss rate for ReadReq accesses 1120system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001699 # mshr miss rate for ReadReq accesses 1121system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.001780 # mshr miss rate for UpgradeReq accesses 1122system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.001780 # mshr miss rate for UpgradeReq accesses |
| 1118system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1119system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses | 1123system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1124system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses |
| 1120system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.441586 # mshr miss rate for ReadExReq accesses 1121system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.441586 # mshr miss rate for ReadExReq accesses 1122system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007919 # mshr miss rate for ReadCleanReq accesses 1123system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007919 # mshr miss rate for ReadCleanReq accesses 1124system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026052 # mshr miss rate for ReadSharedReq accesses 1125system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026052 # mshr miss rate for ReadSharedReq accesses 1126system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001691 # mshr miss rate for demand accesses 1127system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000411 # mshr miss rate for demand accesses 1128system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007919 # mshr miss rate for demand accesses 1129system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.171748 # mshr miss rate for demand accesses 1130system.cpu.l2cache.demand_mshr_miss_rate::total 0.044036 # mshr miss rate for demand accesses 1131system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001691 # mshr miss rate for overall accesses 1132system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000411 # mshr miss rate for overall accesses 1133system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007919 # mshr miss rate for overall accesses 1134system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.171748 # mshr miss rate for overall accesses 1135system.cpu.l2cache.overall_mshr_miss_rate::total 0.044036 # mshr miss rate for overall accesses 1136system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 130548 # average ReadReq mshr miss latency 1137system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122750 # average ReadReq mshr miss latency 1138system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 130425.196850 # average ReadReq mshr miss latency 1139system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68012.614260 # average UpgradeReq mshr miss latency 1140system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68012.614260 # average UpgradeReq mshr miss latency 1141system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71000 # average SCUpgradeReq mshr miss latency 1142system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71000 # average SCUpgradeReq mshr miss latency 1143system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118834.485210 # average ReadExReq mshr miss latency 1144system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118834.485210 # average ReadExReq mshr miss latency 1145system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120722.462156 # average ReadCleanReq mshr miss latency 1146system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120722.462156 # average ReadCleanReq mshr miss latency 1147system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122110.166527 # average ReadSharedReq mshr miss latency 1148system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122110.166527 # average ReadSharedReq mshr miss latency 1149system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 130548 # average overall mshr miss latency 1150system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122750 # average overall mshr miss latency 1151system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120722.462156 # average overall mshr miss latency 1152system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119157.147485 # average overall mshr miss latency 1153system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119379.058302 # average overall mshr miss latency 1154system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 130548 # average overall mshr miss latency 1155system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122750 # average overall mshr miss latency 1156system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120722.462156 # average overall mshr miss latency 1157system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119157.147485 # average overall mshr miss latency 1158system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119379.058302 # average overall mshr miss latency 1159system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113622.405535 # average ReadReq mshr uncacheable latency 1160system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189838.580148 # average ReadReq mshr uncacheable latency 1161system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181628.869525 # average ReadReq mshr uncacheable latency 1162system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113622.405535 # average overall mshr uncacheable latency 1163system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100651.888817 # average overall mshr uncacheable latency 1164system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 101432.129594 # average overall mshr uncacheable latency 1165system.cpu.toL2Bus.snoop_filter.tot_requests 7509695 # Total number of requests made to the snoop filter. 1166system.cpu.toL2Bus.snoop_filter.hit_single_requests 3770160 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1167system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58111 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1168system.cpu.toL2Bus.snoop_filter.tot_snoops 594 # Total number of snoops made to the snoop filter. 1169system.cpu.toL2Bus.snoop_filter.hit_single_snoops 594 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 1125system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437328 # mshr miss rate for ReadExReq accesses 1126system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437328 # mshr miss rate for ReadExReq accesses 1127system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007934 # mshr miss rate for ReadCleanReq accesses 1128system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007934 # mshr miss rate for ReadCleanReq accesses 1129system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026388 # mshr miss rate for ReadSharedReq accesses 1130system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026388 # mshr miss rate for ReadSharedReq accesses 1131system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001767 # mshr miss rate for demand accesses 1132system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000302 # mshr miss rate for demand accesses 1133system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007934 # mshr miss rate for demand accesses 1134system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.169986 # mshr miss rate for demand accesses 1135system.cpu.l2cache.demand_mshr_miss_rate::total 0.043821 # mshr miss rate for demand accesses 1136system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001767 # mshr miss rate for overall accesses 1137system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000302 # mshr miss rate for overall accesses 1138system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007934 # mshr miss rate for overall accesses 1139system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.169986 # mshr miss rate for overall accesses 1140system.cpu.l2cache.overall_mshr_miss_rate::total 0.043821 # mshr miss rate for overall accesses 1141system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75741.666667 # average ReadReq mshr miss latency 1142system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73500 # average ReadReq mshr miss latency 1143system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75723.140496 # average ReadReq mshr miss latency 1144system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19100 # average UpgradeReq mshr miss latency 1145system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19100 # average UpgradeReq mshr miss latency 1146system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72000 # average SCUpgradeReq mshr miss latency 1147system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency 1148system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69230.609718 # average ReadExReq mshr miss latency 1149system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69230.609718 # average ReadExReq mshr miss latency 1150system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70851.594190 # average ReadCleanReq mshr miss latency 1151system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70851.594190 # average ReadCleanReq mshr miss latency 1152system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74260.848602 # average ReadSharedReq mshr miss latency 1153system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74260.848602 # average ReadSharedReq mshr miss latency 1154system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75741.666667 # average overall mshr miss latency 1155system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73500 # average overall mshr miss latency 1156system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70851.594190 # average overall mshr miss latency 1157system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69738.609330 # average overall mshr miss latency 1158system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69895.927005 # average overall mshr miss latency 1159system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75741.666667 # average overall mshr miss latency 1160system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73500 # average overall mshr miss latency 1161system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70851.594190 # average overall mshr miss latency 1162system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69738.609330 # average overall mshr miss latency 1163system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69895.927005 # average overall mshr miss latency 1164system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63513.774105 # average ReadReq mshr uncacheable latency 1165system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189945.451041 # average ReadReq mshr uncacheable latency 1166system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 177936.371566 # average ReadReq mshr uncacheable latency 1167system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63513.774105 # average overall mshr uncacheable latency 1168system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100707.226925 # average overall mshr uncacheable latency 1169system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98746.676240 # average overall mshr uncacheable latency 1170system.cpu.toL2Bus.snoop_filter.tot_requests 7504035 # Total number of requests made to the snoop filter. 1171system.cpu.toL2Bus.snoop_filter.hit_single_requests 3768706 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1172system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58030 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1173system.cpu.toL2Bus.snoop_filter.tot_snoops 170 # Total number of snoops made to the snoop filter. 1174system.cpu.toL2Bus.snoop_filter.hit_single_snoops 170 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 1170system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1175system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1171system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1172system.cpu.toL2Bus.trans_dist::ReadReq 136822 # Transaction distribution 1173system.cpu.toL2Bus.trans_dist::ReadResp 3580395 # Transaction distribution 1174system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution 1175system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution 1176system.cpu.toL2Bus.trans_dist::WritebackDirty 825389 # Transaction distribution 1177system.cpu.toL2Bus.trans_dist::WritebackClean 2894242 # Transaction distribution 1178system.cpu.toL2Bus.trans_dist::CleanEvict 151717 # Transaction distribution 1179system.cpu.toL2Bus.trans_dist::UpgradeReq 2784 # Transaction distribution | 1176system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1177system.cpu.toL2Bus.trans_dist::ReadReq 137182 # Transaction distribution 1178system.cpu.toL2Bus.trans_dist::ReadResp 3577165 # Transaction distribution 1179system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution 1180system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution 1181system.cpu.toL2Bus.trans_dist::WritebackDirty 788847 # Transaction distribution 1182system.cpu.toL2Bus.trans_dist::WritebackClean 2889133 # Transaction distribution 1183system.cpu.toL2Bus.trans_dist::CleanEvict 153180 # Transaction distribution 1184system.cpu.toL2Bus.trans_dist::UpgradeReq 2809 # Transaction distribution |
| 1180system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution | 1185system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution |
| 1181system.cpu.toL2Bus.trans_dist::UpgradeResp 2786 # Transaction distribution 1182system.cpu.toL2Bus.trans_dist::ReadExReq 296207 # Transaction distribution 1183system.cpu.toL2Bus.trans_dist::ReadExResp 296207 # Transaction distribution 1184system.cpu.toL2Bus.trans_dist::ReadCleanReq 2894766 # Transaction distribution 1185system.cpu.toL2Bus.trans_dist::ReadSharedReq 548829 # Transaction distribution 1186system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 1187system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8691264 # Packet count per connected master and slave (bytes) 1188system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2657074 # Packet count per connected master and slave (bytes) 1189system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16340 # Packet count per connected master and slave (bytes) 1190system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 164402 # Packet count per connected master and slave (bytes) 1191system.cpu.toL2Bus.pkt_count::total 11529080 # Packet count per connected master and slave (bytes) 1192system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370735360 # Cumulative packet size per connected master and slave (bytes) 1193system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99133929 # Cumulative packet size per connected master and slave (bytes) 1194system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 19484 # Cumulative packet size per connected master and slave (bytes) 1195system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 295748 # Cumulative packet size per connected master and slave (bytes) 1196system.cpu.toL2Bus.pkt_size::total 470184521 # Cumulative packet size per connected master and slave (bytes) 1197system.cpu.toL2Bus.snoops 192671 # Total snoops (count) 1198system.cpu.toL2Bus.snoopTraffic 8062744 # Total snoop traffic (bytes) 1199system.cpu.toL2Bus.snoop_fanout::samples 4076067 # Request fanout histogram 1200system.cpu.toL2Bus.snoop_fanout::mean 0.021486 # Request fanout histogram 1201system.cpu.toL2Bus.snoop_fanout::stdev 0.144999 # Request fanout histogram | 1186system.cpu.toL2Bus.trans_dist::UpgradeResp 2811 # Transaction distribution 1187system.cpu.toL2Bus.trans_dist::ReadExReq 295522 # Transaction distribution 1188system.cpu.toL2Bus.trans_dist::ReadExResp 295522 # Transaction distribution 1189system.cpu.toL2Bus.trans_dist::ReadCleanReq 2889657 # Transaction distribution 1190system.cpu.toL2Bus.trans_dist::ReadSharedReq 550405 # Transaction distribution 1191system.cpu.toL2Bus.trans_dist::InvalidateReq 4412 # Transaction distribution 1192system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8674948 # Packet count per connected master and slave (bytes) 1193system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2659767 # Packet count per connected master and slave (bytes) 1194system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14702 # Packet count per connected master and slave (bytes) 1195system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159313 # Packet count per connected master and slave (bytes) 1196system.cpu.toL2Bus.pkt_count::total 11508730 # Packet count per connected master and slave (bytes) 1197system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370049536 # Cumulative packet size per connected master and slave (bytes) 1198system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99142941 # Cumulative packet size per connected master and slave (bytes) 1199system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13260 # Cumulative packet size per connected master and slave (bytes) 1200system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 271652 # Cumulative packet size per connected master and slave (bytes) 1201system.cpu.toL2Bus.pkt_size::total 469477389 # Cumulative packet size per connected master and slave (bytes) 1202system.cpu.toL2Bus.snoops 133226 # Total snoops (count) 1203system.cpu.toL2Bus.snoopTraffic 5798108 # Total snoop traffic (bytes) 1204system.cpu.toL2Bus.snoop_fanout::samples 4004431 # Request fanout histogram 1205system.cpu.toL2Bus.snoop_fanout::mean 0.022424 # Request fanout histogram 1206system.cpu.toL2Bus.snoop_fanout::stdev 0.148057 # Request fanout histogram |
| 1202system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1207system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1203system.cpu.toL2Bus.snoop_fanout::0 3988487 97.85% 97.85% # Request fanout histogram 1204system.cpu.toL2Bus.snoop_fanout::1 87580 2.15% 100.00% # Request fanout histogram | 1208system.cpu.toL2Bus.snoop_fanout::0 3914637 97.76% 97.76% # Request fanout histogram 1209system.cpu.toL2Bus.snoop_fanout::1 89794 2.24% 100.00% # Request fanout histogram |
| 1205system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1206system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1207system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1208system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 1210system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1211system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1212system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1213system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1209system.cpu.toL2Bus.snoop_fanout::total 4076067 # Request fanout histogram 1210system.cpu.toL2Bus.reqLayer0.occupancy 7431755500 # Layer occupancy (ticks) | 1214system.cpu.toL2Bus.snoop_fanout::total 4004431 # Request fanout histogram 1215system.cpu.toL2Bus.reqLayer0.occupancy 7421943500 # Layer occupancy (ticks) |
| 1211system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) | 1216system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) |
| 1212system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) | 1217system.cpu.toL2Bus.snoopLayer0.occupancy 275377 # Layer occupancy (ticks) |
| 1213system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1218system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1214system.cpu.toL2Bus.respLayer0.occupancy 4348377811 # Layer occupancy (ticks) | 1219system.cpu.toL2Bus.respLayer0.occupancy 4339894977 # Layer occupancy (ticks) |
| 1215system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) | 1220system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) |
| 1216system.cpu.toL2Bus.respLayer1.occupancy 1313662211 # Layer occupancy (ticks) | 1221system.cpu.toL2Bus.respLayer1.occupancy 1315039189 # Layer occupancy (ticks) |
| 1217system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1222system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1218system.cpu.toL2Bus.respLayer2.occupancy 11470497 # Layer occupancy (ticks) | 1223system.cpu.toL2Bus.respLayer2.occupancy 11390493 # Layer occupancy (ticks) |
| 1219system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1224system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1220system.cpu.toL2Bus.respLayer3.occupancy 90488952 # Layer occupancy (ticks) | 1225system.cpu.toL2Bus.respLayer3.occupancy 91431936 # Layer occupancy (ticks) |
| 1221system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1226system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1222system.iobus.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states | 1227system.iobus.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states |
| 1223system.iobus.trans_dist::ReadReq 30183 # Transaction distribution 1224system.iobus.trans_dist::ReadResp 30183 # Transaction distribution 1225system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1226system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1227system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1228system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1229system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1230system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 34 unchanged lines hidden (view full) --- 1265system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1266system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1267system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1268system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1269system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) 1270system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 1271system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 1272system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) | 1228system.iobus.trans_dist::ReadReq 30183 # Transaction distribution 1229system.iobus.trans_dist::ReadResp 30183 # Transaction distribution 1230system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1231system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1232system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1233system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1234system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1235system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 34 unchanged lines hidden (view full) --- 1270system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1271system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1272system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1273system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1274system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) 1275system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 1276system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 1277system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) |
| 1273system.iobus.reqLayer0.occupancy 46348000 # Layer occupancy (ticks) | 1278system.iobus.reqLayer0.occupancy 46364500 # Layer occupancy (ticks) |
| 1274system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1275system.iobus.reqLayer1.occupancy 107000 # Layer occupancy (ticks) 1276system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1279system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1280system.iobus.reqLayer1.occupancy 107000 # Layer occupancy (ticks) 1281system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1277system.iobus.reqLayer2.occupancy 330500 # Layer occupancy (ticks) | 1282system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) |
| 1278system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1283system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1279system.iobus.reqLayer3.occupancy 30500 # Layer occupancy (ticks) | 1284system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks) |
| 1280system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) | 1285system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) |
| 1281system.iobus.reqLayer4.occupancy 15000 # Layer occupancy (ticks) | 1286system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) |
| 1282system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) | 1287system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 1283system.iobus.reqLayer7.occupancy 85500 # Layer occupancy (ticks) | 1288system.iobus.reqLayer7.occupancy 88000 # Layer occupancy (ticks) |
| 1284system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) | 1289system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) |
| 1285system.iobus.reqLayer8.occupancy 623500 # Layer occupancy (ticks) | 1290system.iobus.reqLayer8.occupancy 618000 # Layer occupancy (ticks) |
| 1286system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1287system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks) 1288system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) | 1291system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1292system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks) 1293system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) |
| 1289system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) | 1294system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) |
| 1290system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1291system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) 1292system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1293system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) 1294system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) | 1295system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1296system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) 1297system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1298system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) 1299system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) |
| 1295system.iobus.reqLayer16.occupancy 51000 # Layer occupancy (ticks) | 1300system.iobus.reqLayer16.occupancy 50000 # Layer occupancy (ticks) |
| 1296system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1297system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 1298system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) | 1301system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1302system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 1303system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) |
| 1299system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) | 1304system.iobus.reqLayer18.occupancy 10500 # Layer occupancy (ticks) |
| 1300system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1301system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 1302system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) | 1305system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1306system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 1307system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) |
| 1303system.iobus.reqLayer20.occupancy 10500 # Layer occupancy (ticks) | 1308system.iobus.reqLayer20.occupancy 10000 # Layer occupancy (ticks) |
| 1304system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1305system.iobus.reqLayer21.occupancy 10000 # Layer occupancy (ticks) 1306system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) | 1309system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1310system.iobus.reqLayer21.occupancy 10000 # Layer occupancy (ticks) 1311system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) |
| 1307system.iobus.reqLayer23.occupancy 6076000 # Layer occupancy (ticks) | 1312system.iobus.reqLayer23.occupancy 6096500 # Layer occupancy (ticks) |
| 1308system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 1313system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| 1309system.iobus.reqLayer24.occupancy 38906500 # Layer occupancy (ticks) | 1314system.iobus.reqLayer24.occupancy 39117500 # Layer occupancy (ticks) |
| 1310system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 1315system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 1311system.iobus.reqLayer25.occupancy 187130005 # Layer occupancy (ticks) | 1316system.iobus.reqLayer25.occupancy 187733842 # Layer occupancy (ticks) |
| 1312system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1313system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1314system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1315system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) 1316system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 1317system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1318system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1319system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1320system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) 1321system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1317system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states | 1322system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states |
| 1318system.iocache.tags.replacements 36424 # number of replacements | 1323system.iocache.tags.replacements 36424 # number of replacements |
| 1319system.iocache.tags.tagsinuse 1.038429 # Cycle average of tags in use | 1324system.iocache.tags.tagsinuse 1.032370 # Cycle average of tags in use |
| 1320system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1321system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1322system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1325system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1326system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1327system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1323system.iocache.tags.warmup_cycle 275018797000 # Cycle when the warmup percentage was hit. 1324system.iocache.tags.occ_blocks::realview.ide 1.038429 # Average occupied blocks per requestor 1325system.iocache.tags.occ_percent::realview.ide 0.064902 # Average percentage of cache occupancy 1326system.iocache.tags.occ_percent::total 0.064902 # Average percentage of cache occupancy | 1328system.iocache.tags.warmup_cycle 270830421000 # Cycle when the warmup percentage was hit. 1329system.iocache.tags.occ_blocks::realview.ide 1.032370 # Average occupied blocks per requestor 1330system.iocache.tags.occ_percent::realview.ide 0.064523 # Average percentage of cache occupancy 1331system.iocache.tags.occ_percent::total 0.064523 # Average percentage of cache occupancy |
| 1327system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1328system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1329system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1330system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1331system.iocache.tags.data_accesses 328122 # Number of data accesses | 1332system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1333system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1334system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1335system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1336system.iocache.tags.data_accesses 328122 # Number of data accesses |
| 1332system.iocache.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states | 1337system.iocache.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states |
| 1333system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1334system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1335system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1336system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1337system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses 1338system.iocache.demand_misses::total 36458 # number of demand (read+write) misses 1339system.iocache.overall_misses::realview.ide 36458 # number of overall misses 1340system.iocache.overall_misses::total 36458 # number of overall misses | 1338system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1339system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1340system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1341system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1342system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses 1343system.iocache.demand_misses::total 36458 # number of demand (read+write) misses 1344system.iocache.overall_misses::realview.ide 36458 # number of overall misses 1345system.iocache.overall_misses::total 36458 # number of overall misses |
| 1341system.iocache.ReadReq_miss_latency::realview.ide 29054877 # number of ReadReq miss cycles 1342system.iocache.ReadReq_miss_latency::total 29054877 # number of ReadReq miss cycles 1343system.iocache.WriteLineReq_miss_latency::realview.ide 4548884128 # number of WriteLineReq miss cycles 1344system.iocache.WriteLineReq_miss_latency::total 4548884128 # number of WriteLineReq miss cycles 1345system.iocache.demand_miss_latency::realview.ide 4577939005 # number of demand (read+write) miss cycles 1346system.iocache.demand_miss_latency::total 4577939005 # number of demand (read+write) miss cycles 1347system.iocache.overall_miss_latency::realview.ide 4577939005 # number of overall miss cycles 1348system.iocache.overall_miss_latency::total 4577939005 # number of overall miss cycles | 1346system.iocache.ReadReq_miss_latency::realview.ide 29494377 # number of ReadReq miss cycles 1347system.iocache.ReadReq_miss_latency::total 29494377 # number of ReadReq miss cycles 1348system.iocache.WriteLineReq_miss_latency::realview.ide 4278402465 # number of WriteLineReq miss cycles 1349system.iocache.WriteLineReq_miss_latency::total 4278402465 # number of WriteLineReq miss cycles 1350system.iocache.demand_miss_latency::realview.ide 4307896842 # number of demand (read+write) miss cycles 1351system.iocache.demand_miss_latency::total 4307896842 # number of demand (read+write) miss cycles 1352system.iocache.overall_miss_latency::realview.ide 4307896842 # number of overall miss cycles 1353system.iocache.overall_miss_latency::total 4307896842 # number of overall miss cycles |
| 1349system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1350system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1351system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1352system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1353system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses 1354system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses 1355system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses 1356system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses 1357system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1358system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1359system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1360system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1361system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1362system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1363system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1364system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1354system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1355system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1356system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1357system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1358system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses 1359system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses 1360system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses 1361system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses 1362system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1363system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1364system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1365system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1366system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1367system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1368system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1369system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1365system.iocache.ReadReq_avg_miss_latency::realview.ide 124166.141026 # average ReadReq miss latency 1366system.iocache.ReadReq_avg_miss_latency::total 124166.141026 # average ReadReq miss latency 1367system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125576.527385 # average WriteLineReq miss latency 1368system.iocache.WriteLineReq_avg_miss_latency::total 125576.527385 # average WriteLineReq miss latency 1369system.iocache.demand_avg_miss_latency::realview.ide 125567.475040 # average overall miss latency 1370system.iocache.demand_avg_miss_latency::total 125567.475040 # average overall miss latency 1371system.iocache.overall_avg_miss_latency::realview.ide 125567.475040 # average overall miss latency 1372system.iocache.overall_avg_miss_latency::total 125567.475040 # average overall miss latency | 1370system.iocache.ReadReq_avg_miss_latency::realview.ide 126044.346154 # average ReadReq miss latency 1371system.iocache.ReadReq_avg_miss_latency::total 126044.346154 # average ReadReq miss latency 1372system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118109.608685 # average WriteLineReq miss latency 1373system.iocache.WriteLineReq_avg_miss_latency::total 118109.608685 # average WriteLineReq miss latency 1374system.iocache.demand_avg_miss_latency::realview.ide 118160.536563 # average overall miss latency 1375system.iocache.demand_avg_miss_latency::total 118160.536563 # average overall miss latency 1376system.iocache.overall_avg_miss_latency::realview.ide 118160.536563 # average overall miss latency 1377system.iocache.overall_avg_miss_latency::total 118160.536563 # average overall miss latency |
| 1373system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1374system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1375system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1376system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1377system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1378system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1379system.iocache.writebacks::writebacks 36190 # number of writebacks 1380system.iocache.writebacks::total 36190 # number of writebacks 1381system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1382system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1383system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1384system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 1385system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses 1386system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses 1387system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses 1388system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses | 1378system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1379system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1380system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1381system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1382system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1383system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1384system.iocache.writebacks::writebacks 36190 # number of writebacks 1385system.iocache.writebacks::total 36190 # number of writebacks 1386system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1387system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1388system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1389system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 1390system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses 1391system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses 1392system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses 1393system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses |
| 1389system.iocache.ReadReq_mshr_miss_latency::realview.ide 17354877 # number of ReadReq MSHR miss cycles 1390system.iocache.ReadReq_mshr_miss_latency::total 17354877 # number of ReadReq MSHR miss cycles 1391system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736261614 # number of WriteLineReq MSHR miss cycles 1392system.iocache.WriteLineReq_mshr_miss_latency::total 2736261614 # number of WriteLineReq MSHR miss cycles 1393system.iocache.demand_mshr_miss_latency::realview.ide 2753616491 # number of demand (read+write) MSHR miss cycles 1394system.iocache.demand_mshr_miss_latency::total 2753616491 # number of demand (read+write) MSHR miss cycles 1395system.iocache.overall_mshr_miss_latency::realview.ide 2753616491 # number of overall MSHR miss cycles 1396system.iocache.overall_mshr_miss_latency::total 2753616491 # number of overall MSHR miss cycles | 1394system.iocache.ReadReq_mshr_miss_latency::realview.ide 17794377 # number of ReadReq MSHR miss cycles 1395system.iocache.ReadReq_mshr_miss_latency::total 17794377 # number of ReadReq MSHR miss cycles 1396system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2465093924 # number of WriteLineReq MSHR miss cycles 1397system.iocache.WriteLineReq_mshr_miss_latency::total 2465093924 # number of WriteLineReq MSHR miss cycles 1398system.iocache.demand_mshr_miss_latency::realview.ide 2482888301 # number of demand (read+write) MSHR miss cycles 1399system.iocache.demand_mshr_miss_latency::total 2482888301 # number of demand (read+write) MSHR miss cycles 1400system.iocache.overall_mshr_miss_latency::realview.ide 2482888301 # number of overall MSHR miss cycles 1401system.iocache.overall_mshr_miss_latency::total 2482888301 # number of overall MSHR miss cycles |
| 1397system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1398system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1399system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1400system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1401system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1402system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1403system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1404system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1402system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1403system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1404system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1405system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1406system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1407system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1408system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1409system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1405system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74166.141026 # average ReadReq mshr miss latency 1406system.iocache.ReadReq_avg_mshr_miss_latency::total 74166.141026 # average ReadReq mshr miss latency 1407system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75537.257454 # average WriteLineReq mshr miss latency 1408system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75537.257454 # average WriteLineReq mshr miss latency 1409system.iocache.demand_avg_mshr_miss_latency::realview.ide 75528.457156 # average overall mshr miss latency 1410system.iocache.demand_avg_mshr_miss_latency::total 75528.457156 # average overall mshr miss latency 1411system.iocache.overall_avg_mshr_miss_latency::realview.ide 75528.457156 # average overall mshr miss latency 1412system.iocache.overall_avg_mshr_miss_latency::total 75528.457156 # average overall mshr miss latency 1413system.membus.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1414system.membus.trans_dist::ReadReq 34888 # Transaction distribution 1415system.membus.trans_dist::ReadResp 72464 # Transaction distribution 1416system.membus.trans_dist::WriteReq 27584 # Transaction distribution 1417system.membus.trans_dist::WriteResp 27584 # Transaction distribution 1418system.membus.trans_dist::WritebackDirty 124285 # Transaction distribution 1419system.membus.trans_dist::CleanEvict 8552 # Transaction distribution 1420system.membus.trans_dist::UpgradeReq 4603 # Transaction distribution | 1410system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76044.346154 # average ReadReq mshr miss latency 1411system.iocache.ReadReq_avg_mshr_miss_latency::total 76044.346154 # average ReadReq mshr miss latency 1412system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68051.400287 # average WriteLineReq mshr miss latency 1413system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68051.400287 # average WriteLineReq mshr miss latency 1414system.iocache.demand_avg_mshr_miss_latency::realview.ide 68102.701766 # average overall mshr miss latency 1415system.iocache.demand_avg_mshr_miss_latency::total 68102.701766 # average overall mshr miss latency 1416system.iocache.overall_avg_mshr_miss_latency::realview.ide 68102.701766 # average overall mshr miss latency 1417system.iocache.overall_avg_mshr_miss_latency::total 68102.701766 # average overall mshr miss latency 1418system.membus.snoop_filter.tot_requests 336558 # Total number of requests made to the snoop filter. 1419system.membus.snoop_filter.hit_single_requests 137845 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1420system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1421system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1422system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1423system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1424system.membus.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1425system.membus.trans_dist::ReadReq 34395 # Transaction distribution 1426system.membus.trans_dist::ReadResp 72195 # Transaction distribution 1427system.membus.trans_dist::WriteReq 27583 # Transaction distribution 1428system.membus.trans_dist::WriteResp 27583 # Transaction distribution 1429system.membus.trans_dist::WritebackDirty 124638 # Transaction distribution 1430system.membus.trans_dist::CleanEvict 8645 # Transaction distribution 1431system.membus.trans_dist::UpgradeReq 128 # Transaction distribution |
| 1421system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1422system.membus.trans_dist::UpgradeResp 2 # Transaction distribution | 1432system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1433system.membus.trans_dist::UpgradeResp 2 # Transaction distribution |
| 1423system.membus.trans_dist::ReadExReq 128933 # Transaction distribution 1424system.membus.trans_dist::ReadExResp 128933 # Transaction distribution 1425system.membus.trans_dist::ReadSharedReq 37576 # Transaction distribution | 1434system.membus.trans_dist::ReadExReq 129117 # Transaction distribution 1435system.membus.trans_dist::ReadExResp 129117 # Transaction distribution 1436system.membus.trans_dist::ReadSharedReq 37800 # Transaction distribution |
| 1426system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1427system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1428system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) | 1437system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1438system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1439system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) |
| 1429system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes) 1430system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450661 # Packet count per connected master and slave (bytes) 1431system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558229 # Packet count per connected master and slave (bytes) | 1440system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) 1441system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446466 # Packet count per connected master and slave (bytes) 1442system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554028 # Packet count per connected master and slave (bytes) |
| 1432system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) 1433system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) | 1443system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) 1444system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) |
| 1434system.membus.pkt_count::total 631126 # Packet count per connected master and slave (bytes) | 1445system.membus.pkt_count::total 626925 # Packet count per connected master and slave (bytes) |
| 1435system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1436system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) | 1446system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1447system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) |
| 1437system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes) 1438system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16521376 # Cumulative packet size per connected master and slave (bytes) 1439system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16685161 # Cumulative packet size per connected master and slave (bytes) | 1448system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) 1449system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16538656 # Cumulative packet size per connected master and slave (bytes) 1450system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16702429 # Cumulative packet size per connected master and slave (bytes) |
| 1440system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1441system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) | 1451system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1452system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) |
| 1442system.membus.pkt_size::total 19002281 # Cumulative packet size per connected master and slave (bytes) | 1453system.membus.pkt_size::total 19019549 # Cumulative packet size per connected master and slave (bytes) |
| 1443system.membus.snoops 504 # Total snoops (count) 1444system.membus.snoopTraffic 32128 # Total snoop traffic (bytes) | 1454system.membus.snoops 504 # Total snoops (count) 1455system.membus.snoopTraffic 32128 # Total snoop traffic (bytes) |
| 1445system.membus.snoop_fanout::samples 402659 # Request fanout histogram 1446system.membus.snoop_fanout::mean 1 # Request fanout histogram 1447system.membus.snoop_fanout::stdev 0 # Request fanout histogram | 1456system.membus.snoop_fanout::samples 265249 # Request fanout histogram 1457system.membus.snoop_fanout::mean 0.018541 # Request fanout histogram 1458system.membus.snoop_fanout::stdev 0.134898 # Request fanout histogram |
| 1448system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1459system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1449system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1450system.membus.snoop_fanout::1 402659 100.00% 100.00% # Request fanout histogram | 1460system.membus.snoop_fanout::0 260331 98.15% 98.15% # Request fanout histogram 1461system.membus.snoop_fanout::1 4918 1.85% 100.00% # Request fanout histogram |
| 1451system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1452system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1462system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1463system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1453system.membus.snoop_fanout::min_value 1 # Request fanout histogram | 1464system.membus.snoop_fanout::min_value 0 # Request fanout histogram |
| 1454system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1465system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1455system.membus.snoop_fanout::total 402659 # Request fanout histogram 1456system.membus.reqLayer0.occupancy 92669500 # Layer occupancy (ticks) | 1466system.membus.snoop_fanout::total 265249 # Request fanout histogram 1467system.membus.reqLayer0.occupancy 92904500 # Layer occupancy (ticks) |
| 1457system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1458system.membus.reqLayer1.occupancy 8000 # Layer occupancy (ticks) 1459system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1468system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1469system.membus.reqLayer1.occupancy 8000 # Layer occupancy (ticks) 1470system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1460system.membus.reqLayer2.occupancy 1708000 # Layer occupancy (ticks) | 1471system.membus.reqLayer2.occupancy 1693000 # Layer occupancy (ticks) |
| 1461system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1472system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1462system.membus.reqLayer5.occupancy 910164615 # Layer occupancy (ticks) | 1473system.membus.reqLayer5.occupancy 906764526 # Layer occupancy (ticks) |
| 1463system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 1474system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 1464system.membus.respLayer2.occupancy 990045000 # Layer occupancy (ticks) | 1475system.membus.respLayer2.occupancy 989491000 # Layer occupancy (ticks) |
| 1465system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1476system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1466system.membus.respLayer3.occupancy 1264123 # Layer occupancy (ticks) | 1477system.membus.respLayer3.occupancy 1228623 # Layer occupancy (ticks) |
| 1467system.membus.respLayer3.utilization 0.0 # Layer utilization (%) | 1478system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1468system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1469system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1470system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1471system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1472system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1473system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1474system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states | 1479system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1480system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1481system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1482system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1483system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1484system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1485system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states |
| 1475system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1476system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1477system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1478system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1479system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1480system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 1486system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1487system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1488system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1489system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1490system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1491system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 1481system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1482system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states | 1492system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1493system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states |
| 1483system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1484system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1485system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1486system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1487system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1488system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1489system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1490system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1506system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1507system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1508system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1509system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1510system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1511system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1512system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1513system.realview.ethernet.droppedPackets 0 # number of packets dropped | 1494system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1495system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1496system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1497system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1498system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1499system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1500system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1501system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1517system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1518system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1519system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1520system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1521system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1522system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1523system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1524system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 1514system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1515system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1516system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1517system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1518system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1519system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1520system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states | 1525system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1526system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1527system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1528system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1529system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1530system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1531system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states |
| 1521system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1522system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1523system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1524system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 1532system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1533system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1534system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1535system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 1525system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1526system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1527system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1528system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1529system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1530system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1531system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1532system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1533system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1534system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1535system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states 1536system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states | 1536system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1537system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1538system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1539system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1540system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1541system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1542system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1543system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1544system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1545system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1546system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states 1547system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states |
| 1537 1538---------- End Simulation Statistics ---------- | 1548 1549---------- End Simulation Statistics ---------- |