| stats.txt (11530:6e143fd2cabf) | stats.txt (11547:dd6dfd38b6c2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.858505 # Number of seconds simulated 4sim_ticks 2858505242500 # Number of ticks simulated 5final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.858505 # Number of seconds simulated 4sim_ticks 2858505242500 # Number of ticks simulated 5final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 258042 # Simulator instruction rate (inst/s) 8host_op_rate 311992 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6591883972 # Simulator tick rate (ticks/s) 10host_mem_usage 625700 # Number of bytes of host memory used 11host_seconds 433.64 # Real time elapsed on the host | 7host_inst_rate 152549 # Simulator instruction rate (inst/s) 8host_op_rate 184443 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3896990443 # Simulator tick rate (ticks/s) 10host_mem_usage 585436 # Number of bytes of host memory used 11host_seconds 733.52 # Real time elapsed on the host |
| 12sim_insts 111897168 # Number of instructions simulated 13sim_ops 135292215 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1705984 # Number of bytes read from this memory --- 393 unchanged lines hidden (view full) --- 413system.cpu.dtb.read_hits 24710833 # DTB read hits 414system.cpu.dtb.read_misses 59358 # DTB read misses 415system.cpu.dtb.write_hits 19424404 # DTB write hits 416system.cpu.dtb.write_misses 6793 # DTB write misses 417system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 418system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 419system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 420system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 12sim_insts 111897168 # Number of instructions simulated 13sim_ops 135292215 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1705984 # Number of bytes read from this memory --- 393 unchanged lines hidden (view full) --- 413system.cpu.dtb.read_hits 24710833 # DTB read hits 414system.cpu.dtb.read_misses 59358 # DTB read misses 415system.cpu.dtb.write_hits 19424404 # DTB write hits 416system.cpu.dtb.write_misses 6793 # DTB write misses 417system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 418system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 419system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 420system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 421system.cpu.dtb.flush_entries 4350 # Number of entries that have been flushed from TLB | 421system.cpu.dtb.flush_entries 4286 # Number of entries that have been flushed from TLB |
| 422system.cpu.dtb.align_faults 1526 # Number of TLB faults due to alignment restrictions 423system.cpu.dtb.prefetch_faults 1789 # Number of TLB faults due to prefetch 424system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 425system.cpu.dtb.perms_faults 754 # Number of TLB faults due to permissions restrictions 426system.cpu.dtb.read_accesses 24770191 # DTB read accesses 427system.cpu.dtb.write_accesses 19431197 # DTB write accesses 428system.cpu.dtb.inst_accesses 0 # ITB inst accesses 429system.cpu.dtb.hits 44135237 # DTB hits --- 63 unchanged lines hidden (view full) --- 493system.cpu.itb.read_hits 0 # DTB read hits 494system.cpu.itb.read_misses 0 # DTB read misses 495system.cpu.itb.write_hits 0 # DTB write hits 496system.cpu.itb.write_misses 0 # DTB write misses 497system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 498system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 499system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 500system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 422system.cpu.dtb.align_faults 1526 # Number of TLB faults due to alignment restrictions 423system.cpu.dtb.prefetch_faults 1789 # Number of TLB faults due to prefetch 424system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 425system.cpu.dtb.perms_faults 754 # Number of TLB faults due to permissions restrictions 426system.cpu.dtb.read_accesses 24770191 # DTB read accesses 427system.cpu.dtb.write_accesses 19431197 # DTB write accesses 428system.cpu.dtb.inst_accesses 0 # ITB inst accesses 429system.cpu.dtb.hits 44135237 # DTB hits --- 63 unchanged lines hidden (view full) --- 493system.cpu.itb.read_hits 0 # DTB read hits 494system.cpu.itb.read_misses 0 # DTB read misses 495system.cpu.itb.write_hits 0 # DTB write hits 496system.cpu.itb.write_misses 0 # DTB write misses 497system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 498system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 499system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 500system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 501system.cpu.itb.flush_entries 2992 # Number of entries that have been flushed from TLB | 501system.cpu.itb.flush_entries 2928 # Number of entries that have been flushed from TLB |
| 502system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 503system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 504system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 505system.cpu.itb.perms_faults 8365 # Number of TLB faults due to permissions restrictions 506system.cpu.itb.read_accesses 0 # DTB read accesses 507system.cpu.itb.write_accesses 0 # DTB write accesses 508system.cpu.itb.inst_accesses 57339683 # ITB inst accesses 509system.cpu.itb.hits 57333922 # DTB hits --- 1027 unchanged lines hidden --- | 502system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 503system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 504system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 505system.cpu.itb.perms_faults 8365 # Number of TLB faults due to permissions restrictions 506system.cpu.itb.read_accesses 0 # DTB read accesses 507system.cpu.itb.write_accesses 0 # DTB write accesses 508system.cpu.itb.inst_accesses 57339683 # ITB inst accesses 509system.cpu.itb.hits 57333922 # DTB hits --- 1027 unchanged lines hidden --- |