| stats.txt (11502:e273e86a873d) | stats.txt (11507:be6065c1d8d2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.858505 # Number of seconds simulated 4sim_ticks 2858505242500 # Number of ticks simulated 5final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.858505 # Number of seconds simulated 4sim_ticks 2858505242500 # Number of ticks simulated 5final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 171882 # Simulator instruction rate (inst/s) 8host_op_rate 207819 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4390877747 # Simulator tick rate (ticks/s) 10host_mem_usage 578076 # Number of bytes of host memory used 11host_seconds 651.01 # Real time elapsed on the host | 7host_inst_rate 125507 # Simulator instruction rate (inst/s) 8host_op_rate 151748 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3206183180 # Simulator tick rate (ticks/s) 10host_mem_usage 578080 # Number of bytes of host memory used 11host_seconds 891.56 # Real time elapsed on the host |
| 12sim_insts 111897168 # Number of instructions simulated 13sim_ops 135292215 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1705984 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9156972 # Number of bytes read from this memory --- 378 unchanged lines hidden (view full) --- 398system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 399system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66151 # Table walker requests started/completed, data/inst 400system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7866 # Table walker requests started/completed, data/inst 401system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 402system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7866 # Table walker requests started/completed, data/inst 403system.cpu.dtb.walker.walkRequestOrigin::total 74017 # Table walker requests started/completed, data/inst 404system.cpu.dtb.inst_hits 0 # ITB inst hits 405system.cpu.dtb.inst_misses 0 # ITB inst misses | 12sim_insts 111897168 # Number of instructions simulated 13sim_ops 135292215 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1705984 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9156972 # Number of bytes read from this memory --- 378 unchanged lines hidden (view full) --- 398system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 399system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66151 # Table walker requests started/completed, data/inst 400system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7866 # Table walker requests started/completed, data/inst 401system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 402system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7866 # Table walker requests started/completed, data/inst 403system.cpu.dtb.walker.walkRequestOrigin::total 74017 # Table walker requests started/completed, data/inst 404system.cpu.dtb.inst_hits 0 # ITB inst hits 405system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 406system.cpu.dtb.read_hits 24710832 # DTB read hits | 406system.cpu.dtb.read_hits 24710833 # DTB read hits |
| 407system.cpu.dtb.read_misses 59358 # DTB read misses | 407system.cpu.dtb.read_misses 59358 # DTB read misses |
| 408system.cpu.dtb.write_hits 19424403 # DTB write hits | 408system.cpu.dtb.write_hits 19424404 # DTB write hits |
| 409system.cpu.dtb.write_misses 6793 # DTB write misses 410system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 411system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 412system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 413system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 414system.cpu.dtb.flush_entries 4350 # Number of entries that have been flushed from TLB 415system.cpu.dtb.align_faults 1526 # Number of TLB faults due to alignment restrictions 416system.cpu.dtb.prefetch_faults 1789 # Number of TLB faults due to prefetch 417system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 418system.cpu.dtb.perms_faults 754 # Number of TLB faults due to permissions restrictions | 409system.cpu.dtb.write_misses 6793 # DTB write misses 410system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 411system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 412system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 413system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 414system.cpu.dtb.flush_entries 4350 # Number of entries that have been flushed from TLB 415system.cpu.dtb.align_faults 1526 # Number of TLB faults due to alignment restrictions 416system.cpu.dtb.prefetch_faults 1789 # Number of TLB faults due to prefetch 417system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 418system.cpu.dtb.perms_faults 754 # Number of TLB faults due to permissions restrictions |
| 419system.cpu.dtb.read_accesses 24770190 # DTB read accesses 420system.cpu.dtb.write_accesses 19431196 # DTB write accesses | 419system.cpu.dtb.read_accesses 24770191 # DTB read accesses 420system.cpu.dtb.write_accesses 19431197 # DTB write accesses |
| 421system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 421system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 422system.cpu.dtb.hits 44135235 # DTB hits | 422system.cpu.dtb.hits 44135237 # DTB hits |
| 423system.cpu.dtb.misses 66151 # DTB misses | 423system.cpu.dtb.misses 66151 # DTB misses |
| 424system.cpu.dtb.accesses 44201386 # DTB accesses | 424system.cpu.dtb.accesses 44201388 # DTB accesses |
| 425system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 426system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 427system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 428system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 429system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 430system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 431system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 432system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 113 unchanged lines hidden (view full) --- 546system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 547system.cpu.op_class_0::total 135292215 # Class of committed instruction 548system.cpu.kern.inst.arm 0 # number of arm instructions executed 549system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed 550system.cpu.tickCycles 228131430 # Number of cycles that the object actually ticked 551system.cpu.idleCycles 104690673 # Total number of cycles that the object has spent stopped 552system.cpu.dcache.tags.replacements 842468 # number of replacements 553system.cpu.dcache.tags.tagsinuse 511.899803 # Cycle average of tags in use | 425system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 426system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 427system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 428system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 429system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 430system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 431system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 432system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 113 unchanged lines hidden (view full) --- 546system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 547system.cpu.op_class_0::total 135292215 # Class of committed instruction 548system.cpu.kern.inst.arm 0 # number of arm instructions executed 549system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed 550system.cpu.tickCycles 228131430 # Number of cycles that the object actually ticked 551system.cpu.idleCycles 104690673 # Total number of cycles that the object has spent stopped 552system.cpu.dcache.tags.replacements 842468 # number of replacements 553system.cpu.dcache.tags.tagsinuse 511.899803 # Cycle average of tags in use |
| 554system.cpu.dcache.tags.total_refs 42541757 # Total number of references to valid blocks. | 554system.cpu.dcache.tags.total_refs 42541759 # Total number of references to valid blocks. |
| 555system.cpu.dcache.tags.sampled_refs 842980 # Sample count of references to valid blocks. | 555system.cpu.dcache.tags.sampled_refs 842980 # Sample count of references to valid blocks. |
| 556system.cpu.dcache.tags.avg_refs 50.465915 # Average number of references to valid blocks. | 556system.cpu.dcache.tags.avg_refs 50.465917 # Average number of references to valid blocks. |
| 557system.cpu.dcache.tags.warmup_cycle 594757500 # Cycle when the warmup percentage was hit. 558system.cpu.dcache.tags.occ_blocks::cpu.data 511.899803 # Average occupied blocks per requestor 559system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy 560system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy 561system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 562system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id 563system.cpu.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id 564system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id 565system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 557system.cpu.dcache.tags.warmup_cycle 594757500 # Cycle when the warmup percentage was hit. 558system.cpu.dcache.tags.occ_blocks::cpu.data 511.899803 # Average occupied blocks per requestor 559system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy 560system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy 561system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 562system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id 563system.cpu.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id 564system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id 565system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 566system.cpu.dcache.tags.tag_accesses 175934547 # Number of tag accesses 567system.cpu.dcache.tags.data_accesses 175934547 # Number of data accesses 568system.cpu.dcache.ReadReq_hits::cpu.data 23016254 # number of ReadReq hits 569system.cpu.dcache.ReadReq_hits::total 23016254 # number of ReadReq hits 570system.cpu.dcache.WriteReq_hits::cpu.data 18262412 # number of WriteReq hits 571system.cpu.dcache.WriteReq_hits::total 18262412 # number of WriteReq hits | 566system.cpu.dcache.tags.tag_accesses 175934555 # Number of tag accesses 567system.cpu.dcache.tags.data_accesses 175934555 # Number of data accesses 568system.cpu.dcache.ReadReq_hits::cpu.data 23016255 # number of ReadReq hits 569system.cpu.dcache.ReadReq_hits::total 23016255 # number of ReadReq hits 570system.cpu.dcache.WriteReq_hits::cpu.data 18262413 # number of WriteReq hits 571system.cpu.dcache.WriteReq_hits::total 18262413 # number of WriteReq hits |
| 572system.cpu.dcache.SoftPFReq_hits::cpu.data 356302 # number of SoftPFReq hits 573system.cpu.dcache.SoftPFReq_hits::total 356302 # number of SoftPFReq hits 574system.cpu.dcache.LoadLockedReq_hits::cpu.data 443705 # number of LoadLockedReq hits 575system.cpu.dcache.LoadLockedReq_hits::total 443705 # number of LoadLockedReq hits 576system.cpu.dcache.StoreCondReq_hits::cpu.data 460205 # number of StoreCondReq hits 577system.cpu.dcache.StoreCondReq_hits::total 460205 # number of StoreCondReq hits | 572system.cpu.dcache.SoftPFReq_hits::cpu.data 356302 # number of SoftPFReq hits 573system.cpu.dcache.SoftPFReq_hits::total 356302 # number of SoftPFReq hits 574system.cpu.dcache.LoadLockedReq_hits::cpu.data 443705 # number of LoadLockedReq hits 575system.cpu.dcache.LoadLockedReq_hits::total 443705 # number of LoadLockedReq hits 576system.cpu.dcache.StoreCondReq_hits::cpu.data 460205 # number of StoreCondReq hits 577system.cpu.dcache.StoreCondReq_hits::total 460205 # number of StoreCondReq hits |
| 578system.cpu.dcache.demand_hits::cpu.data 41278666 # number of demand (read+write) hits 579system.cpu.dcache.demand_hits::total 41278666 # number of demand (read+write) hits 580system.cpu.dcache.overall_hits::cpu.data 41634968 # number of overall hits 581system.cpu.dcache.overall_hits::total 41634968 # number of overall hits | 578system.cpu.dcache.demand_hits::cpu.data 41278668 # number of demand (read+write) hits 579system.cpu.dcache.demand_hits::total 41278668 # number of demand (read+write) hits 580system.cpu.dcache.overall_hits::cpu.data 41634970 # number of overall hits 581system.cpu.dcache.overall_hits::total 41634970 # number of overall hits |
| 582system.cpu.dcache.ReadReq_misses::cpu.data 493842 # number of ReadReq misses 583system.cpu.dcache.ReadReq_misses::total 493842 # number of ReadReq misses 584system.cpu.dcache.WriteReq_misses::cpu.data 547981 # number of WriteReq misses 585system.cpu.dcache.WriteReq_misses::total 547981 # number of WriteReq misses 586system.cpu.dcache.SoftPFReq_misses::cpu.data 169870 # number of SoftPFReq misses 587system.cpu.dcache.SoftPFReq_misses::total 169870 # number of SoftPFReq misses 588system.cpu.dcache.LoadLockedReq_misses::cpu.data 22311 # number of LoadLockedReq misses 589system.cpu.dcache.LoadLockedReq_misses::total 22311 # number of LoadLockedReq misses --- 10 unchanged lines hidden (view full) --- 600system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 292635500 # number of LoadLockedReq miss cycles 601system.cpu.dcache.LoadLockedReq_miss_latency::total 292635500 # number of LoadLockedReq miss cycles 602system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles 603system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles 604system.cpu.dcache.demand_miss_latency::cpu.data 43652936479 # number of demand (read+write) miss cycles 605system.cpu.dcache.demand_miss_latency::total 43652936479 # number of demand (read+write) miss cycles 606system.cpu.dcache.overall_miss_latency::cpu.data 43652936479 # number of overall miss cycles 607system.cpu.dcache.overall_miss_latency::total 43652936479 # number of overall miss cycles | 582system.cpu.dcache.ReadReq_misses::cpu.data 493842 # number of ReadReq misses 583system.cpu.dcache.ReadReq_misses::total 493842 # number of ReadReq misses 584system.cpu.dcache.WriteReq_misses::cpu.data 547981 # number of WriteReq misses 585system.cpu.dcache.WriteReq_misses::total 547981 # number of WriteReq misses 586system.cpu.dcache.SoftPFReq_misses::cpu.data 169870 # number of SoftPFReq misses 587system.cpu.dcache.SoftPFReq_misses::total 169870 # number of SoftPFReq misses 588system.cpu.dcache.LoadLockedReq_misses::cpu.data 22311 # number of LoadLockedReq misses 589system.cpu.dcache.LoadLockedReq_misses::total 22311 # number of LoadLockedReq misses --- 10 unchanged lines hidden (view full) --- 600system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 292635500 # number of LoadLockedReq miss cycles 601system.cpu.dcache.LoadLockedReq_miss_latency::total 292635500 # number of LoadLockedReq miss cycles 602system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles 603system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles 604system.cpu.dcache.demand_miss_latency::cpu.data 43652936479 # number of demand (read+write) miss cycles 605system.cpu.dcache.demand_miss_latency::total 43652936479 # number of demand (read+write) miss cycles 606system.cpu.dcache.overall_miss_latency::cpu.data 43652936479 # number of overall miss cycles 607system.cpu.dcache.overall_miss_latency::total 43652936479 # number of overall miss cycles |
| 608system.cpu.dcache.ReadReq_accesses::cpu.data 23510096 # number of ReadReq accesses(hits+misses) 609system.cpu.dcache.ReadReq_accesses::total 23510096 # number of ReadReq accesses(hits+misses) 610system.cpu.dcache.WriteReq_accesses::cpu.data 18810393 # number of WriteReq accesses(hits+misses) 611system.cpu.dcache.WriteReq_accesses::total 18810393 # number of WriteReq accesses(hits+misses) | 608system.cpu.dcache.ReadReq_accesses::cpu.data 23510097 # number of ReadReq accesses(hits+misses) 609system.cpu.dcache.ReadReq_accesses::total 23510097 # number of ReadReq accesses(hits+misses) 610system.cpu.dcache.WriteReq_accesses::cpu.data 18810394 # number of WriteReq accesses(hits+misses) 611system.cpu.dcache.WriteReq_accesses::total 18810394 # number of WriteReq accesses(hits+misses) |
| 612system.cpu.dcache.SoftPFReq_accesses::cpu.data 526172 # number of SoftPFReq accesses(hits+misses) 613system.cpu.dcache.SoftPFReq_accesses::total 526172 # number of SoftPFReq accesses(hits+misses) 614system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466016 # number of LoadLockedReq accesses(hits+misses) 615system.cpu.dcache.LoadLockedReq_accesses::total 466016 # number of LoadLockedReq accesses(hits+misses) 616system.cpu.dcache.StoreCondReq_accesses::cpu.data 460207 # number of StoreCondReq accesses(hits+misses) 617system.cpu.dcache.StoreCondReq_accesses::total 460207 # number of StoreCondReq accesses(hits+misses) | 612system.cpu.dcache.SoftPFReq_accesses::cpu.data 526172 # number of SoftPFReq accesses(hits+misses) 613system.cpu.dcache.SoftPFReq_accesses::total 526172 # number of SoftPFReq accesses(hits+misses) 614system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466016 # number of LoadLockedReq accesses(hits+misses) 615system.cpu.dcache.LoadLockedReq_accesses::total 466016 # number of LoadLockedReq accesses(hits+misses) 616system.cpu.dcache.StoreCondReq_accesses::cpu.data 460207 # number of StoreCondReq accesses(hits+misses) 617system.cpu.dcache.StoreCondReq_accesses::total 460207 # number of StoreCondReq accesses(hits+misses) |
| 618system.cpu.dcache.demand_accesses::cpu.data 42320489 # number of demand (read+write) accesses 619system.cpu.dcache.demand_accesses::total 42320489 # number of demand (read+write) accesses 620system.cpu.dcache.overall_accesses::cpu.data 42846661 # number of overall (read+write) accesses 621system.cpu.dcache.overall_accesses::total 42846661 # number of overall (read+write) accesses | 618system.cpu.dcache.demand_accesses::cpu.data 42320491 # number of demand (read+write) accesses 619system.cpu.dcache.demand_accesses::total 42320491 # number of demand (read+write) accesses 620system.cpu.dcache.overall_accesses::cpu.data 42846663 # number of overall (read+write) accesses 621system.cpu.dcache.overall_accesses::total 42846663 # number of overall (read+write) accesses |
| 622system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021006 # miss rate for ReadReq accesses 623system.cpu.dcache.ReadReq_miss_rate::total 0.021006 # miss rate for ReadReq accesses 624system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029132 # miss rate for WriteReq accesses 625system.cpu.dcache.WriteReq_miss_rate::total 0.029132 # miss rate for WriteReq accesses 626system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322841 # miss rate for SoftPFReq accesses 627system.cpu.dcache.SoftPFReq_miss_rate::total 0.322841 # miss rate for SoftPFReq accesses 628system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047876 # miss rate for LoadLockedReq accesses 629system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047876 # miss rate for LoadLockedReq accesses --- 844 unchanged lines hidden --- | 622system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021006 # miss rate for ReadReq accesses 623system.cpu.dcache.ReadReq_miss_rate::total 0.021006 # miss rate for ReadReq accesses 624system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029132 # miss rate for WriteReq accesses 625system.cpu.dcache.WriteReq_miss_rate::total 0.029132 # miss rate for WriteReq accesses 626system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322841 # miss rate for SoftPFReq accesses 627system.cpu.dcache.SoftPFReq_miss_rate::total 0.322841 # miss rate for SoftPFReq accesses 628system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047876 # miss rate for LoadLockedReq accesses 629system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047876 # miss rate for LoadLockedReq accesses --- 844 unchanged lines hidden --- |