| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.858505 # Number of seconds simulated 4sim_ticks 2858505242500 # Number of ticks simulated 5final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.858505 # Number of seconds simulated 4sim_ticks 2858505242500 # Number of ticks simulated 5final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 194204 # Simulator instruction rate (inst/s) 8host_op_rate 234807 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4961098243 # Simulator tick rate (ticks/s) 10host_mem_usage 583728 # Number of bytes of host memory used 11host_seconds 576.18 # Real time elapsed on the host | 7host_inst_rate 187730 # Simulator instruction rate (inst/s) 8host_op_rate 226980 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4795719535 # Simulator tick rate (ticks/s) 10host_mem_usage 583724 # Number of bytes of host memory used 11host_seconds 596.05 # Real time elapsed on the host |
| 12sim_insts 111897168 # Number of instructions simulated 13sim_ops 135292215 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1705984 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9156972 # Number of bytes read from this memory --- 626 unchanged lines hidden (view full) --- 646system.cpu.dcache.overall_avg_miss_latency::cpu.data 36026.399822 # average overall miss latency 647system.cpu.dcache.overall_avg_miss_latency::total 36026.399822 # average overall miss latency 648system.cpu.dcache.blocked_cycles::no_mshrs 306 # number of cycles access was blocked 649system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 650system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked 651system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 652system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.304348 # average number of cycles each access was blocked 653system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 111897168 # Number of instructions simulated 13sim_ops 135292215 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1705984 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9156972 # Number of bytes read from this memory --- 626 unchanged lines hidden (view full) --- 646system.cpu.dcache.overall_avg_miss_latency::cpu.data 36026.399822 # average overall miss latency 647system.cpu.dcache.overall_avg_miss_latency::total 36026.399822 # average overall miss latency 648system.cpu.dcache.blocked_cycles::no_mshrs 306 # number of cycles access was blocked 649system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 650system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked 651system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 652system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.304348 # average number of cycles each access was blocked 653system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 654system.cpu.dcache.fast_writes 0 # number of fast writes performed 655system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 656system.cpu.dcache.writebacks::writebacks 699681 # number of writebacks 657system.cpu.dcache.writebacks::total 699681 # number of writebacks 658system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76216 # number of ReadReq MSHR hits 659system.cpu.dcache.ReadReq_mshr_hits::total 76216 # number of ReadReq MSHR hits 660system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249477 # number of WriteReq MSHR hits 661system.cpu.dcache.WriteReq_mshr_hits::total 249477 # number of WriteReq MSHR hits 662system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14071 # number of LoadLockedReq MSHR hits 663system.cpu.dcache.LoadLockedReq_mshr_hits::total 14071 # number of LoadLockedReq MSHR hits --- 32 unchanged lines hidden (view full) --- 696system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165000 # number of StoreCondReq MSHR miss cycles 697system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165000 # number of StoreCondReq MSHR miss cycles 698system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25727386000 # number of demand (read+write) MSHR miss cycles 699system.cpu.dcache.demand_mshr_miss_latency::total 25727386000 # number of demand (read+write) MSHR miss cycles 700system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27438355500 # number of overall MSHR miss cycles 701system.cpu.dcache.overall_mshr_miss_latency::total 27438355500 # number of overall MSHR miss cycles 702system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6277881000 # number of ReadReq MSHR uncacheable cycles 703system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6277881000 # number of ReadReq MSHR uncacheable cycles | 654system.cpu.dcache.writebacks::writebacks 699681 # number of writebacks 655system.cpu.dcache.writebacks::total 699681 # number of writebacks 656system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76216 # number of ReadReq MSHR hits 657system.cpu.dcache.ReadReq_mshr_hits::total 76216 # number of ReadReq MSHR hits 658system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249477 # number of WriteReq MSHR hits 659system.cpu.dcache.WriteReq_mshr_hits::total 249477 # number of WriteReq MSHR hits 660system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14071 # number of LoadLockedReq MSHR hits 661system.cpu.dcache.LoadLockedReq_mshr_hits::total 14071 # number of LoadLockedReq MSHR hits --- 32 unchanged lines hidden (view full) --- 694system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165000 # number of StoreCondReq MSHR miss cycles 695system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165000 # number of StoreCondReq MSHR miss cycles 696system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25727386000 # number of demand (read+write) MSHR miss cycles 697system.cpu.dcache.demand_mshr_miss_latency::total 25727386000 # number of demand (read+write) MSHR miss cycles 698system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27438355500 # number of overall MSHR miss cycles 699system.cpu.dcache.overall_mshr_miss_latency::total 27438355500 # number of overall MSHR miss cycles 700system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6277881000 # number of ReadReq MSHR uncacheable cycles 701system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6277881000 # number of ReadReq MSHR uncacheable cycles |
| 704system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5085127500 # number of WriteReq MSHR uncacheable cycles 705system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5085127500 # number of WriteReq MSHR uncacheable cycles 706system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11363008500 # number of overall MSHR uncacheable cycles 707system.cpu.dcache.overall_mshr_uncacheable_latency::total 11363008500 # number of overall MSHR uncacheable cycles | 702system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6277881000 # number of overall MSHR uncacheable cycles 703system.cpu.dcache.overall_mshr_uncacheable_latency::total 6277881000 # number of overall MSHR uncacheable cycles |
| 708system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017764 # mshr miss rate for ReadReq accesses 709system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017764 # mshr miss rate for ReadReq accesses 710system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015869 # mshr miss rate for WriteReq accesses 711system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015869 # mshr miss rate for WriteReq accesses 712system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230759 # mshr miss rate for SoftPFReq accesses 713system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230759 # mshr miss rate for SoftPFReq accesses 714system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017682 # mshr miss rate for LoadLockedReq accesses 715system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017682 # mshr miss rate for LoadLockedReq accesses --- 14 unchanged lines hidden (view full) --- 730system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82500 # average StoreCondReq mshr miss latency 731system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82500 # average StoreCondReq mshr miss latency 732system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35925.580551 # average overall mshr miss latency 733system.cpu.dcache.demand_avg_mshr_miss_latency::total 35925.580551 # average overall mshr miss latency 734system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32760.298800 # average overall mshr miss latency 735system.cpu.dcache.overall_avg_mshr_miss_latency::total 32760.298800 # average overall mshr miss latency 736system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201679.548959 # average ReadReq mshr uncacheable latency 737system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201679.548959 # average ReadReq mshr uncacheable latency | 704system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017764 # mshr miss rate for ReadReq accesses 705system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017764 # mshr miss rate for ReadReq accesses 706system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015869 # mshr miss rate for WriteReq accesses 707system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015869 # mshr miss rate for WriteReq accesses 708system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230759 # mshr miss rate for SoftPFReq accesses 709system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230759 # mshr miss rate for SoftPFReq accesses 710system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017682 # mshr miss rate for LoadLockedReq accesses 711system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017682 # mshr miss rate for LoadLockedReq accesses --- 14 unchanged lines hidden (view full) --- 726system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82500 # average StoreCondReq mshr miss latency 727system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82500 # average StoreCondReq mshr miss latency 728system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35925.580551 # average overall mshr miss latency 729system.cpu.dcache.demand_avg_mshr_miss_latency::total 35925.580551 # average overall mshr miss latency 730system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32760.298800 # average overall mshr miss latency 731system.cpu.dcache.overall_avg_mshr_miss_latency::total 32760.298800 # average overall mshr miss latency 732system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201679.548959 # average ReadReq mshr uncacheable latency 733system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201679.548959 # average ReadReq mshr uncacheable latency |
| 738system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184357.303412 # average WriteReq mshr uncacheable latency 739system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184357.303412 # average WriteReq mshr uncacheable latency 740system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193541.389177 # average overall mshr uncacheable latency 741system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193541.389177 # average overall mshr uncacheable latency 742system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 734system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106928.531280 # average overall mshr uncacheable latency 735system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106928.531280 # average overall mshr uncacheable latency |
| 743system.cpu.icache.tags.replacements 2894371 # number of replacements 744system.cpu.icache.tags.tagsinuse 511.208818 # Cycle average of tags in use 745system.cpu.icache.tags.total_refs 54430342 # Total number of references to valid blocks. 746system.cpu.icache.tags.sampled_refs 2894883 # Sample count of references to valid blocks. 747system.cpu.icache.tags.avg_refs 18.802260 # Average number of references to valid blocks. 748system.cpu.icache.tags.warmup_cycle 18407091500 # Cycle when the warmup percentage was hit. 749system.cpu.icache.tags.occ_blocks::cpu.inst 511.208818 # Average occupied blocks per requestor 750system.cpu.icache.tags.occ_percent::cpu.inst 0.998455 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 793system.cpu.icache.overall_avg_miss_latency::cpu.inst 13973.899399 # average overall miss latency 794system.cpu.icache.overall_avg_miss_latency::total 13973.899399 # average overall miss latency 795system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 796system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 797system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 798system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 799system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 800system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 736system.cpu.icache.tags.replacements 2894371 # number of replacements 737system.cpu.icache.tags.tagsinuse 511.208818 # Cycle average of tags in use 738system.cpu.icache.tags.total_refs 54430342 # Total number of references to valid blocks. 739system.cpu.icache.tags.sampled_refs 2894883 # Sample count of references to valid blocks. 740system.cpu.icache.tags.avg_refs 18.802260 # Average number of references to valid blocks. 741system.cpu.icache.tags.warmup_cycle 18407091500 # Cycle when the warmup percentage was hit. 742system.cpu.icache.tags.occ_blocks::cpu.inst 511.208818 # Average occupied blocks per requestor 743system.cpu.icache.tags.occ_percent::cpu.inst 0.998455 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 786system.cpu.icache.overall_avg_miss_latency::cpu.inst 13973.899399 # average overall miss latency 787system.cpu.icache.overall_avg_miss_latency::total 13973.899399 # average overall miss latency 788system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 789system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 790system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 791system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 792system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 793system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 801system.cpu.icache.fast_writes 0 # number of fast writes performed 802system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 803system.cpu.icache.writebacks::writebacks 2894371 # number of writebacks 804system.cpu.icache.writebacks::total 2894371 # number of writebacks 805system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2894895 # number of ReadReq MSHR misses 806system.cpu.icache.ReadReq_mshr_misses::total 2894895 # number of ReadReq MSHR misses 807system.cpu.icache.demand_mshr_misses::cpu.inst 2894895 # number of demand (read+write) MSHR misses 808system.cpu.icache.demand_mshr_misses::total 2894895 # number of demand (read+write) MSHR misses 809system.cpu.icache.overall_mshr_misses::cpu.inst 2894895 # number of overall MSHR misses 810system.cpu.icache.overall_mshr_misses::total 2894895 # number of overall MSHR misses --- 22 unchanged lines hidden (view full) --- 833system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12973.899744 # average overall mshr miss latency 834system.cpu.icache.demand_avg_mshr_miss_latency::total 12973.899744 # average overall mshr miss latency 835system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12973.899744 # average overall mshr miss latency 836system.cpu.icache.overall_avg_mshr_miss_latency::total 12973.899744 # average overall mshr miss latency 837system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average ReadReq mshr uncacheable latency 838system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129131.411108 # average ReadReq mshr uncacheable latency 839system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average overall mshr uncacheable latency 840system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129131.411108 # average overall mshr uncacheable latency | 794system.cpu.icache.writebacks::writebacks 2894371 # number of writebacks 795system.cpu.icache.writebacks::total 2894371 # number of writebacks 796system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2894895 # number of ReadReq MSHR misses 797system.cpu.icache.ReadReq_mshr_misses::total 2894895 # number of ReadReq MSHR misses 798system.cpu.icache.demand_mshr_misses::cpu.inst 2894895 # number of demand (read+write) MSHR misses 799system.cpu.icache.demand_mshr_misses::total 2894895 # number of demand (read+write) MSHR misses 800system.cpu.icache.overall_mshr_misses::cpu.inst 2894895 # number of overall MSHR misses 801system.cpu.icache.overall_mshr_misses::total 2894895 # number of overall MSHR misses --- 22 unchanged lines hidden (view full) --- 824system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12973.899744 # average overall mshr miss latency 825system.cpu.icache.demand_avg_mshr_miss_latency::total 12973.899744 # average overall mshr miss latency 826system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12973.899744 # average overall mshr miss latency 827system.cpu.icache.overall_avg_mshr_miss_latency::total 12973.899744 # average overall mshr miss latency 828system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average ReadReq mshr uncacheable latency 829system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129131.411108 # average ReadReq mshr uncacheable latency 830system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average overall mshr uncacheable latency 831system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129131.411108 # average overall mshr uncacheable latency |
| 841system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 842system.cpu.l2cache.tags.replacements 96490 # number of replacements 843system.cpu.l2cache.tags.tagsinuse 65016.669962 # Cycle average of tags in use 844system.cpu.l2cache.tags.total_refs 7024998 # Total number of references to valid blocks. 845system.cpu.l2cache.tags.sampled_refs 161737 # Sample count of references to valid blocks. 846system.cpu.l2cache.tags.avg_refs 43.434700 # Average number of references to valid blocks. 847system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 848system.cpu.l2cache.tags.occ_blocks::writebacks 47281.634154 # Average occupied blocks per requestor 849system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 66.002490 # Average occupied blocks per requestor --- 163 unchanged lines hidden (view full) --- 1013system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128585.575573 # average overall miss latency 1014system.cpu.l2cache.overall_avg_miss_latency::total 128859.041748 # average overall miss latency 1015system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1016system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1017system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1018system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1019system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1020system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 832system.cpu.l2cache.tags.replacements 96490 # number of replacements 833system.cpu.l2cache.tags.tagsinuse 65016.669962 # Cycle average of tags in use 834system.cpu.l2cache.tags.total_refs 7024998 # Total number of references to valid blocks. 835system.cpu.l2cache.tags.sampled_refs 161737 # Sample count of references to valid blocks. 836system.cpu.l2cache.tags.avg_refs 43.434700 # Average number of references to valid blocks. 837system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 838system.cpu.l2cache.tags.occ_blocks::writebacks 47281.634154 # Average occupied blocks per requestor 839system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 66.002490 # Average occupied blocks per requestor --- 163 unchanged lines hidden (view full) --- 1003system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128585.575573 # average overall miss latency 1004system.cpu.l2cache.overall_avg_miss_latency::total 128859.041748 # average overall miss latency 1005system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1006system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1007system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1008system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1009system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1010system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1021system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1022system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 1023system.cpu.l2cache.writebacks::writebacks 88112 # number of writebacks 1024system.cpu.l2cache.writebacks::total 88112 # number of writebacks 1025system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 25 # number of ReadCleanReq MSHR hits 1026system.cpu.l2cache.ReadCleanReq_mshr_hits::total 25 # number of ReadCleanReq MSHR hits 1027system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 140 # number of ReadSharedReq MSHR hits 1028system.cpu.l2cache.ReadSharedReq_mshr_hits::total 140 # number of ReadSharedReq MSHR hits 1029system.cpu.l2cache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits 1030system.cpu.l2cache.demand_mshr_hits::cpu.data 140 # number of demand (read+write) MSHR hits --- 53 unchanged lines hidden (view full) --- 1084system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 15971000 # number of overall MSHR miss cycles 1085system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 122500 # number of overall MSHR miss cycles 1086system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2761977000 # number of overall MSHR miss cycles 1087system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17216054500 # number of overall MSHR miss cycles 1088system.cpu.l2cache.overall_mshr_miss_latency::total 19994125000 # number of overall MSHR miss cycles 1089system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 427218000 # number of ReadReq MSHR uncacheable cycles 1090system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888707000 # number of ReadReq MSHR uncacheable cycles 1091system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6315925000 # number of ReadReq MSHR uncacheable cycles | 1011system.cpu.l2cache.writebacks::writebacks 88112 # number of writebacks 1012system.cpu.l2cache.writebacks::total 88112 # number of writebacks 1013system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 25 # number of ReadCleanReq MSHR hits 1014system.cpu.l2cache.ReadCleanReq_mshr_hits::total 25 # number of ReadCleanReq MSHR hits 1015system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 140 # number of ReadSharedReq MSHR hits 1016system.cpu.l2cache.ReadSharedReq_mshr_hits::total 140 # number of ReadSharedReq MSHR hits 1017system.cpu.l2cache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits 1018system.cpu.l2cache.demand_mshr_hits::cpu.data 140 # number of demand (read+write) MSHR hits --- 53 unchanged lines hidden (view full) --- 1072system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 15971000 # number of overall MSHR miss cycles 1073system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 122500 # number of overall MSHR miss cycles 1074system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2761977000 # number of overall MSHR miss cycles 1075system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17216054500 # number of overall MSHR miss cycles 1076system.cpu.l2cache.overall_mshr_miss_latency::total 19994125000 # number of overall MSHR miss cycles 1077system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 427218000 # number of ReadReq MSHR uncacheable cycles 1078system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888707000 # number of ReadReq MSHR uncacheable cycles 1079system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6315925000 # number of ReadReq MSHR uncacheable cycles |
| 1092system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4767887000 # number of WriteReq MSHR uncacheable cycles 1093system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4767887000 # number of WriteReq MSHR uncacheable cycles | |
| 1094system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 427218000 # number of overall MSHR uncacheable cycles | 1080system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 427218000 # number of overall MSHR uncacheable cycles |
| 1095system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10656594000 # number of overall MSHR uncacheable cycles 1096system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11083812000 # number of overall MSHR uncacheable cycles | 1081system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5888707000 # number of overall MSHR uncacheable cycles 1082system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6315925000 # number of overall MSHR uncacheable cycles |
| 1097system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001706 # mshr miss rate for ReadReq accesses 1098system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000208 # mshr miss rate for ReadReq accesses 1099system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001612 # mshr miss rate for ReadReq accesses 1100system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982361 # mshr miss rate for UpgradeReq accesses 1101system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982361 # mshr miss rate for UpgradeReq accesses 1102system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1103system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1104system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442730 # mshr miss rate for ReadExReq accesses --- 33 unchanged lines hidden (view full) --- 1138system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129845.528455 # average overall mshr miss latency 1139system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency 1140system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120589.285714 # average overall mshr miss latency 1141system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118587.469692 # average overall mshr miss latency 1142system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118868.308720 # average overall mshr miss latency 1143system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average ReadReq mshr uncacheable latency 1144system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189177.171678 # average ReadReq mshr uncacheable latency 1145system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181018.744089 # average ReadReq mshr uncacheable latency | 1083system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001706 # mshr miss rate for ReadReq accesses 1084system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000208 # mshr miss rate for ReadReq accesses 1085system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001612 # mshr miss rate for ReadReq accesses 1086system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982361 # mshr miss rate for UpgradeReq accesses 1087system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982361 # mshr miss rate for UpgradeReq accesses 1088system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1089system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1090system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442730 # mshr miss rate for ReadExReq accesses --- 33 unchanged lines hidden (view full) --- 1124system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129845.528455 # average overall mshr miss latency 1125system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency 1126system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120589.285714 # average overall mshr miss latency 1127system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118587.469692 # average overall mshr miss latency 1128system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118868.308720 # average overall mshr miss latency 1129system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average ReadReq mshr uncacheable latency 1130system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189177.171678 # average ReadReq mshr uncacheable latency 1131system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181018.744089 # average ReadReq mshr uncacheable latency |
| 1146system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172855.998260 # average WriteReq mshr uncacheable latency 1147system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172855.998260 # average WriteReq mshr uncacheable latency | |
| 1148system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average overall mshr uncacheable latency | 1132system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average overall mshr uncacheable latency |
| 1149system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181509.325339 # average overall mshr uncacheable latency 1150system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177414.796555 # average overall mshr uncacheable latency 1151system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1133system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100299.892695 # average overall mshr uncacheable latency 1134system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 101096.856292 # average overall mshr uncacheable latency |
| 1152system.cpu.toL2Bus.snoop_filter.tot_requests 7506242 # Total number of requests made to the snoop filter. 1153system.cpu.toL2Bus.snoop_filter.hit_single_requests 3768367 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1154system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58373 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1155system.cpu.toL2Bus.snoop_filter.tot_snoops 592 # Total number of snoops made to the snoop filter. 1156system.cpu.toL2Bus.snoop_filter.hit_single_snoops 592 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1157system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1158system.cpu.toL2Bus.trans_dist::ReadReq 134878 # Transaction distribution 1159system.cpu.toL2Bus.trans_dist::ReadResp 3577264 # Transaction distribution --- 151 unchanged lines hidden (view full) --- 1311system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1312system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1313system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1314system.iocache.tags.data_accesses 328122 # Number of data accesses 1315system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1316system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1317system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1318system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses | 1135system.cpu.toL2Bus.snoop_filter.tot_requests 7506242 # Total number of requests made to the snoop filter. 1136system.cpu.toL2Bus.snoop_filter.hit_single_requests 3768367 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1137system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58373 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1138system.cpu.toL2Bus.snoop_filter.tot_snoops 592 # Total number of snoops made to the snoop filter. 1139system.cpu.toL2Bus.snoop_filter.hit_single_snoops 592 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1140system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1141system.cpu.toL2Bus.trans_dist::ReadReq 134878 # Transaction distribution 1142system.cpu.toL2Bus.trans_dist::ReadResp 3577264 # Transaction distribution --- 151 unchanged lines hidden (view full) --- 1294system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1295system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1296system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1297system.iocache.tags.data_accesses 328122 # Number of data accesses 1298system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1299system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1300system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1301system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses |
| 1319system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses 1320system.iocache.demand_misses::total 234 # number of demand (read+write) misses 1321system.iocache.overall_misses::realview.ide 234 # number of overall misses 1322system.iocache.overall_misses::total 234 # number of overall misses | 1302system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses 1303system.iocache.demand_misses::total 36458 # number of demand (read+write) misses 1304system.iocache.overall_misses::realview.ide 36458 # number of overall misses 1305system.iocache.overall_misses::total 36458 # number of overall misses |
| 1323system.iocache.ReadReq_miss_latency::realview.ide 29059377 # number of ReadReq miss cycles 1324system.iocache.ReadReq_miss_latency::total 29059377 # number of ReadReq miss cycles 1325system.iocache.WriteLineReq_miss_latency::realview.ide 4548977125 # number of WriteLineReq miss cycles 1326system.iocache.WriteLineReq_miss_latency::total 4548977125 # number of WriteLineReq miss cycles | 1306system.iocache.ReadReq_miss_latency::realview.ide 29059377 # number of ReadReq miss cycles 1307system.iocache.ReadReq_miss_latency::total 29059377 # number of ReadReq miss cycles 1308system.iocache.WriteLineReq_miss_latency::realview.ide 4548977125 # number of WriteLineReq miss cycles 1309system.iocache.WriteLineReq_miss_latency::total 4548977125 # number of WriteLineReq miss cycles |
| 1327system.iocache.demand_miss_latency::realview.ide 29059377 # number of demand (read+write) miss cycles 1328system.iocache.demand_miss_latency::total 29059377 # number of demand (read+write) miss cycles 1329system.iocache.overall_miss_latency::realview.ide 29059377 # number of overall miss cycles 1330system.iocache.overall_miss_latency::total 29059377 # number of overall miss cycles | 1310system.iocache.demand_miss_latency::realview.ide 4578036502 # number of demand (read+write) miss cycles 1311system.iocache.demand_miss_latency::total 4578036502 # number of demand (read+write) miss cycles 1312system.iocache.overall_miss_latency::realview.ide 4578036502 # number of overall miss cycles 1313system.iocache.overall_miss_latency::total 4578036502 # number of overall miss cycles |
| 1331system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1332system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1333system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1334system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) | 1314system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1315system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1316system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1317system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) |
| 1335system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses 1336system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses 1337system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses 1338system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses | 1318system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses 1319system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses 1320system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses 1321system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses |
| 1339system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1340system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1341system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1342system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1343system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1344system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1345system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1346system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1347system.iocache.ReadReq_avg_miss_latency::realview.ide 124185.371795 # average ReadReq miss latency 1348system.iocache.ReadReq_avg_miss_latency::total 124185.371795 # average ReadReq miss latency 1349system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125579.094661 # average WriteLineReq miss latency 1350system.iocache.WriteLineReq_avg_miss_latency::total 125579.094661 # average WriteLineReq miss latency | 1322system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1323system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1324system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1325system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1326system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1327system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1328system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1329system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1330system.iocache.ReadReq_avg_miss_latency::realview.ide 124185.371795 # average ReadReq miss latency 1331system.iocache.ReadReq_avg_miss_latency::total 124185.371795 # average ReadReq miss latency 1332system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125579.094661 # average WriteLineReq miss latency 1333system.iocache.WriteLineReq_avg_miss_latency::total 125579.094661 # average WriteLineReq miss latency |
| 1351system.iocache.demand_avg_miss_latency::realview.ide 124185.371795 # average overall miss latency 1352system.iocache.demand_avg_miss_latency::total 124185.371795 # average overall miss latency 1353system.iocache.overall_avg_miss_latency::realview.ide 124185.371795 # average overall miss latency 1354system.iocache.overall_avg_miss_latency::total 124185.371795 # average overall miss latency | 1334system.iocache.demand_avg_miss_latency::realview.ide 125570.149268 # average overall miss latency 1335system.iocache.demand_avg_miss_latency::total 125570.149268 # average overall miss latency 1336system.iocache.overall_avg_miss_latency::realview.ide 125570.149268 # average overall miss latency 1337system.iocache.overall_avg_miss_latency::total 125570.149268 # average overall miss latency |
| 1355system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1356system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1357system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1358system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1359system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1360system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1338system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1339system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1340system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1341system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1342system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1343system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1361system.iocache.fast_writes 0 # number of fast writes performed 1362system.iocache.cache_copies 0 # number of cache copies performed | |
| 1363system.iocache.writebacks::writebacks 36190 # number of writebacks 1364system.iocache.writebacks::total 36190 # number of writebacks 1365system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1366system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1367system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1368system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses | 1344system.iocache.writebacks::writebacks 36190 # number of writebacks 1345system.iocache.writebacks::total 36190 # number of writebacks 1346system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1347system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1348system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1349system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses |
| 1369system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses 1370system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses 1371system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses 1372system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses | 1350system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses 1351system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses 1352system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses 1353system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses |
| 1373system.iocache.ReadReq_mshr_miss_latency::realview.ide 17359377 # number of ReadReq MSHR miss cycles 1374system.iocache.ReadReq_mshr_miss_latency::total 17359377 # number of ReadReq MSHR miss cycles 1375system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736351620 # number of WriteLineReq MSHR miss cycles 1376system.iocache.WriteLineReq_mshr_miss_latency::total 2736351620 # number of WriteLineReq MSHR miss cycles | 1354system.iocache.ReadReq_mshr_miss_latency::realview.ide 17359377 # number of ReadReq MSHR miss cycles 1355system.iocache.ReadReq_mshr_miss_latency::total 17359377 # number of ReadReq MSHR miss cycles 1356system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736351620 # number of WriteLineReq MSHR miss cycles 1357system.iocache.WriteLineReq_mshr_miss_latency::total 2736351620 # number of WriteLineReq MSHR miss cycles |
| 1377system.iocache.demand_mshr_miss_latency::realview.ide 17359377 # number of demand (read+write) MSHR miss cycles 1378system.iocache.demand_mshr_miss_latency::total 17359377 # number of demand (read+write) MSHR miss cycles 1379system.iocache.overall_mshr_miss_latency::realview.ide 17359377 # number of overall MSHR miss cycles 1380system.iocache.overall_mshr_miss_latency::total 17359377 # number of overall MSHR miss cycles | 1358system.iocache.demand_mshr_miss_latency::realview.ide 2753710997 # number of demand (read+write) MSHR miss cycles 1359system.iocache.demand_mshr_miss_latency::total 2753710997 # number of demand (read+write) MSHR miss cycles 1360system.iocache.overall_mshr_miss_latency::realview.ide 2753710997 # number of overall MSHR miss cycles 1361system.iocache.overall_mshr_miss_latency::total 2753710997 # number of overall MSHR miss cycles |
| 1381system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1382system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1383system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1384system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1385system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1386system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1387system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1388system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1389system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74185.371795 # average ReadReq mshr miss latency 1390system.iocache.ReadReq_avg_mshr_miss_latency::total 74185.371795 # average ReadReq mshr miss latency 1391system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75539.742160 # average WriteLineReq mshr miss latency 1392system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75539.742160 # average WriteLineReq mshr miss latency | 1362system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1363system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1364system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1365system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1366system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1367system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1368system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1369system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1370system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74185.371795 # average ReadReq mshr miss latency 1371system.iocache.ReadReq_avg_mshr_miss_latency::total 74185.371795 # average ReadReq mshr miss latency 1372system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75539.742160 # average WriteLineReq mshr miss latency 1373system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75539.742160 # average WriteLineReq mshr miss latency |
| 1393system.iocache.demand_avg_mshr_miss_latency::realview.ide 74185.371795 # average overall mshr miss latency 1394system.iocache.demand_avg_mshr_miss_latency::total 74185.371795 # average overall mshr miss latency 1395system.iocache.overall_avg_mshr_miss_latency::realview.ide 74185.371795 # average overall mshr miss latency 1396system.iocache.overall_avg_mshr_miss_latency::total 74185.371795 # average overall mshr miss latency 1397system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1374system.iocache.demand_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency 1375system.iocache.demand_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency 1376system.iocache.overall_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency 1377system.iocache.overall_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency |
| 1398system.membus.trans_dist::ReadReq 34891 # Transaction distribution 1399system.membus.trans_dist::ReadResp 72400 # Transaction distribution 1400system.membus.trans_dist::WriteReq 27583 # Transaction distribution 1401system.membus.trans_dist::WriteResp 27583 # Transaction distribution 1402system.membus.trans_dist::WritebackDirty 124302 # Transaction distribution 1403system.membus.trans_dist::CleanEvict 8612 # Transaction distribution 1404system.membus.trans_dist::UpgradeReq 4581 # Transaction distribution 1405system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution --- 88 unchanged lines hidden --- | 1378system.membus.trans_dist::ReadReq 34891 # Transaction distribution 1379system.membus.trans_dist::ReadResp 72400 # Transaction distribution 1380system.membus.trans_dist::WriteReq 27583 # Transaction distribution 1381system.membus.trans_dist::WriteResp 27583 # Transaction distribution 1382system.membus.trans_dist::WritebackDirty 124302 # Transaction distribution 1383system.membus.trans_dist::CleanEvict 8612 # Transaction distribution 1384system.membus.trans_dist::UpgradeReq 4581 # Transaction distribution 1385system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution --- 88 unchanged lines hidden --- |