| stats.txt (11103:38f6188421e0) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.852655 # Number of seconds simulated 4sim_ticks 2852654988500 # Number of ticks simulated 5final_tick 2852654988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.858301 # Number of seconds simulated 4sim_ticks 2858301146500 # Number of ticks simulated 5final_tick 2858301146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 116178 # Simulator instruction rate (inst/s) 8host_op_rate 140471 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2957977243 # Simulator tick rate (ticks/s) 10host_mem_usage 618900 # Number of bytes of host memory used 11host_seconds 964.39 # Real time elapsed on the host 12sim_insts 112040950 # Number of instructions simulated 13sim_ops 135468925 # Number of ops (including micro ops) simulated | 7host_inst_rate 158663 # Simulator instruction rate (inst/s) 8host_op_rate 191838 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4049033168 # Simulator tick rate (ticks/s) 10host_mem_usage 629392 # Number of bytes of host memory used 11host_seconds 705.92 # Real time elapsed on the host 12sim_insts 112003872 # Number of instructions simulated 13sim_ops 135422492 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.dtb.walker 8064 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.dtb.walker 7936 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.inst 1669952 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9187372 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.inst 1692928 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9156716 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::total 10866412 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1669952 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1669952 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 7981376 # Number of bytes written to this memory | 21system.physmem.bytes_read::total 10858604 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1692928 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1692928 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 7945984 # Number of bytes written to this memory |
| 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory | 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory |
| 26system.physmem.bytes_written::total 7998900 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 126 # Number of read requests responded to by this memory | 26system.physmem.bytes_written::total 7963508 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 124 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory | 28system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory |
| 29system.physmem.num_reads::cpu.inst 26093 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 144074 # Number of read requests responded to by this memory | 29system.physmem.num_reads::cpu.inst 26452 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 143595 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::total 170309 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 124709 # Number of write requests responded to by this memory | 32system.physmem.num_reads::total 170187 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 124156 # Number of write requests responded to by this memory |
| 34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory | 34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory |
| 35system.physmem.num_writes::total 129090 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 2827 # Total read bandwidth from this memory (bytes/s) | 35system.physmem.num_writes::total 128537 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 2776 # Total read bandwidth from this memory (bytes/s) |
| 37system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) | 37system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) |
| 38system.physmem.bw_read::cpu.inst 585403 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 3220639 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 3809228 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 585403 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 585403 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 2797876 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2804019 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 2797876 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 2827 # Total bandwidth to/from this memory (bytes/s) | 38system.physmem.bw_read::cpu.inst 592285 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 3203552 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 3798971 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 592285 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 592285 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 2779967 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 6131 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2786098 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 2779967 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 2776 # Total bandwidth to/from this memory (bytes/s) |
| 49system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) | 49system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) |
| 50system.physmem.bw_total::cpu.inst 585403 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 3226782 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 6613247 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 170309 # Number of read requests accepted 55system.physmem.writeReqs 129090 # Number of write requests accepted 56system.physmem.readBursts 170309 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 129090 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 10890880 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue 60system.physmem.bytesWritten 8010944 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 10866412 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 7998900 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 40828 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 10905 # Per bank write bursts 67system.physmem.perBankRdBursts::1 10842 # Per bank write bursts 68system.physmem.perBankRdBursts::2 10713 # Per bank write bursts 69system.physmem.perBankRdBursts::3 10735 # Per bank write bursts 70system.physmem.perBankRdBursts::4 13349 # Per bank write bursts 71system.physmem.perBankRdBursts::5 10818 # Per bank write bursts 72system.physmem.perBankRdBursts::6 11158 # Per bank write bursts 73system.physmem.perBankRdBursts::7 10982 # Per bank write bursts 74system.physmem.perBankRdBursts::8 10119 # Per bank write bursts 75system.physmem.perBankRdBursts::9 10274 # Per bank write bursts 76system.physmem.perBankRdBursts::10 10247 # Per bank write bursts 77system.physmem.perBankRdBursts::11 9187 # Per bank write bursts 78system.physmem.perBankRdBursts::12 10322 # Per bank write bursts 79system.physmem.perBankRdBursts::13 10753 # Per bank write bursts 80system.physmem.perBankRdBursts::14 10041 # Per bank write bursts 81system.physmem.perBankRdBursts::15 9725 # Per bank write bursts 82system.physmem.perBankWrBursts::0 8109 # Per bank write bursts 83system.physmem.perBankWrBursts::1 8208 # Per bank write bursts 84system.physmem.perBankWrBursts::2 8370 # Per bank write bursts 85system.physmem.perBankWrBursts::3 8304 # Per bank write bursts 86system.physmem.perBankWrBursts::4 7540 # Per bank write bursts 87system.physmem.perBankWrBursts::5 7865 # Per bank write bursts 88system.physmem.perBankWrBursts::6 8185 # Per bank write bursts 89system.physmem.perBankWrBursts::7 8104 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7740 # Per bank write bursts 91system.physmem.perBankWrBursts::9 7807 # Per bank write bursts 92system.physmem.perBankWrBursts::10 7671 # Per bank write bursts 93system.physmem.perBankWrBursts::11 7052 # Per bank write bursts 94system.physmem.perBankWrBursts::12 7765 # Per bank write bursts 95system.physmem.perBankWrBursts::13 7977 # Per bank write bursts 96system.physmem.perBankWrBursts::14 7383 # Per bank write bursts 97system.physmem.perBankWrBursts::15 7091 # Per bank write bursts | 50system.physmem.bw_total::cpu.inst 592285 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 3209683 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 6585070 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 170187 # Number of read requests accepted 55system.physmem.writeReqs 128537 # Number of write requests accepted 56system.physmem.readBursts 170187 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 128537 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 10884288 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue 60system.physmem.bytesWritten 7975936 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 10858604 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 7963508 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 40806 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 10600 # Per bank write bursts 67system.physmem.perBankRdBursts::1 10887 # Per bank write bursts 68system.physmem.perBankRdBursts::2 11108 # Per bank write bursts 69system.physmem.perBankRdBursts::3 10980 # Per bank write bursts 70system.physmem.perBankRdBursts::4 13553 # Per bank write bursts 71system.physmem.perBankRdBursts::5 10410 # Per bank write bursts 72system.physmem.perBankRdBursts::6 10585 # Per bank write bursts 73system.physmem.perBankRdBursts::7 10816 # Per bank write bursts 74system.physmem.perBankRdBursts::8 10327 # Per bank write bursts 75system.physmem.perBankRdBursts::9 10604 # Per bank write bursts 76system.physmem.perBankRdBursts::10 9912 # Per bank write bursts 77system.physmem.perBankRdBursts::11 9123 # Per bank write bursts 78system.physmem.perBankRdBursts::12 10363 # Per bank write bursts 79system.physmem.perBankRdBursts::13 10770 # Per bank write bursts 80system.physmem.perBankRdBursts::14 10067 # Per bank write bursts 81system.physmem.perBankRdBursts::15 9962 # Per bank write bursts 82system.physmem.perBankWrBursts::0 7842 # Per bank write bursts 83system.physmem.perBankWrBursts::1 8249 # Per bank write bursts 84system.physmem.perBankWrBursts::2 8721 # Per bank write bursts 85system.physmem.perBankWrBursts::3 8464 # Per bank write bursts 86system.physmem.perBankWrBursts::4 7420 # Per bank write bursts 87system.physmem.perBankWrBursts::5 7583 # Per bank write bursts 88system.physmem.perBankWrBursts::6 7625 # Per bank write bursts 89system.physmem.perBankWrBursts::7 7909 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7872 # Per bank write bursts 91system.physmem.perBankWrBursts::9 8104 # Per bank write bursts 92system.physmem.perBankWrBursts::10 7451 # Per bank write bursts 93system.physmem.perBankWrBursts::11 6976 # Per bank write bursts 94system.physmem.perBankWrBursts::12 7788 # Per bank write bursts 95system.physmem.perBankWrBursts::13 7975 # Per bank write bursts 96system.physmem.perBankWrBursts::14 7387 # Per bank write bursts 97system.physmem.perBankWrBursts::15 7258 # Per bank write bursts |
| 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 99system.physmem.numWrRetry 9 # Number of times write queue was full causing retry 100system.physmem.totGap 2852654585000 # Total gap between requests | 99system.physmem.numWrRetry 16 # Number of times write queue was full causing retry 100system.physmem.totGap 2858300743000 # Total gap between requests |
| 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 543 # Read request sizes (log2) 104system.physmem.readPktSize::3 14 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) | 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 543 # Read request sizes (log2) 104system.physmem.readPktSize::3 14 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 107system.physmem.readPktSize::6 169752 # Read request sizes (log2) | 107system.physmem.readPktSize::6 169630 # Read request sizes (log2) |
| 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 4381 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) | 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 4381 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 114system.physmem.writePktSize::6 124709 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 163118 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 6752 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 288 # What read queue length does an incoming req see | 114system.physmem.writePktSize::6 124156 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 163271 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 6497 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 287 # What read queue length does an incoming req see |
| 118system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 118system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::15 2006 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2382 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 6432 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 6848 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6545 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 6600 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 6545 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 7831 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 8111 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 9317 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 8521 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 8298 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 7372 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 7570 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 7489 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6676 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6538 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6515 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 200 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 252 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 281 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 179 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 148 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 161 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 169 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 158 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 150 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 148 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 123 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 90 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 132 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 105 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 90 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 80 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 106 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 105 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 117 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 84 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 132 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 56 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 40 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 44 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 60691 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 311.442553 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 184.035683 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 329.553660 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 22186 36.56% 36.56% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 14675 24.18% 60.74% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 6464 10.65% 71.39% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3592 5.92% 77.30% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2485 4.09% 81.40% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1671 2.75% 84.15% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1111 1.83% 85.98% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1120 1.85% 87.83% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 7387 12.17% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 60691 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 6290 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 27.051669 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 539.627643 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 6288 99.97% 99.97% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 6290 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 6290 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 19.900000 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.361154 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 12.375647 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 5497 87.39% 87.39% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 61 0.97% 88.36% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 183 2.91% 91.27% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 46 0.73% 92.00% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 63 1.00% 93.00% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 171 2.72% 95.72% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 19 0.30% 96.03% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 8 0.13% 96.15% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 10 0.16% 96.31% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 10 0.16% 96.47% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 3 0.05% 96.52% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 2 0.03% 96.55% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 171 2.72% 99.27% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 2 0.03% 99.30% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 4 0.06% 99.36% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 5 0.08% 99.44% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 3 0.05% 99.49% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::96-99 4 0.06% 99.55% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::100-103 2 0.03% 99.59% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::104-107 1 0.02% 99.60% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::112-115 1 0.02% 99.62% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::116-119 1 0.02% 99.63% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::124-127 1 0.02% 99.65% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::128-131 15 0.24% 99.89% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::132-135 1 0.02% 99.90% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::148-151 1 0.02% 99.92% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::152-155 3 0.05% 99.97% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::224-227 1 0.02% 100.00% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::total 6290 # Writes before turning the bus around for reads 266system.physmem.totQLat 1692148250 # Total ticks spent queuing 267system.physmem.totMemAccLat 4882835750 # Total ticks spent from burst creation until serviced by the DRAM 268system.physmem.totBusLat 850850000 # Total ticks spent in databus transfers 269system.physmem.avgQLat 9943.87 # Average queueing delay per DRAM burst | 162system.physmem.wrQLenPdf::15 1999 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2366 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 6060 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 6285 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6722 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 6794 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 7541 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 7289 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 8121 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 8253 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 8186 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 9555 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 7722 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 7050 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 7178 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6841 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6509 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6410 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 319 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 249 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 180 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 208 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 166 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 173 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 150 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 123 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 172 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 144 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 134 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 141 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 144 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 153 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 91 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 78 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 85 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 59 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 50 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 49 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 40 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 42 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 61607 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 306.136640 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 182.409953 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 323.199512 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 22530 36.57% 36.57% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 14842 24.09% 60.66% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 6878 11.16% 71.83% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3579 5.81% 77.64% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2575 4.18% 81.82% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 2036 3.30% 85.12% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1091 1.77% 86.89% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1049 1.70% 88.59% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 7027 11.41% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 61607 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 6204 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 27.410058 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 569.248357 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 6203 99.98% 99.98% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::total 6204 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 6204 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 20.087685 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 18.454852 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 12.723718 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-19 5415 87.28% 87.28% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::20-23 82 1.32% 88.60% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-27 29 0.47% 89.07% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-31 170 2.74% 91.81% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-35 36 0.58% 92.39% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::36-39 140 2.26% 94.65% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-43 51 0.82% 95.47% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::44-47 9 0.15% 95.62% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::48-51 26 0.42% 96.03% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::52-55 17 0.27% 96.31% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::56-59 4 0.06% 96.37% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::60-63 8 0.13% 96.50% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-67 160 2.58% 99.08% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::68-71 2 0.03% 99.11% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::72-75 4 0.06% 99.18% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::76-79 20 0.32% 99.50% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::80-83 1 0.02% 99.52% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::96-99 2 0.03% 99.55% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::100-103 4 0.06% 99.61% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::108-111 1 0.02% 99.63% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::112-115 3 0.05% 99.68% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::124-127 1 0.02% 99.69% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::128-131 8 0.13% 99.82% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::140-143 1 0.02% 99.84% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::144-147 1 0.02% 99.85% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::152-155 3 0.05% 99.90% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::156-159 3 0.05% 99.95% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::164-167 1 0.02% 99.97% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::168-171 1 0.02% 99.98% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::total 6204 # Writes before turning the bus around for reads 266system.physmem.totQLat 1827154250 # Total ticks spent queuing 267system.physmem.totMemAccLat 5015910500 # Total ticks spent from burst creation until serviced by the DRAM 268system.physmem.totBusLat 850335000 # Total ticks spent in databus transfers 269system.physmem.avgQLat 10743.73 # Average queueing delay per DRAM burst |
| 270system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 270system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 271system.physmem.avgMemAccLat 28693.87 # Average memory access latency per DRAM burst 272system.physmem.avgRdBW 3.82 # Average DRAM read bandwidth in MiByte/s 273system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s 274system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s 275system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s | 271system.physmem.avgMemAccLat 29493.73 # Average memory access latency per DRAM burst 272system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s 273system.physmem.avgWrBW 2.79 # Average achieved write bandwidth in MiByte/s 274system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s 275system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s |
| 276system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 277system.physmem.busUtil 0.05 # Data bus utilization in percentage 278system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 279system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 280system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing | 276system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 277system.physmem.busUtil 0.05 # Data bus utilization in percentage 278system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 279system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 280system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing |
| 281system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing 282system.physmem.readRowHits 140376 # Number of row buffer hits during reads 283system.physmem.writeRowHits 94273 # Number of row buffer hits during writes 284system.physmem.readRowHitRate 82.49 # Row buffer hit rate for reads 285system.physmem.writeRowHitRate 75.30 # Row buffer hit rate for writes 286system.physmem.avgGap 9527936.25 # Average gap between requests 287system.physmem.pageHitRate 79.44 # Row buffer hit rate, read and write combined 288system.physmem_0.actEnergy 240143400 # Energy for activate commands per rank (pJ) 289system.physmem_0.preEnergy 131030625 # Energy for precharge commands per rank (pJ) 290system.physmem_0.readEnergy 698115600 # Energy for read commands per rank (pJ) 291system.physmem_0.writeEnergy 419158800 # Energy for write commands per rank (pJ) 292system.physmem_0.refreshEnergy 186321127200 # Energy for refresh commands per rank (pJ) 293system.physmem_0.actBackEnergy 83459244105 # Energy for active background per rank (pJ) 294system.physmem_0.preBackEnergy 1638379332000 # Energy for precharge background per rank (pJ) 295system.physmem_0.totalEnergy 1909648151730 # Total energy per rank (pJ) 296system.physmem_0.averagePower 669.429846 # Core power per rank (mW) 297system.physmem_0.memoryStateTime::IDLE 2725453951250 # Time in different power states 298system.physmem_0.memoryStateTime::REF 95256200000 # Time in different power states | 281system.physmem.avgWrQLen 26.50 # Average write queue length when enqueuing 282system.physmem.readRowHits 139389 # Number of row buffer hits during reads 283system.physmem.writeRowHits 93694 # Number of row buffer hits during writes 284system.physmem.readRowHitRate 81.96 # Row buffer hit rate for reads 285system.physmem.writeRowHitRate 75.17 # Row buffer hit rate for writes 286system.physmem.avgGap 9568366.60 # Average gap between requests 287system.physmem.pageHitRate 79.09 # Row buffer hit rate, read and write combined 288system.physmem_0.actEnergy 240959880 # Energy for activate commands per rank (pJ) 289system.physmem_0.preEnergy 131476125 # Energy for precharge commands per rank (pJ) 290system.physmem_0.readEnergy 693724200 # Energy for read commands per rank (pJ) 291system.physmem_0.writeEnergy 413508240 # Energy for write commands per rank (pJ) 292system.physmem_0.refreshEnergy 186689833200 # Energy for refresh commands per rank (pJ) 293system.physmem_0.actBackEnergy 86986692810 # Energy for active background per rank (pJ) 294system.physmem_0.preBackEnergy 1638672097500 # Energy for precharge background per rank (pJ) 295system.physmem_0.totalEnergy 1913828291955 # Total energy per rank (pJ) 296system.physmem_0.averagePower 669.570205 # Core power per rank (mW) 297system.physmem_0.memoryStateTime::IDLE 2725916009250 # Time in different power states 298system.physmem_0.memoryStateTime::REF 95444700000 # Time in different power states |
| 299system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 299system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 300system.physmem_0.memoryStateTime::ACT 31938521250 # Time in different power states | 300system.physmem_0.memoryStateTime::ACT 36932994500 # Time in different power states |
| 301system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 301system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 302system.physmem_1.actEnergy 218680560 # Energy for activate commands per rank (pJ) 303system.physmem_1.preEnergy 119319750 # Energy for precharge commands per rank (pJ) 304system.physmem_1.readEnergy 629202600 # Energy for read commands per rank (pJ) 305system.physmem_1.writeEnergy 391949280 # Energy for write commands per rank (pJ) 306system.physmem_1.refreshEnergy 186321127200 # Energy for refresh commands per rank (pJ) 307system.physmem_1.actBackEnergy 82079606700 # Energy for active background per rank (pJ) 308system.physmem_1.preBackEnergy 1639589540250 # Energy for precharge background per rank (pJ) 309system.physmem_1.totalEnergy 1909349426340 # Total energy per rank (pJ) 310system.physmem_1.averagePower 669.325127 # Core power per rank (mW) 311system.physmem_1.memoryStateTime::IDLE 2727485699500 # Time in different power states 312system.physmem_1.memoryStateTime::REF 95256200000 # Time in different power states | 302system.physmem_1.actEnergy 224789040 # Energy for activate commands per rank (pJ) 303system.physmem_1.preEnergy 122652750 # Energy for precharge commands per rank (pJ) 304system.physmem_1.readEnergy 632790600 # Energy for read commands per rank (pJ) 305system.physmem_1.writeEnergy 394055280 # Energy for write commands per rank (pJ) 306system.physmem_1.refreshEnergy 186689833200 # Energy for refresh commands per rank (pJ) 307system.physmem_1.actBackEnergy 85302372735 # Energy for active background per rank (pJ) 308system.physmem_1.preBackEnergy 1640149571250 # Energy for precharge background per rank (pJ) 309system.physmem_1.totalEnergy 1913516064855 # Total energy per rank (pJ) 310system.physmem_1.averagePower 669.460970 # Core power per rank (mW) 311system.physmem_1.memoryStateTime::IDLE 2728391286000 # Time in different power states 312system.physmem_1.memoryStateTime::REF 95444700000 # Time in different power states |
| 313system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 313system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 314system.physmem_1.memoryStateTime::ACT 29912992000 # Time in different power states | 314system.physmem_1.memoryStateTime::ACT 34465013500 # Time in different power states |
| 315system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 316system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory 317system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory 318system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory 319system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory 320system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 321system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 322system.realview.nvmem.bw_read::cpu.inst 179 # Total read bandwidth from this memory (bytes/s) 323system.realview.nvmem.bw_read::total 179 # Total read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_inst_read::cpu.inst 179 # Instruction read bandwidth from this memory (bytes/s) 325system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s) 327system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s) 328system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 329system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 330system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 331system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 332system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 333system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 315system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 316system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory 317system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory 318system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory 319system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory 320system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 321system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 322system.realview.nvmem.bw_read::cpu.inst 179 # Total read bandwidth from this memory (bytes/s) 323system.realview.nvmem.bw_read::total 179 # Total read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_inst_read::cpu.inst 179 # Instruction read bandwidth from this memory (bytes/s) 325system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s) 327system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s) 328system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 329system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 330system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 331system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 332system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 333system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 334system.cpu.branchPred.lookups 31017301 # Number of BP lookups 335system.cpu.branchPred.condPredicted 16826801 # Number of conditional branches predicted 336system.cpu.branchPred.condIncorrect 2510748 # Number of conditional branches incorrect 337system.cpu.branchPred.BTBLookups 18518050 # Number of BTB lookups 338system.cpu.branchPred.BTBHits 13329905 # Number of BTB hits | 334system.cpu.branchPred.lookups 31040865 # Number of BP lookups 335system.cpu.branchPred.condPredicted 16831531 # Number of conditional branches predicted 336system.cpu.branchPred.condIncorrect 2506988 # Number of conditional branches incorrect 337system.cpu.branchPred.BTBLookups 18486474 # Number of BTB lookups 338system.cpu.branchPred.BTBHits 13317466 # Number of BTB hits |
| 339system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 339system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 340system.cpu.branchPred.BTBHitPct 71.983308 # BTB Hit Percentage 341system.cpu.branchPred.usedRAS 7858653 # Number of times the RAS was used to get a target. 342system.cpu.branchPred.RASInCorrect 1517345 # Number of incorrect RAS predictions. | 340system.cpu.branchPred.BTBHitPct 72.038973 # BTB Hit Percentage 341system.cpu.branchPred.usedRAS 7868005 # Number of times the RAS was used to get a target. 342system.cpu.branchPred.RASInCorrect 1514854 # Number of incorrect RAS predictions. |
| 343system.cpu_clk_domain.clock 500 # Clock period in ticks 344system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 345system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 346system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 347system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 348system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 349system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 350system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 365system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 366system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 367system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 368system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 369system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 370system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 371system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 372system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 343system.cpu_clk_domain.clock 500 # Clock period in ticks 344system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 345system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 346system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 347system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 348system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 349system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 350system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 365system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 366system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 367system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 368system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 369system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 370system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 371system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 372system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 373system.cpu.dtb.walker.walks 65935 # Table walker walks requested 374system.cpu.dtb.walker.walksShort 65935 # Table walker walks initiated with short descriptors 375system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43131 # Level at which table walker walks with short descriptors terminate 376system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22804 # Level at which table walker walks with short descriptors terminate 377system.cpu.dtb.walker.walkWaitTime::samples 65935 # Table walker wait (enqueue to first request) latency 378system.cpu.dtb.walker.walkWaitTime::0 65935 100.00% 100.00% # Table walker wait (enqueue to first request) latency 379system.cpu.dtb.walker.walkWaitTime::total 65935 # Table walker wait (enqueue to first request) latency 380system.cpu.dtb.walker.walkCompletionTime::samples 7817 # Table walker service (enqueue to completion) latency 381system.cpu.dtb.walker.walkCompletionTime::mean 11967.954458 # Table walker service (enqueue to completion) latency 382system.cpu.dtb.walker.walkCompletionTime::gmean 9949.329384 # Table walker service (enqueue to completion) latency 383system.cpu.dtb.walker.walkCompletionTime::stdev 7404.205030 # Table walker service (enqueue to completion) latency 384system.cpu.dtb.walker.walkCompletionTime::0-16383 6115 78.23% 78.23% # Table walker service (enqueue to completion) latency 385system.cpu.dtb.walker.walkCompletionTime::16384-32767 1696 21.70% 99.92% # Table walker service (enqueue to completion) latency 386system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.97% # Table walker service (enqueue to completion) latency 387system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 388system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 389system.cpu.dtb.walker.walkCompletionTime::total 7817 # Table walker service (enqueue to completion) latency 390system.cpu.dtb.walker.walksPending::samples 260813000 # Table walker pending requests distribution 391system.cpu.dtb.walker.walksPending::0 260813000 100.00% 100.00% # Table walker pending requests distribution 392system.cpu.dtb.walker.walksPending::total 260813000 # Table walker pending requests distribution 393system.cpu.dtb.walker.walkPageSizes::4K 6422 82.15% 82.15% # Table walker page sizes translated 394system.cpu.dtb.walker.walkPageSizes::1M 1395 17.85% 100.00% # Table walker page sizes translated 395system.cpu.dtb.walker.walkPageSizes::total 7817 # Table walker page sizes translated 396system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 65935 # Table walker requests started/completed, data/inst | 373system.cpu.dtb.walker.walks 66489 # Table walker walks requested 374system.cpu.dtb.walker.walksShort 66489 # Table walker walks initiated with short descriptors 375system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43580 # Level at which table walker walks with short descriptors terminate 376system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22909 # Level at which table walker walks with short descriptors terminate 377system.cpu.dtb.walker.walkWaitTime::samples 66489 # Table walker wait (enqueue to first request) latency 378system.cpu.dtb.walker.walkWaitTime::0 66489 100.00% 100.00% # Table walker wait (enqueue to first request) latency 379system.cpu.dtb.walker.walkWaitTime::total 66489 # Table walker wait (enqueue to first request) latency 380system.cpu.dtb.walker.walkCompletionTime::samples 7766 # Table walker service (enqueue to completion) latency 381system.cpu.dtb.walker.walkCompletionTime::mean 12735.320628 # Table walker service (enqueue to completion) latency 382system.cpu.dtb.walker.walkCompletionTime::gmean 10552.887084 # Table walker service (enqueue to completion) latency 383system.cpu.dtb.walker.walkCompletionTime::stdev 8498.851872 # Table walker service (enqueue to completion) latency 384system.cpu.dtb.walker.walkCompletionTime::0-32767 7759 99.91% 99.91% # Table walker service (enqueue to completion) latency 385system.cpu.dtb.walker.walkCompletionTime::131072-163839 6 0.08% 99.99% # Table walker service (enqueue to completion) latency 386system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 387system.cpu.dtb.walker.walkCompletionTime::total 7766 # Table walker service (enqueue to completion) latency 388system.cpu.dtb.walker.walksPending::samples 513949000 # Table walker pending requests distribution 389system.cpu.dtb.walker.walksPending::0 513949000 100.00% 100.00% # Table walker pending requests distribution 390system.cpu.dtb.walker.walksPending::total 513949000 # Table walker pending requests distribution 391system.cpu.dtb.walker.walkPageSizes::4K 6383 82.19% 82.19% # Table walker page sizes translated 392system.cpu.dtb.walker.walkPageSizes::1M 1383 17.81% 100.00% # Table walker page sizes translated 393system.cpu.dtb.walker.walkPageSizes::total 7766 # Table walker page sizes translated 394system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66489 # Table walker requests started/completed, data/inst |
| 397system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 395system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 398system.cpu.dtb.walker.walkRequestOrigin_Requested::total 65935 # Table walker requests started/completed, data/inst 399system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7817 # Table walker requests started/completed, data/inst | 396system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66489 # Table walker requests started/completed, data/inst 397system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7766 # Table walker requests started/completed, data/inst |
| 400system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 398system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 401system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7817 # Table walker requests started/completed, data/inst 402system.cpu.dtb.walker.walkRequestOrigin::total 73752 # Table walker requests started/completed, data/inst | 399system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7766 # Table walker requests started/completed, data/inst 400system.cpu.dtb.walker.walkRequestOrigin::total 74255 # Table walker requests started/completed, data/inst |
| 403system.cpu.dtb.inst_hits 0 # ITB inst hits 404system.cpu.dtb.inst_misses 0 # ITB inst misses | 401system.cpu.dtb.inst_hits 0 # ITB inst hits 402system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 405system.cpu.dtb.read_hits 24760096 # DTB read hits 406system.cpu.dtb.read_misses 58949 # DTB read misses 407system.cpu.dtb.write_hits 19444061 # DTB write hits 408system.cpu.dtb.write_misses 6986 # DTB write misses | 403system.cpu.dtb.read_hits 24754555 # DTB read hits 404system.cpu.dtb.read_misses 59253 # DTB read misses 405system.cpu.dtb.write_hits 19441053 # DTB write hits 406system.cpu.dtb.write_misses 7236 # DTB write misses |
| 409system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 410system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 411system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 412system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 407system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 408system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 409system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 410system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 413system.cpu.dtb.flush_entries 4353 # Number of entries that have been flushed from TLB 414system.cpu.dtb.align_faults 1337 # Number of TLB faults due to alignment restrictions 415system.cpu.dtb.prefetch_faults 1780 # Number of TLB faults due to prefetch | 411system.cpu.dtb.flush_entries 4351 # Number of entries that have been flushed from TLB 412system.cpu.dtb.align_faults 1268 # Number of TLB faults due to alignment restrictions 413system.cpu.dtb.prefetch_faults 1795 # Number of TLB faults due to prefetch |
| 416system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 414system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 417system.cpu.dtb.perms_faults 739 # Number of TLB faults due to permissions restrictions 418system.cpu.dtb.read_accesses 24819045 # DTB read accesses 419system.cpu.dtb.write_accesses 19451047 # DTB write accesses | 415system.cpu.dtb.perms_faults 764 # Number of TLB faults due to permissions restrictions 416system.cpu.dtb.read_accesses 24813808 # DTB read accesses 417system.cpu.dtb.write_accesses 19448289 # DTB write accesses |
| 420system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 418system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 421system.cpu.dtb.hits 44204157 # DTB hits 422system.cpu.dtb.misses 65935 # DTB misses 423system.cpu.dtb.accesses 44270092 # DTB accesses | 419system.cpu.dtb.hits 44195608 # DTB hits 420system.cpu.dtb.misses 66489 # DTB misses 421system.cpu.dtb.accesses 44262097 # DTB accesses |
| 424system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 425system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 426system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 427system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 428system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 429system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 430system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 431system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 445system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 446system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 447system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 448system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 449system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 450system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 451system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 452system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 422system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 423system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 424system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 425system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 426system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 427system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 428system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 429system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 443system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 444system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 445system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 446system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 447system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 448system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 449system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 450system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 453system.cpu.itb.walker.walks 5452 # Table walker walks requested 454system.cpu.itb.walker.walksShort 5452 # Table walker walks initiated with short descriptors 455system.cpu.itb.walker.walksShortTerminationLevel::Level1 318 # Level at which table walker walks with short descriptors terminate 456system.cpu.itb.walker.walksShortTerminationLevel::Level2 5134 # Level at which table walker walks with short descriptors terminate 457system.cpu.itb.walker.walkWaitTime::samples 5452 # Table walker wait (enqueue to first request) latency 458system.cpu.itb.walker.walkWaitTime::0 5452 100.00% 100.00% # Table walker wait (enqueue to first request) latency 459system.cpu.itb.walker.walkWaitTime::total 5452 # Table walker wait (enqueue to first request) latency 460system.cpu.itb.walker.walkCompletionTime::samples 3184 # Table walker service (enqueue to completion) latency 461system.cpu.itb.walker.walkCompletionTime::mean 12119.032663 # Table walker service (enqueue to completion) latency 462system.cpu.itb.walker.walkCompletionTime::gmean 10076.122020 # Table walker service (enqueue to completion) latency 463system.cpu.itb.walker.walkCompletionTime::stdev 7085.501487 # Table walker service (enqueue to completion) latency 464system.cpu.itb.walker.walkCompletionTime::0-8191 1309 41.11% 41.11% # Table walker service (enqueue to completion) latency 465system.cpu.itb.walker.walkCompletionTime::8192-16383 1160 36.43% 77.54% # Table walker service (enqueue to completion) latency 466system.cpu.itb.walker.walkCompletionTime::16384-24575 714 22.42% 99.97% # Table walker service (enqueue to completion) latency 467system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 468system.cpu.itb.walker.walkCompletionTime::total 3184 # Table walker service (enqueue to completion) latency 469system.cpu.itb.walker.walksPending::samples 260408500 # Table walker pending requests distribution 470system.cpu.itb.walker.walksPending::0 260408500 100.00% 100.00% # Table walker pending requests distribution 471system.cpu.itb.walker.walksPending::total 260408500 # Table walker pending requests distribution 472system.cpu.itb.walker.walkPageSizes::4K 2874 90.26% 90.26% # Table walker page sizes translated 473system.cpu.itb.walker.walkPageSizes::1M 310 9.74% 100.00% # Table walker page sizes translated 474system.cpu.itb.walker.walkPageSizes::total 3184 # Table walker page sizes translated | 451system.cpu.itb.walker.walks 5448 # Table walker walks requested 452system.cpu.itb.walker.walksShort 5448 # Table walker walks initiated with short descriptors 453system.cpu.itb.walker.walksShortTerminationLevel::Level1 320 # Level at which table walker walks with short descriptors terminate 454system.cpu.itb.walker.walksShortTerminationLevel::Level2 5128 # Level at which table walker walks with short descriptors terminate 455system.cpu.itb.walker.walkWaitTime::samples 5448 # Table walker wait (enqueue to first request) latency 456system.cpu.itb.walker.walkWaitTime::0 5448 100.00% 100.00% # Table walker wait (enqueue to first request) latency 457system.cpu.itb.walker.walkWaitTime::total 5448 # Table walker wait (enqueue to first request) latency 458system.cpu.itb.walker.walkCompletionTime::samples 3191 # Table walker service (enqueue to completion) latency 459system.cpu.itb.walker.walkCompletionTime::mean 12717.173300 # Table walker service (enqueue to completion) latency 460system.cpu.itb.walker.walkCompletionTime::gmean 10597.999219 # Table walker service (enqueue to completion) latency 461system.cpu.itb.walker.walkCompletionTime::stdev 7372.723577 # Table walker service (enqueue to completion) latency 462system.cpu.itb.walker.walkCompletionTime::0-16383 2455 76.94% 76.94% # Table walker service (enqueue to completion) latency 463system.cpu.itb.walker.walkCompletionTime::16384-32767 735 23.03% 99.97% # Table walker service (enqueue to completion) latency 464system.cpu.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency 465system.cpu.itb.walker.walkCompletionTime::total 3191 # Table walker service (enqueue to completion) latency 466system.cpu.itb.walker.walksPending::samples 513294500 # Table walker pending requests distribution 467system.cpu.itb.walker.walksPending::0 513294500 100.00% 100.00% # Table walker pending requests distribution 468system.cpu.itb.walker.walksPending::total 513294500 # Table walker pending requests distribution 469system.cpu.itb.walker.walkPageSizes::4K 2881 90.29% 90.29% # Table walker page sizes translated 470system.cpu.itb.walker.walkPageSizes::1M 310 9.71% 100.00% # Table walker page sizes translated 471system.cpu.itb.walker.walkPageSizes::total 3191 # Table walker page sizes translated |
| 475system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 472system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 476system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5452 # Table walker requests started/completed, data/inst 477system.cpu.itb.walker.walkRequestOrigin_Requested::total 5452 # Table walker requests started/completed, data/inst | 473system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5448 # Table walker requests started/completed, data/inst 474system.cpu.itb.walker.walkRequestOrigin_Requested::total 5448 # Table walker requests started/completed, data/inst |
| 478system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 475system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 479system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3184 # Table walker requests started/completed, data/inst 480system.cpu.itb.walker.walkRequestOrigin_Completed::total 3184 # Table walker requests started/completed, data/inst 481system.cpu.itb.walker.walkRequestOrigin::total 8636 # Table walker requests started/completed, data/inst 482system.cpu.itb.inst_hits 57598025 # ITB inst hits 483system.cpu.itb.inst_misses 5452 # ITB inst misses | 476system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3191 # Table walker requests started/completed, data/inst 477system.cpu.itb.walker.walkRequestOrigin_Completed::total 3191 # Table walker requests started/completed, data/inst 478system.cpu.itb.walker.walkRequestOrigin::total 8639 # Table walker requests started/completed, data/inst 479system.cpu.itb.inst_hits 57598121 # ITB inst hits 480system.cpu.itb.inst_misses 5448 # ITB inst misses |
| 484system.cpu.itb.read_hits 0 # DTB read hits 485system.cpu.itb.read_misses 0 # DTB read misses 486system.cpu.itb.write_hits 0 # DTB write hits 487system.cpu.itb.write_misses 0 # DTB write misses 488system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 489system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 490system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 491system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 481system.cpu.itb.read_hits 0 # DTB read hits 482system.cpu.itb.read_misses 0 # DTB read misses 483system.cpu.itb.write_hits 0 # DTB write hits 484system.cpu.itb.write_misses 0 # DTB write misses 485system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 486system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 487system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 488system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 492system.cpu.itb.flush_entries 2973 # Number of entries that have been flushed from TLB | 489system.cpu.itb.flush_entries 2979 # Number of entries that have been flushed from TLB |
| 493system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 494system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 495system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 490system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 491system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 492system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 496system.cpu.itb.perms_faults 8340 # Number of TLB faults due to permissions restrictions | 493system.cpu.itb.perms_faults 8499 # Number of TLB faults due to permissions restrictions |
| 497system.cpu.itb.read_accesses 0 # DTB read accesses 498system.cpu.itb.write_accesses 0 # DTB write accesses | 494system.cpu.itb.read_accesses 0 # DTB read accesses 495system.cpu.itb.write_accesses 0 # DTB write accesses |
| 499system.cpu.itb.inst_accesses 57603477 # ITB inst accesses 500system.cpu.itb.hits 57598025 # DTB hits 501system.cpu.itb.misses 5452 # DTB misses 502system.cpu.itb.accesses 57603477 # DTB accesses 503system.cpu.numCycles 315393196 # number of cpu cycles simulated | 496system.cpu.itb.inst_accesses 57603569 # ITB inst accesses 497system.cpu.itb.hits 57598121 # DTB hits 498system.cpu.itb.misses 5448 # DTB misses 499system.cpu.itb.accesses 57603569 # DTB accesses 500system.cpu.numCycles 332010047 # number of cpu cycles simulated |
| 504system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 505system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 501system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 502system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 506system.cpu.committedInsts 112040950 # Number of instructions committed 507system.cpu.committedOps 135468925 # Number of ops (including micro ops) committed 508system.cpu.discardedOps 7774524 # Number of ops (including micro ops) which were discarded before commit 509system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching 510system.cpu.quiesceCycles 5389977386 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 511system.cpu.cpi 2.814981 # CPI: cycles per instruction 512system.cpu.ipc 0.355242 # IPC: instructions per cycle | 503system.cpu.committedInsts 112003872 # Number of instructions committed 504system.cpu.committedOps 135422492 # Number of ops (including micro ops) committed 505system.cpu.discardedOps 7777324 # Number of ops (including micro ops) which were discarded before commit 506system.cpu.numFetchSuspends 3034 # Number of times Execute suspended instruction fetching 507system.cpu.quiesceCycles 5384653012 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 508system.cpu.cpi 2.964273 # CPI: cycles per instruction 509system.cpu.ipc 0.337351 # IPC: instructions per cycle |
| 513system.cpu.kern.inst.arm 0 # number of arm instructions executed | 510system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 514system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed 515system.cpu.tickCycles 227419103 # Number of cycles that the object actually ticked 516system.cpu.idleCycles 87974093 # Total number of cycles that the object has spent stopped 517system.cpu.dcache.tags.replacements 843754 # number of replacements 518system.cpu.dcache.tags.tagsinuse 511.948230 # Cycle average of tags in use 519system.cpu.dcache.tags.total_refs 42602633 # Total number of references to valid blocks. 520system.cpu.dcache.tags.sampled_refs 844266 # Sample count of references to valid blocks. 521system.cpu.dcache.tags.avg_refs 50.461150 # Average number of references to valid blocks. 522system.cpu.dcache.tags.warmup_cycle 310642500 # Cycle when the warmup percentage was hit. 523system.cpu.dcache.tags.occ_blocks::cpu.data 511.948230 # Average occupied blocks per requestor 524system.cpu.dcache.tags.occ_percent::cpu.data 0.999899 # Average percentage of cache occupancy 525system.cpu.dcache.tags.occ_percent::total 0.999899 # Average percentage of cache occupancy | 511system.cpu.kern.inst.quiesce 3034 # number of quiesce instructions executed 512system.cpu.tickCycles 227998615 # Number of cycles that the object actually ticked 513system.cpu.idleCycles 104011432 # Total number of cycles that the object has spent stopped 514system.cpu.dcache.tags.replacements 840949 # number of replacements 515system.cpu.dcache.tags.tagsinuse 511.900791 # Cycle average of tags in use 516system.cpu.dcache.tags.total_refs 42597434 # Total number of references to valid blocks. 517system.cpu.dcache.tags.sampled_refs 841461 # Sample count of references to valid blocks. 518system.cpu.dcache.tags.avg_refs 50.623183 # Average number of references to valid blocks. 519system.cpu.dcache.tags.warmup_cycle 590729500 # Cycle when the warmup percentage was hit. 520system.cpu.dcache.tags.occ_blocks::cpu.data 511.900791 # Average occupied blocks per requestor 521system.cpu.dcache.tags.occ_percent::cpu.data 0.999806 # Average percentage of cache occupancy 522system.cpu.dcache.tags.occ_percent::total 0.999806 # Average percentage of cache occupancy |
| 526system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 523system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 527system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 528system.cpu.dcache.tags.age_task_id_blocks_1024::1 358 # Occupied blocks per task id 529system.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id | 524system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 525system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id 526system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id |
| 530system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 527system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 531system.cpu.dcache.tags.tag_accesses 176183318 # Number of tag accesses 532system.cpu.dcache.tags.data_accesses 176183318 # Number of data accesses 533system.cpu.dcache.ReadReq_hits::cpu.data 23061882 # number of ReadReq hits 534system.cpu.dcache.ReadReq_hits::total 23061882 # number of ReadReq hits 535system.cpu.dcache.WriteReq_hits::cpu.data 18277764 # number of WriteReq hits 536system.cpu.dcache.WriteReq_hits::total 18277764 # number of WriteReq hits 537system.cpu.dcache.SoftPFReq_hits::cpu.data 356325 # number of SoftPFReq hits 538system.cpu.dcache.SoftPFReq_hits::total 356325 # number of SoftPFReq hits 539system.cpu.dcache.LoadLockedReq_hits::cpu.data 443565 # number of LoadLockedReq hits 540system.cpu.dcache.LoadLockedReq_hits::total 443565 # number of LoadLockedReq hits 541system.cpu.dcache.StoreCondReq_hits::cpu.data 460145 # number of StoreCondReq hits 542system.cpu.dcache.StoreCondReq_hits::total 460145 # number of StoreCondReq hits 543system.cpu.dcache.demand_hits::cpu.data 41339646 # number of demand (read+write) hits 544system.cpu.dcache.demand_hits::total 41339646 # number of demand (read+write) hits 545system.cpu.dcache.overall_hits::cpu.data 41695971 # number of overall hits 546system.cpu.dcache.overall_hits::total 41695971 # number of overall hits 547system.cpu.dcache.ReadReq_misses::cpu.data 494235 # number of ReadReq misses 548system.cpu.dcache.ReadReq_misses::total 494235 # number of ReadReq misses 549system.cpu.dcache.WriteReq_misses::cpu.data 548281 # number of WriteReq misses 550system.cpu.dcache.WriteReq_misses::total 548281 # number of WriteReq misses 551system.cpu.dcache.SoftPFReq_misses::cpu.data 170165 # number of SoftPFReq misses 552system.cpu.dcache.SoftPFReq_misses::total 170165 # number of SoftPFReq misses 553system.cpu.dcache.LoadLockedReq_misses::cpu.data 22392 # number of LoadLockedReq misses 554system.cpu.dcache.LoadLockedReq_misses::total 22392 # number of LoadLockedReq misses | 528system.cpu.dcache.tags.tag_accesses 176149332 # Number of tag accesses 529system.cpu.dcache.tags.data_accesses 176149332 # Number of data accesses 530system.cpu.dcache.ReadReq_hits::cpu.data 23058407 # number of ReadReq hits 531system.cpu.dcache.ReadReq_hits::total 23058407 # number of ReadReq hits 532system.cpu.dcache.WriteReq_hits::cpu.data 18275243 # number of WriteReq hits 533system.cpu.dcache.WriteReq_hits::total 18275243 # number of WriteReq hits 534system.cpu.dcache.SoftPFReq_hits::cpu.data 356879 # number of SoftPFReq hits 535system.cpu.dcache.SoftPFReq_hits::total 356879 # number of SoftPFReq hits 536system.cpu.dcache.LoadLockedReq_hits::cpu.data 443776 # number of LoadLockedReq hits 537system.cpu.dcache.LoadLockedReq_hits::total 443776 # number of LoadLockedReq hits 538system.cpu.dcache.StoreCondReq_hits::cpu.data 460246 # number of StoreCondReq hits 539system.cpu.dcache.StoreCondReq_hits::total 460246 # number of StoreCondReq hits 540system.cpu.dcache.demand_hits::cpu.data 41333650 # number of demand (read+write) hits 541system.cpu.dcache.demand_hits::total 41333650 # number of demand (read+write) hits 542system.cpu.dcache.overall_hits::cpu.data 41690529 # number of overall hits 543system.cpu.dcache.overall_hits::total 41690529 # number of overall hits 544system.cpu.dcache.ReadReq_misses::cpu.data 492651 # number of ReadReq misses 545system.cpu.dcache.ReadReq_misses::total 492651 # number of ReadReq misses 546system.cpu.dcache.WriteReq_misses::cpu.data 547770 # number of WriteReq misses 547system.cpu.dcache.WriteReq_misses::total 547770 # number of WriteReq misses 548system.cpu.dcache.SoftPFReq_misses::cpu.data 169693 # number of SoftPFReq misses 549system.cpu.dcache.SoftPFReq_misses::total 169693 # number of SoftPFReq misses 550system.cpu.dcache.LoadLockedReq_misses::cpu.data 22295 # number of LoadLockedReq misses 551system.cpu.dcache.LoadLockedReq_misses::total 22295 # number of LoadLockedReq misses |
| 555system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 556system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses | 552system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 553system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses |
| 557system.cpu.dcache.demand_misses::cpu.data 1042516 # number of demand (read+write) misses 558system.cpu.dcache.demand_misses::total 1042516 # number of demand (read+write) misses 559system.cpu.dcache.overall_misses::cpu.data 1212681 # number of overall misses 560system.cpu.dcache.overall_misses::total 1212681 # number of overall misses 561system.cpu.dcache.ReadReq_miss_latency::cpu.data 7291153500 # number of ReadReq miss cycles 562system.cpu.dcache.ReadReq_miss_latency::total 7291153500 # number of ReadReq miss cycles 563system.cpu.dcache.WriteReq_miss_latency::cpu.data 23268838480 # number of WriteReq miss cycles 564system.cpu.dcache.WriteReq_miss_latency::total 23268838480 # number of WriteReq miss cycles 565system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 283155000 # number of LoadLockedReq miss cycles 566system.cpu.dcache.LoadLockedReq_miss_latency::total 283155000 # number of LoadLockedReq miss cycles | 554system.cpu.dcache.demand_misses::cpu.data 1040421 # number of demand (read+write) misses 555system.cpu.dcache.demand_misses::total 1040421 # number of demand (read+write) misses 556system.cpu.dcache.overall_misses::cpu.data 1210114 # number of overall misses 557system.cpu.dcache.overall_misses::total 1210114 # number of overall misses 558system.cpu.dcache.ReadReq_miss_latency::cpu.data 8002189000 # number of ReadReq miss cycles 559system.cpu.dcache.ReadReq_miss_latency::total 8002189000 # number of ReadReq miss cycles 560system.cpu.dcache.WriteReq_miss_latency::cpu.data 35630203980 # number of WriteReq miss cycles 561system.cpu.dcache.WriteReq_miss_latency::total 35630203980 # number of WriteReq miss cycles 562system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 292207000 # number of LoadLockedReq miss cycles 563system.cpu.dcache.LoadLockedReq_miss_latency::total 292207000 # number of LoadLockedReq miss cycles |
| 567system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles 568system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles | 564system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles 565system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles |
| 569system.cpu.dcache.demand_miss_latency::cpu.data 30559991980 # number of demand (read+write) miss cycles 570system.cpu.dcache.demand_miss_latency::total 30559991980 # number of demand (read+write) miss cycles 571system.cpu.dcache.overall_miss_latency::cpu.data 30559991980 # number of overall miss cycles 572system.cpu.dcache.overall_miss_latency::total 30559991980 # number of overall miss cycles 573system.cpu.dcache.ReadReq_accesses::cpu.data 23556117 # number of ReadReq accesses(hits+misses) 574system.cpu.dcache.ReadReq_accesses::total 23556117 # number of ReadReq accesses(hits+misses) 575system.cpu.dcache.WriteReq_accesses::cpu.data 18826045 # number of WriteReq accesses(hits+misses) 576system.cpu.dcache.WriteReq_accesses::total 18826045 # number of WriteReq accesses(hits+misses) 577system.cpu.dcache.SoftPFReq_accesses::cpu.data 526490 # number of SoftPFReq accesses(hits+misses) 578system.cpu.dcache.SoftPFReq_accesses::total 526490 # number of SoftPFReq accesses(hits+misses) 579system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465957 # number of LoadLockedReq accesses(hits+misses) 580system.cpu.dcache.LoadLockedReq_accesses::total 465957 # number of LoadLockedReq accesses(hits+misses) 581system.cpu.dcache.StoreCondReq_accesses::cpu.data 460147 # number of StoreCondReq accesses(hits+misses) 582system.cpu.dcache.StoreCondReq_accesses::total 460147 # number of StoreCondReq accesses(hits+misses) 583system.cpu.dcache.demand_accesses::cpu.data 42382162 # number of demand (read+write) accesses 584system.cpu.dcache.demand_accesses::total 42382162 # number of demand (read+write) accesses 585system.cpu.dcache.overall_accesses::cpu.data 42908652 # number of overall (read+write) accesses 586system.cpu.dcache.overall_accesses::total 42908652 # number of overall (read+write) accesses 587system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020981 # miss rate for ReadReq accesses 588system.cpu.dcache.ReadReq_miss_rate::total 0.020981 # miss rate for ReadReq accesses 589system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029124 # miss rate for WriteReq accesses 590system.cpu.dcache.WriteReq_miss_rate::total 0.029124 # miss rate for WriteReq accesses 591system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.323207 # miss rate for SoftPFReq accesses 592system.cpu.dcache.SoftPFReq_miss_rate::total 0.323207 # miss rate for SoftPFReq accesses 593system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048056 # miss rate for LoadLockedReq accesses 594system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048056 # miss rate for LoadLockedReq accesses | 566system.cpu.dcache.demand_miss_latency::cpu.data 43632392980 # number of demand (read+write) miss cycles 567system.cpu.dcache.demand_miss_latency::total 43632392980 # number of demand (read+write) miss cycles 568system.cpu.dcache.overall_miss_latency::cpu.data 43632392980 # number of overall miss cycles 569system.cpu.dcache.overall_miss_latency::total 43632392980 # number of overall miss cycles 570system.cpu.dcache.ReadReq_accesses::cpu.data 23551058 # number of ReadReq accesses(hits+misses) 571system.cpu.dcache.ReadReq_accesses::total 23551058 # number of ReadReq accesses(hits+misses) 572system.cpu.dcache.WriteReq_accesses::cpu.data 18823013 # number of WriteReq accesses(hits+misses) 573system.cpu.dcache.WriteReq_accesses::total 18823013 # number of WriteReq accesses(hits+misses) 574system.cpu.dcache.SoftPFReq_accesses::cpu.data 526572 # number of SoftPFReq accesses(hits+misses) 575system.cpu.dcache.SoftPFReq_accesses::total 526572 # number of SoftPFReq accesses(hits+misses) 576system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466071 # number of LoadLockedReq accesses(hits+misses) 577system.cpu.dcache.LoadLockedReq_accesses::total 466071 # number of LoadLockedReq accesses(hits+misses) 578system.cpu.dcache.StoreCondReq_accesses::cpu.data 460248 # number of StoreCondReq accesses(hits+misses) 579system.cpu.dcache.StoreCondReq_accesses::total 460248 # number of StoreCondReq accesses(hits+misses) 580system.cpu.dcache.demand_accesses::cpu.data 42374071 # number of demand (read+write) accesses 581system.cpu.dcache.demand_accesses::total 42374071 # number of demand (read+write) accesses 582system.cpu.dcache.overall_accesses::cpu.data 42900643 # number of overall (read+write) accesses 583system.cpu.dcache.overall_accesses::total 42900643 # number of overall (read+write) accesses 584system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020918 # miss rate for ReadReq accesses 585system.cpu.dcache.ReadReq_miss_rate::total 0.020918 # miss rate for ReadReq accesses 586system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029101 # miss rate for WriteReq accesses 587system.cpu.dcache.WriteReq_miss_rate::total 0.029101 # miss rate for WriteReq accesses 588system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322260 # miss rate for SoftPFReq accesses 589system.cpu.dcache.SoftPFReq_miss_rate::total 0.322260 # miss rate for SoftPFReq accesses 590system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047836 # miss rate for LoadLockedReq accesses 591system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047836 # miss rate for LoadLockedReq accesses |
| 595system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 596system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses | 592system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 593system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses |
| 597system.cpu.dcache.demand_miss_rate::cpu.data 0.024598 # miss rate for demand accesses 598system.cpu.dcache.demand_miss_rate::total 0.024598 # miss rate for demand accesses 599system.cpu.dcache.overall_miss_rate::cpu.data 0.028262 # miss rate for overall accesses 600system.cpu.dcache.overall_miss_rate::total 0.028262 # miss rate for overall accesses 601system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14752.402197 # average ReadReq miss latency 602system.cpu.dcache.ReadReq_avg_miss_latency::total 14752.402197 # average ReadReq miss latency 603system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42439.622165 # average WriteReq miss latency 604system.cpu.dcache.WriteReq_avg_miss_latency::total 42439.622165 # average WriteReq miss latency 605system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12645.364416 # average LoadLockedReq miss latency 606system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12645.364416 # average LoadLockedReq miss latency | 594system.cpu.dcache.demand_miss_rate::cpu.data 0.024553 # miss rate for demand accesses 595system.cpu.dcache.demand_miss_rate::total 0.024553 # miss rate for demand accesses 596system.cpu.dcache.overall_miss_rate::cpu.data 0.028207 # miss rate for overall accesses 597system.cpu.dcache.overall_miss_rate::total 0.028207 # miss rate for overall accesses 598system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16243.119368 # average ReadReq miss latency 599system.cpu.dcache.ReadReq_avg_miss_latency::total 16243.119368 # average ReadReq miss latency 600system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65045.920697 # average WriteReq miss latency 601system.cpu.dcache.WriteReq_avg_miss_latency::total 65045.920697 # average WriteReq miss latency 602system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13106.391568 # average LoadLockedReq miss latency 603system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13106.391568 # average LoadLockedReq miss latency |
| 607system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83500 # average StoreCondReq miss latency 608system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83500 # average StoreCondReq miss latency | 604system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83500 # average StoreCondReq miss latency 605system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83500 # average StoreCondReq miss latency |
| 609system.cpu.dcache.demand_avg_miss_latency::cpu.data 29313.691090 # average overall miss latency 610system.cpu.dcache.demand_avg_miss_latency::total 29313.691090 # average overall miss latency 611system.cpu.dcache.overall_avg_miss_latency::cpu.data 25200.355229 # average overall miss latency 612system.cpu.dcache.overall_avg_miss_latency::total 25200.355229 # average overall miss latency 613system.cpu.dcache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked | 606system.cpu.dcache.demand_avg_miss_latency::cpu.data 41937.247499 # average overall miss latency 607system.cpu.dcache.demand_avg_miss_latency::total 41937.247499 # average overall miss latency 608system.cpu.dcache.overall_avg_miss_latency::cpu.data 36056.431857 # average overall miss latency 609system.cpu.dcache.overall_avg_miss_latency::total 36056.431857 # average overall miss latency 610system.cpu.dcache.blocked_cycles::no_mshrs 277 # number of cycles access was blocked |
| 614system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 611system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 615system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked | 612system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked |
| 616system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 613system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 617system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.809524 # average number of cycles each access was blocked | 614system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.043478 # average number of cycles each access was blocked |
| 618system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 619system.cpu.dcache.fast_writes 0 # number of fast writes performed 620system.cpu.dcache.cache_copies 0 # number of cache copies performed | 615system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 616system.cpu.dcache.fast_writes 0 # number of fast writes performed 617system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 621system.cpu.dcache.writebacks::writebacks 699241 # number of writebacks 622system.cpu.dcache.writebacks::total 699241 # number of writebacks 623system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75816 # number of ReadReq MSHR hits 624system.cpu.dcache.ReadReq_mshr_hits::total 75816 # number of ReadReq MSHR hits 625system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249572 # number of WriteReq MSHR hits 626system.cpu.dcache.WriteReq_mshr_hits::total 249572 # number of WriteReq MSHR hits 627system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14161 # number of LoadLockedReq MSHR hits 628system.cpu.dcache.LoadLockedReq_mshr_hits::total 14161 # number of LoadLockedReq MSHR hits 629system.cpu.dcache.demand_mshr_hits::cpu.data 325388 # number of demand (read+write) MSHR hits 630system.cpu.dcache.demand_mshr_hits::total 325388 # number of demand (read+write) MSHR hits 631system.cpu.dcache.overall_mshr_hits::cpu.data 325388 # number of overall MSHR hits 632system.cpu.dcache.overall_mshr_hits::total 325388 # number of overall MSHR hits 633system.cpu.dcache.ReadReq_mshr_misses::cpu.data 418419 # number of ReadReq MSHR misses 634system.cpu.dcache.ReadReq_mshr_misses::total 418419 # number of ReadReq MSHR misses 635system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298709 # number of WriteReq MSHR misses 636system.cpu.dcache.WriteReq_mshr_misses::total 298709 # number of WriteReq MSHR misses 637system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121784 # number of SoftPFReq MSHR misses 638system.cpu.dcache.SoftPFReq_mshr_misses::total 121784 # number of SoftPFReq MSHR misses 639system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8231 # number of LoadLockedReq MSHR misses 640system.cpu.dcache.LoadLockedReq_mshr_misses::total 8231 # number of LoadLockedReq MSHR misses | 618system.cpu.dcache.writebacks::writebacks 698521 # number of writebacks 619system.cpu.dcache.writebacks::total 698521 # number of writebacks 620system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76580 # number of ReadReq MSHR hits 621system.cpu.dcache.ReadReq_mshr_hits::total 76580 # number of ReadReq MSHR hits 622system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249277 # number of WriteReq MSHR hits 623system.cpu.dcache.WriteReq_mshr_hits::total 249277 # number of WriteReq MSHR hits 624system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14066 # number of LoadLockedReq MSHR hits 625system.cpu.dcache.LoadLockedReq_mshr_hits::total 14066 # number of LoadLockedReq MSHR hits 626system.cpu.dcache.demand_mshr_hits::cpu.data 325857 # number of demand (read+write) MSHR hits 627system.cpu.dcache.demand_mshr_hits::total 325857 # number of demand (read+write) MSHR hits 628system.cpu.dcache.overall_mshr_hits::cpu.data 325857 # number of overall MSHR hits 629system.cpu.dcache.overall_mshr_hits::total 325857 # number of overall MSHR hits 630system.cpu.dcache.ReadReq_mshr_misses::cpu.data 416071 # number of ReadReq MSHR misses 631system.cpu.dcache.ReadReq_mshr_misses::total 416071 # number of ReadReq MSHR misses 632system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298493 # number of WriteReq MSHR misses 633system.cpu.dcache.WriteReq_mshr_misses::total 298493 # number of WriteReq MSHR misses 634system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121470 # number of SoftPFReq MSHR misses 635system.cpu.dcache.SoftPFReq_mshr_misses::total 121470 # number of SoftPFReq MSHR misses 636system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8229 # number of LoadLockedReq MSHR misses 637system.cpu.dcache.LoadLockedReq_mshr_misses::total 8229 # number of LoadLockedReq MSHR misses |
| 641system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 642system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses | 638system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 639system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses |
| 643system.cpu.dcache.demand_mshr_misses::cpu.data 717128 # number of demand (read+write) MSHR misses 644system.cpu.dcache.demand_mshr_misses::total 717128 # number of demand (read+write) MSHR misses 645system.cpu.dcache.overall_mshr_misses::cpu.data 838912 # number of overall MSHR misses 646system.cpu.dcache.overall_mshr_misses::total 838912 # number of overall MSHR misses | 640system.cpu.dcache.demand_mshr_misses::cpu.data 714564 # number of demand (read+write) MSHR misses 641system.cpu.dcache.demand_mshr_misses::total 714564 # number of demand (read+write) MSHR misses 642system.cpu.dcache.overall_mshr_misses::cpu.data 836034 # number of overall MSHR misses 643system.cpu.dcache.overall_mshr_misses::total 836034 # number of overall MSHR misses |
| 647system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable 648system.cpu.dcache.ReadReq_mshr_uncacheable::total 31128 # number of ReadReq MSHR uncacheable 649system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable 650system.cpu.dcache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable 651system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses 652system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses | 644system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable 645system.cpu.dcache.ReadReq_mshr_uncacheable::total 31128 # number of ReadReq MSHR uncacheable 646system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable 647system.cpu.dcache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable 648system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses 649system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses |
| 653system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5922558000 # number of ReadReq MSHR miss cycles 654system.cpu.dcache.ReadReq_mshr_miss_latency::total 5922558000 # number of ReadReq MSHR miss cycles 655system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12450120000 # number of WriteReq MSHR miss cycles 656system.cpu.dcache.WriteReq_mshr_miss_latency::total 12450120000 # number of WriteReq MSHR miss cycles 657system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1618736500 # number of SoftPFReq MSHR miss cycles 658system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1618736500 # number of SoftPFReq MSHR miss cycles 659system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 109455500 # number of LoadLockedReq MSHR miss cycles 660system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 109455500 # number of LoadLockedReq MSHR miss cycles | 650system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6493922500 # number of ReadReq MSHR miss cycles 651system.cpu.dcache.ReadReq_mshr_miss_latency::total 6493922500 # number of ReadReq MSHR miss cycles 652system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19218375500 # number of WriteReq MSHR miss cycles 653system.cpu.dcache.WriteReq_mshr_miss_latency::total 19218375500 # number of WriteReq MSHR miss cycles 654system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1715298500 # number of SoftPFReq MSHR miss cycles 655system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1715298500 # number of SoftPFReq MSHR miss cycles 656system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 114624000 # number of LoadLockedReq MSHR miss cycles 657system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 114624000 # number of LoadLockedReq MSHR miss cycles |
| 661system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165000 # number of StoreCondReq MSHR miss cycles 662system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165000 # number of StoreCondReq MSHR miss cycles | 658system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165000 # number of StoreCondReq MSHR miss cycles 659system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165000 # number of StoreCondReq MSHR miss cycles |
| 663system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18372678000 # number of demand (read+write) MSHR miss cycles 664system.cpu.dcache.demand_mshr_miss_latency::total 18372678000 # number of demand (read+write) MSHR miss cycles 665system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19991414500 # number of overall MSHR miss cycles 666system.cpu.dcache.overall_mshr_miss_latency::total 19991414500 # number of overall MSHR miss cycles 667system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5909069000 # number of ReadReq MSHR uncacheable cycles 668system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5909069000 # number of ReadReq MSHR uncacheable cycles 669system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4568816000 # number of WriteReq MSHR uncacheable cycles 670system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4568816000 # number of WriteReq MSHR uncacheable cycles 671system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10477885000 # number of overall MSHR uncacheable cycles 672system.cpu.dcache.overall_mshr_uncacheable_latency::total 10477885000 # number of overall MSHR uncacheable cycles 673system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017763 # mshr miss rate for ReadReq accesses 674system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017763 # mshr miss rate for ReadReq accesses 675system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015867 # mshr miss rate for WriteReq accesses 676system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015867 # mshr miss rate for WriteReq accesses 677system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231313 # mshr miss rate for SoftPFReq accesses 678system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231313 # mshr miss rate for SoftPFReq accesses 679system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017665 # mshr miss rate for LoadLockedReq accesses 680system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017665 # mshr miss rate for LoadLockedReq accesses | 660system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25712298000 # number of demand (read+write) MSHR miss cycles 661system.cpu.dcache.demand_mshr_miss_latency::total 25712298000 # number of demand (read+write) MSHR miss cycles 662system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27427596500 # number of overall MSHR miss cycles 663system.cpu.dcache.overall_mshr_miss_latency::total 27427596500 # number of overall MSHR miss cycles 664system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5937313500 # number of ReadReq MSHR uncacheable cycles 665system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5937313500 # number of ReadReq MSHR uncacheable cycles 666system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4787315000 # number of WriteReq MSHR uncacheable cycles 667system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4787315000 # number of WriteReq MSHR uncacheable cycles 668system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10724628500 # number of overall MSHR uncacheable cycles 669system.cpu.dcache.overall_mshr_uncacheable_latency::total 10724628500 # number of overall MSHR uncacheable cycles 670system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017667 # mshr miss rate for ReadReq accesses 671system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017667 # mshr miss rate for ReadReq accesses 672system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015858 # mshr miss rate for WriteReq accesses 673system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015858 # mshr miss rate for WriteReq accesses 674system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230681 # mshr miss rate for SoftPFReq accesses 675system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230681 # mshr miss rate for SoftPFReq accesses 676system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017656 # mshr miss rate for LoadLockedReq accesses 677system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017656 # mshr miss rate for LoadLockedReq accesses |
| 681system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 682system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses | 678system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 679system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses |
| 683system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016921 # mshr miss rate for demand accesses 684system.cpu.dcache.demand_mshr_miss_rate::total 0.016921 # mshr miss rate for demand accesses 685system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019551 # mshr miss rate for overall accesses 686system.cpu.dcache.overall_mshr_miss_rate::total 0.019551 # mshr miss rate for overall accesses 687system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14154.610570 # average ReadReq mshr miss latency 688system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14154.610570 # average ReadReq mshr miss latency 689system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41679.761909 # average WriteReq mshr miss latency 690system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41679.761909 # average WriteReq mshr miss latency 691system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13291.865105 # average SoftPFReq mshr miss latency 692system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13291.865105 # average SoftPFReq mshr miss latency 693system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13297.958936 # average LoadLockedReq mshr miss latency 694system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13297.958936 # average LoadLockedReq mshr miss latency | 680system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016863 # mshr miss rate for demand accesses 681system.cpu.dcache.demand_mshr_miss_rate::total 0.016863 # mshr miss rate for demand accesses 682system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019488 # mshr miss rate for overall accesses 683system.cpu.dcache.overall_mshr_miss_rate::total 0.019488 # mshr miss rate for overall accesses 684system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15607.726806 # average ReadReq mshr miss latency 685system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15607.726806 # average ReadReq mshr miss latency 686system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64384.677363 # average WriteReq mshr miss latency 687system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64384.677363 # average WriteReq mshr miss latency 688system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14121.169836 # average SoftPFReq mshr miss latency 689system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14121.169836 # average SoftPFReq mshr miss latency 690system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13929.274517 # average LoadLockedReq mshr miss latency 691system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13929.274517 # average LoadLockedReq mshr miss latency |
| 695system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82500 # average StoreCondReq mshr miss latency 696system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82500 # average StoreCondReq mshr miss latency | 692system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82500 # average StoreCondReq mshr miss latency 693system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82500 # average StoreCondReq mshr miss latency |
| 697system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25619.802880 # average overall mshr miss latency 698system.cpu.dcache.demand_avg_mshr_miss_latency::total 25619.802880 # average overall mshr miss latency 699system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23830.168719 # average overall mshr miss latency 700system.cpu.dcache.overall_avg_mshr_miss_latency::total 23830.168719 # average overall mshr miss latency 701system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189831.309432 # average ReadReq mshr uncacheable latency 702system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189831.309432 # average ReadReq mshr uncacheable latency 703system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165638.835515 # average WriteReq mshr uncacheable latency 704system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165638.835515 # average WriteReq mshr uncacheable latency 705system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178465.449405 # average overall mshr uncacheable latency 706system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178465.449405 # average overall mshr uncacheable latency | 694system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35983.198146 # average overall mshr miss latency 695system.cpu.dcache.demand_avg_mshr_miss_latency::total 35983.198146 # average overall mshr miss latency 696system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32806.795537 # average overall mshr miss latency 697system.cpu.dcache.overall_avg_mshr_miss_latency::total 32806.795537 # average overall mshr miss latency 698system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190738.675790 # average ReadReq mshr uncacheable latency 699system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190738.675790 # average ReadReq mshr uncacheable latency 700system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173560.345140 # average WriteReq mshr uncacheable latency 701system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173560.345140 # average WriteReq mshr uncacheable latency 702system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 182668.128630 # average overall mshr uncacheable latency 703system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 182668.128630 # average overall mshr uncacheable latency |
| 707system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 704system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 708system.cpu.icache.tags.replacements 2895998 # number of replacements 709system.cpu.icache.tags.tagsinuse 511.404759 # Cycle average of tags in use 710system.cpu.icache.tags.total_refs 54692690 # Total number of references to valid blocks. 711system.cpu.icache.tags.sampled_refs 2896510 # Sample count of references to valid blocks. 712system.cpu.icache.tags.avg_refs 18.882272 # Average number of references to valid blocks. 713system.cpu.icache.tags.warmup_cycle 15448784500 # Cycle when the warmup percentage was hit. 714system.cpu.icache.tags.occ_blocks::cpu.inst 511.404759 # Average occupied blocks per requestor 715system.cpu.icache.tags.occ_percent::cpu.inst 0.998837 # Average percentage of cache occupancy 716system.cpu.icache.tags.occ_percent::total 0.998837 # Average percentage of cache occupancy | 705system.cpu.icache.tags.replacements 2897329 # number of replacements 706system.cpu.icache.tags.tagsinuse 511.212489 # Cycle average of tags in use 707system.cpu.icache.tags.total_refs 54691304 # Total number of references to valid blocks. 708system.cpu.icache.tags.sampled_refs 2897841 # Sample count of references to valid blocks. 709system.cpu.icache.tags.avg_refs 18.873121 # Average number of references to valid blocks. 710system.cpu.icache.tags.warmup_cycle 18295812500 # Cycle when the warmup percentage was hit. 711system.cpu.icache.tags.occ_blocks::cpu.inst 511.212489 # Average occupied blocks per requestor 712system.cpu.icache.tags.occ_percent::cpu.inst 0.998462 # Average percentage of cache occupancy 713system.cpu.icache.tags.occ_percent::total 0.998462 # Average percentage of cache occupancy |
| 717system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 714system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 718system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id | 715system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id |
| 719system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id | 716system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id |
| 720system.cpu.icache.tags.age_task_id_blocks_1024::2 196 # Occupied blocks per task id | 717system.cpu.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id |
| 721system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 718system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 722system.cpu.icache.tags.tag_accesses 60485733 # Number of tag accesses 723system.cpu.icache.tags.data_accesses 60485733 # Number of data accesses 724system.cpu.icache.ReadReq_hits::cpu.inst 54692690 # number of ReadReq hits 725system.cpu.icache.ReadReq_hits::total 54692690 # number of ReadReq hits 726system.cpu.icache.demand_hits::cpu.inst 54692690 # number of demand (read+write) hits 727system.cpu.icache.demand_hits::total 54692690 # number of demand (read+write) hits 728system.cpu.icache.overall_hits::cpu.inst 54692690 # number of overall hits 729system.cpu.icache.overall_hits::total 54692690 # number of overall hits 730system.cpu.icache.ReadReq_misses::cpu.inst 2896522 # number of ReadReq misses 731system.cpu.icache.ReadReq_misses::total 2896522 # number of ReadReq misses 732system.cpu.icache.demand_misses::cpu.inst 2896522 # number of demand (read+write) misses 733system.cpu.icache.demand_misses::total 2896522 # number of demand (read+write) misses 734system.cpu.icache.overall_misses::cpu.inst 2896522 # number of overall misses 735system.cpu.icache.overall_misses::total 2896522 # number of overall misses 736system.cpu.icache.ReadReq_miss_latency::cpu.inst 39250501500 # number of ReadReq miss cycles 737system.cpu.icache.ReadReq_miss_latency::total 39250501500 # number of ReadReq miss cycles 738system.cpu.icache.demand_miss_latency::cpu.inst 39250501500 # number of demand (read+write) miss cycles 739system.cpu.icache.demand_miss_latency::total 39250501500 # number of demand (read+write) miss cycles 740system.cpu.icache.overall_miss_latency::cpu.inst 39250501500 # number of overall miss cycles 741system.cpu.icache.overall_miss_latency::total 39250501500 # number of overall miss cycles 742system.cpu.icache.ReadReq_accesses::cpu.inst 57589212 # number of ReadReq accesses(hits+misses) 743system.cpu.icache.ReadReq_accesses::total 57589212 # number of ReadReq accesses(hits+misses) 744system.cpu.icache.demand_accesses::cpu.inst 57589212 # number of demand (read+write) accesses 745system.cpu.icache.demand_accesses::total 57589212 # number of demand (read+write) accesses 746system.cpu.icache.overall_accesses::cpu.inst 57589212 # number of overall (read+write) accesses 747system.cpu.icache.overall_accesses::total 57589212 # number of overall (read+write) accesses 748system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050296 # miss rate for ReadReq accesses 749system.cpu.icache.ReadReq_miss_rate::total 0.050296 # miss rate for ReadReq accesses 750system.cpu.icache.demand_miss_rate::cpu.inst 0.050296 # miss rate for demand accesses 751system.cpu.icache.demand_miss_rate::total 0.050296 # miss rate for demand accesses 752system.cpu.icache.overall_miss_rate::cpu.inst 0.050296 # miss rate for overall accesses 753system.cpu.icache.overall_miss_rate::total 0.050296 # miss rate for overall accesses 754system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13550.907433 # average ReadReq miss latency 755system.cpu.icache.ReadReq_avg_miss_latency::total 13550.907433 # average ReadReq miss latency 756system.cpu.icache.demand_avg_miss_latency::cpu.inst 13550.907433 # average overall miss latency 757system.cpu.icache.demand_avg_miss_latency::total 13550.907433 # average overall miss latency 758system.cpu.icache.overall_avg_miss_latency::cpu.inst 13550.907433 # average overall miss latency 759system.cpu.icache.overall_avg_miss_latency::total 13550.907433 # average overall miss latency | 719system.cpu.icache.tags.tag_accesses 60487009 # Number of tag accesses 720system.cpu.icache.tags.data_accesses 60487009 # Number of data accesses 721system.cpu.icache.ReadReq_hits::cpu.inst 54691304 # number of ReadReq hits 722system.cpu.icache.ReadReq_hits::total 54691304 # number of ReadReq hits 723system.cpu.icache.demand_hits::cpu.inst 54691304 # number of demand (read+write) hits 724system.cpu.icache.demand_hits::total 54691304 # number of demand (read+write) hits 725system.cpu.icache.overall_hits::cpu.inst 54691304 # number of overall hits 726system.cpu.icache.overall_hits::total 54691304 # number of overall hits 727system.cpu.icache.ReadReq_misses::cpu.inst 2897853 # number of ReadReq misses 728system.cpu.icache.ReadReq_misses::total 2897853 # number of ReadReq misses 729system.cpu.icache.demand_misses::cpu.inst 2897853 # number of demand (read+write) misses 730system.cpu.icache.demand_misses::total 2897853 # number of demand (read+write) misses 731system.cpu.icache.overall_misses::cpu.inst 2897853 # number of overall misses 732system.cpu.icache.overall_misses::total 2897853 # number of overall misses 733system.cpu.icache.ReadReq_miss_latency::cpu.inst 40491792500 # number of ReadReq miss cycles 734system.cpu.icache.ReadReq_miss_latency::total 40491792500 # number of ReadReq miss cycles 735system.cpu.icache.demand_miss_latency::cpu.inst 40491792500 # number of demand (read+write) miss cycles 736system.cpu.icache.demand_miss_latency::total 40491792500 # number of demand (read+write) miss cycles 737system.cpu.icache.overall_miss_latency::cpu.inst 40491792500 # number of overall miss cycles 738system.cpu.icache.overall_miss_latency::total 40491792500 # number of overall miss cycles 739system.cpu.icache.ReadReq_accesses::cpu.inst 57589157 # number of ReadReq accesses(hits+misses) 740system.cpu.icache.ReadReq_accesses::total 57589157 # number of ReadReq accesses(hits+misses) 741system.cpu.icache.demand_accesses::cpu.inst 57589157 # number of demand (read+write) accesses 742system.cpu.icache.demand_accesses::total 57589157 # number of demand (read+write) accesses 743system.cpu.icache.overall_accesses::cpu.inst 57589157 # number of overall (read+write) accesses 744system.cpu.icache.overall_accesses::total 57589157 # number of overall (read+write) accesses 745system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050319 # miss rate for ReadReq accesses 746system.cpu.icache.ReadReq_miss_rate::total 0.050319 # miss rate for ReadReq accesses 747system.cpu.icache.demand_miss_rate::cpu.inst 0.050319 # miss rate for demand accesses 748system.cpu.icache.demand_miss_rate::total 0.050319 # miss rate for demand accesses 749system.cpu.icache.overall_miss_rate::cpu.inst 0.050319 # miss rate for overall accesses 750system.cpu.icache.overall_miss_rate::total 0.050319 # miss rate for overall accesses 751system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13973.031931 # average ReadReq miss latency 752system.cpu.icache.ReadReq_avg_miss_latency::total 13973.031931 # average ReadReq miss latency 753system.cpu.icache.demand_avg_miss_latency::cpu.inst 13973.031931 # average overall miss latency 754system.cpu.icache.demand_avg_miss_latency::total 13973.031931 # average overall miss latency 755system.cpu.icache.overall_avg_miss_latency::cpu.inst 13973.031931 # average overall miss latency 756system.cpu.icache.overall_avg_miss_latency::total 13973.031931 # average overall miss latency |
| 760system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 761system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 762system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 763system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 764system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 765system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 766system.cpu.icache.fast_writes 0 # number of fast writes performed 767system.cpu.icache.cache_copies 0 # number of cache copies performed | 757system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 758system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 759system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 760system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 761system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 762system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 763system.cpu.icache.fast_writes 0 # number of fast writes performed 764system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 768system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2896522 # number of ReadReq MSHR misses 769system.cpu.icache.ReadReq_mshr_misses::total 2896522 # number of ReadReq MSHR misses 770system.cpu.icache.demand_mshr_misses::cpu.inst 2896522 # number of demand (read+write) MSHR misses 771system.cpu.icache.demand_mshr_misses::total 2896522 # number of demand (read+write) MSHR misses 772system.cpu.icache.overall_mshr_misses::cpu.inst 2896522 # number of overall MSHR misses 773system.cpu.icache.overall_mshr_misses::total 2896522 # number of overall MSHR misses 774system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3191 # number of ReadReq MSHR uncacheable 775system.cpu.icache.ReadReq_mshr_uncacheable::total 3191 # number of ReadReq MSHR uncacheable 776system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3191 # number of overall MSHR uncacheable misses 777system.cpu.icache.overall_mshr_uncacheable_misses::total 3191 # number of overall MSHR uncacheable misses 778system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36353980500 # number of ReadReq MSHR miss cycles 779system.cpu.icache.ReadReq_mshr_miss_latency::total 36353980500 # number of ReadReq MSHR miss cycles 780system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36353980500 # number of demand (read+write) MSHR miss cycles 781system.cpu.icache.demand_mshr_miss_latency::total 36353980500 # number of demand (read+write) MSHR miss cycles 782system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36353980500 # number of overall MSHR miss cycles 783system.cpu.icache.overall_mshr_miss_latency::total 36353980500 # number of overall MSHR miss cycles 784system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 248718500 # number of ReadReq MSHR uncacheable cycles 785system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 248718500 # number of ReadReq MSHR uncacheable cycles 786system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 248718500 # number of overall MSHR uncacheable cycles 787system.cpu.icache.overall_mshr_uncacheable_latency::total 248718500 # number of overall MSHR uncacheable cycles 788system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050296 # mshr miss rate for ReadReq accesses 789system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050296 # mshr miss rate for ReadReq accesses 790system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050296 # mshr miss rate for demand accesses 791system.cpu.icache.demand_mshr_miss_rate::total 0.050296 # mshr miss rate for demand accesses 792system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050296 # mshr miss rate for overall accesses 793system.cpu.icache.overall_mshr_miss_rate::total 0.050296 # mshr miss rate for overall accesses 794system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12550.907778 # average ReadReq mshr miss latency 795system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12550.907778 # average ReadReq mshr miss latency 796system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12550.907778 # average overall mshr miss latency 797system.cpu.icache.demand_avg_mshr_miss_latency::total 12550.907778 # average overall mshr miss latency 798system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12550.907778 # average overall mshr miss latency 799system.cpu.icache.overall_avg_mshr_miss_latency::total 12550.907778 # average overall mshr miss latency 800system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77943.748041 # average ReadReq mshr uncacheable latency 801system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77943.748041 # average ReadReq mshr uncacheable latency 802system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77943.748041 # average overall mshr uncacheable latency 803system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77943.748041 # average overall mshr uncacheable latency | 765system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897853 # number of ReadReq MSHR misses 766system.cpu.icache.ReadReq_mshr_misses::total 2897853 # number of ReadReq MSHR misses 767system.cpu.icache.demand_mshr_misses::cpu.inst 2897853 # number of demand (read+write) MSHR misses 768system.cpu.icache.demand_mshr_misses::total 2897853 # number of demand (read+write) MSHR misses 769system.cpu.icache.overall_mshr_misses::cpu.inst 2897853 # number of overall MSHR misses 770system.cpu.icache.overall_mshr_misses::total 2897853 # number of overall MSHR misses 771system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3490 # number of ReadReq MSHR uncacheable 772system.cpu.icache.ReadReq_mshr_uncacheable::total 3490 # number of ReadReq MSHR uncacheable 773system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3490 # number of overall MSHR uncacheable misses 774system.cpu.icache.overall_mshr_uncacheable_misses::total 3490 # number of overall MSHR uncacheable misses 775system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37593940500 # number of ReadReq MSHR miss cycles 776system.cpu.icache.ReadReq_mshr_miss_latency::total 37593940500 # number of ReadReq MSHR miss cycles 777system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37593940500 # number of demand (read+write) MSHR miss cycles 778system.cpu.icache.demand_mshr_miss_latency::total 37593940500 # number of demand (read+write) MSHR miss cycles 779system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37593940500 # number of overall MSHR miss cycles 780system.cpu.icache.overall_mshr_miss_latency::total 37593940500 # number of overall MSHR miss cycles 781system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 450883500 # number of ReadReq MSHR uncacheable cycles 782system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 450883500 # number of ReadReq MSHR uncacheable cycles 783system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 450883500 # number of overall MSHR uncacheable cycles 784system.cpu.icache.overall_mshr_uncacheable_latency::total 450883500 # number of overall MSHR uncacheable cycles 785system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050319 # mshr miss rate for ReadReq accesses 786system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050319 # mshr miss rate for ReadReq accesses 787system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050319 # mshr miss rate for demand accesses 788system.cpu.icache.demand_mshr_miss_rate::total 0.050319 # mshr miss rate for demand accesses 789system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050319 # mshr miss rate for overall accesses 790system.cpu.icache.overall_mshr_miss_rate::total 0.050319 # mshr miss rate for overall accesses 791system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12973.032276 # average ReadReq mshr miss latency 792system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12973.032276 # average ReadReq mshr miss latency 793system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12973.032276 # average overall mshr miss latency 794system.cpu.icache.demand_avg_mshr_miss_latency::total 12973.032276 # average overall mshr miss latency 795system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12973.032276 # average overall mshr miss latency 796system.cpu.icache.overall_avg_mshr_miss_latency::total 12973.032276 # average overall mshr miss latency 797system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129192.979943 # average ReadReq mshr uncacheable latency 798system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129192.979943 # average ReadReq mshr uncacheable latency 799system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129192.979943 # average overall mshr uncacheable latency 800system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129192.979943 # average overall mshr uncacheable latency |
| 804system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 801system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 805system.cpu.l2cache.tags.replacements 97004 # number of replacements 806system.cpu.l2cache.tags.tagsinuse 65057.313836 # Cycle average of tags in use 807system.cpu.l2cache.tags.total_refs 7028000 # Total number of references to valid blocks. 808system.cpu.l2cache.tags.sampled_refs 162262 # Sample count of references to valid blocks. 809system.cpu.l2cache.tags.avg_refs 43.312667 # Average number of references to valid blocks. | 802system.cpu.l2cache.tags.replacements 96606 # number of replacements 803system.cpu.l2cache.tags.tagsinuse 65026.172791 # Cycle average of tags in use 804system.cpu.l2cache.tags.total_refs 7027132 # Total number of references to valid blocks. 805system.cpu.l2cache.tags.sampled_refs 161852 # Sample count of references to valid blocks. 806system.cpu.l2cache.tags.avg_refs 43.417023 # Average number of references to valid blocks. |
| 810system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 807system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 811system.cpu.l2cache.tags.occ_blocks::writebacks 47442.808035 # Average occupied blocks per requestor 812system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 71.645866 # Average occupied blocks per requestor 813system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000381 # Average occupied blocks per requestor 814system.cpu.l2cache.tags.occ_blocks::cpu.inst 12256.178987 # Average occupied blocks per requestor 815system.cpu.l2cache.tags.occ_blocks::cpu.data 5286.680567 # Average occupied blocks per requestor 816system.cpu.l2cache.tags.occ_percent::writebacks 0.723920 # Average percentage of cache occupancy 817system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001093 # Average percentage of cache occupancy | 808system.cpu.l2cache.tags.occ_blocks::writebacks 47537.333831 # Average occupied blocks per requestor 809system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 67.598904 # Average occupied blocks per requestor 810system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000505 # Average occupied blocks per requestor 811system.cpu.l2cache.tags.occ_blocks::cpu.inst 12131.683782 # Average occupied blocks per requestor 812system.cpu.l2cache.tags.occ_blocks::cpu.data 5289.555770 # Average occupied blocks per requestor 813system.cpu.l2cache.tags.occ_percent::writebacks 0.725362 # Average percentage of cache occupancy 814system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001031 # Average percentage of cache occupancy |
| 818system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy | 815system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy |
| 819system.cpu.l2cache.tags.occ_percent::cpu.inst 0.187014 # Average percentage of cache occupancy 820system.cpu.l2cache.tags.occ_percent::cpu.data 0.080668 # Average percentage of cache occupancy 821system.cpu.l2cache.tags.occ_percent::total 0.992696 # Average percentage of cache occupancy 822system.cpu.l2cache.tags.occ_task_id_blocks::1023 62 # Occupied blocks per task id | 816system.cpu.l2cache.tags.occ_percent::cpu.inst 0.185115 # Average percentage of cache occupancy 817system.cpu.l2cache.tags.occ_percent::cpu.data 0.080712 # Average percentage of cache occupancy 818system.cpu.l2cache.tags.occ_percent::total 0.992221 # Average percentage of cache occupancy 819system.cpu.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id |
| 823system.cpu.l2cache.tags.occ_task_id_blocks::1024 65196 # Occupied blocks per task id | 820system.cpu.l2cache.tags.occ_task_id_blocks::1024 65196 # Occupied blocks per task id |
| 824system.cpu.l2cache.tags.age_task_id_blocks_1023::4 62 # Occupied blocks per task id 825system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id 826system.cpu.l2cache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id 827system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2294 # Occupied blocks per task id 828system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6931 # Occupied blocks per task id 829system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55849 # Occupied blocks per task id 830system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000946 # Percentage of cache occupancy per task id | 821system.cpu.l2cache.tags.age_task_id_blocks_1023::4 50 # Occupied blocks per task id 822system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 823system.cpu.l2cache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id 824system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2273 # Occupied blocks per task id 825system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6868 # Occupied blocks per task id 826system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55936 # Occupied blocks per task id 827system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000763 # Percentage of cache occupancy per task id |
| 831system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994812 # Percentage of cache occupancy per task id | 828system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994812 # Percentage of cache occupancy per task id |
| 832system.cpu.l2cache.tags.tag_accesses 60457516 # Number of tag accesses 833system.cpu.l2cache.tags.data_accesses 60457516 # Number of data accesses 834system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 70014 # number of ReadReq hits 835system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4411 # number of ReadReq hits 836system.cpu.l2cache.ReadReq_hits::total 74425 # number of ReadReq hits 837system.cpu.l2cache.Writeback_hits::writebacks 699241 # number of Writeback hits 838system.cpu.l2cache.Writeback_hits::total 699241 # number of Writeback hits 839system.cpu.l2cache.UpgradeReq_hits::cpu.data 51 # number of UpgradeReq hits 840system.cpu.l2cache.UpgradeReq_hits::total 51 # number of UpgradeReq hits 841system.cpu.l2cache.ReadExReq_hits::cpu.data 164459 # number of ReadExReq hits 842system.cpu.l2cache.ReadExReq_hits::total 164459 # number of ReadExReq hits 843system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2873562 # number of ReadCleanReq hits 844system.cpu.l2cache.ReadCleanReq_hits::total 2873562 # number of ReadCleanReq hits 845system.cpu.l2cache.ReadSharedReq_hits::cpu.data 534090 # number of ReadSharedReq hits 846system.cpu.l2cache.ReadSharedReq_hits::total 534090 # number of ReadSharedReq hits 847system.cpu.l2cache.demand_hits::cpu.dtb.walker 70014 # number of demand (read+write) hits 848system.cpu.l2cache.demand_hits::cpu.itb.walker 4411 # number of demand (read+write) hits 849system.cpu.l2cache.demand_hits::cpu.inst 2873562 # number of demand (read+write) hits 850system.cpu.l2cache.demand_hits::cpu.data 698549 # number of demand (read+write) hits 851system.cpu.l2cache.demand_hits::total 3646536 # number of demand (read+write) hits 852system.cpu.l2cache.overall_hits::cpu.dtb.walker 70014 # number of overall hits 853system.cpu.l2cache.overall_hits::cpu.itb.walker 4411 # number of overall hits 854system.cpu.l2cache.overall_hits::cpu.inst 2873562 # number of overall hits 855system.cpu.l2cache.overall_hits::cpu.data 698549 # number of overall hits 856system.cpu.l2cache.overall_hits::total 3646536 # number of overall hits 857system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 126 # number of ReadReq misses | 829system.cpu.l2cache.tags.tag_accesses 60448944 # Number of tag accesses 830system.cpu.l2cache.tags.data_accesses 60448944 # Number of data accesses 831system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 72083 # number of ReadReq hits 832system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4650 # number of ReadReq hits 833system.cpu.l2cache.ReadReq_hits::total 76733 # number of ReadReq hits 834system.cpu.l2cache.Writeback_hits::writebacks 698521 # number of Writeback hits 835system.cpu.l2cache.Writeback_hits::total 698521 # number of Writeback hits 836system.cpu.l2cache.UpgradeReq_hits::cpu.data 47 # number of UpgradeReq hits 837system.cpu.l2cache.UpgradeReq_hits::total 47 # number of UpgradeReq hits 838system.cpu.l2cache.ReadExReq_hits::cpu.data 164594 # number of ReadExReq hits 839system.cpu.l2cache.ReadExReq_hits::total 164594 # number of ReadExReq hits 840system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2874830 # number of ReadCleanReq hits 841system.cpu.l2cache.ReadCleanReq_hits::total 2874830 # number of ReadCleanReq hits 842system.cpu.l2cache.ReadSharedReq_hits::cpu.data 531579 # number of ReadSharedReq hits 843system.cpu.l2cache.ReadSharedReq_hits::total 531579 # number of ReadSharedReq hits 844system.cpu.l2cache.demand_hits::cpu.dtb.walker 72083 # number of demand (read+write) hits 845system.cpu.l2cache.demand_hits::cpu.itb.walker 4650 # number of demand (read+write) hits 846system.cpu.l2cache.demand_hits::cpu.inst 2874830 # number of demand (read+write) hits 847system.cpu.l2cache.demand_hits::cpu.data 696173 # number of demand (read+write) hits 848system.cpu.l2cache.demand_hits::total 3647736 # number of demand (read+write) hits 849system.cpu.l2cache.overall_hits::cpu.dtb.walker 72083 # number of overall hits 850system.cpu.l2cache.overall_hits::cpu.itb.walker 4650 # number of overall hits 851system.cpu.l2cache.overall_hits::cpu.inst 2874830 # number of overall hits 852system.cpu.l2cache.overall_hits::cpu.data 696173 # number of overall hits 853system.cpu.l2cache.overall_hits::total 3647736 # number of overall hits 854system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 124 # number of ReadReq misses |
| 858system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses | 855system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses |
| 859system.cpu.l2cache.ReadReq_misses::total 127 # number of ReadReq misses 860system.cpu.l2cache.UpgradeReq_misses::cpu.data 2798 # number of UpgradeReq misses 861system.cpu.l2cache.UpgradeReq_misses::total 2798 # number of UpgradeReq misses | 856system.cpu.l2cache.ReadReq_misses::total 125 # number of ReadReq misses 857system.cpu.l2cache.UpgradeReq_misses::cpu.data 2732 # number of UpgradeReq misses 858system.cpu.l2cache.UpgradeReq_misses::total 2732 # number of UpgradeReq misses |
| 862system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 863system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses | 859system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 860system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses |
| 864system.cpu.l2cache.ReadExReq_misses::cpu.data 131405 # number of ReadExReq misses 865system.cpu.l2cache.ReadExReq_misses::total 131405 # number of ReadExReq misses 866system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22938 # number of ReadCleanReq misses 867system.cpu.l2cache.ReadCleanReq_misses::total 22938 # number of ReadCleanReq misses 868system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14340 # number of ReadSharedReq misses 869system.cpu.l2cache.ReadSharedReq_misses::total 14340 # number of ReadSharedReq misses 870system.cpu.l2cache.demand_misses::cpu.dtb.walker 126 # number of demand (read+write) misses | 861system.cpu.l2cache.ReadExReq_misses::cpu.data 131125 # number of ReadExReq misses 862system.cpu.l2cache.ReadExReq_misses::total 131125 # number of ReadExReq misses 863system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22992 # number of ReadCleanReq misses 864system.cpu.l2cache.ReadCleanReq_misses::total 22992 # number of ReadCleanReq misses 865system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14186 # number of ReadSharedReq misses 866system.cpu.l2cache.ReadSharedReq_misses::total 14186 # number of ReadSharedReq misses 867system.cpu.l2cache.demand_misses::cpu.dtb.walker 124 # number of demand (read+write) misses |
| 871system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses | 868system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses |
| 872system.cpu.l2cache.demand_misses::cpu.inst 22938 # number of demand (read+write) misses 873system.cpu.l2cache.demand_misses::cpu.data 145745 # number of demand (read+write) misses 874system.cpu.l2cache.demand_misses::total 168810 # number of demand (read+write) misses 875system.cpu.l2cache.overall_misses::cpu.dtb.walker 126 # number of overall misses | 869system.cpu.l2cache.demand_misses::cpu.inst 22992 # number of demand (read+write) misses 870system.cpu.l2cache.demand_misses::cpu.data 145311 # number of demand (read+write) misses 871system.cpu.l2cache.demand_misses::total 168428 # number of demand (read+write) misses 872system.cpu.l2cache.overall_misses::cpu.dtb.walker 124 # number of overall misses |
| 876system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses | 873system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses |
| 877system.cpu.l2cache.overall_misses::cpu.inst 22938 # number of overall misses 878system.cpu.l2cache.overall_misses::cpu.data 145745 # number of overall misses 879system.cpu.l2cache.overall_misses::total 168810 # number of overall misses 880system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 11282500 # number of ReadReq miss cycles 881system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 82500 # number of ReadReq miss cycles 882system.cpu.l2cache.ReadReq_miss_latency::total 11365000 # number of ReadReq miss cycles 883system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1076000 # number of UpgradeReq miss cycles 884system.cpu.l2cache.UpgradeReq_miss_latency::total 1076000 # number of UpgradeReq miss cycles | 874system.cpu.l2cache.overall_misses::cpu.inst 22992 # number of overall misses 875system.cpu.l2cache.overall_misses::cpu.data 145311 # number of overall misses 876system.cpu.l2cache.overall_misses::total 168428 # number of overall misses 877system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 16852000 # number of ReadReq miss cycles 878system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 132500 # number of ReadReq miss cycles 879system.cpu.l2cache.ReadReq_miss_latency::total 16984500 # number of ReadReq miss cycles 880system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 3066500 # number of UpgradeReq miss cycles 881system.cpu.l2cache.UpgradeReq_miss_latency::total 3066500 # number of UpgradeReq miss cycles |
| 885system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles 886system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles | 882system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles 883system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles |
| 887system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10178186000 # number of ReadExReq miss cycles 888system.cpu.l2cache.ReadExReq_miss_latency::total 10178186000 # number of ReadExReq miss cycles 889system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1825056000 # number of ReadCleanReq miss cycles 890system.cpu.l2cache.ReadCleanReq_miss_latency::total 1825056000 # number of ReadCleanReq miss cycles 891system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1190867500 # number of ReadSharedReq miss cycles 892system.cpu.l2cache.ReadSharedReq_miss_latency::total 1190867500 # number of ReadSharedReq miss cycles 893system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 11282500 # number of demand (read+write) miss cycles 894system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 82500 # number of demand (read+write) miss cycles 895system.cpu.l2cache.demand_miss_latency::cpu.inst 1825056000 # number of demand (read+write) miss cycles 896system.cpu.l2cache.demand_miss_latency::cpu.data 11369053500 # number of demand (read+write) miss cycles 897system.cpu.l2cache.demand_miss_latency::total 13205474500 # number of demand (read+write) miss cycles 898system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 11282500 # number of overall miss cycles 899system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 82500 # number of overall miss cycles 900system.cpu.l2cache.overall_miss_latency::cpu.inst 1825056000 # number of overall miss cycles 901system.cpu.l2cache.overall_miss_latency::cpu.data 11369053500 # number of overall miss cycles 902system.cpu.l2cache.overall_miss_latency::total 13205474500 # number of overall miss cycles 903system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 70140 # number of ReadReq accesses(hits+misses) 904system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4412 # number of ReadReq accesses(hits+misses) 905system.cpu.l2cache.ReadReq_accesses::total 74552 # number of ReadReq accesses(hits+misses) 906system.cpu.l2cache.Writeback_accesses::writebacks 699241 # number of Writeback accesses(hits+misses) 907system.cpu.l2cache.Writeback_accesses::total 699241 # number of Writeback accesses(hits+misses) 908system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2849 # number of UpgradeReq accesses(hits+misses) 909system.cpu.l2cache.UpgradeReq_accesses::total 2849 # number of UpgradeReq accesses(hits+misses) | 884system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16810889000 # number of ReadExReq miss cycles 885system.cpu.l2cache.ReadExReq_miss_latency::total 16810889000 # number of ReadExReq miss cycles 886system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 3007737500 # number of ReadCleanReq miss cycles 887system.cpu.l2cache.ReadCleanReq_miss_latency::total 3007737500 # number of ReadCleanReq miss cycles 888system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1878016500 # number of ReadSharedReq miss cycles 889system.cpu.l2cache.ReadSharedReq_miss_latency::total 1878016500 # number of ReadSharedReq miss cycles 890system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 16852000 # number of demand (read+write) miss cycles 891system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 132500 # number of demand (read+write) miss cycles 892system.cpu.l2cache.demand_miss_latency::cpu.inst 3007737500 # number of demand (read+write) miss cycles 893system.cpu.l2cache.demand_miss_latency::cpu.data 18688905500 # number of demand (read+write) miss cycles 894system.cpu.l2cache.demand_miss_latency::total 21713627500 # number of demand (read+write) miss cycles 895system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 16852000 # number of overall miss cycles 896system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 132500 # number of overall miss cycles 897system.cpu.l2cache.overall_miss_latency::cpu.inst 3007737500 # number of overall miss cycles 898system.cpu.l2cache.overall_miss_latency::cpu.data 18688905500 # number of overall miss cycles 899system.cpu.l2cache.overall_miss_latency::total 21713627500 # number of overall miss cycles 900system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 72207 # number of ReadReq accesses(hits+misses) 901system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4651 # number of ReadReq accesses(hits+misses) 902system.cpu.l2cache.ReadReq_accesses::total 76858 # number of ReadReq accesses(hits+misses) 903system.cpu.l2cache.Writeback_accesses::writebacks 698521 # number of Writeback accesses(hits+misses) 904system.cpu.l2cache.Writeback_accesses::total 698521 # number of Writeback accesses(hits+misses) 905system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2779 # number of UpgradeReq accesses(hits+misses) 906system.cpu.l2cache.UpgradeReq_accesses::total 2779 # number of UpgradeReq accesses(hits+misses) |
| 910system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 911system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) | 907system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 908system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) |
| 912system.cpu.l2cache.ReadExReq_accesses::cpu.data 295864 # number of ReadExReq accesses(hits+misses) 913system.cpu.l2cache.ReadExReq_accesses::total 295864 # number of ReadExReq accesses(hits+misses) 914system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2896500 # number of ReadCleanReq accesses(hits+misses) 915system.cpu.l2cache.ReadCleanReq_accesses::total 2896500 # number of ReadCleanReq accesses(hits+misses) 916system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 548430 # number of ReadSharedReq accesses(hits+misses) 917system.cpu.l2cache.ReadSharedReq_accesses::total 548430 # number of ReadSharedReq accesses(hits+misses) 918system.cpu.l2cache.demand_accesses::cpu.dtb.walker 70140 # number of demand (read+write) accesses 919system.cpu.l2cache.demand_accesses::cpu.itb.walker 4412 # number of demand (read+write) accesses 920system.cpu.l2cache.demand_accesses::cpu.inst 2896500 # number of demand (read+write) accesses 921system.cpu.l2cache.demand_accesses::cpu.data 844294 # number of demand (read+write) accesses 922system.cpu.l2cache.demand_accesses::total 3815346 # number of demand (read+write) accesses 923system.cpu.l2cache.overall_accesses::cpu.dtb.walker 70140 # number of overall (read+write) accesses 924system.cpu.l2cache.overall_accesses::cpu.itb.walker 4412 # number of overall (read+write) accesses 925system.cpu.l2cache.overall_accesses::cpu.inst 2896500 # number of overall (read+write) accesses 926system.cpu.l2cache.overall_accesses::cpu.data 844294 # number of overall (read+write) accesses 927system.cpu.l2cache.overall_accesses::total 3815346 # number of overall (read+write) accesses 928system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001796 # miss rate for ReadReq accesses 929system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000227 # miss rate for ReadReq accesses 930system.cpu.l2cache.ReadReq_miss_rate::total 0.001704 # miss rate for ReadReq accesses 931system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.982099 # miss rate for UpgradeReq accesses 932system.cpu.l2cache.UpgradeReq_miss_rate::total 0.982099 # miss rate for UpgradeReq accesses | 909system.cpu.l2cache.ReadExReq_accesses::cpu.data 295719 # number of ReadExReq accesses(hits+misses) 910system.cpu.l2cache.ReadExReq_accesses::total 295719 # number of ReadExReq accesses(hits+misses) 911system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2897822 # number of ReadCleanReq accesses(hits+misses) 912system.cpu.l2cache.ReadCleanReq_accesses::total 2897822 # number of ReadCleanReq accesses(hits+misses) 913system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 545765 # number of ReadSharedReq accesses(hits+misses) 914system.cpu.l2cache.ReadSharedReq_accesses::total 545765 # number of ReadSharedReq accesses(hits+misses) 915system.cpu.l2cache.demand_accesses::cpu.dtb.walker 72207 # number of demand (read+write) accesses 916system.cpu.l2cache.demand_accesses::cpu.itb.walker 4651 # number of demand (read+write) accesses 917system.cpu.l2cache.demand_accesses::cpu.inst 2897822 # number of demand (read+write) accesses 918system.cpu.l2cache.demand_accesses::cpu.data 841484 # number of demand (read+write) accesses 919system.cpu.l2cache.demand_accesses::total 3816164 # number of demand (read+write) accesses 920system.cpu.l2cache.overall_accesses::cpu.dtb.walker 72207 # number of overall (read+write) accesses 921system.cpu.l2cache.overall_accesses::cpu.itb.walker 4651 # number of overall (read+write) accesses 922system.cpu.l2cache.overall_accesses::cpu.inst 2897822 # number of overall (read+write) accesses 923system.cpu.l2cache.overall_accesses::cpu.data 841484 # number of overall (read+write) accesses 924system.cpu.l2cache.overall_accesses::total 3816164 # number of overall (read+write) accesses 925system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001717 # miss rate for ReadReq accesses 926system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000215 # miss rate for ReadReq accesses 927system.cpu.l2cache.ReadReq_miss_rate::total 0.001626 # miss rate for ReadReq accesses 928system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.983087 # miss rate for UpgradeReq accesses 929system.cpu.l2cache.UpgradeReq_miss_rate::total 0.983087 # miss rate for UpgradeReq accesses |
| 933system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 934system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 930system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 931system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 935system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.444140 # miss rate for ReadExReq accesses 936system.cpu.l2cache.ReadExReq_miss_rate::total 0.444140 # miss rate for ReadExReq accesses 937system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007919 # miss rate for ReadCleanReq accesses 938system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007919 # miss rate for ReadCleanReq accesses 939system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026147 # miss rate for ReadSharedReq accesses 940system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026147 # miss rate for ReadSharedReq accesses 941system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001796 # miss rate for demand accesses 942system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000227 # miss rate for demand accesses 943system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007919 # miss rate for demand accesses 944system.cpu.l2cache.demand_miss_rate::cpu.data 0.172624 # miss rate for demand accesses 945system.cpu.l2cache.demand_miss_rate::total 0.044245 # miss rate for demand accesses 946system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001796 # miss rate for overall accesses 947system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000227 # miss rate for overall accesses 948system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007919 # miss rate for overall accesses 949system.cpu.l2cache.overall_miss_rate::cpu.data 0.172624 # miss rate for overall accesses 950system.cpu.l2cache.overall_miss_rate::total 0.044245 # miss rate for overall accesses 951system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89543.650794 # average ReadReq miss latency 952system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82500 # average ReadReq miss latency 953system.cpu.l2cache.ReadReq_avg_miss_latency::total 89488.188976 # average ReadReq miss latency 954system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 384.560400 # average UpgradeReq miss latency 955system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 384.560400 # average UpgradeReq miss latency | 932system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.443411 # miss rate for ReadExReq accesses 933system.cpu.l2cache.ReadExReq_miss_rate::total 0.443411 # miss rate for ReadExReq accesses 934system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007934 # miss rate for ReadCleanReq accesses 935system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007934 # miss rate for ReadCleanReq accesses 936system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.025993 # miss rate for ReadSharedReq accesses 937system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.025993 # miss rate for ReadSharedReq accesses 938system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001717 # miss rate for demand accesses 939system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000215 # miss rate for demand accesses 940system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007934 # miss rate for demand accesses 941system.cpu.l2cache.demand_miss_rate::cpu.data 0.172684 # miss rate for demand accesses 942system.cpu.l2cache.demand_miss_rate::total 0.044135 # miss rate for demand accesses 943system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001717 # miss rate for overall accesses 944system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000215 # miss rate for overall accesses 945system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007934 # miss rate for overall accesses 946system.cpu.l2cache.overall_miss_rate::cpu.data 0.172684 # miss rate for overall accesses 947system.cpu.l2cache.overall_miss_rate::total 0.044135 # miss rate for overall accesses 948system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 135903.225806 # average ReadReq miss latency 949system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132500 # average ReadReq miss latency 950system.cpu.l2cache.ReadReq_avg_miss_latency::total 135876 # average ReadReq miss latency 951system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1122.437775 # average UpgradeReq miss latency 952system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1122.437775 # average UpgradeReq miss latency |
| 956system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 81000 # average SCUpgradeReq miss latency 957system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 81000 # average SCUpgradeReq miss latency | 953system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 81000 # average SCUpgradeReq miss latency 954system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 81000 # average SCUpgradeReq miss latency |
| 958system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77456.611240 # average ReadExReq miss latency 959system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77456.611240 # average ReadExReq miss latency 960system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79564.739733 # average ReadCleanReq miss latency 961system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79564.739733 # average ReadCleanReq miss latency 962system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83045.153417 # average ReadSharedReq miss latency 963system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83045.153417 # average ReadSharedReq miss latency 964system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89543.650794 # average overall miss latency 965system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82500 # average overall miss latency 966system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79564.739733 # average overall miss latency 967system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78006.473635 # average overall miss latency 968system.cpu.l2cache.demand_avg_miss_latency::total 78226.849713 # average overall miss latency 969system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89543.650794 # average overall miss latency 970system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82500 # average overall miss latency 971system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79564.739733 # average overall miss latency 972system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78006.473635 # average overall miss latency 973system.cpu.l2cache.overall_avg_miss_latency::total 78226.849713 # average overall miss latency | 955system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 128205.063870 # average ReadExReq miss latency 956system.cpu.l2cache.ReadExReq_avg_miss_latency::total 128205.063870 # average ReadExReq miss latency 957system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130816.697112 # average ReadCleanReq miss latency 958system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130816.697112 # average ReadCleanReq miss latency 959system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132385.203722 # average ReadSharedReq miss latency 960system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132385.203722 # average ReadSharedReq miss latency 961system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 135903.225806 # average overall miss latency 962system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 132500 # average overall miss latency 963system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130816.697112 # average overall miss latency 964system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128613.150415 # average overall miss latency 965system.cpu.l2cache.demand_avg_miss_latency::total 128919.345358 # average overall miss latency 966system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 135903.225806 # average overall miss latency 967system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 132500 # average overall miss latency 968system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130816.697112 # average overall miss latency 969system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128613.150415 # average overall miss latency 970system.cpu.l2cache.overall_avg_miss_latency::total 128919.345358 # average overall miss latency |
| 974system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 975system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 976system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 977system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 978system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 979system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 980system.cpu.l2cache.fast_writes 0 # number of fast writes performed 981system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 971system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 972system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 973system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 974system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 975system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 976system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 977system.cpu.l2cache.fast_writes 0 # number of fast writes performed 978system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 982system.cpu.l2cache.writebacks::writebacks 88519 # number of writebacks 983system.cpu.l2cache.writebacks::total 88519 # number of writebacks 984system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 25 # number of ReadCleanReq MSHR hits 985system.cpu.l2cache.ReadCleanReq_mshr_hits::total 25 # number of ReadCleanReq MSHR hits 986system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 140 # number of ReadSharedReq MSHR hits 987system.cpu.l2cache.ReadSharedReq_mshr_hits::total 140 # number of ReadSharedReq MSHR hits 988system.cpu.l2cache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits 989system.cpu.l2cache.demand_mshr_hits::cpu.data 140 # number of demand (read+write) MSHR hits 990system.cpu.l2cache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits 991system.cpu.l2cache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits 992system.cpu.l2cache.overall_mshr_hits::cpu.data 140 # number of overall MSHR hits 993system.cpu.l2cache.overall_mshr_hits::total 165 # number of overall MSHR hits 994system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 126 # number of ReadReq MSHR misses | 979system.cpu.l2cache.writebacks::writebacks 87966 # number of writebacks 980system.cpu.l2cache.writebacks::total 87966 # number of writebacks 981system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 19 # number of ReadCleanReq MSHR hits 982system.cpu.l2cache.ReadCleanReq_mshr_hits::total 19 # number of ReadCleanReq MSHR hits 983system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 141 # number of ReadSharedReq MSHR hits 984system.cpu.l2cache.ReadSharedReq_mshr_hits::total 141 # number of ReadSharedReq MSHR hits 985system.cpu.l2cache.demand_mshr_hits::cpu.inst 19 # number of demand (read+write) MSHR hits 986system.cpu.l2cache.demand_mshr_hits::cpu.data 141 # number of demand (read+write) MSHR hits 987system.cpu.l2cache.demand_mshr_hits::total 160 # number of demand (read+write) MSHR hits 988system.cpu.l2cache.overall_mshr_hits::cpu.inst 19 # number of overall MSHR hits 989system.cpu.l2cache.overall_mshr_hits::cpu.data 141 # number of overall MSHR hits 990system.cpu.l2cache.overall_mshr_hits::total 160 # number of overall MSHR hits 991system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 124 # number of ReadReq MSHR misses |
| 995system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses | 992system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses |
| 996system.cpu.l2cache.ReadReq_mshr_misses::total 127 # number of ReadReq MSHR misses 997system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2798 # number of UpgradeReq MSHR misses 998system.cpu.l2cache.UpgradeReq_mshr_misses::total 2798 # number of UpgradeReq MSHR misses | 993system.cpu.l2cache.ReadReq_mshr_misses::total 125 # number of ReadReq MSHR misses 994system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2732 # number of UpgradeReq MSHR misses 995system.cpu.l2cache.UpgradeReq_mshr_misses::total 2732 # number of UpgradeReq MSHR misses |
| 999system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1000system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses | 996system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 997system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses |
| 1001system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131405 # number of ReadExReq MSHR misses 1002system.cpu.l2cache.ReadExReq_mshr_misses::total 131405 # number of ReadExReq MSHR misses 1003system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22913 # number of ReadCleanReq MSHR misses 1004system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22913 # number of ReadCleanReq MSHR misses 1005system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14200 # number of ReadSharedReq MSHR misses 1006system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14200 # number of ReadSharedReq MSHR misses 1007system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 126 # number of demand (read+write) MSHR misses | 998system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131125 # number of ReadExReq MSHR misses 999system.cpu.l2cache.ReadExReq_mshr_misses::total 131125 # number of ReadExReq MSHR misses 1000system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22973 # number of ReadCleanReq MSHR misses 1001system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22973 # number of ReadCleanReq MSHR misses 1002system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14045 # number of ReadSharedReq MSHR misses 1003system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14045 # number of ReadSharedReq MSHR misses 1004system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 124 # number of demand (read+write) MSHR misses |
| 1008system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses | 1005system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses |
| 1009system.cpu.l2cache.demand_mshr_misses::cpu.inst 22913 # number of demand (read+write) MSHR misses 1010system.cpu.l2cache.demand_mshr_misses::cpu.data 145605 # number of demand (read+write) MSHR misses 1011system.cpu.l2cache.demand_mshr_misses::total 168645 # number of demand (read+write) MSHR misses 1012system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 126 # number of overall MSHR misses | 1006system.cpu.l2cache.demand_mshr_misses::cpu.inst 22973 # number of demand (read+write) MSHR misses 1007system.cpu.l2cache.demand_mshr_misses::cpu.data 145170 # number of demand (read+write) MSHR misses 1008system.cpu.l2cache.demand_mshr_misses::total 168268 # number of demand (read+write) MSHR misses 1009system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 124 # number of overall MSHR misses |
| 1013system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses | 1010system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses |
| 1014system.cpu.l2cache.overall_mshr_misses::cpu.inst 22913 # number of overall MSHR misses 1015system.cpu.l2cache.overall_mshr_misses::cpu.data 145605 # number of overall MSHR misses 1016system.cpu.l2cache.overall_mshr_misses::total 168645 # number of overall MSHR misses 1017system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3191 # number of ReadReq MSHR uncacheable | 1011system.cpu.l2cache.overall_mshr_misses::cpu.inst 22973 # number of overall MSHR misses 1012system.cpu.l2cache.overall_mshr_misses::cpu.data 145170 # number of overall MSHR misses 1013system.cpu.l2cache.overall_mshr_misses::total 168268 # number of overall MSHR misses 1014system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3490 # number of ReadReq MSHR uncacheable |
| 1018system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable | 1015system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable |
| 1019system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34319 # number of ReadReq MSHR uncacheable | 1016system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34618 # number of ReadReq MSHR uncacheable |
| 1020system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable 1021system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable | 1017system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable 1018system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable |
| 1022system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3191 # number of overall MSHR uncacheable misses | 1019system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3490 # number of overall MSHR uncacheable misses |
| 1023system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses | 1020system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses |
| 1024system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61902 # number of overall MSHR uncacheable misses 1025system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 10022500 # number of ReadReq MSHR miss cycles 1026system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 72500 # number of ReadReq MSHR miss cycles 1027system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10095000 # number of ReadReq MSHR miss cycles 1028system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 58085500 # number of UpgradeReq MSHR miss cycles 1029system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 58085500 # number of UpgradeReq MSHR miss cycles | 1021system.cpu.l2cache.overall_mshr_uncacheable_misses::total 62201 # number of overall MSHR uncacheable misses 1022system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 15612000 # number of ReadReq MSHR miss cycles 1023system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 122500 # number of ReadReq MSHR miss cycles 1024system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15734500 # number of ReadReq MSHR miss cycles 1025system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 193275000 # number of UpgradeReq MSHR miss cycles 1026system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 193275000 # number of UpgradeReq MSHR miss cycles |
| 1030system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 142000 # number of SCUpgradeReq MSHR miss cycles 1031system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 142000 # number of SCUpgradeReq MSHR miss cycles | 1027system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 142000 # number of SCUpgradeReq MSHR miss cycles 1028system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 142000 # number of SCUpgradeReq MSHR miss cycles |
| 1032system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8864136000 # number of ReadExReq MSHR miss cycles 1033system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8864136000 # number of ReadExReq MSHR miss cycles 1034system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1594702500 # number of ReadCleanReq MSHR miss cycles 1035system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1594702500 # number of ReadCleanReq MSHR miss cycles 1036system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1038186000 # number of ReadSharedReq MSHR miss cycles 1037system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1038186000 # number of ReadSharedReq MSHR miss cycles 1038system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 10022500 # number of demand (read+write) MSHR miss cycles 1039system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 72500 # number of demand (read+write) MSHR miss cycles 1040system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1594702500 # number of demand (read+write) MSHR miss cycles 1041system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9902322000 # number of demand (read+write) MSHR miss cycles 1042system.cpu.l2cache.demand_mshr_miss_latency::total 11507119500 # number of demand (read+write) MSHR miss cycles 1043system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 10022500 # number of overall MSHR miss cycles 1044system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 72500 # number of overall MSHR miss cycles 1045system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1594702500 # number of overall MSHR miss cycles 1046system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9902322000 # number of overall MSHR miss cycles 1047system.cpu.l2cache.overall_mshr_miss_latency::total 11507119500 # number of overall MSHR miss cycles 1048system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 199170000 # number of ReadReq MSHR uncacheable cycles 1049system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5519931000 # number of ReadReq MSHR uncacheable cycles 1050system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5719101000 # number of ReadReq MSHR uncacheable cycles 1051system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4251556500 # number of WriteReq MSHR uncacheable cycles 1052system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4251556500 # number of WriteReq MSHR uncacheable cycles 1053system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 199170000 # number of overall MSHR uncacheable cycles 1054system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9771487500 # number of overall MSHR uncacheable cycles 1055system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9970657500 # number of overall MSHR uncacheable cycles 1056system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001796 # mshr miss rate for ReadReq accesses 1057system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000227 # mshr miss rate for ReadReq accesses 1058system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001704 # mshr miss rate for ReadReq accesses 1059system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982099 # mshr miss rate for UpgradeReq accesses 1060system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982099 # mshr miss rate for UpgradeReq accesses | 1029system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15499639000 # number of ReadExReq MSHR miss cycles 1030system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15499639000 # number of ReadExReq MSHR miss cycles 1031system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2776629500 # number of ReadCleanReq MSHR miss cycles 1032system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2776629500 # number of ReadCleanReq MSHR miss cycles 1033system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1720074500 # number of ReadSharedReq MSHR miss cycles 1034system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1720074500 # number of ReadSharedReq MSHR miss cycles 1035system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 15612000 # number of demand (read+write) MSHR miss cycles 1036system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 122500 # number of demand (read+write) MSHR miss cycles 1037system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2776629500 # number of demand (read+write) MSHR miss cycles 1038system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17219713500 # number of demand (read+write) MSHR miss cycles 1039system.cpu.l2cache.demand_mshr_miss_latency::total 20012077500 # number of demand (read+write) MSHR miss cycles 1040system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 15612000 # number of overall MSHR miss cycles 1041system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 122500 # number of overall MSHR miss cycles 1042system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2776629500 # number of overall MSHR miss cycles 1043system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17219713500 # number of overall MSHR miss cycles 1044system.cpu.l2cache.overall_mshr_miss_latency::total 20012077500 # number of overall MSHR miss cycles 1045system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 396548000 # number of ReadReq MSHR uncacheable cycles 1046system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5548169500 # number of ReadReq MSHR uncacheable cycles 1047system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5944717500 # number of ReadReq MSHR uncacheable cycles 1048system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4470099000 # number of WriteReq MSHR uncacheable cycles 1049system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4470099000 # number of WriteReq MSHR uncacheable cycles 1050system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 396548000 # number of overall MSHR uncacheable cycles 1051system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10018268500 # number of overall MSHR uncacheable cycles 1052system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10414816500 # number of overall MSHR uncacheable cycles 1053system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for ReadReq accesses 1054system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000215 # mshr miss rate for ReadReq accesses 1055system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001626 # mshr miss rate for ReadReq accesses 1056system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.983087 # mshr miss rate for UpgradeReq accesses 1057system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.983087 # mshr miss rate for UpgradeReq accesses |
| 1061system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1062system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses | 1058system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1059system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses |
| 1063system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.444140 # mshr miss rate for ReadExReq accesses 1064system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.444140 # mshr miss rate for ReadExReq accesses 1065system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007911 # mshr miss rate for ReadCleanReq accesses 1066system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007911 # mshr miss rate for ReadCleanReq accesses 1067system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025892 # mshr miss rate for ReadSharedReq accesses 1068system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025892 # mshr miss rate for ReadSharedReq accesses 1069system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001796 # mshr miss rate for demand accesses 1070system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000227 # mshr miss rate for demand accesses 1071system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007911 # mshr miss rate for demand accesses 1072system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172458 # mshr miss rate for demand accesses 1073system.cpu.l2cache.demand_mshr_miss_rate::total 0.044202 # mshr miss rate for demand accesses 1074system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001796 # mshr miss rate for overall accesses 1075system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000227 # mshr miss rate for overall accesses 1076system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007911 # mshr miss rate for overall accesses 1077system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172458 # mshr miss rate for overall accesses 1078system.cpu.l2cache.overall_mshr_miss_rate::total 0.044202 # mshr miss rate for overall accesses 1079system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79543.650794 # average ReadReq mshr miss latency 1080system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 72500 # average ReadReq mshr miss latency 1081system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 79488.188976 # average ReadReq mshr miss latency 1082system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20759.649750 # average UpgradeReq mshr miss latency 1083system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20759.649750 # average UpgradeReq mshr miss latency | 1060system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443411 # mshr miss rate for ReadExReq accesses 1061system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443411 # mshr miss rate for ReadExReq accesses 1062system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for ReadCleanReq accesses 1063system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007928 # mshr miss rate for ReadCleanReq accesses 1064system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025735 # mshr miss rate for ReadSharedReq accesses 1065system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025735 # mshr miss rate for ReadSharedReq accesses 1066system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for demand accesses 1067system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000215 # mshr miss rate for demand accesses 1068system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for demand accesses 1069system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172517 # mshr miss rate for demand accesses 1070system.cpu.l2cache.demand_mshr_miss_rate::total 0.044093 # mshr miss rate for demand accesses 1071system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for overall accesses 1072system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000215 # mshr miss rate for overall accesses 1073system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for overall accesses 1074system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172517 # mshr miss rate for overall accesses 1075system.cpu.l2cache.overall_mshr_miss_rate::total 0.044093 # mshr miss rate for overall accesses 1076system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125903.225806 # average ReadReq mshr miss latency 1077system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122500 # average ReadReq mshr miss latency 1078system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125876 # average ReadReq mshr miss latency 1079system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70744.875549 # average UpgradeReq mshr miss latency 1080system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70744.875549 # average UpgradeReq mshr miss latency |
| 1084system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71000 # average SCUpgradeReq mshr miss latency 1085system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71000 # average SCUpgradeReq mshr miss latency | 1081system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71000 # average SCUpgradeReq mshr miss latency 1082system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71000 # average SCUpgradeReq mshr miss latency |
| 1086system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67456.611240 # average ReadExReq mshr miss latency 1087system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67456.611240 # average ReadExReq mshr miss latency 1088system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69598.153886 # average ReadCleanReq mshr miss latency 1089system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69598.153886 # average ReadCleanReq mshr miss latency 1090system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73111.690141 # average ReadSharedReq mshr miss latency 1091system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73111.690141 # average ReadSharedReq mshr miss latency 1092system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79543.650794 # average overall mshr miss latency 1093system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 72500 # average overall mshr miss latency 1094system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69598.153886 # average overall mshr miss latency 1095system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68008.117853 # average overall mshr miss latency 1096system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68232.793738 # average overall mshr miss latency 1097system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79543.650794 # average overall mshr miss latency 1098system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 72500 # average overall mshr miss latency 1099system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69598.153886 # average overall mshr miss latency 1100system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68008.117853 # average overall mshr miss latency 1101system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68232.793738 # average overall mshr miss latency 1102system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62416.170479 # average ReadReq mshr uncacheable latency 1103system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177330.088666 # average ReadReq mshr uncacheable latency 1104system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166645.327661 # average ReadReq mshr uncacheable latency 1105system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154136.841533 # average WriteReq mshr uncacheable latency 1106system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154136.841533 # average WriteReq mshr uncacheable latency 1107system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62416.170479 # average overall mshr uncacheable latency 1108system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166433.675121 # average overall mshr uncacheable latency 1109system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 161071.653581 # average overall mshr uncacheable latency | 1083system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118205.063870 # average ReadExReq mshr miss latency 1084system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118205.063870 # average ReadExReq mshr miss latency 1085system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120864.906630 # average ReadCleanReq mshr miss latency 1086system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120864.906630 # average ReadCleanReq mshr miss latency 1087system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122468.814525 # average ReadSharedReq mshr miss latency 1088system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122468.814525 # average ReadSharedReq mshr miss latency 1089system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125903.225806 # average overall mshr miss latency 1090system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency 1091system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120864.906630 # average overall mshr miss latency 1092system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118617.575945 # average overall mshr miss latency 1093system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118929.787601 # average overall mshr miss latency 1094system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125903.225806 # average overall mshr miss latency 1095system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency 1096system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120864.906630 # average overall mshr miss latency 1097system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118617.575945 # average overall mshr miss latency 1098system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118929.787601 # average overall mshr miss latency 1099system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113624.068768 # average ReadReq mshr uncacheable latency 1100system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178237.262272 # average ReadReq mshr uncacheable latency 1101system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 171723.308683 # average ReadReq mshr uncacheable latency 1102system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162059.928217 # average WriteReq mshr uncacheable latency 1103system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162059.928217 # average WriteReq mshr uncacheable latency 1104system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113624.068768 # average overall mshr uncacheable latency 1105system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170636.993068 # average overall mshr uncacheable latency 1106system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 167438.087812 # average overall mshr uncacheable latency |
| 1110system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1107system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1111system.cpu.toL2Bus.trans_dist::ReadReq 133644 # Transaction distribution 1112system.cpu.toL2Bus.trans_dist::ReadResp 3578737 # Transaction distribution | 1108system.cpu.toL2Bus.snoop_filter.tot_requests 7509435 # Total number of requests made to the snoop filter. 1109system.cpu.toL2Bus.snoop_filter.hit_single_requests 3770131 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1110system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58870 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1111system.cpu.toL2Bus.snoop_filter.tot_snoops 575 # Total number of snoops made to the snoop filter. 1112system.cpu.toL2Bus.snoop_filter.hit_single_snoops 575 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1113system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1114system.cpu.toL2Bus.trans_dist::ReadReq 134592 # Transaction distribution 1115system.cpu.toL2Bus.trans_dist::ReadResp 3578420 # Transaction distribution |
| 1113system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution 1114system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution | 1116system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution 1117system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution |
| 1115system.cpu.toL2Bus.trans_dist::Writeback 823959 # Transaction distribution 1116system.cpu.toL2Bus.trans_dist::CleanEvict 2990642 # Transaction distribution 1117system.cpu.toL2Bus.trans_dist::UpgradeReq 2849 # Transaction distribution | 1118system.cpu.toL2Bus.trans_dist::Writeback 822692 # Transaction distribution 1119system.cpu.toL2Bus.trans_dist::CleanEvict 2989768 # Transaction distribution 1120system.cpu.toL2Bus.trans_dist::UpgradeReq 2779 # Transaction distribution |
| 1118system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution | 1121system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution |
| 1119system.cpu.toL2Bus.trans_dist::UpgradeResp 2851 # Transaction distribution 1120system.cpu.toL2Bus.trans_dist::ReadExReq 295864 # Transaction distribution 1121system.cpu.toL2Bus.trans_dist::ReadExResp 295864 # Transaction distribution 1122system.cpu.toL2Bus.trans_dist::ReadCleanReq 2896522 # Transaction distribution 1123system.cpu.toL2Bus.trans_dist::ReadSharedReq 548664 # Transaction distribution | 1122system.cpu.toL2Bus.trans_dist::UpgradeResp 2781 # Transaction distribution 1123system.cpu.toL2Bus.trans_dist::ReadExReq 295719 # Transaction distribution 1124system.cpu.toL2Bus.trans_dist::ReadExResp 295719 # Transaction distribution 1125system.cpu.toL2Bus.trans_dist::ReadCleanReq 2897853 # Transaction distribution 1126system.cpu.toL2Bus.trans_dist::ReadSharedReq 545999 # Transaction distribution |
| 1124system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution | 1127system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution |
| 1125system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8644384 # Packet count per connected master and slave (bytes) 1126system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2648037 # Packet count per connected master and slave (bytes) 1127system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14998 # Packet count per connected master and slave (bytes) 1128system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158879 # Packet count per connected master and slave (bytes) 1129system.cpu.toL2Bus.pkt_count::total 11466298 # Packet count per connected master and slave (bytes) 1130system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185580160 # Cumulative packet size per connected master and slave (bytes) 1131system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98978397 # Cumulative packet size per connected master and slave (bytes) 1132system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17648 # Cumulative packet size per connected master and slave (bytes) 1133system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 280560 # Cumulative packet size per connected master and slave (bytes) 1134system.cpu.toL2Bus.pkt_size::total 284856765 # Cumulative packet size per connected master and slave (bytes) 1135system.cpu.toL2Bus.snoops 194832 # Total snoops (count) 1136system.cpu.toL2Bus.snoop_fanout::samples 7814541 # Request fanout histogram 1137system.cpu.toL2Bus.snoop_fanout::mean 1.034451 # Request fanout histogram 1138system.cpu.toL2Bus.snoop_fanout::stdev 0.182385 # Request fanout histogram | 1128system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8648477 # Packet count per connected master and slave (bytes) 1129system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2639755 # Packet count per connected master and slave (bytes) 1130system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15227 # Packet count per connected master and slave (bytes) 1131system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 161605 # Packet count per connected master and slave (bytes) 1132system.cpu.toL2Bus.pkt_count::total 11465064 # Packet count per connected master and slave (bytes) 1133system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185683904 # Cumulative packet size per connected master and slave (bytes) 1134system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98756893 # Cumulative packet size per connected master and slave (bytes) 1135system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18604 # Cumulative packet size per connected master and slave (bytes) 1136system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 288828 # Cumulative packet size per connected master and slave (bytes) 1137system.cpu.toL2Bus.pkt_size::total 284748229 # Cumulative packet size per connected master and slave (bytes) 1138system.cpu.toL2Bus.snoops 192861 # Total snoops (count) 1139system.cpu.toL2Bus.snoop_fanout::samples 7812074 # Request fanout histogram 1140system.cpu.toL2Bus.snoop_fanout::mean 0.018867 # Request fanout histogram 1141system.cpu.toL2Bus.snoop_fanout::stdev 0.136054 # Request fanout histogram |
| 1139system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1142system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1140system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1141system.cpu.toL2Bus.snoop_fanout::1 7545321 96.55% 96.55% # Request fanout histogram 1142system.cpu.toL2Bus.snoop_fanout::2 269220 3.45% 100.00% # Request fanout histogram | 1143system.cpu.toL2Bus.snoop_fanout::0 7664687 98.11% 98.11% # Request fanout histogram 1144system.cpu.toL2Bus.snoop_fanout::1 147387 1.89% 100.00% # Request fanout histogram 1145system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram |
| 1143system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1146system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1144system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1145system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1146system.cpu.toL2Bus.snoop_fanout::total 7814541 # Request fanout histogram 1147system.cpu.toL2Bus.reqLayer0.occupancy 4535355500 # Layer occupancy (ticks) | 1147system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1148system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1149system.cpu.toL2Bus.snoop_fanout::total 7812074 # Request fanout histogram 1150system.cpu.toL2Bus.reqLayer0.occupancy 4533598000 # Layer occupancy (ticks) |
| 1148system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) | 1151system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) |
| 1149system.cpu.toL2Bus.snoopLayer0.occupancy 213000 # Layer occupancy (ticks) | 1152system.cpu.toL2Bus.snoopLayer0.occupancy 377377 # Layer occupancy (ticks) |
| 1150system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1153system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1151system.cpu.toL2Bus.respLayer0.occupancy 4349852430 # Layer occupancy (ticks) | 1154system.cpu.toL2Bus.respLayer0.occupancy 4352382759 # Layer occupancy (ticks) |
| 1152system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) | 1155system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) |
| 1153system.cpu.toL2Bus.respLayer1.occupancy 1312899273 # Layer occupancy (ticks) | 1156system.cpu.toL2Bus.respLayer1.occupancy 1308632806 # Layer occupancy (ticks) |
| 1154system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1157system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1155system.cpu.toL2Bus.respLayer2.occupancy 10586000 # Layer occupancy (ticks) | 1158system.cpu.toL2Bus.respLayer2.occupancy 10576000 # Layer occupancy (ticks) |
| 1156system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1159system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1157system.cpu.toL2Bus.respLayer3.occupancy 88739000 # Layer occupancy (ticks) | 1160system.cpu.toL2Bus.respLayer3.occupancy 89410974 # Layer occupancy (ticks) |
| 1158system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1159system.iobus.trans_dist::ReadReq 30183 # Transaction distribution 1160system.iobus.trans_dist::ReadResp 30183 # Transaction distribution 1161system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1162system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1163system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1164system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1165system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 79 unchanged lines hidden (view full) --- 1245system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1246system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1247system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1248system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1249system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1250system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1251system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1252system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 1161system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1162system.iobus.trans_dist::ReadReq 30183 # Transaction distribution 1163system.iobus.trans_dist::ReadResp 30183 # Transaction distribution 1164system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1165system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1166system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1167system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1168system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 79 unchanged lines hidden (view full) --- 1248system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1249system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1250system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1251system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1252system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1253system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1254system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1255system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 1253system.iobus.reqLayer27.occupancy 187477706 # Layer occupancy (ticks) | 1256system.iobus.reqLayer27.occupancy 186368011 # Layer occupancy (ticks) |
| 1254system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1255system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1256system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1257system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1258system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1259system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) 1260system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1261system.iocache.tags.replacements 36424 # number of replacements | 1257system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1258system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1259system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1260system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1261system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1262system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) 1263system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1264system.iocache.tags.replacements 36424 # number of replacements |
| 1262system.iocache.tags.tagsinuse 1.030922 # Cycle average of tags in use | 1265system.iocache.tags.tagsinuse 1.036757 # Cycle average of tags in use |
| 1263system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1264system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1265system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1266system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1267system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1268system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1266system.iocache.tags.warmup_cycle 270445541000 # Cycle when the warmup percentage was hit. 1267system.iocache.tags.occ_blocks::realview.ide 1.030922 # Average occupied blocks per requestor 1268system.iocache.tags.occ_percent::realview.ide 0.064433 # Average percentage of cache occupancy 1269system.iocache.tags.occ_percent::total 0.064433 # Average percentage of cache occupancy | 1269system.iocache.tags.warmup_cycle 274667845000 # Cycle when the warmup percentage was hit. 1270system.iocache.tags.occ_blocks::realview.ide 1.036757 # Average occupied blocks per requestor 1271system.iocache.tags.occ_percent::realview.ide 0.064797 # Average percentage of cache occupancy 1272system.iocache.tags.occ_percent::total 0.064797 # Average percentage of cache occupancy |
| 1270system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1271system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1272system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1273system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1274system.iocache.tags.data_accesses 328122 # Number of data accesses 1275system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1276system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1277system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1278system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1279system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses 1280system.iocache.demand_misses::total 234 # number of demand (read+write) misses 1281system.iocache.overall_misses::realview.ide 234 # number of overall misses 1282system.iocache.overall_misses::total 234 # number of overall misses | 1273system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1274system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1275system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1276system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1277system.iocache.tags.data_accesses 328122 # Number of data accesses 1278system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1279system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1280system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1281system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1282system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses 1283system.iocache.demand_misses::total 234 # number of demand (read+write) misses 1284system.iocache.overall_misses::realview.ide 234 # number of overall misses 1285system.iocache.overall_misses::total 234 # number of overall misses |
| 1283system.iocache.ReadReq_miss_latency::realview.ide 29161877 # number of ReadReq miss cycles 1284system.iocache.ReadReq_miss_latency::total 29161877 # number of ReadReq miss cycles 1285system.iocache.WriteLineReq_miss_latency::realview.ide 4273547829 # number of WriteLineReq miss cycles 1286system.iocache.WriteLineReq_miss_latency::total 4273547829 # number of WriteLineReq miss cycles 1287system.iocache.demand_miss_latency::realview.ide 29161877 # number of demand (read+write) miss cycles 1288system.iocache.demand_miss_latency::total 29161877 # number of demand (read+write) miss cycles 1289system.iocache.overall_miss_latency::realview.ide 29161877 # number of overall miss cycles 1290system.iocache.overall_miss_latency::total 29161877 # number of overall miss cycles | 1286system.iocache.ReadReq_miss_latency::realview.ide 29104877 # number of ReadReq miss cycles 1287system.iocache.ReadReq_miss_latency::total 29104877 # number of ReadReq miss cycles 1288system.iocache.WriteLineReq_miss_latency::realview.ide 4697807134 # number of WriteLineReq miss cycles 1289system.iocache.WriteLineReq_miss_latency::total 4697807134 # number of WriteLineReq miss cycles 1290system.iocache.demand_miss_latency::realview.ide 29104877 # number of demand (read+write) miss cycles 1291system.iocache.demand_miss_latency::total 29104877 # number of demand (read+write) miss cycles 1292system.iocache.overall_miss_latency::realview.ide 29104877 # number of overall miss cycles 1293system.iocache.overall_miss_latency::total 29104877 # number of overall miss cycles |
| 1291system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1292system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1293system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1294system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1295system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses 1296system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses 1297system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses 1298system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses 1299system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1300system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1301system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1302system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1303system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1304system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1305system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1306system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1294system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1295system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1296system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1297system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1298system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses 1299system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses 1300system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses 1301system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses 1302system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1303system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1304system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1305system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1306system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1307system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1308system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1309system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1307system.iocache.ReadReq_avg_miss_latency::realview.ide 124623.405983 # average ReadReq miss latency 1308system.iocache.ReadReq_avg_miss_latency::total 124623.405983 # average ReadReq miss latency 1309system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117975.591569 # average WriteLineReq miss latency 1310system.iocache.WriteLineReq_avg_miss_latency::total 117975.591569 # average WriteLineReq miss latency 1311system.iocache.demand_avg_miss_latency::realview.ide 124623.405983 # average overall miss latency 1312system.iocache.demand_avg_miss_latency::total 124623.405983 # average overall miss latency 1313system.iocache.overall_avg_miss_latency::realview.ide 124623.405983 # average overall miss latency 1314system.iocache.overall_avg_miss_latency::total 124623.405983 # average overall miss latency 1315system.iocache.blocked_cycles::no_mshrs 9 # number of cycles access was blocked | 1310system.iocache.ReadReq_avg_miss_latency::realview.ide 124379.816239 # average ReadReq miss latency 1311system.iocache.ReadReq_avg_miss_latency::total 124379.816239 # average ReadReq miss latency 1312system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129687.696941 # average WriteLineReq miss latency 1313system.iocache.WriteLineReq_avg_miss_latency::total 129687.696941 # average WriteLineReq miss latency 1314system.iocache.demand_avg_miss_latency::realview.ide 124379.816239 # average overall miss latency 1315system.iocache.demand_avg_miss_latency::total 124379.816239 # average overall miss latency 1316system.iocache.overall_avg_miss_latency::realview.ide 124379.816239 # average overall miss latency 1317system.iocache.overall_avg_miss_latency::total 124379.816239 # average overall miss latency 1318system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 1316system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1319system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1317system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked | 1320system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 1318system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1321system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1319system.iocache.avg_blocked_cycles::no_mshrs 4.500000 # average number of cycles each access was blocked | 1322system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 1320system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1321system.iocache.fast_writes 0 # number of fast writes performed 1322system.iocache.cache_copies 0 # number of cache copies performed 1323system.iocache.writebacks::writebacks 36190 # number of writebacks 1324system.iocache.writebacks::total 36190 # number of writebacks 1325system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1326system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1327system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1328system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 1329system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses 1330system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses 1331system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses 1332system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses | 1323system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1324system.iocache.fast_writes 0 # number of fast writes performed 1325system.iocache.cache_copies 0 # number of cache copies performed 1326system.iocache.writebacks::writebacks 36190 # number of writebacks 1327system.iocache.writebacks::total 36190 # number of writebacks 1328system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1329system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1330system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1331system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 1332system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses 1333system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses 1334system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses 1335system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses |
| 1333system.iocache.ReadReq_mshr_miss_latency::realview.ide 17461877 # number of ReadReq MSHR miss cycles 1334system.iocache.ReadReq_mshr_miss_latency::total 17461877 # number of ReadReq MSHR miss cycles 1335system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2462347829 # number of WriteLineReq MSHR miss cycles 1336system.iocache.WriteLineReq_mshr_miss_latency::total 2462347829 # number of WriteLineReq MSHR miss cycles 1337system.iocache.demand_mshr_miss_latency::realview.ide 17461877 # number of demand (read+write) MSHR miss cycles 1338system.iocache.demand_mshr_miss_latency::total 17461877 # number of demand (read+write) MSHR miss cycles 1339system.iocache.overall_mshr_miss_latency::realview.ide 17461877 # number of overall MSHR miss cycles 1340system.iocache.overall_mshr_miss_latency::total 17461877 # number of overall MSHR miss cycles | 1336system.iocache.ReadReq_mshr_miss_latency::realview.ide 17404877 # number of ReadReq MSHR miss cycles 1337system.iocache.ReadReq_mshr_miss_latency::total 17404877 # number of ReadReq MSHR miss cycles 1338system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886607134 # number of WriteLineReq MSHR miss cycles 1339system.iocache.WriteLineReq_mshr_miss_latency::total 2886607134 # number of WriteLineReq MSHR miss cycles 1340system.iocache.demand_mshr_miss_latency::realview.ide 17404877 # number of demand (read+write) MSHR miss cycles 1341system.iocache.demand_mshr_miss_latency::total 17404877 # number of demand (read+write) MSHR miss cycles 1342system.iocache.overall_mshr_miss_latency::realview.ide 17404877 # number of overall MSHR miss cycles 1343system.iocache.overall_mshr_miss_latency::total 17404877 # number of overall MSHR miss cycles |
| 1341system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1342system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1343system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1344system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1345system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1346system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1347system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1348system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1344system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1345system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1346system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1347system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1348system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1349system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1350system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1351system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1349system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74623.405983 # average ReadReq mshr miss latency 1350system.iocache.ReadReq_avg_mshr_miss_latency::total 74623.405983 # average ReadReq mshr miss latency 1351system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67975.591569 # average WriteLineReq mshr miss latency 1352system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67975.591569 # average WriteLineReq mshr miss latency 1353system.iocache.demand_avg_mshr_miss_latency::realview.ide 74623.405983 # average overall mshr miss latency 1354system.iocache.demand_avg_mshr_miss_latency::total 74623.405983 # average overall mshr miss latency 1355system.iocache.overall_avg_mshr_miss_latency::realview.ide 74623.405983 # average overall mshr miss latency 1356system.iocache.overall_avg_mshr_miss_latency::total 74623.405983 # average overall mshr miss latency | 1352system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74379.816239 # average ReadReq mshr miss latency 1353system.iocache.ReadReq_avg_mshr_miss_latency::total 74379.816239 # average ReadReq mshr miss latency 1354system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79687.696941 # average WriteLineReq mshr miss latency 1355system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79687.696941 # average WriteLineReq mshr miss latency 1356system.iocache.demand_avg_mshr_miss_latency::realview.ide 74379.816239 # average overall mshr miss latency 1357system.iocache.demand_avg_mshr_miss_latency::total 74379.816239 # average overall mshr miss latency 1358system.iocache.overall_avg_mshr_miss_latency::realview.ide 74379.816239 # average overall mshr miss latency 1359system.iocache.overall_avg_mshr_miss_latency::total 74379.816239 # average overall mshr miss latency |
| 1357system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1360system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1358system.membus.trans_dist::ReadReq 34319 # Transaction distribution 1359system.membus.trans_dist::ReadResp 71793 # Transaction distribution | 1361system.membus.trans_dist::ReadReq 34618 # Transaction distribution 1362system.membus.trans_dist::ReadResp 71995 # Transaction distribution |
| 1360system.membus.trans_dist::WriteReq 27583 # Transaction distribution 1361system.membus.trans_dist::WriteResp 27583 # Transaction distribution | 1363system.membus.trans_dist::WriteReq 27583 # Transaction distribution 1364system.membus.trans_dist::WriteResp 27583 # Transaction distribution |
| 1362system.membus.trans_dist::Writeback 124709 # Transaction distribution 1363system.membus.trans_dist::CleanEvict 8498 # Transaction distribution 1364system.membus.trans_dist::UpgradeReq 4604 # Transaction distribution | 1365system.membus.trans_dist::Writeback 124156 # Transaction distribution 1366system.membus.trans_dist::CleanEvict 8653 # Transaction distribution 1367system.membus.trans_dist::UpgradeReq 4582 # Transaction distribution |
| 1365system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution | 1368system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution |
| 1366system.membus.trans_dist::UpgradeResp 4606 # Transaction distribution 1367system.membus.trans_dist::ReadExReq 129599 # Transaction distribution 1368system.membus.trans_dist::ReadExResp 129599 # Transaction distribution 1369system.membus.trans_dist::ReadSharedReq 37474 # Transaction distribution | 1369system.membus.trans_dist::UpgradeResp 4584 # Transaction distribution 1370system.membus.trans_dist::ReadExReq 129275 # Transaction distribution 1371system.membus.trans_dist::ReadExResp 129275 # Transaction distribution 1372system.membus.trans_dist::ReadSharedReq 37377 # Transaction distribution |
| 1370system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1371system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 1372system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1373system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) 1374system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) | 1373system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1374system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 1375system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1376system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) 1377system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) |
| 1375system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455849 # Packet count per connected master and slave (bytes) 1376system.membus.pkt_count_system.cpu.l2cache.mem_side::total 563411 # Packet count per connected master and slave (bytes) | 1378system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455163 # Packet count per connected master and slave (bytes) 1379system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562725 # Packet count per connected master and slave (bytes) |
| 1377system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes) 1378system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes) | 1380system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes) 1381system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes) |
| 1379system.membus.pkt_count::total 672311 # Packet count per connected master and slave (bytes) | 1382system.membus.pkt_count::total 671625 # Packet count per connected master and slave (bytes) |
| 1380system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1381system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) 1382system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) | 1383system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1384system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) 1385system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) |
| 1383system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16548192 # Cumulative packet size per connected master and slave (bytes) 1384system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16711965 # Cumulative packet size per connected master and slave (bytes) | 1386system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16504992 # Cumulative packet size per connected master and slave (bytes) 1387system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16668765 # Cumulative packet size per connected master and slave (bytes) |
| 1385system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1386system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) | 1388system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1389system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) |
| 1387system.membus.pkt_size::total 19029085 # Cumulative packet size per connected master and slave (bytes) | 1390system.membus.pkt_size::total 18985885 # Cumulative packet size per connected master and slave (bytes) |
| 1388system.membus.snoops 506 # Total snoops (count) | 1391system.membus.snoops 506 # Total snoops (count) |
| 1389system.membus.snoop_fanout::samples 403242 # Request fanout histogram | 1392system.membus.snoop_fanout::samples 402707 # Request fanout histogram |
| 1390system.membus.snoop_fanout::mean 1 # Request fanout histogram 1391system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1392system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1393system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1393system.membus.snoop_fanout::mean 1 # Request fanout histogram 1394system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1395system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1396system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1394system.membus.snoop_fanout::1 403242 100.00% 100.00% # Request fanout histogram | 1397system.membus.snoop_fanout::1 402707 100.00% 100.00% # Request fanout histogram |
| 1395system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1396system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1397system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1398system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1398system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1399system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1400system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1401system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1399system.membus.snoop_fanout::total 403242 # Request fanout histogram 1400system.membus.reqLayer0.occupancy 87534500 # Layer occupancy (ticks) | 1402system.membus.snoop_fanout::total 402707 # Request fanout histogram 1403system.membus.reqLayer0.occupancy 87547000 # Layer occupancy (ticks) |
| 1401system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1402system.membus.reqLayer1.occupancy 8500 # Layer occupancy (ticks) 1403system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1404system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1405system.membus.reqLayer1.occupancy 8500 # Layer occupancy (ticks) 1406system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1404system.membus.reqLayer2.occupancy 1700500 # Layer occupancy (ticks) | 1407system.membus.reqLayer2.occupancy 1701500 # Layer occupancy (ticks) |
| 1405system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1408system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1406system.membus.reqLayer5.occupancy 881620222 # Layer occupancy (ticks) | 1409system.membus.reqLayer5.occupancy 878616291 # Layer occupancy (ticks) |
| 1407system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 1410system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 1408system.membus.respLayer2.occupancy 999181641 # Layer occupancy (ticks) | 1411system.membus.respLayer2.occupancy 998538415 # Layer occupancy (ticks) |
| 1409system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1412system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1410system.membus.respLayer3.occupancy 64440498 # Layer occupancy (ticks) | 1413system.membus.respLayer3.occupancy 64594078 # Layer occupancy (ticks) |
| 1411system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1412system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1413system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1414system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1415system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1416system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1417system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1418system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 36 unchanged lines hidden --- | 1414system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1415system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1416system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1417system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1418system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1419system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1420system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1421system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 36 unchanged lines hidden --- |