| stats.txt (10517:ba51f8572571) | stats.txt (10535:4ccec5baf82c) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.852223 # Number of seconds simulated 4sim_ticks 2852222670000 # Number of ticks simulated 5final_tick 2852222670000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.852237 # Number of seconds simulated 4sim_ticks 2852237227000 # Number of ticks simulated 5final_tick 2852237227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 166317 # Simulator instruction rate (inst/s) 8host_op_rate 201081 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4259610797 # Simulator tick rate (ticks/s) 10host_mem_usage 558772 # Number of bytes of host memory used 11host_seconds 669.60 # Real time elapsed on the host 12sim_insts 111365458 # Number of instructions simulated 13sim_ops 134642914 # Number of ops (including micro ops) simulated | 7host_inst_rate 157725 # Simulator instruction rate (inst/s) 8host_op_rate 190692 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4039440180 # Simulator tick rate (ticks/s) 10host_mem_usage 566224 # Number of bytes of host memory used 11host_seconds 706.10 # Real time elapsed on the host 12sim_insts 111368950 # Number of instructions simulated 13sim_ops 134647110 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.dtb.walker 6208 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 10897572 # Number of bytes read from this memory |
|
| 16system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 19system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.dtb.walker 6464 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 10896868 # Number of bytes read from this memory 20system.physmem.bytes_read::total 10904484 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 1667584 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 1667584 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 5681792 # Number of bytes written to this memory 24system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory | 20system.physmem.bytes_read::total 10904868 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 1667392 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 1667392 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 5682816 # Number of bytes written to this memory |
| 25system.physmem.bytes_written::cpu.inst 17524 # Number of bytes written to this memory | 24system.physmem.bytes_written::cpu.inst 17524 # Number of bytes written to this memory |
| 26system.physmem.bytes_written::total 8017652 # Number of bytes written to this memory | 25system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 26system.physmem.bytes_written::total 8018676 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 97 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 170794 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 30system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::cpu.dtb.walker 101 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 170783 # Number of read requests responded to by this memory 31system.physmem.num_reads::total 170902 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 88778 # Number of write requests responded to by this memory 33system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory | 31system.physmem.num_reads::total 170908 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 88794 # Number of write requests responded to by this memory |
| 34system.physmem.num_writes::cpu.inst 4381 # Number of write requests responded to by this memory | 33system.physmem.num_writes::cpu.inst 4381 # Number of write requests responded to by this memory |
| 35system.physmem.num_writes::total 129383 # Number of write requests responded to by this memory | 34system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 129399 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 2177 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 3820710 # Total read bandwidth from this memory (bytes/s) |
| 36system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) | 39system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) |
| 37system.physmem.bw_read::cpu.dtb.walker 2266 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 67 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 3820483 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::total 3823153 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu.inst 584661 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::total 584661 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_write::writebacks 1992058 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::realview.ide 812817 # Write bandwidth from this memory (bytes/s) | 40system.physmem.bw_read::total 3823268 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu.inst 584591 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::total 584591 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_write::writebacks 1992407 # Write bandwidth from this memory (bytes/s) |
| 45system.physmem.bw_write::cpu.inst 6144 # Write bandwidth from this memory (bytes/s) | 44system.physmem.bw_write::cpu.inst 6144 # Write bandwidth from this memory (bytes/s) |
| 46system.physmem.bw_write::total 2811019 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1992058 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::realview.ide 813154 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 2266 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 67 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 3826627 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::total 6634172 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 170902 # Number of read requests accepted 54system.physmem.writeReqs 129383 # Number of write requests accepted 55system.physmem.readBursts 170902 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 129383 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 10927488 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 10240 # Total number of bytes read from write queue 59system.physmem.bytesWritten 8031232 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 10904484 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 8017652 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 160 # Number of DRAM read bursts serviced by the write queue | 45system.physmem.bw_write::realview.ide 812813 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2811364 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1992407 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 2177 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 3826854 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::realview.ide 813150 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::total 6634632 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 170908 # Number of read requests accepted 54system.physmem.writeReqs 129399 # Number of write requests accepted 55system.physmem.readBursts 170908 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 129399 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 10927552 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 10560 # Total number of bytes read from write queue 59system.physmem.bytesWritten 8032256 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 10904868 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 8018676 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 165 # Number of DRAM read bursts serviced by the write queue |
| 63system.physmem.mergedWrBursts 3869 # Number of DRAM write bursts merged with an existing one | 63system.physmem.mergedWrBursts 3869 # Number of DRAM write bursts merged with an existing one |
| 64system.physmem.neitherReadNorWriteReqs 4593 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 10513 # Per bank write bursts 66system.physmem.perBankRdBursts::1 10240 # Per bank write bursts 67system.physmem.perBankRdBursts::2 10772 # Per bank write bursts 68system.physmem.perBankRdBursts::3 10550 # Per bank write bursts 69system.physmem.perBankRdBursts::4 13501 # Per bank write bursts 70system.physmem.perBankRdBursts::5 10124 # Per bank write bursts 71system.physmem.perBankRdBursts::6 11177 # Per bank write bursts 72system.physmem.perBankRdBursts::7 10891 # Per bank write bursts 73system.physmem.perBankRdBursts::8 10227 # Per bank write bursts 74system.physmem.perBankRdBursts::9 10892 # Per bank write bursts 75system.physmem.perBankRdBursts::10 10093 # Per bank write bursts 76system.physmem.perBankRdBursts::11 9609 # Per bank write bursts 77system.physmem.perBankRdBursts::12 10331 # Per bank write bursts 78system.physmem.perBankRdBursts::13 11217 # Per bank write bursts 79system.physmem.perBankRdBursts::14 10288 # Per bank write bursts 80system.physmem.perBankRdBursts::15 10317 # Per bank write bursts | 64system.physmem.neitherReadNorWriteReqs 4597 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 10514 # Per bank write bursts 66system.physmem.perBankRdBursts::1 10246 # Per bank write bursts 67system.physmem.perBankRdBursts::2 10769 # Per bank write bursts 68system.physmem.perBankRdBursts::3 10552 # Per bank write bursts 69system.physmem.perBankRdBursts::4 13499 # Per bank write bursts 70system.physmem.perBankRdBursts::5 10126 # Per bank write bursts 71system.physmem.perBankRdBursts::6 11178 # Per bank write bursts 72system.physmem.perBankRdBursts::7 10889 # Per bank write bursts 73system.physmem.perBankRdBursts::8 10228 # Per bank write bursts 74system.physmem.perBankRdBursts::9 10887 # Per bank write bursts 75system.physmem.perBankRdBursts::10 10100 # Per bank write bursts 76system.physmem.perBankRdBursts::11 9610 # Per bank write bursts 77system.physmem.perBankRdBursts::12 10315 # Per bank write bursts 78system.physmem.perBankRdBursts::13 11222 # Per bank write bursts 79system.physmem.perBankRdBursts::14 10292 # Per bank write bursts 80system.physmem.perBankRdBursts::15 10316 # Per bank write bursts |
| 81system.physmem.perBankWrBursts::0 7730 # Per bank write bursts | 81system.physmem.perBankWrBursts::0 7730 # Per bank write bursts |
| 82system.physmem.perBankWrBursts::1 7662 # Per bank write bursts 83system.physmem.perBankWrBursts::2 8408 # Per bank write bursts 84system.physmem.perBankWrBursts::3 8127 # Per bank write bursts 85system.physmem.perBankWrBursts::4 7860 # Per bank write bursts | 82system.physmem.perBankWrBursts::1 7667 # Per bank write bursts 83system.physmem.perBankWrBursts::2 8410 # Per bank write bursts 84system.physmem.perBankWrBursts::3 8128 # Per bank write bursts 85system.physmem.perBankWrBursts::4 7856 # Per bank write bursts |
| 86system.physmem.perBankWrBursts::5 7340 # Per bank write bursts | 86system.physmem.perBankWrBursts::5 7340 # Per bank write bursts |
| 87system.physmem.perBankWrBursts::6 8206 # Per bank write bursts 88system.physmem.perBankWrBursts::7 8039 # Per bank write bursts 89system.physmem.perBankWrBursts::8 7784 # Per bank write bursts 90system.physmem.perBankWrBursts::9 8077 # Per bank write bursts 91system.physmem.perBankWrBursts::10 7518 # Per bank write bursts | 87system.physmem.perBankWrBursts::6 8209 # Per bank write bursts 88system.physmem.perBankWrBursts::7 8042 # Per bank write bursts 89system.physmem.perBankWrBursts::8 7786 # Per bank write bursts 90system.physmem.perBankWrBursts::9 8073 # Per bank write bursts 91system.physmem.perBankWrBursts::10 7525 # Per bank write bursts |
| 92system.physmem.perBankWrBursts::11 7421 # Per bank write bursts | 92system.physmem.perBankWrBursts::11 7421 # Per bank write bursts |
| 93system.physmem.perBankWrBursts::12 7767 # Per bank write bursts 94system.physmem.perBankWrBursts::13 8402 # Per bank write bursts 95system.physmem.perBankWrBursts::14 7544 # Per bank write bursts | 93system.physmem.perBankWrBursts::12 7760 # Per bank write bursts 94system.physmem.perBankWrBursts::13 8405 # Per bank write bursts 95system.physmem.perBankWrBursts::14 7549 # Per bank write bursts |
| 96system.physmem.perBankWrBursts::15 7603 # Per bank write bursts 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 96system.physmem.perBankWrBursts::15 7603 # Per bank write bursts 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 98system.physmem.numWrRetry 10 # Number of times write queue was full causing retry 99system.physmem.totGap 2852222186000 # Total gap between requests | 98system.physmem.numWrRetry 1 # Number of times write queue was full causing retry 99system.physmem.totGap 2852236741500 # Total gap between requests |
| 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 541 # Read request sizes (log2) 103system.physmem.readPktSize::3 14 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2) | 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 541 # Read request sizes (log2) 103system.physmem.readPktSize::3 14 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 106system.physmem.readPktSize::6 170347 # Read request sizes (log2) | 106system.physmem.readPktSize::6 170353 # Read request sizes (log2) |
| 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 4381 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2) | 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 4381 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 113system.physmem.writePktSize::6 125002 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 164585 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 6110 # What read queue length does an incoming req see | 113system.physmem.writePktSize::6 125018 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 164527 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 6169 # What read queue length does an incoming req see |
| 116system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 116system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 161system.physmem.wrQLenPdf::15 1982 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 2519 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 6120 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 6597 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::19 6634 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::20 7213 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 7428 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 7985 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 8522 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 9334 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 8728 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 8242 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 7692 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 7486 # What write queue length does an incoming req see | 161system.physmem.wrQLenPdf::15 1957 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 2508 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 6099 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 6612 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::19 6647 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::20 7189 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 7393 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 7933 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 8489 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 9295 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 8700 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 8234 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 7658 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 7495 # What write queue length does an incoming req see |
| 175system.physmem.wrQLenPdf::29 6726 # What write queue length does an incoming req see | 175system.physmem.wrQLenPdf::29 6726 # What write queue length does an incoming req see |
| 176system.physmem.wrQLenPdf::30 6557 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 6577 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 6482 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 199 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 169 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 170 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 123 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 118 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 118 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 128 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 116 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 126 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 132 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 123 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 114 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 104 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 47 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see | 176system.physmem.wrQLenPdf::30 6543 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 6568 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 6500 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 212 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 209 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 203 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 177 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 179 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 174 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 155 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 154 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 113 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 114 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 125 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 109 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 102 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 79 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 51 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::53 42 # What write queue length does an incoming req see |
| 200system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see | 200system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see |
| 201system.physmem.wrQLenPdf::55 33 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 11 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 60830 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 311.666217 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 184.364711 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 329.290387 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 22259 36.59% 36.59% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 14417 23.70% 60.29% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 6771 11.13% 71.42% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 3560 5.85% 77.28% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 2627 4.32% 81.59% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 1563 2.57% 84.16% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 1081 1.78% 85.94% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 1081 1.78% 87.72% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 7471 12.28% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 60830 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 6311 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 27.051339 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 576.967682 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-2047 6309 99.97% 99.97% # Reads before turning the bus around for writes | 201system.physmem.wrQLenPdf::55 30 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 35 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 34 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 60829 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 311.689227 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 184.313026 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 329.369125 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 22276 36.62% 36.62% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 14416 23.70% 60.32% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 6737 11.08% 71.40% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 3572 5.87% 77.27% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 2597 4.27% 81.54% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 1607 2.64% 84.18% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 1084 1.78% 85.96% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 1076 1.77% 87.73% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 7464 12.27% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 60829 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 6321 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 27.008859 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 576.510415 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-2047 6319 99.97% 99.97% # Reads before turning the bus around for writes |
| 228system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes | 228system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 230system.physmem.rdPerTurnAround::total 6311 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 6311 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 19.884012 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 18.375867 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 11.802704 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-19 5533 87.67% 87.67% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::20-23 35 0.55% 88.23% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-27 30 0.48% 88.70% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-31 215 3.41% 92.11% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-35 199 3.15% 95.26% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::36-39 15 0.24% 95.50% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-43 17 0.27% 95.77% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::44-47 19 0.30% 96.07% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::48-51 19 0.30% 96.37% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::52-55 6 0.10% 96.47% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::56-59 3 0.05% 96.51% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::60-63 4 0.06% 96.58% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-67 155 2.46% 99.03% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::68-71 5 0.08% 99.11% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::72-75 6 0.10% 99.21% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::76-79 3 0.05% 99.26% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::80-83 12 0.19% 99.45% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::84-87 2 0.03% 99.48% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::92-95 1 0.02% 99.52% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::96-99 7 0.11% 99.64% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::100-103 1 0.02% 99.65% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::104-107 3 0.05% 99.70% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::108-111 1 0.02% 99.71% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::112-115 5 0.08% 99.79% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::116-119 2 0.03% 99.83% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::124-127 1 0.02% 99.84% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::128-131 6 0.10% 99.94% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::136-139 1 0.02% 99.95% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::140-143 3 0.05% 100.00% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::total 6311 # Writes before turning the bus around for reads 266system.physmem.totQLat 1715938250 # Total ticks spent queuing 267system.physmem.totMemAccLat 4917350750 # Total ticks spent from burst creation until serviced by the DRAM 268system.physmem.totBusLat 853710000 # Total ticks spent in databus transfers 269system.physmem.avgQLat 10049.89 # Average queueing delay per DRAM burst | 230system.physmem.rdPerTurnAround::total 6321 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 6321 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 19.855086 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 18.377929 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 11.560499 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-19 5522 87.36% 87.36% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::20-23 41 0.65% 88.01% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-27 34 0.54% 88.55% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-31 217 3.43% 91.98% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-35 214 3.39% 95.36% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::36-39 10 0.16% 95.52% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-43 16 0.25% 95.78% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::44-47 20 0.32% 96.09% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::48-51 24 0.38% 96.47% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::52-55 4 0.06% 96.54% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::56-59 2 0.03% 96.57% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::60-63 2 0.03% 96.60% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-67 162 2.56% 99.16% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::68-71 4 0.06% 99.22% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::72-75 5 0.08% 99.30% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::76-79 3 0.05% 99.35% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::80-83 12 0.19% 99.54% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::84-87 1 0.02% 99.56% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::88-91 1 0.02% 99.57% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::96-99 7 0.11% 99.68% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::104-107 2 0.03% 99.72% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::108-111 1 0.02% 99.73% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::112-115 5 0.08% 99.81% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::120-123 2 0.03% 99.84% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::124-127 1 0.02% 99.86% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::128-131 7 0.11% 99.97% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::136-139 1 0.02% 99.98% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::140-143 1 0.02% 100.00% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::total 6321 # Writes before turning the bus around for reads 264system.physmem.totQLat 1722371500 # Total ticks spent queuing 265system.physmem.totMemAccLat 4923802750 # Total ticks spent from burst creation until serviced by the DRAM 266system.physmem.totBusLat 853715000 # Total ticks spent in databus transfers 267system.physmem.avgQLat 10087.51 # Average queueing delay per DRAM burst |
| 270system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 268system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 271system.physmem.avgMemAccLat 28799.89 # Average memory access latency per DRAM burst | 269system.physmem.avgMemAccLat 28837.51 # Average memory access latency per DRAM burst |
| 272system.physmem.avgRdBW 3.83 # Average DRAM read bandwidth in MiByte/s 273system.physmem.avgWrBW 2.82 # Average achieved write bandwidth in MiByte/s 274system.physmem.avgRdBWSys 3.82 # Average system read bandwidth in MiByte/s 275system.physmem.avgWrBWSys 2.81 # Average system write bandwidth in MiByte/s 276system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 277system.physmem.busUtil 0.05 # Data bus utilization in percentage 278system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 279system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 280system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 270system.physmem.avgRdBW 3.83 # Average DRAM read bandwidth in MiByte/s 271system.physmem.avgWrBW 2.82 # Average achieved write bandwidth in MiByte/s 272system.physmem.avgRdBWSys 3.82 # Average system read bandwidth in MiByte/s 273system.physmem.avgWrBWSys 2.81 # Average system write bandwidth in MiByte/s 274system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 275system.physmem.busUtil 0.05 # Data bus utilization in percentage 276system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 277system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 278system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 281system.physmem.avgWrQLen 23.21 # Average write queue length when enqueuing 282system.physmem.readRowHits 140944 # Number of row buffer hits during reads 283system.physmem.writeRowHits 94455 # Number of row buffer hits during writes | 279system.physmem.avgWrQLen 26.39 # Average write queue length when enqueuing 280system.physmem.readRowHits 140948 # Number of row buffer hits during reads 281system.physmem.writeRowHits 94469 # Number of row buffer hits during writes |
| 284system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads | 282system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads |
| 285system.physmem.writeRowHitRate 75.25 # Row buffer hit rate for writes 286system.physmem.avgGap 9498383.82 # Average gap between requests | 283system.physmem.writeRowHitRate 75.26 # Row buffer hit rate for writes 284system.physmem.avgGap 9497736.45 # Average gap between requests |
| 287system.physmem.pageHitRate 79.46 # Row buffer hit rate, read and write combined | 285system.physmem.pageHitRate 79.46 # Row buffer hit rate, read and write combined |
| 288system.physmem.memoryStateTime::IDLE 2712510439500 # Time in different power states 289system.physmem.memoryStateTime::REF 95241900000 # Time in different power states | 286system.physmem.memoryStateTime::IDLE 2712717626000 # Time in different power states 287system.physmem.memoryStateTime::REF 95242420000 # Time in different power states |
| 290system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 288system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 291system.physmem.memoryStateTime::ACT 44470242000 # Time in different power states | 289system.physmem.memoryStateTime::ACT 44277091000 # Time in different power states |
| 292system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 290system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 293system.physmem.actEnergy::0 234798480 # Energy for activate commands per rank (pJ) 294system.physmem.actEnergy::1 225076320 # Energy for activate commands per rank (pJ) 295system.physmem.preEnergy::0 128114250 # Energy for precharge commands per rank (pJ) 296system.physmem.preEnergy::1 122809500 # Energy for precharge commands per rank (pJ) 297system.physmem.readEnergy::0 684590400 # Energy for read commands per rank (pJ) 298system.physmem.readEnergy::1 647189400 # Energy for read commands per rank (pJ) 299system.physmem.writeEnergy::0 410650560 # Energy for write commands per rank (pJ) 300system.physmem.writeEnergy::1 402511680 # Energy for write commands per rank (pJ) 301system.physmem.refreshEnergy::0 186293156400 # Energy for refresh commands per rank (pJ) 302system.physmem.refreshEnergy::1 186293156400 # Energy for refresh commands per rank (pJ) 303system.physmem.actBackEnergy::0 83147145165 # Energy for active background per rank (pJ) 304system.physmem.actBackEnergy::1 82654300080 # Energy for active background per rank (pJ) 305system.physmem.preBackEnergy::0 1638396165000 # Energy for precharge background per rank (pJ) 306system.physmem.preBackEnergy::1 1638828485250 # Energy for precharge background per rank (pJ) 307system.physmem.totalEnergy::0 1909294620255 # Total energy per rank (pJ) 308system.physmem.totalEnergy::1 1909173528630 # Total energy per rank (pJ) 309system.physmem.averagePower::0 669.406404 # Core power per rank (mW) 310system.physmem.averagePower::1 669.363949 # Core power per rank (mW) | 291system.physmem.actEnergy::0 234707760 # Energy for activate commands per rank (pJ) 292system.physmem.actEnergy::1 225159480 # Energy for activate commands per rank (pJ) 293system.physmem.preEnergy::0 128064750 # Energy for precharge commands per rank (pJ) 294system.physmem.preEnergy::1 122854875 # Energy for precharge commands per rank (pJ) 295system.physmem.readEnergy::0 684629400 # Energy for read commands per rank (pJ) 296system.physmem.readEnergy::1 647158200 # Energy for read commands per rank (pJ) 297system.physmem.writeEnergy::0 410715360 # Energy for write commands per rank (pJ) 298system.physmem.writeEnergy::1 402550560 # Energy for write commands per rank (pJ) 299system.physmem.refreshEnergy::0 186294173520 # Energy for refresh commands per rank (pJ) 300system.physmem.refreshEnergy::1 186294173520 # Energy for refresh commands per rank (pJ) 301system.physmem.actBackEnergy::0 83068916085 # Energy for active background per rank (pJ) 302system.physmem.actBackEnergy::1 82611072135 # Energy for active background per rank (pJ) 303system.physmem.preBackEnergy::0 1638474130500 # Energy for precharge background per rank (pJ) 304system.physmem.preBackEnergy::1 1638875748000 # Energy for precharge background per rank (pJ) 305system.physmem.totalEnergy::0 1909295337375 # Total energy per rank (pJ) 306system.physmem.totalEnergy::1 1909178716770 # Total energy per rank (pJ) 307system.physmem.averagePower::0 669.403001 # Core power per rank (mW) 308system.physmem.averagePower::1 669.362113 # Core power per rank (mW) |
| 311system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory 312system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 313system.realview.nvmem.bytes_inst_read::cpu.inst 448 # Number of instructions bytes read from this memory 314system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 315system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory 316system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 317system.realview.nvmem.bw_read::cpu.inst 157 # Total read bandwidth from this memory (bytes/s) 318system.realview.nvmem.bw_read::total 157 # Total read bandwidth from this memory (bytes/s) 319system.realview.nvmem.bw_inst_read::cpu.inst 157 # Instruction read bandwidth from this memory (bytes/s) 320system.realview.nvmem.bw_inst_read::total 157 # Instruction read bandwidth from this memory (bytes/s) 321system.realview.nvmem.bw_total::cpu.inst 157 # Total bandwidth to/from this memory (bytes/s) 322system.realview.nvmem.bw_total::total 157 # Total bandwidth to/from this memory (bytes/s) | 309system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory 310system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 311system.realview.nvmem.bytes_inst_read::cpu.inst 448 # Number of instructions bytes read from this memory 312system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 313system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory 314system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 315system.realview.nvmem.bw_read::cpu.inst 157 # Total read bandwidth from this memory (bytes/s) 316system.realview.nvmem.bw_read::total 157 # Total read bandwidth from this memory (bytes/s) 317system.realview.nvmem.bw_inst_read::cpu.inst 157 # Instruction read bandwidth from this memory (bytes/s) 318system.realview.nvmem.bw_inst_read::total 157 # Instruction read bandwidth from this memory (bytes/s) 319system.realview.nvmem.bw_total::cpu.inst 157 # Total bandwidth to/from this memory (bytes/s) 320system.realview.nvmem.bw_total::total 157 # Total bandwidth to/from this memory (bytes/s) |
| 323system.membus.trans_dist::ReadReq 71842 # Transaction distribution 324system.membus.trans_dist::ReadResp 71842 # Transaction distribution 325system.membus.trans_dist::WriteReq 27607 # Transaction distribution 326system.membus.trans_dist::WriteResp 27607 # Transaction distribution 327system.membus.trans_dist::Writeback 88778 # Transaction distribution 328system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 329system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 330system.membus.trans_dist::UpgradeReq 4591 # Transaction distribution 331system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 332system.membus.trans_dist::UpgradeResp 4593 # Transaction distribution 333system.membus.trans_dist::ReadExReq 129869 # Transaction distribution 334system.membus.trans_dist::ReadExResp 129869 # Transaction distribution 335system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) 336system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) 337system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) 338system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 448500 # Packet count per connected master and slave (bytes) 339system.membus.pkt_count_system.cpu.l2cache.mem_side::total 556132 # Packet count per connected master and slave (bytes) 340system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) 341system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) 342system.membus.pkt_count::total 628829 # Packet count per connected master and slave (bytes) 343system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) 344system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) 345system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) 346system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16602840 # Cumulative packet size per connected master and slave (bytes) 347system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16766621 # Cumulative packet size per connected master and slave (bytes) 348system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 349system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) 350system.membus.pkt_size::total 19085917 # Cumulative packet size per connected master and slave (bytes) 351system.membus.snoops 219 # Total snoops (count) 352system.membus.snoop_fanout::samples 297178 # Request fanout histogram 353system.membus.snoop_fanout::mean 1 # Request fanout histogram 354system.membus.snoop_fanout::stdev 0 # Request fanout histogram 355system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 356system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 357system.membus.snoop_fanout::1 297178 100.00% 100.00% # Request fanout histogram 358system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 359system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 360system.membus.snoop_fanout::min_value 1 # Request fanout histogram 361system.membus.snoop_fanout::max_value 1 # Request fanout histogram 362system.membus.snoop_fanout::total 297178 # Request fanout histogram 363system.membus.reqLayer0.occupancy 87065000 # Layer occupancy (ticks) 364system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 365system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) 366system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 367system.membus.reqLayer2.occupancy 1712000 # Layer occupancy (ticks) 368system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 369system.membus.reqLayer5.occupancy 1386132250 # Layer occupancy (ticks) 370system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 371system.membus.respLayer2.occupancy 1718569157 # Layer occupancy (ticks) 372system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 373system.membus.respLayer3.occupancy 38335749 # Layer occupancy (ticks) 374system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 375system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 376system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 377system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 378system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 379system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 380system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 381system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 382system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 383system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 384system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 385system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 386system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 387system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 388system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 389system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 390system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 391system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 392system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 393system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 394system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 395system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 396system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 397system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 398system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 399system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 400system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 401system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 402system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 403system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 404system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 405system.realview.ethernet.droppedPackets 0 # number of packets dropped | |
| 406system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 407system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 408system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 409system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 410system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 411system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 321system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 322system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 323system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 324system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 325system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 326system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 412system.iobus.trans_dist::ReadReq 30195 # Transaction distribution 413system.iobus.trans_dist::ReadResp 30195 # Transaction distribution 414system.iobus.trans_dist::WriteReq 59038 # Transaction distribution 415system.iobus.trans_dist::WriteResp 59038 # Transaction distribution 416system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) 417system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 418system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 419system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 420system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 421system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 422system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 423system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 424system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 425system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 426system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 427system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 428system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 429system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 430system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 431system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 432system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 433system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 434system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 435system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 436system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 437system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) 438system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) 439system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) 440system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) 441system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) 442system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 443system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 444system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 445system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 446system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 447system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 448system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 449system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 450system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 451system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 452system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 453system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 454system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 455system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 456system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 457system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 458system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 459system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 460system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 461system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 462system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) 463system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 464system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 465system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) 466system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) 467system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 468system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) 469system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 470system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 471system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 472system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 473system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 474system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 475system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 476system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) 477system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 478system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 479system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 480system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 481system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 482system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 483system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 484system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 485system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 486system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 487system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 488system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 489system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 490system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 491system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 492system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 493system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 494system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 495system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 496system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 497system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 498system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 499system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 500system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 501system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 502system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 503system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 504system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 505system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 506system.iobus.reqLayer27.occupancy 326584849 # Layer occupancy (ticks) 507system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 508system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 509system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 510system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) 511system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 512system.iobus.respLayer3.occupancy 36809251 # Layer occupancy (ticks) 513system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 514system.cpu_clk_domain.clock 500 # Clock period in ticks 515system.cpu.branchPred.lookups 30769128 # Number of BP lookups 516system.cpu.branchPred.condPredicted 16730733 # Number of conditional branches predicted 517system.cpu.branchPred.condIncorrect 2480939 # Number of conditional branches incorrect 518system.cpu.branchPred.BTBLookups 18423796 # Number of BTB lookups 519system.cpu.branchPred.BTBHits 13205412 # Number of BTB hits | 327system.cpu.branchPred.lookups 30773662 # Number of BP lookups 328system.cpu.branchPred.condPredicted 16735793 # Number of conditional branches predicted 329system.cpu.branchPred.condIncorrect 2481146 # Number of conditional branches incorrect 330system.cpu.branchPred.BTBLookups 18414792 # Number of BTB lookups 331system.cpu.branchPred.BTBHits 13204104 # Number of BTB hits |
| 520system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 332system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 521system.cpu.branchPred.BTBHitPct 71.675848 # BTB Hit Percentage 522system.cpu.branchPred.usedRAS 7765211 # Number of times the RAS was used to get a target. 523system.cpu.branchPred.RASInCorrect 1476374 # Number of incorrect RAS predictions. | 333system.cpu.branchPred.BTBHitPct 71.703791 # BTB Hit Percentage 334system.cpu.branchPred.usedRAS 7765871 # Number of times the RAS was used to get a target. 335system.cpu.branchPred.RASInCorrect 1476448 # Number of incorrect RAS predictions. 336system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 524system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 525system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 526system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 527system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 528system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 529system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 530system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 531system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 539system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 540system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 541system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 542system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 543system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 544system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 545system.cpu.dtb.inst_hits 0 # ITB inst hits 546system.cpu.dtb.inst_misses 0 # ITB inst misses | 337system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 338system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 339system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 340system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 341system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 342system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 343system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 344system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 352system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 353system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 354system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 355system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 356system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 357system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 358system.cpu.dtb.inst_hits 0 # ITB inst hits 359system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 547system.cpu.dtb.read_hits 24572928 # DTB read hits 548system.cpu.dtb.read_misses 58429 # DTB read misses 549system.cpu.dtb.write_hits 19368405 # DTB write hits 550system.cpu.dtb.write_misses 5913 # DTB write misses | 360system.cpu.dtb.read_hits 24574985 # DTB read hits 361system.cpu.dtb.read_misses 58557 # DTB read misses 362system.cpu.dtb.write_hits 19368965 # DTB write hits 363system.cpu.dtb.write_misses 5915 # DTB write misses |
| 551system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 552system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 553system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 554system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 364system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 365system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 366system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 367system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 555system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB 556system.cpu.dtb.align_faults 1245 # Number of TLB faults due to alignment restrictions 557system.cpu.dtb.prefetch_faults 1816 # Number of TLB faults due to prefetch | 368system.cpu.dtb.flush_entries 4353 # Number of entries that have been flushed from TLB 369system.cpu.dtb.align_faults 1231 # Number of TLB faults due to alignment restrictions 370system.cpu.dtb.prefetch_faults 1821 # Number of TLB faults due to prefetch |
| 558system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 371system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 559system.cpu.dtb.perms_faults 752 # Number of TLB faults due to permissions restrictions 560system.cpu.dtb.read_accesses 24631357 # DTB read accesses 561system.cpu.dtb.write_accesses 19374318 # DTB write accesses | 372system.cpu.dtb.perms_faults 755 # Number of TLB faults due to permissions restrictions 373system.cpu.dtb.read_accesses 24633542 # DTB read accesses 374system.cpu.dtb.write_accesses 19374880 # DTB write accesses |
| 562system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 375system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 563system.cpu.dtb.hits 43941333 # DTB hits 564system.cpu.dtb.misses 64342 # DTB misses 565system.cpu.dtb.accesses 44005675 # DTB accesses | 376system.cpu.dtb.hits 43943950 # DTB hits 377system.cpu.dtb.misses 64472 # DTB misses 378system.cpu.dtb.accesses 44008422 # DTB accesses |
| 566system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 567system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 568system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 569system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 570system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 571system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 572system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 573system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 579system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 580system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 581system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 582system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 583system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 584system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 585system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 586system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 379system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 380system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 381system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 382system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 383system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 384system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 385system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 386system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 392system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 393system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 394system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 395system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 396system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 397system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 398system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 399system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 587system.cpu.itb.inst_hits 57038768 # ITB inst hits 588system.cpu.itb.inst_misses 5411 # ITB inst misses | 400system.cpu.itb.inst_hits 57039019 # ITB inst hits 401system.cpu.itb.inst_misses 5418 # ITB inst misses |
| 589system.cpu.itb.read_hits 0 # DTB read hits 590system.cpu.itb.read_misses 0 # DTB read misses 591system.cpu.itb.write_hits 0 # DTB write hits 592system.cpu.itb.write_misses 0 # DTB write misses 593system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 594system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 595system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 596system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 402system.cpu.itb.read_hits 0 # DTB read hits 403system.cpu.itb.read_misses 0 # DTB read misses 404system.cpu.itb.write_hits 0 # DTB write hits 405system.cpu.itb.write_misses 0 # DTB write misses 406system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 407system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 408system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 409system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 597system.cpu.itb.flush_entries 2977 # Number of entries that have been flushed from TLB | 410system.cpu.itb.flush_entries 2981 # Number of entries that have been flushed from TLB |
| 598system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 599system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 600system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 411system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 412system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 413system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 601system.cpu.itb.perms_faults 8664 # Number of TLB faults due to permissions restrictions | 414system.cpu.itb.perms_faults 8633 # Number of TLB faults due to permissions restrictions |
| 602system.cpu.itb.read_accesses 0 # DTB read accesses 603system.cpu.itb.write_accesses 0 # DTB write accesses | 415system.cpu.itb.read_accesses 0 # DTB read accesses 416system.cpu.itb.write_accesses 0 # DTB write accesses |
| 604system.cpu.itb.inst_accesses 57044179 # ITB inst accesses 605system.cpu.itb.hits 57038768 # DTB hits 606system.cpu.itb.misses 5411 # DTB misses 607system.cpu.itb.accesses 57044179 # DTB accesses 608system.cpu.numCycles 313347638 # number of cpu cycles simulated | 417system.cpu.itb.inst_accesses 57044437 # ITB inst accesses 418system.cpu.itb.hits 57039019 # DTB hits 419system.cpu.itb.misses 5418 # DTB misses 420system.cpu.itb.accesses 57044437 # DTB accesses 421system.cpu.numCycles 313379229 # number of cpu cycles simulated |
| 609system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 610system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 422system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 423system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 611system.cpu.committedInsts 111365458 # Number of instructions committed 612system.cpu.committedOps 134642914 # Number of ops (including micro ops) committed 613system.cpu.discardedOps 7897593 # Number of ops (including micro ops) which were discarded before commit | 424system.cpu.committedInsts 111368950 # Number of instructions committed 425system.cpu.committedOps 134647110 # Number of ops (including micro ops) committed 426system.cpu.discardedOps 7900477 # Number of ops (including micro ops) which were discarded before commit |
| 614system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching | 427system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching |
| 615system.cpu.quiesceCycles 5391144295 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 616system.cpu.cpi 2.813688 # CPI: cycles per instruction 617system.cpu.ipc 0.355405 # IPC: instructions per cycle | 428system.cpu.quiesceCycles 5391141904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 429system.cpu.cpi 2.813883 # CPI: cycles per instruction 430system.cpu.ipc 0.355381 # IPC: instructions per cycle |
| 618system.cpu.kern.inst.arm 0 # number of arm instructions executed 619system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed | 431system.cpu.kern.inst.arm 0 # number of arm instructions executed 432system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed |
| 620system.cpu.tickCycles 224151816 # Number of cycles that the object actually ticked 621system.cpu.idleCycles 89195822 # Total number of cycles that the object has spent stopped 622system.cpu.icache.tags.replacements 2897350 # number of replacements 623system.cpu.icache.tags.tagsinuse 511.427915 # Cycle average of tags in use 624system.cpu.icache.tags.total_refs 54131849 # Total number of references to valid blocks. 625system.cpu.icache.tags.sampled_refs 2897862 # Sample count of references to valid blocks. 626system.cpu.icache.tags.avg_refs 18.679926 # Average number of references to valid blocks. | 433system.cpu.tickCycles 224160135 # Number of cycles that the object actually ticked 434system.cpu.idleCycles 89219094 # Total number of cycles that the object has spent stopped 435system.cpu.dcache.tags.replacements 841413 # number of replacements 436system.cpu.dcache.tags.tagsinuse 511.953450 # Cycle average of tags in use 437system.cpu.dcache.tags.total_refs 42452187 # Total number of references to valid blocks. 438system.cpu.dcache.tags.sampled_refs 841925 # Sample count of references to valid blocks. 439system.cpu.dcache.tags.avg_refs 50.422766 # Average number of references to valid blocks. 440system.cpu.dcache.tags.warmup_cycle 279721250 # Cycle when the warmup percentage was hit. 441system.cpu.dcache.tags.occ_blocks::cpu.inst 511.953450 # Average occupied blocks per requestor 442system.cpu.dcache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy 443system.cpu.dcache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy 444system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 445system.cpu.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id 446system.cpu.dcache.tags.age_task_id_blocks_1024::1 357 # Occupied blocks per task id 447system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id 448system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 449system.cpu.dcache.tags.tag_accesses 175172385 # Number of tag accesses 450system.cpu.dcache.tags.data_accesses 175172385 # Number of data accesses 451system.cpu.dcache.ReadReq_hits::cpu.inst 23318882 # number of ReadReq hits 452system.cpu.dcache.ReadReq_hits::total 23318882 # number of ReadReq hits 453system.cpu.dcache.WriteReq_hits::cpu.inst 18212211 # number of WriteReq hits 454system.cpu.dcache.WriteReq_hits::total 18212211 # number of WriteReq hits 455system.cpu.dcache.LoadLockedReq_hits::cpu.inst 457846 # number of LoadLockedReq hits 456system.cpu.dcache.LoadLockedReq_hits::total 457846 # number of LoadLockedReq hits 457system.cpu.dcache.StoreCondReq_hits::cpu.inst 460333 # number of StoreCondReq hits 458system.cpu.dcache.StoreCondReq_hits::total 460333 # number of StoreCondReq hits 459system.cpu.dcache.demand_hits::cpu.inst 41531093 # number of demand (read+write) hits 460system.cpu.dcache.demand_hits::total 41531093 # number of demand (read+write) hits 461system.cpu.dcache.overall_hits::cpu.inst 41531093 # number of overall hits 462system.cpu.dcache.overall_hits::total 41531093 # number of overall hits 463system.cpu.dcache.ReadReq_misses::cpu.inst 583694 # number of ReadReq misses 464system.cpu.dcache.ReadReq_misses::total 583694 # number of ReadReq misses 465system.cpu.dcache.WriteReq_misses::cpu.inst 541327 # number of WriteReq misses 466system.cpu.dcache.WriteReq_misses::total 541327 # number of WriteReq misses 467system.cpu.dcache.LoadLockedReq_misses::cpu.inst 8314 # number of LoadLockedReq misses 468system.cpu.dcache.LoadLockedReq_misses::total 8314 # number of LoadLockedReq misses 469system.cpu.dcache.StoreCondReq_misses::cpu.inst 2 # number of StoreCondReq misses 470system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 471system.cpu.dcache.demand_misses::cpu.inst 1125021 # number of demand (read+write) misses 472system.cpu.dcache.demand_misses::total 1125021 # number of demand (read+write) misses 473system.cpu.dcache.overall_misses::cpu.inst 1125021 # number of overall misses 474system.cpu.dcache.overall_misses::total 1125021 # number of overall misses 475system.cpu.dcache.ReadReq_miss_latency::cpu.inst 8654598086 # number of ReadReq miss cycles 476system.cpu.dcache.ReadReq_miss_latency::total 8654598086 # number of ReadReq miss cycles 477system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21588798306 # number of WriteReq miss cycles 478system.cpu.dcache.WriteReq_miss_latency::total 21588798306 # number of WriteReq miss cycles 479system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 117927750 # number of LoadLockedReq miss cycles 480system.cpu.dcache.LoadLockedReq_miss_latency::total 117927750 # number of LoadLockedReq miss cycles 481system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 52502 # number of StoreCondReq miss cycles 482system.cpu.dcache.StoreCondReq_miss_latency::total 52502 # number of StoreCondReq miss cycles 483system.cpu.dcache.demand_miss_latency::cpu.inst 30243396392 # number of demand (read+write) miss cycles 484system.cpu.dcache.demand_miss_latency::total 30243396392 # number of demand (read+write) miss cycles 485system.cpu.dcache.overall_miss_latency::cpu.inst 30243396392 # number of overall miss cycles 486system.cpu.dcache.overall_miss_latency::total 30243396392 # number of overall miss cycles 487system.cpu.dcache.ReadReq_accesses::cpu.inst 23902576 # number of ReadReq accesses(hits+misses) 488system.cpu.dcache.ReadReq_accesses::total 23902576 # number of ReadReq accesses(hits+misses) 489system.cpu.dcache.WriteReq_accesses::cpu.inst 18753538 # number of WriteReq accesses(hits+misses) 490system.cpu.dcache.WriteReq_accesses::total 18753538 # number of WriteReq accesses(hits+misses) 491system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 466160 # number of LoadLockedReq accesses(hits+misses) 492system.cpu.dcache.LoadLockedReq_accesses::total 466160 # number of LoadLockedReq accesses(hits+misses) 493system.cpu.dcache.StoreCondReq_accesses::cpu.inst 460335 # number of StoreCondReq accesses(hits+misses) 494system.cpu.dcache.StoreCondReq_accesses::total 460335 # number of StoreCondReq accesses(hits+misses) 495system.cpu.dcache.demand_accesses::cpu.inst 42656114 # number of demand (read+write) accesses 496system.cpu.dcache.demand_accesses::total 42656114 # number of demand (read+write) accesses 497system.cpu.dcache.overall_accesses::cpu.inst 42656114 # number of overall (read+write) accesses 498system.cpu.dcache.overall_accesses::total 42656114 # number of overall (read+write) accesses 499system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.024420 # miss rate for ReadReq accesses 500system.cpu.dcache.ReadReq_miss_rate::total 0.024420 # miss rate for ReadReq accesses 501system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.028865 # miss rate for WriteReq accesses 502system.cpu.dcache.WriteReq_miss_rate::total 0.028865 # miss rate for WriteReq accesses 503system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.017835 # miss rate for LoadLockedReq accesses 504system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017835 # miss rate for LoadLockedReq accesses 505system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000004 # miss rate for StoreCondReq accesses 506system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 507system.cpu.dcache.demand_miss_rate::cpu.inst 0.026374 # miss rate for demand accesses 508system.cpu.dcache.demand_miss_rate::total 0.026374 # miss rate for demand accesses 509system.cpu.dcache.overall_miss_rate::cpu.inst 0.026374 # miss rate for overall accesses 510system.cpu.dcache.overall_miss_rate::total 0.026374 # miss rate for overall accesses 511system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14827.286362 # average ReadReq miss latency 512system.cpu.dcache.ReadReq_avg_miss_latency::total 14827.286362 # average ReadReq miss latency 513system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39881.251639 # average WriteReq miss latency 514system.cpu.dcache.WriteReq_avg_miss_latency::total 39881.251639 # average WriteReq miss latency 515system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14184.237431 # average LoadLockedReq miss latency 516system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14184.237431 # average LoadLockedReq miss latency 517system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 26251 # average StoreCondReq miss latency 518system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26251 # average StoreCondReq miss latency 519system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26882.517208 # average overall miss latency 520system.cpu.dcache.demand_avg_miss_latency::total 26882.517208 # average overall miss latency 521system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26882.517208 # average overall miss latency 522system.cpu.dcache.overall_avg_miss_latency::total 26882.517208 # average overall miss latency 523system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 524system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 525system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 526system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 527system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 528system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 529system.cpu.dcache.fast_writes 0 # number of fast writes performed 530system.cpu.dcache.cache_copies 0 # number of cache copies performed 531system.cpu.dcache.writebacks::writebacks 697938 # number of writebacks 532system.cpu.dcache.writebacks::total 697938 # number of writebacks 533system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 45858 # number of ReadReq MSHR hits 534system.cpu.dcache.ReadReq_mshr_hits::total 45858 # number of ReadReq MSHR hits 535system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 242707 # number of WriteReq MSHR hits 536system.cpu.dcache.WriteReq_mshr_hits::total 242707 # number of WriteReq MSHR hits 537system.cpu.dcache.demand_mshr_hits::cpu.inst 288565 # number of demand (read+write) MSHR hits 538system.cpu.dcache.demand_mshr_hits::total 288565 # number of demand (read+write) MSHR hits 539system.cpu.dcache.overall_mshr_hits::cpu.inst 288565 # number of overall MSHR hits 540system.cpu.dcache.overall_mshr_hits::total 288565 # number of overall MSHR hits 541system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 537836 # number of ReadReq MSHR misses 542system.cpu.dcache.ReadReq_mshr_misses::total 537836 # number of ReadReq MSHR misses 543system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 298620 # number of WriteReq MSHR misses 544system.cpu.dcache.WriteReq_mshr_misses::total 298620 # number of WriteReq MSHR misses 545system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 8314 # number of LoadLockedReq MSHR misses 546system.cpu.dcache.LoadLockedReq_mshr_misses::total 8314 # number of LoadLockedReq MSHR misses 547system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 2 # number of StoreCondReq MSHR misses 548system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 549system.cpu.dcache.demand_mshr_misses::cpu.inst 836456 # number of demand (read+write) MSHR misses 550system.cpu.dcache.demand_mshr_misses::total 836456 # number of demand (read+write) MSHR misses 551system.cpu.dcache.overall_mshr_misses::cpu.inst 836456 # number of overall MSHR misses 552system.cpu.dcache.overall_mshr_misses::total 836456 # number of overall MSHR misses 553system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6884995145 # number of ReadReq MSHR miss cycles 554system.cpu.dcache.ReadReq_mshr_miss_latency::total 6884995145 # number of ReadReq MSHR miss cycles 555system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 11268709155 # number of WriteReq MSHR miss cycles 556system.cpu.dcache.WriteReq_mshr_miss_latency::total 11268709155 # number of WriteReq MSHR miss cycles 557system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 101270250 # number of LoadLockedReq MSHR miss cycles 558system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 101270250 # number of LoadLockedReq MSHR miss cycles 559system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 48498 # number of StoreCondReq MSHR miss cycles 560system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48498 # number of StoreCondReq MSHR miss cycles 561system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 18153704300 # number of demand (read+write) MSHR miss cycles 562system.cpu.dcache.demand_mshr_miss_latency::total 18153704300 # number of demand (read+write) MSHR miss cycles 563system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 18153704300 # number of overall MSHR miss cycles 564system.cpu.dcache.overall_mshr_miss_latency::total 18153704300 # number of overall MSHR miss cycles 565system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5790985000 # number of ReadReq MSHR uncacheable cycles 566system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790985000 # number of ReadReq MSHR uncacheable cycles 567system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 4439182000 # number of WriteReq MSHR uncacheable cycles 568system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439182000 # number of WriteReq MSHR uncacheable cycles 569system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 10230167000 # number of overall MSHR uncacheable cycles 570system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230167000 # number of overall MSHR uncacheable cycles 571system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.022501 # mshr miss rate for ReadReq accesses 572system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022501 # mshr miss rate for ReadReq accesses 573system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015923 # mshr miss rate for WriteReq accesses 574system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015923 # mshr miss rate for WriteReq accesses 575system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.017835 # mshr miss rate for LoadLockedReq accesses 576system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017835 # mshr miss rate for LoadLockedReq accesses 577system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for StoreCondReq accesses 578system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses 579system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.019609 # mshr miss rate for demand accesses 580system.cpu.dcache.demand_mshr_miss_rate::total 0.019609 # mshr miss rate for demand accesses 581system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019609 # mshr miss rate for overall accesses 582system.cpu.dcache.overall_mshr_miss_rate::total 0.019609 # mshr miss rate for overall accesses 583system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12801.290998 # average ReadReq mshr miss latency 584system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12801.290998 # average ReadReq mshr miss latency 585system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37735.949216 # average WriteReq mshr miss latency 586system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37735.949216 # average WriteReq mshr miss latency 587system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12180.689199 # average LoadLockedReq mshr miss latency 588system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12180.689199 # average LoadLockedReq mshr miss latency 589system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 24249 # average StoreCondReq mshr miss latency 590system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24249 # average StoreCondReq mshr miss latency 591system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21703.119232 # average overall mshr miss latency 592system.cpu.dcache.demand_avg_mshr_miss_latency::total 21703.119232 # average overall mshr miss latency 593system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21703.119232 # average overall mshr miss latency 594system.cpu.dcache.overall_avg_mshr_miss_latency::total 21703.119232 # average overall mshr miss latency 595system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 596system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 597system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 598system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 599system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 600system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 601system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 602system.cpu.icache.tags.replacements 2897611 # number of replacements 603system.cpu.icache.tags.tagsinuse 511.427780 # Cycle average of tags in use 604system.cpu.icache.tags.total_refs 54131846 # Total number of references to valid blocks. 605system.cpu.icache.tags.sampled_refs 2898123 # Sample count of references to valid blocks. 606system.cpu.icache.tags.avg_refs 18.678243 # Average number of references to valid blocks. |
| 627system.cpu.icache.tags.warmup_cycle 15213015250 # Cycle when the warmup percentage was hit. | 607system.cpu.icache.tags.warmup_cycle 15213015250 # Cycle when the warmup percentage was hit. |
| 628system.cpu.icache.tags.occ_blocks::cpu.inst 511.427915 # Average occupied blocks per requestor 629system.cpu.icache.tags.occ_percent::cpu.inst 0.998883 # Average percentage of cache occupancy 630system.cpu.icache.tags.occ_percent::total 0.998883 # Average percentage of cache occupancy | 608system.cpu.icache.tags.occ_blocks::cpu.inst 511.427780 # Average occupied blocks per requestor 609system.cpu.icache.tags.occ_percent::cpu.inst 0.998882 # Average percentage of cache occupancy 610system.cpu.icache.tags.occ_percent::total 0.998882 # Average percentage of cache occupancy |
| 631system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 611system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 632system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 633system.cpu.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 634system.cpu.icache.tags.age_task_id_blocks_1024::2 200 # Occupied blocks per task id | 612system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id 613system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id 614system.cpu.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id |
| 635system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 615system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 636system.cpu.icache.tags.tag_accesses 59927594 # Number of tag accesses 637system.cpu.icache.tags.data_accesses 59927594 # Number of data accesses 638system.cpu.icache.ReadReq_hits::cpu.inst 54131849 # number of ReadReq hits 639system.cpu.icache.ReadReq_hits::total 54131849 # number of ReadReq hits 640system.cpu.icache.demand_hits::cpu.inst 54131849 # number of demand (read+write) hits 641system.cpu.icache.demand_hits::total 54131849 # number of demand (read+write) hits 642system.cpu.icache.overall_hits::cpu.inst 54131849 # number of overall hits 643system.cpu.icache.overall_hits::total 54131849 # number of overall hits 644system.cpu.icache.ReadReq_misses::cpu.inst 2897873 # number of ReadReq misses 645system.cpu.icache.ReadReq_misses::total 2897873 # number of ReadReq misses 646system.cpu.icache.demand_misses::cpu.inst 2897873 # number of demand (read+write) misses 647system.cpu.icache.demand_misses::total 2897873 # number of demand (read+write) misses 648system.cpu.icache.overall_misses::cpu.inst 2897873 # number of overall misses 649system.cpu.icache.overall_misses::total 2897873 # number of overall misses 650system.cpu.icache.ReadReq_miss_latency::cpu.inst 39140139756 # number of ReadReq miss cycles 651system.cpu.icache.ReadReq_miss_latency::total 39140139756 # number of ReadReq miss cycles 652system.cpu.icache.demand_miss_latency::cpu.inst 39140139756 # number of demand (read+write) miss cycles 653system.cpu.icache.demand_miss_latency::total 39140139756 # number of demand (read+write) miss cycles 654system.cpu.icache.overall_miss_latency::cpu.inst 39140139756 # number of overall miss cycles 655system.cpu.icache.overall_miss_latency::total 39140139756 # number of overall miss cycles 656system.cpu.icache.ReadReq_accesses::cpu.inst 57029722 # number of ReadReq accesses(hits+misses) 657system.cpu.icache.ReadReq_accesses::total 57029722 # number of ReadReq accesses(hits+misses) 658system.cpu.icache.demand_accesses::cpu.inst 57029722 # number of demand (read+write) accesses 659system.cpu.icache.demand_accesses::total 57029722 # number of demand (read+write) accesses 660system.cpu.icache.overall_accesses::cpu.inst 57029722 # number of overall (read+write) accesses 661system.cpu.icache.overall_accesses::total 57029722 # number of overall (read+write) accesses 662system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050813 # miss rate for ReadReq accesses 663system.cpu.icache.ReadReq_miss_rate::total 0.050813 # miss rate for ReadReq accesses 664system.cpu.icache.demand_miss_rate::cpu.inst 0.050813 # miss rate for demand accesses 665system.cpu.icache.demand_miss_rate::total 0.050813 # miss rate for demand accesses 666system.cpu.icache.overall_miss_rate::cpu.inst 0.050813 # miss rate for overall accesses 667system.cpu.icache.overall_miss_rate::total 0.050813 # miss rate for overall accesses 668system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.506240 # average ReadReq miss latency 669system.cpu.icache.ReadReq_avg_miss_latency::total 13506.506240 # average ReadReq miss latency 670system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.506240 # average overall miss latency 671system.cpu.icache.demand_avg_miss_latency::total 13506.506240 # average overall miss latency 672system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.506240 # average overall miss latency 673system.cpu.icache.overall_avg_miss_latency::total 13506.506240 # average overall miss latency | 616system.cpu.icache.tags.tag_accesses 59928115 # Number of tag accesses 617system.cpu.icache.tags.data_accesses 59928115 # Number of data accesses 618system.cpu.icache.ReadReq_hits::cpu.inst 54131846 # number of ReadReq hits 619system.cpu.icache.ReadReq_hits::total 54131846 # number of ReadReq hits 620system.cpu.icache.demand_hits::cpu.inst 54131846 # number of demand (read+write) hits 621system.cpu.icache.demand_hits::total 54131846 # number of demand (read+write) hits 622system.cpu.icache.overall_hits::cpu.inst 54131846 # number of overall hits 623system.cpu.icache.overall_hits::total 54131846 # number of overall hits 624system.cpu.icache.ReadReq_misses::cpu.inst 2898135 # number of ReadReq misses 625system.cpu.icache.ReadReq_misses::total 2898135 # number of ReadReq misses 626system.cpu.icache.demand_misses::cpu.inst 2898135 # number of demand (read+write) misses 627system.cpu.icache.demand_misses::total 2898135 # number of demand (read+write) misses 628system.cpu.icache.overall_misses::cpu.inst 2898135 # number of overall misses 629system.cpu.icache.overall_misses::total 2898135 # number of overall misses 630system.cpu.icache.ReadReq_miss_latency::cpu.inst 39145708027 # number of ReadReq miss cycles 631system.cpu.icache.ReadReq_miss_latency::total 39145708027 # number of ReadReq miss cycles 632system.cpu.icache.demand_miss_latency::cpu.inst 39145708027 # number of demand (read+write) miss cycles 633system.cpu.icache.demand_miss_latency::total 39145708027 # number of demand (read+write) miss cycles 634system.cpu.icache.overall_miss_latency::cpu.inst 39145708027 # number of overall miss cycles 635system.cpu.icache.overall_miss_latency::total 39145708027 # number of overall miss cycles 636system.cpu.icache.ReadReq_accesses::cpu.inst 57029981 # number of ReadReq accesses(hits+misses) 637system.cpu.icache.ReadReq_accesses::total 57029981 # number of ReadReq accesses(hits+misses) 638system.cpu.icache.demand_accesses::cpu.inst 57029981 # number of demand (read+write) accesses 639system.cpu.icache.demand_accesses::total 57029981 # number of demand (read+write) accesses 640system.cpu.icache.overall_accesses::cpu.inst 57029981 # number of overall (read+write) accesses 641system.cpu.icache.overall_accesses::total 57029981 # number of overall (read+write) accesses 642system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050818 # miss rate for ReadReq accesses 643system.cpu.icache.ReadReq_miss_rate::total 0.050818 # miss rate for ReadReq accesses 644system.cpu.icache.demand_miss_rate::cpu.inst 0.050818 # miss rate for demand accesses 645system.cpu.icache.demand_miss_rate::total 0.050818 # miss rate for demand accesses 646system.cpu.icache.overall_miss_rate::cpu.inst 0.050818 # miss rate for overall accesses 647system.cpu.icache.overall_miss_rate::total 0.050818 # miss rate for overall accesses 648system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13507.206540 # average ReadReq miss latency 649system.cpu.icache.ReadReq_avg_miss_latency::total 13507.206540 # average ReadReq miss latency 650system.cpu.icache.demand_avg_miss_latency::cpu.inst 13507.206540 # average overall miss latency 651system.cpu.icache.demand_avg_miss_latency::total 13507.206540 # average overall miss latency 652system.cpu.icache.overall_avg_miss_latency::cpu.inst 13507.206540 # average overall miss latency 653system.cpu.icache.overall_avg_miss_latency::total 13507.206540 # average overall miss latency |
| 674system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 675system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 676system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 677system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 678system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 679system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 680system.cpu.icache.fast_writes 0 # number of fast writes performed 681system.cpu.icache.cache_copies 0 # number of cache copies performed | 654system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 655system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 656system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 657system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 658system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 659system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 660system.cpu.icache.fast_writes 0 # number of fast writes performed 661system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 682system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897873 # number of ReadReq MSHR misses 683system.cpu.icache.ReadReq_mshr_misses::total 2897873 # number of ReadReq MSHR misses 684system.cpu.icache.demand_mshr_misses::cpu.inst 2897873 # number of demand (read+write) MSHR misses 685system.cpu.icache.demand_mshr_misses::total 2897873 # number of demand (read+write) MSHR misses 686system.cpu.icache.overall_mshr_misses::cpu.inst 2897873 # number of overall MSHR misses 687system.cpu.icache.overall_mshr_misses::total 2897873 # number of overall MSHR misses 688system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33334905244 # number of ReadReq MSHR miss cycles 689system.cpu.icache.ReadReq_mshr_miss_latency::total 33334905244 # number of ReadReq MSHR miss cycles 690system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33334905244 # number of demand (read+write) MSHR miss cycles 691system.cpu.icache.demand_mshr_miss_latency::total 33334905244 # number of demand (read+write) MSHR miss cycles 692system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33334905244 # number of overall MSHR miss cycles 693system.cpu.icache.overall_mshr_miss_latency::total 33334905244 # number of overall MSHR miss cycles | 662system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2898135 # number of ReadReq MSHR misses 663system.cpu.icache.ReadReq_mshr_misses::total 2898135 # number of ReadReq MSHR misses 664system.cpu.icache.demand_mshr_misses::cpu.inst 2898135 # number of demand (read+write) MSHR misses 665system.cpu.icache.demand_mshr_misses::total 2898135 # number of demand (read+write) MSHR misses 666system.cpu.icache.overall_mshr_misses::cpu.inst 2898135 # number of overall MSHR misses 667system.cpu.icache.overall_mshr_misses::total 2898135 # number of overall MSHR misses 668system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33339952973 # number of ReadReq MSHR miss cycles 669system.cpu.icache.ReadReq_mshr_miss_latency::total 33339952973 # number of ReadReq MSHR miss cycles 670system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33339952973 # number of demand (read+write) MSHR miss cycles 671system.cpu.icache.demand_mshr_miss_latency::total 33339952973 # number of demand (read+write) MSHR miss cycles 672system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33339952973 # number of overall MSHR miss cycles 673system.cpu.icache.overall_mshr_miss_latency::total 33339952973 # number of overall MSHR miss cycles |
| 694system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 222062750 # number of ReadReq MSHR uncacheable cycles 695system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 222062750 # number of ReadReq MSHR uncacheable cycles 696system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 222062750 # number of overall MSHR uncacheable cycles 697system.cpu.icache.overall_mshr_uncacheable_latency::total 222062750 # number of overall MSHR uncacheable cycles | 674system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 222062750 # number of ReadReq MSHR uncacheable cycles 675system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 222062750 # number of ReadReq MSHR uncacheable cycles 676system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 222062750 # number of overall MSHR uncacheable cycles 677system.cpu.icache.overall_mshr_uncacheable_latency::total 222062750 # number of overall MSHR uncacheable cycles |
| 698system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050813 # mshr miss rate for ReadReq accesses 699system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050813 # mshr miss rate for ReadReq accesses 700system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050813 # mshr miss rate for demand accesses 701system.cpu.icache.demand_mshr_miss_rate::total 0.050813 # mshr miss rate for demand accesses 702system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050813 # mshr miss rate for overall accesses 703system.cpu.icache.overall_mshr_miss_rate::total 0.050813 # mshr miss rate for overall accesses 704system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11503.231937 # average ReadReq mshr miss latency 705system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11503.231937 # average ReadReq mshr miss latency 706system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11503.231937 # average overall mshr miss latency 707system.cpu.icache.demand_avg_mshr_miss_latency::total 11503.231937 # average overall mshr miss latency 708system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11503.231937 # average overall mshr miss latency 709system.cpu.icache.overall_avg_mshr_miss_latency::total 11503.231937 # average overall mshr miss latency | 678system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050818 # mshr miss rate for ReadReq accesses 679system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050818 # mshr miss rate for ReadReq accesses 680system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050818 # mshr miss rate for demand accesses 681system.cpu.icache.demand_mshr_miss_rate::total 0.050818 # mshr miss rate for demand accesses 682system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050818 # mshr miss rate for overall accesses 683system.cpu.icache.overall_mshr_miss_rate::total 0.050818 # mshr miss rate for overall accesses 684system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11503.933727 # average ReadReq mshr miss latency 685system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11503.933727 # average ReadReq mshr miss latency 686system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11503.933727 # average overall mshr miss latency 687system.cpu.icache.demand_avg_mshr_miss_latency::total 11503.933727 # average overall mshr miss latency 688system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11503.933727 # average overall mshr miss latency 689system.cpu.icache.overall_avg_mshr_miss_latency::total 11503.933727 # average overall mshr miss latency |
| 710system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 711system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 712system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 713system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 714system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 690system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 691system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 692system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 693system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 694system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 715system.cpu.toL2Bus.trans_dist::ReadReq 3575187 # Transaction distribution 716system.cpu.toL2Bus.trans_dist::ReadResp 3575091 # Transaction distribution 717system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution 718system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution 719system.cpu.toL2Bus.trans_dist::Writeback 697424 # Transaction distribution 720system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36234 # Transaction distribution 721system.cpu.toL2Bus.trans_dist::UpgradeReq 2818 # Transaction distribution 722system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 723system.cpu.toL2Bus.trans_dist::UpgradeResp 2820 # Transaction distribution 724system.cpu.toL2Bus.trans_dist::ReadExReq 295755 # Transaction distribution 725system.cpu.toL2Bus.trans_dist::ReadExResp 295755 # Transaction distribution 726system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5801712 # Packet count per connected master and slave (bytes) 727system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2503299 # Packet count per connected master and slave (bytes) 728system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15293 # Packet count per connected master and slave (bytes) 729system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 155961 # Packet count per connected master and slave (bytes) 730system.cpu.toL2Bus.pkt_count::total 8476265 # Packet count per connected master and slave (bytes) 731system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185653696 # Cumulative packet size per connected master and slave (bytes) 732system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98670557 # Cumulative packet size per connected master and slave (bytes) 733system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 19168 # Cumulative packet size per connected master and slave (bytes) 734system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 276272 # Cumulative packet size per connected master and slave (bytes) 735system.cpu.toL2Bus.pkt_size::total 284619693 # Cumulative packet size per connected master and slave (bytes) 736system.cpu.toL2Bus.snoops 60174 # Total snoops (count) 737system.cpu.toL2Bus.snoop_fanout::samples 4573282 # Request fanout histogram 738system.cpu.toL2Bus.snoop_fanout::mean 5.007974 # Request fanout histogram 739system.cpu.toL2Bus.snoop_fanout::stdev 0.088941 # Request fanout histogram 740system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 741system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 742system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 743system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 744system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 745system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 746system.cpu.toL2Bus.snoop_fanout::5 4536814 99.20% 99.20% # Request fanout histogram 747system.cpu.toL2Bus.snoop_fanout::6 36468 0.80% 100.00% # Request fanout histogram 748system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 749system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 750system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 751system.cpu.toL2Bus.snoop_fanout::total 4573282 # Request fanout histogram 752system.cpu.toL2Bus.reqLayer0.occupancy 3010555155 # Layer occupancy (ticks) 753system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 754system.cpu.toL2Bus.snoopLayer0.occupancy 208500 # Layer occupancy (ticks) 755system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 756system.cpu.toL2Bus.respLayer0.occupancy 4356749506 # Layer occupancy (ticks) 757system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 758system.cpu.toL2Bus.respLayer1.occupancy 1339516197 # Layer occupancy (ticks) 759system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 760system.cpu.toL2Bus.respLayer2.occupancy 10501000 # Layer occupancy (ticks) 761system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 762system.cpu.toL2Bus.respLayer3.occupancy 86895250 # Layer occupancy (ticks) 763system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 764system.cpu.l2cache.tags.replacements 97514 # number of replacements 765system.cpu.l2cache.tags.tagsinuse 65073.344541 # Cycle average of tags in use 766system.cpu.l2cache.tags.total_refs 4041263 # Total number of references to valid blocks. 767system.cpu.l2cache.tags.sampled_refs 162774 # Sample count of references to valid blocks. 768system.cpu.l2cache.tags.avg_refs 24.827448 # Average number of references to valid blocks. | 695system.cpu.l2cache.tags.replacements 97521 # number of replacements 696system.cpu.l2cache.tags.tagsinuse 65074.207270 # Cycle average of tags in use 697system.cpu.l2cache.tags.total_refs 4042767 # Total number of references to valid blocks. 698system.cpu.l2cache.tags.sampled_refs 162784 # Sample count of references to valid blocks. 699system.cpu.l2cache.tags.avg_refs 24.835162 # Average number of references to valid blocks. |
| 769system.cpu.l2cache.tags.warmup_cycle 93462601500 # Cycle when the warmup percentage was hit. | 700system.cpu.l2cache.tags.warmup_cycle 93462601500 # Cycle when the warmup percentage was hit. |
| 770system.cpu.l2cache.tags.occ_blocks::writebacks 47542.577135 # Average occupied blocks per requestor 771system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 54.389093 # Average occupied blocks per requestor 772system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.009502 # Average occupied blocks per requestor 773system.cpu.l2cache.tags.occ_blocks::cpu.inst 17476.368811 # Average occupied blocks per requestor 774system.cpu.l2cache.tags.occ_percent::writebacks 0.725442 # Average percentage of cache occupancy 775system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000830 # Average percentage of cache occupancy | 701system.cpu.l2cache.tags.occ_blocks::writebacks 47538.276045 # Average occupied blocks per requestor 702system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 53.278527 # Average occupied blocks per requestor 703system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000399 # Average occupied blocks per requestor 704system.cpu.l2cache.tags.occ_blocks::cpu.inst 17482.652299 # Average occupied blocks per requestor 705system.cpu.l2cache.tags.occ_percent::writebacks 0.725377 # Average percentage of cache occupancy 706system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000813 # Average percentage of cache occupancy |
| 776system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy | 707system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy |
| 777system.cpu.l2cache.tags.occ_percent::cpu.inst 0.266668 # Average percentage of cache occupancy 778system.cpu.l2cache.tags.occ_percent::total 0.992940 # Average percentage of cache occupancy 779system.cpu.l2cache.tags.occ_task_id_blocks::1023 44 # Occupied blocks per task id 780system.cpu.l2cache.tags.occ_task_id_blocks::1024 65216 # Occupied blocks per task id 781system.cpu.l2cache.tags.age_task_id_blocks_1023::4 44 # Occupied blocks per task id 782system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id | 708system.cpu.l2cache.tags.occ_percent::cpu.inst 0.266764 # Average percentage of cache occupancy 709system.cpu.l2cache.tags.occ_percent::total 0.992954 # Average percentage of cache occupancy 710system.cpu.l2cache.tags.occ_task_id_blocks::1023 40 # Occupied blocks per task id 711system.cpu.l2cache.tags.occ_task_id_blocks::1024 65223 # Occupied blocks per task id 712system.cpu.l2cache.tags.age_task_id_blocks_1023::4 40 # Occupied blocks per task id 713system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id |
| 783system.cpu.l2cache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id | 714system.cpu.l2cache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id |
| 784system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2322 # Occupied blocks per task id 785system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6967 # Occupied blocks per task id 786system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55801 # Occupied blocks per task id 787system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id 788system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995117 # Percentage of cache occupancy per task id 789system.cpu.l2cache.tags.tag_accesses 36568997 # Number of tag accesses 790system.cpu.l2cache.tags.data_accesses 36568997 # Number of data accesses 791system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68967 # number of ReadReq hits 792system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4789 # number of ReadReq hits 793system.cpu.l2cache.ReadReq_hits::cpu.inst 3405854 # number of ReadReq hits 794system.cpu.l2cache.ReadReq_hits::total 3479610 # number of ReadReq hits 795system.cpu.l2cache.Writeback_hits::writebacks 697424 # number of Writeback hits 796system.cpu.l2cache.Writeback_hits::total 697424 # number of Writeback hits | 715system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2327 # Occupied blocks per task id 716system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6958 # Occupied blocks per task id 717system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55810 # Occupied blocks per task id 718system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id 719system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995224 # Percentage of cache occupancy per task id 720system.cpu.l2cache.tags.tag_accesses 36581031 # Number of tag accesses 721system.cpu.l2cache.tags.data_accesses 36581031 # Number of data accesses 722system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69052 # number of ReadReq hits 723system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4779 # number of ReadReq hits 724system.cpu.l2cache.ReadReq_hits::cpu.inst 3406716 # number of ReadReq hits 725system.cpu.l2cache.ReadReq_hits::total 3480547 # number of ReadReq hits 726system.cpu.l2cache.Writeback_hits::writebacks 697938 # number of Writeback hits 727system.cpu.l2cache.Writeback_hits::total 697938 # number of Writeback hits |
| 797system.cpu.l2cache.UpgradeReq_hits::cpu.inst 45 # number of UpgradeReq hits 798system.cpu.l2cache.UpgradeReq_hits::total 45 # number of UpgradeReq hits | 728system.cpu.l2cache.UpgradeReq_hits::cpu.inst 45 # number of UpgradeReq hits 729system.cpu.l2cache.UpgradeReq_hits::total 45 # number of UpgradeReq hits |
| 799system.cpu.l2cache.ReadExReq_hits::cpu.inst 164068 # number of ReadExReq hits 800system.cpu.l2cache.ReadExReq_hits::total 164068 # number of ReadExReq hits 801system.cpu.l2cache.demand_hits::cpu.dtb.walker 68967 # number of demand (read+write) hits 802system.cpu.l2cache.demand_hits::cpu.itb.walker 4789 # number of demand (read+write) hits 803system.cpu.l2cache.demand_hits::cpu.inst 3569922 # number of demand (read+write) hits 804system.cpu.l2cache.demand_hits::total 3643678 # number of demand (read+write) hits 805system.cpu.l2cache.overall_hits::cpu.dtb.walker 68967 # number of overall hits 806system.cpu.l2cache.overall_hits::cpu.itb.walker 4789 # number of overall hits 807system.cpu.l2cache.overall_hits::cpu.inst 3569922 # number of overall hits 808system.cpu.l2cache.overall_hits::total 3643678 # number of overall hits 809system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 101 # number of ReadReq misses 810system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses 811system.cpu.l2cache.ReadReq_misses::cpu.inst 37534 # number of ReadReq misses 812system.cpu.l2cache.ReadReq_misses::total 37638 # number of ReadReq misses 813system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2773 # number of UpgradeReq misses 814system.cpu.l2cache.UpgradeReq_misses::total 2773 # number of UpgradeReq misses | 730system.cpu.l2cache.ReadExReq_hits::cpu.inst 164104 # number of ReadExReq hits 731system.cpu.l2cache.ReadExReq_hits::total 164104 # number of ReadExReq hits 732system.cpu.l2cache.demand_hits::cpu.dtb.walker 69052 # number of demand (read+write) hits 733system.cpu.l2cache.demand_hits::cpu.itb.walker 4779 # number of demand (read+write) hits 734system.cpu.l2cache.demand_hits::cpu.inst 3570820 # number of demand (read+write) hits 735system.cpu.l2cache.demand_hits::total 3644651 # number of demand (read+write) hits 736system.cpu.l2cache.overall_hits::cpu.dtb.walker 69052 # number of overall hits 737system.cpu.l2cache.overall_hits::cpu.itb.walker 4779 # number of overall hits 738system.cpu.l2cache.overall_hits::cpu.inst 3570820 # number of overall hits 739system.cpu.l2cache.overall_hits::total 3644651 # number of overall hits 740system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 97 # number of ReadReq misses 741system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 742system.cpu.l2cache.ReadReq_misses::cpu.inst 37533 # number of ReadReq misses 743system.cpu.l2cache.ReadReq_misses::total 37632 # number of ReadReq misses 744system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2776 # number of UpgradeReq misses 745system.cpu.l2cache.UpgradeReq_misses::total 2776 # number of UpgradeReq misses |
| 815system.cpu.l2cache.SCUpgradeReq_misses::cpu.inst 2 # number of SCUpgradeReq misses 816system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses | 746system.cpu.l2cache.SCUpgradeReq_misses::cpu.inst 2 # number of SCUpgradeReq misses 747system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses |
| 817system.cpu.l2cache.ReadExReq_misses::cpu.inst 131687 # number of ReadExReq misses 818system.cpu.l2cache.ReadExReq_misses::total 131687 # number of ReadExReq misses 819system.cpu.l2cache.demand_misses::cpu.dtb.walker 101 # number of demand (read+write) misses 820system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses 821system.cpu.l2cache.demand_misses::cpu.inst 169221 # number of demand (read+write) misses 822system.cpu.l2cache.demand_misses::total 169325 # number of demand (read+write) misses 823system.cpu.l2cache.overall_misses::cpu.dtb.walker 101 # number of overall misses 824system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses 825system.cpu.l2cache.overall_misses::cpu.inst 169221 # number of overall misses 826system.cpu.l2cache.overall_misses::total 169325 # number of overall misses 827system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 7803500 # number of ReadReq miss cycles 828system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 223500 # number of ReadReq miss cycles 829system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2773793750 # number of ReadReq miss cycles 830system.cpu.l2cache.ReadReq_miss_latency::total 2781820750 # number of ReadReq miss cycles 831system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 1024956 # number of UpgradeReq miss cycles 832system.cpu.l2cache.UpgradeReq_miss_latency::total 1024956 # number of UpgradeReq miss cycles 833system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst 46998 # number of SCUpgradeReq miss cycles 834system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles 835system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9263576682 # number of ReadExReq miss cycles 836system.cpu.l2cache.ReadExReq_miss_latency::total 9263576682 # number of ReadExReq miss cycles 837system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 7803500 # number of demand (read+write) miss cycles 838system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 223500 # number of demand (read+write) miss cycles 839system.cpu.l2cache.demand_miss_latency::cpu.inst 12037370432 # number of demand (read+write) miss cycles 840system.cpu.l2cache.demand_miss_latency::total 12045397432 # number of demand (read+write) miss cycles 841system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 7803500 # number of overall miss cycles 842system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 223500 # number of overall miss cycles 843system.cpu.l2cache.overall_miss_latency::cpu.inst 12037370432 # number of overall miss cycles 844system.cpu.l2cache.overall_miss_latency::total 12045397432 # number of overall miss cycles 845system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69068 # number of ReadReq accesses(hits+misses) 846system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4792 # number of ReadReq accesses(hits+misses) 847system.cpu.l2cache.ReadReq_accesses::cpu.inst 3443388 # number of ReadReq accesses(hits+misses) 848system.cpu.l2cache.ReadReq_accesses::total 3517248 # number of ReadReq accesses(hits+misses) 849system.cpu.l2cache.Writeback_accesses::writebacks 697424 # number of Writeback accesses(hits+misses) 850system.cpu.l2cache.Writeback_accesses::total 697424 # number of Writeback accesses(hits+misses) 851system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2818 # number of UpgradeReq accesses(hits+misses) 852system.cpu.l2cache.UpgradeReq_accesses::total 2818 # number of UpgradeReq accesses(hits+misses) | 748system.cpu.l2cache.ReadExReq_misses::cpu.inst 131700 # number of ReadExReq misses 749system.cpu.l2cache.ReadExReq_misses::total 131700 # number of ReadExReq misses 750system.cpu.l2cache.demand_misses::cpu.dtb.walker 97 # number of demand (read+write) misses 751system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 752system.cpu.l2cache.demand_misses::cpu.inst 169233 # number of demand (read+write) misses 753system.cpu.l2cache.demand_misses::total 169332 # number of demand (read+write) misses 754system.cpu.l2cache.overall_misses::cpu.dtb.walker 97 # number of overall misses 755system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 756system.cpu.l2cache.overall_misses::cpu.inst 169233 # number of overall misses 757system.cpu.l2cache.overall_misses::total 169332 # number of overall misses 758system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 7518750 # number of ReadReq miss cycles 759system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149000 # number of ReadReq miss cycles 760system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2779279750 # number of ReadReq miss cycles 761system.cpu.l2cache.ReadReq_miss_latency::total 2786947500 # number of ReadReq miss cycles 762system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 1021956 # number of UpgradeReq miss cycles 763system.cpu.l2cache.UpgradeReq_miss_latency::total 1021956 # number of UpgradeReq miss cycles 764system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst 46498 # number of SCUpgradeReq miss cycles 765system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46498 # number of SCUpgradeReq miss cycles 766system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9264906431 # number of ReadExReq miss cycles 767system.cpu.l2cache.ReadExReq_miss_latency::total 9264906431 # number of ReadExReq miss cycles 768system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 7518750 # number of demand (read+write) miss cycles 769system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149000 # number of demand (read+write) miss cycles 770system.cpu.l2cache.demand_miss_latency::cpu.inst 12044186181 # number of demand (read+write) miss cycles 771system.cpu.l2cache.demand_miss_latency::total 12051853931 # number of demand (read+write) miss cycles 772system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 7518750 # number of overall miss cycles 773system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149000 # number of overall miss cycles 774system.cpu.l2cache.overall_miss_latency::cpu.inst 12044186181 # number of overall miss cycles 775system.cpu.l2cache.overall_miss_latency::total 12051853931 # number of overall miss cycles 776system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69149 # number of ReadReq accesses(hits+misses) 777system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4781 # number of ReadReq accesses(hits+misses) 778system.cpu.l2cache.ReadReq_accesses::cpu.inst 3444249 # number of ReadReq accesses(hits+misses) 779system.cpu.l2cache.ReadReq_accesses::total 3518179 # number of ReadReq accesses(hits+misses) 780system.cpu.l2cache.Writeback_accesses::writebacks 697938 # number of Writeback accesses(hits+misses) 781system.cpu.l2cache.Writeback_accesses::total 697938 # number of Writeback accesses(hits+misses) 782system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2821 # number of UpgradeReq accesses(hits+misses) 783system.cpu.l2cache.UpgradeReq_accesses::total 2821 # number of UpgradeReq accesses(hits+misses) |
| 853system.cpu.l2cache.SCUpgradeReq_accesses::cpu.inst 2 # number of SCUpgradeReq accesses(hits+misses) 854system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) | 784system.cpu.l2cache.SCUpgradeReq_accesses::cpu.inst 2 # number of SCUpgradeReq accesses(hits+misses) 785system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) |
| 855system.cpu.l2cache.ReadExReq_accesses::cpu.inst 295755 # number of ReadExReq accesses(hits+misses) 856system.cpu.l2cache.ReadExReq_accesses::total 295755 # number of ReadExReq accesses(hits+misses) 857system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69068 # number of demand (read+write) accesses 858system.cpu.l2cache.demand_accesses::cpu.itb.walker 4792 # number of demand (read+write) accesses 859system.cpu.l2cache.demand_accesses::cpu.inst 3739143 # number of demand (read+write) accesses 860system.cpu.l2cache.demand_accesses::total 3813003 # number of demand (read+write) accesses 861system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69068 # number of overall (read+write) accesses 862system.cpu.l2cache.overall_accesses::cpu.itb.walker 4792 # number of overall (read+write) accesses 863system.cpu.l2cache.overall_accesses::cpu.inst 3739143 # number of overall (read+write) accesses 864system.cpu.l2cache.overall_accesses::total 3813003 # number of overall (read+write) accesses 865system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001462 # miss rate for ReadReq accesses 866system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000626 # miss rate for ReadReq accesses 867system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010900 # miss rate for ReadReq accesses 868system.cpu.l2cache.ReadReq_miss_rate::total 0.010701 # miss rate for ReadReq accesses 869system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.984031 # miss rate for UpgradeReq accesses 870system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984031 # miss rate for UpgradeReq accesses | 786system.cpu.l2cache.ReadExReq_accesses::cpu.inst 295804 # number of ReadExReq accesses(hits+misses) 787system.cpu.l2cache.ReadExReq_accesses::total 295804 # number of ReadExReq accesses(hits+misses) 788system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69149 # number of demand (read+write) accesses 789system.cpu.l2cache.demand_accesses::cpu.itb.walker 4781 # number of demand (read+write) accesses 790system.cpu.l2cache.demand_accesses::cpu.inst 3740053 # number of demand (read+write) accesses 791system.cpu.l2cache.demand_accesses::total 3813983 # number of demand (read+write) accesses 792system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69149 # number of overall (read+write) accesses 793system.cpu.l2cache.overall_accesses::cpu.itb.walker 4781 # number of overall (read+write) accesses 794system.cpu.l2cache.overall_accesses::cpu.inst 3740053 # number of overall (read+write) accesses 795system.cpu.l2cache.overall_accesses::total 3813983 # number of overall (read+write) accesses 796system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001403 # miss rate for ReadReq accesses 797system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000418 # miss rate for ReadReq accesses 798system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010897 # miss rate for ReadReq accesses 799system.cpu.l2cache.ReadReq_miss_rate::total 0.010696 # miss rate for ReadReq accesses 800system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.984048 # miss rate for UpgradeReq accesses 801system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984048 # miss rate for UpgradeReq accesses |
| 871system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst 1 # miss rate for SCUpgradeReq accesses 872system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 802system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst 1 # miss rate for SCUpgradeReq accesses 803system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 873system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.445257 # miss rate for ReadExReq accesses 874system.cpu.l2cache.ReadExReq_miss_rate::total 0.445257 # miss rate for ReadExReq accesses 875system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001462 # miss rate for demand accesses 876system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000626 # miss rate for demand accesses 877system.cpu.l2cache.demand_miss_rate::cpu.inst 0.045257 # miss rate for demand accesses 878system.cpu.l2cache.demand_miss_rate::total 0.044407 # miss rate for demand accesses 879system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001462 # miss rate for overall accesses 880system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000626 # miss rate for overall accesses 881system.cpu.l2cache.overall_miss_rate::cpu.inst 0.045257 # miss rate for overall accesses 882system.cpu.l2cache.overall_miss_rate::total 0.044407 # miss rate for overall accesses 883system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77262.376238 # average ReadReq miss latency | 804system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.445227 # miss rate for ReadExReq accesses 805system.cpu.l2cache.ReadExReq_miss_rate::total 0.445227 # miss rate for ReadExReq accesses 806system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001403 # miss rate for demand accesses 807system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000418 # miss rate for demand accesses 808system.cpu.l2cache.demand_miss_rate::cpu.inst 0.045249 # miss rate for demand accesses 809system.cpu.l2cache.demand_miss_rate::total 0.044398 # miss rate for demand accesses 810system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001403 # miss rate for overall accesses 811system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000418 # miss rate for overall accesses 812system.cpu.l2cache.overall_miss_rate::cpu.inst 0.045249 # miss rate for overall accesses 813system.cpu.l2cache.overall_miss_rate::total 0.044398 # miss rate for overall accesses 814system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77512.886598 # average ReadReq miss latency |
| 884system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74500 # average ReadReq miss latency | 815system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74500 # average ReadReq miss latency |
| 885system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73900.829914 # average ReadReq miss latency 886system.cpu.l2cache.ReadReq_avg_miss_latency::total 73909.898241 # average ReadReq miss latency 887system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 369.619906 # average UpgradeReq miss latency 888system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 369.619906 # average UpgradeReq miss latency 889system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst 23499 # average SCUpgradeReq miss latency 890system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23499 # average SCUpgradeReq miss latency 891system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70345.415128 # average ReadExReq miss latency 892system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70345.415128 # average ReadExReq miss latency 893system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77262.376238 # average overall miss latency | 816system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74048.963579 # average ReadReq miss latency 817system.cpu.l2cache.ReadReq_avg_miss_latency::total 74057.916135 # average ReadReq miss latency 818system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 368.139769 # average UpgradeReq miss latency 819system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 368.139769 # average UpgradeReq miss latency 820system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst 23249 # average SCUpgradeReq miss latency 821system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23249 # average SCUpgradeReq miss latency 822system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70348.568193 # average ReadExReq miss latency 823system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70348.568193 # average ReadExReq miss latency 824system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77512.886598 # average overall miss latency |
| 894system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74500 # average overall miss latency | 825system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74500 # average overall miss latency |
| 895system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71134.022562 # average overall miss latency 896system.cpu.l2cache.demand_avg_miss_latency::total 71137.737676 # average overall miss latency 897system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77262.376238 # average overall miss latency | 826system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71169.252929 # average overall miss latency 827system.cpu.l2cache.demand_avg_miss_latency::total 71172.926151 # average overall miss latency 828system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77512.886598 # average overall miss latency |
| 898system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74500 # average overall miss latency | 829system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74500 # average overall miss latency |
| 899system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71134.022562 # average overall miss latency 900system.cpu.l2cache.overall_avg_miss_latency::total 71137.737676 # average overall miss latency | 830system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71169.252929 # average overall miss latency 831system.cpu.l2cache.overall_avg_miss_latency::total 71172.926151 # average overall miss latency |
| 901system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 902system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 903system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 904system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 905system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 906system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 907system.cpu.l2cache.fast_writes 0 # number of fast writes performed 908system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 832system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 833system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 834system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 835system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 836system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 837system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 838system.cpu.l2cache.fast_writes 0 # number of fast writes performed 839system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 909system.cpu.l2cache.writebacks::writebacks 88778 # number of writebacks 910system.cpu.l2cache.writebacks::total 88778 # number of writebacks | 840system.cpu.l2cache.writebacks::writebacks 88794 # number of writebacks 841system.cpu.l2cache.writebacks::total 88794 # number of writebacks |
| 911system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 168 # number of ReadReq MSHR hits 912system.cpu.l2cache.ReadReq_mshr_hits::total 168 # number of ReadReq MSHR hits 913system.cpu.l2cache.demand_mshr_hits::cpu.inst 168 # number of demand (read+write) MSHR hits 914system.cpu.l2cache.demand_mshr_hits::total 168 # number of demand (read+write) MSHR hits 915system.cpu.l2cache.overall_mshr_hits::cpu.inst 168 # number of overall MSHR hits 916system.cpu.l2cache.overall_mshr_hits::total 168 # number of overall MSHR hits | 842system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 168 # number of ReadReq MSHR hits 843system.cpu.l2cache.ReadReq_mshr_hits::total 168 # number of ReadReq MSHR hits 844system.cpu.l2cache.demand_mshr_hits::cpu.inst 168 # number of demand (read+write) MSHR hits 845system.cpu.l2cache.demand_mshr_hits::total 168 # number of demand (read+write) MSHR hits 846system.cpu.l2cache.overall_mshr_hits::cpu.inst 168 # number of overall MSHR hits 847system.cpu.l2cache.overall_mshr_hits::total 168 # number of overall MSHR hits |
| 917system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 101 # number of ReadReq MSHR misses 918system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses 919system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 37366 # number of ReadReq MSHR misses 920system.cpu.l2cache.ReadReq_mshr_misses::total 37470 # number of ReadReq MSHR misses 921system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2773 # number of UpgradeReq MSHR misses 922system.cpu.l2cache.UpgradeReq_mshr_misses::total 2773 # number of UpgradeReq MSHR misses | 848system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 97 # number of ReadReq MSHR misses 849system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 850system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 37365 # number of ReadReq MSHR misses 851system.cpu.l2cache.ReadReq_mshr_misses::total 37464 # number of ReadReq MSHR misses 852system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2776 # number of UpgradeReq MSHR misses 853system.cpu.l2cache.UpgradeReq_mshr_misses::total 2776 # number of UpgradeReq MSHR misses |
| 923system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst 2 # number of SCUpgradeReq MSHR misses 924system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses | 854system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst 2 # number of SCUpgradeReq MSHR misses 855system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses |
| 925system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 131687 # number of ReadExReq MSHR misses 926system.cpu.l2cache.ReadExReq_mshr_misses::total 131687 # number of ReadExReq MSHR misses 927system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 101 # number of demand (read+write) MSHR misses 928system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses 929system.cpu.l2cache.demand_mshr_misses::cpu.inst 169053 # number of demand (read+write) MSHR misses 930system.cpu.l2cache.demand_mshr_misses::total 169157 # number of demand (read+write) MSHR misses 931system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 101 # number of overall MSHR misses 932system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses 933system.cpu.l2cache.overall_mshr_misses::cpu.inst 169053 # number of overall MSHR misses 934system.cpu.l2cache.overall_mshr_misses::total 169157 # number of overall MSHR misses 935system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 6559500 # number of ReadReq MSHR miss cycles 936system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 187500 # number of ReadReq MSHR miss cycles 937system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2294945750 # number of ReadReq MSHR miss cycles 938system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2301692750 # number of ReadReq MSHR miss cycles 939system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 27763773 # number of UpgradeReq MSHR miss cycles 940system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27763773 # number of UpgradeReq MSHR miss cycles | 856system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 131700 # number of ReadExReq MSHR misses 857system.cpu.l2cache.ReadExReq_mshr_misses::total 131700 # number of ReadExReq MSHR misses 858system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 97 # number of demand (read+write) MSHR misses 859system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 860system.cpu.l2cache.demand_mshr_misses::cpu.inst 169065 # number of demand (read+write) MSHR misses 861system.cpu.l2cache.demand_mshr_misses::total 169164 # number of demand (read+write) MSHR misses 862system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 97 # number of overall MSHR misses 863system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 864system.cpu.l2cache.overall_mshr_misses::cpu.inst 169065 # number of overall MSHR misses 865system.cpu.l2cache.overall_mshr_misses::total 169164 # number of overall MSHR misses 866system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 6323250 # number of ReadReq MSHR miss cycles 867system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles 868system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2300603500 # number of ReadReq MSHR miss cycles 869system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2307051750 # number of ReadReq MSHR miss cycles 870system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 27795276 # number of UpgradeReq MSHR miss cycles 871system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27795276 # number of UpgradeReq MSHR miss cycles |
| 941system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst 20002 # number of SCUpgradeReq MSHR miss cycles 942system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles | 872system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst 20002 # number of SCUpgradeReq MSHR miss cycles 873system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles |
| 943system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7581141318 # number of ReadExReq MSHR miss cycles 944system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7581141318 # number of ReadExReq MSHR miss cycles 945system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 6559500 # number of demand (read+write) MSHR miss cycles 946system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 187500 # number of demand (read+write) MSHR miss cycles 947system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9876087068 # number of demand (read+write) MSHR miss cycles 948system.cpu.l2cache.demand_mshr_miss_latency::total 9882834068 # number of demand (read+write) MSHR miss cycles 949system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 6559500 # number of overall MSHR miss cycles 950system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 187500 # number of overall MSHR miss cycles 951system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9876087068 # number of overall MSHR miss cycles 952system.cpu.l2cache.overall_mshr_miss_latency::total 9882834068 # number of overall MSHR miss cycles 953system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5545310750 # number of ReadReq MSHR uncacheable cycles 954system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545310750 # number of ReadReq MSHR uncacheable cycles 955system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 4106655500 # number of WriteReq MSHR uncacheable cycles 956system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4106655500 # number of WriteReq MSHR uncacheable cycles 957system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 9651966250 # number of overall MSHR uncacheable cycles 958system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9651966250 # number of overall MSHR uncacheable cycles 959system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001462 # mshr miss rate for ReadReq accesses 960system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000626 # mshr miss rate for ReadReq accesses 961system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010852 # mshr miss rate for ReadReq accesses 962system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010653 # mshr miss rate for ReadReq accesses 963system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.984031 # mshr miss rate for UpgradeReq accesses 964system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984031 # mshr miss rate for UpgradeReq accesses | 874system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7582295069 # number of ReadExReq MSHR miss cycles 875system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7582295069 # number of ReadExReq MSHR miss cycles 876system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 6323250 # number of demand (read+write) MSHR miss cycles 877system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 878system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9882898569 # number of demand (read+write) MSHR miss cycles 879system.cpu.l2cache.demand_mshr_miss_latency::total 9889346819 # number of demand (read+write) MSHR miss cycles 880system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 6323250 # number of overall MSHR miss cycles 881system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles 882system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9882898569 # number of overall MSHR miss cycles 883system.cpu.l2cache.overall_mshr_miss_latency::total 9889346819 # number of overall MSHR miss cycles 884system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5545290750 # number of ReadReq MSHR uncacheable cycles 885system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545290750 # number of ReadReq MSHR uncacheable cycles 886system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 4106643000 # number of WriteReq MSHR uncacheable cycles 887system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4106643000 # number of WriteReq MSHR uncacheable cycles 888system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 9651933750 # number of overall MSHR uncacheable cycles 889system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9651933750 # number of overall MSHR uncacheable cycles 890system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001403 # mshr miss rate for ReadReq accesses 891system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000418 # mshr miss rate for ReadReq accesses 892system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010849 # mshr miss rate for ReadReq accesses 893system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010649 # mshr miss rate for ReadReq accesses 894system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.984048 # mshr miss rate for UpgradeReq accesses 895system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984048 # mshr miss rate for UpgradeReq accesses |
| 965system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses 966system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses | 896system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses 897system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses |
| 967system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.445257 # mshr miss rate for ReadExReq accesses 968system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.445257 # mshr miss rate for ReadExReq accesses 969system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001462 # mshr miss rate for demand accesses 970system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000626 # mshr miss rate for demand accesses 971system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.045212 # mshr miss rate for demand accesses 972system.cpu.l2cache.demand_mshr_miss_rate::total 0.044363 # mshr miss rate for demand accesses 973system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001462 # mshr miss rate for overall accesses 974system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000626 # mshr miss rate for overall accesses 975system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.045212 # mshr miss rate for overall accesses 976system.cpu.l2cache.overall_mshr_miss_rate::total 0.044363 # mshr miss rate for overall accesses 977system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64945.544554 # average ReadReq mshr miss latency | 898system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.445227 # mshr miss rate for ReadExReq accesses 899system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.445227 # mshr miss rate for ReadExReq accesses 900system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001403 # mshr miss rate for demand accesses 901system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000418 # mshr miss rate for demand accesses 902system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.045204 # mshr miss rate for demand accesses 903system.cpu.l2cache.demand_mshr_miss_rate::total 0.044354 # mshr miss rate for demand accesses 904system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001403 # mshr miss rate for overall accesses 905system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000418 # mshr miss rate for overall accesses 906system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.045204 # mshr miss rate for overall accesses 907system.cpu.l2cache.overall_mshr_miss_rate::total 0.044354 # mshr miss rate for overall accesses 908system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65188.144330 # average ReadReq mshr miss latency |
| 978system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency | 909system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency |
| 979system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61418.020393 # average ReadReq mshr miss latency 980system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61427.615426 # average ReadReq mshr miss latency 981system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10012.179228 # average UpgradeReq mshr miss latency 982system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10012.179228 # average UpgradeReq mshr miss latency | 910system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61571.082564 # average ReadReq mshr miss latency 911system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61580.497277 # average ReadReq mshr miss latency 912system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10012.707493 # average UpgradeReq mshr miss latency 913system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10012.707493 # average UpgradeReq mshr miss latency |
| 983system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 10001 # average SCUpgradeReq mshr miss latency 984system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency | 914system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 10001 # average SCUpgradeReq mshr miss latency 915system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency |
| 985system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57569.398027 # average ReadExReq mshr miss latency 986system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57569.398027 # average ReadExReq mshr miss latency 987system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64945.544554 # average overall mshr miss latency | 916system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57572.475847 # average ReadExReq mshr miss latency 917system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57572.475847 # average ReadExReq mshr miss latency 918system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65188.144330 # average overall mshr miss latency |
| 988system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency | 919system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency |
| 989system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58420.063933 # average overall mshr miss latency 990system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58424.032514 # average overall mshr miss latency 991system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64945.544554 # average overall mshr miss latency | 920system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58456.206601 # average overall mshr miss latency 921system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58460.114557 # average overall mshr miss latency 922system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65188.144330 # average overall mshr miss latency |
| 992system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency | 923system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency |
| 993system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58420.063933 # average overall mshr miss latency 994system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58424.032514 # average overall mshr miss latency | 924system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58456.206601 # average overall mshr miss latency 925system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58460.114557 # average overall mshr miss latency |
| 995system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 996system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 997system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 998system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 999system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1000system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1001system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 926system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 927system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 928system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 929system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 930system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 931system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 932system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1002system.cpu.dcache.tags.replacements 840767 # number of replacements 1003system.cpu.dcache.tags.tagsinuse 511.953448 # Cycle average of tags in use 1004system.cpu.dcache.tags.total_refs 42450068 # Total number of references to valid blocks. 1005system.cpu.dcache.tags.sampled_refs 841279 # Sample count of references to valid blocks. 1006system.cpu.dcache.tags.avg_refs 50.458965 # Average number of references to valid blocks. 1007system.cpu.dcache.tags.warmup_cycle 279721250 # Cycle when the warmup percentage was hit. 1008system.cpu.dcache.tags.occ_blocks::cpu.inst 511.953448 # Average occupied blocks per requestor 1009system.cpu.dcache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy 1010system.cpu.dcache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy 1011system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1012system.cpu.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 1013system.cpu.dcache.tags.age_task_id_blocks_1024::1 358 # Occupied blocks per task id 1014system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id 1015system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1016system.cpu.dcache.tags.tag_accesses 175160699 # Number of tag accesses 1017system.cpu.dcache.tags.data_accesses 175160699 # Number of data accesses 1018system.cpu.dcache.ReadReq_hits::cpu.inst 23317429 # number of ReadReq hits 1019system.cpu.dcache.ReadReq_hits::total 23317429 # number of ReadReq hits 1020system.cpu.dcache.WriteReq_hits::cpu.inst 18211581 # number of WriteReq hits 1021system.cpu.dcache.WriteReq_hits::total 18211581 # number of WriteReq hits 1022system.cpu.dcache.LoadLockedReq_hits::cpu.inst 457826 # number of LoadLockedReq hits 1023system.cpu.dcache.LoadLockedReq_hits::total 457826 # number of LoadLockedReq hits 1024system.cpu.dcache.StoreCondReq_hits::cpu.inst 460320 # number of StoreCondReq hits 1025system.cpu.dcache.StoreCondReq_hits::total 460320 # number of StoreCondReq hits 1026system.cpu.dcache.demand_hits::cpu.inst 41529010 # number of demand (read+write) hits 1027system.cpu.dcache.demand_hits::total 41529010 # number of demand (read+write) hits 1028system.cpu.dcache.overall_hits::cpu.inst 41529010 # number of overall hits 1029system.cpu.dcache.overall_hits::total 41529010 # number of overall hits 1030system.cpu.dcache.ReadReq_misses::cpu.inst 583115 # number of ReadReq misses 1031system.cpu.dcache.ReadReq_misses::total 583115 # number of ReadReq misses 1032system.cpu.dcache.WriteReq_misses::cpu.inst 541259 # number of WriteReq misses 1033system.cpu.dcache.WriteReq_misses::total 541259 # number of WriteReq misses 1034system.cpu.dcache.LoadLockedReq_misses::cpu.inst 8317 # number of LoadLockedReq misses 1035system.cpu.dcache.LoadLockedReq_misses::total 8317 # number of LoadLockedReq misses 1036system.cpu.dcache.StoreCondReq_misses::cpu.inst 2 # number of StoreCondReq misses 1037system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 1038system.cpu.dcache.demand_misses::cpu.inst 1124374 # number of demand (read+write) misses 1039system.cpu.dcache.demand_misses::total 1124374 # number of demand (read+write) misses 1040system.cpu.dcache.overall_misses::cpu.inst 1124374 # number of overall misses 1041system.cpu.dcache.overall_misses::total 1124374 # number of overall misses 1042system.cpu.dcache.ReadReq_miss_latency::cpu.inst 8642422585 # number of ReadReq miss cycles 1043system.cpu.dcache.ReadReq_miss_latency::total 8642422585 # number of ReadReq miss cycles 1044system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21588022799 # number of WriteReq miss cycles 1045system.cpu.dcache.WriteReq_miss_latency::total 21588022799 # number of WriteReq miss cycles 1046system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 117987000 # number of LoadLockedReq miss cycles 1047system.cpu.dcache.LoadLockedReq_miss_latency::total 117987000 # number of LoadLockedReq miss cycles 1048system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 53002 # number of StoreCondReq miss cycles 1049system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles 1050system.cpu.dcache.demand_miss_latency::cpu.inst 30230445384 # number of demand (read+write) miss cycles 1051system.cpu.dcache.demand_miss_latency::total 30230445384 # number of demand (read+write) miss cycles 1052system.cpu.dcache.overall_miss_latency::cpu.inst 30230445384 # number of overall miss cycles 1053system.cpu.dcache.overall_miss_latency::total 30230445384 # number of overall miss cycles 1054system.cpu.dcache.ReadReq_accesses::cpu.inst 23900544 # number of ReadReq accesses(hits+misses) 1055system.cpu.dcache.ReadReq_accesses::total 23900544 # number of ReadReq accesses(hits+misses) 1056system.cpu.dcache.WriteReq_accesses::cpu.inst 18752840 # number of WriteReq accesses(hits+misses) 1057system.cpu.dcache.WriteReq_accesses::total 18752840 # number of WriteReq accesses(hits+misses) 1058system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 466143 # number of LoadLockedReq accesses(hits+misses) 1059system.cpu.dcache.LoadLockedReq_accesses::total 466143 # number of LoadLockedReq accesses(hits+misses) 1060system.cpu.dcache.StoreCondReq_accesses::cpu.inst 460322 # number of StoreCondReq accesses(hits+misses) 1061system.cpu.dcache.StoreCondReq_accesses::total 460322 # number of StoreCondReq accesses(hits+misses) 1062system.cpu.dcache.demand_accesses::cpu.inst 42653384 # number of demand (read+write) accesses 1063system.cpu.dcache.demand_accesses::total 42653384 # number of demand (read+write) accesses 1064system.cpu.dcache.overall_accesses::cpu.inst 42653384 # number of overall (read+write) accesses 1065system.cpu.dcache.overall_accesses::total 42653384 # number of overall (read+write) accesses 1066system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.024398 # miss rate for ReadReq accesses 1067system.cpu.dcache.ReadReq_miss_rate::total 0.024398 # miss rate for ReadReq accesses 1068system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.028863 # miss rate for WriteReq accesses 1069system.cpu.dcache.WriteReq_miss_rate::total 0.028863 # miss rate for WriteReq accesses 1070system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.017842 # miss rate for LoadLockedReq accesses 1071system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017842 # miss rate for LoadLockedReq accesses 1072system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000004 # miss rate for StoreCondReq accesses 1073system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 1074system.cpu.dcache.demand_miss_rate::cpu.inst 0.026361 # miss rate for demand accesses 1075system.cpu.dcache.demand_miss_rate::total 0.026361 # miss rate for demand accesses 1076system.cpu.dcache.overall_miss_rate::cpu.inst 0.026361 # miss rate for overall accesses 1077system.cpu.dcache.overall_miss_rate::total 0.026361 # miss rate for overall accesses 1078system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14821.128911 # average ReadReq miss latency 1079system.cpu.dcache.ReadReq_avg_miss_latency::total 14821.128911 # average ReadReq miss latency 1080system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39884.829257 # average WriteReq miss latency 1081system.cpu.dcache.WriteReq_avg_miss_latency::total 39884.829257 # average WriteReq miss latency 1082system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14186.245040 # average LoadLockedReq miss latency 1083system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14186.245040 # average LoadLockedReq miss latency 1084system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 26501 # average StoreCondReq miss latency 1085system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency 1086system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26886.467834 # average overall miss latency 1087system.cpu.dcache.demand_avg_miss_latency::total 26886.467834 # average overall miss latency 1088system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26886.467834 # average overall miss latency 1089system.cpu.dcache.overall_avg_miss_latency::total 26886.467834 # average overall miss latency 1090system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1091system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1092system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1093system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1094system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1095system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1096system.cpu.dcache.fast_writes 0 # number of fast writes performed 1097system.cpu.dcache.cache_copies 0 # number of cache copies performed 1098system.cpu.dcache.writebacks::writebacks 697424 # number of writebacks 1099system.cpu.dcache.writebacks::total 697424 # number of writebacks 1100system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 45879 # number of ReadReq MSHR hits 1101system.cpu.dcache.ReadReq_mshr_hits::total 45879 # number of ReadReq MSHR hits 1102system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 242691 # number of WriteReq MSHR hits 1103system.cpu.dcache.WriteReq_mshr_hits::total 242691 # number of WriteReq MSHR hits 1104system.cpu.dcache.demand_mshr_hits::cpu.inst 288570 # number of demand (read+write) MSHR hits 1105system.cpu.dcache.demand_mshr_hits::total 288570 # number of demand (read+write) MSHR hits 1106system.cpu.dcache.overall_mshr_hits::cpu.inst 288570 # number of overall MSHR hits 1107system.cpu.dcache.overall_mshr_hits::total 288570 # number of overall MSHR hits 1108system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 537236 # number of ReadReq MSHR misses 1109system.cpu.dcache.ReadReq_mshr_misses::total 537236 # number of ReadReq MSHR misses 1110system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 298568 # number of WriteReq MSHR misses 1111system.cpu.dcache.WriteReq_mshr_misses::total 298568 # number of WriteReq MSHR misses 1112system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 8317 # number of LoadLockedReq MSHR misses 1113system.cpu.dcache.LoadLockedReq_mshr_misses::total 8317 # number of LoadLockedReq MSHR misses 1114system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 2 # number of StoreCondReq MSHR misses 1115system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 1116system.cpu.dcache.demand_mshr_misses::cpu.inst 835804 # number of demand (read+write) MSHR misses 1117system.cpu.dcache.demand_mshr_misses::total 835804 # number of demand (read+write) MSHR misses 1118system.cpu.dcache.overall_mshr_misses::cpu.inst 835804 # number of overall MSHR misses 1119system.cpu.dcache.overall_mshr_misses::total 835804 # number of overall MSHR misses 1120system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6874982646 # number of ReadReq MSHR miss cycles 1121system.cpu.dcache.ReadReq_mshr_miss_latency::total 6874982646 # number of ReadReq MSHR miss cycles 1122system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 11266915159 # number of WriteReq MSHR miss cycles 1123system.cpu.dcache.WriteReq_mshr_miss_latency::total 11266915159 # number of WriteReq MSHR miss cycles 1124system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 101324000 # number of LoadLockedReq MSHR miss cycles 1125system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 101324000 # number of LoadLockedReq MSHR miss cycles 1126system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 48998 # number of StoreCondReq MSHR miss cycles 1127system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles 1128system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 18141897805 # number of demand (read+write) MSHR miss cycles 1129system.cpu.dcache.demand_mshr_miss_latency::total 18141897805 # number of demand (read+write) MSHR miss cycles 1130system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 18141897805 # number of overall MSHR miss cycles 1131system.cpu.dcache.overall_mshr_miss_latency::total 18141897805 # number of overall MSHR miss cycles 1132system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5791016000 # number of ReadReq MSHR uncacheable cycles 1133system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791016000 # number of ReadReq MSHR uncacheable cycles 1134system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 4439188000 # number of WriteReq MSHR uncacheable cycles 1135system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439188000 # number of WriteReq MSHR uncacheable cycles 1136system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 10230204000 # number of overall MSHR uncacheable cycles 1137system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230204000 # number of overall MSHR uncacheable cycles 1138system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.022478 # mshr miss rate for ReadReq accesses 1139system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022478 # mshr miss rate for ReadReq accesses 1140system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015921 # mshr miss rate for WriteReq accesses 1141system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015921 # mshr miss rate for WriteReq accesses 1142system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.017842 # mshr miss rate for LoadLockedReq accesses 1143system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017842 # mshr miss rate for LoadLockedReq accesses 1144system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for StoreCondReq accesses 1145system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses 1146system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.019595 # mshr miss rate for demand accesses 1147system.cpu.dcache.demand_mshr_miss_rate::total 0.019595 # mshr miss rate for demand accesses 1148system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019595 # mshr miss rate for overall accesses 1149system.cpu.dcache.overall_mshr_miss_rate::total 0.019595 # mshr miss rate for overall accesses 1150system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12796.950774 # average ReadReq mshr miss latency 1151system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12796.950774 # average ReadReq mshr miss latency 1152system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37736.512818 # average WriteReq mshr miss latency 1153system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37736.512818 # average WriteReq mshr miss latency 1154system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12182.758206 # average LoadLockedReq mshr miss latency 1155system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12182.758206 # average LoadLockedReq mshr miss latency 1156system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 24499 # average StoreCondReq mshr miss latency 1157system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency 1158system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21705.923644 # average overall mshr miss latency 1159system.cpu.dcache.demand_avg_mshr_miss_latency::total 21705.923644 # average overall mshr miss latency 1160system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21705.923644 # average overall mshr miss latency 1161system.cpu.dcache.overall_avg_mshr_miss_latency::total 21705.923644 # average overall mshr miss latency 1162system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1163system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1164system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 1165system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1166system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1167system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1168system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 933system.cpu.toL2Bus.trans_dist::ReadReq 3576313 # Transaction distribution 934system.cpu.toL2Bus.trans_dist::ReadResp 3576217 # Transaction distribution 935system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution 936system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution 937system.cpu.toL2Bus.trans_dist::Writeback 697938 # Transaction distribution 938system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution 939system.cpu.toL2Bus.trans_dist::UpgradeReq 2821 # Transaction distribution 940system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 941system.cpu.toL2Bus.trans_dist::UpgradeResp 2823 # Transaction distribution 942system.cpu.toL2Bus.trans_dist::ReadExReq 295804 # Transaction distribution 943system.cpu.toL2Bus.trans_dist::ReadExResp 295804 # Transaction distribution 944system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5802238 # Packet count per connected master and slave (bytes) 945system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2505111 # Packet count per connected master and slave (bytes) 946system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15298 # Packet count per connected master and slave (bytes) 947system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 156293 # Packet count per connected master and slave (bytes) 948system.cpu.toL2Bus.pkt_count::total 8478940 # Packet count per connected master and slave (bytes) 949system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185670592 # Cumulative packet size per connected master and slave (bytes) 950system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98744797 # Cumulative packet size per connected master and slave (bytes) 951system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 19124 # Cumulative packet size per connected master and slave (bytes) 952system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 276596 # Cumulative packet size per connected master and slave (bytes) 953system.cpu.toL2Bus.pkt_size::total 284711109 # Cumulative packet size per connected master and slave (bytes) 954system.cpu.toL2Bus.snoops 60360 # Total snoops (count) 955system.cpu.toL2Bus.snoop_fanout::samples 4574965 # Request fanout histogram 956system.cpu.toL2Bus.snoop_fanout::mean 5.007969 # Request fanout histogram 957system.cpu.toL2Bus.snoop_fanout::stdev 0.088914 # Request fanout histogram 958system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 959system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 960system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 961system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 962system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 963system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 964system.cpu.toL2Bus.snoop_fanout::5 4538506 99.20% 99.20% # Request fanout histogram 965system.cpu.toL2Bus.snoop_fanout::6 36459 0.80% 100.00% # Request fanout histogram 966system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 967system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 968system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 969system.cpu.toL2Bus.snoop_fanout::total 4574965 # Request fanout histogram 970system.cpu.toL2Bus.reqLayer0.occupancy 3011909666 # Layer occupancy (ticks) 971system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 972system.cpu.toL2Bus.snoopLayer0.occupancy 208500 # Layer occupancy (ticks) 973system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 974system.cpu.toL2Bus.respLayer0.occupancy 4357140777 # Layer occupancy (ticks) 975system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 976system.cpu.toL2Bus.respLayer1.occupancy 1340495452 # Layer occupancy (ticks) 977system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 978system.cpu.toL2Bus.respLayer2.occupancy 10517000 # Layer occupancy (ticks) 979system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 980system.cpu.toL2Bus.respLayer3.occupancy 87146500 # Layer occupancy (ticks) 981system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 982system.iobus.trans_dist::ReadReq 30195 # Transaction distribution 983system.iobus.trans_dist::ReadResp 30195 # Transaction distribution 984system.iobus.trans_dist::WriteReq 59038 # Transaction distribution 985system.iobus.trans_dist::WriteResp 59038 # Transaction distribution 986system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) 987system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 988system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 989system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 990system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 991system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 992system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 993system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 994system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 995system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 996system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 997system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 998system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 999system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1000system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1001system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1002system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1003system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1004system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1005system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1006system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1007system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) 1008system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) 1009system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) 1010system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) 1011system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) 1012system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1013system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1014system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1015system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1016system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1017system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1018system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1019system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1020system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1021system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1022system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1023system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1024system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1025system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1026system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1027system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1028system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1029system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1030system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1031system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1032system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) 1033system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 1034system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 1035system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) 1036system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) 1037system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1038system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) 1039system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1040system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 1041system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1042system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 1043system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1044system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 1045system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1046system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) 1047system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1048system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 1049system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1050system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1051system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1052system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1053system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1054system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1055system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1056system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 1057system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1058system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1059system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1060system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1061system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1062system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 1063system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1064system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1065system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1066system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1067system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1068system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1069system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1070system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1071system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1072system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1073system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1074system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1075system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1076system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks) 1077system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1078system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1079system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1080system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) 1081system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1082system.iobus.respLayer3.occupancy 36804753 # Layer occupancy (ticks) 1083system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1169system.iocache.tags.replacements 36424 # number of replacements | 1084system.iocache.tags.replacements 36424 # number of replacements |
| 1170system.iocache.tags.tagsinuse 1.031475 # Cycle average of tags in use | 1085system.iocache.tags.tagsinuse 1.031563 # Cycle average of tags in use |
| 1171system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1172system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1173system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1174system.iocache.tags.warmup_cycle 269946820000 # Cycle when the warmup percentage was hit. | 1086system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1087system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1088system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1089system.iocache.tags.warmup_cycle 269946820000 # Cycle when the warmup percentage was hit. |
| 1175system.iocache.tags.occ_blocks::realview.ide 1.031475 # Average occupied blocks per requestor 1176system.iocache.tags.occ_percent::realview.ide 0.064467 # Average percentage of cache occupancy 1177system.iocache.tags.occ_percent::total 0.064467 # Average percentage of cache occupancy | 1090system.iocache.tags.occ_blocks::realview.ide 1.031563 # Average occupied blocks per requestor 1091system.iocache.tags.occ_percent::realview.ide 0.064473 # Average percentage of cache occupancy 1092system.iocache.tags.occ_percent::total 0.064473 # Average percentage of cache occupancy |
| 1178system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1179system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1180system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1181system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1182system.iocache.tags.data_accesses 328122 # Number of data accesses 1183system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 1184system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 1185system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1186system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1187system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses 1188system.iocache.demand_misses::total 234 # number of demand (read+write) misses 1189system.iocache.overall_misses::realview.ide 234 # number of overall misses 1190system.iocache.overall_misses::total 234 # number of overall misses | 1093system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1094system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1095system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1096system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1097system.iocache.tags.data_accesses 328122 # Number of data accesses 1098system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 1099system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 1100system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1101system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1102system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses 1103system.iocache.demand_misses::total 234 # number of demand (read+write) misses 1104system.iocache.overall_misses::realview.ide 234 # number of overall misses 1105system.iocache.overall_misses::total 234 # number of overall misses |
| 1191system.iocache.ReadReq_miss_latency::realview.ide 27954377 # number of ReadReq miss cycles 1192system.iocache.ReadReq_miss_latency::total 27954377 # number of ReadReq miss cycles 1193system.iocache.demand_miss_latency::realview.ide 27954377 # number of demand (read+write) miss cycles 1194system.iocache.demand_miss_latency::total 27954377 # number of demand (read+write) miss cycles 1195system.iocache.overall_miss_latency::realview.ide 27954377 # number of overall miss cycles 1196system.iocache.overall_miss_latency::total 27954377 # number of overall miss cycles | 1106system.iocache.ReadReq_miss_latency::realview.ide 27956377 # number of ReadReq miss cycles 1107system.iocache.ReadReq_miss_latency::total 27956377 # number of ReadReq miss cycles 1108system.iocache.demand_miss_latency::realview.ide 27956377 # number of demand (read+write) miss cycles 1109system.iocache.demand_miss_latency::total 27956377 # number of demand (read+write) miss cycles 1110system.iocache.overall_miss_latency::realview.ide 27956377 # number of overall miss cycles 1111system.iocache.overall_miss_latency::total 27956377 # number of overall miss cycles |
| 1197system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1198system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1199system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1200system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 1201system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses 1202system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses 1203system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses 1204system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses 1205system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1206system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1207system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1208system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1209system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1210system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1112system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1113system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1114system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1115system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 1116system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses 1117system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses 1118system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses 1119system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses 1120system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1121system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1122system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1123system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1124system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1125system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1211system.iocache.ReadReq_avg_miss_latency::realview.ide 119463.149573 # average ReadReq miss latency 1212system.iocache.ReadReq_avg_miss_latency::total 119463.149573 # average ReadReq miss latency 1213system.iocache.demand_avg_miss_latency::realview.ide 119463.149573 # average overall miss latency 1214system.iocache.demand_avg_miss_latency::total 119463.149573 # average overall miss latency 1215system.iocache.overall_avg_miss_latency::realview.ide 119463.149573 # average overall miss latency 1216system.iocache.overall_avg_miss_latency::total 119463.149573 # average overall miss latency | 1126system.iocache.ReadReq_avg_miss_latency::realview.ide 119471.696581 # average ReadReq miss latency 1127system.iocache.ReadReq_avg_miss_latency::total 119471.696581 # average ReadReq miss latency 1128system.iocache.demand_avg_miss_latency::realview.ide 119471.696581 # average overall miss latency 1129system.iocache.demand_avg_miss_latency::total 119471.696581 # average overall miss latency 1130system.iocache.overall_avg_miss_latency::realview.ide 119471.696581 # average overall miss latency 1131system.iocache.overall_avg_miss_latency::total 119471.696581 # average overall miss latency |
| 1217system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1218system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1219system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1220system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1221system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1222system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1223system.iocache.fast_writes 36224 # number of fast writes performed 1224system.iocache.cache_copies 0 # number of cache copies performed 1225system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1226system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1227system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses 1228system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses 1229system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses 1230system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses | 1132system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1133system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1134system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1135system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1136system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1137system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1138system.iocache.fast_writes 36224 # number of fast writes performed 1139system.iocache.cache_copies 0 # number of cache copies performed 1140system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1141system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1142system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses 1143system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses 1144system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses 1145system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses |
| 1231system.iocache.ReadReq_mshr_miss_latency::realview.ide 15785377 # number of ReadReq MSHR miss cycles 1232system.iocache.ReadReq_mshr_miss_latency::total 15785377 # number of ReadReq MSHR miss cycles 1233system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2212496723 # number of WriteInvalidateReq MSHR miss cycles 1234system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2212496723 # number of WriteInvalidateReq MSHR miss cycles 1235system.iocache.demand_mshr_miss_latency::realview.ide 15785377 # number of demand (read+write) MSHR miss cycles 1236system.iocache.demand_mshr_miss_latency::total 15785377 # number of demand (read+write) MSHR miss cycles 1237system.iocache.overall_mshr_miss_latency::realview.ide 15785377 # number of overall MSHR miss cycles 1238system.iocache.overall_mshr_miss_latency::total 15785377 # number of overall MSHR miss cycles | 1146system.iocache.ReadReq_mshr_miss_latency::realview.ide 15787377 # number of ReadReq MSHR miss cycles 1147system.iocache.ReadReq_mshr_miss_latency::total 15787377 # number of ReadReq MSHR miss cycles 1148system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2211427725 # number of WriteInvalidateReq MSHR miss cycles 1149system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2211427725 # number of WriteInvalidateReq MSHR miss cycles 1150system.iocache.demand_mshr_miss_latency::realview.ide 15787377 # number of demand (read+write) MSHR miss cycles 1151system.iocache.demand_mshr_miss_latency::total 15787377 # number of demand (read+write) MSHR miss cycles 1152system.iocache.overall_mshr_miss_latency::realview.ide 15787377 # number of overall MSHR miss cycles 1153system.iocache.overall_mshr_miss_latency::total 15787377 # number of overall MSHR miss cycles |
| 1239system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1240system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1241system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1242system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1243system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1244system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1154system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1155system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1156system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1157system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1158system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1159system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1245system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67458.876068 # average ReadReq mshr miss latency 1246system.iocache.ReadReq_avg_mshr_miss_latency::total 67458.876068 # average ReadReq mshr miss latency | 1160system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67467.423077 # average ReadReq mshr miss latency 1161system.iocache.ReadReq_avg_mshr_miss_latency::total 67467.423077 # average ReadReq mshr miss latency |
| 1247system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 1248system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency | 1162system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 1163system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency |
| 1249system.iocache.demand_avg_mshr_miss_latency::realview.ide 67458.876068 # average overall mshr miss latency 1250system.iocache.demand_avg_mshr_miss_latency::total 67458.876068 # average overall mshr miss latency 1251system.iocache.overall_avg_mshr_miss_latency::realview.ide 67458.876068 # average overall mshr miss latency 1252system.iocache.overall_avg_mshr_miss_latency::total 67458.876068 # average overall mshr miss latency | 1164system.iocache.demand_avg_mshr_miss_latency::realview.ide 67467.423077 # average overall mshr miss latency 1165system.iocache.demand_avg_mshr_miss_latency::total 67467.423077 # average overall mshr miss latency 1166system.iocache.overall_avg_mshr_miss_latency::realview.ide 67467.423077 # average overall mshr miss latency 1167system.iocache.overall_avg_mshr_miss_latency::total 67467.423077 # average overall mshr miss latency |
| 1253system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1168system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1169system.membus.trans_dist::ReadReq 71836 # Transaction distribution 1170system.membus.trans_dist::ReadResp 71836 # Transaction distribution 1171system.membus.trans_dist::WriteReq 27607 # Transaction distribution 1172system.membus.trans_dist::WriteResp 27607 # Transaction distribution 1173system.membus.trans_dist::Writeback 88794 # Transaction distribution 1174system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1175system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 1176system.membus.trans_dist::UpgradeReq 4595 # Transaction distribution 1177system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1178system.membus.trans_dist::UpgradeResp 4597 # Transaction distribution 1179system.membus.trans_dist::ReadExReq 129881 # Transaction distribution 1180system.membus.trans_dist::ReadExResp 129881 # Transaction distribution 1181system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) 1182system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) 1183system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) 1184system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 448536 # Packet count per connected master and slave (bytes) 1185system.membus.pkt_count_system.cpu.l2cache.mem_side::total 556168 # Packet count per connected master and slave (bytes) 1186system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) 1187system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) 1188system.membus.pkt_count::total 628865 # Packet count per connected master and slave (bytes) 1189system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) 1190system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) 1191system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) 1192system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16604248 # Cumulative packet size per connected master and slave (bytes) 1193system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16768029 # Cumulative packet size per connected master and slave (bytes) 1194system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 1195system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) 1196system.membus.pkt_size::total 19087325 # Cumulative packet size per connected master and slave (bytes) 1197system.membus.snoops 219 # Total snoops (count) 1198system.membus.snoop_fanout::samples 297195 # Request fanout histogram 1199system.membus.snoop_fanout::mean 1 # Request fanout histogram 1200system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1201system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1202system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1203system.membus.snoop_fanout::1 297195 100.00% 100.00% # Request fanout histogram 1204system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1205system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1206system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1207system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1208system.membus.snoop_fanout::total 297195 # Request fanout histogram 1209system.membus.reqLayer0.occupancy 87032500 # Layer occupancy (ticks) 1210system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1211system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) 1212system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1213system.membus.reqLayer2.occupancy 1706500 # Layer occupancy (ticks) 1214system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1215system.membus.reqLayer5.occupancy 1386266250 # Layer occupancy (ticks) 1216system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1217system.membus.respLayer2.occupancy 1718628403 # Layer occupancy (ticks) 1218system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 1219system.membus.respLayer3.occupancy 38334247 # Layer occupancy (ticks) 1220system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1221system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1222system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1223system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1224system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1225system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1226system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1227system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1228system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1229system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1230system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1231system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1232system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1233system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1234system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1235system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1236system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1237system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1238system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1239system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1240system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1241system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1242system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1243system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1244system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1245system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1246system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1247system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1248system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1249system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1250system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1251system.realview.ethernet.droppedPackets 0 # number of packets dropped |
|
| 1254 1255---------- End Simulation Statistics ---------- | 1252 1253---------- End Simulation Statistics ---------- |