| stats.txt (10352:5f1f92bf76ee) | stats.txt (10369:cc10d6851778) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.566439 # Number of seconds simulated 4sim_ticks 2566439177500 # Number of ticks simulated 5final_tick 2566439177500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.566439 # Number of seconds simulated 4sim_ticks 2566439177500 # Number of ticks simulated 5final_tick 2566439177500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 73545 # Simulator instruction rate (inst/s) 8host_op_rate 88536 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3115018228 # Simulator tick rate (ticks/s) 10host_mem_usage 470576 # Number of bytes of host memory used 11host_seconds 823.89 # Real time elapsed on the host | 7host_inst_rate 109798 # Simulator instruction rate (inst/s) 8host_op_rate 132178 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4650508258 # Simulator tick rate (ticks/s) 10host_mem_usage 408644 # Number of bytes of host memory used 11host_seconds 551.86 # Real time elapsed on the host |
| 12sim_insts 60593470 # Number of instructions simulated 13sim_ops 72944147 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 60593470 # Number of instructions simulated 13sim_ops 72944147 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.realview.nvmem.bytes_read::cpu.inst 256 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::total 256 # Number of bytes read from this memory 18system.realview.nvmem.bytes_inst_read::cpu.inst 256 # Number of instructions bytes read from this memory 19system.realview.nvmem.bytes_inst_read::total 256 # Number of instructions bytes read from this memory 20system.realview.nvmem.num_reads::cpu.inst 4 # Number of read requests responded to by this memory 21system.realview.nvmem.num_reads::total 4 # Number of read requests responded to by this memory 22system.realview.nvmem.bw_read::cpu.inst 100 # Total read bandwidth from this memory (bytes/s) 23system.realview.nvmem.bw_read::total 100 # Total read bandwidth from this memory (bytes/s) 24system.realview.nvmem.bw_inst_read::cpu.inst 100 # Instruction read bandwidth from this memory (bytes/s) 25system.realview.nvmem.bw_inst_read::total 100 # Instruction read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_total::cpu.inst 100 # Total bandwidth to/from this memory (bytes/s) 27system.realview.nvmem.bw_total::total 100 # Total bandwidth to/from this memory (bytes/s) |
|
| 16system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 10079960 # Number of bytes read from this memory 20system.physmem.bytes_read::total 131191960 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 1001344 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 1001344 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 3811328 # Number of bytes written to this memory --- 207 unchanged lines hidden (view full) --- 231system.physmem.wrPerTurnAround::gmean 17.203067 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::stdev 0.975146 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::16 2381 38.41% 38.41% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::17 18 0.29% 38.70% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::18 3787 61.09% 99.79% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::19 12 0.19% 99.98% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::total 6199 # Writes before turning the bus around for reads | 28system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory 29system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory 30system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 31system.physmem.bytes_read::cpu.inst 10079960 # Number of bytes read from this memory 32system.physmem.bytes_read::total 131191960 # Number of bytes read from this memory 33system.physmem.bytes_inst_read::cpu.inst 1001344 # Number of instructions bytes read from this memory 34system.physmem.bytes_inst_read::total 1001344 # Number of instructions bytes read from this memory 35system.physmem.bytes_written::writebacks 3811328 # Number of bytes written to this memory --- 207 unchanged lines hidden (view full) --- 243system.physmem.wrPerTurnAround::gmean 17.203067 # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::stdev 0.975146 # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::16 2381 38.41% 38.41% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::17 18 0.29% 38.70% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::18 3787 61.09% 99.79% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::19 12 0.19% 99.98% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::total 6199 # Writes before turning the bus around for reads |
| 239system.physmem.totQLat 394563559000 # Total ticks spent queuing 240system.physmem.totMemAccLat 681341509000 # Total ticks spent from burst creation until serviced by the DRAM | 251system.physmem.totQLat 394563558000 # Total ticks spent queuing 252system.physmem.totMemAccLat 681341508000 # Total ticks spent from burst creation until serviced by the DRAM |
| 241system.physmem.totBusLat 76474120000 # Total ticks spent in databus transfers 242system.physmem.avgQLat 25797.20 # Average queueing delay per DRAM burst 243system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 244system.physmem.avgMemAccLat 44547.20 # Average memory access latency per DRAM burst 245system.physmem.avgRdBW 381.41 # Average DRAM read bandwidth in MiByte/s 246system.physmem.avgWrBW 2.66 # Average achieved write bandwidth in MiByte/s 247system.physmem.avgRdBWSys 51.12 # Average system read bandwidth in MiByte/s 248system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s --- 9 unchanged lines hidden (view full) --- 258system.physmem.writeRowHitRate 83.72 # Row buffer hit rate for writes 259system.physmem.avgGap 159307.76 # Average gap between requests 260system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined 261system.physmem.memoryStateTime::IDLE 2209628504250 # Time in different power states 262system.physmem.memoryStateTime::REF 85698860000 # Time in different power states 263system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 264system.physmem.memoryStateTime::ACT 271106544500 # Time in different power states 265system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 253system.physmem.totBusLat 76474120000 # Total ticks spent in databus transfers 254system.physmem.avgQLat 25797.20 # Average queueing delay per DRAM burst 255system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 256system.physmem.avgMemAccLat 44547.20 # Average memory access latency per DRAM burst 257system.physmem.avgRdBW 381.41 # Average DRAM read bandwidth in MiByte/s 258system.physmem.avgWrBW 2.66 # Average achieved write bandwidth in MiByte/s 259system.physmem.avgRdBWSys 51.12 # Average system read bandwidth in MiByte/s 260system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s --- 9 unchanged lines hidden (view full) --- 270system.physmem.writeRowHitRate 83.72 # Row buffer hit rate for writes 271system.physmem.avgGap 159307.76 # Average gap between requests 272system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined 273system.physmem.memoryStateTime::IDLE 2209628504250 # Time in different power states 274system.physmem.memoryStateTime::REF 85698860000 # Time in different power states 275system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 276system.physmem.memoryStateTime::ACT 271106544500 # Time in different power states 277system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 266system.realview.nvmem.bytes_read::cpu.inst 256 # Number of bytes read from this memory 267system.realview.nvmem.bytes_read::total 256 # Number of bytes read from this memory 268system.realview.nvmem.bytes_inst_read::cpu.inst 256 # Number of instructions bytes read from this memory 269system.realview.nvmem.bytes_inst_read::total 256 # Number of instructions bytes read from this memory 270system.realview.nvmem.num_reads::cpu.inst 4 # Number of read requests responded to by this memory 271system.realview.nvmem.num_reads::total 4 # Number of read requests responded to by this memory 272system.realview.nvmem.bw_read::cpu.inst 100 # Total read bandwidth from this memory (bytes/s) 273system.realview.nvmem.bw_read::total 100 # Total read bandwidth from this memory (bytes/s) 274system.realview.nvmem.bw_inst_read::cpu.inst 100 # Instruction read bandwidth from this memory (bytes/s) 275system.realview.nvmem.bw_inst_read::total 100 # Instruction read bandwidth from this memory (bytes/s) 276system.realview.nvmem.bw_total::cpu.inst 100 # Total bandwidth to/from this memory (bytes/s) 277system.realview.nvmem.bw_total::total 100 # Total bandwidth to/from this memory (bytes/s) | |
| 278system.membus.throughput 54713053 # Throughput (bytes/s) 279system.membus.trans_dist::ReadReq 16348871 # Transaction distribution 280system.membus.trans_dist::ReadResp 16348871 # Transaction distribution 281system.membus.trans_dist::WriteReq 763365 # Transaction distribution 282system.membus.trans_dist::WriteResp 763365 # Transaction distribution 283system.membus.trans_dist::Writeback 59552 # Transaction distribution 284system.membus.trans_dist::UpgradeReq 4670 # Transaction distribution 285system.membus.trans_dist::UpgradeResp 4670 # Transaction distribution --- 22 unchanged lines hidden (view full) --- 308system.membus.reqLayer0.occupancy 1781248000 # Layer occupancy (ticks) 309system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 310system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) 311system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 312system.membus.reqLayer2.occupancy 3519500 # Layer occupancy (ticks) 313system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 314system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) 315system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 278system.membus.throughput 54713053 # Throughput (bytes/s) 279system.membus.trans_dist::ReadReq 16348871 # Transaction distribution 280system.membus.trans_dist::ReadResp 16348871 # Transaction distribution 281system.membus.trans_dist::WriteReq 763365 # Transaction distribution 282system.membus.trans_dist::WriteResp 763365 # Transaction distribution 283system.membus.trans_dist::Writeback 59552 # Transaction distribution 284system.membus.trans_dist::UpgradeReq 4670 # Transaction distribution 285system.membus.trans_dist::UpgradeResp 4670 # Transaction distribution --- 22 unchanged lines hidden (view full) --- 308system.membus.reqLayer0.occupancy 1781248000 # Layer occupancy (ticks) 309system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 310system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) 311system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 312system.membus.reqLayer2.occupancy 3519500 # Layer occupancy (ticks) 313system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 314system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) 315system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 316system.membus.reqLayer6.occupancy 17618628000 # Layer occupancy (ticks) | 316system.membus.reqLayer6.occupancy 17618629000 # Layer occupancy (ticks) |
| 317system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) | 317system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) |
| 318system.membus.respLayer1.occupancy 4827706725 # Layer occupancy (ticks) | 318system.membus.respLayer1.occupancy 4827707725 # Layer occupancy (ticks) |
| 319system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 320system.membus.respLayer2.occupancy 37448813750 # Layer occupancy (ticks) 321system.membus.respLayer2.utilization 1.5 # Layer utilization (%) 322system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 323system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 324system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 325system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 326system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. --- 286 unchanged lines hidden (view full) --- 613system.cpu.icache.overall_mshr_misses::cpu.inst 1529816 # number of overall MSHR misses 614system.cpu.icache.overall_mshr_misses::total 1529816 # number of overall MSHR misses 615system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17611902863 # number of ReadReq MSHR miss cycles 616system.cpu.icache.ReadReq_mshr_miss_latency::total 17611902863 # number of ReadReq MSHR miss cycles 617system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17611902863 # number of demand (read+write) MSHR miss cycles 618system.cpu.icache.demand_mshr_miss_latency::total 17611902863 # number of demand (read+write) MSHR miss cycles 619system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17611902863 # number of overall MSHR miss cycles 620system.cpu.icache.overall_mshr_miss_latency::total 17611902863 # number of overall MSHR miss cycles | 319system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 320system.membus.respLayer2.occupancy 37448813750 # Layer occupancy (ticks) 321system.membus.respLayer2.utilization 1.5 # Layer utilization (%) 322system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 323system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 324system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 325system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 326system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. --- 286 unchanged lines hidden (view full) --- 613system.cpu.icache.overall_mshr_misses::cpu.inst 1529816 # number of overall MSHR misses 614system.cpu.icache.overall_mshr_misses::total 1529816 # number of overall MSHR misses 615system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17611902863 # number of ReadReq MSHR miss cycles 616system.cpu.icache.ReadReq_mshr_miss_latency::total 17611902863 # number of ReadReq MSHR miss cycles 617system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17611902863 # number of demand (read+write) MSHR miss cycles 618system.cpu.icache.demand_mshr_miss_latency::total 17611902863 # number of demand (read+write) MSHR miss cycles 619system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17611902863 # number of overall MSHR miss cycles 620system.cpu.icache.overall_mshr_miss_latency::total 17611902863 # number of overall MSHR miss cycles |
| 621system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 172141250 # number of ReadReq MSHR uncacheable cycles 622system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 172141250 # number of ReadReq MSHR uncacheable cycles 623system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 172141250 # number of overall MSHR uncacheable cycles 624system.cpu.icache.overall_mshr_uncacheable_latency::total 172141250 # number of overall MSHR uncacheable cycles | 621system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 172140750 # number of ReadReq MSHR uncacheable cycles 622system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 172140750 # number of ReadReq MSHR uncacheable cycles 623system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 172140750 # number of overall MSHR uncacheable cycles 624system.cpu.icache.overall_mshr_uncacheable_latency::total 172140750 # number of overall MSHR uncacheable cycles |
| 625system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for ReadReq accesses 626system.cpu.icache.ReadReq_mshr_miss_rate::total 0.066812 # mshr miss rate for ReadReq accesses 627system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for demand accesses 628system.cpu.icache.demand_mshr_miss_rate::total 0.066812 # mshr miss rate for demand accesses 629system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for overall accesses 630system.cpu.icache.overall_mshr_miss_rate::total 0.066812 # mshr miss rate for overall accesses 631system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11512.432125 # average ReadReq mshr miss latency 632system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11512.432125 # average ReadReq mshr miss latency --- 208 unchanged lines hidden (view full) --- 841system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1370000 # number of demand (read+write) MSHR miss cycles 842system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 843system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9056055223 # number of demand (read+write) MSHR miss cycles 844system.cpu.l2cache.demand_mshr_miss_latency::total 9057550223 # number of demand (read+write) MSHR miss cycles 845system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1370000 # number of overall MSHR miss cycles 846system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles 847system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9056055223 # number of overall MSHR miss cycles 848system.cpu.l2cache.overall_mshr_miss_latency::total 9057550223 # number of overall MSHR miss cycles | 625system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for ReadReq accesses 626system.cpu.icache.ReadReq_mshr_miss_rate::total 0.066812 # mshr miss rate for ReadReq accesses 627system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for demand accesses 628system.cpu.icache.demand_mshr_miss_rate::total 0.066812 # mshr miss rate for demand accesses 629system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for overall accesses 630system.cpu.icache.overall_mshr_miss_rate::total 0.066812 # mshr miss rate for overall accesses 631system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11512.432125 # average ReadReq mshr miss latency 632system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11512.432125 # average ReadReq mshr miss latency --- 208 unchanged lines hidden (view full) --- 841system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1370000 # number of demand (read+write) MSHR miss cycles 842system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 843system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9056055223 # number of demand (read+write) MSHR miss cycles 844system.cpu.l2cache.demand_mshr_miss_latency::total 9057550223 # number of demand (read+write) MSHR miss cycles 845system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1370000 # number of overall MSHR miss cycles 846system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles 847system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9056055223 # number of overall MSHR miss cycles 848system.cpu.l2cache.overall_mshr_miss_latency::total 9057550223 # number of overall MSHR miss cycles |
| 849system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 167362107750 # number of ReadReq MSHR uncacheable cycles 850system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167362107750 # number of ReadReq MSHR uncacheable cycles | 849system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 167362107250 # number of ReadReq MSHR uncacheable cycles 850system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167362107250 # number of ReadReq MSHR uncacheable cycles |
| 851system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 16707879855 # number of WriteReq MSHR uncacheable cycles 852system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16707879855 # number of WriteReq MSHR uncacheable cycles | 851system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 16707879855 # number of WriteReq MSHR uncacheable cycles 852system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16707879855 # number of WriteReq MSHR uncacheable cycles |
| 853system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 184069987605 # number of overall MSHR uncacheable cycles 854system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184069987605 # number of overall MSHR uncacheable cycles | 853system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 184069987105 # number of overall MSHR uncacheable cycles 854system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184069987105 # number of overall MSHR uncacheable cycles |
| 855system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000504 # mshr miss rate for ReadReq accesses 856system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000182 # mshr miss rate for ReadReq accesses 857system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012310 # mshr miss rate for ReadReq accesses 858system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011992 # mshr miss rate for ReadReq accesses 859system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.991588 # mshr miss rate for UpgradeReq accesses 860system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991588 # mshr miss rate for UpgradeReq accesses 861system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.538690 # mshr miss rate for ReadExReq accesses 862system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.538690 # mshr miss rate for ReadExReq accesses --- 143 unchanged lines hidden (view full) --- 1006system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10813361832 # number of WriteReq MSHR miss cycles 1007system.cpu.dcache.WriteReq_mshr_miss_latency::total 10813361832 # number of WriteReq MSHR miss cycles 1008system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 129211000 # number of LoadLockedReq MSHR miss cycles 1009system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 129211000 # number of LoadLockedReq MSHR miss cycles 1010system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15637320643 # number of demand (read+write) MSHR miss cycles 1011system.cpu.dcache.demand_mshr_miss_latency::total 15637320643 # number of demand (read+write) MSHR miss cycles 1012system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 15637320643 # number of overall MSHR miss cycles 1013system.cpu.dcache.overall_mshr_miss_latency::total 15637320643 # number of overall MSHR miss cycles | 855system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000504 # mshr miss rate for ReadReq accesses 856system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000182 # mshr miss rate for ReadReq accesses 857system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012310 # mshr miss rate for ReadReq accesses 858system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011992 # mshr miss rate for ReadReq accesses 859system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.991588 # mshr miss rate for UpgradeReq accesses 860system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991588 # mshr miss rate for UpgradeReq accesses 861system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.538690 # mshr miss rate for ReadExReq accesses 862system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.538690 # mshr miss rate for ReadExReq accesses --- 143 unchanged lines hidden (view full) --- 1006system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10813361832 # number of WriteReq MSHR miss cycles 1007system.cpu.dcache.WriteReq_mshr_miss_latency::total 10813361832 # number of WriteReq MSHR miss cycles 1008system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 129211000 # number of LoadLockedReq MSHR miss cycles 1009system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 129211000 # number of LoadLockedReq MSHR miss cycles 1010system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15637320643 # number of demand (read+write) MSHR miss cycles 1011system.cpu.dcache.demand_mshr_miss_latency::total 15637320643 # number of demand (read+write) MSHR miss cycles 1012system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 15637320643 # number of overall MSHR miss cycles 1013system.cpu.dcache.overall_mshr_miss_latency::total 15637320643 # number of overall MSHR miss cycles |
| 1014system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182632094250 # number of ReadReq MSHR uncacheable cycles 1015system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182632094250 # number of ReadReq MSHR uncacheable cycles | 1014system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182632094750 # number of ReadReq MSHR uncacheable cycles 1015system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182632094750 # number of ReadReq MSHR uncacheable cycles |
| 1016system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058171145 # number of WriteReq MSHR uncacheable cycles 1017system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058171145 # number of WriteReq MSHR uncacheable cycles | 1016system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058171145 # number of WriteReq MSHR uncacheable cycles 1017system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058171145 # number of WriteReq MSHR uncacheable cycles |
| 1018system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208690265395 # number of overall MSHR uncacheable cycles 1019system.cpu.dcache.overall_mshr_uncacheable_latency::total 208690265395 # number of overall MSHR uncacheable cycles | 1018system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208690265895 # number of overall MSHR uncacheable cycles 1019system.cpu.dcache.overall_mshr_uncacheable_latency::total 208690265895 # number of overall MSHR uncacheable cycles |
| 1020system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.031343 # mshr miss rate for ReadReq accesses 1021system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031343 # mshr miss rate for ReadReq accesses 1022system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.024498 # mshr miss rate for WriteReq accesses 1023system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024498 # mshr miss rate for WriteReq accesses 1024system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043608 # mshr miss rate for LoadLockedReq accesses 1025system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043608 # mshr miss rate for LoadLockedReq accesses 1026system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.028202 # mshr miss rate for demand accesses 1027system.cpu.dcache.demand_mshr_miss_rate::total 0.028202 # mshr miss rate for demand accesses --- 46 unchanged lines hidden --- | 1020system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.031343 # mshr miss rate for ReadReq accesses 1021system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031343 # mshr miss rate for ReadReq accesses 1022system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.024498 # mshr miss rate for WriteReq accesses 1023system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024498 # mshr miss rate for WriteReq accesses 1024system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043608 # mshr miss rate for LoadLockedReq accesses 1025system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043608 # mshr miss rate for LoadLockedReq accesses 1026system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.028202 # mshr miss rate for demand accesses 1027system.cpu.dcache.demand_mshr_miss_rate::total 0.028202 # mshr miss rate for demand accesses --- 46 unchanged lines hidden --- |