| stats.txt (10261:dc198e224a85) | stats.txt (10352:5f1f92bf76ee) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.567677 # Number of seconds simulated 4sim_ticks 2567677478000 # Number of ticks simulated 5final_tick 2567677478000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.566439 # Number of seconds simulated 4sim_ticks 2566439177500 # Number of ticks simulated 5final_tick 2566439177500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 53140 # Simulator instruction rate (inst/s) 8host_op_rate 68307 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2251849348 # Simulator tick rate (ticks/s) 10host_mem_usage 443244 # Number of bytes of host memory used 11host_seconds 1140.25 # Real time elapsed on the host 12sim_insts 60592948 # Number of instructions simulated 13sim_ops 77887482 # Number of ops (including micro ops) simulated | 7host_inst_rate 73545 # Simulator instruction rate (inst/s) 8host_op_rate 88536 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3115018228 # Simulator tick rate (ticks/s) 10host_mem_usage 470576 # Number of bytes of host memory used 11host_seconds 823.89 # Real time elapsed on the host 12sim_insts 60593470 # Number of instructions simulated 13sim_ops 72944147 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.dtb.walker 1152 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu.inst 10106264 # Number of bytes read from this memory 20system.physmem.bytes_read::total 131218072 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 1017856 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 1017856 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 3829760 # Number of bytes written to this memory | 19system.physmem.bytes_read::cpu.inst 10079960 # Number of bytes read from this memory 20system.physmem.bytes_read::total 131191960 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 1001344 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 1001344 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 3811328 # Number of bytes written to this memory |
| 24system.physmem.bytes_written::cpu.inst 3016072 # Number of bytes written to this memory | 24system.physmem.bytes_written::cpu.inst 3016072 # Number of bytes written to this memory |
| 25system.physmem.bytes_written::total 6845832 # Number of bytes written to this memory | 25system.physmem.bytes_written::total 6827400 # Number of bytes written to this memory |
| 26system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory | 26system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::cpu.dtb.walker 18 # Number of read requests responded to by this memory | 27system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory | 28system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory |
| 29system.physmem.num_reads::cpu.inst 157946 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15296782 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 59840 # Number of write requests responded to by this memory | 29system.physmem.num_reads::cpu.inst 157525 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15296364 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 59552 # Number of write requests responded to by this memory |
| 32system.physmem.num_writes::cpu.inst 754018 # Number of write requests responded to by this memory | 32system.physmem.num_writes::cpu.inst 754018 # Number of write requests responded to by this memory |
| 33system.physmem.num_writes::total 813858 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47167344 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 449 # Total read bandwidth from this memory (bytes/s) | 33system.physmem.num_writes::total 813570 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47190103 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 524 # Total read bandwidth from this memory (bytes/s) |
| 36system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) | 36system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) |
| 37system.physmem.bw_read::cpu.inst 3935955 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 51103798 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu.inst 396411 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::total 396411 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_write::writebacks 1491527 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_write::cpu.inst 1174630 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 2666157 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1491527 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::realview.clcd 47167344 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.dtb.walker 449 # Total bandwidth to/from this memory (bytes/s) | 37system.physmem.bw_read::cpu.inst 3927605 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 51118281 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu.inst 390169 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::total 390169 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_write::writebacks 1485065 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_write::cpu.inst 1175197 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 2660262 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1485065 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::realview.clcd 47190103 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.dtb.walker 524 # Total bandwidth to/from this memory (bytes/s) |
| 47system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) | 47system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) |
| 48system.physmem.bw_total::cpu.inst 5110586 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::total 53769956 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.readReqs 15296782 # Number of read requests accepted 51system.physmem.writeReqs 813858 # Number of write requests accepted 52system.physmem.readBursts 15296782 # Number of DRAM read bursts, including those serviced by the write queue 53system.physmem.writeBursts 813858 # Number of DRAM write bursts, including those merged in the write queue 54system.physmem.bytesReadDRAM 978883904 # Total number of bytes read from DRAM 55system.physmem.bytesReadWrQ 110144 # Total number of bytes read from write queue 56system.physmem.bytesWritten 6853696 # Total number of bytes written to DRAM 57system.physmem.bytesReadSys 131218072 # Total read bytes from the system interface side 58system.physmem.bytesWrittenSys 6845832 # Total written bytes from the system interface side 59system.physmem.servicedByWrQ 1721 # Number of DRAM read bursts serviced by the write queue 60system.physmem.mergedWrBursts 706743 # Number of DRAM write bursts merged with an existing one 61system.physmem.neitherReadNorWriteReqs 4671 # Number of requests that are neither read nor write 62system.physmem.perBankRdBursts::0 955926 # Per bank write bursts 63system.physmem.perBankRdBursts::1 955615 # Per bank write bursts 64system.physmem.perBankRdBursts::2 955732 # Per bank write bursts 65system.physmem.perBankRdBursts::3 955955 # Per bank write bursts 66system.physmem.perBankRdBursts::4 957630 # Per bank write bursts 67system.physmem.perBankRdBursts::5 955653 # Per bank write bursts 68system.physmem.perBankRdBursts::6 955569 # Per bank write bursts 69system.physmem.perBankRdBursts::7 955430 # Per bank write bursts 70system.physmem.perBankRdBursts::8 956341 # Per bank write bursts 71system.physmem.perBankRdBursts::9 955977 # Per bank write bursts 72system.physmem.perBankRdBursts::10 955547 # Per bank write bursts 73system.physmem.perBankRdBursts::11 955151 # Per bank write bursts 74system.physmem.perBankRdBursts::12 956306 # Per bank write bursts 75system.physmem.perBankRdBursts::13 956026 # Per bank write bursts 76system.physmem.perBankRdBursts::14 956165 # Per bank write bursts 77system.physmem.perBankRdBursts::15 956038 # Per bank write bursts 78system.physmem.perBankWrBursts::0 6624 # Per bank write bursts 79system.physmem.perBankWrBursts::1 6445 # Per bank write bursts 80system.physmem.perBankWrBursts::2 6544 # Per bank write bursts 81system.physmem.perBankWrBursts::3 6594 # Per bank write bursts 82system.physmem.perBankWrBursts::4 6491 # Per bank write bursts 83system.physmem.perBankWrBursts::5 6747 # Per bank write bursts 84system.physmem.perBankWrBursts::6 6783 # Per bank write bursts 85system.physmem.perBankWrBursts::7 6690 # Per bank write bursts 86system.physmem.perBankWrBursts::8 7075 # Per bank write bursts 87system.physmem.perBankWrBursts::9 6811 # Per bank write bursts 88system.physmem.perBankWrBursts::10 6482 # Per bank write bursts 89system.physmem.perBankWrBursts::11 6150 # Per bank write bursts 90system.physmem.perBankWrBursts::12 7106 # Per bank write bursts 91system.physmem.perBankWrBursts::13 6684 # Per bank write bursts 92system.physmem.perBankWrBursts::14 7011 # Per bank write bursts 93system.physmem.perBankWrBursts::15 6852 # Per bank write bursts | 48system.physmem.bw_total::cpu.inst 5102802 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::total 53778543 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.readReqs 15296364 # Number of read requests accepted 51system.physmem.writeReqs 813570 # Number of write requests accepted 52system.physmem.readBursts 15296364 # Number of DRAM read bursts, including those serviced by the write queue 53system.physmem.writeBursts 813570 # Number of DRAM write bursts, including those merged in the write queue 54system.physmem.bytesReadDRAM 978868736 # Total number of bytes read from DRAM 55system.physmem.bytesReadWrQ 98560 # Total number of bytes read from write queue 56system.physmem.bytesWritten 6836224 # Total number of bytes written to DRAM 57system.physmem.bytesReadSys 131191960 # Total read bytes from the system interface side 58system.physmem.bytesWrittenSys 6827400 # Total written bytes from the system interface side 59system.physmem.servicedByWrQ 1540 # Number of DRAM read bursts serviced by the write queue 60system.physmem.mergedWrBursts 706728 # Number of DRAM write bursts merged with an existing one 61system.physmem.neitherReadNorWriteReqs 4670 # Number of requests that are neither read nor write 62system.physmem.perBankRdBursts::0 955903 # Per bank write bursts 63system.physmem.perBankRdBursts::1 955584 # Per bank write bursts 64system.physmem.perBankRdBursts::2 955711 # Per bank write bursts 65system.physmem.perBankRdBursts::3 955912 # Per bank write bursts 66system.physmem.perBankRdBursts::4 957606 # Per bank write bursts 67system.physmem.perBankRdBursts::5 955733 # Per bank write bursts 68system.physmem.perBankRdBursts::6 955604 # Per bank write bursts 69system.physmem.perBankRdBursts::7 955438 # Per bank write bursts 70system.physmem.perBankRdBursts::8 956293 # Per bank write bursts 71system.physmem.perBankRdBursts::9 955954 # Per bank write bursts 72system.physmem.perBankRdBursts::10 955536 # Per bank write bursts 73system.physmem.perBankRdBursts::11 955097 # Per bank write bursts 74system.physmem.perBankRdBursts::12 956286 # Per bank write bursts 75system.physmem.perBankRdBursts::13 955995 # Per bank write bursts 76system.physmem.perBankRdBursts::14 956150 # Per bank write bursts 77system.physmem.perBankRdBursts::15 956022 # Per bank write bursts 78system.physmem.perBankWrBursts::0 6610 # Per bank write bursts 79system.physmem.perBankWrBursts::1 6419 # Per bank write bursts 80system.physmem.perBankWrBursts::2 6537 # Per bank write bursts 81system.physmem.perBankWrBursts::3 6577 # Per bank write bursts 82system.physmem.perBankWrBursts::4 6482 # Per bank write bursts 83system.physmem.perBankWrBursts::5 6744 # Per bank write bursts 84system.physmem.perBankWrBursts::6 6779 # Per bank write bursts 85system.physmem.perBankWrBursts::7 6682 # Per bank write bursts 86system.physmem.perBankWrBursts::8 7031 # Per bank write bursts 87system.physmem.perBankWrBursts::9 6794 # Per bank write bursts 88system.physmem.perBankWrBursts::10 6476 # Per bank write bursts 89system.physmem.perBankWrBursts::11 6093 # Per bank write bursts 90system.physmem.perBankWrBursts::12 7096 # Per bank write bursts 91system.physmem.perBankWrBursts::13 6664 # Per bank write bursts 92system.physmem.perBankWrBursts::14 6987 # Per bank write bursts 93system.physmem.perBankWrBursts::15 6845 # Per bank write bursts |
| 94system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 95system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 94system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 95system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 96system.physmem.totGap 2567675574500 # Total gap between requests | 96system.physmem.totGap 2566437420000 # Total gap between requests |
| 97system.physmem.readPktSize::0 0 # Read request sizes (log2) 98system.physmem.readPktSize::1 0 # Read request sizes (log2) | 97system.physmem.readPktSize::0 0 # Read request sizes (log2) 98system.physmem.readPktSize::1 0 # Read request sizes (log2) |
| 99system.physmem.readPktSize::2 38 # Read request sizes (log2) 100system.physmem.readPktSize::3 15138816 # Read request sizes (log2) | 99system.physmem.readPktSize::2 18 # Read request sizes (log2) 100system.physmem.readPktSize::3 15138826 # Read request sizes (log2) |
| 101system.physmem.readPktSize::4 0 # Read request sizes (log2) 102system.physmem.readPktSize::5 0 # Read request sizes (log2) | 101system.physmem.readPktSize::4 0 # Read request sizes (log2) 102system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 103system.physmem.readPktSize::6 157928 # Read request sizes (log2) | 103system.physmem.readPktSize::6 157520 # Read request sizes (log2) |
| 104system.physmem.writePktSize::0 0 # Write request sizes (log2) 105system.physmem.writePktSize::1 0 # Write request sizes (log2) 106system.physmem.writePktSize::2 754018 # Write request sizes (log2) 107system.physmem.writePktSize::3 0 # Write request sizes (log2) 108system.physmem.writePktSize::4 0 # Write request sizes (log2) 109system.physmem.writePktSize::5 0 # Write request sizes (log2) | 104system.physmem.writePktSize::0 0 # Write request sizes (log2) 105system.physmem.writePktSize::1 0 # Write request sizes (log2) 106system.physmem.writePktSize::2 754018 # Write request sizes (log2) 107system.physmem.writePktSize::3 0 # Write request sizes (log2) 108system.physmem.writePktSize::4 0 # Write request sizes (log2) 109system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 110system.physmem.writePktSize::6 59840 # Write request sizes (log2) 111system.physmem.rdQLenPdf::0 1112326 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::1 958648 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::2 963944 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::3 1085542 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::4 974308 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::5 1043218 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::6 2679684 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::7 2578598 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::8 3358182 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::9 142716 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::10 121801 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::11 111705 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::12 108393 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::13 19289 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::14 18414 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::15 18153 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::16 135 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see | 110system.physmem.writePktSize::6 59552 # Write request sizes (log2) 111system.physmem.rdQLenPdf::0 1111382 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::1 958419 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::2 963594 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::3 1074014 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::4 973771 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::5 1037292 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::6 2691805 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::7 2600171 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::8 3390697 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::9 128159 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::10 109522 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::11 101552 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::12 98177 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::13 19262 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::14 18514 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::15 18294 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::16 197 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see |
| 130system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see --- 12 unchanged lines hidden (view full) --- 150system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 130system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see --- 12 unchanged lines hidden (view full) --- 150system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 158system.physmem.wrQLenPdf::15 3806 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::16 3819 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::17 6193 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::18 6217 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::19 6223 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::20 6217 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::21 6218 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::22 6219 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::23 6219 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::24 6220 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::25 6221 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::26 6217 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::27 6225 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::28 6219 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::29 6217 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::30 6216 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::31 6218 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::32 6216 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see | 158system.physmem.wrQLenPdf::15 3800 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::16 3820 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::17 6181 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::18 6199 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::19 6202 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::20 6201 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::21 6201 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::22 6202 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::23 6203 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::24 6202 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::25 6203 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::26 6203 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::27 6206 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::28 6200 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::29 6204 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::30 6199 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::31 6201 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::32 6199 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see |
| 177system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 199system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 177system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 199system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 207system.physmem.bytesPerActivate::samples 1015088 # Bytes accessed per row activation 208system.physmem.bytesPerActivate::mean 971.085857 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::gmean 904.509360 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::stdev 205.145024 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::0-127 22501 2.22% 2.22% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::128-255 22772 2.24% 4.46% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::256-383 8563 0.84% 5.30% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::384-511 2455 0.24% 5.55% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::512-639 2778 0.27% 5.82% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::640-767 1897 0.19% 6.01% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::768-895 8457 0.83% 6.84% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::896-1023 971 0.10% 6.93% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::1024-1151 944694 93.07% 100.00% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::total 1015088 # Bytes accessed per row activation 221system.physmem.rdPerTurnAround::samples 6216 # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::mean 2460.593951 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::stdev 115853.550339 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::0-524287 6211 99.92% 99.92% # Reads before turning the bus around for writes | 207system.physmem.bytesPerActivate::samples 1014534 # Bytes accessed per row activation 208system.physmem.bytesPerActivate::mean 971.583959 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::gmean 905.812030 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::stdev 204.103928 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::0-127 21965 2.17% 2.17% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::128-255 22634 2.23% 4.40% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::256-383 8771 0.86% 5.26% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::384-511 2477 0.24% 5.50% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::512-639 2600 0.26% 5.76% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::640-767 1707 0.17% 5.93% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::768-895 8766 0.86% 6.79% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::896-1023 1031 0.10% 6.89% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::1024-1151 944583 93.11% 100.00% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::total 1014534 # Bytes accessed per row activation 221system.physmem.rdPerTurnAround::samples 6199 # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::mean 2467.302629 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::stdev 115861.516346 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::0-524287 6194 99.92% 99.92% # Reads before turning the bus around for writes |
| 225system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes | 225system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 228system.physmem.rdPerTurnAround::total 6216 # Reads before turning the bus around for writes 229system.physmem.wrPerTurnAround::samples 6216 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::mean 17.227960 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::gmean 17.199911 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::stdev 0.974162 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::16 2395 38.53% 38.53% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::17 16 0.26% 38.79% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::18 3798 61.10% 99.89% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::19 7 0.11% 100.00% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::total 6216 # Writes before turning the bus around for reads 238system.physmem.totQLat 396370290250 # Total ticks spent queuing 239system.physmem.totMemAccLat 683152684000 # Total ticks spent from burst creation until serviced by the DRAM 240system.physmem.totBusLat 76475305000 # Total ticks spent in databus transfers 241system.physmem.avgQLat 25914.92 # Average queueing delay per DRAM burst | 228system.physmem.rdPerTurnAround::total 6199 # Reads before turning the bus around for writes 229system.physmem.wrPerTurnAround::samples 6199 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::mean 17.231166 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::gmean 17.203067 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::stdev 0.975146 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::16 2381 38.41% 38.41% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::17 18 0.29% 38.70% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::18 3787 61.09% 99.79% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::19 12 0.19% 99.98% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::total 6199 # Writes before turning the bus around for reads 239system.physmem.totQLat 394563559000 # Total ticks spent queuing 240system.physmem.totMemAccLat 681341509000 # Total ticks spent from burst creation until serviced by the DRAM 241system.physmem.totBusLat 76474120000 # Total ticks spent in databus transfers 242system.physmem.avgQLat 25797.20 # Average queueing delay per DRAM burst |
| 242system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 243system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 243system.physmem.avgMemAccLat 44664.92 # Average memory access latency per DRAM burst 244system.physmem.avgRdBW 381.23 # Average DRAM read bandwidth in MiByte/s 245system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s 246system.physmem.avgRdBWSys 51.10 # Average system read bandwidth in MiByte/s 247system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s | 244system.physmem.avgMemAccLat 44547.20 # Average memory access latency per DRAM burst 245system.physmem.avgRdBW 381.41 # Average DRAM read bandwidth in MiByte/s 246system.physmem.avgWrBW 2.66 # Average achieved write bandwidth in MiByte/s 247system.physmem.avgRdBWSys 51.12 # Average system read bandwidth in MiByte/s 248system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s |
| 248system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 249system.physmem.busUtil 3.00 # Data bus utilization in percentage 250system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads 251system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes | 249system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 250system.physmem.busUtil 3.00 # Data bus utilization in percentage 251system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads 252system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes |
| 252system.physmem.avgRdQLen 6.49 # Average read queue length when enqueuing 253system.physmem.avgWrQLen 27.85 # Average write queue length when enqueuing 254system.physmem.readRowHits 14297424 # Number of row buffer hits during reads 255system.physmem.writeRowHits 89638 # Number of row buffer hits during writes | 253system.physmem.avgRdQLen 6.61 # Average read queue length when enqueuing 254system.physmem.avgWrQLen 26.40 # Average write queue length when enqueuing 255system.physmem.readRowHits 14297661 # Number of row buffer hits during reads 256system.physmem.writeRowHits 89445 # Number of row buffer hits during writes |
| 256system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads | 257system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads |
| 257system.physmem.writeRowHitRate 83.68 # Row buffer hit rate for writes 258system.physmem.avgGap 159377.63 # Average gap between requests | 258system.physmem.writeRowHitRate 83.72 # Row buffer hit rate for writes 259system.physmem.avgGap 159307.76 # Average gap between requests |
| 259system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined | 260system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined |
| 260system.physmem.memoryStateTime::IDLE 2210132306750 # Time in different power states 261system.physmem.memoryStateTime::REF 85740200000 # Time in different power states | 261system.physmem.memoryStateTime::IDLE 2209628504250 # Time in different power states 262system.physmem.memoryStateTime::REF 85698860000 # Time in different power states |
| 262system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 263system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 263system.physmem.memoryStateTime::ACT 271799415750 # Time in different power states | 264system.physmem.memoryStateTime::ACT 271106544500 # Time in different power states |
| 264system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 265system.realview.nvmem.bytes_read::cpu.inst 256 # Number of bytes read from this memory 266system.realview.nvmem.bytes_read::total 256 # Number of bytes read from this memory 267system.realview.nvmem.bytes_inst_read::cpu.inst 256 # Number of instructions bytes read from this memory 268system.realview.nvmem.bytes_inst_read::total 256 # Number of instructions bytes read from this memory 269system.realview.nvmem.num_reads::cpu.inst 4 # Number of read requests responded to by this memory 270system.realview.nvmem.num_reads::total 4 # Number of read requests responded to by this memory 271system.realview.nvmem.bw_read::cpu.inst 100 # Total read bandwidth from this memory (bytes/s) 272system.realview.nvmem.bw_read::total 100 # Total read bandwidth from this memory (bytes/s) 273system.realview.nvmem.bw_inst_read::cpu.inst 100 # Instruction read bandwidth from this memory (bytes/s) 274system.realview.nvmem.bw_inst_read::total 100 # Instruction read bandwidth from this memory (bytes/s) 275system.realview.nvmem.bw_total::cpu.inst 100 # Total bandwidth to/from this memory (bytes/s) 276system.realview.nvmem.bw_total::total 100 # Total bandwidth to/from this memory (bytes/s) | 265system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 266system.realview.nvmem.bytes_read::cpu.inst 256 # Number of bytes read from this memory 267system.realview.nvmem.bytes_read::total 256 # Number of bytes read from this memory 268system.realview.nvmem.bytes_inst_read::cpu.inst 256 # Number of instructions bytes read from this memory 269system.realview.nvmem.bytes_inst_read::total 256 # Number of instructions bytes read from this memory 270system.realview.nvmem.num_reads::cpu.inst 4 # Number of read requests responded to by this memory 271system.realview.nvmem.num_reads::total 4 # Number of read requests responded to by this memory 272system.realview.nvmem.bw_read::cpu.inst 100 # Total read bandwidth from this memory (bytes/s) 273system.realview.nvmem.bw_read::total 100 # Total read bandwidth from this memory (bytes/s) 274system.realview.nvmem.bw_inst_read::cpu.inst 100 # Instruction read bandwidth from this memory (bytes/s) 275system.realview.nvmem.bw_inst_read::total 100 # Instruction read bandwidth from this memory (bytes/s) 276system.realview.nvmem.bw_total::cpu.inst 100 # Total bandwidth to/from this memory (bytes/s) 277system.realview.nvmem.bw_total::total 100 # Total bandwidth to/from this memory (bytes/s) |
| 277system.membus.throughput 54704015 # Throughput (bytes/s) 278system.membus.trans_dist::ReadReq 16349240 # Transaction distribution 279system.membus.trans_dist::ReadResp 16349240 # Transaction distribution | 278system.membus.throughput 54713053 # Throughput (bytes/s) 279system.membus.trans_dist::ReadReq 16348871 # Transaction distribution 280system.membus.trans_dist::ReadResp 16348871 # Transaction distribution |
| 280system.membus.trans_dist::WriteReq 763365 # Transaction distribution 281system.membus.trans_dist::WriteResp 763365 # Transaction distribution | 281system.membus.trans_dist::WriteReq 763365 # Transaction distribution 282system.membus.trans_dist::WriteResp 763365 # Transaction distribution |
| 282system.membus.trans_dist::Writeback 59840 # Transaction distribution 283system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution 284system.membus.trans_dist::UpgradeResp 4671 # Transaction distribution 285system.membus.trans_dist::ReadExReq 131634 # Transaction distribution 286system.membus.trans_dist::ReadExResp 131634 # Transaction distribution | 283system.membus.trans_dist::Writeback 59552 # Transaction distribution 284system.membus.trans_dist::UpgradeReq 4670 # Transaction distribution 285system.membus.trans_dist::UpgradeResp 4670 # Transaction distribution 286system.membus.trans_dist::ReadExReq 131585 # Transaction distribution 287system.membus.trans_dist::ReadExResp 131585 # Transaction distribution |
| 287system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383068 # Packet count per connected master and slave (bytes) 288system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 8 # Packet count per connected master and slave (bytes) 289system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3800 # Packet count per connected master and slave (bytes) 290system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) | 288system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383068 # Packet count per connected master and slave (bytes) 289system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 8 # Packet count per connected master and slave (bytes) 290system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3800 # Packet count per connected master and slave (bytes) 291system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) |
| 291system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893150 # Packet count per connected master and slave (bytes) 292system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280028 # Packet count per connected master and slave (bytes) | 292system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1892024 # Packet count per connected master and slave (bytes) 293system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4278902 # Packet count per connected master and slave (bytes) |
| 293system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) 294system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) | 294system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) 295system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) |
| 295system.membus.pkt_count::total 34557660 # Packet count per connected master and slave (bytes) | 296system.membus.pkt_count::total 34556534 # Packet count per connected master and slave (bytes) |
| 296system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390502 # Cumulative packet size per connected master and slave (bytes) 297system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 256 # Cumulative packet size per connected master and slave (bytes) 298system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7600 # Cumulative packet size per connected master and slave (bytes) 299system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) | 297system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390502 # Cumulative packet size per connected master and slave (bytes) 298system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 256 # Cumulative packet size per connected master and slave (bytes) 299system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7600 # Cumulative packet size per connected master and slave (bytes) 300system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) |
| 300system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16953376 # Cumulative packet size per connected master and slave (bytes) 301system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19351738 # Cumulative packet size per connected master and slave (bytes) | 301system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16908832 # Cumulative packet size per connected master and slave (bytes) 302system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19307194 # Cumulative packet size per connected master and slave (bytes) |
| 302system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) 303system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) | 303system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) 304system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) |
| 304system.membus.tot_pkt_size::total 140462266 # Cumulative packet size per connected master and slave (bytes) 305system.membus.data_through_bus 140462266 # Total data (bytes) | 305system.membus.tot_pkt_size::total 140417722 # Cumulative packet size per connected master and slave (bytes) 306system.membus.data_through_bus 140417722 # Total data (bytes) |
| 306system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 307system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 307system.membus.reqLayer0.occupancy 1731218500 # Layer occupancy (ticks) | 308system.membus.reqLayer0.occupancy 1781248000 # Layer occupancy (ticks) |
| 308system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 309system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) 310system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 309system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 310system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) 311system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 311system.membus.reqLayer2.occupancy 3525000 # Layer occupancy (ticks) | 312system.membus.reqLayer2.occupancy 3519500 # Layer occupancy (ticks) |
| 312system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 313system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) 314system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 313system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 314system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) 315system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 315system.membus.reqLayer6.occupancy 17560732500 # Layer occupancy (ticks) | 316system.membus.reqLayer6.occupancy 17618628000 # Layer occupancy (ticks) |
| 316system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) | 317system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) |
| 317system.membus.respLayer1.occupancy 4805026968 # Layer occupancy (ticks) | 318system.membus.respLayer1.occupancy 4827706725 # Layer occupancy (ticks) |
| 318system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | 319system.membus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 319system.membus.respLayer2.occupancy 37408380500 # Layer occupancy (ticks) | 320system.membus.respLayer2.occupancy 37448813750 # Layer occupancy (ticks) |
| 320system.membus.respLayer2.utilization 1.5 # Layer utilization (%) 321system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 322system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 323system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 324system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 325system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 326system.cf0.dma_write_txs 0 # Number of DMA write transactions. | 321system.membus.respLayer2.utilization 1.5 # Layer utilization (%) 322system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 323system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 324system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 325system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 326system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 327system.cf0.dma_write_txs 0 # Number of DMA write transactions. |
| 327system.iobus.throughput 48098342 # Throughput (bytes/s) | 328system.iobus.throughput 48121550 # Throughput (bytes/s) |
| 328system.iobus.trans_dist::ReadReq 16322172 # Transaction distribution 329system.iobus.trans_dist::ReadResp 16322172 # Transaction distribution 330system.iobus.trans_dist::WriteReq 8178 # Transaction distribution 331system.iobus.trans_dist::WriteResp 8178 # Transaction distribution 332system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) 333system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) 334system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 524 # Packet count per connected master and slave (bytes) 335system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) --- 93 unchanged lines hidden (view full) --- 429system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 430system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 431system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 432system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 433system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) 434system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 435system.iobus.respLayer0.occupancy 2374890000 # Layer occupancy (ticks) 436system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) | 329system.iobus.trans_dist::ReadReq 16322172 # Transaction distribution 330system.iobus.trans_dist::ReadResp 16322172 # Transaction distribution 331system.iobus.trans_dist::WriteReq 8178 # Transaction distribution 332system.iobus.trans_dist::WriteResp 8178 # Transaction distribution 333system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) 334system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) 335system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 524 # Packet count per connected master and slave (bytes) 336system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) --- 93 unchanged lines hidden (view full) --- 430system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 431system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 432system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 433system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 434system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) 435system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 436system.iobus.respLayer0.occupancy 2374890000 # Layer occupancy (ticks) 437system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 437system.iobus.respLayer1.occupancy 38224979500 # Layer occupancy (ticks) | 438system.iobus.respLayer1.occupancy 38181688250 # Layer occupancy (ticks) |
| 438system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 439system.cpu_clk_domain.clock 500 # Clock period in ticks | 439system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 440system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 440system.cpu.branchPred.lookups 12907759 # Number of BP lookups 441system.cpu.branchPred.condPredicted 9898849 # Number of conditional branches predicted 442system.cpu.branchPred.condIncorrect 1085572 # Number of conditional branches incorrect 443system.cpu.branchPred.BTBLookups 8888360 # Number of BTB lookups 444system.cpu.branchPred.BTBHits 6291175 # Number of BTB hits | 441system.cpu.branchPred.lookups 12541574 # Number of BP lookups 442system.cpu.branchPred.condPredicted 9090690 # Number of conditional branches predicted 443system.cpu.branchPred.condIncorrect 1061681 # Number of conditional branches incorrect 444system.cpu.branchPred.BTBLookups 8536244 # Number of BTB lookups 445system.cpu.branchPred.BTBHits 6183587 # Number of BTB hits |
| 445system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 446system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 446system.cpu.branchPred.BTBHitPct 70.779930 # BTB Hit Percentage 447system.cpu.branchPred.usedRAS 1515479 # Number of times the RAS was used to get a target. 448system.cpu.branchPred.RASInCorrect 141893 # Number of incorrect RAS predictions. | 447system.cpu.branchPred.BTBHitPct 72.439202 # BTB Hit Percentage 448system.cpu.branchPred.usedRAS 1558068 # Number of times the RAS was used to get a target. 449system.cpu.branchPred.RASInCorrect 139509 # Number of incorrect RAS predictions. |
| 449system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 450system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 451system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 452system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 453system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 454system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 455system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 456system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 464system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 465system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 466system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 467system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 468system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 469system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 470system.cpu.dtb.inst_hits 0 # ITB inst hits 471system.cpu.dtb.inst_misses 0 # ITB inst misses | 450system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 451system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 452system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 453system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 454system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 455system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 456system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 457system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 465system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 466system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 467system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 468system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 469system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 470system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 471system.cpu.dtb.inst_hits 0 # ITB inst hits 472system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 472system.cpu.dtb.read_hits 15416418 # DTB read hits 473system.cpu.dtb.read_misses 42733 # DTB read misses 474system.cpu.dtb.write_hits 11344011 # DTB write hits 475system.cpu.dtb.write_misses 3796 # DTB write misses | 473system.cpu.dtb.read_hits 13629654 # DTB read hits 474system.cpu.dtb.read_misses 33608 # DTB read misses 475system.cpu.dtb.write_hits 11376786 # DTB write hits 476system.cpu.dtb.write_misses 3775 # DTB write misses |
| 476system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 477system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 478system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 479system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 477system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 478system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 479system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 480system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 480system.cpu.dtb.flush_entries 3452 # Number of entries that have been flushed from TLB 481system.cpu.dtb.align_faults 1264 # Number of TLB faults due to alignment restrictions 482system.cpu.dtb.prefetch_faults 262 # Number of TLB faults due to prefetch | 481system.cpu.dtb.flush_entries 3449 # Number of entries that have been flushed from TLB 482system.cpu.dtb.align_faults 1586 # Number of TLB faults due to alignment restrictions 483system.cpu.dtb.prefetch_faults 251 # Number of TLB faults due to prefetch |
| 483system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 484system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 484system.cpu.dtb.perms_faults 531 # Number of TLB faults due to permissions restrictions 485system.cpu.dtb.read_accesses 15459151 # DTB read accesses 486system.cpu.dtb.write_accesses 11347807 # DTB write accesses | 485system.cpu.dtb.perms_faults 593 # Number of TLB faults due to permissions restrictions 486system.cpu.dtb.read_accesses 13663262 # DTB read accesses 487system.cpu.dtb.write_accesses 11380561 # DTB write accesses |
| 487system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 488system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 488system.cpu.dtb.hits 26760429 # DTB hits 489system.cpu.dtb.misses 46529 # DTB misses 490system.cpu.dtb.accesses 26806958 # DTB accesses | 489system.cpu.dtb.hits 25006440 # DTB hits 490system.cpu.dtb.misses 37383 # DTB misses 491system.cpu.dtb.accesses 25043823 # DTB accesses |
| 491system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 492system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 493system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 494system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 495system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 496system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 497system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 498system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 504system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 505system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 506system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 507system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 508system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 509system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 510system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 511system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 492system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 493system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 494system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 495system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 496system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 497system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 498system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 499system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 505system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 506system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 507system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 508system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 509system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 510system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 511system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 512system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 512system.cpu.itb.inst_hits 23352687 # ITB inst hits 513system.cpu.itb.inst_misses 9286 # ITB inst misses | 513system.cpu.itb.inst_hits 22903214 # ITB inst hits 514system.cpu.itb.inst_misses 9061 # ITB inst misses |
| 514system.cpu.itb.read_hits 0 # DTB read hits 515system.cpu.itb.read_misses 0 # DTB read misses 516system.cpu.itb.write_hits 0 # DTB write hits 517system.cpu.itb.write_misses 0 # DTB write misses 518system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 519system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 520system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 521system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 515system.cpu.itb.read_hits 0 # DTB read hits 516system.cpu.itb.read_misses 0 # DTB read misses 517system.cpu.itb.write_hits 0 # DTB write hits 518system.cpu.itb.write_misses 0 # DTB write misses 519system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 520system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 521system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 522system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 522system.cpu.itb.flush_entries 2392 # Number of entries that have been flushed from TLB | 523system.cpu.itb.flush_entries 2388 # Number of entries that have been flushed from TLB |
| 523system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 524system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 525system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 524system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 525system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 526system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 526system.cpu.itb.perms_faults 4189 # Number of TLB faults due to permissions restrictions | 527system.cpu.itb.perms_faults 5760 # Number of TLB faults due to permissions restrictions |
| 527system.cpu.itb.read_accesses 0 # DTB read accesses 528system.cpu.itb.write_accesses 0 # DTB write accesses | 528system.cpu.itb.read_accesses 0 # DTB read accesses 529system.cpu.itb.write_accesses 0 # DTB write accesses |
| 529system.cpu.itb.inst_accesses 23361973 # ITB inst accesses 530system.cpu.itb.hits 23352687 # DTB hits 531system.cpu.itb.misses 9286 # DTB misses 532system.cpu.itb.accesses 23361973 # DTB accesses 533system.cpu.numCycles 576983411 # number of cpu cycles simulated | 530system.cpu.itb.inst_accesses 22912275 # ITB inst accesses 531system.cpu.itb.hits 22903214 # DTB hits 532system.cpu.itb.misses 9061 # DTB misses 533system.cpu.itb.accesses 22912275 # DTB accesses 534system.cpu.numCycles 572663270 # number of cpu cycles simulated |
| 534system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 535system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 535system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 536system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 536system.cpu.committedInsts 60592948 # Number of instructions committed 537system.cpu.committedOps 77887482 # Number of ops (including micro ops) committed 538system.cpu.discardedOps 3584241 # Number of ops (including micro ops) which were discarded before commit 539system.cpu.numFetchSuspends 77491 # Number of times Execute suspended instruction fetching 540system.cpu.quiesceCycles 4560301069 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 541system.cpu.cpi 9.522287 # CPI: cycles per instruction 542system.cpu.ipc 0.105017 # IPC: instructions per cycle | 537system.cpu.committedInsts 60593470 # Number of instructions committed 538system.cpu.committedOps 72944147 # Number of ops (including micro ops) committed 539system.cpu.discardedOps 3225433 # Number of ops (including micro ops) which were discarded before commit 540system.cpu.numFetchSuspends 77492 # Number of times Execute suspended instruction fetching 541system.cpu.quiesceCycles 4562060973 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 542system.cpu.cpi 9.450907 # CPI: cycles per instruction 543system.cpu.ipc 0.105810 # IPC: instructions per cycle |
| 543system.cpu.kern.inst.arm 0 # number of arm instructions executed | 544system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 544system.cpu.kern.inst.quiesce 82977 # number of quiesce instructions executed 545system.cpu.tickCycles 470832364 # Number of cycles that the object actually ticked 546system.cpu.idleCycles 106151047 # Total number of cycles that the object has spent stopped 547system.cpu.icache.tags.replacements 1545254 # number of replacements 548system.cpu.icache.tags.tagsinuse 511.467506 # Cycle average of tags in use 549system.cpu.icache.tags.total_refs 21802506 # Total number of references to valid blocks. 550system.cpu.icache.tags.sampled_refs 1545766 # Sample count of references to valid blocks. 551system.cpu.icache.tags.avg_refs 14.104661 # Average number of references to valid blocks. 552system.cpu.icache.tags.warmup_cycle 10068892000 # Cycle when the warmup percentage was hit. 553system.cpu.icache.tags.occ_blocks::cpu.inst 511.467506 # Average occupied blocks per requestor 554system.cpu.icache.tags.occ_percent::cpu.inst 0.998960 # Average percentage of cache occupancy 555system.cpu.icache.tags.occ_percent::total 0.998960 # Average percentage of cache occupancy | 545system.cpu.kern.inst.quiesce 82978 # number of quiesce instructions executed 546system.cpu.tickCycles 466702382 # Number of cycles that the object actually ticked 547system.cpu.idleCycles 105960888 # Total number of cycles that the object has spent stopped 548system.cpu.icache.tags.replacements 1529303 # number of replacements 549system.cpu.icache.tags.tagsinuse 511.463660 # Cycle average of tags in use 550system.cpu.icache.tags.total_refs 21367406 # Total number of references to valid blocks. 551system.cpu.icache.tags.sampled_refs 1529815 # Sample count of references to valid blocks. 552system.cpu.icache.tags.avg_refs 13.967314 # Average number of references to valid blocks. 553system.cpu.icache.tags.warmup_cycle 9992606000 # Cycle when the warmup percentage was hit. 554system.cpu.icache.tags.occ_blocks::cpu.inst 511.463660 # Average occupied blocks per requestor 555system.cpu.icache.tags.occ_percent::cpu.inst 0.998952 # Average percentage of cache occupancy 556system.cpu.icache.tags.occ_percent::total 0.998952 # Average percentage of cache occupancy |
| 556system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 557system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 557system.cpu.icache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id 558system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id 559system.cpu.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id | 558system.cpu.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 559system.cpu.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id 560system.cpu.icache.tags.age_task_id_blocks_1024::2 190 # Occupied blocks per task id |
| 560system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 561system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 561system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 562system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 562system.cpu.icache.tags.tag_accesses 24894039 # Number of tag accesses 563system.cpu.icache.tags.data_accesses 24894039 # Number of data accesses 564system.cpu.icache.ReadReq_hits::cpu.inst 21802506 # number of ReadReq hits 565system.cpu.icache.ReadReq_hits::total 21802506 # number of ReadReq hits 566system.cpu.icache.demand_hits::cpu.inst 21802506 # number of demand (read+write) hits 567system.cpu.icache.demand_hits::total 21802506 # number of demand (read+write) hits 568system.cpu.icache.overall_hits::cpu.inst 21802506 # number of overall hits 569system.cpu.icache.overall_hits::total 21802506 # number of overall hits 570system.cpu.icache.ReadReq_misses::cpu.inst 1545767 # number of ReadReq misses 571system.cpu.icache.ReadReq_misses::total 1545767 # number of ReadReq misses 572system.cpu.icache.demand_misses::cpu.inst 1545767 # number of demand (read+write) misses 573system.cpu.icache.demand_misses::total 1545767 # number of demand (read+write) misses 574system.cpu.icache.overall_misses::cpu.inst 1545767 # number of overall misses 575system.cpu.icache.overall_misses::total 1545767 # number of overall misses 576system.cpu.icache.ReadReq_miss_latency::cpu.inst 20898816329 # number of ReadReq miss cycles 577system.cpu.icache.ReadReq_miss_latency::total 20898816329 # number of ReadReq miss cycles 578system.cpu.icache.demand_miss_latency::cpu.inst 20898816329 # number of demand (read+write) miss cycles 579system.cpu.icache.demand_miss_latency::total 20898816329 # number of demand (read+write) miss cycles 580system.cpu.icache.overall_miss_latency::cpu.inst 20898816329 # number of overall miss cycles 581system.cpu.icache.overall_miss_latency::total 20898816329 # number of overall miss cycles 582system.cpu.icache.ReadReq_accesses::cpu.inst 23348273 # number of ReadReq accesses(hits+misses) 583system.cpu.icache.ReadReq_accesses::total 23348273 # number of ReadReq accesses(hits+misses) 584system.cpu.icache.demand_accesses::cpu.inst 23348273 # number of demand (read+write) accesses 585system.cpu.icache.demand_accesses::total 23348273 # number of demand (read+write) accesses 586system.cpu.icache.overall_accesses::cpu.inst 23348273 # number of overall (read+write) accesses 587system.cpu.icache.overall_accesses::total 23348273 # number of overall (read+write) accesses 588system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.066205 # miss rate for ReadReq accesses 589system.cpu.icache.ReadReq_miss_rate::total 0.066205 # miss rate for ReadReq accesses 590system.cpu.icache.demand_miss_rate::cpu.inst 0.066205 # miss rate for demand accesses 591system.cpu.icache.demand_miss_rate::total 0.066205 # miss rate for demand accesses 592system.cpu.icache.overall_miss_rate::cpu.inst 0.066205 # miss rate for overall accesses 593system.cpu.icache.overall_miss_rate::total 0.066205 # miss rate for overall accesses 594system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13520.030075 # average ReadReq miss latency 595system.cpu.icache.ReadReq_avg_miss_latency::total 13520.030075 # average ReadReq miss latency 596system.cpu.icache.demand_avg_miss_latency::cpu.inst 13520.030075 # average overall miss latency 597system.cpu.icache.demand_avg_miss_latency::total 13520.030075 # average overall miss latency 598system.cpu.icache.overall_avg_miss_latency::cpu.inst 13520.030075 # average overall miss latency 599system.cpu.icache.overall_avg_miss_latency::total 13520.030075 # average overall miss latency | 563system.cpu.icache.tags.tag_accesses 24427037 # Number of tag accesses 564system.cpu.icache.tags.data_accesses 24427037 # Number of data accesses 565system.cpu.icache.ReadReq_hits::cpu.inst 21367406 # number of ReadReq hits 566system.cpu.icache.ReadReq_hits::total 21367406 # number of ReadReq hits 567system.cpu.icache.demand_hits::cpu.inst 21367406 # number of demand (read+write) hits 568system.cpu.icache.demand_hits::total 21367406 # number of demand (read+write) hits 569system.cpu.icache.overall_hits::cpu.inst 21367406 # number of overall hits 570system.cpu.icache.overall_hits::total 21367406 # number of overall hits 571system.cpu.icache.ReadReq_misses::cpu.inst 1529816 # number of ReadReq misses 572system.cpu.icache.ReadReq_misses::total 1529816 # number of ReadReq misses 573system.cpu.icache.demand_misses::cpu.inst 1529816 # number of demand (read+write) misses 574system.cpu.icache.demand_misses::total 1529816 # number of demand (read+write) misses 575system.cpu.icache.overall_misses::cpu.inst 1529816 # number of overall misses 576system.cpu.icache.overall_misses::total 1529816 # number of overall misses 577system.cpu.icache.ReadReq_miss_latency::cpu.inst 20677210137 # number of ReadReq miss cycles 578system.cpu.icache.ReadReq_miss_latency::total 20677210137 # number of ReadReq miss cycles 579system.cpu.icache.demand_miss_latency::cpu.inst 20677210137 # number of demand (read+write) miss cycles 580system.cpu.icache.demand_miss_latency::total 20677210137 # number of demand (read+write) miss cycles 581system.cpu.icache.overall_miss_latency::cpu.inst 20677210137 # number of overall miss cycles 582system.cpu.icache.overall_miss_latency::total 20677210137 # number of overall miss cycles 583system.cpu.icache.ReadReq_accesses::cpu.inst 22897222 # number of ReadReq accesses(hits+misses) 584system.cpu.icache.ReadReq_accesses::total 22897222 # number of ReadReq accesses(hits+misses) 585system.cpu.icache.demand_accesses::cpu.inst 22897222 # number of demand (read+write) accesses 586system.cpu.icache.demand_accesses::total 22897222 # number of demand (read+write) accesses 587system.cpu.icache.overall_accesses::cpu.inst 22897222 # number of overall (read+write) accesses 588system.cpu.icache.overall_accesses::total 22897222 # number of overall (read+write) accesses 589system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.066812 # miss rate for ReadReq accesses 590system.cpu.icache.ReadReq_miss_rate::total 0.066812 # miss rate for ReadReq accesses 591system.cpu.icache.demand_miss_rate::cpu.inst 0.066812 # miss rate for demand accesses 592system.cpu.icache.demand_miss_rate::total 0.066812 # miss rate for demand accesses 593system.cpu.icache.overall_miss_rate::cpu.inst 0.066812 # miss rate for overall accesses 594system.cpu.icache.overall_miss_rate::total 0.066812 # miss rate for overall accesses 595system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13516.141900 # average ReadReq miss latency 596system.cpu.icache.ReadReq_avg_miss_latency::total 13516.141900 # average ReadReq miss latency 597system.cpu.icache.demand_avg_miss_latency::cpu.inst 13516.141900 # average overall miss latency 598system.cpu.icache.demand_avg_miss_latency::total 13516.141900 # average overall miss latency 599system.cpu.icache.overall_avg_miss_latency::cpu.inst 13516.141900 # average overall miss latency 600system.cpu.icache.overall_avg_miss_latency::total 13516.141900 # average overall miss latency |
| 600system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 601system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 602system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 603system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 604system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 605system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 606system.cpu.icache.fast_writes 0 # number of fast writes performed 607system.cpu.icache.cache_copies 0 # number of cache copies performed | 601system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 602system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 603system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 604system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 605system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 606system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 607system.cpu.icache.fast_writes 0 # number of fast writes performed 608system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 608system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1545767 # number of ReadReq MSHR misses 609system.cpu.icache.ReadReq_mshr_misses::total 1545767 # number of ReadReq MSHR misses 610system.cpu.icache.demand_mshr_misses::cpu.inst 1545767 # number of demand (read+write) MSHR misses 611system.cpu.icache.demand_mshr_misses::total 1545767 # number of demand (read+write) MSHR misses 612system.cpu.icache.overall_mshr_misses::cpu.inst 1545767 # number of overall MSHR misses 613system.cpu.icache.overall_mshr_misses::total 1545767 # number of overall MSHR misses 614system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17801487671 # number of ReadReq MSHR miss cycles 615system.cpu.icache.ReadReq_mshr_miss_latency::total 17801487671 # number of ReadReq MSHR miss cycles 616system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17801487671 # number of demand (read+write) MSHR miss cycles 617system.cpu.icache.demand_mshr_miss_latency::total 17801487671 # number of demand (read+write) MSHR miss cycles 618system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17801487671 # number of overall MSHR miss cycles 619system.cpu.icache.overall_mshr_miss_latency::total 17801487671 # number of overall MSHR miss cycles 620system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 172412750 # number of ReadReq MSHR uncacheable cycles 621system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 172412750 # number of ReadReq MSHR uncacheable cycles 622system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 172412750 # number of overall MSHR uncacheable cycles 623system.cpu.icache.overall_mshr_uncacheable_latency::total 172412750 # number of overall MSHR uncacheable cycles 624system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066205 # mshr miss rate for ReadReq accesses 625system.cpu.icache.ReadReq_mshr_miss_rate::total 0.066205 # mshr miss rate for ReadReq accesses 626system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066205 # mshr miss rate for demand accesses 627system.cpu.icache.demand_mshr_miss_rate::total 0.066205 # mshr miss rate for demand accesses 628system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066205 # mshr miss rate for overall accesses 629system.cpu.icache.overall_mshr_miss_rate::total 0.066205 # mshr miss rate for overall accesses 630system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11516.281348 # average ReadReq mshr miss latency 631system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11516.281348 # average ReadReq mshr miss latency 632system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11516.281348 # average overall mshr miss latency 633system.cpu.icache.demand_avg_mshr_miss_latency::total 11516.281348 # average overall mshr miss latency 634system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11516.281348 # average overall mshr miss latency 635system.cpu.icache.overall_avg_mshr_miss_latency::total 11516.281348 # average overall mshr miss latency | 609system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1529816 # number of ReadReq MSHR misses 610system.cpu.icache.ReadReq_mshr_misses::total 1529816 # number of ReadReq MSHR misses 611system.cpu.icache.demand_mshr_misses::cpu.inst 1529816 # number of demand (read+write) MSHR misses 612system.cpu.icache.demand_mshr_misses::total 1529816 # number of demand (read+write) MSHR misses 613system.cpu.icache.overall_mshr_misses::cpu.inst 1529816 # number of overall MSHR misses 614system.cpu.icache.overall_mshr_misses::total 1529816 # number of overall MSHR misses 615system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17611902863 # number of ReadReq MSHR miss cycles 616system.cpu.icache.ReadReq_mshr_miss_latency::total 17611902863 # number of ReadReq MSHR miss cycles 617system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17611902863 # number of demand (read+write) MSHR miss cycles 618system.cpu.icache.demand_mshr_miss_latency::total 17611902863 # number of demand (read+write) MSHR miss cycles 619system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17611902863 # number of overall MSHR miss cycles 620system.cpu.icache.overall_mshr_miss_latency::total 17611902863 # number of overall MSHR miss cycles 621system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 172141250 # number of ReadReq MSHR uncacheable cycles 622system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 172141250 # number of ReadReq MSHR uncacheable cycles 623system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 172141250 # number of overall MSHR uncacheable cycles 624system.cpu.icache.overall_mshr_uncacheable_latency::total 172141250 # number of overall MSHR uncacheable cycles 625system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for ReadReq accesses 626system.cpu.icache.ReadReq_mshr_miss_rate::total 0.066812 # mshr miss rate for ReadReq accesses 627system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for demand accesses 628system.cpu.icache.demand_mshr_miss_rate::total 0.066812 # mshr miss rate for demand accesses 629system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for overall accesses 630system.cpu.icache.overall_mshr_miss_rate::total 0.066812 # mshr miss rate for overall accesses 631system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11512.432125 # average ReadReq mshr miss latency 632system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11512.432125 # average ReadReq mshr miss latency 633system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11512.432125 # average overall mshr miss latency 634system.cpu.icache.demand_avg_mshr_miss_latency::total 11512.432125 # average overall mshr miss latency 635system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11512.432125 # average overall mshr miss latency 636system.cpu.icache.overall_avg_mshr_miss_latency::total 11512.432125 # average overall mshr miss latency |
| 636system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 637system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 638system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 639system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 640system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 637system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 638system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 639system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 640system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 641system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 641system.cpu.toL2Bus.throughput 71776562 # Throughput (bytes/s) 642system.cpu.toL2Bus.trans_dist::ReadReq 3214470 # Transaction distribution 643system.cpu.toL2Bus.trans_dist::ReadResp 3214469 # Transaction distribution | 642system.cpu.toL2Bus.throughput 71285625 # Throughput (bytes/s) 643system.cpu.toL2Bus.trans_dist::ReadReq 3182019 # Transaction distribution 644system.cpu.toL2Bus.trans_dist::ReadResp 3182018 # Transaction distribution |
| 644system.cpu.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution 645system.cpu.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution | 645system.cpu.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution 646system.cpu.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution |
| 646system.cpu.toL2Bus.trans_dist::Writeback 602969 # Transaction distribution 647system.cpu.toL2Bus.trans_dist::UpgradeReq 2961 # Transaction distribution 648system.cpu.toL2Bus.trans_dist::UpgradeResp 2961 # Transaction distribution 649system.cpu.toL2Bus.trans_dist::ReadExReq 247546 # Transaction distribution 650system.cpu.toL2Bus.trans_dist::ReadExResp 247546 # Transaction distribution 651system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3094256 # Packet count per connected master and slave (bytes) 652system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5780457 # Packet count per connected master and slave (bytes) 653system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 29847 # Packet count per connected master and slave (bytes) 654system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126652 # Packet count per connected master and slave (bytes) 655system.cpu.toL2Bus.pkt_count::total 9031212 # Packet count per connected master and slave (bytes) 656system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 98954304 # Cumulative packet size per connected master and slave (bytes) 657system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84855034 # Cumulative packet size per connected master and slave (bytes) 658system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 45620 # Cumulative packet size per connected master and slave (bytes) 659system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214364 # Cumulative packet size per connected master and slave (bytes) 660system.cpu.toL2Bus.tot_pkt_size::total 184069322 # Cumulative packet size per connected master and slave (bytes) 661system.cpu.toL2Bus.data_through_bus 184069322 # Total data (bytes) 662system.cpu.toL2Bus.snoop_data_through_bus 229740 # Total snoop data (bytes) 663system.cpu.toL2Bus.reqLayer0.occupancy 3400466435 # Layer occupancy (ticks) | 647system.cpu.toL2Bus.trans_dist::Writeback 600964 # Transaction distribution 648system.cpu.toL2Bus.trans_dist::UpgradeReq 2972 # Transaction distribution 649system.cpu.toL2Bus.trans_dist::UpgradeResp 2972 # Transaction distribution 650system.cpu.toL2Bus.trans_dist::ReadExReq 247467 # Transaction distribution 651system.cpu.toL2Bus.trans_dist::ReadExResp 247467 # Transaction distribution 652system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3062398 # Packet count per connected master and slave (bytes) 653system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5774016 # Packet count per connected master and slave (bytes) 654system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 28971 # Packet count per connected master and slave (bytes) 655system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 100817 # Packet count per connected master and slave (bytes) 656system.cpu.toL2Bus.pkt_count::total 8966202 # Packet count per connected master and slave (bytes) 657system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 97936512 # Cumulative packet size per connected master and slave (bytes) 658system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84584698 # Cumulative packet size per connected master and slave (bytes) 659system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43908 # Cumulative packet size per connected master and slave (bytes) 660system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 166616 # Cumulative packet size per connected master and slave (bytes) 661system.cpu.toL2Bus.tot_pkt_size::total 182731734 # Cumulative packet size per connected master and slave (bytes) 662system.cpu.toL2Bus.data_through_bus 182731734 # Total data (bytes) 663system.cpu.toL2Bus.snoop_data_through_bus 218488 # Total snoop data (bytes) 664system.cpu.toL2Bus.reqLayer0.occupancy 3381194945 # Layer occupancy (ticks) |
| 664system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 665system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 665system.cpu.toL2Bus.respLayer0.occupancy 2325579079 # Layer occupancy (ticks) | 666system.cpu.toL2Bus.respLayer0.occupancy 2301585887 # Layer occupancy (ticks) |
| 666system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 667system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 667system.cpu.toL2Bus.respLayer1.occupancy 2551211790 # Layer occupancy (ticks) | 668system.cpu.toL2Bus.respLayer1.occupancy 2547997212 # Layer occupancy (ticks) |
| 668system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 669system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 669system.cpu.toL2Bus.respLayer2.occupancy 18447489 # Layer occupancy (ticks) | 670system.cpu.toL2Bus.respLayer2.occupancy 18000487 # Layer occupancy (ticks) |
| 670system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 671system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 671system.cpu.toL2Bus.respLayer3.occupancy 73062749 # Layer occupancy (ticks) | 672system.cpu.toL2Bus.respLayer3.occupancy 59164999 # Layer occupancy (ticks) |
| 672system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 673system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 673system.cpu.l2cache.tags.replacements 65493 # number of replacements 674system.cpu.l2cache.tags.tagsinuse 51631.050557 # Cycle average of tags in use 675system.cpu.l2cache.tags.total_refs 2439202 # Total number of references to valid blocks. 676system.cpu.l2cache.tags.sampled_refs 130882 # Sample count of references to valid blocks. 677system.cpu.l2cache.tags.avg_refs 18.636650 # Average number of references to valid blocks. 678system.cpu.l2cache.tags.warmup_cycle 2525290748000 # Cycle when the warmup percentage was hit. 679system.cpu.l2cache.tags.occ_blocks::writebacks 36364.368368 # Average occupied blocks per requestor 680system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.573566 # Average occupied blocks per requestor | 674system.cpu.l2cache.tags.replacements 65085 # number of replacements 675system.cpu.l2cache.tags.tagsinuse 51558.734735 # Cycle average of tags in use 676system.cpu.l2cache.tags.total_refs 2407104 # Total number of references to valid blocks. 677system.cpu.l2cache.tags.sampled_refs 130473 # Sample count of references to valid blocks. 678system.cpu.l2cache.tags.avg_refs 18.449058 # Average number of references to valid blocks. 679system.cpu.l2cache.tags.warmup_cycle 2524856942500 # Cycle when the warmup percentage was hit. 680system.cpu.l2cache.tags.occ_blocks::writebacks 36497.819876 # Average occupied blocks per requestor 681system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.059887 # Average occupied blocks per requestor |
| 681system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000576 # Average occupied blocks per requestor | 682system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000576 # Average occupied blocks per requestor |
| 682system.cpu.l2cache.tags.occ_blocks::cpu.inst 15253.108047 # Average occupied blocks per requestor 683system.cpu.l2cache.tags.occ_percent::writebacks 0.554876 # Average percentage of cache occupancy 684system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000207 # Average percentage of cache occupancy | 683system.cpu.l2cache.tags.occ_blocks::cpu.inst 15046.854396 # Average occupied blocks per requestor 684system.cpu.l2cache.tags.occ_percent::writebacks 0.556913 # Average percentage of cache occupancy 685system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000215 # Average percentage of cache occupancy |
| 685system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy | 686system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy |
| 686system.cpu.l2cache.tags.occ_percent::cpu.inst 0.232744 # Average percentage of cache occupancy 687system.cpu.l2cache.tags.occ_percent::total 0.787827 # Average percentage of cache occupancy 688system.cpu.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id 689system.cpu.l2cache.tags.occ_task_id_blocks::1024 65379 # Occupied blocks per task id 690system.cpu.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id 691system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 692system.cpu.l2cache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id 693system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2430 # Occupied blocks per task id 694system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6701 # Occupied blocks per task id 695system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56138 # Occupied blocks per task id 696system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000153 # Percentage of cache occupancy per task id 697system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997604 # Percentage of cache occupancy per task id 698system.cpu.l2cache.tags.tag_accesses 23227461 # Number of tag accesses 699system.cpu.l2cache.tags.data_accesses 23227461 # Number of data accesses 700system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53573 # number of ReadReq hits 701system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11403 # number of ReadReq hits 702system.cpu.l2cache.ReadReq_hits::cpu.inst 1910560 # number of ReadReq hits 703system.cpu.l2cache.ReadReq_hits::total 1975536 # number of ReadReq hits 704system.cpu.l2cache.Writeback_hits::writebacks 602969 # number of Writeback hits 705system.cpu.l2cache.Writeback_hits::total 602969 # number of Writeback hits | 687system.cpu.l2cache.tags.occ_percent::cpu.inst 0.229597 # Average percentage of cache occupancy 688system.cpu.l2cache.tags.occ_percent::total 0.786724 # Average percentage of cache occupancy 689system.cpu.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id 690system.cpu.l2cache.tags.occ_task_id_blocks::1024 65374 # Occupied blocks per task id 691system.cpu.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id 692system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id 693system.cpu.l2cache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id 694system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2560 # Occupied blocks per task id 695system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6585 # Occupied blocks per task id 696system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56117 # Occupied blocks per task id 697system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id 698system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997528 # Percentage of cache occupancy per task id 699system.cpu.l2cache.tags.tag_accesses 22967155 # Number of tag accesses 700system.cpu.l2cache.tags.data_accesses 22967155 # Number of data accesses 701system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 41633 # number of ReadReq hits 702system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10975 # number of ReadReq hits 703system.cpu.l2cache.ReadReq_hits::cpu.inst 1892880 # number of ReadReq hits 704system.cpu.l2cache.ReadReq_hits::total 1945488 # number of ReadReq hits 705system.cpu.l2cache.Writeback_hits::writebacks 600964 # number of Writeback hits 706system.cpu.l2cache.Writeback_hits::total 600964 # number of Writeback hits |
| 706system.cpu.l2cache.UpgradeReq_hits::cpu.inst 25 # number of UpgradeReq hits 707system.cpu.l2cache.UpgradeReq_hits::total 25 # number of UpgradeReq hits | 707system.cpu.l2cache.UpgradeReq_hits::cpu.inst 25 # number of UpgradeReq hits 708system.cpu.l2cache.UpgradeReq_hits::total 25 # number of UpgradeReq hits |
| 708system.cpu.l2cache.ReadExReq_hits::cpu.inst 114177 # number of ReadExReq hits 709system.cpu.l2cache.ReadExReq_hits::total 114177 # number of ReadExReq hits 710system.cpu.l2cache.demand_hits::cpu.dtb.walker 53573 # number of demand (read+write) hits 711system.cpu.l2cache.demand_hits::cpu.itb.walker 11403 # number of demand (read+write) hits 712system.cpu.l2cache.demand_hits::cpu.inst 2024737 # number of demand (read+write) hits 713system.cpu.l2cache.demand_hits::total 2089713 # number of demand (read+write) hits 714system.cpu.l2cache.overall_hits::cpu.dtb.walker 53573 # number of overall hits 715system.cpu.l2cache.overall_hits::cpu.itb.walker 11403 # number of overall hits 716system.cpu.l2cache.overall_hits::cpu.inst 2024737 # number of overall hits 717system.cpu.l2cache.overall_hits::total 2089713 # number of overall hits 718system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 18 # number of ReadReq misses | 709system.cpu.l2cache.ReadExReq_hits::cpu.inst 114159 # number of ReadExReq hits 710system.cpu.l2cache.ReadExReq_hits::total 114159 # number of ReadExReq hits 711system.cpu.l2cache.demand_hits::cpu.dtb.walker 41633 # number of demand (read+write) hits 712system.cpu.l2cache.demand_hits::cpu.itb.walker 10975 # number of demand (read+write) hits 713system.cpu.l2cache.demand_hits::cpu.inst 2007039 # number of demand (read+write) hits 714system.cpu.l2cache.demand_hits::total 2059647 # number of demand (read+write) hits 715system.cpu.l2cache.overall_hits::cpu.dtb.walker 41633 # number of overall hits 716system.cpu.l2cache.overall_hits::cpu.itb.walker 10975 # number of overall hits 717system.cpu.l2cache.overall_hits::cpu.inst 2007039 # number of overall hits 718system.cpu.l2cache.overall_hits::total 2059647 # number of overall hits 719system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses |
| 719system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses | 720system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses |
| 720system.cpu.l2cache.ReadReq_misses::cpu.inst 24020 # number of ReadReq misses 721system.cpu.l2cache.ReadReq_misses::total 24040 # number of ReadReq misses 722system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2936 # number of UpgradeReq misses 723system.cpu.l2cache.UpgradeReq_misses::total 2936 # number of UpgradeReq misses 724system.cpu.l2cache.ReadExReq_misses::cpu.inst 133369 # number of ReadExReq misses 725system.cpu.l2cache.ReadExReq_misses::total 133369 # number of ReadExReq misses 726system.cpu.l2cache.demand_misses::cpu.dtb.walker 18 # number of demand (read+write) misses | 721system.cpu.l2cache.ReadReq_misses::cpu.inst 23661 # number of ReadReq misses 722system.cpu.l2cache.ReadReq_misses::total 23684 # number of ReadReq misses 723system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2947 # number of UpgradeReq misses 724system.cpu.l2cache.UpgradeReq_misses::total 2947 # number of UpgradeReq misses 725system.cpu.l2cache.ReadExReq_misses::cpu.inst 133308 # number of ReadExReq misses 726system.cpu.l2cache.ReadExReq_misses::total 133308 # number of ReadExReq misses 727system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses |
| 727system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses | 728system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses |
| 728system.cpu.l2cache.demand_misses::cpu.inst 157389 # number of demand (read+write) misses 729system.cpu.l2cache.demand_misses::total 157409 # number of demand (read+write) misses 730system.cpu.l2cache.overall_misses::cpu.dtb.walker 18 # number of overall misses | 729system.cpu.l2cache.demand_misses::cpu.inst 156969 # number of demand (read+write) misses 730system.cpu.l2cache.demand_misses::total 156992 # number of demand (read+write) misses 731system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses |
| 731system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses | 732system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses |
| 732system.cpu.l2cache.overall_misses::cpu.inst 157389 # number of overall misses 733system.cpu.l2cache.overall_misses::total 157409 # number of overall misses 734system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1388250 # number of ReadReq miss cycles | 733system.cpu.l2cache.overall_misses::cpu.inst 156969 # number of overall misses 734system.cpu.l2cache.overall_misses::total 156992 # number of overall misses 735system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1631500 # number of ReadReq miss cycles |
| 735system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles | 736system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles |
| 736system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1729894000 # number of ReadReq miss cycles 737system.cpu.l2cache.ReadReq_miss_latency::total 1731431750 # number of ReadReq miss cycles 738system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 394983 # number of UpgradeReq miss cycles 739system.cpu.l2cache.UpgradeReq_miss_latency::total 394983 # number of UpgradeReq miss cycles 740system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9208617265 # number of ReadExReq miss cycles 741system.cpu.l2cache.ReadExReq_miss_latency::total 9208617265 # number of ReadExReq miss cycles 742system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1388250 # number of demand (read+write) miss cycles | 737system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1700660750 # number of ReadReq miss cycles 738system.cpu.l2cache.ReadReq_miss_latency::total 1702441750 # number of ReadReq miss cycles 739system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 347985 # number of UpgradeReq miss cycles 740system.cpu.l2cache.UpgradeReq_miss_latency::total 347985 # number of UpgradeReq miss cycles 741system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9353977027 # number of ReadExReq miss cycles 742system.cpu.l2cache.ReadExReq_miss_latency::total 9353977027 # number of ReadExReq miss cycles 743system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1631500 # number of demand (read+write) miss cycles |
| 743system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles | 744system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles |
| 744system.cpu.l2cache.demand_miss_latency::cpu.inst 10938511265 # number of demand (read+write) miss cycles 745system.cpu.l2cache.demand_miss_latency::total 10940049015 # number of demand (read+write) miss cycles 746system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1388250 # number of overall miss cycles | 745system.cpu.l2cache.demand_miss_latency::cpu.inst 11054637777 # number of demand (read+write) miss cycles 746system.cpu.l2cache.demand_miss_latency::total 11056418777 # number of demand (read+write) miss cycles 747system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1631500 # number of overall miss cycles |
| 747system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles | 748system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles |
| 748system.cpu.l2cache.overall_miss_latency::cpu.inst 10938511265 # number of overall miss cycles 749system.cpu.l2cache.overall_miss_latency::total 10940049015 # number of overall miss cycles 750system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53591 # number of ReadReq accesses(hits+misses) 751system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11405 # number of ReadReq accesses(hits+misses) 752system.cpu.l2cache.ReadReq_accesses::cpu.inst 1934580 # number of ReadReq accesses(hits+misses) 753system.cpu.l2cache.ReadReq_accesses::total 1999576 # number of ReadReq accesses(hits+misses) 754system.cpu.l2cache.Writeback_accesses::writebacks 602969 # number of Writeback accesses(hits+misses) 755system.cpu.l2cache.Writeback_accesses::total 602969 # number of Writeback accesses(hits+misses) 756system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2961 # number of UpgradeReq accesses(hits+misses) 757system.cpu.l2cache.UpgradeReq_accesses::total 2961 # number of UpgradeReq accesses(hits+misses) 758system.cpu.l2cache.ReadExReq_accesses::cpu.inst 247546 # number of ReadExReq accesses(hits+misses) 759system.cpu.l2cache.ReadExReq_accesses::total 247546 # number of ReadExReq accesses(hits+misses) 760system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53591 # number of demand (read+write) accesses 761system.cpu.l2cache.demand_accesses::cpu.itb.walker 11405 # number of demand (read+write) accesses 762system.cpu.l2cache.demand_accesses::cpu.inst 2182126 # number of demand (read+write) accesses 763system.cpu.l2cache.demand_accesses::total 2247122 # number of demand (read+write) accesses 764system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53591 # number of overall (read+write) accesses 765system.cpu.l2cache.overall_accesses::cpu.itb.walker 11405 # number of overall (read+write) accesses 766system.cpu.l2cache.overall_accesses::cpu.inst 2182126 # number of overall (read+write) accesses 767system.cpu.l2cache.overall_accesses::total 2247122 # number of overall (read+write) accesses 768system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000336 # miss rate for ReadReq accesses 769system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000175 # miss rate for ReadReq accesses 770system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012416 # miss rate for ReadReq accesses 771system.cpu.l2cache.ReadReq_miss_rate::total 0.012023 # miss rate for ReadReq accesses 772system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.991557 # miss rate for UpgradeReq accesses 773system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991557 # miss rate for UpgradeReq accesses 774system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.538765 # miss rate for ReadExReq accesses 775system.cpu.l2cache.ReadExReq_miss_rate::total 0.538765 # miss rate for ReadExReq accesses 776system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000336 # miss rate for demand accesses 777system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000175 # miss rate for demand accesses 778system.cpu.l2cache.demand_miss_rate::cpu.inst 0.072126 # miss rate for demand accesses 779system.cpu.l2cache.demand_miss_rate::total 0.070049 # miss rate for demand accesses 780system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000336 # miss rate for overall accesses 781system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000175 # miss rate for overall accesses 782system.cpu.l2cache.overall_miss_rate::cpu.inst 0.072126 # miss rate for overall accesses 783system.cpu.l2cache.overall_miss_rate::total 0.070049 # miss rate for overall accesses 784system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77125 # average ReadReq miss latency | 749system.cpu.l2cache.overall_miss_latency::cpu.inst 11054637777 # number of overall miss cycles 750system.cpu.l2cache.overall_miss_latency::total 11056418777 # number of overall miss cycles 751system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 41654 # number of ReadReq accesses(hits+misses) 752system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10977 # number of ReadReq accesses(hits+misses) 753system.cpu.l2cache.ReadReq_accesses::cpu.inst 1916541 # number of ReadReq accesses(hits+misses) 754system.cpu.l2cache.ReadReq_accesses::total 1969172 # number of ReadReq accesses(hits+misses) 755system.cpu.l2cache.Writeback_accesses::writebacks 600964 # number of Writeback accesses(hits+misses) 756system.cpu.l2cache.Writeback_accesses::total 600964 # number of Writeback accesses(hits+misses) 757system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2972 # number of UpgradeReq accesses(hits+misses) 758system.cpu.l2cache.UpgradeReq_accesses::total 2972 # number of UpgradeReq accesses(hits+misses) 759system.cpu.l2cache.ReadExReq_accesses::cpu.inst 247467 # number of ReadExReq accesses(hits+misses) 760system.cpu.l2cache.ReadExReq_accesses::total 247467 # number of ReadExReq accesses(hits+misses) 761system.cpu.l2cache.demand_accesses::cpu.dtb.walker 41654 # number of demand (read+write) accesses 762system.cpu.l2cache.demand_accesses::cpu.itb.walker 10977 # number of demand (read+write) accesses 763system.cpu.l2cache.demand_accesses::cpu.inst 2164008 # number of demand (read+write) accesses 764system.cpu.l2cache.demand_accesses::total 2216639 # number of demand (read+write) accesses 765system.cpu.l2cache.overall_accesses::cpu.dtb.walker 41654 # number of overall (read+write) accesses 766system.cpu.l2cache.overall_accesses::cpu.itb.walker 10977 # number of overall (read+write) accesses 767system.cpu.l2cache.overall_accesses::cpu.inst 2164008 # number of overall (read+write) accesses 768system.cpu.l2cache.overall_accesses::total 2216639 # number of overall (read+write) accesses 769system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000504 # miss rate for ReadReq accesses 770system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000182 # miss rate for ReadReq accesses 771system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012346 # miss rate for ReadReq accesses 772system.cpu.l2cache.ReadReq_miss_rate::total 0.012027 # miss rate for ReadReq accesses 773system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.991588 # miss rate for UpgradeReq accesses 774system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991588 # miss rate for UpgradeReq accesses 775system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.538690 # miss rate for ReadExReq accesses 776system.cpu.l2cache.ReadExReq_miss_rate::total 0.538690 # miss rate for ReadExReq accesses 777system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000504 # miss rate for demand accesses 778system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000182 # miss rate for demand accesses 779system.cpu.l2cache.demand_miss_rate::cpu.inst 0.072536 # miss rate for demand accesses 780system.cpu.l2cache.demand_miss_rate::total 0.070824 # miss rate for demand accesses 781system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000504 # miss rate for overall accesses 782system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000182 # miss rate for overall accesses 783system.cpu.l2cache.overall_miss_rate::cpu.inst 0.072536 # miss rate for overall accesses 784system.cpu.l2cache.overall_miss_rate::total 0.070824 # miss rate for overall accesses 785system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77690.476190 # average ReadReq miss latency |
| 785system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency | 786system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency |
| 786system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72018.900916 # average ReadReq miss latency 787system.cpu.l2cache.ReadReq_avg_miss_latency::total 72022.951331 # average ReadReq miss latency 788system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 134.530995 # average UpgradeReq miss latency 789system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 134.530995 # average UpgradeReq miss latency 790system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69046.159640 # average ReadExReq miss latency 791system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69046.159640 # average ReadExReq miss latency 792system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77125 # average overall miss latency | 787system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71876.114704 # average ReadReq miss latency 788system.cpu.l2cache.ReadReq_avg_miss_latency::total 71881.512836 # average ReadReq miss latency 789system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 118.081099 # average UpgradeReq miss latency 790system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 118.081099 # average UpgradeReq miss latency 791system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70168.159653 # average ReadExReq miss latency 792system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70168.159653 # average ReadExReq miss latency 793system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77690.476190 # average overall miss latency |
| 793system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency | 794system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency |
| 794system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69499.846018 # average overall miss latency 795system.cpu.l2cache.demand_avg_miss_latency::total 69500.784676 # average overall miss latency 796system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77125 # average overall miss latency | 795system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70425.611280 # average overall miss latency 796system.cpu.l2cache.demand_avg_miss_latency::total 70426.638154 # average overall miss latency 797system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77690.476190 # average overall miss latency |
| 797system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency | 798system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency |
| 798system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69499.846018 # average overall miss latency 799system.cpu.l2cache.overall_avg_miss_latency::total 69500.784676 # average overall miss latency | 799system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70425.611280 # average overall miss latency 800system.cpu.l2cache.overall_avg_miss_latency::total 70426.638154 # average overall miss latency |
| 800system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 801system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 802system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 803system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 804system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 805system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 806system.cpu.l2cache.fast_writes 0 # number of fast writes performed 807system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 801system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 802system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 803system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 804system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 805system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 806system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 807system.cpu.l2cache.fast_writes 0 # number of fast writes performed 808system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 808system.cpu.l2cache.writebacks::writebacks 59840 # number of writebacks 809system.cpu.l2cache.writebacks::total 59840 # number of writebacks 810system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits 811system.cpu.l2cache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits 812system.cpu.l2cache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits 813system.cpu.l2cache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits 814system.cpu.l2cache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits 815system.cpu.l2cache.overall_mshr_hits::total 70 # number of overall MSHR hits 816system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 18 # number of ReadReq MSHR misses | 809system.cpu.l2cache.writebacks::writebacks 59552 # number of writebacks 810system.cpu.l2cache.writebacks::total 59552 # number of writebacks 811system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits 812system.cpu.l2cache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits 813system.cpu.l2cache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits 814system.cpu.l2cache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits 815system.cpu.l2cache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits 816system.cpu.l2cache.overall_mshr_hits::total 69 # number of overall MSHR hits 817system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses |
| 817system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses | 818system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses |
| 818system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 23950 # number of ReadReq MSHR misses 819system.cpu.l2cache.ReadReq_mshr_misses::total 23970 # number of ReadReq MSHR misses 820system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2936 # number of UpgradeReq MSHR misses 821system.cpu.l2cache.UpgradeReq_mshr_misses::total 2936 # number of UpgradeReq MSHR misses 822system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 133369 # number of ReadExReq MSHR misses 823system.cpu.l2cache.ReadExReq_mshr_misses::total 133369 # number of ReadExReq MSHR misses 824system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 18 # number of demand (read+write) MSHR misses | 819system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 23592 # number of ReadReq MSHR misses 820system.cpu.l2cache.ReadReq_mshr_misses::total 23615 # number of ReadReq MSHR misses 821system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2947 # number of UpgradeReq MSHR misses 822system.cpu.l2cache.UpgradeReq_mshr_misses::total 2947 # number of UpgradeReq MSHR misses 823system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 133308 # number of ReadExReq MSHR misses 824system.cpu.l2cache.ReadExReq_mshr_misses::total 133308 # number of ReadExReq MSHR misses 825system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses |
| 825system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses | 826system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses |
| 826system.cpu.l2cache.demand_mshr_misses::cpu.inst 157319 # number of demand (read+write) MSHR misses 827system.cpu.l2cache.demand_mshr_misses::total 157339 # number of demand (read+write) MSHR misses 828system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 18 # number of overall MSHR misses | 827system.cpu.l2cache.demand_mshr_misses::cpu.inst 156900 # number of demand (read+write) MSHR misses 828system.cpu.l2cache.demand_mshr_misses::total 156923 # number of demand (read+write) MSHR misses 829system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses |
| 829system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses | 830system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses |
| 830system.cpu.l2cache.overall_mshr_misses::cpu.inst 157319 # number of overall MSHR misses 831system.cpu.l2cache.overall_mshr_misses::total 157339 # number of overall MSHR misses 832system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1165250 # number of ReadReq MSHR miss cycles | 831system.cpu.l2cache.overall_mshr_misses::cpu.inst 156900 # number of overall MSHR misses 832system.cpu.l2cache.overall_mshr_misses::total 156923 # number of overall MSHR misses 833system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1370000 # number of ReadReq MSHR miss cycles |
| 833system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles | 834system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles |
| 834system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1425512750 # number of ReadReq MSHR miss cycles 835system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1426803000 # number of ReadReq MSHR miss cycles 836system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 29363936 # number of UpgradeReq MSHR miss cycles 837system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29363936 # number of UpgradeReq MSHR miss cycles 838system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7535729235 # number of ReadExReq MSHR miss cycles 839system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7535729235 # number of ReadExReq MSHR miss cycles 840system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1165250 # number of demand (read+write) MSHR miss cycles | 835system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1400834750 # number of ReadReq MSHR miss cycles 836system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1402329750 # number of ReadReq MSHR miss cycles 837system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 29473947 # number of UpgradeReq MSHR miss cycles 838system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29473947 # number of UpgradeReq MSHR miss cycles 839system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7655220473 # number of ReadExReq MSHR miss cycles 840system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7655220473 # number of ReadExReq MSHR miss cycles 841system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1370000 # number of demand (read+write) MSHR miss cycles |
| 841system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles | 842system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles |
| 842system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8961241985 # number of demand (read+write) MSHR miss cycles 843system.cpu.l2cache.demand_mshr_miss_latency::total 8962532235 # number of demand (read+write) MSHR miss cycles 844system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1165250 # number of overall MSHR miss cycles | 843system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9056055223 # number of demand (read+write) MSHR miss cycles 844system.cpu.l2cache.demand_mshr_miss_latency::total 9057550223 # number of demand (read+write) MSHR miss cycles 845system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1370000 # number of overall MSHR miss cycles |
| 845system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles | 846system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles |
| 846system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8961241985 # number of overall MSHR miss cycles 847system.cpu.l2cache.overall_mshr_miss_latency::total 8962532235 # number of overall MSHR miss cycles 848system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 167312402000 # number of ReadReq MSHR uncacheable cycles 849system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167312402000 # number of ReadReq MSHR uncacheable cycles 850system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 16707876361 # number of WriteReq MSHR uncacheable cycles 851system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16707876361 # number of WriteReq MSHR uncacheable cycles 852system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 184020278361 # number of overall MSHR uncacheable cycles 853system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184020278361 # number of overall MSHR uncacheable cycles 854system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000336 # mshr miss rate for ReadReq accesses 855system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000175 # mshr miss rate for ReadReq accesses 856system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012380 # mshr miss rate for ReadReq accesses 857system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011988 # mshr miss rate for ReadReq accesses 858system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.991557 # mshr miss rate for UpgradeReq accesses 859system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991557 # mshr miss rate for UpgradeReq accesses 860system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.538765 # mshr miss rate for ReadExReq accesses 861system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.538765 # mshr miss rate for ReadExReq accesses 862system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000336 # mshr miss rate for demand accesses 863system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000175 # mshr miss rate for demand accesses 864system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.072094 # mshr miss rate for demand accesses 865system.cpu.l2cache.demand_mshr_miss_rate::total 0.070018 # mshr miss rate for demand accesses 866system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000336 # mshr miss rate for overall accesses 867system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000175 # mshr miss rate for overall accesses 868system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.072094 # mshr miss rate for overall accesses 869system.cpu.l2cache.overall_mshr_miss_rate::total 0.070018 # mshr miss rate for overall accesses 870system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64736.111111 # average ReadReq mshr miss latency | 847system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9056055223 # number of overall MSHR miss cycles 848system.cpu.l2cache.overall_mshr_miss_latency::total 9057550223 # number of overall MSHR miss cycles 849system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 167362107750 # number of ReadReq MSHR uncacheable cycles 850system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167362107750 # number of ReadReq MSHR uncacheable cycles 851system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 16707879855 # number of WriteReq MSHR uncacheable cycles 852system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16707879855 # number of WriteReq MSHR uncacheable cycles 853system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 184069987605 # number of overall MSHR uncacheable cycles 854system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184069987605 # number of overall MSHR uncacheable cycles 855system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000504 # mshr miss rate for ReadReq accesses 856system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000182 # mshr miss rate for ReadReq accesses 857system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012310 # mshr miss rate for ReadReq accesses 858system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011992 # mshr miss rate for ReadReq accesses 859system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.991588 # mshr miss rate for UpgradeReq accesses 860system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991588 # mshr miss rate for UpgradeReq accesses 861system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.538690 # mshr miss rate for ReadExReq accesses 862system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.538690 # mshr miss rate for ReadExReq accesses 863system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000504 # mshr miss rate for demand accesses 864system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000182 # mshr miss rate for demand accesses 865system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.072504 # mshr miss rate for demand accesses 866system.cpu.l2cache.demand_mshr_miss_rate::total 0.070793 # mshr miss rate for demand accesses 867system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000504 # mshr miss rate for overall accesses 868system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000182 # mshr miss rate for overall accesses 869system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.072504 # mshr miss rate for overall accesses 870system.cpu.l2cache.overall_mshr_miss_rate::total 0.070793 # mshr miss rate for overall accesses 871system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65238.095238 # average ReadReq mshr miss latency |
| 871system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency | 872system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency |
| 872system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59520.365344 # average ReadReq mshr miss latency 873system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59524.530663 # average ReadReq mshr miss latency 874system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10001.340599 # average UpgradeReq mshr miss latency 875system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.340599 # average UpgradeReq mshr miss latency 876system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56502.854749 # average ReadExReq mshr miss latency 877system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56502.854749 # average ReadExReq mshr miss latency 878system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64736.111111 # average overall mshr miss latency | 873system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59377.532638 # average ReadReq mshr miss latency 874system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59383.008681 # average ReadReq mshr miss latency 875system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10001.339328 # average UpgradeReq mshr miss latency 876system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.339328 # average UpgradeReq mshr miss latency 877system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57425.064310 # average ReadExReq mshr miss latency 878system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57425.064310 # average ReadExReq mshr miss latency 879system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65238.095238 # average overall mshr miss latency |
| 879system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency | 880system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency |
| 880system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56962.235871 # average overall mshr miss latency 881system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56963.195616 # average overall mshr miss latency 882system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64736.111111 # average overall mshr miss latency | 881system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57718.643869 # average overall mshr miss latency 882system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57719.711088 # average overall mshr miss latency 883system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65238.095238 # average overall mshr miss latency |
| 883system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency | 884system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency |
| 884system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56962.235871 # average overall mshr miss latency 885system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56963.195616 # average overall mshr miss latency | 885system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57718.643869 # average overall mshr miss latency 886system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57719.711088 # average overall mshr miss latency |
| 886system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 887system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 888system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 889system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 890system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 891system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 892system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 887system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 888system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 889system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 890system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 891system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 892system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 893system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 893system.cpu.dcache.tags.replacements 637780 # number of replacements 894system.cpu.dcache.tags.tagsinuse 511.959208 # Cycle average of tags in use 895system.cpu.dcache.tags.total_refs 23638258 # Total number of references to valid blocks. 896system.cpu.dcache.tags.sampled_refs 638292 # Sample count of references to valid blocks. 897system.cpu.dcache.tags.avg_refs 37.033612 # Average number of references to valid blocks. 898system.cpu.dcache.tags.warmup_cycle 227414250 # Cycle when the warmup percentage was hit. 899system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959208 # Average occupied blocks per requestor | 894system.cpu.dcache.tags.replacements 635561 # number of replacements 895system.cpu.dcache.tags.tagsinuse 511.959259 # Cycle average of tags in use 896system.cpu.dcache.tags.total_refs 21828853 # Total number of references to valid blocks. 897system.cpu.dcache.tags.sampled_refs 636073 # Sample count of references to valid blocks. 898system.cpu.dcache.tags.avg_refs 34.318157 # Average number of references to valid blocks. 899system.cpu.dcache.tags.warmup_cycle 227074250 # Cycle when the warmup percentage was hit. 900system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959259 # Average occupied blocks per requestor |
| 900system.cpu.dcache.tags.occ_percent::cpu.inst 0.999920 # Average percentage of cache occupancy 901system.cpu.dcache.tags.occ_percent::total 0.999920 # Average percentage of cache occupancy 902system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 901system.cpu.dcache.tags.occ_percent::cpu.inst 0.999920 # Average percentage of cache occupancy 902system.cpu.dcache.tags.occ_percent::total 0.999920 # Average percentage of cache occupancy 903system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 903system.cpu.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id 904system.cpu.dcache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id 905system.cpu.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id | 904system.cpu.dcache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id 905system.cpu.dcache.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id 906system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id |
| 906system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 907system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 907system.cpu.dcache.tags.tag_accesses 98967232 # Number of tag accesses 908system.cpu.dcache.tags.data_accesses 98967232 # Number of data accesses 909system.cpu.dcache.ReadReq_hits::cpu.inst 13401610 # number of ReadReq hits 910system.cpu.dcache.ReadReq_hits::total 13401610 # number of ReadReq hits 911system.cpu.dcache.WriteReq_hits::cpu.inst 9749262 # number of WriteReq hits 912system.cpu.dcache.WriteReq_hits::total 9749262 # number of WriteReq hits 913system.cpu.dcache.LoadLockedReq_hits::cpu.inst 236772 # number of LoadLockedReq hits 914system.cpu.dcache.LoadLockedReq_hits::total 236772 # number of LoadLockedReq hits 915system.cpu.dcache.StoreCondReq_hits::cpu.inst 247602 # number of StoreCondReq hits 916system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits 917system.cpu.dcache.demand_hits::cpu.inst 23150872 # number of demand (read+write) hits 918system.cpu.dcache.demand_hits::total 23150872 # number of demand (read+write) hits 919system.cpu.dcache.overall_hits::cpu.inst 23150872 # number of overall hits 920system.cpu.dcache.overall_hits::total 23150872 # number of overall hits 921system.cpu.dcache.ReadReq_misses::cpu.inst 462868 # number of ReadReq misses 922system.cpu.dcache.ReadReq_misses::total 462868 # number of ReadReq misses 923system.cpu.dcache.WriteReq_misses::cpu.inst 473290 # number of WriteReq misses 924system.cpu.dcache.WriteReq_misses::total 473290 # number of WriteReq misses 925system.cpu.dcache.LoadLockedReq_misses::cpu.inst 10831 # number of LoadLockedReq misses 926system.cpu.dcache.LoadLockedReq_misses::total 10831 # number of LoadLockedReq misses 927system.cpu.dcache.demand_misses::cpu.inst 936158 # number of demand (read+write) misses 928system.cpu.dcache.demand_misses::total 936158 # number of demand (read+write) misses 929system.cpu.dcache.overall_misses::cpu.inst 936158 # number of overall misses 930system.cpu.dcache.overall_misses::total 936158 # number of overall misses 931system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7014286436 # number of ReadReq miss cycles 932system.cpu.dcache.ReadReq_miss_latency::total 7014286436 # number of ReadReq miss cycles 933system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21912161323 # number of WriteReq miss cycles 934system.cpu.dcache.WriteReq_miss_latency::total 21912161323 # number of WriteReq miss cycles 935system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 150765000 # number of LoadLockedReq miss cycles 936system.cpu.dcache.LoadLockedReq_miss_latency::total 150765000 # number of LoadLockedReq miss cycles 937system.cpu.dcache.demand_miss_latency::cpu.inst 28926447759 # number of demand (read+write) miss cycles 938system.cpu.dcache.demand_miss_latency::total 28926447759 # number of demand (read+write) miss cycles 939system.cpu.dcache.overall_miss_latency::cpu.inst 28926447759 # number of overall miss cycles 940system.cpu.dcache.overall_miss_latency::total 28926447759 # number of overall miss cycles 941system.cpu.dcache.ReadReq_accesses::cpu.inst 13864478 # number of ReadReq accesses(hits+misses) 942system.cpu.dcache.ReadReq_accesses::total 13864478 # number of ReadReq accesses(hits+misses) 943system.cpu.dcache.WriteReq_accesses::cpu.inst 10222552 # number of WriteReq accesses(hits+misses) 944system.cpu.dcache.WriteReq_accesses::total 10222552 # number of WriteReq accesses(hits+misses) 945system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 247603 # number of LoadLockedReq accesses(hits+misses) 946system.cpu.dcache.LoadLockedReq_accesses::total 247603 # number of LoadLockedReq accesses(hits+misses) 947system.cpu.dcache.StoreCondReq_accesses::cpu.inst 247602 # number of StoreCondReq accesses(hits+misses) 948system.cpu.dcache.StoreCondReq_accesses::total 247602 # number of StoreCondReq accesses(hits+misses) 949system.cpu.dcache.demand_accesses::cpu.inst 24087030 # number of demand (read+write) accesses 950system.cpu.dcache.demand_accesses::total 24087030 # number of demand (read+write) accesses 951system.cpu.dcache.overall_accesses::cpu.inst 24087030 # number of overall (read+write) accesses 952system.cpu.dcache.overall_accesses::total 24087030 # number of overall (read+write) accesses 953system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.033385 # miss rate for ReadReq accesses 954system.cpu.dcache.ReadReq_miss_rate::total 0.033385 # miss rate for ReadReq accesses 955system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.046299 # miss rate for WriteReq accesses 956system.cpu.dcache.WriteReq_miss_rate::total 0.046299 # miss rate for WriteReq accesses 957system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.043743 # miss rate for LoadLockedReq accesses 958system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043743 # miss rate for LoadLockedReq accesses 959system.cpu.dcache.demand_miss_rate::cpu.inst 0.038866 # miss rate for demand accesses 960system.cpu.dcache.demand_miss_rate::total 0.038866 # miss rate for demand accesses 961system.cpu.dcache.overall_miss_rate::cpu.inst 0.038866 # miss rate for overall accesses 962system.cpu.dcache.overall_miss_rate::total 0.038866 # miss rate for overall accesses 963system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15153.967083 # average ReadReq miss latency 964system.cpu.dcache.ReadReq_avg_miss_latency::total 15153.967083 # average ReadReq miss latency 965system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46297.537077 # average WriteReq miss latency 966system.cpu.dcache.WriteReq_avg_miss_latency::total 46297.537077 # average WriteReq miss latency 967system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13919.767335 # average LoadLockedReq miss latency 968system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13919.767335 # average LoadLockedReq miss latency 969system.cpu.dcache.demand_avg_miss_latency::cpu.inst 30899.108654 # average overall miss latency 970system.cpu.dcache.demand_avg_miss_latency::total 30899.108654 # average overall miss latency 971system.cpu.dcache.overall_avg_miss_latency::cpu.inst 30899.108654 # average overall miss latency 972system.cpu.dcache.overall_avg_miss_latency::total 30899.108654 # average overall miss latency | 908system.cpu.dcache.tags.tag_accesses 91724261 # Number of tag accesses 909system.cpu.dcache.tags.data_accesses 91724261 # Number of data accesses 910system.cpu.dcache.ReadReq_hits::cpu.inst 11595405 # number of ReadReq hits 911system.cpu.dcache.ReadReq_hits::total 11595405 # number of ReadReq hits 912system.cpu.dcache.WriteReq_hits::cpu.inst 9746069 # number of WriteReq hits 913system.cpu.dcache.WriteReq_hits::total 9746069 # number of WriteReq hits 914system.cpu.dcache.LoadLockedReq_hits::cpu.inst 236744 # number of LoadLockedReq hits 915system.cpu.dcache.LoadLockedReq_hits::total 236744 # number of LoadLockedReq hits 916system.cpu.dcache.StoreCondReq_hits::cpu.inst 247613 # number of StoreCondReq hits 917system.cpu.dcache.StoreCondReq_hits::total 247613 # number of StoreCondReq hits 918system.cpu.dcache.demand_hits::cpu.inst 21341474 # number of demand (read+write) hits 919system.cpu.dcache.demand_hits::total 21341474 # number of demand (read+write) hits 920system.cpu.dcache.overall_hits::cpu.inst 21341474 # number of overall hits 921system.cpu.dcache.overall_hits::total 21341474 # number of overall hits 922system.cpu.dcache.ReadReq_misses::cpu.inst 458732 # number of ReadReq misses 923system.cpu.dcache.ReadReq_misses::total 458732 # number of ReadReq misses 924system.cpu.dcache.WriteReq_misses::cpu.inst 476614 # number of WriteReq misses 925system.cpu.dcache.WriteReq_misses::total 476614 # number of WriteReq misses 926system.cpu.dcache.LoadLockedReq_misses::cpu.inst 10870 # number of LoadLockedReq misses 927system.cpu.dcache.LoadLockedReq_misses::total 10870 # number of LoadLockedReq misses 928system.cpu.dcache.demand_misses::cpu.inst 935346 # number of demand (read+write) misses 929system.cpu.dcache.demand_misses::total 935346 # number of demand (read+write) misses 930system.cpu.dcache.overall_misses::cpu.inst 935346 # number of overall misses 931system.cpu.dcache.overall_misses::total 935346 # number of overall misses 932system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6943170934 # number of ReadReq miss cycles 933system.cpu.dcache.ReadReq_miss_latency::total 6943170934 # number of ReadReq miss cycles 934system.cpu.dcache.WriteReq_miss_latency::cpu.inst 22231593506 # number of WriteReq miss cycles 935system.cpu.dcache.WriteReq_miss_latency::total 22231593506 # number of WriteReq miss cycles 936system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 151835000 # number of LoadLockedReq miss cycles 937system.cpu.dcache.LoadLockedReq_miss_latency::total 151835000 # number of LoadLockedReq miss cycles 938system.cpu.dcache.demand_miss_latency::cpu.inst 29174764440 # number of demand (read+write) miss cycles 939system.cpu.dcache.demand_miss_latency::total 29174764440 # number of demand (read+write) miss cycles 940system.cpu.dcache.overall_miss_latency::cpu.inst 29174764440 # number of overall miss cycles 941system.cpu.dcache.overall_miss_latency::total 29174764440 # number of overall miss cycles 942system.cpu.dcache.ReadReq_accesses::cpu.inst 12054137 # number of ReadReq accesses(hits+misses) 943system.cpu.dcache.ReadReq_accesses::total 12054137 # number of ReadReq accesses(hits+misses) 944system.cpu.dcache.WriteReq_accesses::cpu.inst 10222683 # number of WriteReq accesses(hits+misses) 945system.cpu.dcache.WriteReq_accesses::total 10222683 # number of WriteReq accesses(hits+misses) 946system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 247614 # number of LoadLockedReq accesses(hits+misses) 947system.cpu.dcache.LoadLockedReq_accesses::total 247614 # number of LoadLockedReq accesses(hits+misses) 948system.cpu.dcache.StoreCondReq_accesses::cpu.inst 247613 # number of StoreCondReq accesses(hits+misses) 949system.cpu.dcache.StoreCondReq_accesses::total 247613 # number of StoreCondReq accesses(hits+misses) 950system.cpu.dcache.demand_accesses::cpu.inst 22276820 # number of demand (read+write) accesses 951system.cpu.dcache.demand_accesses::total 22276820 # number of demand (read+write) accesses 952system.cpu.dcache.overall_accesses::cpu.inst 22276820 # number of overall (read+write) accesses 953system.cpu.dcache.overall_accesses::total 22276820 # number of overall (read+write) accesses 954system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.038056 # miss rate for ReadReq accesses 955system.cpu.dcache.ReadReq_miss_rate::total 0.038056 # miss rate for ReadReq accesses 956system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.046623 # miss rate for WriteReq accesses 957system.cpu.dcache.WriteReq_miss_rate::total 0.046623 # miss rate for WriteReq accesses 958system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.043899 # miss rate for LoadLockedReq accesses 959system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043899 # miss rate for LoadLockedReq accesses 960system.cpu.dcache.demand_miss_rate::cpu.inst 0.041987 # miss rate for demand accesses 961system.cpu.dcache.demand_miss_rate::total 0.041987 # miss rate for demand accesses 962system.cpu.dcache.overall_miss_rate::cpu.inst 0.041987 # miss rate for overall accesses 963system.cpu.dcache.overall_miss_rate::total 0.041987 # miss rate for overall accesses 964system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15135.571388 # average ReadReq miss latency 965system.cpu.dcache.ReadReq_avg_miss_latency::total 15135.571388 # average ReadReq miss latency 966system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46644.860424 # average WriteReq miss latency 967system.cpu.dcache.WriteReq_avg_miss_latency::total 46644.860424 # average WriteReq miss latency 968system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13968.261270 # average LoadLockedReq miss latency 969system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13968.261270 # average LoadLockedReq miss latency 970system.cpu.dcache.demand_avg_miss_latency::cpu.inst 31191.414129 # average overall miss latency 971system.cpu.dcache.demand_avg_miss_latency::total 31191.414129 # average overall miss latency 972system.cpu.dcache.overall_avg_miss_latency::cpu.inst 31191.414129 # average overall miss latency 973system.cpu.dcache.overall_avg_miss_latency::total 31191.414129 # average overall miss latency |
| 973system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 974system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 975system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 976system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 977system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 978system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 979system.cpu.dcache.fast_writes 0 # number of fast writes performed 980system.cpu.dcache.cache_copies 0 # number of cache copies performed | 974system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 975system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 976system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 977system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 978system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 979system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 980system.cpu.dcache.fast_writes 0 # number of fast writes performed 981system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 981system.cpu.dcache.writebacks::writebacks 602969 # number of writebacks 982system.cpu.dcache.writebacks::total 602969 # number of writebacks 983system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 82884 # number of ReadReq MSHR hits 984system.cpu.dcache.ReadReq_mshr_hits::total 82884 # number of ReadReq MSHR hits 985system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 222784 # number of WriteReq MSHR hits 986system.cpu.dcache.WriteReq_mshr_hits::total 222784 # number of WriteReq MSHR hits 987system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 68 # number of LoadLockedReq MSHR hits 988system.cpu.dcache.LoadLockedReq_mshr_hits::total 68 # number of LoadLockedReq MSHR hits 989system.cpu.dcache.demand_mshr_hits::cpu.inst 305668 # number of demand (read+write) MSHR hits 990system.cpu.dcache.demand_mshr_hits::total 305668 # number of demand (read+write) MSHR hits 991system.cpu.dcache.overall_mshr_hits::cpu.inst 305668 # number of overall MSHR hits 992system.cpu.dcache.overall_mshr_hits::total 305668 # number of overall MSHR hits 993system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 379984 # number of ReadReq MSHR misses 994system.cpu.dcache.ReadReq_mshr_misses::total 379984 # number of ReadReq MSHR misses 995system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 250506 # number of WriteReq MSHR misses 996system.cpu.dcache.WriteReq_mshr_misses::total 250506 # number of WriteReq MSHR misses 997system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 10763 # number of LoadLockedReq MSHR misses 998system.cpu.dcache.LoadLockedReq_mshr_misses::total 10763 # number of LoadLockedReq MSHR misses 999system.cpu.dcache.demand_mshr_misses::cpu.inst 630490 # number of demand (read+write) MSHR misses 1000system.cpu.dcache.demand_mshr_misses::total 630490 # number of demand (read+write) MSHR misses 1001system.cpu.dcache.overall_mshr_misses::cpu.inst 630490 # number of overall MSHR misses 1002system.cpu.dcache.overall_mshr_misses::total 630490 # number of overall MSHR misses 1003system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4859150309 # number of ReadReq MSHR miss cycles 1004system.cpu.dcache.ReadReq_mshr_miss_latency::total 4859150309 # number of ReadReq MSHR miss cycles 1005system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10668108512 # number of WriteReq MSHR miss cycles 1006system.cpu.dcache.WriteReq_mshr_miss_latency::total 10668108512 # number of WriteReq MSHR miss cycles 1007system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 128265000 # number of LoadLockedReq MSHR miss cycles 1008system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 128265000 # number of LoadLockedReq MSHR miss cycles 1009system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15527258821 # number of demand (read+write) MSHR miss cycles 1010system.cpu.dcache.demand_mshr_miss_latency::total 15527258821 # number of demand (read+write) MSHR miss cycles 1011system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 15527258821 # number of overall MSHR miss cycles 1012system.cpu.dcache.overall_mshr_miss_latency::total 15527258821 # number of overall MSHR miss cycles 1013system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182582279000 # number of ReadReq MSHR uncacheable cycles 1014system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182582279000 # number of ReadReq MSHR uncacheable cycles 1015system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058245639 # number of WriteReq MSHR uncacheable cycles 1016system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058245639 # number of WriteReq MSHR uncacheable cycles 1017system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208640524639 # number of overall MSHR uncacheable cycles 1018system.cpu.dcache.overall_mshr_uncacheable_latency::total 208640524639 # number of overall MSHR uncacheable cycles 1019system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.027407 # mshr miss rate for ReadReq accesses 1020system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027407 # mshr miss rate for ReadReq accesses 1021system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.024505 # mshr miss rate for WriteReq accesses 1022system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses 1023system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043469 # mshr miss rate for LoadLockedReq accesses 1024system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043469 # mshr miss rate for LoadLockedReq accesses 1025system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.026175 # mshr miss rate for demand accesses 1026system.cpu.dcache.demand_mshr_miss_rate::total 0.026175 # mshr miss rate for demand accesses 1027system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.026175 # mshr miss rate for overall accesses 1028system.cpu.dcache.overall_mshr_miss_rate::total 0.026175 # mshr miss rate for overall accesses 1029system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12787.776088 # average ReadReq mshr miss latency 1030system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12787.776088 # average ReadReq mshr miss latency 1031system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 42586.239499 # average WriteReq mshr miss latency 1032system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42586.239499 # average WriteReq mshr miss latency 1033system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11917.216389 # average LoadLockedReq mshr miss latency 1034system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11917.216389 # average LoadLockedReq mshr miss latency 1035system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24627.288016 # average overall mshr miss latency 1036system.cpu.dcache.demand_avg_mshr_miss_latency::total 24627.288016 # average overall mshr miss latency 1037system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24627.288016 # average overall mshr miss latency 1038system.cpu.dcache.overall_avg_mshr_miss_latency::total 24627.288016 # average overall mshr miss latency | 982system.cpu.dcache.writebacks::writebacks 600964 # number of writebacks 983system.cpu.dcache.writebacks::total 600964 # number of writebacks 984system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 80923 # number of ReadReq MSHR hits 985system.cpu.dcache.ReadReq_mshr_hits::total 80923 # number of ReadReq MSHR hits 986system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 226176 # number of WriteReq MSHR hits 987system.cpu.dcache.WriteReq_mshr_hits::total 226176 # number of WriteReq MSHR hits 988system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 72 # number of LoadLockedReq MSHR hits 989system.cpu.dcache.LoadLockedReq_mshr_hits::total 72 # number of LoadLockedReq MSHR hits 990system.cpu.dcache.demand_mshr_hits::cpu.inst 307099 # number of demand (read+write) MSHR hits 991system.cpu.dcache.demand_mshr_hits::total 307099 # number of demand (read+write) MSHR hits 992system.cpu.dcache.overall_mshr_hits::cpu.inst 307099 # number of overall MSHR hits 993system.cpu.dcache.overall_mshr_hits::total 307099 # number of overall MSHR hits 994system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 377809 # number of ReadReq MSHR misses 995system.cpu.dcache.ReadReq_mshr_misses::total 377809 # number of ReadReq MSHR misses 996system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 250438 # number of WriteReq MSHR misses 997system.cpu.dcache.WriteReq_mshr_misses::total 250438 # number of WriteReq MSHR misses 998system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 10798 # number of LoadLockedReq MSHR misses 999system.cpu.dcache.LoadLockedReq_mshr_misses::total 10798 # number of LoadLockedReq MSHR misses 1000system.cpu.dcache.demand_mshr_misses::cpu.inst 628247 # number of demand (read+write) MSHR misses 1001system.cpu.dcache.demand_mshr_misses::total 628247 # number of demand (read+write) MSHR misses 1002system.cpu.dcache.overall_mshr_misses::cpu.inst 628247 # number of overall MSHR misses 1003system.cpu.dcache.overall_mshr_misses::total 628247 # number of overall MSHR misses 1004system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4823958811 # number of ReadReq MSHR miss cycles 1005system.cpu.dcache.ReadReq_mshr_miss_latency::total 4823958811 # number of ReadReq MSHR miss cycles 1006system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10813361832 # number of WriteReq MSHR miss cycles 1007system.cpu.dcache.WriteReq_mshr_miss_latency::total 10813361832 # number of WriteReq MSHR miss cycles 1008system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 129211000 # number of LoadLockedReq MSHR miss cycles 1009system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 129211000 # number of LoadLockedReq MSHR miss cycles 1010system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15637320643 # number of demand (read+write) MSHR miss cycles 1011system.cpu.dcache.demand_mshr_miss_latency::total 15637320643 # number of demand (read+write) MSHR miss cycles 1012system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 15637320643 # number of overall MSHR miss cycles 1013system.cpu.dcache.overall_mshr_miss_latency::total 15637320643 # number of overall MSHR miss cycles 1014system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182632094250 # number of ReadReq MSHR uncacheable cycles 1015system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182632094250 # number of ReadReq MSHR uncacheable cycles 1016system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058171145 # number of WriteReq MSHR uncacheable cycles 1017system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058171145 # number of WriteReq MSHR uncacheable cycles 1018system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208690265395 # number of overall MSHR uncacheable cycles 1019system.cpu.dcache.overall_mshr_uncacheable_latency::total 208690265395 # number of overall MSHR uncacheable cycles 1020system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.031343 # mshr miss rate for ReadReq accesses 1021system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031343 # mshr miss rate for ReadReq accesses 1022system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.024498 # mshr miss rate for WriteReq accesses 1023system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024498 # mshr miss rate for WriteReq accesses 1024system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043608 # mshr miss rate for LoadLockedReq accesses 1025system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043608 # mshr miss rate for LoadLockedReq accesses 1026system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.028202 # mshr miss rate for demand accesses 1027system.cpu.dcache.demand_mshr_miss_rate::total 0.028202 # mshr miss rate for demand accesses 1028system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.028202 # mshr miss rate for overall accesses 1029system.cpu.dcache.overall_mshr_miss_rate::total 0.028202 # mshr miss rate for overall accesses 1030system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12768.247477 # average ReadReq mshr miss latency 1031system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12768.247477 # average ReadReq mshr miss latency 1032system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 43177.799823 # average WriteReq mshr miss latency 1033system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43177.799823 # average WriteReq mshr miss latency 1034system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11966.197444 # average LoadLockedReq mshr miss latency 1035system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11966.197444 # average LoadLockedReq mshr miss latency 1036system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24890.402410 # average overall mshr miss latency 1037system.cpu.dcache.demand_avg_mshr_miss_latency::total 24890.402410 # average overall mshr miss latency 1038system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24890.402410 # average overall mshr miss latency 1039system.cpu.dcache.overall_avg_mshr_miss_latency::total 24890.402410 # average overall mshr miss latency |
| 1039system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1040system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1041system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 1042system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1043system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1044system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1045system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1046system.iocache.tags.replacements 0 # number of replacements --- 7 unchanged lines hidden (view full) --- 1054system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1055system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1056system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1057system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1058system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1059system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1060system.iocache.fast_writes 0 # number of fast writes performed 1061system.iocache.cache_copies 0 # number of cache copies performed | 1040system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1041system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1042system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 1043system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1044system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1045system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1046system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1047system.iocache.tags.replacements 0 # number of replacements --- 7 unchanged lines hidden (view full) --- 1055system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1056system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1057system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1058system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1059system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1060system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1061system.iocache.fast_writes 0 # number of fast writes performed 1062system.iocache.cache_copies 0 # number of cache copies performed |
| 1062system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1738541884500 # number of ReadReq MSHR uncacheable cycles 1063system.iocache.ReadReq_mshr_uncacheable_latency::total 1738541884500 # number of ReadReq MSHR uncacheable cycles 1064system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1738541884500 # number of overall MSHR uncacheable cycles 1065system.iocache.overall_mshr_uncacheable_latency::total 1738541884500 # number of overall MSHR uncacheable cycles | 1063system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736623648250 # number of ReadReq MSHR uncacheable cycles 1064system.iocache.ReadReq_mshr_uncacheable_latency::total 1736623648250 # number of ReadReq MSHR uncacheable cycles 1065system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736623648250 # number of overall MSHR uncacheable cycles 1066system.iocache.overall_mshr_uncacheable_latency::total 1736623648250 # number of overall MSHR uncacheable cycles |
| 1066system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1067system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1068system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1069system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1070system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1071 1072---------- End Simulation Statistics ---------- | 1067system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1068system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1069system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1070system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1071system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1072 1073---------- End Simulation Statistics ---------- |