| stats.txt (10260:384d554cea8c) | stats.txt (10261:dc198e224a85) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3final_tick 2567690995500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 4host_inst_rate 83247 # Simulator instruction rate (inst/s) 5host_mem_usage 453632 # Number of bytes of host memory used 6host_op_rate 107007 # Simulator op (including micro ops) rate (op/s) 7host_seconds 727.87 # Real time elapsed on the host 8host_tick_rate 3527658330 # Simulator tick rate (ticks/s) | 3sim_seconds 2.567677 # Number of seconds simulated 4sim_ticks 2567677478000 # Number of ticks simulated 5final_tick 2567677478000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 9sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 10sim_insts 60593069 # Number of instructions simulated 11sim_ops 77887632 # Number of ops (including micro ops) simulated 12sim_seconds 2.567691 # Number of seconds simulated 13sim_ticks 2567690995500 # Number of ticks simulated 14system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 15system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 16system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 17system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 18system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 19system.cf0.dma_write_txs 0 # Number of DMA write transactions. | 7host_inst_rate 53140 # Simulator instruction rate (inst/s) 8host_op_rate 68307 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2251849348 # Simulator tick rate (ticks/s) 10host_mem_usage 443244 # Number of bytes of host memory used 11host_seconds 1140.25 # Real time elapsed on the host 12sim_insts 60592948 # Number of instructions simulated 13sim_ops 77887482 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts |
| 20system.clk_domain.clock 1000 # Clock period in ticks | 15system.clk_domain.clock 1000 # Clock period in ticks |
| 21system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 22system.cpu.branchPred.BTBHitPct 71.037327 # BTB Hit Percentage 23system.cpu.branchPred.BTBHits 6285951 # Number of BTB hits 24system.cpu.branchPred.BTBLookups 8848800 # Number of BTB lookups 25system.cpu.branchPred.RASInCorrect 141766 # Number of incorrect RAS predictions. 26system.cpu.branchPred.condIncorrect 1083327 # Number of conditional branches incorrect 27system.cpu.branchPred.condPredicted 9899581 # Number of conditional branches predicted 28system.cpu.branchPred.lookups 12901223 # Number of BP lookups 29system.cpu.branchPred.usedRAS 1514142 # Number of times the RAS was used to get a target. 30system.cpu.committedInsts 60593069 # Number of instructions committed 31system.cpu.committedOps 77887632 # Number of ops (including micro ops) committed 32system.cpu.cpi 9.521608 # CPI: cycles per instruction 33system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 247603 # number of LoadLockedReq accesses(hits+misses) 34system.cpu.dcache.LoadLockedReq_accesses::total 247603 # number of LoadLockedReq accesses(hits+misses) 35system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13892.781561 # average LoadLockedReq miss latency 36system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13892.781561 # average LoadLockedReq miss latency 37system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11890.018527 # average LoadLockedReq mshr miss latency 38system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11890.018527 # average LoadLockedReq mshr miss latency 39system.cpu.dcache.LoadLockedReq_hits::cpu.inst 236735 # number of LoadLockedReq hits 40system.cpu.dcache.LoadLockedReq_hits::total 236735 # number of LoadLockedReq hits 41system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 150986750 # number of LoadLockedReq miss cycles 42system.cpu.dcache.LoadLockedReq_miss_latency::total 150986750 # number of LoadLockedReq miss cycles 43system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.043893 # miss rate for LoadLockedReq accesses 44system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043893 # miss rate for LoadLockedReq accesses 45system.cpu.dcache.LoadLockedReq_misses::cpu.inst 10868 # number of LoadLockedReq misses 46system.cpu.dcache.LoadLockedReq_misses::total 10868 # number of LoadLockedReq misses 47system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 73 # number of LoadLockedReq MSHR hits 48system.cpu.dcache.LoadLockedReq_mshr_hits::total 73 # number of LoadLockedReq MSHR hits 49system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 128352750 # number of LoadLockedReq MSHR miss cycles 50system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 128352750 # number of LoadLockedReq MSHR miss cycles 51system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043598 # mshr miss rate for LoadLockedReq accesses 52system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043598 # mshr miss rate for LoadLockedReq accesses 53system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 10795 # number of LoadLockedReq MSHR misses 54system.cpu.dcache.LoadLockedReq_mshr_misses::total 10795 # number of LoadLockedReq MSHR misses 55system.cpu.dcache.ReadReq_accesses::cpu.inst 13864450 # number of ReadReq accesses(hits+misses) 56system.cpu.dcache.ReadReq_accesses::total 13864450 # number of ReadReq accesses(hits+misses) 57system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15150.498583 # average ReadReq miss latency 58system.cpu.dcache.ReadReq_avg_miss_latency::total 15150.498583 # average ReadReq miss latency 59system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12786.142134 # average ReadReq mshr miss latency 60system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12786.142134 # average ReadReq mshr miss latency 61system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 62system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 63system.cpu.dcache.ReadReq_hits::cpu.inst 13401466 # number of ReadReq hits 64system.cpu.dcache.ReadReq_hits::total 13401466 # number of ReadReq hits 65system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7014438436 # number of ReadReq miss cycles 66system.cpu.dcache.ReadReq_miss_latency::total 7014438436 # number of ReadReq miss cycles 67system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.033394 # miss rate for ReadReq accesses 68system.cpu.dcache.ReadReq_miss_rate::total 0.033394 # miss rate for ReadReq accesses 69system.cpu.dcache.ReadReq_misses::cpu.inst 462984 # number of ReadReq misses 70system.cpu.dcache.ReadReq_misses::total 462984 # number of ReadReq misses 71system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 82872 # number of ReadReq MSHR hits 72system.cpu.dcache.ReadReq_mshr_hits::total 82872 # number of ReadReq MSHR hits 73system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4860166059 # number of ReadReq MSHR miss cycles 74system.cpu.dcache.ReadReq_mshr_miss_latency::total 4860166059 # number of ReadReq MSHR miss cycles 75system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.027416 # mshr miss rate for ReadReq accesses 76system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027416 # mshr miss rate for ReadReq accesses 77system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 380112 # number of ReadReq MSHR misses 78system.cpu.dcache.ReadReq_mshr_misses::total 380112 # number of ReadReq MSHR misses 79system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182581857500 # number of ReadReq MSHR uncacheable cycles 80system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182581857500 # number of ReadReq MSHR uncacheable cycles 81system.cpu.dcache.StoreCondReq_accesses::cpu.inst 247602 # number of StoreCondReq accesses(hits+misses) 82system.cpu.dcache.StoreCondReq_accesses::total 247602 # number of StoreCondReq accesses(hits+misses) 83system.cpu.dcache.StoreCondReq_hits::cpu.inst 247602 # number of StoreCondReq hits 84system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits 85system.cpu.dcache.WriteReq_accesses::cpu.inst 10222557 # number of WriteReq accesses(hits+misses) 86system.cpu.dcache.WriteReq_accesses::total 10222557 # number of WriteReq accesses(hits+misses) 87system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46293.122518 # average WriteReq miss latency 88system.cpu.dcache.WriteReq_avg_miss_latency::total 46293.122518 # average WriteReq miss latency 89system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 42586.604187 # average WriteReq mshr miss latency 90system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42586.604187 # average WriteReq mshr miss latency 91system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 92system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 93system.cpu.dcache.WriteReq_hits::cpu.inst 9749254 # number of WriteReq hits 94system.cpu.dcache.WriteReq_hits::total 9749254 # number of WriteReq hits 95system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21910673767 # number of WriteReq miss cycles 96system.cpu.dcache.WriteReq_miss_latency::total 21910673767 # number of WriteReq miss cycles 97system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.046300 # miss rate for WriteReq accesses 98system.cpu.dcache.WriteReq_miss_rate::total 0.046300 # miss rate for WriteReq accesses 99system.cpu.dcache.WriteReq_misses::cpu.inst 473303 # number of WriteReq misses 100system.cpu.dcache.WriteReq_misses::total 473303 # number of WriteReq misses 101system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 222786 # number of WriteReq MSHR hits 102system.cpu.dcache.WriteReq_mshr_hits::total 222786 # number of WriteReq MSHR hits 103system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10668668321 # number of WriteReq MSHR miss cycles 104system.cpu.dcache.WriteReq_mshr_miss_latency::total 10668668321 # number of WriteReq MSHR miss cycles 105system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.024506 # mshr miss rate for WriteReq accesses 106system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024506 # mshr miss rate for WriteReq accesses 107system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 250517 # number of WriteReq MSHR misses 108system.cpu.dcache.WriteReq_mshr_misses::total 250517 # number of WriteReq MSHR misses 109system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058222680 # number of WriteReq MSHR uncacheable cycles 110system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058222680 # number of WriteReq MSHR uncacheable cycles 111system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 112system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 113system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 114system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 115system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 116system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 117system.cpu.dcache.cache_copies 0 # number of cache copies performed 118system.cpu.dcache.demand_accesses::cpu.inst 24087007 # number of demand (read+write) accesses 119system.cpu.dcache.demand_accesses::total 24087007 # number of demand (read+write) accesses 120system.cpu.dcache.demand_avg_miss_latency::cpu.inst 30893.424989 # average overall miss latency 121system.cpu.dcache.demand_avg_miss_latency::total 30893.424989 # average overall miss latency 122system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24624.358188 # average overall mshr miss latency 123system.cpu.dcache.demand_avg_mshr_miss_latency::total 24624.358188 # average overall mshr miss latency 124system.cpu.dcache.demand_hits::cpu.inst 23150720 # number of demand (read+write) hits 125system.cpu.dcache.demand_hits::total 23150720 # number of demand (read+write) hits 126system.cpu.dcache.demand_miss_latency::cpu.inst 28925112203 # number of demand (read+write) miss cycles 127system.cpu.dcache.demand_miss_latency::total 28925112203 # number of demand (read+write) miss cycles 128system.cpu.dcache.demand_miss_rate::cpu.inst 0.038871 # miss rate for demand accesses 129system.cpu.dcache.demand_miss_rate::total 0.038871 # miss rate for demand accesses 130system.cpu.dcache.demand_misses::cpu.inst 936287 # number of demand (read+write) misses 131system.cpu.dcache.demand_misses::total 936287 # number of demand (read+write) misses 132system.cpu.dcache.demand_mshr_hits::cpu.inst 305658 # number of demand (read+write) MSHR hits 133system.cpu.dcache.demand_mshr_hits::total 305658 # number of demand (read+write) MSHR hits 134system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15528834380 # number of demand (read+write) MSHR miss cycles 135system.cpu.dcache.demand_mshr_miss_latency::total 15528834380 # number of demand (read+write) MSHR miss cycles 136system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.026181 # mshr miss rate for demand accesses 137system.cpu.dcache.demand_mshr_miss_rate::total 0.026181 # mshr miss rate for demand accesses 138system.cpu.dcache.demand_mshr_misses::cpu.inst 630629 # number of demand (read+write) MSHR misses 139system.cpu.dcache.demand_mshr_misses::total 630629 # number of demand (read+write) MSHR misses 140system.cpu.dcache.fast_writes 0 # number of fast writes performed 141system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 142system.cpu.dcache.overall_accesses::cpu.inst 24087007 # number of overall (read+write) accesses 143system.cpu.dcache.overall_accesses::total 24087007 # number of overall (read+write) accesses 144system.cpu.dcache.overall_avg_miss_latency::cpu.inst 30893.424989 # average overall miss latency 145system.cpu.dcache.overall_avg_miss_latency::total 30893.424989 # average overall miss latency 146system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24624.358188 # average overall mshr miss latency 147system.cpu.dcache.overall_avg_mshr_miss_latency::total 24624.358188 # average overall mshr miss latency 148system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 149system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 150system.cpu.dcache.overall_hits::cpu.inst 23150720 # number of overall hits 151system.cpu.dcache.overall_hits::total 23150720 # number of overall hits 152system.cpu.dcache.overall_miss_latency::cpu.inst 28925112203 # number of overall miss cycles 153system.cpu.dcache.overall_miss_latency::total 28925112203 # number of overall miss cycles 154system.cpu.dcache.overall_miss_rate::cpu.inst 0.038871 # miss rate for overall accesses 155system.cpu.dcache.overall_miss_rate::total 0.038871 # miss rate for overall accesses 156system.cpu.dcache.overall_misses::cpu.inst 936287 # number of overall misses 157system.cpu.dcache.overall_misses::total 936287 # number of overall misses 158system.cpu.dcache.overall_mshr_hits::cpu.inst 305658 # number of overall MSHR hits 159system.cpu.dcache.overall_mshr_hits::total 305658 # number of overall MSHR hits 160system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 15528834380 # number of overall MSHR miss cycles 161system.cpu.dcache.overall_mshr_miss_latency::total 15528834380 # number of overall MSHR miss cycles 162system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.026181 # mshr miss rate for overall accesses 163system.cpu.dcache.overall_mshr_miss_rate::total 0.026181 # mshr miss rate for overall accesses 164system.cpu.dcache.overall_mshr_misses::cpu.inst 630629 # number of overall MSHR misses 165system.cpu.dcache.overall_mshr_misses::total 630629 # number of overall MSHR misses 166system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208640080180 # number of overall MSHR uncacheable cycles 167system.cpu.dcache.overall_mshr_uncacheable_latency::total 208640080180 # number of overall MSHR uncacheable cycles 168system.cpu.dcache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id 169system.cpu.dcache.tags.age_task_id_blocks_1024::1 341 # Occupied blocks per task id 170system.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id 171system.cpu.dcache.tags.avg_refs 37.024295 # Average number of references to valid blocks. 172system.cpu.dcache.tags.data_accesses 98967296 # Number of data accesses 173system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959208 # Average occupied blocks per requestor 174system.cpu.dcache.tags.occ_percent::cpu.inst 0.999920 # Average percentage of cache occupancy 175system.cpu.dcache.tags.occ_percent::total 0.999920 # Average percentage of cache occupancy 176system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 177system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 178system.cpu.dcache.tags.replacements 637936 # number of replacements 179system.cpu.dcache.tags.sampled_refs 638448 # Sample count of references to valid blocks. 180system.cpu.dcache.tags.tag_accesses 98967296 # Number of tag accesses 181system.cpu.dcache.tags.tagsinuse 511.959208 # Cycle average of tags in use 182system.cpu.dcache.tags.total_refs 23638087 # Total number of references to valid blocks. 183system.cpu.dcache.tags.warmup_cycle 227414250 # Cycle when the warmup percentage was hit. 184system.cpu.dcache.writebacks::writebacks 603000 # number of writebacks 185system.cpu.dcache.writebacks::total 603000 # number of writebacks 186system.cpu.discardedOps 3607979 # Number of ops (including micro ops) which were discarded before commit 187system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 188system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 189system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 190system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 191system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 192system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 193system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 194system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 195system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 196system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 197system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 198system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 199system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 200system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 201system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 202system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 203system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 204system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 205system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 206system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 207system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 208system.cpu.dtb.accesses 26805017 # DTB accesses 209system.cpu.dtb.align_faults 1584 # Number of TLB faults due to alignment restrictions 210system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 211system.cpu.dtb.flush_entries 3457 # Number of entries that have been flushed from TLB 212system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 213system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 214system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 215system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 216system.cpu.dtb.hits 26758984 # DTB hits 217system.cpu.dtb.inst_accesses 0 # ITB inst accesses 218system.cpu.dtb.inst_hits 0 # ITB inst hits 219system.cpu.dtb.inst_misses 0 # ITB inst misses 220system.cpu.dtb.misses 46033 # DTB misses 221system.cpu.dtb.perms_faults 524 # Number of TLB faults due to permissions restrictions 222system.cpu.dtb.prefetch_faults 266 # Number of TLB faults due to prefetch 223system.cpu.dtb.read_accesses 15458164 # DTB read accesses 224system.cpu.dtb.read_hits 15416095 # DTB read hits 225system.cpu.dtb.read_misses 42069 # DTB read misses 226system.cpu.dtb.write_accesses 11346853 # DTB write accesses 227system.cpu.dtb.write_hits 11342889 # DTB write hits 228system.cpu.dtb.write_misses 3964 # DTB write misses 229system.cpu.icache.ReadReq_accesses::cpu.inst 23332180 # number of ReadReq accesses(hits+misses) 230system.cpu.icache.ReadReq_accesses::total 23332180 # number of ReadReq accesses(hits+misses) 231system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13520.944355 # average ReadReq miss latency 232system.cpu.icache.ReadReq_avg_miss_latency::total 13520.944355 # average ReadReq miss latency 233system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11517.182541 # average ReadReq mshr miss latency 234system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11517.182541 # average ReadReq mshr miss latency 235system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 236system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 237system.cpu.icache.ReadReq_hits::cpu.inst 21786211 # number of ReadReq hits 238system.cpu.icache.ReadReq_hits::total 21786211 # number of ReadReq hits 239system.cpu.icache.ReadReq_miss_latency::cpu.inst 20902960824 # number of ReadReq miss cycles 240system.cpu.icache.ReadReq_miss_latency::total 20902960824 # number of ReadReq miss cycles 241system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.066259 # miss rate for ReadReq accesses 242system.cpu.icache.ReadReq_miss_rate::total 0.066259 # miss rate for ReadReq accesses 243system.cpu.icache.ReadReq_misses::cpu.inst 1545969 # number of ReadReq misses 244system.cpu.icache.ReadReq_misses::total 1545969 # number of ReadReq misses 245system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17805207176 # number of ReadReq MSHR miss cycles 246system.cpu.icache.ReadReq_mshr_miss_latency::total 17805207176 # number of ReadReq MSHR miss cycles 247system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066259 # mshr miss rate for ReadReq accesses 248system.cpu.icache.ReadReq_mshr_miss_rate::total 0.066259 # mshr miss rate for ReadReq accesses 249system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1545969 # number of ReadReq MSHR misses 250system.cpu.icache.ReadReq_mshr_misses::total 1545969 # number of ReadReq MSHR misses 251system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 172412750 # number of ReadReq MSHR uncacheable cycles 252system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 172412750 # number of ReadReq MSHR uncacheable cycles 253system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 254system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 255system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 256system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 257system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 258system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 259system.cpu.icache.cache_copies 0 # number of cache copies performed 260system.cpu.icache.demand_accesses::cpu.inst 23332180 # number of demand (read+write) accesses 261system.cpu.icache.demand_accesses::total 23332180 # number of demand (read+write) accesses 262system.cpu.icache.demand_avg_miss_latency::cpu.inst 13520.944355 # average overall miss latency 263system.cpu.icache.demand_avg_miss_latency::total 13520.944355 # average overall miss latency 264system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11517.182541 # average overall mshr miss latency 265system.cpu.icache.demand_avg_mshr_miss_latency::total 11517.182541 # average overall mshr miss latency 266system.cpu.icache.demand_hits::cpu.inst 21786211 # number of demand (read+write) hits 267system.cpu.icache.demand_hits::total 21786211 # number of demand (read+write) hits 268system.cpu.icache.demand_miss_latency::cpu.inst 20902960824 # number of demand (read+write) miss cycles 269system.cpu.icache.demand_miss_latency::total 20902960824 # number of demand (read+write) miss cycles 270system.cpu.icache.demand_miss_rate::cpu.inst 0.066259 # miss rate for demand accesses 271system.cpu.icache.demand_miss_rate::total 0.066259 # miss rate for demand accesses 272system.cpu.icache.demand_misses::cpu.inst 1545969 # number of demand (read+write) misses 273system.cpu.icache.demand_misses::total 1545969 # number of demand (read+write) misses 274system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17805207176 # number of demand (read+write) MSHR miss cycles 275system.cpu.icache.demand_mshr_miss_latency::total 17805207176 # number of demand (read+write) MSHR miss cycles 276system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066259 # mshr miss rate for demand accesses 277system.cpu.icache.demand_mshr_miss_rate::total 0.066259 # mshr miss rate for demand accesses 278system.cpu.icache.demand_mshr_misses::cpu.inst 1545969 # number of demand (read+write) MSHR misses 279system.cpu.icache.demand_mshr_misses::total 1545969 # number of demand (read+write) MSHR misses 280system.cpu.icache.fast_writes 0 # number of fast writes performed 281system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 282system.cpu.icache.overall_accesses::cpu.inst 23332180 # number of overall (read+write) accesses 283system.cpu.icache.overall_accesses::total 23332180 # number of overall (read+write) accesses 284system.cpu.icache.overall_avg_miss_latency::cpu.inst 13520.944355 # average overall miss latency 285system.cpu.icache.overall_avg_miss_latency::total 13520.944355 # average overall miss latency 286system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11517.182541 # average overall mshr miss latency 287system.cpu.icache.overall_avg_mshr_miss_latency::total 11517.182541 # average overall mshr miss latency 288system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 289system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 290system.cpu.icache.overall_hits::cpu.inst 21786211 # number of overall hits 291system.cpu.icache.overall_hits::total 21786211 # number of overall hits 292system.cpu.icache.overall_miss_latency::cpu.inst 20902960824 # number of overall miss cycles 293system.cpu.icache.overall_miss_latency::total 20902960824 # number of overall miss cycles 294system.cpu.icache.overall_miss_rate::cpu.inst 0.066259 # miss rate for overall accesses 295system.cpu.icache.overall_miss_rate::total 0.066259 # miss rate for overall accesses 296system.cpu.icache.overall_misses::cpu.inst 1545969 # number of overall misses 297system.cpu.icache.overall_misses::total 1545969 # number of overall misses 298system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17805207176 # number of overall MSHR miss cycles 299system.cpu.icache.overall_mshr_miss_latency::total 17805207176 # number of overall MSHR miss cycles 300system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066259 # mshr miss rate for overall accesses 301system.cpu.icache.overall_mshr_miss_rate::total 0.066259 # mshr miss rate for overall accesses 302system.cpu.icache.overall_mshr_misses::cpu.inst 1545969 # number of overall MSHR misses 303system.cpu.icache.overall_mshr_misses::total 1545969 # number of overall MSHR misses 304system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 172412750 # number of overall MSHR uncacheable cycles 305system.cpu.icache.overall_mshr_uncacheable_latency::total 172412750 # number of overall MSHR uncacheable cycles 306system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 307system.cpu.icache.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id 308system.cpu.icache.tags.age_task_id_blocks_1024::2 181 # Occupied blocks per task id 309system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 310system.cpu.icache.tags.avg_refs 14.092278 # Average number of references to valid blocks. 311system.cpu.icache.tags.data_accesses 24878148 # Number of data accesses 312system.cpu.icache.tags.occ_blocks::cpu.inst 511.467492 # Average occupied blocks per requestor 313system.cpu.icache.tags.occ_percent::cpu.inst 0.998960 # Average percentage of cache occupancy 314system.cpu.icache.tags.occ_percent::total 0.998960 # Average percentage of cache occupancy 315system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 316system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 317system.cpu.icache.tags.replacements 1545456 # number of replacements 318system.cpu.icache.tags.sampled_refs 1545968 # Sample count of references to valid blocks. 319system.cpu.icache.tags.tag_accesses 24878148 # Number of tag accesses 320system.cpu.icache.tags.tagsinuse 511.467492 # Cycle average of tags in use 321system.cpu.icache.tags.total_refs 21786211 # Total number of references to valid blocks. 322system.cpu.icache.tags.warmup_cycle 10068892000 # Cycle when the warmup percentage was hit. 323system.cpu.idleCycles 106196788 # Total number of cycles that the CPU has spent unscheduled due to idling 324system.cpu.ipc 0.105024 # IPC: instructions per cycle 325system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 326system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 327system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 328system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 329system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 330system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 331system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 332system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 333system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 334system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 335system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 336system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 337system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 338system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 339system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 340system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 341system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 342system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 343system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 344system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 345system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 346system.cpu.itb.accesses 23345804 # DTB accesses 347system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 348system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 349system.cpu.itb.flush_entries 2396 # Number of entries that have been flushed from TLB 350system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 351system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 352system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 353system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 354system.cpu.itb.hits 23336489 # DTB hits 355system.cpu.itb.inst_accesses 23345804 # ITB inst accesses 356system.cpu.itb.inst_hits 23336489 # ITB inst hits 357system.cpu.itb.inst_misses 9315 # ITB inst misses 358system.cpu.itb.misses 9315 # DTB misses 359system.cpu.itb.perms_faults 4052 # Number of TLB faults due to permissions restrictions 360system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 361system.cpu.itb.read_accesses 0 # DTB read accesses 362system.cpu.itb.read_hits 0 # DTB read hits 363system.cpu.itb.read_misses 0 # DTB read misses 364system.cpu.itb.write_accesses 0 # DTB write accesses 365system.cpu.itb.write_hits 0 # DTB write hits 366system.cpu.itb.write_misses 0 # DTB write misses 367system.cpu.kern.inst.arm 0 # number of arm instructions executed 368system.cpu.kern.inst.quiesce 82977 # number of quiesce instructions executed 369system.cpu.l2cache.ReadExReq_accesses::cpu.inst 247542 # number of ReadExReq accesses(hits+misses) 370system.cpu.l2cache.ReadExReq_accesses::total 247542 # number of ReadExReq accesses(hits+misses) 371system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69059.848663 # average ReadExReq miss latency 372system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69059.848663 # average ReadExReq miss latency 373system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56515.321009 # average ReadExReq mshr miss latency 374system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56515.321009 # average ReadExReq mshr miss latency 375system.cpu.l2cache.ReadExReq_hits::cpu.inst 114197 # number of ReadExReq hits 376system.cpu.l2cache.ReadExReq_hits::total 114197 # number of ReadExReq hits 377system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9208785520 # number of ReadExReq miss cycles 378system.cpu.l2cache.ReadExReq_miss_latency::total 9208785520 # number of ReadExReq miss cycles 379system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.538676 # miss rate for ReadExReq accesses 380system.cpu.l2cache.ReadExReq_miss_rate::total 0.538676 # miss rate for ReadExReq accesses 381system.cpu.l2cache.ReadExReq_misses::cpu.inst 133345 # number of ReadExReq misses 382system.cpu.l2cache.ReadExReq_misses::total 133345 # number of ReadExReq misses 383system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7536035480 # number of ReadExReq MSHR miss cycles 384system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7536035480 # number of ReadExReq MSHR miss cycles 385system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.538676 # mshr miss rate for ReadExReq accesses 386system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.538676 # mshr miss rate for ReadExReq accesses 387system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 133345 # number of ReadExReq MSHR misses 388system.cpu.l2cache.ReadExReq_mshr_misses::total 133345 # number of ReadExReq MSHR misses 389system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52818 # number of ReadReq accesses(hits+misses) 390system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11330 # number of ReadReq accesses(hits+misses) 391system.cpu.l2cache.ReadReq_accesses::cpu.inst 1934916 # number of ReadReq accesses(hits+misses) 392system.cpu.l2cache.ReadReq_accesses::total 1999064 # number of ReadReq accesses(hits+misses) 393system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85107.142857 # average ReadReq miss latency 394system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency 395system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71955.193483 # average ReadReq miss latency 396system.cpu.l2cache.ReadReq_avg_miss_latency::total 71966.894361 # average ReadReq miss latency 397system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72773.809524 # average ReadReq mshr miss latency 398system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency 399system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59447.036018 # average ReadReq mshr miss latency 400system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59458.945900 # average ReadReq mshr miss latency 401system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 402system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 403system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52797 # number of ReadReq hits 404system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11328 # number of ReadReq hits 405system.cpu.l2cache.ReadReq_hits::cpu.inst 1910857 # number of ReadReq hits 406system.cpu.l2cache.ReadReq_hits::total 1974982 # number of ReadReq hits 407system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1787250 # number of ReadReq miss cycles 408system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles 409system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1731170000 # number of ReadReq miss cycles 410system.cpu.l2cache.ReadReq_miss_latency::total 1733106750 # number of ReadReq miss cycles 411system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000398 # miss rate for ReadReq accesses 412system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000177 # miss rate for ReadReq accesses 413system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012434 # miss rate for ReadReq accesses 414system.cpu.l2cache.ReadReq_miss_rate::total 0.012047 # miss rate for ReadReq accesses 415system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses 416system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 417system.cpu.l2cache.ReadReq_misses::cpu.inst 24059 # number of ReadReq misses 418system.cpu.l2cache.ReadReq_misses::total 24082 # number of ReadReq misses 419system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits 420system.cpu.l2cache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits 421system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1528250 # number of ReadReq MSHR miss cycles 422system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles 423system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1426015500 # number of ReadReq MSHR miss cycles 424system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1427668750 # number of ReadReq MSHR miss cycles 425system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000398 # mshr miss rate for ReadReq accesses 426system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000177 # mshr miss rate for ReadReq accesses 427system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012397 # mshr miss rate for ReadReq accesses 428system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012011 # mshr miss rate for ReadReq accesses 429system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses 430system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 431system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 23988 # number of ReadReq MSHR misses 432system.cpu.l2cache.ReadReq_mshr_misses::total 24011 # number of ReadReq MSHR misses 433system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 167311975000 # number of ReadReq MSHR uncacheable cycles 434system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167311975000 # number of ReadReq MSHR uncacheable cycles 435system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2976 # number of UpgradeReq accesses(hits+misses) 436system.cpu.l2cache.UpgradeReq_accesses::total 2976 # number of UpgradeReq accesses(hits+misses) 437system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 126.265763 # average UpgradeReq miss latency 438system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 126.265763 # average UpgradeReq miss latency 439system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10004.558983 # average UpgradeReq mshr miss latency 440system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10004.558983 # average UpgradeReq mshr miss latency 441system.cpu.l2cache.UpgradeReq_hits::cpu.inst 26 # number of UpgradeReq hits 442system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 443system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 372484 # number of UpgradeReq miss cycles 444system.cpu.l2cache.UpgradeReq_miss_latency::total 372484 # number of UpgradeReq miss cycles 445system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.991263 # miss rate for UpgradeReq accesses 446system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991263 # miss rate for UpgradeReq accesses 447system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2950 # number of UpgradeReq misses 448system.cpu.l2cache.UpgradeReq_misses::total 2950 # number of UpgradeReq misses 449system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 29513449 # number of UpgradeReq MSHR miss cycles 450system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29513449 # number of UpgradeReq MSHR miss cycles 451system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.991263 # mshr miss rate for UpgradeReq accesses 452system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991263 # mshr miss rate for UpgradeReq accesses 453system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2950 # number of UpgradeReq MSHR misses 454system.cpu.l2cache.UpgradeReq_mshr_misses::total 2950 # number of UpgradeReq MSHR misses 455system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 456system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 457system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 16707831820 # number of WriteReq MSHR uncacheable cycles 458system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16707831820 # number of WriteReq MSHR uncacheable cycles 459system.cpu.l2cache.Writeback_accesses::writebacks 603000 # number of Writeback accesses(hits+misses) 460system.cpu.l2cache.Writeback_accesses::total 603000 # number of Writeback accesses(hits+misses) 461system.cpu.l2cache.Writeback_hits::writebacks 603000 # number of Writeback hits 462system.cpu.l2cache.Writeback_hits::total 603000 # number of Writeback hits 463system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 464system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 465system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 466system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 467system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 468system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 469system.cpu.l2cache.cache_copies 0 # number of cache copies performed 470system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52818 # number of demand (read+write) accesses 471system.cpu.l2cache.demand_accesses::cpu.itb.walker 11330 # number of demand (read+write) accesses 472system.cpu.l2cache.demand_accesses::cpu.inst 2182458 # number of demand (read+write) accesses 473system.cpu.l2cache.demand_accesses::total 2246606 # number of demand (read+write) accesses 474system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85107.142857 # average overall miss latency 475system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency 476system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69502.398414 # average overall miss latency 477system.cpu.l2cache.demand_avg_miss_latency::total 69504.546679 # average overall miss latency 478system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72773.809524 # average overall mshr miss latency 479system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 480system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56962.309115 # average overall mshr miss latency 481system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56964.489629 # average overall mshr miss latency 482system.cpu.l2cache.demand_hits::cpu.dtb.walker 52797 # number of demand (read+write) hits 483system.cpu.l2cache.demand_hits::cpu.itb.walker 11328 # number of demand (read+write) hits 484system.cpu.l2cache.demand_hits::cpu.inst 2025054 # number of demand (read+write) hits 485system.cpu.l2cache.demand_hits::total 2089179 # number of demand (read+write) hits 486system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1787250 # number of demand (read+write) miss cycles 487system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles 488system.cpu.l2cache.demand_miss_latency::cpu.inst 10939955520 # number of demand (read+write) miss cycles 489system.cpu.l2cache.demand_miss_latency::total 10941892270 # number of demand (read+write) miss cycles 490system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000398 # miss rate for demand accesses 491system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000177 # miss rate for demand accesses 492system.cpu.l2cache.demand_miss_rate::cpu.inst 0.072122 # miss rate for demand accesses 493system.cpu.l2cache.demand_miss_rate::total 0.070073 # miss rate for demand accesses 494system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses 495system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 496system.cpu.l2cache.demand_misses::cpu.inst 157404 # number of demand (read+write) misses 497system.cpu.l2cache.demand_misses::total 157427 # number of demand (read+write) misses 498system.cpu.l2cache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits 499system.cpu.l2cache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits 500system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1528250 # number of demand (read+write) MSHR miss cycles 501system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 502system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8962050980 # number of demand (read+write) MSHR miss cycles 503system.cpu.l2cache.demand_mshr_miss_latency::total 8963704230 # number of demand (read+write) MSHR miss cycles 504system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000398 # mshr miss rate for demand accesses 505system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000177 # mshr miss rate for demand accesses 506system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.072090 # mshr miss rate for demand accesses 507system.cpu.l2cache.demand_mshr_miss_rate::total 0.070042 # mshr miss rate for demand accesses 508system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses 509system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 510system.cpu.l2cache.demand_mshr_misses::cpu.inst 157333 # number of demand (read+write) MSHR misses 511system.cpu.l2cache.demand_mshr_misses::total 157356 # number of demand (read+write) MSHR misses 512system.cpu.l2cache.fast_writes 0 # number of fast writes performed 513system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 514system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52818 # number of overall (read+write) accesses 515system.cpu.l2cache.overall_accesses::cpu.itb.walker 11330 # number of overall (read+write) accesses 516system.cpu.l2cache.overall_accesses::cpu.inst 2182458 # number of overall (read+write) accesses 517system.cpu.l2cache.overall_accesses::total 2246606 # number of overall (read+write) accesses 518system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85107.142857 # average overall miss latency 519system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency 520system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69502.398414 # average overall miss latency 521system.cpu.l2cache.overall_avg_miss_latency::total 69504.546679 # average overall miss latency 522system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72773.809524 # average overall mshr miss latency 523system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 524system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56962.309115 # average overall mshr miss latency 525system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56964.489629 # average overall mshr miss latency 526system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 527system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 528system.cpu.l2cache.overall_hits::cpu.dtb.walker 52797 # number of overall hits 529system.cpu.l2cache.overall_hits::cpu.itb.walker 11328 # number of overall hits 530system.cpu.l2cache.overall_hits::cpu.inst 2025054 # number of overall hits 531system.cpu.l2cache.overall_hits::total 2089179 # number of overall hits 532system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1787250 # number of overall miss cycles 533system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles 534system.cpu.l2cache.overall_miss_latency::cpu.inst 10939955520 # number of overall miss cycles 535system.cpu.l2cache.overall_miss_latency::total 10941892270 # number of overall miss cycles 536system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000398 # miss rate for overall accesses 537system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000177 # miss rate for overall accesses 538system.cpu.l2cache.overall_miss_rate::cpu.inst 0.072122 # miss rate for overall accesses 539system.cpu.l2cache.overall_miss_rate::total 0.070073 # miss rate for overall accesses 540system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses 541system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 542system.cpu.l2cache.overall_misses::cpu.inst 157404 # number of overall misses 543system.cpu.l2cache.overall_misses::total 157427 # number of overall misses 544system.cpu.l2cache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits 545system.cpu.l2cache.overall_mshr_hits::total 71 # number of overall MSHR hits 546system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1528250 # number of overall MSHR miss cycles 547system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles 548system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8962050980 # number of overall MSHR miss cycles 549system.cpu.l2cache.overall_mshr_miss_latency::total 8963704230 # number of overall MSHR miss cycles 550system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000398 # mshr miss rate for overall accesses 551system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000177 # mshr miss rate for overall accesses 552system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.072090 # mshr miss rate for overall accesses 553system.cpu.l2cache.overall_mshr_miss_rate::total 0.070042 # mshr miss rate for overall accesses 554system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses 555system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 556system.cpu.l2cache.overall_mshr_misses::cpu.inst 157333 # number of overall MSHR misses 557system.cpu.l2cache.overall_mshr_misses::total 157356 # number of overall MSHR misses 558system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 184019806820 # number of overall MSHR uncacheable cycles 559system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184019806820 # number of overall MSHR uncacheable cycles 560system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 561system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id 562system.cpu.l2cache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id 563system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2431 # Occupied blocks per task id 564system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6707 # Occupied blocks per task id 565system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56131 # Occupied blocks per task id 566system.cpu.l2cache.tags.avg_refs 18.629243 # Average number of references to valid blocks. 567system.cpu.l2cache.tags.data_accesses 23223720 # Number of data accesses 568system.cpu.l2cache.tags.occ_blocks::writebacks 36351.350875 # Average occupied blocks per requestor 569system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 12.813342 # Average occupied blocks per requestor 570system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000576 # Average occupied blocks per requestor 571system.cpu.l2cache.tags.occ_blocks::cpu.inst 15263.969553 # Average occupied blocks per requestor 572system.cpu.l2cache.tags.occ_percent::writebacks 0.554678 # Average percentage of cache occupancy 573system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000196 # Average percentage of cache occupancy 574system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 575system.cpu.l2cache.tags.occ_percent::cpu.inst 0.232910 # Average percentage of cache occupancy 576system.cpu.l2cache.tags.occ_percent::total 0.787783 # Average percentage of cache occupancy 577system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 578system.cpu.l2cache.tags.occ_task_id_blocks::1024 65377 # Occupied blocks per task id 579system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id 580system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997574 # Percentage of cache occupancy per task id 581system.cpu.l2cache.tags.replacements 65515 # number of replacements 582system.cpu.l2cache.tags.sampled_refs 130905 # Sample count of references to valid blocks. 583system.cpu.l2cache.tags.tag_accesses 23223720 # Number of tag accesses 584system.cpu.l2cache.tags.tagsinuse 51628.134347 # Cycle average of tags in use 585system.cpu.l2cache.tags.total_refs 2438661 # Total number of references to valid blocks. 586system.cpu.l2cache.tags.warmup_cycle 2525287108000 # Cycle when the warmup percentage was hit. 587system.cpu.l2cache.writebacks::writebacks 59837 # number of writebacks 588system.cpu.l2cache.writebacks::total 59837 # number of writebacks 589system.cpu.numCycles 576943440 # number of cpu cycles simulated 590system.cpu.numFetchSuspends 77491 # Number of times Execute suspended instruction fetching 591system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 592system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 593system.cpu.quiesceCycles 4560354752 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 594system.cpu.tickCycles 470746652 # Number of cycles that the CPU actually ticked 595system.cpu.toL2Bus.data_through_bus 184089158 # Total data (bytes) 596system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3094634 # Packet count per connected master and slave (bytes) 597system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5780828 # Packet count per connected master and slave (bytes) 598system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 29817 # Packet count per connected master and slave (bytes) 599system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 125263 # Packet count per connected master and slave (bytes) 600system.cpu.toL2Bus.pkt_count::total 9030542 # Packet count per connected master and slave (bytes) 601system.cpu.toL2Bus.reqLayer0.occupancy 3400418424 # Layer occupancy (ticks) 602system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 603system.cpu.toL2Bus.respLayer0.occupancy 2325892574 # Layer occupancy (ticks) 604system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 605system.cpu.toL2Bus.respLayer1.occupancy 2551470440 # Layer occupancy (ticks) 606system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 607system.cpu.toL2Bus.respLayer2.occupancy 18491990 # Layer occupancy (ticks) 608system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 609system.cpu.toL2Bus.respLayer3.occupancy 72446749 # Layer occupancy (ticks) 610system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 611system.cpu.toL2Bus.snoop_data_through_bus 232512 # Total snoop data (bytes) 612system.cpu.toL2Bus.throughput 71784989 # Throughput (bytes/s) 613system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 98965568 # Cumulative packet size per connected master and slave (bytes) 614system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84866998 # Cumulative packet size per connected master and slave (bytes) 615system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 45320 # Cumulative packet size per connected master and slave (bytes) 616system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 211272 # Cumulative packet size per connected master and slave (bytes) 617system.cpu.toL2Bus.tot_pkt_size::total 184089158 # Cumulative packet size per connected master and slave (bytes) 618system.cpu.toL2Bus.trans_dist::ReadReq 3214260 # Transaction distribution 619system.cpu.toL2Bus.trans_dist::ReadResp 3214259 # Transaction distribution 620system.cpu.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution 621system.cpu.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution 622system.cpu.toL2Bus.trans_dist::Writeback 603000 # Transaction distribution 623system.cpu.toL2Bus.trans_dist::UpgradeReq 2976 # Transaction distribution 624system.cpu.toL2Bus.trans_dist::UpgradeResp 2976 # Transaction distribution 625system.cpu.toL2Bus.trans_dist::ReadExReq 247542 # Transaction distribution 626system.cpu.toL2Bus.trans_dist::ReadExResp 247542 # Transaction distribution 627system.cpu_clk_domain.clock 500 # Clock period in ticks 628system.iobus.data_through_bus 123501026 # Total data (bytes) 629system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) 630system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) 631system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 524 # Packet count per connected master and slave (bytes) 632system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) 633system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 634system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 635system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 636system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 637system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 638system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 639system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 640system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 641system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 642system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 643system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 644system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 645system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 646system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 647system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 648system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 649system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 650system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 651system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 652system.iobus.pkt_count_system.bridge.master::total 2383066 # Packet count per connected master and slave (bytes) 653system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) 654system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) 655system.iobus.pkt_count::total 32660698 # Packet count per connected master and slave (bytes) 656system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) 657system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 658system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) 659system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 660system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 661system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 662system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 663system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 664system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 665system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 666system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 667system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 668system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 669system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 670system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 671system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 672system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 673system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 674system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 675system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 676system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 677system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 678system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 679system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 680system.iobus.reqLayer2.occupancy 524000 # Layer occupancy (ticks) 681system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 682system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 683system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 684system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 685system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 686system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 687system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 688system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 689system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 690system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) 691system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 692system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks) 693system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 694system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 695system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 696system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 697system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 698system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) 699system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 700system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 701system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 702system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 703system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 704system.iobus.respLayer0.occupancy 2374888000 # Layer occupancy (ticks) 705system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 706system.iobus.respLayer1.occupancy 38216821000 # Layer occupancy (ticks) 707system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 708system.iobus.throughput 48098087 # Throughput (bytes/s) 709system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) 710system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) 711system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1048 # Cumulative packet size per connected master and slave (bytes) 712system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) 713system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 714system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 715system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 716system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 717system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 718system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 719system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 720system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 721system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 722system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 723system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 724system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 725system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 726system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 727system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 728system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 729system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 730system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 731system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 732system.iobus.tot_pkt_size_system.bridge.master::total 2390498 # Cumulative packet size per connected master and slave (bytes) 733system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) 734system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) 735system.iobus.tot_pkt_size::total 123501026 # Cumulative packet size per connected master and slave (bytes) 736system.iobus.trans_dist::ReadReq 16322171 # Transaction distribution 737system.iobus.trans_dist::ReadResp 16322171 # Transaction distribution 738system.iobus.trans_dist::WriteReq 8178 # Transaction distribution 739system.iobus.trans_dist::WriteResp 8178 # Transaction distribution 740system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 741system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 742system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1738144017000 # number of ReadReq MSHR uncacheable cycles 743system.iocache.ReadReq_mshr_uncacheable_latency::total 1738144017000 # number of ReadReq MSHR uncacheable cycles 744system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 745system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 746system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 747system.iocache.blocked::no_targets 0 # number of cycles access was blocked 748system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 749system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 750system.iocache.cache_copies 0 # number of cache copies performed 751system.iocache.fast_writes 0 # number of fast writes performed 752system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 753system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 754system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 755system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1738144017000 # number of overall MSHR uncacheable cycles 756system.iocache.overall_mshr_uncacheable_latency::total 1738144017000 # number of overall MSHR uncacheable cycles 757system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 758system.iocache.tags.data_accesses 0 # Number of data accesses 759system.iocache.tags.replacements 0 # number of replacements 760system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 761system.iocache.tags.tag_accesses 0 # Number of tag accesses 762system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 763system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 764system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 765system.membus.data_through_bus 140463478 # Total data (bytes) 766system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383066 # Packet count per connected master and slave (bytes) 767system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 8 # Packet count per connected master and slave (bytes) 768system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3800 # Packet count per connected master and slave (bytes) 769system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) 770system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893209 # Packet count per connected master and slave (bytes) 771system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280085 # Packet count per connected master and slave (bytes) 772system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) 773system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) 774system.membus.pkt_count::total 34557717 # Packet count per connected master and slave (bytes) 775system.membus.reqLayer0.occupancy 1731044000 # Layer occupancy (ticks) 776system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 777system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) 778system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 779system.membus.reqLayer2.occupancy 3530500 # Layer occupancy (ticks) 780system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 781system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) 782system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 783system.membus.reqLayer6.occupancy 17560934000 # Layer occupancy (ticks) 784system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) 785system.membus.respLayer1.occupancy 4805612001 # Layer occupancy (ticks) 786system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 787system.membus.respLayer2.occupancy 37417137000 # Layer occupancy (ticks) 788system.membus.respLayer2.utilization 1.5 # Layer utilization (%) 789system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 790system.membus.throughput 54704199 # Throughput (bytes/s) 791system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390498 # Cumulative packet size per connected master and slave (bytes) 792system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 256 # Cumulative packet size per connected master and slave (bytes) 793system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7600 # Cumulative packet size per connected master and slave (bytes) 794system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) 795system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16954592 # Cumulative packet size per connected master and slave (bytes) 796system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19352950 # Cumulative packet size per connected master and slave (bytes) 797system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) 798system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) 799system.membus.tot_pkt_size::total 140463478 # Cumulative packet size per connected master and slave (bytes) 800system.membus.trans_dist::ReadReq 16349280 # Transaction distribution 801system.membus.trans_dist::ReadResp 16349280 # Transaction distribution 802system.membus.trans_dist::WriteReq 763365 # Transaction distribution 803system.membus.trans_dist::WriteResp 763365 # Transaction distribution 804system.membus.trans_dist::Writeback 59837 # Transaction distribution 805system.membus.trans_dist::UpgradeReq 4680 # Transaction distribution 806system.membus.trans_dist::UpgradeResp 4680 # Transaction distribution 807system.membus.trans_dist::ReadExReq 131615 # Transaction distribution 808system.membus.trans_dist::ReadExResp 131615 # Transaction distribution 809system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 810system.physmem.avgGap 159378.28 # Average gap between requests 811system.physmem.avgMemAccLat 44638.69 # Average memory access latency per DRAM burst 812system.physmem.avgQLat 25888.69 # Average queueing delay per DRAM burst 813system.physmem.avgRdBW 381.23 # Average DRAM read bandwidth in MiByte/s 814system.physmem.avgRdBWSys 51.10 # Average system read bandwidth in MiByte/s 815system.physmem.avgRdQLen 6.57 # Average read queue length when enqueuing 816system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s 817system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s 818system.physmem.avgWrQLen 25.93 # Average write queue length when enqueuing 819system.physmem.busUtil 3.00 # Data bus utilization in percentage 820system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads 821system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 822system.physmem.bw_inst_read::cpu.inst 396534 # Instruction read bandwidth from this memory (bytes/s) 823system.physmem.bw_inst_read::total 396534 # Instruction read bandwidth from this memory (bytes/s) 824system.physmem.bw_read::realview.clcd 47167096 # Total read bandwidth from this memory (bytes/s) 825system.physmem.bw_read::cpu.dtb.walker 523 # Total read bandwidth from this memory (bytes/s) 826system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) 827system.physmem.bw_read::cpu.inst 3936408 # Total read bandwidth from this memory (bytes/s) 828system.physmem.bw_read::total 51104078 # Total read bandwidth from this memory (bytes/s) 829system.physmem.bw_total::writebacks 1491444 # Total bandwidth to/from this memory (bytes/s) 830system.physmem.bw_total::realview.clcd 47167096 # Total bandwidth to/from this memory (bytes/s) 831system.physmem.bw_total::cpu.dtb.walker 523 # Total bandwidth to/from this memory (bytes/s) 832system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) 833system.physmem.bw_total::cpu.inst 5111032 # Total bandwidth to/from this memory (bytes/s) 834system.physmem.bw_total::total 53770146 # Total bandwidth to/from this memory (bytes/s) 835system.physmem.bw_write::writebacks 1491444 # Write bandwidth from this memory (bytes/s) 836system.physmem.bw_write::cpu.inst 1174624 # Write bandwidth from this memory (bytes/s) 837system.physmem.bw_write::total 2666068 # Write bandwidth from this memory (bytes/s) 838system.physmem.bytesPerActivate::samples 1015061 # Bytes accessed per row activation 839system.physmem.bytesPerActivate::mean 971.117866 # Bytes accessed per row activation 840system.physmem.bytesPerActivate::gmean 904.579267 # Bytes accessed per row activation 841system.physmem.bytesPerActivate::stdev 205.091565 # Bytes accessed per row activation 842system.physmem.bytesPerActivate::0-127 22463 2.21% 2.21% # Bytes accessed per row activation 843system.physmem.bytesPerActivate::128-255 22781 2.24% 4.46% # Bytes accessed per row activation 844system.physmem.bytesPerActivate::256-383 8586 0.85% 5.30% # Bytes accessed per row activation 845system.physmem.bytesPerActivate::384-511 2483 0.24% 5.55% # Bytes accessed per row activation 846system.physmem.bytesPerActivate::512-639 2672 0.26% 5.81% # Bytes accessed per row activation 847system.physmem.bytesPerActivate::640-767 1833 0.18% 5.99% # Bytes accessed per row activation 848system.physmem.bytesPerActivate::768-895 8618 0.85% 6.84% # Bytes accessed per row activation 849system.physmem.bytesPerActivate::896-1023 926 0.09% 6.93% # Bytes accessed per row activation 850system.physmem.bytesPerActivate::1024-1151 944699 93.07% 100.00% # Bytes accessed per row activation 851system.physmem.bytesPerActivate::total 1015061 # Bytes accessed per row activation 852system.physmem.bytesReadDRAM 978888704 # Total number of bytes read from DRAM 853system.physmem.bytesReadSys 131219480 # Total read bytes from the system interface side 854system.physmem.bytesReadWrQ 106752 # Total number of bytes read from write queue 855system.physmem.bytesWritten 6855168 # Total number of bytes written to DRAM 856system.physmem.bytesWrittenSys 6845640 # Total written bytes from the system interface side 857system.physmem.bytes_inst_read::cpu.inst 1018176 # Number of instructions bytes read from this memory 858system.physmem.bytes_inst_read::total 1018176 # Number of instructions bytes read from this memory | |
| 859system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory | 16system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory |
| 860system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.dtb.walker 1152 # Number of bytes read from this memory |
| 861system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory |
| 862system.physmem.bytes_read::cpu.inst 10107480 # Number of bytes read from this memory 863system.physmem.bytes_read::total 131219480 # Number of bytes read from this memory 864system.physmem.bytes_written::writebacks 3829568 # Number of bytes written to this memory | 19system.physmem.bytes_read::cpu.inst 10106264 # Number of bytes read from this memory 20system.physmem.bytes_read::total 131218072 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 1017856 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 1017856 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 3829760 # Number of bytes written to this memory |
| 865system.physmem.bytes_written::cpu.inst 3016072 # Number of bytes written to this memory | 24system.physmem.bytes_written::cpu.inst 3016072 # Number of bytes written to this memory |
| 866system.physmem.bytes_written::total 6845640 # Number of bytes written to this memory 867system.physmem.memoryStateTime::IDLE 2210491886500 # Time in different power states 868system.physmem.memoryStateTime::REF 85740720000 # Time in different power states 869system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 870system.physmem.memoryStateTime::ACT 271454888500 # Time in different power states 871system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 872system.physmem.mergedWrBursts 706728 # Number of DRAM write bursts merged with an existing one 873system.physmem.neitherReadNorWriteReqs 4680 # Number of requests that are neither read nor write 874system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 875system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 25system.physmem.bytes_written::total 6845832 # Number of bytes written to this memory |
| 876system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory | 26system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory |
| 877system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory | 27system.physmem.num_reads::cpu.dtb.walker 18 # Number of read requests responded to by this memory |
| 878system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory | 28system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory |
| 879system.physmem.num_reads::cpu.inst 157965 # Number of read requests responded to by this memory 880system.physmem.num_reads::total 15296804 # Number of read requests responded to by this memory 881system.physmem.num_writes::writebacks 59837 # Number of write requests responded to by this memory | 29system.physmem.num_reads::cpu.inst 157946 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15296782 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 59840 # Number of write requests responded to by this memory |
| 882system.physmem.num_writes::cpu.inst 754018 # Number of write requests responded to by this memory | 32system.physmem.num_writes::cpu.inst 754018 # Number of write requests responded to by this memory |
| 883system.physmem.num_writes::total 813855 # Number of write requests responded to by this memory 884system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined 885system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 886system.physmem.perBankRdBursts::0 955934 # Per bank write bursts 887system.physmem.perBankRdBursts::1 955610 # Per bank write bursts 888system.physmem.perBankRdBursts::2 955719 # Per bank write bursts 889system.physmem.perBankRdBursts::3 955960 # Per bank write bursts 890system.physmem.perBankRdBursts::4 957705 # Per bank write bursts 891system.physmem.perBankRdBursts::5 955718 # Per bank write bursts | 33system.physmem.num_writes::total 813858 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47167344 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 449 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 3935955 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 51103798 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu.inst 396411 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::total 396411 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_write::writebacks 1491527 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_write::cpu.inst 1174630 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 2666157 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1491527 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::realview.clcd 47167344 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.dtb.walker 449 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.inst 5110586 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::total 53769956 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.readReqs 15296782 # Number of read requests accepted 51system.physmem.writeReqs 813858 # Number of write requests accepted 52system.physmem.readBursts 15296782 # Number of DRAM read bursts, including those serviced by the write queue 53system.physmem.writeBursts 813858 # Number of DRAM write bursts, including those merged in the write queue 54system.physmem.bytesReadDRAM 978883904 # Total number of bytes read from DRAM 55system.physmem.bytesReadWrQ 110144 # Total number of bytes read from write queue 56system.physmem.bytesWritten 6853696 # Total number of bytes written to DRAM 57system.physmem.bytesReadSys 131218072 # Total read bytes from the system interface side 58system.physmem.bytesWrittenSys 6845832 # Total written bytes from the system interface side 59system.physmem.servicedByWrQ 1721 # Number of DRAM read bursts serviced by the write queue 60system.physmem.mergedWrBursts 706743 # Number of DRAM write bursts merged with an existing one 61system.physmem.neitherReadNorWriteReqs 4671 # Number of requests that are neither read nor write 62system.physmem.perBankRdBursts::0 955926 # Per bank write bursts 63system.physmem.perBankRdBursts::1 955615 # Per bank write bursts 64system.physmem.perBankRdBursts::2 955732 # Per bank write bursts 65system.physmem.perBankRdBursts::3 955955 # Per bank write bursts 66system.physmem.perBankRdBursts::4 957630 # Per bank write bursts 67system.physmem.perBankRdBursts::5 955653 # Per bank write bursts |
| 892system.physmem.perBankRdBursts::6 955569 # Per bank write bursts | 68system.physmem.perBankRdBursts::6 955569 # Per bank write bursts |
| 893system.physmem.perBankRdBursts::7 955478 # Per bank write bursts 894system.physmem.perBankRdBursts::8 956345 # Per bank write bursts 895system.physmem.perBankRdBursts::9 955973 # Per bank write bursts 896system.physmem.perBankRdBursts::10 955562 # Per bank write bursts 897system.physmem.perBankRdBursts::11 955146 # Per bank write bursts 898system.physmem.perBankRdBursts::12 956303 # Per bank write bursts 899system.physmem.perBankRdBursts::13 956034 # Per bank write bursts 900system.physmem.perBankRdBursts::14 956157 # Per bank write bursts 901system.physmem.perBankRdBursts::15 955923 # Per bank write bursts 902system.physmem.perBankWrBursts::0 6634 # Per bank write bursts | 69system.physmem.perBankRdBursts::7 955430 # Per bank write bursts 70system.physmem.perBankRdBursts::8 956341 # Per bank write bursts 71system.physmem.perBankRdBursts::9 955977 # Per bank write bursts 72system.physmem.perBankRdBursts::10 955547 # Per bank write bursts 73system.physmem.perBankRdBursts::11 955151 # Per bank write bursts 74system.physmem.perBankRdBursts::12 956306 # Per bank write bursts 75system.physmem.perBankRdBursts::13 956026 # Per bank write bursts 76system.physmem.perBankRdBursts::14 956165 # Per bank write bursts 77system.physmem.perBankRdBursts::15 956038 # Per bank write bursts 78system.physmem.perBankWrBursts::0 6624 # Per bank write bursts |
| 903system.physmem.perBankWrBursts::1 6445 # Per bank write bursts | 79system.physmem.perBankWrBursts::1 6445 # Per bank write bursts |
| 904system.physmem.perBankWrBursts::2 6533 # Per bank write bursts 905system.physmem.perBankWrBursts::3 6602 # Per bank write bursts 906system.physmem.perBankWrBursts::4 6504 # Per bank write bursts 907system.physmem.perBankWrBursts::5 6748 # Per bank write bursts 908system.physmem.perBankWrBursts::6 6784 # Per bank write bursts 909system.physmem.perBankWrBursts::7 6699 # Per bank write bursts | 80system.physmem.perBankWrBursts::2 6544 # Per bank write bursts 81system.physmem.perBankWrBursts::3 6594 # Per bank write bursts 82system.physmem.perBankWrBursts::4 6491 # Per bank write bursts 83system.physmem.perBankWrBursts::5 6747 # Per bank write bursts 84system.physmem.perBankWrBursts::6 6783 # Per bank write bursts 85system.physmem.perBankWrBursts::7 6690 # Per bank write bursts |
| 910system.physmem.perBankWrBursts::8 7075 # Per bank write bursts | 86system.physmem.perBankWrBursts::8 7075 # Per bank write bursts |
| 911system.physmem.perBankWrBursts::9 6807 # Per bank write bursts 912system.physmem.perBankWrBursts::10 6488 # Per bank write bursts 913system.physmem.perBankWrBursts::11 6148 # Per bank write bursts 914system.physmem.perBankWrBursts::12 7101 # Per bank write bursts | 87system.physmem.perBankWrBursts::9 6811 # Per bank write bursts 88system.physmem.perBankWrBursts::10 6482 # Per bank write bursts 89system.physmem.perBankWrBursts::11 6150 # Per bank write bursts 90system.physmem.perBankWrBursts::12 7106 # Per bank write bursts |
| 915system.physmem.perBankWrBursts::13 6684 # Per bank write bursts | 91system.physmem.perBankWrBursts::13 6684 # Per bank write bursts |
| 916system.physmem.perBankWrBursts::14 7006 # Per bank write bursts 917system.physmem.perBankWrBursts::15 6854 # Per bank write bursts 918system.physmem.rdPerTurnAround::samples 6216 # Reads before turning the bus around for writes 919system.physmem.rdPerTurnAround::mean 2460.607465 # Reads before turning the bus around for writes 920system.physmem.rdPerTurnAround::stdev 89585.482628 # Reads before turning the bus around for writes 921system.physmem.rdPerTurnAround::0-262143 6210 99.90% 99.90% # Reads before turning the bus around for writes 922system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.94% # Reads before turning the bus around for writes 923system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.95% # Reads before turning the bus around for writes 924system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.97% # Reads before turning the bus around for writes 925system.physmem.rdPerTurnAround::2.62144e+06-2.88358e+06 1 0.02% 99.98% # Reads before turning the bus around for writes 926system.physmem.rdPerTurnAround::6.02931e+06-6.29146e+06 1 0.02% 100.00% # Reads before turning the bus around for writes 927system.physmem.rdPerTurnAround::total 6216 # Reads before turning the bus around for writes 928system.physmem.rdQLenPdf::0 1112302 # What read queue length does an incoming req see 929system.physmem.rdQLenPdf::1 958564 # What read queue length does an incoming req see 930system.physmem.rdQLenPdf::2 963836 # What read queue length does an incoming req see 931system.physmem.rdQLenPdf::3 1083179 # What read queue length does an incoming req see 932system.physmem.rdQLenPdf::4 974176 # What read queue length does an incoming req see 933system.physmem.rdQLenPdf::5 1042396 # What read queue length does an incoming req see 934system.physmem.rdQLenPdf::6 2682768 # What read queue length does an incoming req see 935system.physmem.rdQLenPdf::7 2583039 # What read queue length does an incoming req see 936system.physmem.rdQLenPdf::8 3365419 # What read queue length does an incoming req see 937system.physmem.rdQLenPdf::9 138919 # What read queue length does an incoming req see 938system.physmem.rdQLenPdf::10 118710 # What read queue length does an incoming req see 939system.physmem.rdQLenPdf::11 109585 # What read queue length does an incoming req see 940system.physmem.rdQLenPdf::12 106194 # What read queue length does an incoming req see 941system.physmem.rdQLenPdf::13 19284 # What read queue length does an incoming req see 942system.physmem.rdQLenPdf::14 18426 # What read queue length does an incoming req see 943system.physmem.rdQLenPdf::15 18172 # What read queue length does an incoming req see 944system.physmem.rdQLenPdf::16 159 # What read queue length does an incoming req see 945system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see 946system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see | 92system.physmem.perBankWrBursts::14 7011 # Per bank write bursts 93system.physmem.perBankWrBursts::15 6852 # Per bank write bursts 94system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 95system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 96system.physmem.totGap 2567675574500 # Total gap between requests 97system.physmem.readPktSize::0 0 # Read request sizes (log2) 98system.physmem.readPktSize::1 0 # Read request sizes (log2) 99system.physmem.readPktSize::2 38 # Read request sizes (log2) 100system.physmem.readPktSize::3 15138816 # Read request sizes (log2) 101system.physmem.readPktSize::4 0 # Read request sizes (log2) 102system.physmem.readPktSize::5 0 # Read request sizes (log2) 103system.physmem.readPktSize::6 157928 # Read request sizes (log2) 104system.physmem.writePktSize::0 0 # Write request sizes (log2) 105system.physmem.writePktSize::1 0 # Write request sizes (log2) 106system.physmem.writePktSize::2 754018 # Write request sizes (log2) 107system.physmem.writePktSize::3 0 # Write request sizes (log2) 108system.physmem.writePktSize::4 0 # Write request sizes (log2) 109system.physmem.writePktSize::5 0 # Write request sizes (log2) 110system.physmem.writePktSize::6 59840 # Write request sizes (log2) 111system.physmem.rdQLenPdf::0 1112326 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::1 958648 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::2 963944 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::3 1085542 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::4 974308 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::5 1043218 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::6 2679684 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::7 2578598 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::8 3358182 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::9 142716 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::10 121801 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::11 111705 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::12 108393 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::13 19289 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::14 18414 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::15 18153 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::16 135 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see |
| 947system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 948system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 949system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 950system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 951system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 952system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 953system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 954system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 955system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 956system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 957system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 958system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 959system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 130system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 960system.physmem.readBursts 15296804 # Number of DRAM read bursts, including those serviced by the write queue 961system.physmem.readPktSize::0 0 # Read request sizes (log2) 962system.physmem.readPktSize::1 0 # Read request sizes (log2) 963system.physmem.readPktSize::2 38 # Read request sizes (log2) 964system.physmem.readPktSize::3 15138816 # Read request sizes (log2) 965system.physmem.readPktSize::4 0 # Read request sizes (log2) 966system.physmem.readPktSize::5 0 # Read request sizes (log2) 967system.physmem.readPktSize::6 157950 # Read request sizes (log2) 968system.physmem.readReqs 15296804 # Number of read requests accepted 969system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads 970system.physmem.readRowHits 14297551 # Number of row buffer hits during reads 971system.physmem.servicedByWrQ 1668 # Number of DRAM read bursts serviced by the write queue 972system.physmem.totBusLat 76475680000 # Total ticks spent in databus transfers 973system.physmem.totGap 2567689117500 # Total gap between requests 974system.physmem.totMemAccLat 682754832250 # Total ticks spent from burst creation until serviced by the DRAM 975system.physmem.totQLat 395971032250 # Total ticks spent queuing 976system.physmem.wrPerTurnAround::samples 6216 # Writes before turning the bus around for reads 977system.physmem.wrPerTurnAround::mean 17.231660 # Writes before turning the bus around for reads 978system.physmem.wrPerTurnAround::gmean 17.203648 # Writes before turning the bus around for reads 979system.physmem.wrPerTurnAround::stdev 0.973536 # Writes before turning the bus around for reads 980system.physmem.wrPerTurnAround::16 2382 38.32% 38.32% # Writes before turning the bus around for reads 981system.physmem.wrPerTurnAround::17 22 0.35% 38.67% # Writes before turning the bus around for reads 982system.physmem.wrPerTurnAround::18 3802 61.16% 99.84% # Writes before turning the bus around for reads 983system.physmem.wrPerTurnAround::19 10 0.16% 100.00% # Writes before turning the bus around for reads 984system.physmem.wrPerTurnAround::total 6216 # Writes before turning the bus around for reads | |
| 985system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 986system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 987system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 988system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 989system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 990system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 991system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 992system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 993system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 994system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 995system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 996system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 997system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 998system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 999system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 143system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 1000system.physmem.wrQLenPdf::15 3810 # What write queue length does an incoming req see 1001system.physmem.wrQLenPdf::16 3834 # What write queue length does an incoming req see 1002system.physmem.wrQLenPdf::17 6190 # What write queue length does an incoming req see | 158system.physmem.wrQLenPdf::15 3806 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::16 3819 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::17 6193 # What write queue length does an incoming req see |
| 1003system.physmem.wrQLenPdf::18 6217 # What write queue length does an incoming req see | 161system.physmem.wrQLenPdf::18 6217 # What write queue length does an incoming req see |
| 1004system.physmem.wrQLenPdf::19 6219 # What write queue length does an incoming req see | 162system.physmem.wrQLenPdf::19 6223 # What write queue length does an incoming req see |
| 1005system.physmem.wrQLenPdf::20 6217 # What write queue length does an incoming req see 1006system.physmem.wrQLenPdf::21 6218 # What write queue length does an incoming req see | 163system.physmem.wrQLenPdf::20 6217 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::21 6218 # What write queue length does an incoming req see |
| 1007system.physmem.wrQLenPdf::22 6217 # What write queue length does an incoming req see 1008system.physmem.wrQLenPdf::23 6220 # What write queue length does an incoming req see 1009system.physmem.wrQLenPdf::24 6217 # What write queue length does an incoming req see 1010system.physmem.wrQLenPdf::25 6219 # What write queue length does an incoming req see 1011system.physmem.wrQLenPdf::26 6222 # What write queue length does an incoming req see | 165system.physmem.wrQLenPdf::22 6219 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::23 6219 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::24 6220 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::25 6221 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::26 6217 # What write queue length does an incoming req see |
| 1012system.physmem.wrQLenPdf::27 6225 # What write queue length does an incoming req see | 170system.physmem.wrQLenPdf::27 6225 # What write queue length does an incoming req see |
| 1013system.physmem.wrQLenPdf::28 6221 # What write queue length does an incoming req see | 171system.physmem.wrQLenPdf::28 6219 # What write queue length does an incoming req see |
| 1014system.physmem.wrQLenPdf::29 6217 # What write queue length does an incoming req see 1015system.physmem.wrQLenPdf::30 6216 # What write queue length does an incoming req see | 172system.physmem.wrQLenPdf::29 6217 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::30 6216 # What write queue length does an incoming req see |
| 1016system.physmem.wrQLenPdf::31 6216 # What write queue length does an incoming req see | 174system.physmem.wrQLenPdf::31 6218 # What write queue length does an incoming req see |
| 1017system.physmem.wrQLenPdf::32 6216 # What write queue length does an incoming req see | 175system.physmem.wrQLenPdf::32 6216 # What write queue length does an incoming req see |
| 1018system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see | 176system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see |
| 1019system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 1020system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 1021system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 1022system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 1023system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 1024system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 1025system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 1026system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 1041system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 1042system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 1043system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 1044system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 1045system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 1046system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 1047system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 1048system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 177system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 199system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 1049system.physmem.writeBursts 813855 # Number of DRAM write bursts, including those merged in the write queue 1050system.physmem.writePktSize::0 0 # Write request sizes (log2) 1051system.physmem.writePktSize::1 0 # Write request sizes (log2) 1052system.physmem.writePktSize::2 754018 # Write request sizes (log2) 1053system.physmem.writePktSize::3 0 # Write request sizes (log2) 1054system.physmem.writePktSize::4 0 # Write request sizes (log2) 1055system.physmem.writePktSize::5 0 # Write request sizes (log2) 1056system.physmem.writePktSize::6 59837 # Write request sizes (log2) 1057system.physmem.writeReqs 813855 # Number of write requests accepted 1058system.physmem.writeRowHitRate 83.67 # Row buffer hit rate for writes 1059system.physmem.writeRowHits 89636 # Number of row buffer hits during writes 1060system.realview.nvmem.bw_inst_read::cpu.inst 100 # Instruction read bandwidth from this memory (bytes/s) 1061system.realview.nvmem.bw_inst_read::total 100 # Instruction read bandwidth from this memory (bytes/s) 1062system.realview.nvmem.bw_read::cpu.inst 100 # Total read bandwidth from this memory (bytes/s) 1063system.realview.nvmem.bw_read::total 100 # Total read bandwidth from this memory (bytes/s) 1064system.realview.nvmem.bw_total::cpu.inst 100 # Total bandwidth to/from this memory (bytes/s) 1065system.realview.nvmem.bw_total::total 100 # Total bandwidth to/from this memory (bytes/s) 1066system.realview.nvmem.bytes_inst_read::cpu.inst 256 # Number of instructions bytes read from this memory 1067system.realview.nvmem.bytes_inst_read::total 256 # Number of instructions bytes read from this memory | 207system.physmem.bytesPerActivate::samples 1015088 # Bytes accessed per row activation 208system.physmem.bytesPerActivate::mean 971.085857 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::gmean 904.509360 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::stdev 205.145024 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::0-127 22501 2.22% 2.22% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::128-255 22772 2.24% 4.46% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::256-383 8563 0.84% 5.30% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::384-511 2455 0.24% 5.55% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::512-639 2778 0.27% 5.82% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::640-767 1897 0.19% 6.01% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::768-895 8457 0.83% 6.84% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::896-1023 971 0.10% 6.93% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::1024-1151 944694 93.07% 100.00% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::total 1015088 # Bytes accessed per row activation 221system.physmem.rdPerTurnAround::samples 6216 # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::mean 2460.593951 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::stdev 115853.550339 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::0-524287 6211 99.92% 99.92% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::total 6216 # Reads before turning the bus around for writes 229system.physmem.wrPerTurnAround::samples 6216 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::mean 17.227960 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::gmean 17.199911 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::stdev 0.974162 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::16 2395 38.53% 38.53% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::17 16 0.26% 38.79% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::18 3798 61.10% 99.89% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::19 7 0.11% 100.00% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::total 6216 # Writes before turning the bus around for reads 238system.physmem.totQLat 396370290250 # Total ticks spent queuing 239system.physmem.totMemAccLat 683152684000 # Total ticks spent from burst creation until serviced by the DRAM 240system.physmem.totBusLat 76475305000 # Total ticks spent in databus transfers 241system.physmem.avgQLat 25914.92 # Average queueing delay per DRAM burst 242system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 243system.physmem.avgMemAccLat 44664.92 # Average memory access latency per DRAM burst 244system.physmem.avgRdBW 381.23 # Average DRAM read bandwidth in MiByte/s 245system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s 246system.physmem.avgRdBWSys 51.10 # Average system read bandwidth in MiByte/s 247system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s 248system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 249system.physmem.busUtil 3.00 # Data bus utilization in percentage 250system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads 251system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 252system.physmem.avgRdQLen 6.49 # Average read queue length when enqueuing 253system.physmem.avgWrQLen 27.85 # Average write queue length when enqueuing 254system.physmem.readRowHits 14297424 # Number of row buffer hits during reads 255system.physmem.writeRowHits 89638 # Number of row buffer hits during writes 256system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads 257system.physmem.writeRowHitRate 83.68 # Row buffer hit rate for writes 258system.physmem.avgGap 159377.63 # Average gap between requests 259system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined 260system.physmem.memoryStateTime::IDLE 2210132306750 # Time in different power states 261system.physmem.memoryStateTime::REF 85740200000 # Time in different power states 262system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 263system.physmem.memoryStateTime::ACT 271799415750 # Time in different power states 264system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 1068system.realview.nvmem.bytes_read::cpu.inst 256 # Number of bytes read from this memory 1069system.realview.nvmem.bytes_read::total 256 # Number of bytes read from this memory | 265system.realview.nvmem.bytes_read::cpu.inst 256 # Number of bytes read from this memory 266system.realview.nvmem.bytes_read::total 256 # Number of bytes read from this memory |
| 267system.realview.nvmem.bytes_inst_read::cpu.inst 256 # Number of instructions bytes read from this memory 268system.realview.nvmem.bytes_inst_read::total 256 # Number of instructions bytes read from this memory |
|
| 1070system.realview.nvmem.num_reads::cpu.inst 4 # Number of read requests responded to by this memory 1071system.realview.nvmem.num_reads::total 4 # Number of read requests responded to by this memory | 269system.realview.nvmem.num_reads::cpu.inst 4 # Number of read requests responded to by this memory 270system.realview.nvmem.num_reads::total 4 # Number of read requests responded to by this memory |
| 1072system.voltage_domain.voltage 1 # Voltage in Volts | 271system.realview.nvmem.bw_read::cpu.inst 100 # Total read bandwidth from this memory (bytes/s) 272system.realview.nvmem.bw_read::total 100 # Total read bandwidth from this memory (bytes/s) 273system.realview.nvmem.bw_inst_read::cpu.inst 100 # Instruction read bandwidth from this memory (bytes/s) 274system.realview.nvmem.bw_inst_read::total 100 # Instruction read bandwidth from this memory (bytes/s) 275system.realview.nvmem.bw_total::cpu.inst 100 # Total bandwidth to/from this memory (bytes/s) 276system.realview.nvmem.bw_total::total 100 # Total bandwidth to/from this memory (bytes/s) 277system.membus.throughput 54704015 # Throughput (bytes/s) 278system.membus.trans_dist::ReadReq 16349240 # Transaction distribution 279system.membus.trans_dist::ReadResp 16349240 # Transaction distribution 280system.membus.trans_dist::WriteReq 763365 # Transaction distribution 281system.membus.trans_dist::WriteResp 763365 # Transaction distribution 282system.membus.trans_dist::Writeback 59840 # Transaction distribution 283system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution 284system.membus.trans_dist::UpgradeResp 4671 # Transaction distribution 285system.membus.trans_dist::ReadExReq 131634 # Transaction distribution 286system.membus.trans_dist::ReadExResp 131634 # Transaction distribution 287system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383068 # Packet count per connected master and slave (bytes) 288system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 8 # Packet count per connected master and slave (bytes) 289system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3800 # Packet count per connected master and slave (bytes) 290system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) 291system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893150 # Packet count per connected master and slave (bytes) 292system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280028 # Packet count per connected master and slave (bytes) 293system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) 294system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) 295system.membus.pkt_count::total 34557660 # Packet count per connected master and slave (bytes) 296system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390502 # Cumulative packet size per connected master and slave (bytes) 297system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 256 # Cumulative packet size per connected master and slave (bytes) 298system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7600 # Cumulative packet size per connected master and slave (bytes) 299system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) 300system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16953376 # Cumulative packet size per connected master and slave (bytes) 301system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19351738 # Cumulative packet size per connected master and slave (bytes) 302system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) 303system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) 304system.membus.tot_pkt_size::total 140462266 # Cumulative packet size per connected master and slave (bytes) 305system.membus.data_through_bus 140462266 # Total data (bytes) 306system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 307system.membus.reqLayer0.occupancy 1731218500 # Layer occupancy (ticks) 308system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 309system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) 310system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 311system.membus.reqLayer2.occupancy 3525000 # Layer occupancy (ticks) 312system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 313system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) 314system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 315system.membus.reqLayer6.occupancy 17560732500 # Layer occupancy (ticks) 316system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) 317system.membus.respLayer1.occupancy 4805026968 # Layer occupancy (ticks) 318system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 319system.membus.respLayer2.occupancy 37408380500 # Layer occupancy (ticks) 320system.membus.respLayer2.utilization 1.5 # Layer utilization (%) 321system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 322system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 323system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 324system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 325system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 326system.cf0.dma_write_txs 0 # Number of DMA write transactions. 327system.iobus.throughput 48098342 # Throughput (bytes/s) 328system.iobus.trans_dist::ReadReq 16322172 # Transaction distribution 329system.iobus.trans_dist::ReadResp 16322172 # Transaction distribution 330system.iobus.trans_dist::WriteReq 8178 # Transaction distribution 331system.iobus.trans_dist::WriteResp 8178 # Transaction distribution 332system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) 333system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) 334system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 524 # Packet count per connected master and slave (bytes) 335system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) 336system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 337system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 338system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 339system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 340system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 341system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 342system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 343system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 344system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 345system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 346system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 347system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 348system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 349system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 350system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 351system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 352system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 353system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 354system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 355system.iobus.pkt_count_system.bridge.master::total 2383068 # Packet count per connected master and slave (bytes) 356system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) 357system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) 358system.iobus.pkt_count::total 32660700 # Packet count per connected master and slave (bytes) 359system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) 360system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) 361system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1048 # Cumulative packet size per connected master and slave (bytes) 362system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) 363system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 364system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 365system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 366system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 367system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 368system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 369system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 370system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 371system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 372system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 373system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 374system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 375system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 376system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 377system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 378system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 379system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 380system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 381system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 382system.iobus.tot_pkt_size_system.bridge.master::total 2390502 # Cumulative packet size per connected master and slave (bytes) 383system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) 384system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) 385system.iobus.tot_pkt_size::total 123501030 # Cumulative packet size per connected master and slave (bytes) 386system.iobus.data_through_bus 123501030 # Total data (bytes) 387system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) 388system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 389system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) 390system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 391system.iobus.reqLayer2.occupancy 524000 # Layer occupancy (ticks) 392system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 393system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks) 394system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 395system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 396system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 397system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 398system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 399system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) 400system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 401system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 402system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 403system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 404system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 405system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 406system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 407system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 408system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 409system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 410system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 411system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 412system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 413system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 414system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 415system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 416system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 417system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 418system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 419system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 420system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 421system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 422system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 423system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 424system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 425system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 426system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 427system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 428system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 429system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 430system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 431system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 432system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 433system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) 434system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 435system.iobus.respLayer0.occupancy 2374890000 # Layer occupancy (ticks) 436system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 437system.iobus.respLayer1.occupancy 38224979500 # Layer occupancy (ticks) 438system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 439system.cpu_clk_domain.clock 500 # Clock period in ticks 440system.cpu.branchPred.lookups 12907759 # Number of BP lookups 441system.cpu.branchPred.condPredicted 9898849 # Number of conditional branches predicted 442system.cpu.branchPred.condIncorrect 1085572 # Number of conditional branches incorrect 443system.cpu.branchPred.BTBLookups 8888360 # Number of BTB lookups 444system.cpu.branchPred.BTBHits 6291175 # Number of BTB hits 445system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 446system.cpu.branchPred.BTBHitPct 70.779930 # BTB Hit Percentage 447system.cpu.branchPred.usedRAS 1515479 # Number of times the RAS was used to get a target. 448system.cpu.branchPred.RASInCorrect 141893 # Number of incorrect RAS predictions. 449system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 450system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 451system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 452system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 453system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 454system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 455system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 456system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 457system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 458system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 459system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 460system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 461system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 462system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 463system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 464system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 465system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 466system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 467system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 468system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 469system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 470system.cpu.dtb.inst_hits 0 # ITB inst hits 471system.cpu.dtb.inst_misses 0 # ITB inst misses 472system.cpu.dtb.read_hits 15416418 # DTB read hits 473system.cpu.dtb.read_misses 42733 # DTB read misses 474system.cpu.dtb.write_hits 11344011 # DTB write hits 475system.cpu.dtb.write_misses 3796 # DTB write misses 476system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 477system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 478system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 479system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 480system.cpu.dtb.flush_entries 3452 # Number of entries that have been flushed from TLB 481system.cpu.dtb.align_faults 1264 # Number of TLB faults due to alignment restrictions 482system.cpu.dtb.prefetch_faults 262 # Number of TLB faults due to prefetch 483system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 484system.cpu.dtb.perms_faults 531 # Number of TLB faults due to permissions restrictions 485system.cpu.dtb.read_accesses 15459151 # DTB read accesses 486system.cpu.dtb.write_accesses 11347807 # DTB write accesses 487system.cpu.dtb.inst_accesses 0 # ITB inst accesses 488system.cpu.dtb.hits 26760429 # DTB hits 489system.cpu.dtb.misses 46529 # DTB misses 490system.cpu.dtb.accesses 26806958 # DTB accesses 491system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 492system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 493system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 494system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 495system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 496system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 497system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 498system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 499system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 500system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 501system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 502system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 503system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 504system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 505system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 506system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 507system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 508system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 509system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 510system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 511system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 512system.cpu.itb.inst_hits 23352687 # ITB inst hits 513system.cpu.itb.inst_misses 9286 # ITB inst misses 514system.cpu.itb.read_hits 0 # DTB read hits 515system.cpu.itb.read_misses 0 # DTB read misses 516system.cpu.itb.write_hits 0 # DTB write hits 517system.cpu.itb.write_misses 0 # DTB write misses 518system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 519system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 520system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 521system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 522system.cpu.itb.flush_entries 2392 # Number of entries that have been flushed from TLB 523system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 524system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 525system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 526system.cpu.itb.perms_faults 4189 # Number of TLB faults due to permissions restrictions 527system.cpu.itb.read_accesses 0 # DTB read accesses 528system.cpu.itb.write_accesses 0 # DTB write accesses 529system.cpu.itb.inst_accesses 23361973 # ITB inst accesses 530system.cpu.itb.hits 23352687 # DTB hits 531system.cpu.itb.misses 9286 # DTB misses 532system.cpu.itb.accesses 23361973 # DTB accesses 533system.cpu.numCycles 576983411 # number of cpu cycles simulated 534system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 535system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 536system.cpu.committedInsts 60592948 # Number of instructions committed 537system.cpu.committedOps 77887482 # Number of ops (including micro ops) committed 538system.cpu.discardedOps 3584241 # Number of ops (including micro ops) which were discarded before commit 539system.cpu.numFetchSuspends 77491 # Number of times Execute suspended instruction fetching 540system.cpu.quiesceCycles 4560301069 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 541system.cpu.cpi 9.522287 # CPI: cycles per instruction 542system.cpu.ipc 0.105017 # IPC: instructions per cycle 543system.cpu.kern.inst.arm 0 # number of arm instructions executed 544system.cpu.kern.inst.quiesce 82977 # number of quiesce instructions executed 545system.cpu.tickCycles 470832364 # Number of cycles that the object actually ticked 546system.cpu.idleCycles 106151047 # Total number of cycles that the object has spent stopped 547system.cpu.icache.tags.replacements 1545254 # number of replacements 548system.cpu.icache.tags.tagsinuse 511.467506 # Cycle average of tags in use 549system.cpu.icache.tags.total_refs 21802506 # Total number of references to valid blocks. 550system.cpu.icache.tags.sampled_refs 1545766 # Sample count of references to valid blocks. 551system.cpu.icache.tags.avg_refs 14.104661 # Average number of references to valid blocks. 552system.cpu.icache.tags.warmup_cycle 10068892000 # Cycle when the warmup percentage was hit. 553system.cpu.icache.tags.occ_blocks::cpu.inst 511.467506 # Average occupied blocks per requestor 554system.cpu.icache.tags.occ_percent::cpu.inst 0.998960 # Average percentage of cache occupancy 555system.cpu.icache.tags.occ_percent::total 0.998960 # Average percentage of cache occupancy 556system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 557system.cpu.icache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id 558system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id 559system.cpu.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id 560system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 561system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 562system.cpu.icache.tags.tag_accesses 24894039 # Number of tag accesses 563system.cpu.icache.tags.data_accesses 24894039 # Number of data accesses 564system.cpu.icache.ReadReq_hits::cpu.inst 21802506 # number of ReadReq hits 565system.cpu.icache.ReadReq_hits::total 21802506 # number of ReadReq hits 566system.cpu.icache.demand_hits::cpu.inst 21802506 # number of demand (read+write) hits 567system.cpu.icache.demand_hits::total 21802506 # number of demand (read+write) hits 568system.cpu.icache.overall_hits::cpu.inst 21802506 # number of overall hits 569system.cpu.icache.overall_hits::total 21802506 # number of overall hits 570system.cpu.icache.ReadReq_misses::cpu.inst 1545767 # number of ReadReq misses 571system.cpu.icache.ReadReq_misses::total 1545767 # number of ReadReq misses 572system.cpu.icache.demand_misses::cpu.inst 1545767 # number of demand (read+write) misses 573system.cpu.icache.demand_misses::total 1545767 # number of demand (read+write) misses 574system.cpu.icache.overall_misses::cpu.inst 1545767 # number of overall misses 575system.cpu.icache.overall_misses::total 1545767 # number of overall misses 576system.cpu.icache.ReadReq_miss_latency::cpu.inst 20898816329 # number of ReadReq miss cycles 577system.cpu.icache.ReadReq_miss_latency::total 20898816329 # number of ReadReq miss cycles 578system.cpu.icache.demand_miss_latency::cpu.inst 20898816329 # number of demand (read+write) miss cycles 579system.cpu.icache.demand_miss_latency::total 20898816329 # number of demand (read+write) miss cycles 580system.cpu.icache.overall_miss_latency::cpu.inst 20898816329 # number of overall miss cycles 581system.cpu.icache.overall_miss_latency::total 20898816329 # number of overall miss cycles 582system.cpu.icache.ReadReq_accesses::cpu.inst 23348273 # number of ReadReq accesses(hits+misses) 583system.cpu.icache.ReadReq_accesses::total 23348273 # number of ReadReq accesses(hits+misses) 584system.cpu.icache.demand_accesses::cpu.inst 23348273 # number of demand (read+write) accesses 585system.cpu.icache.demand_accesses::total 23348273 # number of demand (read+write) accesses 586system.cpu.icache.overall_accesses::cpu.inst 23348273 # number of overall (read+write) accesses 587system.cpu.icache.overall_accesses::total 23348273 # number of overall (read+write) accesses 588system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.066205 # miss rate for ReadReq accesses 589system.cpu.icache.ReadReq_miss_rate::total 0.066205 # miss rate for ReadReq accesses 590system.cpu.icache.demand_miss_rate::cpu.inst 0.066205 # miss rate for demand accesses 591system.cpu.icache.demand_miss_rate::total 0.066205 # miss rate for demand accesses 592system.cpu.icache.overall_miss_rate::cpu.inst 0.066205 # miss rate for overall accesses 593system.cpu.icache.overall_miss_rate::total 0.066205 # miss rate for overall accesses 594system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13520.030075 # average ReadReq miss latency 595system.cpu.icache.ReadReq_avg_miss_latency::total 13520.030075 # average ReadReq miss latency 596system.cpu.icache.demand_avg_miss_latency::cpu.inst 13520.030075 # average overall miss latency 597system.cpu.icache.demand_avg_miss_latency::total 13520.030075 # average overall miss latency 598system.cpu.icache.overall_avg_miss_latency::cpu.inst 13520.030075 # average overall miss latency 599system.cpu.icache.overall_avg_miss_latency::total 13520.030075 # average overall miss latency 600system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 601system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 602system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 603system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 604system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 605system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 606system.cpu.icache.fast_writes 0 # number of fast writes performed 607system.cpu.icache.cache_copies 0 # number of cache copies performed 608system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1545767 # number of ReadReq MSHR misses 609system.cpu.icache.ReadReq_mshr_misses::total 1545767 # number of ReadReq MSHR misses 610system.cpu.icache.demand_mshr_misses::cpu.inst 1545767 # number of demand (read+write) MSHR misses 611system.cpu.icache.demand_mshr_misses::total 1545767 # number of demand (read+write) MSHR misses 612system.cpu.icache.overall_mshr_misses::cpu.inst 1545767 # number of overall MSHR misses 613system.cpu.icache.overall_mshr_misses::total 1545767 # number of overall MSHR misses 614system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17801487671 # number of ReadReq MSHR miss cycles 615system.cpu.icache.ReadReq_mshr_miss_latency::total 17801487671 # number of ReadReq MSHR miss cycles 616system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17801487671 # number of demand (read+write) MSHR miss cycles 617system.cpu.icache.demand_mshr_miss_latency::total 17801487671 # number of demand (read+write) MSHR miss cycles 618system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17801487671 # number of overall MSHR miss cycles 619system.cpu.icache.overall_mshr_miss_latency::total 17801487671 # number of overall MSHR miss cycles 620system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 172412750 # number of ReadReq MSHR uncacheable cycles 621system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 172412750 # number of ReadReq MSHR uncacheable cycles 622system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 172412750 # number of overall MSHR uncacheable cycles 623system.cpu.icache.overall_mshr_uncacheable_latency::total 172412750 # number of overall MSHR uncacheable cycles 624system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066205 # mshr miss rate for ReadReq accesses 625system.cpu.icache.ReadReq_mshr_miss_rate::total 0.066205 # mshr miss rate for ReadReq accesses 626system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066205 # mshr miss rate for demand accesses 627system.cpu.icache.demand_mshr_miss_rate::total 0.066205 # mshr miss rate for demand accesses 628system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066205 # mshr miss rate for overall accesses 629system.cpu.icache.overall_mshr_miss_rate::total 0.066205 # mshr miss rate for overall accesses 630system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11516.281348 # average ReadReq mshr miss latency 631system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11516.281348 # average ReadReq mshr miss latency 632system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11516.281348 # average overall mshr miss latency 633system.cpu.icache.demand_avg_mshr_miss_latency::total 11516.281348 # average overall mshr miss latency 634system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11516.281348 # average overall mshr miss latency 635system.cpu.icache.overall_avg_mshr_miss_latency::total 11516.281348 # average overall mshr miss latency 636system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 637system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 638system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 639system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 640system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 641system.cpu.toL2Bus.throughput 71776562 # Throughput (bytes/s) 642system.cpu.toL2Bus.trans_dist::ReadReq 3214470 # Transaction distribution 643system.cpu.toL2Bus.trans_dist::ReadResp 3214469 # Transaction distribution 644system.cpu.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution 645system.cpu.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution 646system.cpu.toL2Bus.trans_dist::Writeback 602969 # Transaction distribution 647system.cpu.toL2Bus.trans_dist::UpgradeReq 2961 # Transaction distribution 648system.cpu.toL2Bus.trans_dist::UpgradeResp 2961 # Transaction distribution 649system.cpu.toL2Bus.trans_dist::ReadExReq 247546 # Transaction distribution 650system.cpu.toL2Bus.trans_dist::ReadExResp 247546 # Transaction distribution 651system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3094256 # Packet count per connected master and slave (bytes) 652system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5780457 # Packet count per connected master and slave (bytes) 653system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 29847 # Packet count per connected master and slave (bytes) 654system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126652 # Packet count per connected master and slave (bytes) 655system.cpu.toL2Bus.pkt_count::total 9031212 # Packet count per connected master and slave (bytes) 656system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 98954304 # Cumulative packet size per connected master and slave (bytes) 657system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84855034 # Cumulative packet size per connected master and slave (bytes) 658system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 45620 # Cumulative packet size per connected master and slave (bytes) 659system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214364 # Cumulative packet size per connected master and slave (bytes) 660system.cpu.toL2Bus.tot_pkt_size::total 184069322 # Cumulative packet size per connected master and slave (bytes) 661system.cpu.toL2Bus.data_through_bus 184069322 # Total data (bytes) 662system.cpu.toL2Bus.snoop_data_through_bus 229740 # Total snoop data (bytes) 663system.cpu.toL2Bus.reqLayer0.occupancy 3400466435 # Layer occupancy (ticks) 664system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 665system.cpu.toL2Bus.respLayer0.occupancy 2325579079 # Layer occupancy (ticks) 666system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 667system.cpu.toL2Bus.respLayer1.occupancy 2551211790 # Layer occupancy (ticks) 668system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 669system.cpu.toL2Bus.respLayer2.occupancy 18447489 # Layer occupancy (ticks) 670system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 671system.cpu.toL2Bus.respLayer3.occupancy 73062749 # Layer occupancy (ticks) 672system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 673system.cpu.l2cache.tags.replacements 65493 # number of replacements 674system.cpu.l2cache.tags.tagsinuse 51631.050557 # Cycle average of tags in use 675system.cpu.l2cache.tags.total_refs 2439202 # Total number of references to valid blocks. 676system.cpu.l2cache.tags.sampled_refs 130882 # Sample count of references to valid blocks. 677system.cpu.l2cache.tags.avg_refs 18.636650 # Average number of references to valid blocks. 678system.cpu.l2cache.tags.warmup_cycle 2525290748000 # Cycle when the warmup percentage was hit. 679system.cpu.l2cache.tags.occ_blocks::writebacks 36364.368368 # Average occupied blocks per requestor 680system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.573566 # Average occupied blocks per requestor 681system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000576 # Average occupied blocks per requestor 682system.cpu.l2cache.tags.occ_blocks::cpu.inst 15253.108047 # Average occupied blocks per requestor 683system.cpu.l2cache.tags.occ_percent::writebacks 0.554876 # Average percentage of cache occupancy 684system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000207 # Average percentage of cache occupancy 685system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 686system.cpu.l2cache.tags.occ_percent::cpu.inst 0.232744 # Average percentage of cache occupancy 687system.cpu.l2cache.tags.occ_percent::total 0.787827 # Average percentage of cache occupancy 688system.cpu.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id 689system.cpu.l2cache.tags.occ_task_id_blocks::1024 65379 # Occupied blocks per task id 690system.cpu.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id 691system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 692system.cpu.l2cache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id 693system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2430 # Occupied blocks per task id 694system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6701 # Occupied blocks per task id 695system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56138 # Occupied blocks per task id 696system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000153 # Percentage of cache occupancy per task id 697system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997604 # Percentage of cache occupancy per task id 698system.cpu.l2cache.tags.tag_accesses 23227461 # Number of tag accesses 699system.cpu.l2cache.tags.data_accesses 23227461 # Number of data accesses 700system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53573 # number of ReadReq hits 701system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11403 # number of ReadReq hits 702system.cpu.l2cache.ReadReq_hits::cpu.inst 1910560 # number of ReadReq hits 703system.cpu.l2cache.ReadReq_hits::total 1975536 # number of ReadReq hits 704system.cpu.l2cache.Writeback_hits::writebacks 602969 # number of Writeback hits 705system.cpu.l2cache.Writeback_hits::total 602969 # number of Writeback hits 706system.cpu.l2cache.UpgradeReq_hits::cpu.inst 25 # number of UpgradeReq hits 707system.cpu.l2cache.UpgradeReq_hits::total 25 # number of UpgradeReq hits 708system.cpu.l2cache.ReadExReq_hits::cpu.inst 114177 # number of ReadExReq hits 709system.cpu.l2cache.ReadExReq_hits::total 114177 # number of ReadExReq hits 710system.cpu.l2cache.demand_hits::cpu.dtb.walker 53573 # number of demand (read+write) hits 711system.cpu.l2cache.demand_hits::cpu.itb.walker 11403 # number of demand (read+write) hits 712system.cpu.l2cache.demand_hits::cpu.inst 2024737 # number of demand (read+write) hits 713system.cpu.l2cache.demand_hits::total 2089713 # number of demand (read+write) hits 714system.cpu.l2cache.overall_hits::cpu.dtb.walker 53573 # number of overall hits 715system.cpu.l2cache.overall_hits::cpu.itb.walker 11403 # number of overall hits 716system.cpu.l2cache.overall_hits::cpu.inst 2024737 # number of overall hits 717system.cpu.l2cache.overall_hits::total 2089713 # number of overall hits 718system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 18 # number of ReadReq misses 719system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 720system.cpu.l2cache.ReadReq_misses::cpu.inst 24020 # number of ReadReq misses 721system.cpu.l2cache.ReadReq_misses::total 24040 # number of ReadReq misses 722system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2936 # number of UpgradeReq misses 723system.cpu.l2cache.UpgradeReq_misses::total 2936 # number of UpgradeReq misses 724system.cpu.l2cache.ReadExReq_misses::cpu.inst 133369 # number of ReadExReq misses 725system.cpu.l2cache.ReadExReq_misses::total 133369 # number of ReadExReq misses 726system.cpu.l2cache.demand_misses::cpu.dtb.walker 18 # number of demand (read+write) misses 727system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 728system.cpu.l2cache.demand_misses::cpu.inst 157389 # number of demand (read+write) misses 729system.cpu.l2cache.demand_misses::total 157409 # number of demand (read+write) misses 730system.cpu.l2cache.overall_misses::cpu.dtb.walker 18 # number of overall misses 731system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 732system.cpu.l2cache.overall_misses::cpu.inst 157389 # number of overall misses 733system.cpu.l2cache.overall_misses::total 157409 # number of overall misses 734system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1388250 # number of ReadReq miss cycles 735system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles 736system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1729894000 # number of ReadReq miss cycles 737system.cpu.l2cache.ReadReq_miss_latency::total 1731431750 # number of ReadReq miss cycles 738system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 394983 # number of UpgradeReq miss cycles 739system.cpu.l2cache.UpgradeReq_miss_latency::total 394983 # number of UpgradeReq miss cycles 740system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9208617265 # number of ReadExReq miss cycles 741system.cpu.l2cache.ReadExReq_miss_latency::total 9208617265 # number of ReadExReq miss cycles 742system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1388250 # number of demand (read+write) miss cycles 743system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles 744system.cpu.l2cache.demand_miss_latency::cpu.inst 10938511265 # number of demand (read+write) miss cycles 745system.cpu.l2cache.demand_miss_latency::total 10940049015 # number of demand (read+write) miss cycles 746system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1388250 # number of overall miss cycles 747system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles 748system.cpu.l2cache.overall_miss_latency::cpu.inst 10938511265 # number of overall miss cycles 749system.cpu.l2cache.overall_miss_latency::total 10940049015 # number of overall miss cycles 750system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53591 # number of ReadReq accesses(hits+misses) 751system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11405 # number of ReadReq accesses(hits+misses) 752system.cpu.l2cache.ReadReq_accesses::cpu.inst 1934580 # number of ReadReq accesses(hits+misses) 753system.cpu.l2cache.ReadReq_accesses::total 1999576 # number of ReadReq accesses(hits+misses) 754system.cpu.l2cache.Writeback_accesses::writebacks 602969 # number of Writeback accesses(hits+misses) 755system.cpu.l2cache.Writeback_accesses::total 602969 # number of Writeback accesses(hits+misses) 756system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2961 # number of UpgradeReq accesses(hits+misses) 757system.cpu.l2cache.UpgradeReq_accesses::total 2961 # number of UpgradeReq accesses(hits+misses) 758system.cpu.l2cache.ReadExReq_accesses::cpu.inst 247546 # number of ReadExReq accesses(hits+misses) 759system.cpu.l2cache.ReadExReq_accesses::total 247546 # number of ReadExReq accesses(hits+misses) 760system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53591 # number of demand (read+write) accesses 761system.cpu.l2cache.demand_accesses::cpu.itb.walker 11405 # number of demand (read+write) accesses 762system.cpu.l2cache.demand_accesses::cpu.inst 2182126 # number of demand (read+write) accesses 763system.cpu.l2cache.demand_accesses::total 2247122 # number of demand (read+write) accesses 764system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53591 # number of overall (read+write) accesses 765system.cpu.l2cache.overall_accesses::cpu.itb.walker 11405 # number of overall (read+write) accesses 766system.cpu.l2cache.overall_accesses::cpu.inst 2182126 # number of overall (read+write) accesses 767system.cpu.l2cache.overall_accesses::total 2247122 # number of overall (read+write) accesses 768system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000336 # miss rate for ReadReq accesses 769system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000175 # miss rate for ReadReq accesses 770system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012416 # miss rate for ReadReq accesses 771system.cpu.l2cache.ReadReq_miss_rate::total 0.012023 # miss rate for ReadReq accesses 772system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.991557 # miss rate for UpgradeReq accesses 773system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991557 # miss rate for UpgradeReq accesses 774system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.538765 # miss rate for ReadExReq accesses 775system.cpu.l2cache.ReadExReq_miss_rate::total 0.538765 # miss rate for ReadExReq accesses 776system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000336 # miss rate for demand accesses 777system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000175 # miss rate for demand accesses 778system.cpu.l2cache.demand_miss_rate::cpu.inst 0.072126 # miss rate for demand accesses 779system.cpu.l2cache.demand_miss_rate::total 0.070049 # miss rate for demand accesses 780system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000336 # miss rate for overall accesses 781system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000175 # miss rate for overall accesses 782system.cpu.l2cache.overall_miss_rate::cpu.inst 0.072126 # miss rate for overall accesses 783system.cpu.l2cache.overall_miss_rate::total 0.070049 # miss rate for overall accesses 784system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77125 # average ReadReq miss latency 785system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency 786system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72018.900916 # average ReadReq miss latency 787system.cpu.l2cache.ReadReq_avg_miss_latency::total 72022.951331 # average ReadReq miss latency 788system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 134.530995 # average UpgradeReq miss latency 789system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 134.530995 # average UpgradeReq miss latency 790system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69046.159640 # average ReadExReq miss latency 791system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69046.159640 # average ReadExReq miss latency 792system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77125 # average overall miss latency 793system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency 794system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69499.846018 # average overall miss latency 795system.cpu.l2cache.demand_avg_miss_latency::total 69500.784676 # average overall miss latency 796system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77125 # average overall miss latency 797system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency 798system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69499.846018 # average overall miss latency 799system.cpu.l2cache.overall_avg_miss_latency::total 69500.784676 # average overall miss latency 800system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 801system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 802system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 803system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 804system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 805system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 806system.cpu.l2cache.fast_writes 0 # number of fast writes performed 807system.cpu.l2cache.cache_copies 0 # number of cache copies performed 808system.cpu.l2cache.writebacks::writebacks 59840 # number of writebacks 809system.cpu.l2cache.writebacks::total 59840 # number of writebacks 810system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits 811system.cpu.l2cache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits 812system.cpu.l2cache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits 813system.cpu.l2cache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits 814system.cpu.l2cache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits 815system.cpu.l2cache.overall_mshr_hits::total 70 # number of overall MSHR hits 816system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 18 # number of ReadReq MSHR misses 817system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 818system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 23950 # number of ReadReq MSHR misses 819system.cpu.l2cache.ReadReq_mshr_misses::total 23970 # number of ReadReq MSHR misses 820system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2936 # number of UpgradeReq MSHR misses 821system.cpu.l2cache.UpgradeReq_mshr_misses::total 2936 # number of UpgradeReq MSHR misses 822system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 133369 # number of ReadExReq MSHR misses 823system.cpu.l2cache.ReadExReq_mshr_misses::total 133369 # number of ReadExReq MSHR misses 824system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 18 # number of demand (read+write) MSHR misses 825system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 826system.cpu.l2cache.demand_mshr_misses::cpu.inst 157319 # number of demand (read+write) MSHR misses 827system.cpu.l2cache.demand_mshr_misses::total 157339 # number of demand (read+write) MSHR misses 828system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 18 # number of overall MSHR misses 829system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 830system.cpu.l2cache.overall_mshr_misses::cpu.inst 157319 # number of overall MSHR misses 831system.cpu.l2cache.overall_mshr_misses::total 157339 # number of overall MSHR misses 832system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1165250 # number of ReadReq MSHR miss cycles 833system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles 834system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1425512750 # number of ReadReq MSHR miss cycles 835system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1426803000 # number of ReadReq MSHR miss cycles 836system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 29363936 # number of UpgradeReq MSHR miss cycles 837system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29363936 # number of UpgradeReq MSHR miss cycles 838system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7535729235 # number of ReadExReq MSHR miss cycles 839system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7535729235 # number of ReadExReq MSHR miss cycles 840system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1165250 # number of demand (read+write) MSHR miss cycles 841system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 842system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8961241985 # number of demand (read+write) MSHR miss cycles 843system.cpu.l2cache.demand_mshr_miss_latency::total 8962532235 # number of demand (read+write) MSHR miss cycles 844system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1165250 # number of overall MSHR miss cycles 845system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles 846system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8961241985 # number of overall MSHR miss cycles 847system.cpu.l2cache.overall_mshr_miss_latency::total 8962532235 # number of overall MSHR miss cycles 848system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 167312402000 # number of ReadReq MSHR uncacheable cycles 849system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167312402000 # number of ReadReq MSHR uncacheable cycles 850system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 16707876361 # number of WriteReq MSHR uncacheable cycles 851system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16707876361 # number of WriteReq MSHR uncacheable cycles 852system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 184020278361 # number of overall MSHR uncacheable cycles 853system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184020278361 # number of overall MSHR uncacheable cycles 854system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000336 # mshr miss rate for ReadReq accesses 855system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000175 # mshr miss rate for ReadReq accesses 856system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012380 # mshr miss rate for ReadReq accesses 857system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011988 # mshr miss rate for ReadReq accesses 858system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.991557 # mshr miss rate for UpgradeReq accesses 859system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991557 # mshr miss rate for UpgradeReq accesses 860system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.538765 # mshr miss rate for ReadExReq accesses 861system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.538765 # mshr miss rate for ReadExReq accesses 862system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000336 # mshr miss rate for demand accesses 863system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000175 # mshr miss rate for demand accesses 864system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.072094 # mshr miss rate for demand accesses 865system.cpu.l2cache.demand_mshr_miss_rate::total 0.070018 # mshr miss rate for demand accesses 866system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000336 # mshr miss rate for overall accesses 867system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000175 # mshr miss rate for overall accesses 868system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.072094 # mshr miss rate for overall accesses 869system.cpu.l2cache.overall_mshr_miss_rate::total 0.070018 # mshr miss rate for overall accesses 870system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64736.111111 # average ReadReq mshr miss latency 871system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency 872system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59520.365344 # average ReadReq mshr miss latency 873system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59524.530663 # average ReadReq mshr miss latency 874system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10001.340599 # average UpgradeReq mshr miss latency 875system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.340599 # average UpgradeReq mshr miss latency 876system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56502.854749 # average ReadExReq mshr miss latency 877system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56502.854749 # average ReadExReq mshr miss latency 878system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64736.111111 # average overall mshr miss latency 879system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 880system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56962.235871 # average overall mshr miss latency 881system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56963.195616 # average overall mshr miss latency 882system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64736.111111 # average overall mshr miss latency 883system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 884system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56962.235871 # average overall mshr miss latency 885system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56963.195616 # average overall mshr miss latency 886system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 887system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 888system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 889system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 890system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 891system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 892system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 893system.cpu.dcache.tags.replacements 637780 # number of replacements 894system.cpu.dcache.tags.tagsinuse 511.959208 # Cycle average of tags in use 895system.cpu.dcache.tags.total_refs 23638258 # Total number of references to valid blocks. 896system.cpu.dcache.tags.sampled_refs 638292 # Sample count of references to valid blocks. 897system.cpu.dcache.tags.avg_refs 37.033612 # Average number of references to valid blocks. 898system.cpu.dcache.tags.warmup_cycle 227414250 # Cycle when the warmup percentage was hit. 899system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959208 # Average occupied blocks per requestor 900system.cpu.dcache.tags.occ_percent::cpu.inst 0.999920 # Average percentage of cache occupancy 901system.cpu.dcache.tags.occ_percent::total 0.999920 # Average percentage of cache occupancy 902system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 903system.cpu.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id 904system.cpu.dcache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id 905system.cpu.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id 906system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 907system.cpu.dcache.tags.tag_accesses 98967232 # Number of tag accesses 908system.cpu.dcache.tags.data_accesses 98967232 # Number of data accesses 909system.cpu.dcache.ReadReq_hits::cpu.inst 13401610 # number of ReadReq hits 910system.cpu.dcache.ReadReq_hits::total 13401610 # number of ReadReq hits 911system.cpu.dcache.WriteReq_hits::cpu.inst 9749262 # number of WriteReq hits 912system.cpu.dcache.WriteReq_hits::total 9749262 # number of WriteReq hits 913system.cpu.dcache.LoadLockedReq_hits::cpu.inst 236772 # number of LoadLockedReq hits 914system.cpu.dcache.LoadLockedReq_hits::total 236772 # number of LoadLockedReq hits 915system.cpu.dcache.StoreCondReq_hits::cpu.inst 247602 # number of StoreCondReq hits 916system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits 917system.cpu.dcache.demand_hits::cpu.inst 23150872 # number of demand (read+write) hits 918system.cpu.dcache.demand_hits::total 23150872 # number of demand (read+write) hits 919system.cpu.dcache.overall_hits::cpu.inst 23150872 # number of overall hits 920system.cpu.dcache.overall_hits::total 23150872 # number of overall hits 921system.cpu.dcache.ReadReq_misses::cpu.inst 462868 # number of ReadReq misses 922system.cpu.dcache.ReadReq_misses::total 462868 # number of ReadReq misses 923system.cpu.dcache.WriteReq_misses::cpu.inst 473290 # number of WriteReq misses 924system.cpu.dcache.WriteReq_misses::total 473290 # number of WriteReq misses 925system.cpu.dcache.LoadLockedReq_misses::cpu.inst 10831 # number of LoadLockedReq misses 926system.cpu.dcache.LoadLockedReq_misses::total 10831 # number of LoadLockedReq misses 927system.cpu.dcache.demand_misses::cpu.inst 936158 # number of demand (read+write) misses 928system.cpu.dcache.demand_misses::total 936158 # number of demand (read+write) misses 929system.cpu.dcache.overall_misses::cpu.inst 936158 # number of overall misses 930system.cpu.dcache.overall_misses::total 936158 # number of overall misses 931system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7014286436 # number of ReadReq miss cycles 932system.cpu.dcache.ReadReq_miss_latency::total 7014286436 # number of ReadReq miss cycles 933system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21912161323 # number of WriteReq miss cycles 934system.cpu.dcache.WriteReq_miss_latency::total 21912161323 # number of WriteReq miss cycles 935system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 150765000 # number of LoadLockedReq miss cycles 936system.cpu.dcache.LoadLockedReq_miss_latency::total 150765000 # number of LoadLockedReq miss cycles 937system.cpu.dcache.demand_miss_latency::cpu.inst 28926447759 # number of demand (read+write) miss cycles 938system.cpu.dcache.demand_miss_latency::total 28926447759 # number of demand (read+write) miss cycles 939system.cpu.dcache.overall_miss_latency::cpu.inst 28926447759 # number of overall miss cycles 940system.cpu.dcache.overall_miss_latency::total 28926447759 # number of overall miss cycles 941system.cpu.dcache.ReadReq_accesses::cpu.inst 13864478 # number of ReadReq accesses(hits+misses) 942system.cpu.dcache.ReadReq_accesses::total 13864478 # number of ReadReq accesses(hits+misses) 943system.cpu.dcache.WriteReq_accesses::cpu.inst 10222552 # number of WriteReq accesses(hits+misses) 944system.cpu.dcache.WriteReq_accesses::total 10222552 # number of WriteReq accesses(hits+misses) 945system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 247603 # number of LoadLockedReq accesses(hits+misses) 946system.cpu.dcache.LoadLockedReq_accesses::total 247603 # number of LoadLockedReq accesses(hits+misses) 947system.cpu.dcache.StoreCondReq_accesses::cpu.inst 247602 # number of StoreCondReq accesses(hits+misses) 948system.cpu.dcache.StoreCondReq_accesses::total 247602 # number of StoreCondReq accesses(hits+misses) 949system.cpu.dcache.demand_accesses::cpu.inst 24087030 # number of demand (read+write) accesses 950system.cpu.dcache.demand_accesses::total 24087030 # number of demand (read+write) accesses 951system.cpu.dcache.overall_accesses::cpu.inst 24087030 # number of overall (read+write) accesses 952system.cpu.dcache.overall_accesses::total 24087030 # number of overall (read+write) accesses 953system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.033385 # miss rate for ReadReq accesses 954system.cpu.dcache.ReadReq_miss_rate::total 0.033385 # miss rate for ReadReq accesses 955system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.046299 # miss rate for WriteReq accesses 956system.cpu.dcache.WriteReq_miss_rate::total 0.046299 # miss rate for WriteReq accesses 957system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.043743 # miss rate for LoadLockedReq accesses 958system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043743 # miss rate for LoadLockedReq accesses 959system.cpu.dcache.demand_miss_rate::cpu.inst 0.038866 # miss rate for demand accesses 960system.cpu.dcache.demand_miss_rate::total 0.038866 # miss rate for demand accesses 961system.cpu.dcache.overall_miss_rate::cpu.inst 0.038866 # miss rate for overall accesses 962system.cpu.dcache.overall_miss_rate::total 0.038866 # miss rate for overall accesses 963system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15153.967083 # average ReadReq miss latency 964system.cpu.dcache.ReadReq_avg_miss_latency::total 15153.967083 # average ReadReq miss latency 965system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46297.537077 # average WriteReq miss latency 966system.cpu.dcache.WriteReq_avg_miss_latency::total 46297.537077 # average WriteReq miss latency 967system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13919.767335 # average LoadLockedReq miss latency 968system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13919.767335 # average LoadLockedReq miss latency 969system.cpu.dcache.demand_avg_miss_latency::cpu.inst 30899.108654 # average overall miss latency 970system.cpu.dcache.demand_avg_miss_latency::total 30899.108654 # average overall miss latency 971system.cpu.dcache.overall_avg_miss_latency::cpu.inst 30899.108654 # average overall miss latency 972system.cpu.dcache.overall_avg_miss_latency::total 30899.108654 # average overall miss latency 973system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 974system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 975system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 976system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 977system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 978system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 979system.cpu.dcache.fast_writes 0 # number of fast writes performed 980system.cpu.dcache.cache_copies 0 # number of cache copies performed 981system.cpu.dcache.writebacks::writebacks 602969 # number of writebacks 982system.cpu.dcache.writebacks::total 602969 # number of writebacks 983system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 82884 # number of ReadReq MSHR hits 984system.cpu.dcache.ReadReq_mshr_hits::total 82884 # number of ReadReq MSHR hits 985system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 222784 # number of WriteReq MSHR hits 986system.cpu.dcache.WriteReq_mshr_hits::total 222784 # number of WriteReq MSHR hits 987system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 68 # number of LoadLockedReq MSHR hits 988system.cpu.dcache.LoadLockedReq_mshr_hits::total 68 # number of LoadLockedReq MSHR hits 989system.cpu.dcache.demand_mshr_hits::cpu.inst 305668 # number of demand (read+write) MSHR hits 990system.cpu.dcache.demand_mshr_hits::total 305668 # number of demand (read+write) MSHR hits 991system.cpu.dcache.overall_mshr_hits::cpu.inst 305668 # number of overall MSHR hits 992system.cpu.dcache.overall_mshr_hits::total 305668 # number of overall MSHR hits 993system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 379984 # number of ReadReq MSHR misses 994system.cpu.dcache.ReadReq_mshr_misses::total 379984 # number of ReadReq MSHR misses 995system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 250506 # number of WriteReq MSHR misses 996system.cpu.dcache.WriteReq_mshr_misses::total 250506 # number of WriteReq MSHR misses 997system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 10763 # number of LoadLockedReq MSHR misses 998system.cpu.dcache.LoadLockedReq_mshr_misses::total 10763 # number of LoadLockedReq MSHR misses 999system.cpu.dcache.demand_mshr_misses::cpu.inst 630490 # number of demand (read+write) MSHR misses 1000system.cpu.dcache.demand_mshr_misses::total 630490 # number of demand (read+write) MSHR misses 1001system.cpu.dcache.overall_mshr_misses::cpu.inst 630490 # number of overall MSHR misses 1002system.cpu.dcache.overall_mshr_misses::total 630490 # number of overall MSHR misses 1003system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4859150309 # number of ReadReq MSHR miss cycles 1004system.cpu.dcache.ReadReq_mshr_miss_latency::total 4859150309 # number of ReadReq MSHR miss cycles 1005system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10668108512 # number of WriteReq MSHR miss cycles 1006system.cpu.dcache.WriteReq_mshr_miss_latency::total 10668108512 # number of WriteReq MSHR miss cycles 1007system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 128265000 # number of LoadLockedReq MSHR miss cycles 1008system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 128265000 # number of LoadLockedReq MSHR miss cycles 1009system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15527258821 # number of demand (read+write) MSHR miss cycles 1010system.cpu.dcache.demand_mshr_miss_latency::total 15527258821 # number of demand (read+write) MSHR miss cycles 1011system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 15527258821 # number of overall MSHR miss cycles 1012system.cpu.dcache.overall_mshr_miss_latency::total 15527258821 # number of overall MSHR miss cycles 1013system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182582279000 # number of ReadReq MSHR uncacheable cycles 1014system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182582279000 # number of ReadReq MSHR uncacheable cycles 1015system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058245639 # number of WriteReq MSHR uncacheable cycles 1016system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058245639 # number of WriteReq MSHR uncacheable cycles 1017system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208640524639 # number of overall MSHR uncacheable cycles 1018system.cpu.dcache.overall_mshr_uncacheable_latency::total 208640524639 # number of overall MSHR uncacheable cycles 1019system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.027407 # mshr miss rate for ReadReq accesses 1020system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027407 # mshr miss rate for ReadReq accesses 1021system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.024505 # mshr miss rate for WriteReq accesses 1022system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses 1023system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043469 # mshr miss rate for LoadLockedReq accesses 1024system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043469 # mshr miss rate for LoadLockedReq accesses 1025system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.026175 # mshr miss rate for demand accesses 1026system.cpu.dcache.demand_mshr_miss_rate::total 0.026175 # mshr miss rate for demand accesses 1027system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.026175 # mshr miss rate for overall accesses 1028system.cpu.dcache.overall_mshr_miss_rate::total 0.026175 # mshr miss rate for overall accesses 1029system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12787.776088 # average ReadReq mshr miss latency 1030system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12787.776088 # average ReadReq mshr miss latency 1031system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 42586.239499 # average WriteReq mshr miss latency 1032system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42586.239499 # average WriteReq mshr miss latency 1033system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11917.216389 # average LoadLockedReq mshr miss latency 1034system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11917.216389 # average LoadLockedReq mshr miss latency 1035system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24627.288016 # average overall mshr miss latency 1036system.cpu.dcache.demand_avg_mshr_miss_latency::total 24627.288016 # average overall mshr miss latency 1037system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24627.288016 # average overall mshr miss latency 1038system.cpu.dcache.overall_avg_mshr_miss_latency::total 24627.288016 # average overall mshr miss latency 1039system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1040system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1041system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 1042system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1043system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1044system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1045system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1046system.iocache.tags.replacements 0 # number of replacements 1047system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 1048system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1049system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 1050system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 1051system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1052system.iocache.tags.tag_accesses 0 # Number of tag accesses 1053system.iocache.tags.data_accesses 0 # Number of data accesses 1054system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1055system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1056system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1057system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1058system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1059system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1060system.iocache.fast_writes 0 # number of fast writes performed 1061system.iocache.cache_copies 0 # number of cache copies performed 1062system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1738541884500 # number of ReadReq MSHR uncacheable cycles 1063system.iocache.ReadReq_mshr_uncacheable_latency::total 1738541884500 # number of ReadReq MSHR uncacheable cycles 1064system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1738541884500 # number of overall MSHR uncacheable cycles 1065system.iocache.overall_mshr_uncacheable_latency::total 1738541884500 # number of overall MSHR uncacheable cycles 1066system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1067system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1068system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1069system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1070system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1073 1074---------- End Simulation Statistics ---------- | 1071 1072---------- End Simulation Statistics ---------- |