3,5c3,5
< sim_seconds 2.854926 # Number of seconds simulated
< sim_ticks 2854925996500 # Number of ticks simulated
< final_tick 2854925996500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.854886 # Number of seconds simulated
> sim_ticks 2854886132500 # Number of ticks simulated
> final_tick 2854886132500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 259837 # Simulator instruction rate (inst/s)
< host_op_rate 314167 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 6622138542 # Simulator tick rate (ticks/s)
< host_mem_usage 588096 # Number of bytes of host memory used
< host_seconds 431.12 # Real time elapsed on the host
< sim_insts 112020669 # Number of instructions simulated
< sim_ops 135443008 # Number of ops (including micro ops) simulated
---
> host_inst_rate 259825 # Simulator instruction rate (inst/s)
> host_op_rate 314145 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 6635713455 # Simulator tick rate (ticks/s)
> host_mem_usage 588360 # Number of bytes of host memory used
> host_seconds 430.23 # Real time elapsed on the host
> sim_insts 111784531 # Number of instructions simulated
> sim_ops 135154718 # Number of ops (including micro ops) simulated
16,20c16,20
< system.physmem.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.dtb.walker 7040 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 1667200 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9190572 # Number of bytes read from this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.dtb.walker 7232 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 1667840 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9176172 # Number of bytes read from this memory
22,25c22,25
< system.physmem.bytes_read::total 10865900 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1667200 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1667200 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7979712 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 10852268 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1667840 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1667840 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7959296 # Number of bytes written to this memory
27,31c27,31
< system.physmem.bytes_written::total 7997236 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.dtb.walker 110 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 26050 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 144124 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::total 7976820 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.dtb.walker 113 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 26060 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 143899 # Number of read requests responded to by this memory
33,34c33,34
< system.physmem.num_reads::total 170301 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 124683 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 170088 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 124364 # Number of write requests responded to by this memory
36,40c36,40
< system.physmem.num_writes::total 129064 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.dtb.walker 2466 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 583973 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3219198 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 128745 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 2533 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 584205 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3214199 # Total read bandwidth from this memory (bytes/s)
42,45c42,45
< system.physmem.bw_read::total 3806018 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 583973 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 583973 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2795068 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 3801296 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 584205 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 584205 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2787956 # Write bandwidth from this memory (bytes/s)
47,52c47,52
< system.physmem.bw_write::total 2801206 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2795068 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 2466 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 583973 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 3225336 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 2794094 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2787956 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 2533 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 584205 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 3220337 # Total bandwidth to/from this memory (bytes/s)
54,64c54,64
< system.physmem.bw_total::total 6607224 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 170301 # Number of read requests accepted
< system.physmem.writeReqs 129064 # Number of write requests accepted
< system.physmem.readBursts 170301 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 129064 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 10890496 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue
< system.physmem.bytesWritten 8010048 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 10865900 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7997236 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_total::total 6595390 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 170088 # Number of read requests accepted
> system.physmem.writeReqs 128745 # Number of write requests accepted
> system.physmem.readBursts 170088 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 128745 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 10876160 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7989120 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 10852268 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7976820 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue
67,98c67,98
< system.physmem.perBankRdBursts::0 10638 # Per bank write bursts
< system.physmem.perBankRdBursts::1 10529 # Per bank write bursts
< system.physmem.perBankRdBursts::2 10665 # Per bank write bursts
< system.physmem.perBankRdBursts::3 10242 # Per bank write bursts
< system.physmem.perBankRdBursts::4 13390 # Per bank write bursts
< system.physmem.perBankRdBursts::5 10196 # Per bank write bursts
< system.physmem.perBankRdBursts::6 10392 # Per bank write bursts
< system.physmem.perBankRdBursts::7 10920 # Per bank write bursts
< system.physmem.perBankRdBursts::8 10199 # Per bank write bursts
< system.physmem.perBankRdBursts::9 10416 # Per bank write bursts
< system.physmem.perBankRdBursts::10 10277 # Per bank write bursts
< system.physmem.perBankRdBursts::11 9652 # Per bank write bursts
< system.physmem.perBankRdBursts::12 10777 # Per bank write bursts
< system.physmem.perBankRdBursts::13 11476 # Per bank write bursts
< system.physmem.perBankRdBursts::14 10256 # Per bank write bursts
< system.physmem.perBankRdBursts::15 10139 # Per bank write bursts
< system.physmem.perBankWrBursts::0 7926 # Per bank write bursts
< system.physmem.perBankWrBursts::1 7916 # Per bank write bursts
< system.physmem.perBankWrBursts::2 8341 # Per bank write bursts
< system.physmem.perBankWrBursts::3 7830 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7635 # Per bank write bursts
< system.physmem.perBankWrBursts::5 7427 # Per bank write bursts
< system.physmem.perBankWrBursts::6 7524 # Per bank write bursts
< system.physmem.perBankWrBursts::7 8090 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7812 # Per bank write bursts
< system.physmem.perBankWrBursts::9 7846 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7622 # Per bank write bursts
< system.physmem.perBankWrBursts::11 7450 # Per bank write bursts
< system.physmem.perBankWrBursts::12 8154 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8593 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7575 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7416 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 10602 # Per bank write bursts
> system.physmem.perBankRdBursts::1 10348 # Per bank write bursts
> system.physmem.perBankRdBursts::2 10682 # Per bank write bursts
> system.physmem.perBankRdBursts::3 10189 # Per bank write bursts
> system.physmem.perBankRdBursts::4 13369 # Per bank write bursts
> system.physmem.perBankRdBursts::5 10294 # Per bank write bursts
> system.physmem.perBankRdBursts::6 10368 # Per bank write bursts
> system.physmem.perBankRdBursts::7 10838 # Per bank write bursts
> system.physmem.perBankRdBursts::8 10130 # Per bank write bursts
> system.physmem.perBankRdBursts::9 10489 # Per bank write bursts
> system.physmem.perBankRdBursts::10 10055 # Per bank write bursts
> system.physmem.perBankRdBursts::11 9592 # Per bank write bursts
> system.physmem.perBankRdBursts::12 10755 # Per bank write bursts
> system.physmem.perBankRdBursts::13 11804 # Per bank write bursts
> system.physmem.perBankRdBursts::14 10513 # Per bank write bursts
> system.physmem.perBankRdBursts::15 9912 # Per bank write bursts
> system.physmem.perBankWrBursts::0 7846 # Per bank write bursts
> system.physmem.perBankWrBursts::1 7741 # Per bank write bursts
> system.physmem.perBankWrBursts::2 8334 # Per bank write bursts
> system.physmem.perBankWrBursts::3 7790 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7606 # Per bank write bursts
> system.physmem.perBankWrBursts::5 7522 # Per bank write bursts
> system.physmem.perBankWrBursts::6 7517 # Per bank write bursts
> system.physmem.perBankWrBursts::7 7997 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7756 # Per bank write bursts
> system.physmem.perBankWrBursts::9 7896 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7435 # Per bank write bursts
> system.physmem.perBankWrBursts::11 7391 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8149 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8812 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7798 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7240 # Per bank write bursts
100,101c100,101
< system.physmem.numWrRetry 56 # Number of times write queue was full causing retry
< system.physmem.totGap 2854925546000 # Total gap between requests
---
> system.physmem.numWrRetry 69 # Number of times write queue was full causing retry
> system.physmem.totGap 2854885682000 # Total gap between requests
108c108
< system.physmem.readPktSize::6 169744 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 169531 # Read request sizes (log2)
115,119c115,119
< system.physmem.writePktSize::6 124683 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 160221 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 9636 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 294 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 124364 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 160094 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 9538 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 296 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
163,229c163,229
< system.physmem.wrQLenPdf::15 1833 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2641 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5947 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 6248 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6539 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6191 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6635 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 6984 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 7561 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 7557 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 8594 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 9006 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7531 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 7120 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 7083 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6851 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6591 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 453 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 463 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 366 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 298 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 246 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 263 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 286 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 255 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 211 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 270 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 254 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 268 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 280 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 200 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 256 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 235 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 219 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 209 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 188 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 208 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 231 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 203 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 214 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 246 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 160 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 98 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 138 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 60414 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 312.849340 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 185.889118 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 328.883375 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 21657 35.85% 35.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14616 24.19% 60.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6864 11.36% 71.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3516 5.82% 77.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2636 4.36% 81.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1611 2.67% 84.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1067 1.77% 86.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 953 1.58% 87.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7494 12.40% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 60414 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6196 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 27.463041 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 582.417033 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6195 99.98% 99.98% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 1848 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2664 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5925 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6226 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6598 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6259 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6588 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6880 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 7703 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 7446 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 8538 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 9004 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7391 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7010 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 7044 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6699 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6588 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6615 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 419 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 445 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 410 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 300 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 298 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 326 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 266 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 257 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 249 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 277 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 297 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 322 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 214 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 255 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 286 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 243 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 219 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 232 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 207 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 222 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 175 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 195 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 255 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 242 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 116 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 248 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 189 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 190 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 111 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 60347 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 312.612325 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 185.506399 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 329.136235 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 21716 35.99% 35.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 14599 24.19% 60.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6802 11.27% 71.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3528 5.85% 77.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2551 4.23% 81.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1581 2.62% 84.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1111 1.84% 85.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1010 1.67% 87.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7449 12.34% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 60347 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6172 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 27.532242 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 583.546907 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6171 99.98% 99.98% # Reads before turning the bus around for writes
231,259c231,258
< system.physmem.rdPerTurnAround::total 6196 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6196 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 20.199645 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.300177 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 15.412164 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5485 88.52% 88.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 67 1.08% 89.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 43 0.69% 90.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 35 0.56% 90.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 272 4.39% 95.26% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 29 0.47% 95.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 8 0.13% 95.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 11 0.18% 96.03% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 11 0.18% 96.21% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 3 0.05% 96.26% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 4 0.06% 96.32% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 7 0.11% 96.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 138 2.23% 98.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 3 0.05% 98.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 2 0.03% 98.74% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 7 0.11% 98.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 6 0.10% 98.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 1 0.02% 98.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 1 0.02% 98.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 1 0.02% 99.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 13 0.21% 99.21% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 2 0.03% 99.24% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 3 0.05% 99.29% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 12 0.19% 99.48% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 6172 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6172 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.225211 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.326492 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 15.268498 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5463 88.51% 88.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 63 1.02% 89.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 33 0.53% 90.07% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 41 0.66% 90.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 274 4.44% 95.17% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 26 0.42% 95.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 14 0.23% 95.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 8 0.13% 95.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 10 0.16% 96.11% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 4 0.06% 96.18% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 5 0.08% 96.26% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 7 0.11% 96.37% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 140 2.27% 98.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 5 0.08% 98.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 4 0.06% 98.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 6 0.10% 98.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 3 0.05% 98.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 2 0.03% 98.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 3 0.05% 99.01% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 1 0.02% 99.03% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 11 0.18% 99.21% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 3 0.05% 99.25% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 14 0.23% 99.48% # Writes before turning the bus around for reads
262,277c261,275
< system.physmem.wrPerTurnAround::140-143 3 0.05% 99.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 2 0.03% 99.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 1 0.02% 99.74% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 1 0.02% 99.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 1 0.02% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 3 0.05% 99.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::180-183 1 0.02% 99.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-187 1 0.02% 99.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::188-191 4 0.06% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-195 4 0.06% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6196 # Writes before turning the bus around for reads
< system.physmem.totQLat 4595967000 # Total ticks spent queuing
< system.physmem.totMemAccLat 7786542000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 850820000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 27009.04 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::140-143 6 0.10% 99.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 2 0.03% 99.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 2 0.03% 99.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 1 0.02% 99.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::172-175 2 0.03% 99.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-179 1 0.02% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::184-187 1 0.02% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::188-191 2 0.03% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-195 3 0.05% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::196-199 2 0.03% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6172 # Writes before turning the bus around for reads
> system.physmem.totQLat 4562123250 # Total ticks spent queuing
> system.physmem.totMemAccLat 7748498250 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 849700000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 26845.49 # Average queueing delay per DRAM burst
279c277
< system.physmem.avgMemAccLat 45759.04 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 45595.49 # Average memory access latency per DRAM burst
281,283c279,281
< system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgWrBW 2.80 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s
289,334c287,332
< system.physmem.avgWrQLen 23.01 # Average write queue length when enqueuing
< system.physmem.readRowHits 140583 # Number of row buffer hits during reads
< system.physmem.writeRowHits 94323 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 82.62 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 75.35 # Row buffer hit rate for writes
< system.physmem.avgGap 9536604.30 # Average gap between requests
< system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 218405460 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 116085255 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 620980080 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 327236580 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 6016710960.000001 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 4587085260 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 376629120 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 12457025670 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 8414413920 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 671932680540 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 705069857835 # Total energy per rank (pJ)
< system.physmem_0.averagePower 246.966071 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 2843548486750 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 708499000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 2558586000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 2794649429000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 21912527500 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 7778804250 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 27318150750 # Time in different power states
< system.physmem_1.actEnergy 212957640 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 113185875 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 593990880 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 326082960 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 6113824080.000001 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 4455367380 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 374460480 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 12365716800 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 8661645120 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 671979444945 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 705199696980 # Total energy per rank (pJ)
< system.physmem_1.averagePower 247.011550 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 2844173514000 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 705782750 # Time in different power states
< system.physmem_1.memoryStateTime::REF 2600572000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 2794499397250 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 22556418250 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 7446062750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 27117763500 # Time in different power states
< system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
---
> system.physmem.avgWrQLen 25.21 # Average write queue length when enqueuing
> system.physmem.readRowHits 140395 # Number of row buffer hits during reads
> system.physmem.writeRowHits 94027 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 82.61 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 75.31 # Row buffer hit rate for writes
> system.physmem.avgGap 9553448.52 # Average gap between requests
> system.physmem.pageHitRate 79.52 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 217784280 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 115755090 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 618966600 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 325482660 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 6028389120.000001 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 4546972650 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 380659200 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 12537712590 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 8446773120 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 671876398965 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 705097688865 # Total energy per rank (pJ)
> system.physmem_0.averagePower 246.979269 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 2843583812750 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 720868250 # Time in different power states
> system.physmem_0.memoryStateTime::REF 2563490000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 2794425375000 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 21996678750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 7684667500 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 27495053000 # Time in different power states
> system.physmem_1.actEnergy 213100440 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 113261775 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 594405000 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 326129940 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 6103375200.000001 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 4480349340 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 365416320 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 12364122510 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 8637319200 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 671971041390 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 705171178185 # Total energy per rank (pJ)
> system.physmem_1.averagePower 247.005010 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 2844103138750 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 682770250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 2596086000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 2794495958000 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 22493040000 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 7504072000 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 27114206250 # Time in different power states
> system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
347,349c345,347
< system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
---
> system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
356,360c354,358
< system.cpu.branchPred.lookups 31074836 # Number of BP lookups
< system.cpu.branchPred.condPredicted 16867509 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 2481345 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 18655029 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 10408802 # Number of BTB hits
---
> system.cpu.branchPred.lookups 31050902 # Number of BP lookups
> system.cpu.branchPred.condPredicted 16823011 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 2467385 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 18598277 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 10398347 # Number of BTB hits
362,368c360,366
< system.cpu.branchPred.BTBHitPct 55.796225 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 7856601 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 1514233 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 3068747 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 2872226 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 196521 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 109392 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.BTBHitPct 55.910271 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 7909634 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 1502216 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 3035557 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 2846976 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 188581 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 109207 # Number of mispredicted indirect branches.
370c368
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
400,414c398,411
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.cpu.dtb.walker.walks 68070 # Table walker walks requested
< system.cpu.dtb.walker.walksShort 68070 # Table walker walks initiated with short descriptors
< system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44787 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23283 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walkWaitTime::samples 68070 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0 68070 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::total 68070 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 7877 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 10134.378571 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 8445.879455 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 9567.630419 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-65535 7869 99.90% 99.90% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::65536-131071 6 0.08% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::131072-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.cpu.dtb.walker.walks 67916 # Table walker walks requested
> system.cpu.dtb.walker.walksShort 67916 # Table walker walks initiated with short descriptors
> system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44853 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23063 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walkWaitTime::samples 67916 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0 67916 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::total 67916 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 7871 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 10132.638801 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 8470.700593 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 9365.136659 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-65535 7864 99.91% 99.91% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::65536-131071 6 0.08% 99.99% # Table walker service (enqueue to completion) latency
416c413
< system.cpu.dtb.walker.walkCompletionTime::total 7877 # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.walkCompletionTime::total 7871 # Table walker service (enqueue to completion) latency
420,423c417,420
< system.cpu.dtb.walker.walkPageSizes::4K 6513 82.68% 82.68% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::1M 1364 17.32% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 7877 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 68070 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkPageSizes::4K 6482 82.35% 82.35% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::1M 1389 17.65% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 7871 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 67916 # Table walker requests started/completed, data/inst
425,426c422,423
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 68070 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7877 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 67916 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7871 # Table walker requests started/completed, data/inst
428,429c425,426
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7877 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 75947 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7871 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 75787 # Table walker requests started/completed, data/inst
432,435c429,432
< system.cpu.dtb.read_hits 24743648 # DTB read hits
< system.cpu.dtb.read_misses 61017 # DTB read misses
< system.cpu.dtb.write_hits 19435570 # DTB write hits
< system.cpu.dtb.write_misses 7053 # DTB write misses
---
> system.cpu.dtb.read_hits 24685993 # DTB read hits
> system.cpu.dtb.read_misses 61030 # DTB read misses
> system.cpu.dtb.write_hits 19409907 # DTB write hits
> system.cpu.dtb.write_misses 6886 # DTB write misses
440,442c437,439
< system.cpu.dtb.flush_entries 4279 # Number of entries that have been flushed from TLB
< system.cpu.dtb.align_faults 1461 # Number of TLB faults due to alignment restrictions
< system.cpu.dtb.prefetch_faults 1806 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.flush_entries 4276 # Number of entries that have been flushed from TLB
> system.cpu.dtb.align_faults 1444 # Number of TLB faults due to alignment restrictions
> system.cpu.dtb.prefetch_faults 1826 # Number of TLB faults due to prefetch
445,446c442,443
< system.cpu.dtb.read_accesses 24804665 # DTB read accesses
< system.cpu.dtb.write_accesses 19442623 # DTB write accesses
---
> system.cpu.dtb.read_accesses 24747023 # DTB read accesses
> system.cpu.dtb.write_accesses 19416793 # DTB write accesses
448,451c445,448
< system.cpu.dtb.hits 44179218 # DTB hits
< system.cpu.dtb.misses 68070 # DTB misses
< system.cpu.dtb.accesses 44247288 # DTB accesses
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.hits 44095900 # DTB hits
> system.cpu.dtb.misses 67916 # DTB misses
> system.cpu.dtb.accesses 44163816 # DTB accesses
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
481,495c478,492
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.cpu.itb.walker.walks 5855 # Table walker walks requested
< system.cpu.itb.walker.walksShort 5855 # Table walker walks initiated with short descriptors
< system.cpu.itb.walker.walksShortTerminationLevel::Level1 322 # Level at which table walker walks with short descriptors terminate
< system.cpu.itb.walker.walksShortTerminationLevel::Level2 5533 # Level at which table walker walks with short descriptors terminate
< system.cpu.itb.walker.walkWaitTime::samples 5855 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::0 5855 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::total 5855 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkCompletionTime::samples 3194 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::mean 10424.389480 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 8603.860466 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 6932.586443 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::0-8191 1846 57.80% 57.80% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::8192-16383 798 24.98% 82.78% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::16384-24575 544 17.03% 99.81% # Table walker service (enqueue to completion) latency
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.cpu.itb.walker.walks 5836 # Table walker walks requested
> system.cpu.itb.walker.walksShort 5836 # Table walker walks initiated with short descriptors
> system.cpu.itb.walker.walksShortTerminationLevel::Level1 323 # Level at which table walker walks with short descriptors terminate
> system.cpu.itb.walker.walksShortTerminationLevel::Level2 5513 # Level at which table walker walks with short descriptors terminate
> system.cpu.itb.walker.walkWaitTime::samples 5836 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::0 5836 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::total 5836 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkCompletionTime::samples 3199 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::mean 10502.500781 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 8663.235820 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 6980.719897 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::0-8191 1845 57.67% 57.67% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::8192-16383 784 24.51% 82.18% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::16384-24575 564 17.63% 99.81% # Table walker service (enqueue to completion) latency
498c495
< system.cpu.itb.walker.walkCompletionTime::total 3194 # Table walker service (enqueue to completion) latency
---
> system.cpu.itb.walker.walkCompletionTime::total 3199 # Table walker service (enqueue to completion) latency
502,504c499,501
< system.cpu.itb.walker.walkPageSizes::4K 2884 90.29% 90.29% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::1M 310 9.71% 100.00% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::total 3194 # Table walker page sizes translated
---
> system.cpu.itb.walker.walkPageSizes::4K 2889 90.31% 90.31% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::1M 310 9.69% 100.00% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::total 3199 # Table walker page sizes translated
506,507c503,504
< system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5855 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Requested::total 5855 # Table walker requests started/completed, data/inst
---
> system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5836 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Requested::total 5836 # Table walker requests started/completed, data/inst
509,513c506,510
< system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3194 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Completed::total 3194 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin::total 9049 # Table walker requests started/completed, data/inst
< system.cpu.itb.inst_hits 57481594 # ITB inst hits
< system.cpu.itb.inst_misses 5855 # ITB inst misses
---
> system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3199 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Completed::total 3199 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin::total 9035 # Table walker requests started/completed, data/inst
> system.cpu.itb.inst_hits 57468050 # ITB inst hits
> system.cpu.itb.inst_misses 5836 # ITB inst misses
522c519
< system.cpu.itb.flush_entries 2915 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_entries 2922 # Number of entries that have been flushed from TLB
526c523
< system.cpu.itb.perms_faults 8308 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 8340 # Number of TLB faults due to permissions restrictions
529,532c526,529
< system.cpu.itb.inst_accesses 57487449 # ITB inst accesses
< system.cpu.itb.hits 57481594 # DTB hits
< system.cpu.itb.misses 5855 # DTB misses
< system.cpu.itb.accesses 57487449 # DTB accesses
---
> system.cpu.itb.inst_accesses 57473886 # ITB inst accesses
> system.cpu.itb.hits 57468050 # DTB hits
> system.cpu.itb.misses 5836 # DTB misses
> system.cpu.itb.accesses 57473886 # DTB accesses
535,536c532,533
< system.cpu.pwrStateClkGateDist::mean 887934091.386746 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::stdev 17437787888.707882 # Distribution of time spent in the clock gated state
---
> system.cpu.pwrStateClkGateDist::mean 887944293.276624 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::stdev 17437791477.805088 # Distribution of time spent in the clock gated state
544c541
< system.cpu.pwrStateClkGateDist::max_value 499966196768 # Distribution of time spent in the clock gated state
---
> system.cpu.pwrStateClkGateDist::max_value 499966835544 # Distribution of time spent in the clock gated state
546,548c543,545
< system.cpu.pwrStateResidencyTicks::ON 161821897324 # Cumulative time (in ticks) in various power states
< system.cpu.pwrStateResidencyTicks::CLK_GATED 2693104099176 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 323646748 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 161751090992 # Cumulative time (in ticks) in various power states
> system.cpu.pwrStateResidencyTicks::CLK_GATED 2693135041508 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 323505132 # number of cpu cycles simulated
551,553c548,550
< system.cpu.committedInsts 112020669 # Number of instructions committed
< system.cpu.committedOps 135443008 # Number of ops (including micro ops) committed
< system.cpu.discardedOps 7814596 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.committedInsts 111784531 # Number of instructions committed
> system.cpu.committedOps 135154718 # Number of ops (including micro ops) committed
> system.cpu.discardedOps 7776689 # Number of ops (including micro ops) which were discarded before commit
555,557c552,554
< system.cpu.quiesceCycles 5386269471 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.cpi 2.889170 # CPI: cycles per instruction
< system.cpu.ipc 0.346120 # IPC: instructions per cycle
---
> system.cpu.quiesceCycles 5386331427 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.cpi 2.894006 # CPI: cycles per instruction
> system.cpu.ipc 0.345542 # IPC: instructions per cycle
559,591c556,588
< system.cpu.op_class_0::IntAlu 90804901 67.04% 67.04% # Class of committed instruction
< system.cpu.op_class_0::IntMult 113201 0.08% 67.13% # Class of committed instruction
< system.cpu.op_class_0::IntDiv 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::FloatAdd 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::FloatCmp 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::FloatCvt 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::FloatMult 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::FloatMultAcc 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::FloatDiv 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::FloatMisc 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::FloatSqrt 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::SimdAdd 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::SimdAlu 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::SimdCmp 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::SimdCvt 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::SimdMisc 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::SimdMult 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::SimdShift 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::SimdSqrt 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatMisc 8481 0.01% 67.13% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.13% # Class of committed instruction
< system.cpu.op_class_0::MemRead 24247912 17.90% 85.04% # Class of committed instruction
< system.cpu.op_class_0::MemWrite 20254880 14.95% 99.99% # Class of committed instruction
---
> system.cpu.op_class_0::IntAlu 90595549 67.03% 67.03% # Class of committed instruction
> system.cpu.op_class_0::IntMult 113150 0.08% 67.12% # Class of committed instruction
> system.cpu.op_class_0::IntDiv 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::FloatAdd 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::FloatCmp 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::FloatCvt 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::FloatMult 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::FloatMultAcc 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::FloatDiv 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::FloatMisc 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::FloatSqrt 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::SimdAdd 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::SimdAlu 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::SimdCmp 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::SimdCvt 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::SimdMisc 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::SimdMult 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::SimdShift 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::SimdSqrt 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatMisc 8471 0.01% 67.12% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.12% # Class of committed instruction
> system.cpu.op_class_0::MemRead 24195627 17.90% 85.02% # Class of committed instruction
> system.cpu.op_class_0::MemWrite 20228352 14.97% 99.99% # Class of committed instruction
593c590
< system.cpu.op_class_0::FloatMemWrite 8588 0.01% 100.00% # Class of committed instruction
---
> system.cpu.op_class_0::FloatMemWrite 8524 0.01% 100.00% # Class of committed instruction
596c593
< system.cpu.op_class_0::total 135443008 # Class of committed instruction
---
> system.cpu.op_class_0::total 135154718 # Class of committed instruction
599,606c596,603
< system.cpu.tickCycles 217947056 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 105699692 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 844723 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.945160 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 42637807 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 845235 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 50.444914 # Average number of references to valid blocks.
---
> system.cpu.tickCycles 217865051 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 105640081 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 843791 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.945118 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 42554576 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 844303 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 50.402019 # Average number of references to valid blocks.
608c605
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.945160 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.945118 # Average occupied blocks per requestor
612,614c609,611
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 364 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id
616,640c613,637
< system.cpu.dcache.tags.tag_accesses 176206878 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 176206878 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 23101260 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23101260 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 18273431 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 18273431 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 356861 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 356861 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 443340 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 443340 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 460050 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 460050 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 41374691 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 41374691 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 41731552 # number of overall hits
< system.cpu.dcache.overall_hits::total 41731552 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 465078 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 465078 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 548776 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 548776 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 169103 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 169103 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 22503 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 22503 # number of LoadLockedReq misses
---
> system.cpu.dcache.tags.tag_accesses 175868835 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 175868835 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 23043762 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23043762 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 18247268 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 18247268 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 357174 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 357174 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 443432 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 443432 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 460038 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 460038 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 41291030 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 41291030 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 41648204 # number of overall hits
> system.cpu.dcache.overall_hits::total 41648204 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 465012 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 465012 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 548381 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 548381 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 168658 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 168658 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 22398 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 22398 # number of LoadLockedReq misses
643,652c640,649
< system.cpu.dcache.demand_misses::cpu.data 1013854 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1013854 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1182957 # number of overall misses
< system.cpu.dcache.overall_misses::total 1182957 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 7334484000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7334484000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 26875060480 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 26875060480 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306737000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 306737000 # number of LoadLockedReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 1013393 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1013393 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1182051 # number of overall misses
> system.cpu.dcache.overall_misses::total 1182051 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 7327923000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7327923000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 26756956980 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 26756956980 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306920500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 306920500 # number of LoadLockedReq miss cycles
655,680c652,677
< system.cpu.dcache.demand_miss_latency::cpu.data 34209544480 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 34209544480 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 34209544480 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 34209544480 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 23566338 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23566338 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 18822207 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 18822207 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 525964 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 525964 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465843 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 465843 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 460052 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 460052 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 42388545 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42388545 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 42914509 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 42914509 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019735 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.019735 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029156 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.029156 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.321511 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.321511 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048306 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048306 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_miss_latency::cpu.data 34084879980 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 34084879980 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 34084879980 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 34084879980 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 23508774 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23508774 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 18795649 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 18795649 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 525832 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 525832 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465830 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 465830 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 460040 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 460040 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 42304423 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42304423 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 42830255 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 42830255 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019780 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.019780 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029176 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.029176 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.320745 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.320745 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048082 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048082 # miss rate for LoadLockedReq accesses
683,692c680,689
< system.cpu.dcache.demand_miss_rate::cpu.data 0.023918 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.023918 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.027565 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.027565 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15770.438507 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 15770.438507 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48972.732918 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 48972.732918 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13630.938097 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13630.938097 # average LoadLockedReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.023955 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.023955 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.027599 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.027599 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15758.567521 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 15758.567521 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48792.640482 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 48792.640482 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13703.031521 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13703.031521 # average LoadLockedReq miss latency
695,699c692,696
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 33742.081680 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 33742.081680 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 28918.671160 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 28918.671160 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 224 # number of cycles access was blocked
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 33634.414270 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 33634.414270 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 28835.371723 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 28835.371723 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked
703c700
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.666667 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.571429 # average number of cycles each access was blocked
705,724c702,721
< system.cpu.dcache.writebacks::writebacks 702249 # number of writebacks
< system.cpu.dcache.writebacks::total 702249 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45641 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 45641 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249535 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 249535 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14278 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 14278 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 295176 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 295176 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 295176 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 295176 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 419437 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 419437 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299241 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 299241 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121149 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 121149 # number of SoftPFReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8225 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 8225 # number of LoadLockedReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 701301 # number of writebacks
> system.cpu.dcache.writebacks::total 701301 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45802 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 45802 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249489 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 249489 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14157 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 14157 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 295291 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 295291 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 295291 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 295291 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 419210 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 419210 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298892 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 298892 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 120813 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 120813 # number of SoftPFReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8241 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 8241 # number of LoadLockedReq MSHR misses
727,730c724,727
< system.cpu.dcache.demand_mshr_misses::cpu.data 718678 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 718678 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 839827 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 839827 # number of overall MSHR misses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 718102 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 718102 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 838915 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 838915 # number of overall MSHR misses
737,744c734,741
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447841000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447841000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14303453000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 14303453000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1653166500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1653166500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 121747500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 121747500 # number of LoadLockedReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6438741500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6438741500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14235579000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 14235579000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1652909500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1652909500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 122323000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 122323000 # number of LoadLockedReq MSHR miss cycles
747,762c744,759
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20751294000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 20751294000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22404460500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 22404460500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6305636000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6305636000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6305636000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 6305636000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017798 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017798 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015898 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015898 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230337 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230337 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017656 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017656 # mshr miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20674320500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 20674320500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22327230000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 22327230000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6305432000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6305432000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6305432000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 6305432000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017832 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017832 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015902 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.229756 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.229756 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017691 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017691 # mshr miss rate for LoadLockedReq accesses
765,776c762,773
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016955 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.016955 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019570 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.019570 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15372.608997 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15372.608997 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47799.108411 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47799.108411 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13645.729639 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13645.729639 # average SoftPFReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14802.127660 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14802.127660 # average LoadLockedReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016975 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.016975 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019587 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.019587 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15359.226879 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15359.226879 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47627.835472 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47627.835472 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13681.553310 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13681.553310 # average SoftPFReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14843.222910 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14843.222910 # average LoadLockedReq mshr miss latency
779,794c776,791
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28874.258013 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 28874.258013 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26677.471074 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 26677.471074 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202558.175394 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202558.175394 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107395.782948 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107395.782948 # average overall mshr uncacheable latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 2891615 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.370867 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 54580851 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 2892127 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 18.872218 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 16116545500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.370867 # Average occupied blocks per requestor
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28790.228268 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 28790.228268 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26614.412664 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 26614.412664 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202551.622229 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202551.622229 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107392.308478 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107392.308478 # average overall mshr uncacheable latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 2889413 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.370681 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 54569461 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 2889925 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 18.882656 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 16116553500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.370681 # Average occupied blocks per requestor
798,800c795,797
< system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id
802,840c799,837
< system.cpu.icache.tags.tag_accesses 60365128 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 60365128 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 54580851 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 54580851 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 54580851 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 54580851 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 54580851 # number of overall hits
< system.cpu.icache.overall_hits::total 54580851 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 2892139 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 2892139 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 2892139 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 2892139 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 2892139 # number of overall misses
< system.cpu.icache.overall_misses::total 2892139 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 39804335500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 39804335500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 39804335500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 39804335500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 39804335500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 39804335500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 57472990 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 57472990 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 57472990 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 57472990 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 57472990 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 57472990 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050322 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.050322 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.050322 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.050322 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.050322 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.050322 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13762.939990 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13762.939990 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13762.939990 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13762.939990 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13762.939990 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13762.939990 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 60349332 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 60349332 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 54569461 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 54569461 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 54569461 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 54569461 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 54569461 # number of overall hits
> system.cpu.icache.overall_hits::total 54569461 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 2889936 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 2889936 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 2889936 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 2889936 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 2889936 # number of overall misses
> system.cpu.icache.overall_misses::total 2889936 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 39799359500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 39799359500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 39799359500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 39799359500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 39799359500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 39799359500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 57459397 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 57459397 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 57459397 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 57459397 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 57459397 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 57459397 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050295 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.050295 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.050295 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.050295 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.050295 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.050295 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13771.709650 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13771.709650 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13771.709650 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13771.709650 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13771.709650 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13771.709650 # average overall miss latency
847,854c844,851
< system.cpu.icache.writebacks::writebacks 2891615 # number of writebacks
< system.cpu.icache.writebacks::total 2891615 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2892139 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 2892139 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 2892139 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 2892139 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 2892139 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 2892139 # number of overall MSHR misses
---
> system.cpu.icache.writebacks::writebacks 2889413 # number of writebacks
> system.cpu.icache.writebacks::total 2889413 # number of writebacks
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2889936 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 2889936 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 2889936 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 2889936 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 2889936 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 2889936 # number of overall MSHR misses
859,864c856,861
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36912197500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 36912197500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36912197500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 36912197500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36912197500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 36912197500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36909424500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 36909424500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36909424500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 36909424500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36909424500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 36909424500 # number of overall MSHR miss cycles
869,880c866,877
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050322 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050322 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050322 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.050322 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050322 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.050322 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12762.940336 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12762.940336 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12762.940336 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12762.940336 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12762.940336 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12762.940336 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050295 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050295 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050295 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.050295 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050295 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.050295 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12771.709996 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12771.709996 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12771.709996 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12771.709996 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12771.709996 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12771.709996 # average overall mshr miss latency
885,940c882,938
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 97098 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65145.315179 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 7321379 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 162490 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 45.057413 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 271905816000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 69.248317 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.032949 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 12118.407979 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 52957.625933 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001057 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.184912 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.808069 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.994039 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65342 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 50 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4586 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60692 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000763 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997040 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 60089878 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 60089878 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68391 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3372 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 71763 # number of ReadReq hits
< system.cpu.l2cache.WritebackDirty_hits::writebacks 702249 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 702249 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 2840964 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 2840964 # number of WritebackClean hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 2784 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 2784 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 166689 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 166689 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2869145 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 2869145 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 534458 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 534458 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 68391 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 3372 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 2869145 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 701147 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 3642055 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 68391 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 3372 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 2869145 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 701147 # number of overall hits
< system.cpu.l2cache.overall_hits::total 3642055 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 110 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 112 # number of ReadReq misses
---
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 96873 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65145.709178 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 7314750 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 162275 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 45.076259 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 99924187000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 73.512854 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023684 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 12110.922280 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 52961.250360 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001122 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.184798 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.808125 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.994045 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65344 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 57 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4564 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60694 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000885 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 60034528 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 60034528 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 67803 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3361 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 71164 # number of ReadReq hits
> system.cpu.l2cache.WritebackDirty_hits::writebacks 701301 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 701301 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 2838672 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 2838672 # number of WritebackClean hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 2815 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 2815 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 166503 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 166503 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2866935 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 2866935 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 533944 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 533944 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 67803 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 3361 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 2866935 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 700447 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 3638546 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 67803 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 3361 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 2866935 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 700447 # number of overall hits
> system.cpu.l2cache.overall_hits::total 3638546 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 113 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 114 # number of ReadReq misses
945,963c943,961
< system.cpu.l2cache.ReadExReq_misses::cpu.data 129768 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 129768 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22956 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 22956 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14347 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 14347 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 110 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.inst 22956 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 144115 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 167183 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 110 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.inst 22956 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 144115 # number of overall misses
< system.cpu.l2cache.overall_misses::total 167183 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 35753500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 193000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 35946500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 129573 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 129573 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22965 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 22965 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14315 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 14315 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 113 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 22965 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 143888 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 166967 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 113 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 22965 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 143888 # number of overall misses
> system.cpu.l2cache.overall_misses::total 166967 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 38662500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 89500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 38752000 # number of ReadReq miss cycles
968,992c966,990
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12066822500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 12066822500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2380927500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 2380927500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1746972000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 1746972000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 35753500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 193000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 2380927500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 13813794500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 16230668500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 35753500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 193000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 2380927500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 13813794500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 16230668500 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68501 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3374 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 71875 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 702249 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 702249 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 2840964 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 2840964 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2790 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2790 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12000990500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 12000990500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2404531500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 2404531500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1744805500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 1744805500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 38662500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 89500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 2404531500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 13745796000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 16189079500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 38662500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 89500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 2404531500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 13745796000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 16189079500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 67916 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3362 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 71278 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 701301 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 701301 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 2838672 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 2838672 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2821 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2821 # number of UpgradeReq accesses(hits+misses)
995,1015c993,1013
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 296457 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 296457 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2892101 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 2892101 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 548805 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 548805 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68501 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 3374 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 2892101 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 845262 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 3809238 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68501 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 3374 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 2892101 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 845262 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 3809238 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001606 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000593 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.001558 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.002151 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.002151 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 296076 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 296076 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2889900 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 2889900 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 548259 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 548259 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 67916 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 3362 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 2889900 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 844335 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 3805513 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 67916 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 3362 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 2889900 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 844335 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 3805513 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001664 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000297 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.001599 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.002127 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.002127 # miss rate for UpgradeReq accesses
1018,1036c1016,1034
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437730 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.437730 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007937 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007937 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026142 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026142 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001606 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000593 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007937 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.170497 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.043889 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001606 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000593 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007937 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.170497 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.043889 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 325031.818182 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 96500 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 320950.892857 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437634 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.437634 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007947 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007947 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026110 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026110 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001664 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000297 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007947 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.170416 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.043875 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001664 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000297 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007947 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.170416 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.043875 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 342146.017699 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89500 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 339929.824561 # average ReadReq miss latency
1041,1056c1039,1054
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92987.658745 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92987.658745 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103717.002091 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103717.002091 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 121765.665296 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 121765.665296 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 325031.818182 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 96500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103717.002091 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95852.579537 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 97083.247100 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 325031.818182 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 96500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103717.002091 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95852.579537 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 97083.247100 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92619.531075 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92619.531075 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 104704.180274 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 104704.180274 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 121886.517639 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 121886.517639 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 342146.017699 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 104704.180274 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95531.218726 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 96959.755521 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 342146.017699 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 104704.180274 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95531.218726 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 96959.755521 # average overall miss latency
1063,1077c1061,1075
< system.cpu.l2cache.writebacks::writebacks 88493 # number of writebacks
< system.cpu.l2cache.writebacks::total 88493 # number of writebacks
< system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 14 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::total 14 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 145 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::total 145 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 145 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 159 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 145 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 159 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 110 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 112 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.writebacks::writebacks 88174 # number of writebacks
> system.cpu.l2cache.writebacks::total 88174 # number of writebacks
> system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 144 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::total 144 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 144 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 157 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 144 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 157 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 113 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 114 # number of ReadReq MSHR misses
1082,1097c1080,1095
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 129768 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 129768 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22942 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22942 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14202 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14202 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 110 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 22942 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 143970 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 167024 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 110 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 22942 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 143970 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 167024 # number of overall MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 129573 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 129573 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22952 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22952 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14171 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14171 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 113 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 22952 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 143744 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 166810 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 113 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 22952 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 143744 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 166810 # number of overall MSHR misses
1106,1108c1104,1106
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 34653500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 173000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 34826500 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 37532500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 79500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37612000 # number of ReadReq MSHR miss cycles
1113,1128c1111,1126
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10769142500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10769142500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2149471500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2149471500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1592398000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1592398000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 34653500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 173000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2149471500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12361540500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 14545838500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 34653500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 173000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2149471500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12361540500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 14545838500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10705260500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10705260500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2173786500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2173786500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1590255500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1590255500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 37532500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 79500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2173786500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12295516000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 14506914500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 37532500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 79500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2173786500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12295516000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 14506914500 # number of overall MSHR miss cycles
1130,1131c1128,1129
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5916431500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6133251000 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5916233500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6133053000 # number of ReadReq MSHR uncacheable cycles
1133,1139c1131,1137
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5916431500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6133251000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001606 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000593 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001558 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.002151 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.002151 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5916233500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6133053000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001664 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000297 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001599 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.002127 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.002127 # mshr miss rate for UpgradeReq accesses
1142,1160c1140,1158
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437730 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437730 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007933 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007933 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025878 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025878 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001606 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000593 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007933 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170326 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.043847 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001606 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000593 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007933 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170326 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.043847 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 86500 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 310950.892857 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437634 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437634 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007942 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007942 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025847 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025847 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001664 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000297 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007942 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170245 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.043834 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001664 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000297 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007942 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170245 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.043834 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 332146.017699 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 329929.824561 # average ReadReq mshr miss latency
1165,1180c1163,1178
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82987.658745 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82987.658745 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93691.548252 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93691.548252 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 112124.911984 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 112124.911984 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 86500 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93691.548252 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85861.919150 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87088.313656 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 315031.818182 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 86500 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93691.548252 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85861.919150 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87088.313656 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82619.531075 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82619.531075 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 94710.112409 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 94710.112409 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 112219.003599 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 112219.003599 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 332146.017699 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 94710.112409 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85537.594613 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86966.695642 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 332146.017699 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 94710.112409 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85537.594613 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86966.695642 # average overall mshr miss latency
1182,1183c1180,1181
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190055.621587 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 179078.250460 # average ReadReq mshr uncacheable latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190049.261163 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 179072.469269 # average ReadReq mshr uncacheable latency
1185,1191c1183,1189
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100766.963586 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 99190.577847 # average overall mshr uncacheable latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 7507397 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 3770030 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58003 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 175 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 175 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100763.591307 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 99187.375673 # average overall mshr uncacheable latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 7501348 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 3767098 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58079 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 189 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 189 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1193,1195c1191,1193
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadReq 136990 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 3578080 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadReq 136577 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 3574918 # Transaction distribution
1198,1201c1196,1199
< system.cpu.toL2Bus.trans_dist::WritebackDirty 790742 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 2891615 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 151079 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2790 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 789475 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 2889413 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 151189 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2821 # Transaction distribution
1203,1223c1201,1222
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2792 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 296457 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 296457 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 2892139 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 549026 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateReq 4412 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8682092 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2658406 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14762 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159854 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 11515114 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370357376 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99233193 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13496 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 274004 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 469878069 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 132782 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 5798856 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 4006498 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.022233 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.147442 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2823 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 296076 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 296076 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 2889936 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 548482 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateReq 4413 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateResp 16 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8675486 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2655698 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14711 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158895 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 11504790 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370075584 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99113193 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13448 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 271664 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 469473889 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 132758 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 5779048 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 4002764 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.022319 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.147720 # Request fanout histogram
1225,1226c1224,1225
< system.cpu.toL2Bus.snoop_fanout::0 3917420 97.78% 97.78% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 89078 2.22% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 3913425 97.77% 97.77% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 89339 2.23% 100.00% # Request fanout histogram
1231,1232c1230,1231
< system.cpu.toL2Bus.snoop_fanout::total 4006498 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 7428208500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 4002764 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 7421735500 # Layer occupancy (ticks)
1234c1233
< system.cpu.toL2Bus.snoopLayer0.occupancy 281377 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 289875 # Layer occupancy (ticks)
1236c1235
< system.cpu.toL2Bus.respLayer0.occupancy 4343459350 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 4340119421 # Layer occupancy (ticks)
1238c1237
< system.cpu.toL2Bus.respLayer1.occupancy 1314433554 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1313068534 # Layer occupancy (ticks)
1240c1239
< system.cpu.toL2Bus.respLayer2.occupancy 11390994 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 11352493 # Layer occupancy (ticks)
1242c1241
< system.cpu.toL2Bus.respLayer3.occupancy 91384437 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 91007942 # Layer occupancy (ticks)
1244c1243
< system.iobus.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
1295c1294
< system.iobus.reqLayer0.occupancy 46308000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer0.occupancy 46393500 # Layer occupancy (ticks)
1299c1298
< system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer2.occupancy 333000 # Layer occupancy (ticks)
1305c1304
< system.iobus.reqLayer7.occupancy 88500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks)
1307c1306
< system.iobus.reqLayer8.occupancy 618500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer8.occupancy 613000 # Layer occupancy (ticks)
1309c1308
< system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer10.occupancy 21500 # Layer occupancy (ticks)
1329c1328
< system.iobus.reqLayer23.occupancy 6088500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 6090000 # Layer occupancy (ticks)
1331c1330
< system.iobus.reqLayer24.occupancy 39091500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 39095500 # Layer occupancy (ticks)
1333c1332
< system.iobus.reqLayer25.occupancy 187755828 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 187683346 # Layer occupancy (ticks)
1339c1338
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
1341c1340
< system.iocache.tags.tagsinuse 1.033906 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.033754 # Cycle average of tags in use
1345,1348c1344,1347
< system.iocache.tags.warmup_cycle 272036495000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 1.033906 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.064619 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.064619 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 272028370000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 1.033754 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.064610 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.064610 # Average percentage of cache occupancy
1354c1353
< system.iocache.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
---
> system.iocache.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
1363,1370c1362,1369
< system.iocache.ReadReq_miss_latency::realview.ide 37411877 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 37411877 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::realview.ide 4363182951 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4363182951 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 4400594828 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 4400594828 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 4400594828 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 4400594828 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 29456377 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 29456377 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::realview.ide 4371874969 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4371874969 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 4401331346 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4401331346 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 4401331346 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4401331346 # number of overall miss cycles
1387,1394c1386,1393
< system.iocache.ReadReq_avg_miss_latency::realview.ide 159879.816239 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 159879.816239 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120450.059381 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 120450.059381 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 120703.133140 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 120703.133140 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 120703.133140 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 120703.133140 # average overall miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 125881.952991 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 125881.952991 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120690.011291 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 120690.011291 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 120723.334961 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 120723.334961 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 120723.334961 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 120723.334961 # average overall miss latency
1411,1418c1410,1417
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 25711877 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 25711877 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2549871160 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2549871160 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 2575583037 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 2575583037 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 2575583037 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 2575583037 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 17756377 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 17756377 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2558822831 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2558822831 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 2576579208 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2576579208 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 2576579208 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2576579208 # number of overall MSHR miss cycles
1427,1437c1426,1436
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 109879.816239 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 109879.816239 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70391.761263 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70391.761263 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 70645.209200 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 70645.209200 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 70645.209200 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 70645.209200 # average overall mshr miss latency
< system.membus.snoop_filter.tot_requests 337068 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 138136 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.membus.snoop_filter.hit_multi_requests 489 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75881.952991 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 75881.952991 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70638.881156 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70638.881156 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 70672.532997 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 70672.532997 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 70672.532997 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 70672.532997 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 336642 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 137901 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 539 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1441c1440
< system.membus.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
1443c1442
< system.membus.trans_dist::ReadResp 71739 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 71720 # Transaction distribution
1446,1447c1445,1446
< system.membus.trans_dist::WritebackDirty 124683 # Transaction distribution
< system.membus.trans_dist::CleanEvict 8839 # Transaction distribution
---
> system.membus.trans_dist::WritebackDirty 124364 # Transaction distribution
> system.membus.trans_dist::CleanEvict 8933 # Transaction distribution
1451,1453c1450,1452
< system.membus.trans_dist::ReadExReq 129646 # Transaction distribution
< system.membus.trans_dist::ReadExResp 129646 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 37490 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 129451 # Transaction distribution
> system.membus.trans_dist::ReadExResp 129451 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 37471 # Transaction distribution
1454a1454
> system.membus.trans_dist::InvalidateResp 4363 # Transaction distribution
1458,1459c1458,1459
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446846 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554414 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446194 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553762 # Packet count per connected master and slave (bytes)
1462c1462
< system.membus.pkt_count::total 627311 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 626659 # Packet count per connected master and slave (bytes)
1466,1467c1466,1467
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16546016 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16709801 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16511968 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16675753 # Cumulative packet size per connected master and slave (bytes)
1470,1475c1470,1475
< system.membus.pkt_size::total 19026921 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 505 # Total snoops (count)
< system.membus.snoopTraffic 32192 # Total snoop traffic (bytes)
< system.membus.snoop_fanout::samples 265323 # Request fanout histogram
< system.membus.snoop_fanout::mean 0.018540 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0.134893 # Request fanout histogram
---
> system.membus.pkt_size::total 18992873 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 4867 # Total snoops (count)
> system.membus.snoopTraffic 32128 # Total snoop traffic (bytes)
> system.membus.snoop_fanout::samples 265109 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.018562 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.134973 # Request fanout histogram
1477,1478c1477,1478
< system.membus.snoop_fanout::0 260404 98.15% 98.15% # Request fanout histogram
< system.membus.snoop_fanout::1 4919 1.85% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 260188 98.14% 98.14% # Request fanout histogram
> system.membus.snoop_fanout::1 4921 1.86% 100.00% # Request fanout histogram
1483,1484c1483,1484
< system.membus.snoop_fanout::total 265323 # Request fanout histogram
< system.membus.reqLayer0.occupancy 92820000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 265109 # Request fanout histogram
> system.membus.reqLayer0.occupancy 92913500 # Layer occupancy (ticks)
1488c1488
< system.membus.reqLayer2.occupancy 1700500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 1698000 # Layer occupancy (ticks)
1490c1490
< system.membus.reqLayer5.occupancy 905922529 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 904283412 # Layer occupancy (ticks)
1492c1492
< system.membus.respLayer2.occupancy 989794500 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 988660500 # Layer occupancy (ticks)
1494c1494
< system.membus.respLayer3.occupancy 1230123 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 5813415 # Layer occupancy (ticks)
1496,1502c1496,1502
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
1509,1510c1509,1510
< system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
---
> system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
1542,1548c1542,1548
< system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
---
> system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
1553,1564c1553,1564
< system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
< system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854925996500 # Cumulative time (in ticks) in various power states
---
> system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states
> system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states