7,11c7,11
< host_inst_rate 194204 # Simulator instruction rate (inst/s)
< host_op_rate 234807 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 4961098243 # Simulator tick rate (ticks/s)
< host_mem_usage 583728 # Number of bytes of host memory used
< host_seconds 576.18 # Real time elapsed on the host
---
> host_inst_rate 187730 # Simulator instruction rate (inst/s)
> host_op_rate 226980 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 4795719535 # Simulator tick rate (ticks/s)
> host_mem_usage 583724 # Number of bytes of host memory used
> host_seconds 596.05 # Real time elapsed on the host
654,655d653
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
704,707c702,703
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5085127500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5085127500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11363008500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 11363008500 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6277881000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 6277881000 # number of overall MSHR uncacheable cycles
738,742c734,735
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184357.303412 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184357.303412 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193541.389177 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193541.389177 # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106928.531280 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106928.531280 # average overall mshr uncacheable latency
801,802d793
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
841d831
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1021,1022d1010
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1092,1093d1079
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4767887000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4767887000 # number of WriteReq MSHR uncacheable cycles
1095,1096c1081,1082
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10656594000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11083812000 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5888707000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6315925000 # number of overall MSHR uncacheable cycles
1146,1147d1131
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172855.998260 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172855.998260 # average WriteReq mshr uncacheable latency
1149,1151c1133,1134
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181509.325339 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177414.796555 # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100299.892695 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 101096.856292 # average overall mshr uncacheable latency
1319,1322c1302,1305
< system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses
< system.iocache.demand_misses::total 234 # number of demand (read+write) misses
< system.iocache.overall_misses::realview.ide 234 # number of overall misses
< system.iocache.overall_misses::total 234 # number of overall misses
---
> system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses
> system.iocache.demand_misses::total 36458 # number of demand (read+write) misses
> system.iocache.overall_misses::realview.ide 36458 # number of overall misses
> system.iocache.overall_misses::total 36458 # number of overall misses
1327,1330c1310,1313
< system.iocache.demand_miss_latency::realview.ide 29059377 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 29059377 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 29059377 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 29059377 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 4578036502 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4578036502 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 4578036502 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4578036502 # number of overall miss cycles
1335,1338c1318,1321
< system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses
< system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses
> system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses
1351,1354c1334,1337
< system.iocache.demand_avg_miss_latency::realview.ide 124185.371795 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 124185.371795 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 124185.371795 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 124185.371795 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 125570.149268 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 125570.149268 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 125570.149268 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 125570.149268 # average overall miss latency
1361,1362d1343
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1369,1372c1350,1353
< system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses
1377,1380c1358,1361
< system.iocache.demand_mshr_miss_latency::realview.ide 17359377 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 17359377 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 17359377 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 17359377 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 2753710997 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2753710997 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 2753710997 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2753710997 # number of overall MSHR miss cycles
1393,1397c1374,1377
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 74185.371795 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 74185.371795 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 74185.371795 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 74185.371795 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency
< host_inst_rate 194204 # Simulator instruction rate (inst/s)
< host_op_rate 234807 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 4961098243 # Simulator tick rate (ticks/s)
< host_mem_usage 583728 # Number of bytes of host memory used
< host_seconds 576.18 # Real time elapsed on the host
---
> host_inst_rate 187730 # Simulator instruction rate (inst/s)
> host_op_rate 226980 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 4795719535 # Simulator tick rate (ticks/s)
> host_mem_usage 583724 # Number of bytes of host memory used
> host_seconds 596.05 # Real time elapsed on the host
654,655d653
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
704,707c702,703
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5085127500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5085127500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11363008500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 11363008500 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6277881000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 6277881000 # number of overall MSHR uncacheable cycles
738,742c734,735
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184357.303412 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184357.303412 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193541.389177 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193541.389177 # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106928.531280 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106928.531280 # average overall mshr uncacheable latency
801,802d793
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
841d831
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1021,1022d1010
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1092,1093d1079
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4767887000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4767887000 # number of WriteReq MSHR uncacheable cycles
1095,1096c1081,1082
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10656594000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11083812000 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5888707000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6315925000 # number of overall MSHR uncacheable cycles
1146,1147d1131
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172855.998260 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172855.998260 # average WriteReq mshr uncacheable latency
1149,1151c1133,1134
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181509.325339 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177414.796555 # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100299.892695 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 101096.856292 # average overall mshr uncacheable latency
1319,1322c1302,1305
< system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses
< system.iocache.demand_misses::total 234 # number of demand (read+write) misses
< system.iocache.overall_misses::realview.ide 234 # number of overall misses
< system.iocache.overall_misses::total 234 # number of overall misses
---
> system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses
> system.iocache.demand_misses::total 36458 # number of demand (read+write) misses
> system.iocache.overall_misses::realview.ide 36458 # number of overall misses
> system.iocache.overall_misses::total 36458 # number of overall misses
1327,1330c1310,1313
< system.iocache.demand_miss_latency::realview.ide 29059377 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 29059377 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 29059377 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 29059377 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 4578036502 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4578036502 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 4578036502 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4578036502 # number of overall miss cycles
1335,1338c1318,1321
< system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses
< system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses
> system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses
1351,1354c1334,1337
< system.iocache.demand_avg_miss_latency::realview.ide 124185.371795 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 124185.371795 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 124185.371795 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 124185.371795 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 125570.149268 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 125570.149268 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 125570.149268 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 125570.149268 # average overall miss latency
1361,1362d1343
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1369,1372c1350,1353
< system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses
1377,1380c1358,1361
< system.iocache.demand_mshr_miss_latency::realview.ide 17359377 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 17359377 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 17359377 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 17359377 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 2753710997 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2753710997 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 2753710997 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2753710997 # number of overall MSHR miss cycles
1393,1397c1374,1377
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 74185.371795 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 74185.371795 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 74185.371795 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 74185.371795 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency