3,5c3,5
< sim_seconds 2.858559 # Number of seconds simulated
< sim_ticks 2858558607500 # Number of ticks simulated
< final_tick 2858558607500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.858536 # Number of seconds simulated
> sim_ticks 2858536032500 # Number of ticks simulated
> final_tick 2858536032500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 164210 # Simulator instruction rate (inst/s)
< host_op_rate 198546 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 4188709682 # Simulator tick rate (ticks/s)
< host_mem_usage 583452 # Number of bytes of host memory used
< host_seconds 682.44 # Real time elapsed on the host
< sim_insts 112064376 # Number of instructions simulated
< sim_ops 135496266 # Number of ops (including micro ops) simulated
---
> host_inst_rate 177299 # Simulator instruction rate (inst/s)
> host_op_rate 214372 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 4522420422 # Simulator tick rate (ticks/s)
> host_mem_usage 585260 # Number of bytes of host memory used
> host_seconds 632.08 # Real time elapsed on the host
> sim_insts 112067614 # Number of instructions simulated
> sim_ops 135500271 # Number of ops (including micro ops) simulated
16,19c16,19
< system.physmem.bytes_read::cpu.dtb.walker 8064 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 1707776 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9151404 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.dtb.walker 8000 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 1708096 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9152172 # Number of bytes read from this memory
21,24c21,24
< system.physmem.bytes_read::total 10868268 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1707776 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1707776 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7938560 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 10869356 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1708096 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1708096 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7939328 # Number of bytes written to this memory
26,30c26,30
< system.physmem.bytes_written::total 7956084 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.dtb.walker 126 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 26684 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 143512 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::total 7956852 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.dtb.walker 125 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 26689 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 143524 # Number of read requests responded to by this memory
32,33c32,33
< system.physmem.num_reads::total 170338 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 124040 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 170355 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 124052 # Number of write requests responded to by this memory
35,39c35,39
< system.physmem.num_writes::total 128421 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.dtb.walker 2821 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 597426 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3201405 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 128433 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 2799 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 597542 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3201699 # Total read bandwidth from this memory (bytes/s)
41,44c41,44
< system.physmem.bw_read::total 3802010 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 597426 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 597426 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2777120 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 3802420 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 597542 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 597542 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2777411 # Write bandwidth from this memory (bytes/s)
46,51c46,51
< system.physmem.bw_write::total 2783250 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2777120 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 2821 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 597426 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 3207535 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 2783541 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2777411 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 2799 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 597542 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 3207829 # Total bandwidth to/from this memory (bytes/s)
53,63c53,63
< system.physmem.bw_total::total 6585260 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 170338 # Number of read requests accepted
< system.physmem.writeReqs 128421 # Number of write requests accepted
< system.physmem.readBursts 170338 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 128421 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 10893184 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 8448 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7968384 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 10868268 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7956084 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 132 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_total::total 6585961 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 170355 # Number of read requests accepted
> system.physmem.writeReqs 128433 # Number of write requests accepted
> system.physmem.readBursts 170355 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 128433 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 10894592 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 8128 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7969344 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 10869356 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7956852 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 127 # Number of DRAM read bursts serviced by the write queue
65,82c65,82
< system.physmem.neitherReadNorWriteReqs 49420 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 10768 # Per bank write bursts
< system.physmem.perBankRdBursts::1 10789 # Per bank write bursts
< system.physmem.perBankRdBursts::2 10902 # Per bank write bursts
< system.physmem.perBankRdBursts::3 10725 # Per bank write bursts
< system.physmem.perBankRdBursts::4 14061 # Per bank write bursts
< system.physmem.perBankRdBursts::5 10215 # Per bank write bursts
< system.physmem.perBankRdBursts::6 11008 # Per bank write bursts
< system.physmem.perBankRdBursts::7 10953 # Per bank write bursts
< system.physmem.perBankRdBursts::8 9930 # Per bank write bursts
< system.physmem.perBankRdBursts::9 10231 # Per bank write bursts
< system.physmem.perBankRdBursts::10 9936 # Per bank write bursts
< system.physmem.perBankRdBursts::11 9160 # Per bank write bursts
< system.physmem.perBankRdBursts::12 10275 # Per bank write bursts
< system.physmem.perBankRdBursts::13 11196 # Per bank write bursts
< system.physmem.perBankRdBursts::14 10249 # Per bank write bursts
< system.physmem.perBankRdBursts::15 9808 # Per bank write bursts
< system.physmem.perBankWrBursts::0 8070 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 10771 # Per bank write bursts
> system.physmem.perBankRdBursts::1 10790 # Per bank write bursts
> system.physmem.perBankRdBursts::2 10898 # Per bank write bursts
> system.physmem.perBankRdBursts::3 10736 # Per bank write bursts
> system.physmem.perBankRdBursts::4 14068 # Per bank write bursts
> system.physmem.perBankRdBursts::5 10207 # Per bank write bursts
> system.physmem.perBankRdBursts::6 11005 # Per bank write bursts
> system.physmem.perBankRdBursts::7 10952 # Per bank write bursts
> system.physmem.perBankRdBursts::8 9928 # Per bank write bursts
> system.physmem.perBankRdBursts::9 10232 # Per bank write bursts
> system.physmem.perBankRdBursts::10 9939 # Per bank write bursts
> system.physmem.perBankRdBursts::11 9163 # Per bank write bursts
> system.physmem.perBankRdBursts::12 10281 # Per bank write bursts
> system.physmem.perBankRdBursts::13 11195 # Per bank write bursts
> system.physmem.perBankRdBursts::14 10251 # Per bank write bursts
> system.physmem.perBankRdBursts::15 9812 # Per bank write bursts
> system.physmem.perBankWrBursts::0 8074 # Per bank write bursts
84,97c84,97
< system.physmem.perBankWrBursts::2 8537 # Per bank write bursts
< system.physmem.perBankWrBursts::3 8263 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7645 # Per bank write bursts
< system.physmem.perBankWrBursts::5 7425 # Per bank write bursts
< system.physmem.perBankWrBursts::6 7936 # Per bank write bursts
< system.physmem.perBankWrBursts::7 8025 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7562 # Per bank write bursts
< system.physmem.perBankWrBursts::9 7724 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7502 # Per bank write bursts
< system.physmem.perBankWrBursts::11 7049 # Per bank write bursts
< system.physmem.perBankWrBursts::12 7677 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8301 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7534 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7111 # Per bank write bursts
---
> system.physmem.perBankWrBursts::2 8532 # Per bank write bursts
> system.physmem.perBankWrBursts::3 8274 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7651 # Per bank write bursts
> system.physmem.perBankWrBursts::5 7419 # Per bank write bursts
> system.physmem.perBankWrBursts::6 7942 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8023 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7561 # Per bank write bursts
> system.physmem.perBankWrBursts::9 7722 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7504 # Per bank write bursts
> system.physmem.perBankWrBursts::11 7050 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7678 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8296 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7536 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7114 # Per bank write bursts
99,100c99,100
< system.physmem.numWrRetry 7 # Number of times write queue was full causing retry
< system.physmem.totGap 2858558162000 # Total gap between requests
---
> system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
> system.physmem.totGap 2858535588000 # Total gap between requests
107c107
< system.physmem.readPktSize::6 169781 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 169798 # Read request sizes (log2)
114,117c114,117
< system.physmem.writePktSize::6 124040 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 163465 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 6437 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 292 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 124052 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 163475 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 6450 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 291 # What read queue length does an incoming req see
162,228c162,228
< system.physmem.wrQLenPdf::15 2066 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2481 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 6095 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 6319 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6805 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6796 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 7303 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8169 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 8339 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 8103 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 9752 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7728 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 7120 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 7191 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6834 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6459 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6425 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 256 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 168 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 137 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 174 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 142 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 157 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 145 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 127 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 93 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 114 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 113 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 99 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 84 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 84 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 61 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 80 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 61 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 35 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 37 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 36 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 24 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 25 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 21 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 61425 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 307.065592 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 182.884404 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 323.926844 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 22406 36.48% 36.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14897 24.25% 60.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6725 10.95% 71.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3636 5.92% 77.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2599 4.23% 81.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1993 3.24% 85.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1038 1.69% 86.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1103 1.80% 88.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7028 11.44% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 61425 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6226 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 27.335689 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 568.600385 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6225 99.98% 99.98% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 1920 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2999 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 6966 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6332 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 7132 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6386 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6374 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6606 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 7201 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 6977 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 7506 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 8488 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7336 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7586 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 8729 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 7393 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 7050 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 7132 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 1109 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 326 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 234 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 153 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 129 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 147 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 100 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 104 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 116 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 106 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 143 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 94 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 137 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 98 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 132 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 77 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 46 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 82 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 64 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 68 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 75 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 61427 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 307.093102 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 182.837118 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 324.066728 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 22431 36.52% 36.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 14913 24.28% 60.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6673 10.86% 71.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3644 5.93% 77.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2598 4.23% 81.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2007 3.27% 85.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1018 1.66% 86.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1090 1.77% 88.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7053 11.48% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 61427 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6076 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 28.016458 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 575.560734 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6075 99.98% 99.98% # Reads before turning the bus around for writes
230,266c230,265
< system.physmem.rdPerTurnAround::total 6226 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6226 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 19.997751 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.449468 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 12.121367 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5404 86.80% 86.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 111 1.78% 88.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 39 0.63% 89.21% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 181 2.91% 92.11% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 25 0.40% 92.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 156 2.51% 95.02% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 42 0.67% 95.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 8 0.13% 95.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 19 0.31% 96.13% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 12 0.19% 96.32% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 4 0.06% 96.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 6 0.10% 96.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 165 2.65% 99.13% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 3 0.05% 99.18% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 4 0.06% 99.25% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 22 0.35% 99.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 2 0.03% 99.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 3 0.05% 99.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 1 0.02% 99.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 1 0.02% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 9 0.14% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 1 0.02% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 1 0.02% 99.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 1 0.02% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 3 0.05% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 2 0.03% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6226 # Writes before turning the bus around for reads
< system.physmem.totQLat 1816793750 # Total ticks spent queuing
< system.physmem.totMemAccLat 5008156250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 851030000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 10674.09 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 6076 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6075 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.495967 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.543257 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 14.157568 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5370 88.40% 88.40% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 94 1.55% 89.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 44 0.72% 90.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 49 0.81% 91.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 46 0.76% 92.23% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 25 0.41% 92.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 47 0.77% 93.42% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 10 0.16% 93.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 146 2.40% 95.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 3 0.05% 96.03% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 8 0.13% 96.16% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 10 0.16% 96.33% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 76 1.25% 97.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 4 0.07% 97.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 5 0.08% 97.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 24 0.40% 98.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 88 1.45% 99.57% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 2 0.03% 99.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 1 0.02% 99.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 8 0.13% 99.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 1 0.02% 99.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 8 0.13% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 2 0.03% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 2 0.03% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-179 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6075 # Writes before turning the bus around for reads
> system.physmem.totQLat 1806632250 # Total ticks spent queuing
> system.physmem.totMemAccLat 4998407250 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 851140000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 10613.01 # Average queueing delay per DRAM burst
268c267
< system.physmem.avgMemAccLat 29424.09 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 29363.01 # Average memory access latency per DRAM burst
278,280c277,279
< system.physmem.avgWrQLen 23.34 # Average write queue length when enqueuing
< system.physmem.readRowHits 139582 # Number of row buffer hits during reads
< system.physmem.writeRowHits 93704 # Number of row buffer hits during writes
---
> system.physmem.avgWrQLen 21.23 # Average write queue length when enqueuing
> system.physmem.readRowHits 139599 # Number of row buffer hits during reads
> system.physmem.writeRowHits 93721 # Number of row buffer hits during writes
282,283c281,282
< system.physmem.writeRowHitRate 75.24 # Row buffer hit rate for writes
< system.physmem.avgGap 9568107.28 # Average gap between requests
---
> system.physmem.writeRowHitRate 75.25 # Row buffer hit rate for writes
> system.physmem.avgGap 9567103.06 # Average gap between requests
285,295c284,294
< system.physmem_0.actEnergy 242131680 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 132115500 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 697483800 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 415018080 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 186707124240 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 87047496990 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1638777600000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1914018970290 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.574900 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 2726091168500 # Time in different power states
< system.physmem_0.memoryStateTime::REF 95453540000 # Time in different power states
---
> system.physmem_0.actEnergy 242282880 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 132198000 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 697530600 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 415063440 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 186705598560 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 87013655235 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1638793270500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1913999599215 # Total energy per rank (pJ)
> system.physmem_0.averagePower 669.573595 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 2726118833250 # Time in different power states
> system.physmem_0.memoryStateTime::REF 95452760000 # Time in different power states
297c296
< system.physmem_0.memoryStateTime::ACT 37013727750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 36964415750 # Time in different power states
299,301c298,300
< system.physmem_1.actEnergy 222241320 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 121262625 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 630115200 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 222075000 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 121171875 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 630240000 # Energy for read commands per rank (pJ)
303,309c302,308
< system.physmem_1.refreshEnergy 186707124240 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 85156608060 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1640436274500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1913665406745 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.451214 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 2728865158250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 95453540000 # Time in different power states
---
> system.physmem_1.refreshEnergy 186705598560 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 85155956550 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1640422830750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1913649653535 # Total energy per rank (pJ)
> system.physmem_1.averagePower 669.451174 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2728842952750 # Time in different power states
> system.physmem_1.memoryStateTime::REF 95452760000 # Time in different power states
311c310
< system.physmem_1.memoryStateTime::ACT 34239762750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 34240173750 # Time in different power states
331,335c330,334
< system.cpu.branchPred.lookups 31021791 # Number of BP lookups
< system.cpu.branchPred.condPredicted 16837881 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 2510623 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 18481524 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 13330573 # Number of BTB hits
---
> system.cpu.branchPred.lookups 31018850 # Number of BP lookups
> system.cpu.branchPred.condPredicted 16837096 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 2510697 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 18467994 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 13332341 # Number of BTB hits
337,339c336,338
< system.cpu.branchPred.BTBHitPct 72.129187 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 7835102 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 1517797 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 72.191603 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 7836957 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 1518082 # Number of incorrect RAS predictions.
370,381c369,380
< system.cpu.dtb.walker.walks 66394 # Table walker walks requested
< system.cpu.dtb.walker.walksShort 66394 # Table walker walks initiated with short descriptors
< system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43409 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22985 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walkWaitTime::samples 66394 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0 66394 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::total 66394 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 7806 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 12863.502434 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 10677.385301 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 8586.171053 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-32767 7798 99.90% 99.90% # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.walks 66340 # Table walker walks requested
> system.cpu.dtb.walker.walksShort 66340 # Table walker walks initiated with short descriptors
> system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43350 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22990 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walkWaitTime::samples 66340 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0 66340 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::total 66340 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 7812 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 12842.037890 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 10664.293591 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 8573.106392 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-32767 7804 99.90% 99.90% # Table walker service (enqueue to completion) latency
384c383
< system.cpu.dtb.walker.walkCompletionTime::total 7806 # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.walkCompletionTime::total 7812 # Table walker service (enqueue to completion) latency
388,391c387,390
< system.cpu.dtb.walker.walkPageSizes::4K 6430 82.37% 82.37% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::1M 1376 17.63% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 7806 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66394 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkPageSizes::4K 6422 82.21% 82.21% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::1M 1390 17.79% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 7812 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66340 # Table walker requests started/completed, data/inst
393,394c392,393
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66394 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7806 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66340 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7812 # Table walker requests started/completed, data/inst
396,397c395,396
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7806 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 74200 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7812 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 74152 # Table walker requests started/completed, data/inst
400,403c399,402
< system.cpu.dtb.read_hits 24767538 # DTB read hits
< system.cpu.dtb.read_misses 59423 # DTB read misses
< system.cpu.dtb.write_hits 19447940 # DTB write hits
< system.cpu.dtb.write_misses 6971 # DTB write misses
---
> system.cpu.dtb.read_hits 24767530 # DTB read hits
> system.cpu.dtb.read_misses 59359 # DTB read misses
> system.cpu.dtb.write_hits 19448397 # DTB write hits
> system.cpu.dtb.write_misses 6981 # DTB write misses
408,410c407,409
< system.cpu.dtb.flush_entries 4352 # Number of entries that have been flushed from TLB
< system.cpu.dtb.align_faults 1291 # Number of TLB faults due to alignment restrictions
< system.cpu.dtb.prefetch_faults 1803 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.flush_entries 4358 # Number of entries that have been flushed from TLB
> system.cpu.dtb.align_faults 1306 # Number of TLB faults due to alignment restrictions
> system.cpu.dtb.prefetch_faults 1806 # Number of TLB faults due to prefetch
412,414c411,413
< system.cpu.dtb.perms_faults 767 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 24826961 # DTB read accesses
< system.cpu.dtb.write_accesses 19454911 # DTB write accesses
---
> system.cpu.dtb.perms_faults 756 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 24826889 # DTB read accesses
> system.cpu.dtb.write_accesses 19455378 # DTB write accesses
416,418c415,417
< system.cpu.dtb.hits 44215478 # DTB hits
< system.cpu.dtb.misses 66394 # DTB misses
< system.cpu.dtb.accesses 44281872 # DTB accesses
---
> system.cpu.dtb.hits 44215927 # DTB hits
> system.cpu.dtb.misses 66340 # DTB misses
> system.cpu.dtb.accesses 44282267 # DTB accesses
448,449c447,448
< system.cpu.itb.walker.walks 5448 # Table walker walks requested
< system.cpu.itb.walker.walksShort 5448 # Table walker walks initiated with short descriptors
---
> system.cpu.itb.walker.walks 5454 # Table walker walks requested
> system.cpu.itb.walker.walksShort 5454 # Table walker walks initiated with short descriptors
451,454c450,453
< system.cpu.itb.walker.walksShortTerminationLevel::Level2 5127 # Level at which table walker walks with short descriptors terminate
< system.cpu.itb.walker.walkWaitTime::samples 5448 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::0 5448 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::total 5448 # Table walker wait (enqueue to first request) latency
---
> system.cpu.itb.walker.walksShortTerminationLevel::Level2 5133 # Level at which table walker walks with short descriptors terminate
> system.cpu.itb.walker.walkWaitTime::samples 5454 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::0 5454 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::total 5454 # Table walker wait (enqueue to first request) latency
456,460c455,459
< system.cpu.itb.walker.walkCompletionTime::mean 13028.710386 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 10952.783272 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 7366.378700 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::0-16383 2453 76.97% 76.97% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::16384-32767 733 23.00% 99.97% # Table walker service (enqueue to completion) latency
---
> system.cpu.itb.walker.walkCompletionTime::mean 13010.982115 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 10938.412651 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 7360.815983 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::0-16383 2457 77.09% 77.09% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::16384-32767 729 22.87% 99.97% # Table walker service (enqueue to completion) latency
470,471c469,470
< system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5448 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Requested::total 5448 # Table walker requests started/completed, data/inst
---
> system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5454 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Requested::total 5454 # Table walker requests started/completed, data/inst
475,477c474,476
< system.cpu.itb.walker.walkRequestOrigin::total 8635 # Table walker requests started/completed, data/inst
< system.cpu.itb.inst_hits 57565583 # ITB inst hits
< system.cpu.itb.inst_misses 5448 # ITB inst misses
---
> system.cpu.itb.walker.walkRequestOrigin::total 8641 # Table walker requests started/completed, data/inst
> system.cpu.itb.inst_hits 57568551 # ITB inst hits
> system.cpu.itb.inst_misses 5454 # ITB inst misses
490c489
< system.cpu.itb.perms_faults 8500 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 8464 # Number of TLB faults due to permissions restrictions
493,497c492,496
< system.cpu.itb.inst_accesses 57571031 # ITB inst accesses
< system.cpu.itb.hits 57565583 # DTB hits
< system.cpu.itb.misses 5448 # DTB misses
< system.cpu.itb.accesses 57571031 # DTB accesses
< system.cpu.numCycles 333209630 # number of cpu cycles simulated
---
> system.cpu.itb.inst_accesses 57574005 # ITB inst accesses
> system.cpu.itb.hits 57568551 # DTB hits
> system.cpu.itb.misses 5454 # DTB misses
> system.cpu.itb.accesses 57574005 # DTB accesses
> system.cpu.numCycles 333181944 # number of cpu cycles simulated
500,502c499,501
< system.cpu.committedInsts 112064376 # Number of instructions committed
< system.cpu.committedOps 135496266 # Number of ops (including micro ops) committed
< system.cpu.discardedOps 7785576 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.committedInsts 112067614 # Number of instructions committed
> system.cpu.committedOps 135500271 # Number of ops (including micro ops) committed
> system.cpu.discardedOps 7782146 # Number of ops (including micro ops) which were discarded before commit
504,506c503,505
< system.cpu.quiesceCycles 5383968359 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.cpi 2.973377 # CPI: cycles per instruction
< system.cpu.ipc 0.336318 # IPC: instructions per cycle
---
> system.cpu.quiesceCycles 5383950822 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.cpi 2.973044 # CPI: cycles per instruction
> system.cpu.ipc 0.336356 # IPC: instructions per cycle
509,515c508,514
< system.cpu.tickCycles 228553577 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 104656053 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.replacements 842821 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.899795 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 42614913 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 843333 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 50.531537 # Average number of references to valid blocks.
---
> system.cpu.tickCycles 228532556 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 104649388 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 842951 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.899807 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 42615127 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 843463 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 50.524003 # Average number of references to valid blocks.
517c516
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.899795 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.899807 # Average occupied blocks per requestor
521c520
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
523c522
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id
525,542c524,541
< system.cpu.dcache.tags.tag_accesses 176231729 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 176231729 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 23070027 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23070027 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 18281270 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 18281270 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 356578 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 356578 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 443846 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 443846 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 460293 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 460293 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 41351297 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 41351297 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 41707875 # number of overall hits
< system.cpu.dcache.overall_hits::total 41707875 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 494345 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 494345 # number of ReadReq misses
---
> system.cpu.dcache.tags.tag_accesses 176233418 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 176233418 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 23069734 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23069734 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 18281775 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 18281775 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 356571 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 356571 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 443857 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 443857 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 460299 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 460299 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 41351509 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 41351509 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 41708080 # number of overall hits
> system.cpu.dcache.overall_hits::total 41708080 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 494516 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 494516 # number of ReadReq misses
547,548c546,547
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 22262 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 22262 # number of LoadLockedReq misses
---
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 22259 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 22259 # number of LoadLockedReq misses
551,560c550,559
< system.cpu.dcache.demand_misses::cpu.data 1043035 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1043035 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1212813 # number of overall misses
< system.cpu.dcache.overall_misses::total 1212813 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 8029817000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 8029817000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 35659469481 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 35659469481 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 293513500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 293513500 # number of LoadLockedReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 1043206 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1043206 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1212984 # number of overall misses
> system.cpu.dcache.overall_misses::total 1212984 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 8031253000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 8031253000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 35635370481 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 35635370481 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 293366000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 293366000 # number of LoadLockedReq miss cycles
563,588c562,587
< system.cpu.dcache.demand_miss_latency::cpu.data 43689286481 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 43689286481 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 43689286481 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 43689286481 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 23564372 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23564372 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 18829960 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 18829960 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 526356 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 526356 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466108 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 466108 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 460295 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 460295 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 42394332 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42394332 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 42920688 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 42920688 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020978 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.020978 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029139 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.029139 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322554 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.322554 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047761 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047761 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_miss_latency::cpu.data 43666623481 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 43666623481 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 43666623481 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 43666623481 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 23564250 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23564250 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 18830465 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 18830465 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 526349 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 526349 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466116 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 466116 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 460301 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 460301 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 42394715 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42394715 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 42921064 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 42921064 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020986 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.020986 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029138 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.029138 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322558 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.322558 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047754 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047754 # miss rate for LoadLockedReq accesses
591,600c590,599
< system.cpu.dcache.demand_miss_rate::cpu.data 0.024603 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.024603 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.028257 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.028257 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16243.346246 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 16243.346246 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64990.193882 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 64990.193882 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13184.507232 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13184.507232 # average LoadLockedReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.024607 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.024607 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.028261 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.028261 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16240.633266 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 16240.633266 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64946.272906 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 64946.272906 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13179.657667 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13179.657667 # average LoadLockedReq miss latency
603,606c602,605
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 41886.692662 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 41886.692662 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 36023.102062 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 36023.102062 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 41858.102312 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 41858.102312 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 35999.340042 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 35999.340042 # average overall miss latency
615,632c614,631
< system.cpu.dcache.writebacks::writebacks 699997 # number of writebacks
< system.cpu.dcache.writebacks::total 699997 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76799 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 76799 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249722 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 249722 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 13994 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 13994 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 326521 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 326521 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 326521 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 326521 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417546 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 417546 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298968 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 298968 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121374 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 121374 # number of SoftPFReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 700113 # number of writebacks
> system.cpu.dcache.writebacks::total 700113 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76813 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 76813 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249717 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 249717 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 13991 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 13991 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 326530 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 326530 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 326530 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 326530 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417703 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 417703 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298973 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 298973 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121335 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 121335 # number of SoftPFReq MSHR misses
637,640c636,639
< system.cpu.dcache.demand_mshr_misses::cpu.data 716514 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 716514 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 837888 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 837888 # number of overall MSHR misses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 716676 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 716676 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 838011 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 838011 # number of overall MSHR misses
647,654c646,653
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6518403500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6518403500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19210408500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 19210408500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1713722500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1713722500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 116087000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 116087000 # number of LoadLockedReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6520814500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6520814500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19192223000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 19192223000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1711136500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1711136500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115838000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115838000 # number of LoadLockedReq MSHR miss cycles
657,668c656,667
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25728812000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 25728812000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27442534500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 27442534500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6277728500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6277728500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5083599000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5083599000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11361327500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 11361327500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017719 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017719 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25713037500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 25713037500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27424174000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 27424174000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6277780500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6277780500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5083615500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5083615500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11361396000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 11361396000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017726 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017726 # mshr miss rate for ReadReq accesses
671,672c670,671
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230593 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230593 # mshr miss rate for SoftPFReq accesses
---
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230522 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230522 # mshr miss rate for SoftPFReq accesses
677,688c676,687
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016901 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.016901 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019522 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.019522 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15611.222476 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15611.222476 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64255.734727 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64255.734727 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14119.354227 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14119.354227 # average SoftPFReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14040.517658 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14040.517658 # average LoadLockedReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016905 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.016905 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019524 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.019524 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15611.126805 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15611.126805 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64193.833557 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64193.833557 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14102.579635 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14102.579635 # average SoftPFReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14010.401548 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14010.401548 # average LoadLockedReq mshr miss latency
691,700c690,699
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35908.317214 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 35908.317214 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32752.031894 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 32752.031894 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201661.692901 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201661.692901 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184295.207367 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184295.207367 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193502.869844 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193502.869844 # average overall mshr uncacheable latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35878.189726 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 35878.189726 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32725.315061 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 32725.315061 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201663.363315 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201663.363315 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184295.805539 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184295.805539 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193504.036516 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193504.036516 # average overall mshr uncacheable latency
702,706c701,705
< system.cpu.icache.tags.replacements 2896771 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.208867 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 54659323 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 2897283 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 18.865718 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 2897049 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.208859 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 54662046 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 2897561 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 18.864847 # Average number of references to valid blocks.
708c707
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.208867 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.208859 # Average occupied blocks per requestor
712,714c711,713
< system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 198 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id
716,753c715,752
< system.cpu.icache.tags.tag_accesses 60453912 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 60453912 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 54659323 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 54659323 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 54659323 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 54659323 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 54659323 # number of overall hits
< system.cpu.icache.overall_hits::total 54659323 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 2897295 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 2897295 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 2897295 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 2897295 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 2897295 # number of overall misses
< system.cpu.icache.overall_misses::total 2897295 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 40482979500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 40482979500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 40482979500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 40482979500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 40482979500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 40482979500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 57556618 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 57556618 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 57556618 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 57556618 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 57556618 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 57556618 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050338 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.050338 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.050338 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.050338 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.050338 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.050338 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13972.681242 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13972.681242 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13972.681242 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13972.681242 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13972.681242 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13972.681242 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 60457191 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 60457191 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 54662046 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 54662046 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 54662046 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 54662046 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 54662046 # number of overall hits
> system.cpu.icache.overall_hits::total 54662046 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 2897573 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 2897573 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 2897573 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 2897573 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 2897573 # number of overall misses
> system.cpu.icache.overall_misses::total 2897573 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 40485768000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 40485768000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 40485768000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 40485768000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 40485768000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 40485768000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 57559619 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 57559619 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 57559619 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 57559619 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 57559619 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 57559619 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050340 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.050340 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.050340 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.050340 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.050340 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.050340 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13972.303027 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13972.303027 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13972.303027 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13972.303027 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13972.303027 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13972.303027 # average overall miss latency
762,769c761,768
< system.cpu.icache.writebacks::writebacks 2896771 # number of writebacks
< system.cpu.icache.writebacks::total 2896771 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897295 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 2897295 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 2897295 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 2897295 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 2897295 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 2897295 # number of overall MSHR misses
---
> system.cpu.icache.writebacks::writebacks 2897049 # number of writebacks
> system.cpu.icache.writebacks::total 2897049 # number of writebacks
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897573 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 2897573 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 2897573 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 2897573 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 2897573 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 2897573 # number of overall MSHR misses
774,779c773,778
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37585685500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 37585685500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37585685500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 37585685500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37585685500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 37585685500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37588196000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 37588196000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37588196000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 37588196000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37588196000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 37588196000 # number of overall MSHR miss cycles
784,795c783,794
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050338 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050338 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050338 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.050338 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050338 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.050338 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12972.681587 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12972.681587 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12972.681587 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12972.681587 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12972.681587 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12972.681587 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050340 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050340 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050340 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.050340 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050340 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.050340 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12972.303373 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12972.303373 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12972.303373 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12972.303373 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12972.303373 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12972.303373 # average overall mshr miss latency
801,805c800,804
< system.cpu.l2cache.tags.replacements 96429 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65020.981729 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 7029446 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 161675 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 43.478868 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 96446 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65019.357335 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 7030182 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 161691 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 43.479118 # Average number of references to valid blocks.
807,813c806,812
< system.cpu.l2cache.tags.occ_blocks::writebacks 47364.263187 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 66.053437 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000511 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 12253.462544 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 5337.202051 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.722721 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001008 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 47362.045211 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 65.242479 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.009917 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 12253.651278 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 5338.408451 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.722687 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000996 # Average percentage of cache occupancy
815,817c814,816
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186973 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.081439 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.992141 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186976 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.081458 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.992117 # Average percentage of cache occupancy
819c818
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65195 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65194 # Occupied blocks per task id
822,825c821,824
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2288 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6887 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55906 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2289 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6892 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55898 # Occupied blocks per task id
827,856c826,855
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994797 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 60471950 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 60471950 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 72267 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4708 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 76975 # number of ReadReq hits
< system.cpu.l2cache.WritebackDirty_hits::writebacks 699997 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 699997 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 2845126 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 2845126 # number of WritebackClean hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 50 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 50 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 165178 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 165178 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2874314 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 2874314 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 532946 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 532946 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 72267 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 4708 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 2874314 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 698124 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 3649413 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 72267 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 4708 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 2874314 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 698124 # number of overall hits
< system.cpu.l2cache.overall_hits::total 3649413 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 126 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses
---
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994781 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 60478007 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 60478007 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 72095 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4693 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 76788 # number of ReadReq hits
> system.cpu.l2cache.WritebackDirty_hits::writebacks 700113 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 700113 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 2845529 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 2845529 # number of WritebackClean hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 48 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 165186 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 165186 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2874588 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 2874588 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 533051 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 533051 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 72095 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 4693 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 2874588 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 698237 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 3649613 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 72095 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 4693 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 2874588 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 698237 # number of overall hits
> system.cpu.l2cache.overall_hits::total 3649613 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 125 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
858,859c857,858
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 2741 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 2741 # number of UpgradeReq misses
---
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 2737 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 2737 # number of UpgradeReq misses
862,882c861,881
< system.cpu.l2cache.ReadExReq_misses::cpu.data 131004 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 131004 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22956 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 22956 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14237 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 14237 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 126 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.inst 22956 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 145241 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 168324 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 126 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.inst 22956 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 145241 # number of overall misses
< system.cpu.l2cache.overall_misses::total 168324 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 17848000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 132500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 17980500 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 3067000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 3067000 # number of UpgradeReq miss cycles
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 131007 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 131007 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22960 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 22960 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14250 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 14250 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 125 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 22960 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 145257 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 168344 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 125 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 22960 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 145257 # number of overall misses
> system.cpu.l2cache.overall_misses::total 168344 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 17736500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 279000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 18015500 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2961500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 2961500 # number of UpgradeReq miss cycles
885,909c884,908
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16795048000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 16795048000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2992845000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 2992845000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1882606000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 1882606000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 17848000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 132500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 2992845000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 18677654000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 21688479500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 17848000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 132500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 2992845000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 18677654000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 21688479500 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 72393 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4709 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 77102 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 699997 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 699997 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 2845126 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 2845126 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2791 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2791 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16784670000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 16784670000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2992161000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 2992161000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1880931500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 1880931500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 17736500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 279000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 2992161000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 18665601500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 21675778000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 17736500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 279000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 2992161000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 18665601500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 21675778000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 72220 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4695 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 76915 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 700113 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 700113 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 2845529 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 2845529 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2785 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2785 # number of UpgradeReq accesses(hits+misses)
912,932c911,931
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 296182 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 296182 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2897270 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 2897270 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 547183 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 547183 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 72393 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 4709 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 2897270 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 843365 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 3817737 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 72393 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 4709 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 2897270 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 843365 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 3817737 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001740 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000212 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.001647 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.982085 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.982085 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 296193 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 296193 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2897548 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 2897548 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 547301 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 547301 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 72220 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 4695 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 2897548 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 843494 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 3817957 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 72220 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 4695 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 2897548 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 843494 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 3817957 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001731 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000426 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.001651 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.982765 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.982765 # miss rate for UpgradeReq accesses
935,955c934,954
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.442309 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.442309 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007923 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007923 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026019 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026019 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001740 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000212 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007923 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.172216 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.044090 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001740 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000212 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007923 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.172216 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.044090 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 141650.793651 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132500 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 141578.740157 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1118.934695 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1118.934695 # average UpgradeReq miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.442303 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.442303 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007924 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007924 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026037 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026037 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001731 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000426 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007924 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.172209 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.044093 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001731 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000426 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007924 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.172209 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.044093 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 141892 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 139500 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 141854.330709 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1082.024114 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1082.024114 # average UpgradeReq miss latency
958,973c957,972
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 128202.558700 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 128202.558700 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130373.105071 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130373.105071 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132233.335675 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132233.335675 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 141650.793651 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 132500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130373.105071 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128597.668702 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 128849.596611 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 141650.793651 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 132500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130373.105071 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128597.668702 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 128849.596611 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 128120.405780 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 128120.405780 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130320.601045 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130320.601045 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 131995.192982 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 131995.192982 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 141892 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 139500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130320.601045 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128500.530095 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 128758.839044 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 141892 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 139500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130320.601045 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128500.530095 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 128758.839044 # average overall miss latency
982,985c981,984
< system.cpu.l2cache.writebacks::writebacks 87850 # number of writebacks
< system.cpu.l2cache.writebacks::total 87850 # number of writebacks
< system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 24 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::total 24 # number of ReadCleanReq MSHR hits
---
> system.cpu.l2cache.writebacks::writebacks 87862 # number of writebacks
> system.cpu.l2cache.writebacks::total 87862 # number of writebacks
> system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 23 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::total 23 # number of ReadCleanReq MSHR hits
988c987
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 23 # number of demand (read+write) MSHR hits
990,991c989,990
< system.cpu.l2cache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 23 # number of overall MSHR hits
993,995c992,994
< system.cpu.l2cache.overall_mshr_hits::total 166 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 126 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.overall_mshr_hits::total 165 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 125 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
997,998c996,997
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2741 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 2741 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2737 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 2737 # number of UpgradeReq MSHR misses
1001,1016c1000,1015
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131004 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 131004 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22932 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22932 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14095 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14095 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 126 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 22932 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 145099 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 168158 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 126 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 22932 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 145099 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 168158 # number of overall MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131007 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 131007 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22937 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22937 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14108 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14108 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 125 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 22937 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 145115 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 168179 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 125 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 22937 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 145115 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 168179 # number of overall MSHR misses
1025,1029c1024,1028
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 16588000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 122500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16710500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 193945500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 193945500 # number of UpgradeReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 16486500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 259000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16745500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 186130000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 186130000 # number of UpgradeReq MSHR miss cycles
1032,1047c1031,1046
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15485008000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15485008000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2761851500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2761851500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1724788500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1724788500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 16588000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 122500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2761851500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17209796500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 19988358500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 16588000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 122500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2761851500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17209796500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 19988358500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15474600000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15474600000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2761139500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2761139500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1723039000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1723039000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 16486500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 259000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2761139500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17197639000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 19975524000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 16486500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 259000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2761139500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17197639000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 19975524000 # number of overall MSHR miss cycles
1049,1052c1048,1051
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888547000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6315765000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4766348500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4766348500 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888601000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6315819000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4766368000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4766368000 # number of WriteReq MSHR uncacheable cycles
1054,1060c1053,1059
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10654895500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11082113500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001740 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000212 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001647 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982085 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982085 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10654969000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11082187000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001731 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000426 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001651 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982765 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982765 # mshr miss rate for UpgradeReq accesses
1063,1083c1062,1082
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442309 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442309 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007915 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007915 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025759 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025759 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001740 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000212 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007915 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172048 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.044047 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001740 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000212 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007915 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172048 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.044047 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 131650.793651 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122500 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131578.740157 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70757.205399 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70757.205399 # average UpgradeReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442303 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442303 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007916 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007916 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025777 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025777 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001731 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000426 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007916 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172040 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.044049 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001731 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000426 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007916 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172040 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.044049 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 131892 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131854.330709 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68005.115090 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68005.115090 # average UpgradeReq mshr miss latency
1086,1101c1085,1100
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118202.558700 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118202.558700 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120436.573347 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120436.573347 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122368.818730 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122368.818730 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 131650.793651 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120436.573347 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118607.271587 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118866.533260 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 131650.793651 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120436.573347 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118607.271587 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118866.533260 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118120.405780 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118120.405780 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120379.278022 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120379.278022 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122132.052736 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122132.052736 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 131892 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120379.278022 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118510.415877 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118775.376236 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 131892 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120379.278022 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118510.415877 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118775.376236 # average overall mshr miss latency
1103,1106c1102,1105
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189159.877931 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181003.782994 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172793.956642 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172793.956642 # average WriteReq mshr uncacheable latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189161.612592 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181005.330582 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172794.663573 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172794.663573 # average WriteReq mshr uncacheable latency
1108,1109c1107,1108
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181471.122731 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177379.091506 # average overall mshr uncacheable latency
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181472.374561 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177380.267939 # average overall mshr uncacheable latency
1111,1113c1110,1112
< system.cpu.toL2Bus.snoop_filter.tot_requests 7512196 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 3771568 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58931 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_requests 7513127 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 3772095 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58799 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1117,1118c1116,1117
< system.cpu.toL2Bus.trans_dist::ReadReq 134847 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 3579536 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 134810 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 3579896 # Transaction distribution
1121,1124c1120,1123
< system.cpu.toL2Bus.trans_dist::WritebackDirty 824044 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 2845126 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 144354 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2791 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 824175 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 2897049 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 151656 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2785 # Transaction distribution
1126,1130c1125,1129
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2793 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 296182 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 296182 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 2897295 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 547417 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2787 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 296193 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 296193 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 2897573 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 547535 # Transaction distribution
1132,1145c1131,1144
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8647216 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2645494 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15284 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 161772 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 11469766 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 367754112 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98971817 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18836 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 289572 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 467034337 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 192407 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 4075202 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.021767 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.145921 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8699695 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2653154 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15282 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 161550 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 11529681 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 371094976 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98987561 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18780 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 288880 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 470390197 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 192578 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 4075586 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.021763 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.145909 # Request fanout histogram
1147,1148c1146,1147
< system.cpu.toL2Bus.snoop_fanout::0 3986498 97.82% 97.82% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 88704 2.18% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 3986889 97.82% 97.82% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 88697 2.18% 100.00% # Request fanout histogram
1153,1154c1152,1153
< system.cpu.toL2Bus.snoop_fanout::total 4075202 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 7433298000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 4075586 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 7434078000 # Layer occupancy (ticks)
1156c1155
< system.cpu.toL2Bus.snoopLayer0.occupancy 379376 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks)
1158c1157
< system.cpu.toL2Bus.respLayer0.occupancy 4352139390 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 4352565871 # Layer occupancy (ticks)
1160c1159
< system.cpu.toL2Bus.respLayer1.occupancy 1311523184 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1311717177 # Layer occupancy (ticks)
1162c1161
< system.cpu.toL2Bus.respLayer2.occupancy 10577994 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 10589994 # Layer occupancy (ticks)
1164c1163
< system.cpu.toL2Bus.respLayer3.occupancy 89414413 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 89368907 # Layer occupancy (ticks)
1216c1215
< system.iobus.reqLayer0.occupancy 46508500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer0.occupancy 46502500 # Layer occupancy (ticks)
1228c1227
< system.iobus.reqLayer8.occupancy 576500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer8.occupancy 612500 # Layer occupancy (ticks)
1250c1249
< system.iobus.reqLayer23.occupancy 6069000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 6064500 # Layer occupancy (ticks)
1254c1253
< system.iobus.reqLayer25.occupancy 186322027 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 187144507 # Layer occupancy (ticks)
1261c1260
< system.iocache.tags.tagsinuse 1.036865 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.036750 # Cycle average of tags in use
1265,1268c1264,1267
< system.iocache.tags.warmup_cycle 274891173000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 1.036865 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.064804 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.064804 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 274891170000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 1.036750 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.064797 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.064797 # Average percentage of cache occupancy
1282,1289c1281,1288
< system.iocache.ReadReq_miss_latency::realview.ide 29064376 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 29064376 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::realview.ide 4718637651 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4718637651 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 29064376 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 29064376 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 29064376 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 29064376 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 29054877 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 29054877 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::realview.ide 4549676630 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4549676630 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 29054877 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 29054877 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 29054877 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 29054877 # number of overall miss cycles
1306,1314c1305,1313
< system.iocache.ReadReq_avg_miss_latency::realview.ide 124206.735043 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 124206.735043 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130262.744341 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 130262.744341 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 124206.735043 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 124206.735043 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 124206.735043 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 124206.735043 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 864 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 124166.141026 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 124166.141026 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125598.405201 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 125598.405201 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 124166.141026 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 124166.141026 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 124166.141026 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 124166.141026 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1316c1315
< system.iocache.blocked::no_mshrs 82 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1318c1317
< system.iocache.avg_blocked_cycles::no_mshrs 10.536585 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1332,1339c1331,1338
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 17364376 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 17364376 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2907437651 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2907437651 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 17364376 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 17364376 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 17364376 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 17364376 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 17354877 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 17354877 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2737053618 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2737053618 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 17354877 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 17354877 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 17354877 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 17354877 # number of overall MSHR miss cycles
1348,1355c1347,1354
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74206.735043 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 74206.735043 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80262.744341 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80262.744341 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 74206.735043 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 74206.735043 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 74206.735043 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 74206.735043 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74166.141026 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 74166.141026 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75559.121522 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75559.121522 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 74166.141026 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 74166.141026 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 74166.141026 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 74166.141026 # average overall mshr miss latency
1358c1357
< system.membus.trans_dist::ReadResp 72281 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 72299 # Transaction distribution
1361,1362c1360,1361
< system.membus.trans_dist::WritebackDirty 124040 # Transaction distribution
< system.membus.trans_dist::CleanEvict 8592 # Transaction distribution
---
> system.membus.trans_dist::WritebackDirty 124052 # Transaction distribution
> system.membus.trans_dist::CleanEvict 8818 # Transaction distribution
1365,1368c1364,1367
< system.membus.trans_dist::UpgradeResp 4606 # Transaction distribution
< system.membus.trans_dist::ReadExReq 129141 # Transaction distribution
< system.membus.trans_dist::ReadExResp 129141 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 37388 # Transaction distribution
---
> system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
> system.membus.trans_dist::ReadExReq 129140 # Transaction distribution
> system.membus.trans_dist::ReadExResp 129140 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 37406 # Transaction distribution
1370d1368
< system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
1374,1378c1372,1376
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455331 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562899 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 671799 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450778 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558346 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 631243 # Packet count per connected master and slave (bytes)
1382,1383c1380,1381
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16507232 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16671017 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16509088 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16672873 # Cumulative packet size per connected master and slave (bytes)
1386c1384
< system.membus.pkt_size::total 18988137 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 18989993 # Cumulative packet size per connected master and slave (bytes)
1388c1386
< system.membus.snoop_fanout::samples 402696 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 402733 # Request fanout histogram
1393c1391
< system.membus.snoop_fanout::1 402696 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 402733 100.00% 100.00% # Request fanout histogram
1398,1399c1396,1397
< system.membus.snoop_fanout::total 402696 # Request fanout histogram
< system.membus.reqLayer0.occupancy 87390000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 402733 # Request fanout histogram
> system.membus.reqLayer0.occupancy 87415500 # Layer occupancy (ticks)
1403c1401
< system.membus.reqLayer2.occupancy 1706000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 1703000 # Layer occupancy (ticks)
1405c1403
< system.membus.reqLayer5.occupancy 878074394 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 878266116 # Layer occupancy (ticks)
1407c1405
< system.membus.respLayer2.occupancy 999225638 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 990100000 # Layer occupancy (ticks)
1409c1407
< system.membus.respLayer3.occupancy 64122797 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 1264123 # Layer occupancy (ticks)