3,5c3,5
< sim_seconds 2.852796 # Number of seconds simulated
< sim_ticks 2852795541500 # Number of ticks simulated
< final_tick 2852795541500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.852793 # Number of seconds simulated
> sim_ticks 2852793222500 # Number of ticks simulated
> final_tick 2852793222500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 152327 # Simulator instruction rate (inst/s)
< host_op_rate 184181 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 3876544573 # Simulator tick rate (ticks/s)
< host_mem_usage 573860 # Number of bytes of host memory used
< host_seconds 735.91 # Real time elapsed on the host
< sim_insts 112099513 # Number of instructions simulated
< sim_ops 135541235 # Number of ops (including micro ops) simulated
---
> host_inst_rate 170913 # Simulator instruction rate (inst/s)
> host_op_rate 206647 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 4363431399 # Simulator tick rate (ticks/s)
> host_mem_usage 626396 # Number of bytes of host memory used
> host_seconds 653.80 # Real time elapsed on the host
> sim_insts 111742418 # Number of instructions simulated
> sim_ops 135104867 # Number of ops (including micro ops) simulated
16,19c16,19
< system.physmem.bytes_read::cpu.dtb.walker 7488 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 1672384 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9151084 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.dtb.walker 7552 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 1671744 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9171756 # Number of bytes read from this memory
21,24c21,24
< system.physmem.bytes_read::total 10831980 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1672384 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1672384 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7949952 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 10852140 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1671744 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1671744 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7973376 # Number of bytes written to this memory
26,30c26,30
< system.physmem.bytes_written::total 7967476 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.dtb.walker 117 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 26131 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 143507 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::total 7990900 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.dtb.walker 118 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 26121 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 143830 # Number of read requests responded to by this memory
32,33c32,33
< system.physmem.num_reads::total 169771 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 124218 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 170086 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 124584 # Number of write requests responded to by this memory
35,39c35,39
< system.physmem.num_writes::total 128599 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.dtb.walker 2625 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 586226 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3207760 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 128965 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 2647 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 586003 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3215009 # Total read bandwidth from this memory (bytes/s)
41,44c41,44
< system.physmem.bw_read::total 3796970 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 586226 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 586226 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2786723 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 3804040 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 586003 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 586003 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2794937 # Write bandwidth from this memory (bytes/s)
46,51c46,51
< system.physmem.bw_write::total 2792866 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2786723 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 2625 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 586226 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 3213903 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 2801079 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2794937 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 2647 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 586003 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 3221152 # Total bandwidth to/from this memory (bytes/s)
53,97c53,97
< system.physmem.bw_total::total 6589836 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 169771 # Number of read requests accepted
< system.physmem.writeReqs 164823 # Number of write requests accepted
< system.physmem.readBursts 169771 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 164823 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 10857344 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue
< system.physmem.bytesWritten 9026432 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 10831980 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 10285812 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 23760 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 4596 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 10712 # Per bank write bursts
< system.physmem.perBankRdBursts::1 10437 # Per bank write bursts
< system.physmem.perBankRdBursts::2 10571 # Per bank write bursts
< system.physmem.perBankRdBursts::3 10533 # Per bank write bursts
< system.physmem.perBankRdBursts::4 13317 # Per bank write bursts
< system.physmem.perBankRdBursts::5 10551 # Per bank write bursts
< system.physmem.perBankRdBursts::6 11242 # Per bank write bursts
< system.physmem.perBankRdBursts::7 11054 # Per bank write bursts
< system.physmem.perBankRdBursts::8 10299 # Per bank write bursts
< system.physmem.perBankRdBursts::9 10415 # Per bank write bursts
< system.physmem.perBankRdBursts::10 10045 # Per bank write bursts
< system.physmem.perBankRdBursts::11 9308 # Per bank write bursts
< system.physmem.perBankRdBursts::12 10198 # Per bank write bursts
< system.physmem.perBankRdBursts::13 10751 # Per bank write bursts
< system.physmem.perBankRdBursts::14 10066 # Per bank write bursts
< system.physmem.perBankRdBursts::15 10147 # Per bank write bursts
< system.physmem.perBankWrBursts::0 8889 # Per bank write bursts
< system.physmem.perBankWrBursts::1 8834 # Per bank write bursts
< system.physmem.perBankWrBursts::2 9167 # Per bank write bursts
< system.physmem.perBankWrBursts::3 9119 # Per bank write bursts
< system.physmem.perBankWrBursts::4 8534 # Per bank write bursts
< system.physmem.perBankWrBursts::5 8844 # Per bank write bursts
< system.physmem.perBankWrBursts::6 9286 # Per bank write bursts
< system.physmem.perBankWrBursts::7 9148 # Per bank write bursts
< system.physmem.perBankWrBursts::8 9054 # Per bank write bursts
< system.physmem.perBankWrBursts::9 9024 # Per bank write bursts
< system.physmem.perBankWrBursts::10 8594 # Per bank write bursts
< system.physmem.perBankWrBursts::11 8355 # Per bank write bursts
< system.physmem.perBankWrBursts::12 8781 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8812 # Per bank write bursts
< system.physmem.perBankWrBursts::14 8169 # Per bank write bursts
< system.physmem.perBankWrBursts::15 8428 # Per bank write bursts
---
> system.physmem.bw_total::total 6605119 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 170086 # Number of read requests accepted
> system.physmem.writeReqs 165189 # Number of write requests accepted
> system.physmem.readBursts 170086 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 165189 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 10878016 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue
> system.physmem.bytesWritten 9060544 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 10852140 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 10309236 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 23589 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 4592 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 10719 # Per bank write bursts
> system.physmem.perBankRdBursts::1 10428 # Per bank write bursts
> system.physmem.perBankRdBursts::2 10712 # Per bank write bursts
> system.physmem.perBankRdBursts::3 10613 # Per bank write bursts
> system.physmem.perBankRdBursts::4 13554 # Per bank write bursts
> system.physmem.perBankRdBursts::5 10863 # Per bank write bursts
> system.physmem.perBankRdBursts::6 10988 # Per bank write bursts
> system.physmem.perBankRdBursts::7 10936 # Per bank write bursts
> system.physmem.perBankRdBursts::8 10331 # Per bank write bursts
> system.physmem.perBankRdBursts::9 10532 # Per bank write bursts
> system.physmem.perBankRdBursts::10 10066 # Per bank write bursts
> system.physmem.perBankRdBursts::11 9201 # Per bank write bursts
> system.physmem.perBankRdBursts::12 10334 # Per bank write bursts
> system.physmem.perBankRdBursts::13 10898 # Per bank write bursts
> system.physmem.perBankRdBursts::14 9868 # Per bank write bursts
> system.physmem.perBankRdBursts::15 9926 # Per bank write bursts
> system.physmem.perBankWrBursts::0 8834 # Per bank write bursts
> system.physmem.perBankWrBursts::1 8868 # Per bank write bursts
> system.physmem.perBankWrBursts::2 9254 # Per bank write bursts
> system.physmem.perBankWrBursts::3 9172 # Per bank write bursts
> system.physmem.perBankWrBursts::4 8841 # Per bank write bursts
> system.physmem.perBankWrBursts::5 9153 # Per bank write bursts
> system.physmem.perBankWrBursts::6 9171 # Per bank write bursts
> system.physmem.perBankWrBursts::7 9059 # Per bank write bursts
> system.physmem.perBankWrBursts::8 9082 # Per bank write bursts
> system.physmem.perBankWrBursts::9 9087 # Per bank write bursts
> system.physmem.perBankWrBursts::10 8650 # Per bank write bursts
> system.physmem.perBankWrBursts::11 8253 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8834 # Per bank write bursts
> system.physmem.perBankWrBursts::13 9086 # Per bank write bursts
> system.physmem.perBankWrBursts::14 8043 # Per bank write bursts
> system.physmem.perBankWrBursts::15 8184 # Per bank write bursts
99,100c99,100
< system.physmem.numWrRetry 51 # Number of times write queue was full causing retry
< system.physmem.totGap 2852795136500 # Total gap between requests
---
> system.physmem.numWrRetry 57 # Number of times write queue was full causing retry
> system.physmem.totGap 2852792816500 # Total gap between requests
107c107
< system.physmem.readPktSize::6 169214 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 169529 # Read request sizes (log2)
114,117c114,117
< system.physmem.writePktSize::6 160442 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 162758 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 6597 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 279 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 160808 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 162438 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 7239 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 280 # What read queue length does an incoming req see
162,182c162,182
< system.physmem.wrQLenPdf::15 1516 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 1699 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5280 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5852 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5924 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5946 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6342 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 6398 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 7894 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 6370 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 6428 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 7866 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 6812 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6543 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 8817 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 7197 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6972 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6804 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 1271 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 983 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 1250 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 1512 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 1780 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5363 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5964 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5965 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6140 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6462 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 7734 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 6362 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 6578 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 7861 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 6959 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6631 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 8774 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 7460 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 7276 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 1172 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 1027 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 1399 # What write queue length does an incoming req see
184,228c184,228
< system.physmem.wrQLenPdf::37 2008 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 1709 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 1835 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 2187 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 1851 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 1900 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 1690 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 1804 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 1636 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 1366 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 1353 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 1187 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 764 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 515 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 464 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 320 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 251 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 245 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 214 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 240 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 178 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 160 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 125 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 125 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 139 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 87 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 149 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 61582 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 322.881881 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 189.150015 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 338.764187 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 22212 36.07% 36.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14518 23.58% 59.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6522 10.59% 70.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3539 5.75% 75.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2583 4.19% 80.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1569 2.55% 82.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1183 1.92% 84.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1177 1.91% 86.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8279 13.44% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 61582 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5853 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 28.981890 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 585.529205 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 5852 99.98% 99.98% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::37 2324 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 1705 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 1727 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 2359 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 1811 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 2019 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 1582 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 1683 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 1336 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 1322 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 1503 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 1150 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 683 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 415 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 318 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 302 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 243 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 164 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 140 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 208 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 261 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 130 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 101 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 114 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 98 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 161 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 61793 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 322.665933 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 189.077551 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 338.586947 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 22269 36.04% 36.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 14610 23.64% 59.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6509 10.53% 70.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3452 5.59% 75.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2793 4.52% 80.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1471 2.38% 82.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1217 1.97% 84.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1102 1.78% 86.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8370 13.55% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 61793 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5884 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 28.884772 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 583.981749 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 5883 99.98% 99.98% # Reads before turning the bus around for writes
230,252c230,252
< system.physmem.rdPerTurnAround::total 5853 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5853 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 24.096703 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.379226 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 43.965113 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-31 5522 94.34% 94.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-47 97 1.66% 96.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-63 18 0.31% 96.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-79 12 0.21% 96.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-95 21 0.36% 96.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-111 25 0.43% 97.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-127 23 0.39% 97.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-143 16 0.27% 97.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-159 12 0.21% 98.17% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-175 2 0.03% 98.21% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-191 16 0.27% 98.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-207 11 0.19% 98.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::208-223 11 0.19% 98.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-239 5 0.09% 98.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::240-255 1 0.02% 98.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::256-271 1 0.02% 98.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::272-287 1 0.02% 98.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::288-303 9 0.15% 99.15% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 5884 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5884 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 24.060333 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.369950 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 43.410965 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-31 5554 94.39% 94.39% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-47 88 1.50% 95.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-63 18 0.31% 96.19% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-79 15 0.25% 96.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-95 30 0.51% 96.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-111 27 0.46% 97.42% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-127 26 0.44% 97.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-143 9 0.15% 98.01% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-159 10 0.17% 98.18% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-175 1 0.02% 98.20% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-191 18 0.31% 98.50% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-207 12 0.20% 98.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-223 8 0.14% 98.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-239 5 0.08% 98.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::240-255 2 0.03% 98.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-271 3 0.05% 99.01% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::272-287 2 0.03% 99.05% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::288-303 6 0.10% 99.15% # Writes before turning the bus around for reads
254,272c254,272
< system.physmem.wrPerTurnAround::320-335 2 0.03% 99.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::336-351 7 0.12% 99.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::352-367 16 0.27% 99.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::368-383 1 0.02% 99.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::384-399 2 0.03% 99.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::400-415 4 0.07% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::416-431 1 0.02% 99.81% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::432-447 3 0.05% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::448-463 1 0.02% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::512-527 1 0.02% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::544-559 1 0.02% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::560-575 2 0.03% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::688-703 2 0.03% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5853 # Writes before turning the bus around for reads
< system.physmem.totQLat 1681739444 # Total ticks spent queuing
< system.physmem.totMemAccLat 4862601944 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 848230000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 9913.23 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::320-335 3 0.05% 99.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::336-351 3 0.05% 99.35% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::352-367 16 0.27% 99.63% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::368-383 3 0.05% 99.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::400-415 2 0.03% 99.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::432-447 2 0.03% 99.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::464-479 1 0.02% 99.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::480-495 2 0.03% 99.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::496-511 1 0.02% 99.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::512-527 3 0.05% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::528-543 2 0.03% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::544-559 2 0.03% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::560-575 3 0.05% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::576-591 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5884 # Writes before turning the bus around for reads
> system.physmem.totQLat 1705654500 # Total ticks spent queuing
> system.physmem.totMemAccLat 4892573250 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 849845000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 10035.09 # Average queueing delay per DRAM burst
274c274
< system.physmem.avgMemAccLat 28663.23 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 28785.09 # Average memory access latency per DRAM burst
276c276
< system.physmem.avgWrBW 3.16 # Average achieved write bandwidth in MiByte/s
---
> system.physmem.avgWrBW 3.18 # Average achieved write bandwidth in MiByte/s
283,294c283,294
< system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 25.33 # Average write queue length when enqueuing
< system.physmem.readRowHits 140075 # Number of row buffer hits during reads
< system.physmem.writeRowHits 109026 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 82.57 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 77.29 # Row buffer hit rate for writes
< system.physmem.avgGap 8526139.55 # Average gap between requests
< system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 241398360 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 131715375 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 689652600 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 465400080 # Energy for write commands per rank (pJ)
---
> system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 22.27 # Average write queue length when enqueuing
> system.physmem.readRowHits 140294 # Number of row buffer hits during reads
> system.physmem.writeRowHits 109452 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 82.54 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 77.30 # Row buffer hit rate for writes
> system.physmem.avgGap 8508814.60 # Average gap between requests
> system.physmem.pageHitRate 80.16 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 242736480 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 132445500 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 692741400 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 468840960 # Energy for write commands per rank (pJ)
296,300c296,300
< system.physmem_0.actBackEnergy 83595060855 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1638344286000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1909797794550 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.449413 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 2725393996990 # Time in different power states
---
> system.physmem_0.actBackEnergy 83545935120 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1638387378750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1909800359490 # Total energy per rank (pJ)
> system.physmem_0.averagePower 669.450312 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 2725465336224 # Time in different power states
303c303
< system.physmem_0.memoryStateTime::ACT 32133948010 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 32062608776 # Time in different power states
305,308c305,308
< system.physmem_1.actEnergy 224161560 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 122310375 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 633578400 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 448526160 # Energy for write commands per rank (pJ)
---
> system.physmem_1.actEnergy 224418600 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 122450625 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 633009000 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 448539120 # Energy for write commands per rank (pJ)
310,314c310,314
< system.physmem_1.actBackEnergy 82127793645 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1639631362500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1909518013920 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.351340 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 2727553667240 # Time in different power states
---
> system.physmem_1.actBackEnergy 82219424850 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1639550984250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1909529107725 # Total energy per rank (pJ)
> system.physmem_1.averagePower 669.355229 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2727414398224 # Time in different power states
317c317
< system.physmem_1.memoryStateTime::ACT 29980898760 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 30117847276 # Time in different power states
337,341c337,341
< system.cpu.branchPred.lookups 31028841 # Number of BP lookups
< system.cpu.branchPred.condPredicted 16848703 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 2523288 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 18558243 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 13348746 # Number of BTB hits
---
> system.cpu.branchPred.lookups 31001883 # Number of BP lookups
> system.cpu.branchPred.condPredicted 16796453 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 2502337 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 18460820 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 13284720 # Number of BTB hits
343,345c343,345
< system.cpu.branchPred.BTBHitPct 71.928932 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 7829101 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 1515846 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 71.961701 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 7904518 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 1496209 # Number of incorrect RAS predictions.
376,390c376,390
< system.cpu.dtb.walker.walks 66007 # Table walker walks requested
< system.cpu.dtb.walker.walksShort 66007 # Table walker walks initiated with short descriptors
< system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43361 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22646 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walkWaitTime::samples 66007 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0 66007 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::total 66007 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 7799 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 11136.363636 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 8861.352080 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 7418.451261 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-16383 6073 77.87% 77.87% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::16384-32767 1719 22.04% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.97% # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.walks 66819 # Table walker walks requested
> system.cpu.dtb.walker.walksShort 66819 # Table walker walks initiated with short descriptors
> system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43911 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22908 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walkWaitTime::samples 66819 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0 66819 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::total 66819 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 7827 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 11026.574677 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 8748.919938 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 7443.454079 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-16383 6102 77.96% 77.96% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::16384-32767 1719 21.96% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.97% # Table walker service (enqueue to completion) latency
393c393
< system.cpu.dtb.walker.walkCompletionTime::total 7799 # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.walkCompletionTime::total 7827 # Table walker service (enqueue to completion) latency
397,400c397,400
< system.cpu.dtb.walker.walkPageSizes::4K 6423 82.36% 82.36% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::1M 1376 17.64% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 7799 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66007 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkPageSizes::4K 6438 82.25% 82.25% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::1M 1389 17.75% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 7827 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66819 # Table walker requests started/completed, data/inst
402,403c402,403
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66007 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7799 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66819 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7827 # Table walker requests started/completed, data/inst
405,406c405,406
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7799 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 73806 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7827 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 74646 # Table walker requests started/completed, data/inst
409,412c409,412
< system.cpu.dtb.read_hits 24765986 # DTB read hits
< system.cpu.dtb.read_misses 59321 # DTB read misses
< system.cpu.dtb.write_hits 19441821 # DTB write hits
< system.cpu.dtb.write_misses 6686 # DTB write misses
---
> system.cpu.dtb.read_hits 24698795 # DTB read hits
> system.cpu.dtb.read_misses 59886 # DTB read misses
> system.cpu.dtb.write_hits 19408206 # DTB write hits
> system.cpu.dtb.write_misses 6933 # DTB write misses
417,419c417,419
< system.cpu.dtb.flush_entries 4350 # Number of entries that have been flushed from TLB
< system.cpu.dtb.align_faults 1269 # Number of TLB faults due to alignment restrictions
< system.cpu.dtb.prefetch_faults 1784 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.flush_entries 4360 # Number of entries that have been flushed from TLB
> system.cpu.dtb.align_faults 1246 # Number of TLB faults due to alignment restrictions
> system.cpu.dtb.prefetch_faults 1786 # Number of TLB faults due to prefetch
421,423c421,423
< system.cpu.dtb.perms_faults 729 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 24825307 # DTB read accesses
< system.cpu.dtb.write_accesses 19448507 # DTB write accesses
---
> system.cpu.dtb.perms_faults 745 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 24758681 # DTB read accesses
> system.cpu.dtb.write_accesses 19415139 # DTB write accesses
425,427c425,427
< system.cpu.dtb.hits 44207807 # DTB hits
< system.cpu.dtb.misses 66007 # DTB misses
< system.cpu.dtb.accesses 44273814 # DTB accesses
---
> system.cpu.dtb.hits 44107001 # DTB hits
> system.cpu.dtb.misses 66819 # DTB misses
> system.cpu.dtb.accesses 44173820 # DTB accesses
457,470c457,470
< system.cpu.itb.walker.walks 5444 # Table walker walks requested
< system.cpu.itb.walker.walksShort 5444 # Table walker walks initiated with short descriptors
< system.cpu.itb.walker.walksShortTerminationLevel::Level1 317 # Level at which table walker walks with short descriptors terminate
< system.cpu.itb.walker.walksShortTerminationLevel::Level2 5127 # Level at which table walker walks with short descriptors terminate
< system.cpu.itb.walker.walkWaitTime::samples 5444 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::0 5444 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::total 5444 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkCompletionTime::samples 3189 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::mean 11300.094073 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 9048.158428 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 7023.995661 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::0-8191 1265 39.67% 39.67% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::8192-16383 1207 37.85% 77.52% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::16384-24575 716 22.45% 99.97% # Table walker service (enqueue to completion) latency
---
> system.cpu.itb.walker.walks 5459 # Table walker walks requested
> system.cpu.itb.walker.walksShort 5459 # Table walker walks initiated with short descriptors
> system.cpu.itb.walker.walksShortTerminationLevel::Level1 321 # Level at which table walker walks with short descriptors terminate
> system.cpu.itb.walker.walksShortTerminationLevel::Level2 5138 # Level at which table walker walks with short descriptors terminate
> system.cpu.itb.walker.walkWaitTime::samples 5459 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::0 5459 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::total 5459 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkCompletionTime::samples 3190 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::mean 11236.050157 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 8968.317634 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 7059.322929 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::0-8191 1291 40.47% 40.47% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::8192-16383 1179 36.96% 77.43% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::16384-24575 719 22.54% 99.97% # Table walker service (enqueue to completion) latency
472c472
< system.cpu.itb.walker.walkCompletionTime::total 3189 # Table walker service (enqueue to completion) latency
---
> system.cpu.itb.walker.walkCompletionTime::total 3190 # Table walker service (enqueue to completion) latency
476c476
< system.cpu.itb.walker.walkPageSizes::4K 2879 90.28% 90.28% # Table walker page sizes translated
---
> system.cpu.itb.walker.walkPageSizes::4K 2880 90.28% 90.28% # Table walker page sizes translated
478c478
< system.cpu.itb.walker.walkPageSizes::total 3189 # Table walker page sizes translated
---
> system.cpu.itb.walker.walkPageSizes::total 3190 # Table walker page sizes translated
480,481c480,481
< system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5444 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Requested::total 5444 # Table walker requests started/completed, data/inst
---
> system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5459 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Requested::total 5459 # Table walker requests started/completed, data/inst
483,487c483,487
< system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3189 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Completed::total 3189 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin::total 8633 # Table walker requests started/completed, data/inst
< system.cpu.itb.inst_hits 57608448 # ITB inst hits
< system.cpu.itb.inst_misses 5444 # ITB inst misses
---
> system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3190 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Completed::total 3190 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin::total 8649 # Table walker requests started/completed, data/inst
> system.cpu.itb.inst_hits 57544146 # ITB inst hits
> system.cpu.itb.inst_misses 5459 # ITB inst misses
500c500
< system.cpu.itb.perms_faults 8408 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 8374 # Number of TLB faults due to permissions restrictions
503,507c503,507
< system.cpu.itb.inst_accesses 57613892 # ITB inst accesses
< system.cpu.itb.hits 57608448 # DTB hits
< system.cpu.itb.misses 5444 # DTB misses
< system.cpu.itb.accesses 57613892 # DTB accesses
< system.cpu.numCycles 315454477 # number of cpu cycles simulated
---
> system.cpu.itb.inst_accesses 57549605 # ITB inst accesses
> system.cpu.itb.hits 57544146 # DTB hits
> system.cpu.itb.misses 5459 # DTB misses
> system.cpu.itb.accesses 57549605 # DTB accesses
> system.cpu.numCycles 315425036 # number of cpu cycles simulated
510,512c510,512
< system.cpu.committedInsts 112099513 # Number of instructions committed
< system.cpu.committedOps 135541235 # Number of ops (including micro ops) committed
< system.cpu.discardedOps 7725935 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.committedInsts 111742418 # Number of instructions committed
> system.cpu.committedOps 135104867 # Number of ops (including micro ops) committed
> system.cpu.discardedOps 7746377 # Number of ops (including micro ops) which were discarded before commit
514,516c514,516
< system.cpu.quiesceCycles 5390197145 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.cpi 2.814058 # CPI: cycles per instruction
< system.cpu.ipc 0.355359 # IPC: instructions per cycle
---
> system.cpu.quiesceCycles 5390221882 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.cpi 2.822787 # CPI: cycles per instruction
> system.cpu.ipc 0.354260 # IPC: instructions per cycle
519,525c519,525
< system.cpu.tickCycles 227606231 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 87848246 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.replacements 842088 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.947851 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 42623753 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 842600 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 50.585987 # Average number of references to valid blocks.
---
> system.cpu.tickCycles 227203186 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 88221850 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 843958 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.947848 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 42509637 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 844470 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 50.338836 # Average number of references to valid blocks.
527c527
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.947851 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.947848 # Average occupied blocks per requestor
531c531
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
533c533
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id
535,558c535,558
< system.cpu.dcache.tags.tag_accesses 176253823 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 176253823 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 23074723 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23074723 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 18285747 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 18285747 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 356646 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 356646 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 443503 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 443503 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 460198 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 460198 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 41360470 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 41360470 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 41717116 # number of overall hits
< system.cpu.dcache.overall_hits::total 41717116 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 491782 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 491782 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 547820 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 547820 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 169860 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 169860 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 22518 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 22518 # number of LoadLockedReq misses
---
> system.cpu.dcache.tags.tag_accesses 175807461 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 175807461 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 23001062 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23001062 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 18245677 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 18245677 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 356392 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 356392 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 443406 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 443406 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 460170 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 460170 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 41246739 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 41246739 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 41603131 # number of overall hits
> system.cpu.dcache.overall_hits::total 41603131 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 493519 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 493519 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 547788 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 547788 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 170140 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 170140 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 22585 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 22585 # number of LoadLockedReq misses
561,598c561,598
< system.cpu.dcache.demand_misses::cpu.data 1039602 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1039602 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1209462 # number of overall misses
< system.cpu.dcache.overall_misses::total 1209462 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 7264308005 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7264308005 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 23337097788 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 23337097788 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 285724000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 285724000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 30601405793 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 30601405793 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 30601405793 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 30601405793 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 23566505 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23566505 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 18833567 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 18833567 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 526506 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 526506 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466021 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 466021 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 460200 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 460200 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 42400072 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42400072 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 42926578 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 42926578 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020868 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.020868 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029087 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.029087 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322617 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.322617 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048320 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048320 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_misses::cpu.data 1041307 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1041307 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1211447 # number of overall misses
> system.cpu.dcache.overall_misses::total 1211447 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 7303521091 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7303521091 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 23397429282 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 23397429282 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 285183750 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 285183750 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 30700950373 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 30700950373 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 30700950373 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 30700950373 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 23494581 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23494581 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 18793465 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 18793465 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 526532 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 526532 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465991 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 465991 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 460172 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 460172 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 42288046 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42288046 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 42814578 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 42814578 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021006 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.021006 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029148 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.029148 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.323133 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.323133 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048467 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048467 # miss rate for LoadLockedReq accesses
601,617c601,617
< system.cpu.dcache.demand_miss_rate::cpu.data 0.024519 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.024519 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.028175 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.028175 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14771.398719 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14771.398719 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42599.937549 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 42599.937549 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12688.693490 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12688.693490 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 29435.693461 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 29435.693461 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 25301.667843 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 25301.667843 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 252 # number of cycles access was blocked
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.024624 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.024624 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.028295 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.028295 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14798.865071 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14798.865071 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42712.562674 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 42712.562674 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12627.130839 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12627.130839 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83500 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83500 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 29483.092280 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 29483.092280 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 25342.380123 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 25342.380123 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 238 # number of cycles access was blocked
619c619
< system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked
621c621
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.900000 # average number of cycles each access was blocked
625,644c625,644
< system.cpu.dcache.writebacks::writebacks 697883 # number of writebacks
< system.cpu.dcache.writebacks::total 697883 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74969 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 74969 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249041 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 249041 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14294 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 14294 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 324010 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 324010 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 324010 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 324010 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 416813 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 416813 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298779 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 298779 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121645 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 121645 # number of SoftPFReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8224 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 8224 # number of LoadLockedReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 699616 # number of writebacks
> system.cpu.dcache.writebacks::total 699616 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75147 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 75147 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249007 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 249007 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14321 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 14321 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 324154 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 324154 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 324154 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 324154 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 418372 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 418372 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298781 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 298781 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121907 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 121907 # number of SoftPFReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8264 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 8264 # number of LoadLockedReq MSHR misses
647,650c647,650
< system.cpu.dcache.demand_mshr_misses::cpu.data 715592 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 715592 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 837237 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 837237 # number of overall MSHR misses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 717153 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 717153 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 839060 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 839060 # number of overall MSHR misses
657,684c657,684
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5688327646 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5688327646 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12278776156 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 12278776156 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1560607790 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1560607790 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 106146500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 106146500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17967103802 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 17967103802 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19527711592 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 19527711592 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5837082750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5837082750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4510053000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4510053000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10347135750 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 10347135750 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017687 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017687 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015864 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015864 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231042 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231042 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017647 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017647 # mshr miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5719215890 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5719215890 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12311488911 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 12311488911 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1563028750 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1563028750 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 105928000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105928000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 164000 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18030704801 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 18030704801 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19593733551 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 19593733551 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5833996750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5833996750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4510200000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4510200000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10344196750 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 10344196750 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017807 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017807 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015898 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015898 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231528 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231528 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017734 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017734 # mshr miss rate for LoadLockedReq accesses
687,710c687,710
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016877 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.016877 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019504 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.019504 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13647.193456 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13647.193456 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41096.516676 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41096.516676 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12829.197994 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12829.197994 # average SoftPFReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12906.918774 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12906.918774 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81250 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81250 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25108.027762 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 25108.027762 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23323.994988 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 23323.994988 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187518.721087 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187518.721087 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163508.429105 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163508.429105 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176238.451909 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176238.451909 # average overall mshr uncacheable latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016959 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.016959 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019598 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.019598 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13670.168869 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13670.168869 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41205.728982 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41205.728982 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12821.484820 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12821.484820 # average SoftPFReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12818.005808 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12818.005808 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25142.061458 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 25142.061458 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23352.005281 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 23352.005281 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187419.582048 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187419.582048 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163513.758474 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163513.758474 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176188.393146 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176188.393146 # average overall mshr uncacheable latency
712,720c712,720
< system.cpu.icache.tags.replacements 2896868 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.399912 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 54702268 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 2897380 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 18.879908 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 15532248250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.399912 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.998828 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.998828 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 2897206 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.401811 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 54637656 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 2897718 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 18.855408 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 15497791250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.401811 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.998832 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.998832 # Average percentage of cache occupancy
722,724c722,724
< system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id
726,763c726,763
< system.cpu.icache.tags.tag_accesses 60497051 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 60497051 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 54702268 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 54702268 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 54702268 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 54702268 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 54702268 # number of overall hits
< system.cpu.icache.overall_hits::total 54702268 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 2897392 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 2897392 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 2897392 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 2897392 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 2897392 # number of overall misses
< system.cpu.icache.overall_misses::total 2897392 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 39291591662 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 39291591662 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 39291591662 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 39291591662 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 39291591662 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 39291591662 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 57599660 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 57599660 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 57599660 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 57599660 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 57599660 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 57599660 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050302 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.050302 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.050302 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.050302 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.050302 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.050302 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13561.020277 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13561.020277 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13561.020277 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13561.020277 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13561.020277 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13561.020277 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 60433115 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 60433115 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 54637656 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 54637656 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 54637656 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 54637656 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 54637656 # number of overall hits
> system.cpu.icache.overall_hits::total 54637656 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 2897730 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 2897730 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 2897730 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 2897730 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 2897730 # number of overall misses
> system.cpu.icache.overall_misses::total 2897730 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 39295051229 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 39295051229 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 39295051229 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 39295051229 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 39295051229 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 39295051229 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 57535386 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 57535386 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 57535386 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 57535386 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 57535386 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 57535386 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050364 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.050364 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.050364 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.050364 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.050364 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.050364 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13560.632367 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13560.632367 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13560.632367 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13560.632367 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13560.632367 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13560.632367 # average overall miss latency
772,777c772,777
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897392 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 2897392 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 2897392 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 2897392 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 2897392 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 2897392 # number of overall MSHR misses
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897730 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 2897730 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 2897730 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 2897730 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 2897730 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 2897730 # number of overall MSHR misses
782,787c782,787
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34935956838 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 34935956838 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34935956838 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 34935956838 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34935956838 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 34935956838 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34939012271 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 34939012271 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34939012271 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 34939012271 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34939012271 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 34939012271 # number of overall MSHR miss cycles
792,803c792,803
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050302 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050302 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050302 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.050302 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050302 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.050302 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12057.725305 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12057.725305 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12057.725305 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12057.725305 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12057.725305 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12057.725305 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050364 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050364 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050364 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.050364 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050364 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.050364 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12057.373279 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12057.373279 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12057.373279 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12057.373279 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12057.373279 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12057.373279 # average overall mshr miss latency
809,813c809,813
< system.cpu.l2cache.tags.replacements 96519 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65064.584640 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4043303 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 161770 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 24.994146 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 96812 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65065.452586 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4048611 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 162072 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 24.980324 # Average number of references to valid blocks.
815,821c815,821
< system.cpu.l2cache.tags.occ_blocks::writebacks 47432.807159 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 63.814603 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000383 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 12239.354143 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 5328.608352 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.723767 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000974 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 47495.130648 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 59.738238 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.009476 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 12201.333788 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 5309.240435 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.724718 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000912 # Average percentage of cache occupancy
823,828c823,828
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186758 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.081308 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.992807 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 39 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65212 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 39 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186178 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.081013 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.992820 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 46 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65214 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 46 # Occupied blocks per task id
830,865c830,865
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2301 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6950 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55839 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000595 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995056 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 36587667 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 36587667 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 70357 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4500 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 2874373 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 532417 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 3481647 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 697883 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 697883 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 51 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 51 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 165019 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 165019 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 70357 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 4500 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 2874373 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 697436 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 3646666 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 70357 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 4500 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 2874373 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 697436 # number of overall hits
< system.cpu.l2cache.overall_hits::total 3646666 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 117 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.inst 22990 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 14260 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 37368 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 2783 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 2783 # number of UpgradeReq misses
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2294 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6948 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55853 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000702 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995087 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 36624702 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 36624702 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 71053 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4456 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 2874723 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 534200 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 3484432 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 699616 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 699616 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 54 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 54 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 164782 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 164782 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 71053 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 4456 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 2874723 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 698982 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 3649214 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 71053 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 4456 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 2874723 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 698982 # number of overall hits
> system.cpu.l2cache.overall_hits::total 3649214 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 118 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.inst 22979 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 14338 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 37437 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 2773 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 2773 # number of UpgradeReq misses
868,909c868,909
< system.cpu.l2cache.ReadExReq_misses::cpu.data 130931 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 130931 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 117 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.inst 22990 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 145191 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 168299 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 117 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.inst 22990 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 145191 # number of overall misses
< system.cpu.l2cache.overall_misses::total 168299 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 10468750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 82500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1843397750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1191861290 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 3045810290 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1125464 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 1125464 # number of UpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10149479687 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 10149479687 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 10468750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 82500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1843397750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 11341340977 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 13195289977 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 10468750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 82500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1843397750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 11341340977 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 13195289977 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 70474 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4501 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 2897363 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 546677 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 3519015 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 697883 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 697883 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2834 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2834 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 131177 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 131177 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 118 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 22979 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 145515 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 168614 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 118 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 22979 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 145515 # number of overall misses
> system.cpu.l2cache.overall_misses::total 168614 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 10044750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 179750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1842559750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1204180000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 3056964250 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1091465 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 1091465 # number of UpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10184869681 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 10184869681 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 10044750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 179750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1842559750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11389049681 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 13241833931 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 10044750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 179750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1842559750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11389049681 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 13241833931 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 71171 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4458 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 2897702 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 548538 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 3521869 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 699616 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 699616 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2827 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2827 # number of UpgradeReq accesses(hits+misses)
912,930c912,930
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 295950 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 295950 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 70474 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 4501 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 2897363 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 842627 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 3814965 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 70474 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 4501 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 2897363 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 842627 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 3814965 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001660 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000222 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.007935 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026085 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.010619 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.982004 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.982004 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 295959 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 295959 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 71171 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 4458 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 2897702 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 844497 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 3817828 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 71171 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 4458 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 2897702 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 844497 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 3817828 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001658 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000449 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.007930 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026139 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.010630 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.980898 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.980898 # miss rate for UpgradeReq accesses
933,965c933,965
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.442409 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.442409 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001660 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000222 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007935 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.172308 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.044115 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001660 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000222 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007935 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.172308 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.044115 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89476.495726 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82500 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80182.590257 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83580.735624 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 81508.517716 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 404.406755 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 404.406755 # average UpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80250 # average SCUpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77517.774148 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77517.774148 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89476.495726 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80182.590257 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78113.250663 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 78403.852530 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89476.495726 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80182.590257 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78113.250663 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 78403.852530 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.443227 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.443227 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001658 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000449 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007930 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.172310 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.044165 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001658 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000449 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007930 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.172310 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.044165 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85125 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89875 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80184.505418 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83985.214116 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 81656.229132 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 393.604400 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 393.604400 # average UpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 81000 # average SCUpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 81000 # average SCUpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77642.190940 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77642.190940 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85125 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89875 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80184.505418 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78267.186757 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 78533.419117 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85125 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89875 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80184.505418 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78267.186757 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 78533.419117 # average overall miss latency
974,991c974,991
< system.cpu.l2cache.writebacks::writebacks 88028 # number of writebacks
< system.cpu.l2cache.writebacks::total 88028 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 21 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 146 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 21 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 146 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 21 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 146 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 167 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 117 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 22969 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14114 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 37201 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2783 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 2783 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.writebacks::writebacks 88394 # number of writebacks
> system.cpu.l2cache.writebacks::total 88394 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 20 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 140 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 160 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 20 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 140 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 160 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 20 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 140 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 160 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 118 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 22959 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14198 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 37277 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2773 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 2773 # number of UpgradeReq MSHR misses
994,1005c994,1005
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130931 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 130931 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 117 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 22969 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 145045 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 168132 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 117 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 22969 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 145045 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 168132 # number of overall MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131177 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 131177 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 118 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 22959 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 145375 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 168454 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 118 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 22959 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 145375 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 168454 # number of overall MSHR misses
1014,1034c1014,1034
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 9004250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 70000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1554748750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1005120210 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2568943210 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 49466283 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 49466283 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 136000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 136000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8511009313 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8511009313 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 9004250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 70000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1554748750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9516129523 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 11079952523 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 9004250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 70000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1554748750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9516129523 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 11079952523 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 8565250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 154250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1554112000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1016371500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2579203000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 49277273 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 49277273 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 137000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 137000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8543347819 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8543347819 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8565250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 154250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1554112000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9559719319 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 11122550819 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8565250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 154250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1554112000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9559719319 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 11122550819 # number of overall MSHR miss cycles
1036,1039c1036,1039
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5400789000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5592518750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151344500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151344500 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5397684500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5589414250 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151492500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151492500 # number of WriteReq MSHR uncacheable cycles
1041,1049c1041,1049
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9552133500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9743863250 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001660 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000222 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025818 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010571 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982004 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982004 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9549177000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9740906750 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001658 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000449 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007923 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025883 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010584 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.980898 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.980898 # mshr miss rate for UpgradeReq accesses
1052,1084c1052,1084
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442409 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442409 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001660 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000222 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.044072 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001660 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000222 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.044072 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76959.401709 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67689.004746 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71214.411931 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69055.756834 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17774.445922 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17774.445922 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68000 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68000 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65003.775370 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65003.775370 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76959.401709 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67689.004746 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65608.118329 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65900.319529 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76959.401709 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67689.004746 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65608.118329 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65900.319529 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443227 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443227 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001658 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000449 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007923 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172144 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.044123 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001658 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000449 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007923 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172144 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.044123 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72586.864407 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 77125 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67690.753082 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71585.540217 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69190.197709 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17770.383339 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17770.383339 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68500 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65128.397654 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65128.397654 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72586.864407 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 77125 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67690.753082 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65759.032289 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66027.228911 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72586.864407 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 77125 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67690.753082 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65759.032289 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66027.228911 # average overall mshr miss latency
1086,1089c1086,1089
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173502.602159 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163047.193878 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150503.734184 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150503.734184 # average WriteReq mshr uncacheable latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173402.868800 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162956.683673 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150509.099808 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150509.099808 # average WriteReq mshr uncacheable latency
1091,1092c1091,1092
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162697.509836 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157456.219802 # average overall mshr uncacheable latency
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162647.153004 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157408.444161 # average overall mshr uncacheable latency
1094,1095c1094,1095
< system.cpu.toL2Bus.trans_dist::ReadReq 3577827 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 3577732 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 3581126 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 3581032 # Transaction distribution
1098,1100c1098,1100
< system.cpu.toL2Bus.trans_dist::Writeback 697883 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2834 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 699616 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36257 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2827 # Transaction distribution
1102,1118c1102,1118
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2836 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 295950 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 295950 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5801098 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506371 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15072 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159127 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 8481668 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185634176 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98784669 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18004 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 281896 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 284718745 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 60910 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 4638337 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1.029260 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.168533 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2829 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 295959 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 295959 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5801775 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2511831 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15055 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 160898 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 8489559 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185655872 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99015325 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17832 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 284684 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 284973713 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 61355 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 4643370 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1.029465 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.169105 # Request fanout histogram
1121,1122c1121,1122
< system.cpu.toL2Bus.snoop_fanout::1 4502621 97.07% 97.07% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 135716 2.93% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 4506555 97.05% 97.05% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 136815 2.95% 100.00% # Request fanout histogram
1126,1127c1126,1127
< system.cpu.toL2Bus.snoop_fanout::total 4638337 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 3012597000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 4643370 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 3016847250 # Layer occupancy (ticks)
1129c1129
< system.cpu.toL2Bus.snoopLayer0.occupancy 210000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 211500 # Layer occupancy (ticks)
1131c1131
< system.cpu.toL2Bus.respLayer0.occupancy 4356351412 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 4356806979 # Layer occupancy (ticks)
1133c1133
< system.cpu.toL2Bus.respLayer1.occupancy 1341303908 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1344182949 # Layer occupancy (ticks)
1135c1135
< system.cpu.toL2Bus.respLayer2.occupancy 10571000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 10597250 # Layer occupancy (ticks)
1137c1137
< system.cpu.toL2Bus.respLayer3.occupancy 88656750 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 89732000 # Layer occupancy (ticks)
1234c1234
< system.iobus.reqLayer27.occupancy 198957934 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 198883474 # Layer occupancy (ticks)
1240c1240
< system.iobus.respLayer3.occupancy 36810010 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 36810507 # Layer occupancy (ticks)
1243c1243
< system.iocache.tags.tagsinuse 1.031201 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.031423 # Cycle average of tags in use
1247,1250c1247,1250
< system.iocache.tags.warmup_cycle 270527174000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 1.031201 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.064450 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.064450 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 270485733000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 1.031423 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.064464 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.064464 # Average percentage of cache occupancy
1264,1271c1264,1271
< system.iocache.ReadReq_miss_latency::realview.ide 29240377 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 29240377 # number of ReadReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6662157547 # number of WriteInvalidateReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::total 6662157547 # number of WriteInvalidateReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 29240377 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 29240377 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 29240377 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 29240377 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 29239875 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 29239875 # number of ReadReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6650280092 # number of WriteInvalidateReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::total 6650280092 # number of WriteInvalidateReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 29239875 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 29239875 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 29239875 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 29239875 # number of overall miss cycles
1288,1296c1288,1296
< system.iocache.ReadReq_avg_miss_latency::realview.ide 124958.876068 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 124958.876068 # average ReadReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183915.568325 # average WriteInvalidateReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::total 183915.568325 # average WriteInvalidateReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 124958.876068 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 124958.876068 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 124958.876068 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 124958.876068 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 23447 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 124956.730769 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 124956.730769 # average ReadReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183587.679218 # average WriteInvalidateReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::total 183587.679218 # average WriteInvalidateReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 124956.730769 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 124956.730769 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 124956.730769 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 124956.730769 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 22674 # number of cycles access was blocked
1298c1298
< system.iocache.blocked::no_mshrs 3545 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3485 # number of cycles access was blocked
1300c1300
< system.iocache.avg_blocked_cycles::no_mshrs 6.614104 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 6.506169 # average number of cycles each access was blocked
1314,1321c1314,1321
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 16932377 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 16932377 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4778489567 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4778489567 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 16932377 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 16932377 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 16932377 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 16932377 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 16928877 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 16928877 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4766620104 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4766620104 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 16928877 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 16928877 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 16928877 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 16928877 # number of overall MSHR miss cycles
1330,1337c1330,1337
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72360.585470 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 72360.585470 # average ReadReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131915.016757 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131915.016757 # average WriteInvalidateReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 72360.585470 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 72360.585470 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 72360.585470 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 72360.585470 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72345.628205 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 72345.628205 # average ReadReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131587.348277 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131587.348277 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 72345.628205 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 72345.628205 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 72345.628205 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 72345.628205 # average overall mshr miss latency
1339,1340c1339,1340
< system.membus.trans_dist::ReadReq 71735 # Transaction distribution
< system.membus.trans_dist::ReadResp 71735 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 71811 # Transaction distribution
> system.membus.trans_dist::ReadResp 71811 # Transaction distribution
1343c1343
< system.membus.trans_dist::Writeback 124218 # Transaction distribution
---
> system.membus.trans_dist::Writeback 124584 # Transaction distribution
1346c1346
< system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 4592 # Transaction distribution
1348,1350c1348,1350
< system.membus.trans_dist::UpgradeResp 4598 # Transaction distribution
< system.membus.trans_dist::ReadExReq 129118 # Transaction distribution
< system.membus.trans_dist::ReadExResp 129118 # Transaction distribution
---
> system.membus.trans_dist::UpgradeResp 4594 # Transaction distribution
> system.membus.trans_dist::ReadExReq 129358 # Transaction distribution
> system.membus.trans_dist::ReadExResp 129358 # Transaction distribution
1354,1355c1354,1355
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445781 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553341 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446770 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554330 # Packet count per connected master and slave (bytes)
1358c1358
< system.membus.pkt_count::total 662228 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 663217 # Packet count per connected master and slave (bytes)
1362,1363c1362,1363
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16482336 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16646045 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16525920 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16689629 # Cumulative packet size per connected master and slave (bytes)
1366,1368c1366,1368
< system.membus.pkt_size::total 21281501 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 506 # Total snoops (count)
< system.membus.snoop_fanout::samples 393527 # Request fanout histogram
---
> system.membus.pkt_size::total 21325085 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 507 # Total snoops (count)
> system.membus.snoop_fanout::samples 394211 # Request fanout histogram
1373c1373
< system.membus.snoop_fanout::1 393527 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 394211 100.00% 100.00% # Request fanout histogram
1378,1379c1378,1379
< system.membus.snoop_fanout::total 393527 # Request fanout histogram
< system.membus.reqLayer0.occupancy 90546500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 394211 # Request fanout histogram
> system.membus.reqLayer0.occupancy 87591000 # Layer occupancy (ticks)
1383c1383
< system.membus.reqLayer2.occupancy 1706500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 1723500 # Layer occupancy (ticks)
1385c1385
< system.membus.reqLayer5.occupancy 1023221651 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 1025789403 # Layer occupancy (ticks)
1387c1387
< system.membus.respLayer2.occupancy 996325444 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 997949408 # Layer occupancy (ticks)
1389c1389
< system.membus.respLayer3.occupancy 37473990 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 37471493 # Layer occupancy (ticks)