3,5c3,5
< sim_seconds 2.852832 # Number of seconds simulated
< sim_ticks 2852831758500 # Number of ticks simulated
< final_tick 2852831758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.852840 # Number of seconds simulated
> sim_ticks 2852839554500 # Number of ticks simulated
> final_tick 2852839554500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 111123 # Simulator instruction rate (inst/s)
< host_op_rate 134357 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2834419538 # Simulator tick rate (ticks/s)
< host_mem_usage 554504 # Number of bytes of host memory used
< host_seconds 1006.50 # Real time elapsed on the host
< sim_insts 111845135 # Number of instructions simulated
< sim_ops 135229426 # Number of ops (including micro ops) simulated
---
> host_inst_rate 169032 # Simulator instruction rate (inst/s)
> host_op_rate 204382 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 4294589830 # Simulator tick rate (ticks/s)
> host_mem_usage 620820 # Number of bytes of host memory used
> host_seconds 664.29 # Real time elapsed on the host
> sim_insts 112285680 # Number of instructions simulated
> sim_ops 135768245 # Number of ops (including micro ops) simulated
16,19c16,19
< system.physmem.bytes_read::cpu.dtb.walker 7744 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 1669888 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9170532 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.dtb.walker 7680 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 1672128 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9190636 # Number of bytes read from this memory
21,24c21,24
< system.physmem.bytes_read::total 10849188 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1669888 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1669888 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7971008 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 10871532 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1672128 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1672128 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7983360 # Number of bytes written to this memory
26,30c26,30
< system.physmem.bytes_written::total 7988532 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.dtb.walker 121 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 26092 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 143809 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::total 8000884 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.dtb.walker 120 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 26127 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 144125 # Number of read requests responded to by this memory
32,33c32,33
< system.physmem.num_reads::total 170038 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 124547 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 170389 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 124740 # Number of write requests responded to by this memory
35,39c35,39
< system.physmem.num_writes::total 128928 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.dtb.walker 2714 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 585344 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3214537 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 129121 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 2692 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 586128 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3221575 # Total read bandwidth from this memory (bytes/s)
41,44c41,44
< system.physmem.bw_read::total 3802954 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 585344 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 585344 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2794069 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 3810776 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 586128 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 586128 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2798391 # Write bandwidth from this memory (bytes/s)
46,51c46,51
< system.physmem.bw_write::total 2800211 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2794069 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 2714 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 585344 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 3220679 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 2804533 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2798391 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 2692 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 586128 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 3227717 # Total bandwidth to/from this memory (bytes/s)
53,97c53,97
< system.physmem.bw_total::total 6603165 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 170038 # Number of read requests accepted
< system.physmem.writeReqs 165152 # Number of write requests accepted
< system.physmem.readBursts 170038 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 165152 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 10876672 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 5760 # Total number of bytes read from write queue
< system.physmem.bytesWritten 9051328 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 10849188 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 10306868 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 90 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 23701 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 4591 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 10711 # Per bank write bursts
< system.physmem.perBankRdBursts::1 10418 # Per bank write bursts
< system.physmem.perBankRdBursts::2 10743 # Per bank write bursts
< system.physmem.perBankRdBursts::3 10617 # Per bank write bursts
< system.physmem.perBankRdBursts::4 13557 # Per bank write bursts
< system.physmem.perBankRdBursts::5 10851 # Per bank write bursts
< system.physmem.perBankRdBursts::6 10986 # Per bank write bursts
< system.physmem.perBankRdBursts::7 10951 # Per bank write bursts
< system.physmem.perBankRdBursts::8 10335 # Per bank write bursts
< system.physmem.perBankRdBursts::9 10516 # Per bank write bursts
< system.physmem.perBankRdBursts::10 10068 # Per bank write bursts
< system.physmem.perBankRdBursts::11 9192 # Per bank write bursts
< system.physmem.perBankRdBursts::12 10325 # Per bank write bursts
< system.physmem.perBankRdBursts::13 10893 # Per bank write bursts
< system.physmem.perBankRdBursts::14 9864 # Per bank write bursts
< system.physmem.perBankRdBursts::15 9921 # Per bank write bursts
< system.physmem.perBankWrBursts::0 8907 # Per bank write bursts
< system.physmem.perBankWrBursts::1 8809 # Per bank write bursts
< system.physmem.perBankWrBursts::2 9307 # Per bank write bursts
< system.physmem.perBankWrBursts::3 9147 # Per bank write bursts
< system.physmem.perBankWrBursts::4 8787 # Per bank write bursts
< system.physmem.perBankWrBursts::5 9076 # Per bank write bursts
< system.physmem.perBankWrBursts::6 9209 # Per bank write bursts
< system.physmem.perBankWrBursts::7 9123 # Per bank write bursts
< system.physmem.perBankWrBursts::8 9054 # Per bank write bursts
< system.physmem.perBankWrBursts::9 9064 # Per bank write bursts
< system.physmem.perBankWrBursts::10 8553 # Per bank write bursts
< system.physmem.perBankWrBursts::11 8266 # Per bank write bursts
< system.physmem.perBankWrBursts::12 8846 # Per bank write bursts
< system.physmem.perBankWrBursts::13 9045 # Per bank write bursts
< system.physmem.perBankWrBursts::14 8063 # Per bank write bursts
< system.physmem.perBankWrBursts::15 8171 # Per bank write bursts
---
> system.physmem.bw_total::total 6615309 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 170389 # Number of read requests accepted
> system.physmem.writeReqs 165345 # Number of write requests accepted
> system.physmem.readBursts 170389 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 165345 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 10897024 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 7872 # Total number of bytes read from write queue
> system.physmem.bytesWritten 9054784 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 10871532 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 10319220 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 123 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 23835 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 4587 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 10917 # Per bank write bursts
> system.physmem.perBankRdBursts::1 10861 # Per bank write bursts
> system.physmem.perBankRdBursts::2 10721 # Per bank write bursts
> system.physmem.perBankRdBursts::3 10725 # Per bank write bursts
> system.physmem.perBankRdBursts::4 13339 # Per bank write bursts
> system.physmem.perBankRdBursts::5 10813 # Per bank write bursts
> system.physmem.perBankRdBursts::6 11142 # Per bank write bursts
> system.physmem.perBankRdBursts::7 10985 # Per bank write bursts
> system.physmem.perBankRdBursts::8 10153 # Per bank write bursts
> system.physmem.perBankRdBursts::9 10280 # Per bank write bursts
> system.physmem.perBankRdBursts::10 10274 # Per bank write bursts
> system.physmem.perBankRdBursts::11 9203 # Per bank write bursts
> system.physmem.perBankRdBursts::12 10314 # Per bank write bursts
> system.physmem.perBankRdBursts::13 10760 # Per bank write bursts
> system.physmem.perBankRdBursts::14 10035 # Per bank write bursts
> system.physmem.perBankRdBursts::15 9744 # Per bank write bursts
> system.physmem.perBankWrBursts::0 9017 # Per bank write bursts
> system.physmem.perBankWrBursts::1 9225 # Per bank write bursts
> system.physmem.perBankWrBursts::2 9344 # Per bank write bursts
> system.physmem.perBankWrBursts::3 9210 # Per bank write bursts
> system.physmem.perBankWrBursts::4 8591 # Per bank write bursts
> system.physmem.perBankWrBursts::5 8923 # Per bank write bursts
> system.physmem.perBankWrBursts::6 9235 # Per bank write bursts
> system.physmem.perBankWrBursts::7 9154 # Per bank write bursts
> system.physmem.perBankWrBursts::8 8919 # Per bank write bursts
> system.physmem.perBankWrBursts::9 8830 # Per bank write bursts
> system.physmem.perBankWrBursts::10 8770 # Per bank write bursts
> system.physmem.perBankWrBursts::11 8263 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8824 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8884 # Per bank write bursts
> system.physmem.perBankWrBursts::14 8238 # Per bank write bursts
> system.physmem.perBankWrBursts::15 8054 # Per bank write bursts
99,100c99,100
< system.physmem.numWrRetry 51 # Number of times write queue was full causing retry
< system.physmem.totGap 2852831352500 # Total gap between requests
---
> system.physmem.numWrRetry 37 # Number of times write queue was full causing retry
> system.physmem.totGap 2852839149500 # Total gap between requests
103c103
< system.physmem.readPktSize::2 541 # Read request sizes (log2)
---
> system.physmem.readPktSize::2 543 # Read request sizes (log2)
107c107
< system.physmem.readPktSize::6 169483 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 169832 # Read request sizes (log2)
114,116c114,116
< system.physmem.writePktSize::6 160771 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 163196 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 6460 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 160964 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 163637 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 6336 # What read queue length does an incoming req see
118c118
< system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see
162,228c162,228
< system.physmem.wrQLenPdf::15 1486 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 1656 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5410 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5965 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6177 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5982 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6172 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 6639 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 7573 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 6474 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 6716 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8051 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 6751 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6513 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 8515 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 7300 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6993 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6732 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 1421 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 1060 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 1325 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 2414 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 2262 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 1874 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 1812 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 2371 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 1817 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 1970 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 1688 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 1902 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 1644 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 1359 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 1311 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 1040 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 618 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 389 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 373 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 299 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 175 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 113 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 153 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 139 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 140 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 107 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 88 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 113 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 62 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 157 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 61712 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 322.918330 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 189.336942 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 338.461853 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 22238 36.04% 36.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14509 23.51% 59.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6552 10.62% 70.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3615 5.86% 76.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2651 4.30% 80.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1538 2.49% 82.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1136 1.84% 84.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1152 1.87% 86.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8321 13.48% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 61712 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5883 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 28.886962 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 584.019916 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 5882 99.98% 99.98% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 1489 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 1693 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5447 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5908 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6153 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6085 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6368 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6736 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 7709 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 6427 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 6419 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 8137 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 6722 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6648 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 8422 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 7164 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6970 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6919 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 1319 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 1058 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 1390 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 2313 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 2314 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 1761 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 1866 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 2309 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 1753 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 1926 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 1707 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 1951 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 1587 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 1269 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 1250 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 1117 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 648 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 488 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 362 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 274 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 289 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 203 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 130 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 164 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 134 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 153 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 93 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 89 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 81 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 43 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 61975 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 321.932134 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 188.780856 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 337.844354 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 22404 36.15% 36.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 14558 23.49% 59.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6628 10.69% 70.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3590 5.79% 76.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2633 4.25% 80.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1568 2.53% 82.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1136 1.83% 84.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1187 1.92% 86.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8271 13.35% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 61975 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5903 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 28.841945 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 583.033382 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 5902 99.98% 99.98% # Reads before turning the bus around for writes
230,269c230,270
< system.physmem.rdPerTurnAround::total 5883 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5883 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 24.039946 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.374321 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 43.145306 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-31 5549 94.32% 94.32% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-47 83 1.41% 95.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-63 21 0.36% 96.09% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-79 19 0.32% 96.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-95 30 0.51% 96.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-111 24 0.41% 97.33% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-127 22 0.37% 97.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-143 15 0.25% 97.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-159 11 0.19% 98.15% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-175 3 0.05% 98.20% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-191 21 0.36% 98.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-207 13 0.22% 98.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::208-223 9 0.15% 98.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-239 6 0.10% 99.03% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::240-255 2 0.03% 99.07% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::256-271 2 0.03% 99.10% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::272-287 4 0.07% 99.17% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::288-303 7 0.12% 99.29% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::304-319 3 0.05% 99.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::320-335 2 0.03% 99.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::336-351 6 0.10% 99.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::352-367 9 0.15% 99.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::368-383 2 0.03% 99.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::400-415 3 0.05% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::464-479 2 0.03% 99.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::496-511 2 0.03% 99.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::512-527 1 0.02% 99.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::528-543 5 0.08% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::544-559 2 0.03% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::560-575 5 0.08% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5883 # Writes before turning the bus around for reads
< system.physmem.totQLat 1723441444 # Total ticks spent queuing
< system.physmem.totMemAccLat 4909966444 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 849740000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 10140.99 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 5903 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5903 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 23.967644 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.368451 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 42.492651 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-31 5572 94.39% 94.39% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-47 86 1.46% 95.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-63 22 0.37% 96.22% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-79 13 0.22% 96.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-95 26 0.44% 96.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-111 23 0.39% 97.27% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-127 23 0.39% 97.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-143 20 0.34% 98.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-159 7 0.12% 98.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-175 2 0.03% 98.15% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-191 23 0.39% 98.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-207 13 0.22% 98.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-223 11 0.19% 98.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-239 2 0.03% 98.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::240-255 2 0.03% 99.02% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-271 3 0.05% 99.07% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::272-287 2 0.03% 99.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::288-303 6 0.10% 99.20% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::304-319 7 0.12% 99.32% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::320-335 5 0.08% 99.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::336-351 2 0.03% 99.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::352-367 15 0.25% 99.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::384-399 4 0.07% 99.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::416-431 1 0.02% 99.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::480-495 3 0.05% 99.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::496-511 2 0.03% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::512-527 1 0.02% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::528-543 2 0.03% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::544-559 2 0.03% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::560-575 2 0.03% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::720-735 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5903 # Writes before turning the bus around for reads
> system.physmem.totQLat 1723482630 # Total ticks spent queuing
> system.physmem.totMemAccLat 4915970130 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 851330000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 10122.29 # Average queueing delay per DRAM burst
271,272c272,273
< system.physmem.avgMemAccLat 28890.99 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28872.29 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 3.82 # Average DRAM read bandwidth in MiByte/s
274,275c275,276
< system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 3.62 # Average system write bandwidth in MiByte/s
281,298c282,299
< system.physmem.avgWrQLen 27.38 # Average write queue length when enqueuing
< system.physmem.readRowHits 140236 # Number of row buffer hits during reads
< system.physmem.writeRowHits 109426 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 82.52 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 77.36 # Row buffer hit rate for writes
< system.physmem.avgGap 8511087.30 # Average gap between requests
< system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 243129600 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 132660000 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 692905200 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 468925200 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 186332824080 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 83554754445 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1638403001250 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1909828199775 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.450935 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 2725489926444 # Time in different power states
< system.physmem_0.memoryStateTime::REF 95262180000 # Time in different power states
---
> system.physmem.avgWrQLen 25.62 # Average write queue length when enqueuing
> system.physmem.readRowHits 140451 # Number of row buffer hits during reads
> system.physmem.writeRowHits 109320 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 82.49 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 77.25 # Row buffer hit rate for writes
> system.physmem.avgGap 8497319.75 # Average gap between requests
> system.physmem.pageHitRate 80.11 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 245019600 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 133691250 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 698123400 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 471089520 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 186333332640 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 83679210810 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1638298500750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1909858967970 # Total energy per rank (pJ)
> system.physmem_0.averagePower 669.459893 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 2725317218918 # Time in different power states
> system.physmem_0.memoryStateTime::REF 95262440000 # Time in different power states
300c301
< system.physmem_0.memoryStateTime::ACT 32075649806 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 32255883582 # Time in different power states
302,312c303,313
< system.physmem_1.actEnergy 223413120 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 121902000 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 632681400 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 447521760 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 186332824080 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 82328316795 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1639478823750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1909565482905 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.358845 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 2727297379194 # Time in different power states
< system.physmem_1.memoryStateTime::REF 95262180000 # Time in different power states
---
> system.physmem_1.actEnergy 223511400 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 121955625 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 629943600 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 445707360 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 186333332640 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 82264054140 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1639539866250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1909558371015 # Total energy per rank (pJ)
> system.physmem_1.averagePower 669.354525 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2727396126418 # Time in different power states
> system.physmem_1.memoryStateTime::REF 95262440000 # Time in different power states
314c315
< system.physmem_1.memoryStateTime::ACT 30272102306 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 30180892082 # Time in different power states
334,338c335,339
< system.cpu.branchPred.lookups 31016169 # Number of BP lookups
< system.cpu.branchPred.condPredicted 16821620 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 2509164 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 18454178 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 13299317 # Number of BTB hits
---
> system.cpu.branchPred.lookups 31043514 # Number of BP lookups
> system.cpu.branchPred.condPredicted 16869099 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 2536489 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 18574786 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 13386311 # Number of BTB hits
340,342c341,343
< system.cpu.branchPred.BTBHitPct 72.066699 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 7885459 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 1501288 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 72.067108 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 7804422 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 1529182 # Number of incorrect RAS predictions.
373,385c374,386
< system.cpu.dtb.walker.walks 66365 # Table walker walks requested
< system.cpu.dtb.walker.walksShort 66365 # Table walker walks initiated with short descriptors
< system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43579 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22786 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walkWaitTime::samples 66365 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0 66365 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::total 66365 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 7796 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 11013.949461 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 8730.002722 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 7624.437396 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-16383 6093 78.16% 78.16% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::16384-32767 1696 21.75% 99.91% # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.walks 65823 # Table walker walks requested
> system.cpu.dtb.walker.walksShort 65823 # Table walker walks initiated with short descriptors
> system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43117 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22706 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walkWaitTime::samples 65823 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0 65823 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::total 65823 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 7829 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 10980.553072 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 8717.816397 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 7451.711579 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-16383 6121 78.18% 78.18% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::16384-32767 1701 21.73% 99.91% # Table walker service (enqueue to completion) latency
387c388,389
< system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.97% # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.97% # Table walker service (enqueue to completion) latency
389,390c391,392
< system.cpu.dtb.walker.walkCompletionTime::229376-245759 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::total 7796 # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::total 7829 # Table walker service (enqueue to completion) latency
394,397c396,399
< system.cpu.dtb.walker.walkPageSizes::4K 6406 82.17% 82.17% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::1M 1390 17.83% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 7796 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66365 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkPageSizes::4K 6444 82.31% 82.31% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::1M 1385 17.69% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 7829 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 65823 # Table walker requests started/completed, data/inst
399,400c401,402
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66365 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7796 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 65823 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7829 # Table walker requests started/completed, data/inst
402,403c404,405
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7796 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 74161 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7829 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 73652 # Table walker requests started/completed, data/inst
406,409c408,411
< system.cpu.dtb.read_hits 24709745 # DTB read hits
< system.cpu.dtb.read_misses 59626 # DTB read misses
< system.cpu.dtb.write_hits 19412201 # DTB write hits
< system.cpu.dtb.write_misses 6739 # DTB write misses
---
> system.cpu.dtb.read_hits 24809902 # DTB read hits
> system.cpu.dtb.read_misses 58990 # DTB read misses
> system.cpu.dtb.write_hits 19469042 # DTB write hits
> system.cpu.dtb.write_misses 6833 # DTB write misses
414,416c416,418
< system.cpu.dtb.flush_entries 4351 # Number of entries that have been flushed from TLB
< system.cpu.dtb.align_faults 1292 # Number of TLB faults due to alignment restrictions
< system.cpu.dtb.prefetch_faults 1782 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB
> system.cpu.dtb.align_faults 1238 # Number of TLB faults due to alignment restrictions
> system.cpu.dtb.prefetch_faults 1767 # Number of TLB faults due to prefetch
418,420c420,422
< system.cpu.dtb.perms_faults 733 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 24769371 # DTB read accesses
< system.cpu.dtb.write_accesses 19418940 # DTB write accesses
---
> system.cpu.dtb.perms_faults 748 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 24868892 # DTB read accesses
> system.cpu.dtb.write_accesses 19475875 # DTB write accesses
422,424c424,426
< system.cpu.dtb.hits 44121946 # DTB hits
< system.cpu.dtb.misses 66365 # DTB misses
< system.cpu.dtb.accesses 44188311 # DTB accesses
---
> system.cpu.dtb.hits 44278944 # DTB hits
> system.cpu.dtb.misses 65823 # DTB misses
> system.cpu.dtb.accesses 44344767 # DTB accesses
454,467c456,469
< system.cpu.itb.walker.walks 5448 # Table walker walks requested
< system.cpu.itb.walker.walksShort 5448 # Table walker walks initiated with short descriptors
< system.cpu.itb.walker.walksShortTerminationLevel::Level1 319 # Level at which table walker walks with short descriptors terminate
< system.cpu.itb.walker.walksShortTerminationLevel::Level2 5129 # Level at which table walker walks with short descriptors terminate
< system.cpu.itb.walker.walkWaitTime::samples 5448 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::0 5448 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::total 5448 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkCompletionTime::samples 3189 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::mean 11214.016933 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 8947.518192 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 7056.251032 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::0-8191 1295 40.61% 40.61% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::8192-16383 1177 36.91% 77.52% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::16384-24575 716 22.45% 99.97% # Table walker service (enqueue to completion) latency
---
> system.cpu.itb.walker.walks 5435 # Table walker walks requested
> system.cpu.itb.walker.walksShort 5435 # Table walker walks initiated with short descriptors
> system.cpu.itb.walker.walksShortTerminationLevel::Level1 321 # Level at which table walker walks with short descriptors terminate
> system.cpu.itb.walker.walksShortTerminationLevel::Level2 5114 # Level at which table walker walks with short descriptors terminate
> system.cpu.itb.walker.walkWaitTime::samples 5435 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::0 5435 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::total 5435 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkCompletionTime::samples 3183 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::mean 11172.007540 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 8898.591631 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 7073.724538 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::0-8191 1308 41.09% 41.09% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::8192-16383 1159 36.41% 77.51% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::16384-24575 715 22.46% 99.97% # Table walker service (enqueue to completion) latency
469c471
< system.cpu.itb.walker.walkCompletionTime::total 3189 # Table walker service (enqueue to completion) latency
---
> system.cpu.itb.walker.walkCompletionTime::total 3183 # Table walker service (enqueue to completion) latency
473,475c475,477
< system.cpu.itb.walker.walkPageSizes::4K 2879 90.28% 90.28% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::1M 310 9.72% 100.00% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::total 3189 # Table walker page sizes translated
---
> system.cpu.itb.walker.walkPageSizes::4K 2873 90.26% 90.26% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::1M 310 9.74% 100.00% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::total 3183 # Table walker page sizes translated
477,478c479,480
< system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5448 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Requested::total 5448 # Table walker requests started/completed, data/inst
---
> system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5435 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Requested::total 5435 # Table walker requests started/completed, data/inst
480,484c482,486
< system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3189 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Completed::total 3189 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin::total 8637 # Table walker requests started/completed, data/inst
< system.cpu.itb.inst_hits 57588649 # ITB inst hits
< system.cpu.itb.inst_misses 5448 # ITB inst misses
---
> system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3183 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Completed::total 3183 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin::total 8618 # Table walker requests started/completed, data/inst
> system.cpu.itb.inst_hits 57700454 # ITB inst hits
> system.cpu.itb.inst_misses 5435 # ITB inst misses
493c495
< system.cpu.itb.flush_entries 2978 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_entries 2972 # Number of entries that have been flushed from TLB
497c499
< system.cpu.itb.perms_faults 8467 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 8445 # Number of TLB faults due to permissions restrictions
500,504c502,506
< system.cpu.itb.inst_accesses 57594097 # ITB inst accesses
< system.cpu.itb.hits 57588649 # DTB hits
< system.cpu.itb.misses 5448 # DTB misses
< system.cpu.itb.accesses 57594097 # DTB accesses
< system.cpu.numCycles 315565701 # number of cpu cycles simulated
---
> system.cpu.itb.inst_accesses 57705889 # ITB inst accesses
> system.cpu.itb.hits 57700454 # DTB hits
> system.cpu.itb.misses 5435 # DTB misses
> system.cpu.itb.accesses 57705889 # DTB accesses
> system.cpu.numCycles 315730000 # number of cpu cycles simulated
507,509c509,511
< system.cpu.committedInsts 111845135 # Number of instructions committed
< system.cpu.committedOps 135229426 # Number of ops (including micro ops) committed
< system.cpu.discardedOps 7692999 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.committedInsts 112285680 # Number of instructions committed
> system.cpu.committedOps 135768245 # Number of ops (including micro ops) committed
> system.cpu.discardedOps 7761547 # Number of ops (including micro ops) which were discarded before commit
511,513c513,515
< system.cpu.quiesceCycles 5390158471 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.cpi 2.821452 # CPI: cycles per instruction
< system.cpu.ipc 0.354427 # IPC: instructions per cycle
---
> system.cpu.quiesceCycles 5390009685 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.cpi 2.811846 # CPI: cycles per instruction
> system.cpu.ipc 0.355638 # IPC: instructions per cycle
516,522c518,524
< system.cpu.tickCycles 227544928 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 88020773 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.replacements 842581 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.947861 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 42538360 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 843093 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 50.455122 # Average number of references to valid blocks.
---
> system.cpu.tickCycles 227805023 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 87924977 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 842413 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.947858 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 42688411 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 842925 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 50.643190 # Average number of references to valid blocks.
524c526
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.947861 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.947858 # Average occupied blocks per requestor
528,530c530,532
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id
532,555c534,557
< system.cpu.dcache.tags.tag_accesses 175914832 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 175914832 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 23018220 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23018220 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 18257083 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 18257083 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 356514 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 356514 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 443429 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 443429 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 460179 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 460179 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 41275303 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 41275303 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 41631817 # number of overall hits
< system.cpu.dcache.overall_hits::total 41631817 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 492255 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 492255 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 547766 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 547766 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 169911 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 169911 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 22569 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 22569 # number of LoadLockedReq misses
---
> system.cpu.dcache.tags.tag_accesses 176513094 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 176513094 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 23118388 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23118388 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 18306742 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 18306742 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 356409 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 356409 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 443709 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 443709 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 460231 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 460231 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 41425130 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 41425130 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 41781539 # number of overall hits
> system.cpu.dcache.overall_hits::total 41781539 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 491811 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 491811 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 547829 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 547829 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 170067 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 170067 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 22347 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 22347 # number of LoadLockedReq misses
558,595c560,597
< system.cpu.dcache.demand_misses::cpu.data 1040021 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1040021 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1209932 # number of overall misses
< system.cpu.dcache.overall_misses::total 1209932 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 7281770758 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7281770758 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 23432647284 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 23432647284 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 285921000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 285921000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 30714418042 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 30714418042 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 30714418042 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 30714418042 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 23510475 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23510475 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 18804849 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 18804849 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 526425 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 526425 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465998 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 465998 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 460181 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 460181 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 42315324 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42315324 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 42841749 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 42841749 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020938 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.020938 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029129 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.029129 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322764 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.322764 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048432 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048432 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_misses::cpu.data 1039640 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1039640 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1209707 # number of overall misses
> system.cpu.dcache.overall_misses::total 1209707 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 7276171447 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7276171447 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 23463335520 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 23463335520 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 282730000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 282730000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 30739506967 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 30739506967 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 30739506967 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 30739506967 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 23610199 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23610199 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 18854571 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 18854571 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 526476 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 526476 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466056 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 466056 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 460233 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 460233 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 42464770 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42464770 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 42991246 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 42991246 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020830 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.020830 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029056 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.029056 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.323029 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.323029 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047949 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047949 # miss rate for LoadLockedReq accesses
598,614c600,616
< system.cpu.dcache.demand_miss_rate::cpu.data 0.024578 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.024578 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.028242 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.028242 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14792.680131 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14792.680131 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42778.572025 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 42778.572025 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12668.749169 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12668.749169 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 29532.497942 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 29532.497942 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 25385.243172 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 25385.243172 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 240 # number of cycles access was blocked
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.024482 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.024482 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.028138 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.028138 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14794.649666 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14794.649666 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42829.670426 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 42829.670426 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12651.810086 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12651.810086 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83500 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83500 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 29567.453125 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 29567.453125 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 25410.704383 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 25410.704383 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 271 # number of cycles access was blocked
616c618
< system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked
618c620
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.318182 # average number of cycles each access was blocked
622,641c624,643
< system.cpu.dcache.writebacks::writebacks 698329 # number of writebacks
< system.cpu.dcache.writebacks::total 698329 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75041 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 75041 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249041 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 249041 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14319 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 14319 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 324082 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 324082 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 324082 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 324082 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417214 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 417214 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298725 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 298725 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121762 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 121762 # number of SoftPFReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8250 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 8250 # number of LoadLockedReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 697807 # number of writebacks
> system.cpu.dcache.writebacks::total 697807 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74753 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 74753 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249005 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 249005 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14114 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 14114 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 323758 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 323758 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 323758 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 323758 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417058 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 417058 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298824 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 298824 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121668 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 121668 # number of SoftPFReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8233 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 8233 # number of LoadLockedReq MSHR misses
644,675c646,683
< system.cpu.dcache.demand_mshr_misses::cpu.data 715939 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 715939 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 837701 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 837701 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5703446143 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5703446143 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12331014162 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 12331014162 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562604290 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562604290 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 106206750 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 106206750 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18034460305 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 18034460305 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19597064595 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 19597064595 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5836567000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5836567000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4510270500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4510270500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346837500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346837500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017746 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017746 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015886 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015886 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231300 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231300 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017704 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017704 # mshr miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 715882 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 715882 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 837550 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 837550 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.ReadReq_mshr_uncacheable::total 31128 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
> system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5703692140 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5703692140 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12347213418 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 12347213418 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562689830 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562689830 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 105383000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105383000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 164000 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18050905558 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 18050905558 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19613595388 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 19613595388 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5837245750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5837245750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4509635000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4509635000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346880750 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346880750 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017664 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017664 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015849 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015849 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231099 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231099 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017665 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017665 # mshr miss rate for LoadLockedReq accesses
678,701c686,709
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016919 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.016919 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019553 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.019553 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13670.313419 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13670.313419 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41278.815506 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41278.815506 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12833.267276 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12833.267276 # average SoftPFReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12873.545455 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12873.545455 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81250 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81250 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25189.939792 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 25189.939792 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23393.865586 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 23393.865586 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016858 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.016858 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019482 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.019482 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13676.016621 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13676.016621 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41319.349912 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41319.349912 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12843.885245 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12843.885245 # average SoftPFReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12800.072877 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12800.072877 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25214.917484 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 25214.917484 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23417.820295 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 23417.820295 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187523.957530 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187523.957530 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163493.274843 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163493.274843 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176234.108600 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176234.108600 # average overall mshr uncacheable latency
703,707c711,715
< system.cpu.icache.tags.replacements 2897467 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.399907 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 54681814 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 2897979 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 18.868948 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 2897053 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.399913 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 54794053 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 2897565 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 18.910379 # Average number of references to valid blocks.
709c717
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.399907 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.399913 # Average occupied blocks per requestor
713c721
< system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
715c723
< system.cpu.icache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::2 196 # Occupied blocks per task id
717,754c725,762
< system.cpu.icache.tags.tag_accesses 60477795 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 60477795 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 54681814 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 54681814 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 54681814 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 54681814 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 54681814 # number of overall hits
< system.cpu.icache.overall_hits::total 54681814 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 2897991 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 2897991 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 2897991 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 2897991 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 2897991 # number of overall misses
< system.cpu.icache.overall_misses::total 2897991 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 39294300362 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 39294300362 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 39294300362 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 39294300362 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 39294300362 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 39294300362 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 57579805 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 57579805 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 57579805 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 57579805 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 57579805 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 57579805 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050330 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.050330 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.050330 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.050330 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.050330 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.050330 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13559.151965 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13559.151965 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13559.151965 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13559.151965 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13559.151965 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13559.151965 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 60589206 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 60589206 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 54794053 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 54794053 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 54794053 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 54794053 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 54794053 # number of overall hits
> system.cpu.icache.overall_hits::total 54794053 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 2897577 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 2897577 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 2897577 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 2897577 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 2897577 # number of overall misses
> system.cpu.icache.overall_misses::total 2897577 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 39289899153 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 39289899153 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 39289899153 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 39289899153 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 39289899153 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 39289899153 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 57691630 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 57691630 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 57691630 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 57691630 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 57691630 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 57691630 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050225 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.050225 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.050225 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.050225 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.050225 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.050225 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13559.570342 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13559.570342 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13559.570342 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13559.570342 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13559.570342 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13559.570342 # average overall miss latency
763,774c771,786
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897991 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 2897991 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 2897991 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 2897991 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 2897991 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 2897991 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34937740638 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 34937740638 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34937740638 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 34937740638 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34937740638 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 34937740638 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897577 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 2897577 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 2897577 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 2897577 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 2897577 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 2897577 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3172 # number of ReadReq MSHR uncacheable
> system.cpu.icache.ReadReq_mshr_uncacheable::total 3172 # number of ReadReq MSHR uncacheable
> system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3172 # number of overall MSHR uncacheable misses
> system.cpu.icache.overall_mshr_uncacheable_misses::total 3172 # number of overall MSHR uncacheable misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34933961847 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 34933961847 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34933961847 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 34933961847 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34933961847 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 34933961847 # number of overall MSHR miss cycles
779,794c791,806
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050330 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050330 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050330 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.050330 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050330 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.050330 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12055.848565 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12055.848565 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12055.848565 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12055.848565 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12055.848565 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12055.848565 # average overall mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
< system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
< system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050225 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050225 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050225 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.050225 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050225 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.050225 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12056.266959 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12056.266959 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12056.266959 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12056.266959 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12056.266959 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12056.266959 # average overall mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77990.778689 # average ReadReq mshr uncacheable latency
> system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77990.778689 # average ReadReq mshr uncacheable latency
> system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77990.778689 # average overall mshr uncacheable latency
> system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77990.778689 # average overall mshr uncacheable latency
796,800c808,812
< system.cpu.l2cache.tags.replacements 96766 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65065.875064 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4045925 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 162028 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 24.970530 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 97102 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65057.867689 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4043768 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 162361 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 24.906030 # Average number of references to valid blocks.
802,807c814,819
< system.cpu.l2cache.tags.occ_blocks::writebacks 47500.722639 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 67.826977 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000383 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 12189.076144 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 5308.248921 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.724804 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 47470.110176 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 67.851294 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.009474 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 12225.097724 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 5294.799022 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.724336 # Average percentage of cache occupancy
810,817c822,829
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.185991 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.080997 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.992826 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 44 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65218 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 44 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186540 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.080792 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.992704 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65201 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 58 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
819,852c831,864
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6937 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55861 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995148 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 36601578 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 36601578 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 70583 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4448 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 2875013 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 532926 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 3482970 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 698329 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 698329 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 53 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 53 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 164703 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 164703 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 70583 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 4448 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 2875013 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 697629 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 3647673 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 70583 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 4448 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 2875013 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 697629 # number of overall hits
< system.cpu.l2cache.overall_hits::total 3647673 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 121 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.inst 22948 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 14295 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 37365 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 2778 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 2778 # number of UpgradeReq misses
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6944 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55834 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000885 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994888 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 36586462 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 36586462 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69776 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4408 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 2874567 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 532630 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 3481381 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 697807 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 697807 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 52 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 52 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 164524 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 164524 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 69776 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 4408 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 2874567 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 697154 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 3645905 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 69776 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 4408 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 2874567 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 697154 # number of overall hits
> system.cpu.l2cache.overall_hits::total 3645905 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 120 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.inst 22985 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 14324 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 37431 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 2777 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 2777 # number of UpgradeReq misses
855,896c867,908
< system.cpu.l2cache.ReadExReq_misses::cpu.data 131196 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 131196 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 121 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.inst 22948 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 145491 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 168561 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 121 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.inst 22948 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 145491 # number of overall misses
< system.cpu.l2cache.overall_misses::total 168561 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 10389500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 82500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1838002000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1203040290 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 3051514290 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1092965 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 1092965 # number of UpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10205321187 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 10205321187 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 10389500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 82500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1838002000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 11408361477 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 13256835477 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 10389500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 82500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1838002000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 11408361477 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 13256835477 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 70704 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4449 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 2897961 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 547221 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 3520335 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 698329 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 698329 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2831 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2831 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 131476 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 131476 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 120 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 22985 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 145800 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 168907 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 120 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 22985 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 145800 # number of overall misses
> system.cpu.l2cache.overall_misses::total 168907 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 10600250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 179750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1839480250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1206111580 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 3056371830 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1094965 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 1094965 # number of UpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10223101190 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 10223101190 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 10600250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 179750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1839480250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11429212770 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 13279473020 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 10600250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 179750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1839480250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11429212770 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 13279473020 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69896 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4410 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 2897552 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 546954 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 3518812 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 697807 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 697807 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2829 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2829 # number of UpgradeReq accesses(hits+misses)
899,917c911,929
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 295899 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 295899 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 70704 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 4449 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 2897961 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 843120 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 3816234 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 70704 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 4449 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 2897961 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 843120 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 3816234 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001711 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000225 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.007919 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026123 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.010614 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.981279 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.981279 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 296000 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 296000 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69896 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 4410 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 2897552 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 842954 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 3814812 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69896 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 4410 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 2897552 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 842954 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 3814812 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001717 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000454 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.007933 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026189 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.010637 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.981619 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.981619 # miss rate for UpgradeReq accesses
920,952c932,964
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.443381 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.443381 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001711 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000225 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007919 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.172563 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.044169 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001711 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000225 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007919 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.172563 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.044169 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85863.636364 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82500 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80094.213003 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84158.117524 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 81667.718185 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 393.435925 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 393.435925 # average UpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80250 # average SCUpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77786.831817 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77786.831817 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85863.636364 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80094.213003 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78412.832938 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 78647.109812 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85863.636364 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80094.213003 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78412.832938 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 78647.109812 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.444176 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.444176 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001717 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000454 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007933 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.172963 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.044277 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001717 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000454 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007933 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.172963 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.044277 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88335.416667 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89875 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80029.595388 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84202.148841 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 81653.491224 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 394.297803 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 394.297803 # average UpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 81000 # average SCUpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 81000 # average SCUpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77756.405656 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77756.405656 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88335.416667 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89875 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80029.595388 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78389.662346 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 78620.027708 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88335.416667 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89875 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80029.595388 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78389.662346 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 78620.027708 # average overall miss latency
961,978c973,990
< system.cpu.l2cache.writebacks::writebacks 88357 # number of writebacks
< system.cpu.l2cache.writebacks::total 88357 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 18 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 143 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 161 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 18 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 143 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 161 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 18 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 143 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 161 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 121 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 22930 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14152 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 37204 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2778 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 2778 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.writebacks::writebacks 88550 # number of writebacks
> system.cpu.l2cache.writebacks::total 88550 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 20 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 140 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 160 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 20 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 140 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 160 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 20 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 140 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 160 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 120 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 22965 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14184 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 37271 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2777 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 2777 # number of UpgradeReq MSHR misses
981,1013c993,1033
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131196 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 131196 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 121 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 22930 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 145348 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 168400 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 121 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 22930 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 145348 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 168400 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 8873000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 70000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1549821750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1015754460 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2574519210 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 49350278 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 49350278 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 136000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 136000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8563537813 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8563537813 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8873000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 70000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1549821750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9579292273 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 11138057023 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8873000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 70000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1549821750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9579292273 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 11138057023 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131476 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 131476 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 120 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 22965 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 145660 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 168747 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 120 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 22965 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 145660 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 168747 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3172 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34300 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3172 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61883 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 9096750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 154250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1550905750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1018516170 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2578672920 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 49510277 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 49510277 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 137000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 137000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8577805310 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8577805310 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 9096750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 154250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1550905750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9596321480 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 11156478230 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 9096750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 154250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1550905750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9596321480 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 11156478230 # number of overall MSHR miss cycles
1015,1018c1035,1038
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5400289500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5592019250 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151564500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151564500 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5400947000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5592676750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4150934000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4150934000 # number of WriteReq MSHR uncacheable cycles
1020,1028c1040,1048
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9551854000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9743583750 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001711 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000225 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025862 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010568 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.981279 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9551881000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9743610750 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000454 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007926 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025933 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010592 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.981619 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.981619 # mshr miss rate for UpgradeReq accesses
1031,1071c1051,1091
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443381 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443381 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001711 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000225 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172393 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.044127 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001711 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000225 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172393 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.044127 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73330.578512 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67589.260794 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71774.622668 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69200.064778 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17764.678906 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17764.678906 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68000 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68000 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65272.857503 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65272.857503 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73330.578512 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67589.260794 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65905.910456 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66140.481134 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73330.578512 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67589.260794 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65905.910456 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66140.481134 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.444176 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.444176 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000454 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007926 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172797 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.044235 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000454 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007926 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172797 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.044235 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75806.250000 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 77125 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67533.453081 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71807.400592 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69187.113842 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17828.691754 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17828.691754 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68500 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65242.365983 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65242.365983 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75806.250000 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 77125 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67533.453081 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65881.652341 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66113.638939 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75806.250000 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 77125 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67533.453081 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65881.652341 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66113.638939 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60444.435687 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173507.677975 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163051.800292 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150488.851829 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150488.851829 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60444.435687 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162693.209109 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157452.139521 # average overall mshr uncacheable latency
1073,1074c1093,1094
< system.cpu.toL2Bus.trans_dist::ReadReq 3579472 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 3579378 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 3578143 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 3578049 # Transaction distribution
1077,1079c1097,1099
< system.cpu.toL2Bus.trans_dist::Writeback 698329 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2831 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 697807 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36253 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2829 # Transaction distribution
1081,1097c1101,1117
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2833 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 295899 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 295899 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5802295 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2507794 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15026 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159855 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 8484970 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185672448 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98844821 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17796 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 282816 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 284817881 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 61238 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 4578493 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 3.007970 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.088920 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2831 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 296000 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 296000 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5801472 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506940 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14959 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158425 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 8481796 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185646272 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98800797 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17640 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 279584 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 284744293 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 61425 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 4638617 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1.029225 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.168438 # Request fanout histogram
1100,1103c1120,1121
< system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::3 4542001 99.20% 99.20% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 36492 0.80% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 4503052 97.08% 97.08% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 135565 2.92% 100.00% # Request fanout histogram
1105,1108c1123,1126
< system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 4578493 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 3014061750 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 4638617 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 3012663750 # Layer occupancy (ticks)
1112c1130
< system.cpu.toL2Bus.respLayer0.occupancy 4357263112 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 4356641403 # Layer occupancy (ticks)
1114c1132
< system.cpu.toL2Bus.respLayer1.occupancy 1342100655 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1341917112 # Layer occupancy (ticks)
1116c1134
< system.cpu.toL2Bus.respLayer2.occupancy 10577000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 10549250 # Layer occupancy (ticks)
1118c1136
< system.cpu.toL2Bus.respLayer3.occupancy 89155750 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 88533000 # Layer occupancy (ticks)
1215c1233
< system.iobus.reqLayer27.occupancy 198870981 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 198836241 # Layer occupancy (ticks)
1221c1239
< system.iobus.respLayer3.occupancy 36810507 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 36810509 # Layer occupancy (ticks)
1224c1242
< system.iocache.tags.tagsinuse 1.031296 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.031382 # Cycle average of tags in use
1228,1231c1246,1249
< system.iocache.tags.warmup_cycle 270543128000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 1.031296 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.064456 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.064456 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 270536492000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 1.031382 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.064461 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.064461 # Average percentage of cache occupancy
1245,1252c1263,1270
< system.iocache.ReadReq_miss_latency::realview.ide 29239875 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 29239875 # number of ReadReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6646548599 # number of WriteInvalidateReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::total 6646548599 # number of WriteInvalidateReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 29239875 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 29239875 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 29239875 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 29239875 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 29235877 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 29235877 # number of ReadReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6642330855 # number of WriteInvalidateReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::total 6642330855 # number of WriteInvalidateReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 29235877 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 29235877 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 29235877 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 29235877 # number of overall miss cycles
1269,1277c1287,1295
< system.iocache.ReadReq_avg_miss_latency::realview.ide 124956.730769 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 124956.730769 # average ReadReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183484.667596 # average WriteInvalidateReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::total 183484.667596 # average WriteInvalidateReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 124956.730769 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 124956.730769 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 124956.730769 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 124956.730769 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 22676 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 124939.645299 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 124939.645299 # average ReadReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183368.232525 # average WriteInvalidateReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::total 183368.232525 # average WriteInvalidateReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 124939.645299 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 124939.645299 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 124939.645299 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 124939.645299 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 22431 # number of cycles access was blocked
1279c1297
< system.iocache.blocked::no_mshrs 3466 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3441 # number of cycles access was blocked
1281c1299
< system.iocache.avg_blocked_cycles::no_mshrs 6.542412 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 6.518745 # average number of cycles each access was blocked
1295,1302c1313,1320
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 16928877 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 16928877 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4762888611 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4762888611 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 16928877 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 16928877 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 16928877 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 16928877 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 16926877 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 16926877 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4758664873 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4758664873 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 16926877 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 16926877 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 16926877 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 16926877 # number of overall MSHR miss cycles
1311,1318c1329,1336
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72345.628205 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 72345.628205 # average ReadReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131484.336655 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131484.336655 # average WriteInvalidateReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 72345.628205 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 72345.628205 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 72345.628205 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 72345.628205 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72337.081197 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 72337.081197 # average ReadReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131367.736114 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131367.736114 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 72337.081197 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 72337.081197 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 72337.081197 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 72337.081197 # average overall mshr miss latency
1320,1321c1338,1339
< system.membus.trans_dist::ReadReq 71736 # Transaction distribution
< system.membus.trans_dist::ReadResp 71736 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 71805 # Transaction distribution
> system.membus.trans_dist::ReadResp 71805 # Transaction distribution
1324c1342
< system.membus.trans_dist::Writeback 124547 # Transaction distribution
---
> system.membus.trans_dist::Writeback 124740 # Transaction distribution
1327c1345
< system.membus.trans_dist::UpgradeReq 4591 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 4587 # Transaction distribution
1329,1331c1347,1349
< system.membus.trans_dist::UpgradeResp 4593 # Transaction distribution
< system.membus.trans_dist::ReadExReq 129383 # Transaction distribution
< system.membus.trans_dist::ReadExResp 129383 # Transaction distribution
---
> system.membus.trans_dist::UpgradeResp 4589 # Transaction distribution
> system.membus.trans_dist::ReadExReq 129666 # Transaction distribution
> system.membus.trans_dist::ReadExResp 129666 # Transaction distribution
1335,1336c1353,1354
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446633 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554193 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447521 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 555081 # Packet count per connected master and slave (bytes)
1339c1357
< system.membus.pkt_count::total 663080 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 663968 # Packet count per connected master and slave (bytes)
1343,1344c1361,1362
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16520600 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16684309 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16555296 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16719005 # Cumulative packet size per connected master and slave (bytes)
1347,1349c1365,1367
< system.membus.pkt_size::total 21319765 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 505 # Total snoops (count)
< system.membus.snoop_fanout::samples 332236 # Request fanout histogram
---
> system.membus.pkt_size::total 21354461 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 506 # Total snoops (count)
> system.membus.snoop_fanout::samples 394644 # Request fanout histogram
1354c1372
< system.membus.snoop_fanout::1 332236 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 394644 100.00% 100.00% # Request fanout histogram
1359,1360c1377,1378
< system.membus.snoop_fanout::total 332236 # Request fanout histogram
< system.membus.reqLayer0.occupancy 90365500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 394644 # Request fanout histogram
> system.membus.reqLayer0.occupancy 90290000 # Layer occupancy (ticks)
1364c1382
< system.membus.reqLayer2.occupancy 1715000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 1707500 # Layer occupancy (ticks)
1366c1384
< system.membus.reqLayer5.occupancy 1025055153 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 1026254667 # Layer occupancy (ticks)
1368c1386
< system.membus.respLayer2.occupancy 997764949 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 999643493 # Layer occupancy (ticks)
1370c1388
< system.membus.respLayer3.occupancy 37471493 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 37473491 # Layer occupancy (ticks)