3,5c3,5
< sim_seconds 2.852858 # Number of seconds simulated
< sim_ticks 2852857543000 # Number of ticks simulated
< final_tick 2852857543000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.853442 # Number of seconds simulated
> sim_ticks 2853442108500 # Number of ticks simulated
> final_tick 2853442108500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 109881 # Simulator instruction rate (inst/s)
< host_op_rate 132861 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2793727953 # Simulator tick rate (ticks/s)
< host_mem_usage 608784 # Number of bytes of host memory used
< host_seconds 1021.17 # Real time elapsed on the host
< sim_insts 112207125 # Number of instructions simulated
< sim_ops 135672670 # Number of ops (including micro ops) simulated
---
> host_inst_rate 171765 # Simulator instruction rate (inst/s)
> host_op_rate 207684 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 4374009836 # Simulator tick rate (ticks/s)
> host_mem_usage 619996 # Number of bytes of host memory used
> host_seconds 652.36 # Real time elapsed on the host
> sim_insts 112053421 # Number of instructions simulated
> sim_ops 135485276 # Number of ops (including micro ops) simulated
16c16
< system.physmem.bytes_read::cpu.dtb.walker 8192 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.dtb.walker 7296 # Number of bytes read from this memory
18,19c18,19
< system.physmem.bytes_read::cpu.inst 1662912 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9175012 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 1671680 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9169380 # Number of bytes read from this memory
21,24c21,24
< system.physmem.bytes_read::total 10847140 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1662912 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1662912 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7962752 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 10849380 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1671680 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1671680 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7972992 # Number of bytes written to this memory
26,27c26,27
< system.physmem.bytes_written::total 7980276 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.dtb.walker 128 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::total 7990516 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.dtb.walker 114 # Number of read requests responded to by this memory
29,30c29,30
< system.physmem.num_reads::cpu.inst 25983 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 143879 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 26120 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 143791 # Number of read requests responded to by this memory
32,33c32,33
< system.physmem.num_reads::total 170006 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 124418 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 170041 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 124578 # Number of write requests responded to by this memory
35,36c35,36
< system.physmem.num_writes::total 128799 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.dtb.walker 2872 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 128959 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 2557 # Total read bandwidth from this memory (bytes/s)
38,48c38,48
< system.physmem.bw_read::cpu.inst 582893 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3216078 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 3802202 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 582893 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 582893 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2791150 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 2797292 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2791150 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 2872 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 585847 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3213445 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 3802208 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 585847 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 585847 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2794166 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu.data 6141 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 2800308 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2794166 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 2557 # Total bandwidth to/from this memory (bytes/s)
50,97c50,97
< system.physmem.bw_total::cpu.inst 582893 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 3222220 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 6599494 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 170006 # Number of read requests accepted
< system.physmem.writeReqs 165023 # Number of write requests accepted
< system.physmem.readBursts 170006 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 165023 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 10873728 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue
< system.physmem.bytesWritten 10175104 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 10847140 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 10298612 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 6006 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 4596 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 10656 # Per bank write bursts
< system.physmem.perBankRdBursts::1 10651 # Per bank write bursts
< system.physmem.perBankRdBursts::2 10704 # Per bank write bursts
< system.physmem.perBankRdBursts::3 10614 # Per bank write bursts
< system.physmem.perBankRdBursts::4 13356 # Per bank write bursts
< system.physmem.perBankRdBursts::5 10666 # Per bank write bursts
< system.physmem.perBankRdBursts::6 11042 # Per bank write bursts
< system.physmem.perBankRdBursts::7 10972 # Per bank write bursts
< system.physmem.perBankRdBursts::8 10208 # Per bank write bursts
< system.physmem.perBankRdBursts::9 10672 # Per bank write bursts
< system.physmem.perBankRdBursts::10 10509 # Per bank write bursts
< system.physmem.perBankRdBursts::11 9657 # Per bank write bursts
< system.physmem.perBankRdBursts::12 10109 # Per bank write bursts
< system.physmem.perBankRdBursts::13 10747 # Per bank write bursts
< system.physmem.perBankRdBursts::14 9757 # Per bank write bursts
< system.physmem.perBankRdBursts::15 9582 # Per bank write bursts
< system.physmem.perBankWrBursts::0 10072 # Per bank write bursts
< system.physmem.perBankWrBursts::1 10092 # Per bank write bursts
< system.physmem.perBankWrBursts::2 10491 # Per bank write bursts
< system.physmem.perBankWrBursts::3 10304 # Per bank write bursts
< system.physmem.perBankWrBursts::4 9538 # Per bank write bursts
< system.physmem.perBankWrBursts::5 9899 # Per bank write bursts
< system.physmem.perBankWrBursts::6 10133 # Per bank write bursts
< system.physmem.perBankWrBursts::7 10134 # Per bank write bursts
< system.physmem.perBankWrBursts::8 10091 # Per bank write bursts
< system.physmem.perBankWrBursts::9 10380 # Per bank write bursts
< system.physmem.perBankWrBursts::10 10169 # Per bank write bursts
< system.physmem.perBankWrBursts::11 9697 # Per bank write bursts
< system.physmem.perBankWrBursts::12 9799 # Per bank write bursts
< system.physmem.perBankWrBursts::13 10201 # Per bank write bursts
< system.physmem.perBankWrBursts::14 9040 # Per bank write bursts
< system.physmem.perBankWrBursts::15 8946 # Per bank write bursts
---
> system.physmem.bw_total::cpu.inst 585847 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 3219587 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 6602516 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 170041 # Number of read requests accepted
> system.physmem.writeReqs 165183 # Number of write requests accepted
> system.physmem.readBursts 170041 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 165183 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 10875008 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue
> system.physmem.bytesWritten 9072064 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 10849380 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 10308852 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 23407 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 4604 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 10431 # Per bank write bursts
> system.physmem.perBankRdBursts::1 10779 # Per bank write bursts
> system.physmem.perBankRdBursts::2 11040 # Per bank write bursts
> system.physmem.perBankRdBursts::3 10735 # Per bank write bursts
> system.physmem.perBankRdBursts::4 13061 # Per bank write bursts
> system.physmem.perBankRdBursts::5 10390 # Per bank write bursts
> system.physmem.perBankRdBursts::6 11080 # Per bank write bursts
> system.physmem.perBankRdBursts::7 11267 # Per bank write bursts
> system.physmem.perBankRdBursts::8 10153 # Per bank write bursts
> system.physmem.perBankRdBursts::9 10232 # Per bank write bursts
> system.physmem.perBankRdBursts::10 10264 # Per bank write bursts
> system.physmem.perBankRdBursts::11 9394 # Per bank write bursts
> system.physmem.perBankRdBursts::12 10277 # Per bank write bursts
> system.physmem.perBankRdBursts::13 10799 # Per bank write bursts
> system.physmem.perBankRdBursts::14 10090 # Per bank write bursts
> system.physmem.perBankRdBursts::15 9930 # Per bank write bursts
> system.physmem.perBankWrBursts::0 8676 # Per bank write bursts
> system.physmem.perBankWrBursts::1 9067 # Per bank write bursts
> system.physmem.perBankWrBursts::2 9547 # Per bank write bursts
> system.physmem.perBankWrBursts::3 9319 # Per bank write bursts
> system.physmem.perBankWrBursts::4 8434 # Per bank write bursts
> system.physmem.perBankWrBursts::5 8678 # Per bank write bursts
> system.physmem.perBankWrBursts::6 9214 # Per bank write bursts
> system.physmem.perBankWrBursts::7 9423 # Per bank write bursts
> system.physmem.perBankWrBursts::8 8918 # Per bank write bursts
> system.physmem.perBankWrBursts::9 8886 # Per bank write bursts
> system.physmem.perBankWrBursts::10 8752 # Per bank write bursts
> system.physmem.perBankWrBursts::11 8449 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8824 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8894 # Per bank write bursts
> system.physmem.perBankWrBursts::14 8297 # Per bank write bursts
> system.physmem.perBankWrBursts::15 8373 # Per bank write bursts
99,100c99,100
< system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
< system.physmem.totGap 2852857119000 # Total gap between requests
---
> system.physmem.numWrRetry 40 # Number of times write queue was full causing retry
> system.physmem.totGap 2853441702500 # Total gap between requests
107c107
< system.physmem.readPktSize::6 169451 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 169486 # Read request sizes (log2)
114,117c114,117
< system.physmem.writePktSize::6 160642 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 163533 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 6320 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 160802 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 163468 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 6406 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see
162,287c162,272
< system.physmem.wrQLenPdf::15 2240 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3913 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 7826 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 8953 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 9279 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 10066 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 10452 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 11206 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 11037 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 11618 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 10744 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 10251 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 9284 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 8811 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 7662 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 7362 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 7187 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 7081 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 369 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 334 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 303 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 264 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 255 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 256 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 240 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 236 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 236 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 218 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 201 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 162 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 73 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 56 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 26 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 14 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 8 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 62962 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 334.308059 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 193.690406 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 348.894179 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 22562 35.83% 35.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14454 22.96% 58.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6551 10.40% 69.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3518 5.59% 74.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2542 4.04% 78.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1533 2.43% 81.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1128 1.79% 83.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1127 1.79% 84.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 9547 15.16% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 62962 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6648 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 25.554603 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 562.154464 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6646 99.97% 99.97% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 6648 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6648 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 23.914862 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 19.938842 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 22.611148 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5537 83.29% 83.29% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 45 0.68% 83.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 19 0.29% 84.25% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 242 3.64% 87.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 123 1.85% 89.74% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 53 0.80% 90.54% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 26 0.39% 90.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 33 0.50% 91.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 114 1.71% 93.14% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 19 0.29% 93.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 14 0.21% 93.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 11 0.17% 93.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 33 0.50% 94.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 20 0.30% 94.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 10 0.15% 94.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 22 0.33% 95.08% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 60 0.90% 95.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 16 0.24% 96.22% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 7 0.11% 96.33% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 13 0.20% 96.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 84 1.26% 97.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 5 0.08% 97.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 9 0.14% 98.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 9 0.14% 98.13% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 15 0.23% 98.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 3 0.05% 98.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 10 0.15% 98.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 3 0.05% 98.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 37 0.56% 99.16% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 8 0.12% 99.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 4 0.06% 99.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 9 0.14% 99.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 5 0.08% 99.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 4 0.06% 99.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-163 2 0.03% 99.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 4 0.06% 99.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::168-171 5 0.08% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 2 0.03% 99.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 1 0.02% 99.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::180-183 1 0.02% 99.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-187 2 0.03% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::188-191 1 0.02% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-195 1 0.02% 99.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::196-199 1 0.02% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::200-203 4 0.06% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-227 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::232-235 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6648 # Writes before turning the bus around for reads
< system.physmem.totQLat 1659710000 # Total ticks spent queuing
< system.physmem.totMemAccLat 4845372500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 849510000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 9768.63 # Average queueing delay per DRAM burst
---
> system.physmem.wrQLenPdf::15 1516 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 1813 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5347 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6005 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6027 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5842 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6230 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6324 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 7720 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 6542 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 6696 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 7845 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 6904 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6687 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 8673 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 7583 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6877 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6843 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 1218 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 1028 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 1305 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 2232 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 2241 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 1757 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 1803 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 2628 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 2085 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 1860 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 1791 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 1847 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 1817 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 1379 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 1327 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 1020 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 736 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 354 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 280 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 202 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 187 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 175 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 123 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 130 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 172 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 121 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 68 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 93 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 53 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 100 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 61793 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 322.802648 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 189.147121 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 338.470119 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 22296 36.08% 36.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 14465 23.41% 59.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6637 10.74% 70.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3539 5.73% 75.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2616 4.23% 80.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1600 2.59% 82.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1149 1.86% 84.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1212 1.96% 86.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8279 13.40% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 61793 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5874 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 28.927818 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 584.509202 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 5873 99.98% 99.98% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 5874 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5873 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 24.134684 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.418054 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 43.798135 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-31 5542 94.36% 94.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-47 90 1.53% 95.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-63 17 0.29% 96.19% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-79 15 0.26% 96.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-95 16 0.27% 96.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-111 28 0.48% 97.19% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-127 28 0.48% 97.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-143 13 0.22% 97.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-159 10 0.17% 98.06% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-175 8 0.14% 98.20% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-191 17 0.29% 98.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-207 16 0.27% 98.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-223 10 0.17% 98.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-239 6 0.10% 99.03% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-271 3 0.05% 99.08% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::272-287 5 0.09% 99.17% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::288-303 7 0.12% 99.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::304-319 1 0.02% 99.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::320-335 5 0.09% 99.39% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::336-351 11 0.19% 99.57% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::352-367 8 0.14% 99.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::368-383 2 0.03% 99.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::384-399 3 0.05% 99.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::416-431 1 0.02% 99.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::480-495 1 0.02% 99.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::528-543 3 0.05% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::544-559 1 0.02% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::560-575 1 0.02% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::592-607 1 0.02% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::672-687 1 0.02% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::688-703 1 0.02% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5873 # Writes before turning the bus around for reads
> system.physmem.totQLat 1685079736 # Total ticks spent queuing
> system.physmem.totMemAccLat 4871117236 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 849610000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 9916.78 # Average queueing delay per DRAM burst
289c274
< system.physmem.avgMemAccLat 28518.63 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 28666.78 # Average memory access latency per DRAM burst
291c276
< system.physmem.avgWrBW 3.57 # Average achieved write bandwidth in MiByte/s
---
> system.physmem.avgWrBW 3.18 # Average achieved write bandwidth in MiByte/s
295c280
< system.physmem.busUtil 0.06 # Data bus utilization in percentage
---
> system.physmem.busUtil 0.05 # Data bus utilization in percentage
297,316c282,301
< system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
< system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 27.33 # Average write queue length when enqueuing
< system.physmem.readRowHits 140084 # Number of row buffer hits during reads
< system.physmem.writeRowHits 125841 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 82.45 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 79.14 # Row buffer hit rate for writes
< system.physmem.avgGap 8515254.26 # Average gap between requests
< system.physmem.pageHitRate 80.85 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 246909600 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 134722500 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 691555800 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 522696240 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 186334349760 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 83503223595 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1638462219000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1909895676495 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.469106 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 2725585905000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 95262960000 # Time in different power states
---
> system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
> system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing
> system.physmem.readRowHits 140217 # Number of row buffer hits during reads
> system.physmem.writeRowHits 109661 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 82.52 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 77.35 # Row buffer hit rate for writes
> system.physmem.avgGap 8512044.79 # Average gap between requests
> system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 242267760 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 132189750 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 692507400 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 468860400 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 186372491760 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 83617160895 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1638712655250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1910238133215 # Total energy per rank (pJ)
> system.physmem_0.averagePower 669.452112 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 2726011845150 # Time in different power states
> system.physmem_0.memoryStateTime::REF 95282460000 # Time in different power states
318c303
< system.physmem_0.memoryStateTime::ACT 32002250000 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 32147776350 # Time in different power states
320,330c305,315
< system.physmem_1.actEnergy 229083120 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 124995750 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 633664200 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 507533040 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 186334349760 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 82044200295 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1639742072250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1909615898415 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.371033 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 2727729306000 # Time in different power states
< system.physmem_1.memoryStateTime::REF 95262960000 # Time in different power states
---
> system.physmem_1.actEnergy 224857080 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 122689875 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 632876400 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 449634240 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 186372491760 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 82395435150 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1639784344500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1909982329005 # Total energy per rank (pJ)
> system.physmem_1.averagePower 669.362464 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2727805815350 # Time in different power states
> system.physmem_1.memoryStateTime::REF 95282460000 # Time in different power states
332c317
< system.physmem_1.memoryStateTime::ACT 29860939000 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 30353736650 # Time in different power states
352,356c337,341
< system.cpu.branchPred.lookups 31058702 # Number of BP lookups
< system.cpu.branchPred.condPredicted 16880390 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 2530392 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 18557624 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 13376459 # Number of BTB hits
---
> system.cpu.branchPred.lookups 31053109 # Number of BP lookups
> system.cpu.branchPred.condPredicted 16852863 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 2525514 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 18620216 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 13364906 # Number of BTB hits
358,360c343,345
< system.cpu.branchPred.BTBHitPct 72.080666 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 7810096 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 1523796 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 71.776321 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 7853668 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 1516989 # Number of incorrect RAS predictions.
391,414c376,400
< system.cpu.dtb.walker.walks 66845 # Table walker walks requested
< system.cpu.dtb.walker.walksShort 66845 # Table walker walks initiated with short descriptors
< system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43967 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22878 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walkWaitTime::samples 66845 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0 66845 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::total 66845 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 7791 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 10107.303299 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 7513.505454 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 7923.201613 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-32767 7786 99.94% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::131072-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::total 7791 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walksPending::samples 234495500 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::0 234495500 100.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::total 234495500 # Table walker pending requests distribution
< system.cpu.dtb.walker.walkPageSizes::4K 6429 82.52% 82.52% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::1M 1362 17.48% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 7791 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66845 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walks 65844 # Table walker walks requested
> system.cpu.dtb.walker.walksShort 65844 # Table walker walks initiated with short descriptors
> system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43330 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22514 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walkWaitTime::samples 65844 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0 65844 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::total 65844 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 7786 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 11086.116106 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 8821.657087 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 7338.018596 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-16383 6073 78.00% 78.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::16384-32767 1707 21.92% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::163840-180223 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::total 7786 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walksPending::samples 262515000 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::0 262515000 100.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::total 262515000 # Table walker pending requests distribution
> system.cpu.dtb.walker.walkPageSizes::4K 6400 82.20% 82.20% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::1M 1386 17.80% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 7786 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 65844 # Table walker requests started/completed, data/inst
416,417c402,403
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66845 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7791 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 65844 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7786 # Table walker requests started/completed, data/inst
419,420c405,406
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7791 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 74636 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7786 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 73630 # Table walker requests started/completed, data/inst
423,426c409,412
< system.cpu.dtb.read_hits 24793006 # DTB read hits
< system.cpu.dtb.read_misses 59858 # DTB read misses
< system.cpu.dtb.write_hits 19468400 # DTB write hits
< system.cpu.dtb.write_misses 6987 # DTB write misses
---
> system.cpu.dtb.read_hits 24757406 # DTB read hits
> system.cpu.dtb.read_misses 59085 # DTB read misses
> system.cpu.dtb.write_hits 19449348 # DTB write hits
> system.cpu.dtb.write_misses 6759 # DTB write misses
432,433c418,419
< system.cpu.dtb.align_faults 1289 # Number of TLB faults due to alignment restrictions
< system.cpu.dtb.prefetch_faults 1775 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.align_faults 1268 # Number of TLB faults due to alignment restrictions
> system.cpu.dtb.prefetch_faults 1766 # Number of TLB faults due to prefetch
435,437c421,423
< system.cpu.dtb.perms_faults 757 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 24852864 # DTB read accesses
< system.cpu.dtb.write_accesses 19475387 # DTB write accesses
---
> system.cpu.dtb.perms_faults 739 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 24816491 # DTB read accesses
> system.cpu.dtb.write_accesses 19456107 # DTB write accesses
439,441c425,427
< system.cpu.dtb.hits 44261406 # DTB hits
< system.cpu.dtb.misses 66845 # DTB misses
< system.cpu.dtb.accesses 44328251 # DTB accesses
---
> system.cpu.dtb.hits 44206754 # DTB hits
> system.cpu.dtb.misses 65844 # DTB misses
> system.cpu.dtb.accesses 44272598 # DTB accesses
471,492c457,478
< system.cpu.itb.walker.walks 5440 # Table walker walks requested
< system.cpu.itb.walker.walksShort 5440 # Table walker walks initiated with short descriptors
< system.cpu.itb.walker.walksShortTerminationLevel::Level1 316 # Level at which table walker walks with short descriptors terminate
< system.cpu.itb.walker.walksShortTerminationLevel::Level2 5124 # Level at which table walker walks with short descriptors terminate
< system.cpu.itb.walker.walkWaitTime::samples 5440 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::0 5440 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::total 5440 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkCompletionTime::samples 3188 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::mean 10236.198243 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 7641.069075 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 7067.497935 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::0-8191 1310 41.09% 41.09% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::8192-16383 1157 36.29% 77.38% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::16384-24575 720 22.58% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::73728-81919 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::total 3188 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walksPending::samples 234126500 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::0 234126500 100.00% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::total 234126500 # Table walker pending requests distribution
< system.cpu.itb.walker.walkPageSizes::4K 2879 90.31% 90.31% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::1M 309 9.69% 100.00% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::total 3188 # Table walker page sizes translated
---
> system.cpu.itb.walker.walks 5446 # Table walker walks requested
> system.cpu.itb.walker.walksShort 5446 # Table walker walks initiated with short descriptors
> system.cpu.itb.walker.walksShortTerminationLevel::Level1 324 # Level at which table walker walks with short descriptors terminate
> system.cpu.itb.walker.walksShortTerminationLevel::Level2 5122 # Level at which table walker walks with short descriptors terminate
> system.cpu.itb.walker.walkWaitTime::samples 5446 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::0 5446 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::total 5446 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkCompletionTime::samples 3184 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::mean 11253.454774 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 8989.562910 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 7050.042435 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::0-8191 1281 40.23% 40.23% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::8192-16383 1185 37.22% 77.45% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::16384-24575 717 22.52% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::total 3184 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walksPending::samples 262109500 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::0 262109500 100.00% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::total 262109500 # Table walker pending requests distribution
> system.cpu.itb.walker.walkPageSizes::4K 2875 90.30% 90.30% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::1M 309 9.70% 100.00% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::total 3184 # Table walker page sizes translated
494,495c480,481
< system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5440 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Requested::total 5440 # Table walker requests started/completed, data/inst
---
> system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5446 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Requested::total 5446 # Table walker requests started/completed, data/inst
497,501c483,487
< system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3188 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Completed::total 3188 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin::total 8628 # Table walker requests started/completed, data/inst
< system.cpu.itb.inst_hits 57692911 # ITB inst hits
< system.cpu.itb.inst_misses 5440 # ITB inst misses
---
> system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3184 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Completed::total 3184 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin::total 8630 # Table walker requests started/completed, data/inst
> system.cpu.itb.inst_hits 57726188 # ITB inst hits
> system.cpu.itb.inst_misses 5446 # ITB inst misses
510c496
< system.cpu.itb.flush_entries 2976 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_entries 2973 # Number of entries that have been flushed from TLB
514c500
< system.cpu.itb.perms_faults 8340 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 8450 # Number of TLB faults due to permissions restrictions
517,521c503,507
< system.cpu.itb.inst_accesses 57698351 # ITB inst accesses
< system.cpu.itb.hits 57692911 # DTB hits
< system.cpu.itb.misses 5440 # DTB misses
< system.cpu.itb.accesses 57698351 # DTB accesses
< system.cpu.numCycles 314937774 # number of cpu cycles simulated
---
> system.cpu.itb.inst_accesses 57731634 # ITB inst accesses
> system.cpu.itb.hits 57726188 # DTB hits
> system.cpu.itb.misses 5446 # DTB misses
> system.cpu.itb.accesses 57731634 # DTB accesses
> system.cpu.numCycles 317415724 # number of cpu cycles simulated
524,526c510,512
< system.cpu.committedInsts 112207125 # Number of instructions committed
< system.cpu.committedOps 135672670 # Number of ops (including micro ops) committed
< system.cpu.discardedOps 7783589 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.committedInsts 112053421 # Number of instructions committed
> system.cpu.committedOps 135485276 # Number of ops (including micro ops) committed
> system.cpu.discardedOps 7764036 # Number of ops (including micro ops) which were discarded before commit
528,530c514,516
< system.cpu.quiesceCycles 5390825701 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.cpi 2.806754 # CPI: cycles per instruction
< system.cpu.ipc 0.356283 # IPC: instructions per cycle
---
> system.cpu.quiesceCycles 5389516808 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.cpi 2.832718 # CPI: cycles per instruction
> system.cpu.ipc 0.353018 # IPC: instructions per cycle
533,543c519,529
< system.cpu.tickCycles 228221487 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 86716287 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.replacements 841983 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.953279 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 42762284 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 842495 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 50.756721 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 281436250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.953279 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999909 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy
---
> system.cpu.tickCycles 228406815 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 89008909 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 842109 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.947879 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 42706608 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 842621 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 50.683057 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 313221250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.947879 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999898 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999898 # Average percentage of cache occupancy
545,547c531,533
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 357 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id
549,568c535,554
< system.cpu.dcache.tags.tag_accesses 176413277 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 176413277 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 23536274 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23536274 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 18304900 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 18304900 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 457909 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 457909 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 460268 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 460268 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 41841174 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 41841174 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 41841174 # number of overall hits
< system.cpu.dcache.overall_hits::total 41841174 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 583393 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 583393 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 541748 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 541748 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 8195 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 8195 # number of LoadLockedReq misses
---
> system.cpu.dcache.tags.tag_accesses 176191359 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 176191359 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 23499832 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23499832 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 18286134 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 18286134 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 457571 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 457571 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 460116 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 460116 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 41785966 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 41785966 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 41785966 # number of overall hits
> system.cpu.dcache.overall_hits::total 41785966 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 583874 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 583874 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 541283 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 541283 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 8366 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 8366 # number of LoadLockedReq misses
571,604c557,590
< system.cpu.dcache.demand_misses::cpu.data 1125141 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1125141 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1125141 # number of overall misses
< system.cpu.dcache.overall_misses::total 1125141 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 8651014339 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 8651014339 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 21393186307 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 21393186307 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 116036500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 116036500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150500 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 150500 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 30044200646 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 30044200646 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 30044200646 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 30044200646 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 24119667 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 24119667 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 18846648 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 18846648 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466104 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 466104 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 460270 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 460270 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 42966315 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42966315 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 42966315 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 42966315 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024187 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.024187 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028745 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.028745 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017582 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017582 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_misses::cpu.data 1125157 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1125157 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1125157 # number of overall misses
> system.cpu.dcache.overall_misses::total 1125157 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 8774452459 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 8774452459 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 23299729316 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 23299729316 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 120081750 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 120081750 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 32074181775 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 32074181775 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 32074181775 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 32074181775 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 24083706 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 24083706 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 18827417 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 18827417 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465937 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 465937 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 460118 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 460118 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 42911123 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42911123 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 42911123 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 42911123 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024244 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.024244 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028750 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.028750 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017955 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017955 # miss rate for LoadLockedReq accesses
607,622c593,608
< system.cpu.dcache.demand_miss_rate::cpu.data 0.026187 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.026187 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.026187 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.026187 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14828.793522 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14828.793522 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39489.183729 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 39489.183729 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14159.426480 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14159.426480 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75250 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75250 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 26702.609403 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 26702.609403 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 26702.609403 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 26702.609403 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.026221 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.026221 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.026221 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.026221 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15027.989702 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 15027.989702 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43045.374261 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 43045.374261 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14353.544107 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14353.544107 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 28506.405573 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 28506.405573 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 28506.405573 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 28506.405573 # average overall miss latency
631,646c617,632
< system.cpu.dcache.writebacks::writebacks 698310 # number of writebacks
< system.cpu.dcache.writebacks::total 698310 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45149 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 45149 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 242834 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 242834 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 287983 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 287983 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 287983 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 287983 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 538244 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 538244 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298914 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 298914 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8195 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 8195 # number of LoadLockedReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 697919 # number of writebacks
> system.cpu.dcache.writebacks::total 697919 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45195 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 45195 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 242825 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 242825 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 288020 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 288020 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 288020 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 288020 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 538679 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 538679 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298458 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 298458 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8366 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 8366 # number of LoadLockedReq MSHR misses
649,676c635,662
< system.cpu.dcache.demand_mshr_misses::cpu.data 837158 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 837158 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 837158 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 837158 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6893184142 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6893184142 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11166823654 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11166823654 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99620500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99620500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146500 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146500 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18060007796 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 18060007796 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18060007796 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 18060007796 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5790998000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790998000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4439562500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439562500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10230560500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230560500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.022316 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022316 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015860 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015860 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017582 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017582 # mshr miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 837137 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 837137 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 837137 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 837137 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7251218502 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7251218502 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12288582898 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 12288582898 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 107501250 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 107501250 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19539801400 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 19539801400 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19539801400 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 19539801400 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5836783750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5836783750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4510033500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4510033500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346817250 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346817250 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.022367 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022367 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015852 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015852 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017955 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017955 # mshr miss rate for LoadLockedReq accesses
679,694c665,680
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.019484 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.019484 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019484 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.019484 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12806.801640 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12806.801640 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37357.981406 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37357.981406 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12156.253813 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12156.253813 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73250 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73250 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21572.997924 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 21572.997924 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21572.997924 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 21572.997924 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.019509 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.019509 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019509 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.019509 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13461.112280 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13461.112280 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41173.575170 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41173.575170 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12849.778867 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12849.778867 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81250 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81250 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23341.223002 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 23341.223002 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23341.223002 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 23341.223002 # average overall mshr miss latency
702,710c688,696
< system.cpu.icache.tags.replacements 2900110 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.424371 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 54783568 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 2900622 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 18.886835 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 15309705250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.424371 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.998876 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.998876 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 2898605 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.397830 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 54818221 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 2899117 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 18.908592 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 15715014250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.397830 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.998824 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.998824 # Average percentage of cache occupancy
712,714c698,700
< system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id
716,753c702,739
< system.cpu.icache.tags.tag_accesses 60584835 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 60584835 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 54783568 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 54783568 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 54783568 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 54783568 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 54783568 # number of overall hits
< system.cpu.icache.overall_hits::total 54783568 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 2900634 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 2900634 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 2900634 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 2900634 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 2900634 # number of overall misses
< system.cpu.icache.overall_misses::total 2900634 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 39169046291 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 39169046291 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 39169046291 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 39169046291 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 39169046291 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 39169046291 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 57684202 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 57684202 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 57684202 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 57684202 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 57684202 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 57684202 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050285 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.050285 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.050285 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.050285 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.050285 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.050285 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13503.615517 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13503.615517 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13503.615517 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13503.615517 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13503.615517 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13503.615517 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 60616478 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 60616478 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 54818221 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 54818221 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 54818221 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 54818221 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 54818221 # number of overall hits
> system.cpu.icache.overall_hits::total 54818221 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 2899129 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 2899129 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 2899129 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 2899129 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 2899129 # number of overall misses
> system.cpu.icache.overall_misses::total 2899129 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 39309012875 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 39309012875 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 39309012875 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 39309012875 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 39309012875 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 39309012875 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 57717350 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 57717350 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 57717350 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 57717350 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 57717350 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 57717350 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050230 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.050230 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.050230 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.050230 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.050230 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.050230 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13558.904373 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13558.904373 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13558.904373 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13558.904373 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13558.904373 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13558.904373 # average overall miss latency
762,789c748,775
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2900634 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 2900634 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 2900634 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 2900634 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 2900634 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 2900634 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33358375709 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 33358375709 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33358375709 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 33358375709 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33358375709 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 33358375709 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 222066250 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 222066250 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 222066250 # number of overall MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::total 222066250 # number of overall MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050285 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050285 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050285 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.050285 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050285 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.050285 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11500.373956 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11500.373956 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11500.373956 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11500.373956 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11500.373956 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11500.373956 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2899129 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 2899129 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 2899129 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 2899129 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 2899129 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 2899129 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34950907125 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 34950907125 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34950907125 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 34950907125 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34950907125 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 34950907125 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 247386750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 247386750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 247386750 # number of overall MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::total 247386750 # number of overall MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050230 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050230 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050230 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.050230 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050230 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.050230 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12055.657794 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12055.657794 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12055.657794 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12055.657794 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12055.657794 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12055.657794 # average overall mshr miss latency
795,799c781,785
< system.cpu.l2cache.tags.replacements 96921 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65071.012008 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4047776 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 162169 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 24.960233 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 96782 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65059.413288 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4045474 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 162031 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 24.967284 # Average number of references to valid blocks.
801,807c787,793
< system.cpu.l2cache.tags.occ_blocks::writebacks 47498.508165 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 71.489031 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000365 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 12194.784847 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 5306.229599 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.724770 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001091 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 47373.506796 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 67.256900 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000383 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 12244.945403 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 5373.703806 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.722862 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001026 # Average percentage of cache occupancy
809,845c795,831
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186078 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.080967 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.992905 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 37 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65211 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 37 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2285 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6934 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55872 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000565 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995041 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 36621683 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 36621683 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 71038 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4429 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 2877594 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 532037 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 3485098 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 698310 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 698310 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 53 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 53 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 164919 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 164919 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 71038 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 4429 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 2877594 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 696956 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 3650017 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 71038 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 4429 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 2877594 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 696956 # number of overall hits
< system.cpu.l2cache.overall_hits::total 3650017 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 128 # number of ReadReq misses
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186843 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.081996 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.992728 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 31 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65218 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2276 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6932 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55893 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000473 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995148 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 36598730 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 36598730 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69951 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4476 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 2876131 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 532779 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 3483337 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 697919 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 697919 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 49 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 49 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 164415 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 164415 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 69951 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 4476 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 2876131 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 697194 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 3647752 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 69951 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 4476 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 2876131 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 697194 # number of overall hits
> system.cpu.l2cache.overall_hits::total 3647752 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 114 # number of ReadReq misses
847,851c833,837
< system.cpu.l2cache.ReadReq_misses::cpu.inst 23013 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 14397 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 37539 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 2779 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 2779 # number of UpgradeReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 22980 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 14261 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 37356 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 2807 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 2807 # number of UpgradeReq misses
854,856c840,842
< system.cpu.l2cache.ReadExReq_misses::cpu.data 131168 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 131168 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 128 # number of demand (read+write) misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 131192 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 131192 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 114 # number of demand (read+write) misses
858,861c844,847
< system.cpu.l2cache.demand_misses::cpu.inst 23013 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 145565 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 168707 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 128 # number of overall misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 22980 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 145453 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 168548 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 114 # number of overall misses
863,895c849,881
< system.cpu.l2cache.overall_misses::cpu.inst 23013 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 145565 # number of overall misses
< system.cpu.l2cache.overall_misses::total 168707 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 10214250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 74500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1672158250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1100939750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 2783386750 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 790966 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 790966 # number of UpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 144500 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144500 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9154216683 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 9154216683 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 10214250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 74500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1672158250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10255156433 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 11937603433 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 10214250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 74500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1672158250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10255156433 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 11937603433 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 71166 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4430 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 2900607 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 546434 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 3522637 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 698310 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 698310 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2832 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2832 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::cpu.inst 22980 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 145453 # number of overall misses
> system.cpu.l2cache.overall_misses::total 168548 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 9734000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 82500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1838541652 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1191731612 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 3040089764 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1092965 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 1092965 # number of UpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10173645453 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 10173645453 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 9734000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 82500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1838541652 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11365377065 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 13213735217 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 9734000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 82500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1838541652 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11365377065 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 13213735217 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 70065 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4477 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 2899111 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 547040 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 3520693 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 697919 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 697919 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2856 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2856 # number of UpgradeReq accesses(hits+misses)
898,916c884,902
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 296087 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 296087 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 71166 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 4430 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 2900607 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 842521 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 3818724 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 71166 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 4430 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 2900607 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 842521 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 3818724 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001799 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000226 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.007934 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026347 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.010657 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.981285 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.981285 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 295607 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 295607 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 70065 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 4477 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 2899111 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 842647 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 3816300 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 70065 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 4477 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 2899111 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 842647 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 3816300 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001627 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000223 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.007927 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026069 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.010610 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.982843 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.982843 # miss rate for UpgradeReq accesses
919,951c905,937
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.443005 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.443005 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001799 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000226 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007934 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.172773 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.044179 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001799 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000226 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007934 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.172773 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.044179 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79798.828125 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74500 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72661.463086 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76470.080572 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 74146.534271 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 284.622526 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 284.622526 # average UpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 72250 # average SCUpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72250 # average SCUpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69790.014966 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69790.014966 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79798.828125 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72661.463086 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70450.701975 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 70759.384216 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79798.828125 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72661.463086 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70450.701975 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 70759.384216 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.443805 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.443805 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001627 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000223 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007927 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.172614 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.044165 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001627 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000223 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007927 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.172614 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.044165 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85385.964912 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82500 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80006.164143 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83565.781642 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 81381.565585 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 389.371215 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 389.371215 # average UpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80250 # average SCUpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77547.757889 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77547.757889 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85385.964912 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80006.164143 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78137.797536 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 78397.460765 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85385.964912 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80006.164143 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78137.797536 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 78397.460765 # average overall miss latency
960,963c946,949
< system.cpu.l2cache.writebacks::writebacks 88228 # number of writebacks
< system.cpu.l2cache.writebacks::total 88228 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 20 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 142 # number of ReadReq MSHR hits
---
> system.cpu.l2cache.writebacks::writebacks 88388 # number of writebacks
> system.cpu.l2cache.writebacks::total 88388 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 140 # number of ReadReq MSHR hits
965,966c951,952
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 20 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 142 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 140 # number of demand (read+write) MSHR hits
968,969c954,955
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 20 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 142 # number of overall MSHR hits
---
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 140 # number of overall MSHR hits
971c957
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 128 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 114 # number of ReadReq MSHR misses
973,977c959,963
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 22993 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14255 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 37377 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2779 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 2779 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 22958 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14121 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 37194 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2807 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 2807 # number of UpgradeReq MSHR misses
980,982c966,968
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131168 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 131168 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 128 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131192 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 131192 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 114 # number of demand (read+write) MSHR misses
984,987c970,973
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 22993 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 145423 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 168545 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 128 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 22958 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 145313 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 168386 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 114 # number of overall MSHR misses
989,1027c975,1013
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 22993 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 145423 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 168545 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 8641250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 62500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1382505500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 913321500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2304530750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27979779 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27979779 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7500556317 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7500556317 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8641250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 62500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1382505500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8413877817 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 9805087067 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8641250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 62500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1382505500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8413877817 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 9805087067 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 159586250 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385715000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545301250 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107025000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107025000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 159586250 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9492740000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652326250 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007927 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026087 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010611 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.981285 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.981285 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 22958 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 145313 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 168386 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 8305000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 70000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1550026348 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1005062888 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2563464236 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 49859307 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 49859307 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 136000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 136000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8531883047 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8531883047 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8305000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 70000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1550026348 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9536945935 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 11095347283 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8305000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 70000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1550026348 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9536945935 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 11095347283 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 191729750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5400527000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5592256750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151319000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151319000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 191729750 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9551846000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9743575750 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001627 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007919 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025813 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010564 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982843 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982843 # mshr miss rate for UpgradeReq accesses
1030,1062c1016,1048
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443005 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443005 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007927 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172605 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.044136 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007927 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172605 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.044136 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60127.234376 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64070.256051 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61656.386280 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10068.290392 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10068.290392 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57182.821397 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57182.821397 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60127.234376 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57857.957937 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58174.891376 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60127.234376 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57857.957937 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58174.891376 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443805 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443805 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001627 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007919 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172448 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.044123 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001627 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007919 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172448 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.044123 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72850.877193 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70000 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67515.739524 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71175.050492 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68921.445287 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17762.489134 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17762.489134 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68000 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68000 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65033.561856 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65033.561856 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72850.877193 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67515.739524 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65630.369857 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65892.338336 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72850.877193 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67515.739524 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65630.369857 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65892.338336 # average overall mshr miss latency
1072,1078c1058,1064
< system.cpu.toL2Bus.trans_dist::ReadReq 3581727 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 3581627 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 698310 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2832 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 3579627 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 3579531 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 697919 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2856 # Transaction distribution
1080,1096c1066,1082
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2834 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 296087 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 296087 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5807240 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506645 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14994 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 160889 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 8489768 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185830784 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98804957 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17720 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 284664 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 284938125 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 61311 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 4581044 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5.007958 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.088854 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2858 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 295607 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 295607 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5804583 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506486 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15045 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158423 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 8484537 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185746048 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98788181 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17908 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 280260 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 284832397 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 61029 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 4577967 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3.007970 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.088920 # Request fanout histogram
1101,1104c1087,1088
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 4544586 99.20% 99.20% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 36458 0.80% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 4541479 99.20% 99.20% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 36488 0.80% 100.00% # Request fanout histogram
1106,1109c1090,1093
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 4581044 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 3015323412 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 4577967 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 3013390750 # Layer occupancy (ticks)
1111c1095
< system.cpu.toL2Bus.snoopLayer0.occupancy 202500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 208500 # Layer occupancy (ticks)
1113c1097
< system.cpu.toL2Bus.respLayer0.occupancy 4360848041 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 4358889625 # Layer occupancy (ticks)
1115c1099
< system.cpu.toL2Bus.respLayer1.occupancy 1341145704 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1341438850 # Layer occupancy (ticks)
1117c1101
< system.cpu.toL2Bus.respLayer2.occupancy 10564000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 10568000 # Layer occupancy (ticks)
1119c1103
< system.cpu.toL2Bus.respLayer3.occupancy 89727250 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 88362250 # Layer occupancy (ticks)
1121,1124c1105,1108
< system.iobus.trans_dist::ReadReq 30195 # Transaction distribution
< system.iobus.trans_dist::ReadResp 30195 # Transaction distribution
< system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
< system.iobus.trans_dist::WriteResp 22814 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
> system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
> system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
> system.iobus.trans_dist::WriteResp 22790 # Transaction distribution
1126c1110
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
1147c1131
< system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
1150,1151c1134,1135
< system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
1172c1156
< system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
1175,1176c1159,1160
< system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks)
1216c1200
< system.iobus.reqLayer27.occupancy 347055145 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 198914708 # Layer occupancy (ticks)
1220c1204
< system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
1222c1206
< system.iobus.respLayer3.occupancy 36804505 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 36809505 # Layer occupancy (ticks)
1225c1209
< system.iocache.tags.tagsinuse 1.033413 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.032937 # Cycle average of tags in use
1229,1232c1213,1216
< system.iocache.tags.warmup_cycle 270192614000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 1.033413 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.064588 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.064588 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 270823051000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 1.032937 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.064559 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.064559 # Average percentage of cache occupancy
1246,1253c1230,1237
< system.iocache.ReadReq_miss_latency::realview.ide 27950377 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 27950377 # number of ReadReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9592588263 # number of WriteInvalidateReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::total 9592588263 # number of WriteInvalidateReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 27950377 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 27950377 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 27950377 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 27950377 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 29244877 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 29244877 # number of ReadReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6652334326 # number of WriteInvalidateReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::total 6652334326 # number of WriteInvalidateReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 29244877 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 29244877 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 29244877 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 29244877 # number of overall miss cycles
1270,1278c1254,1262
< system.iocache.ReadReq_avg_miss_latency::realview.ide 119446.055556 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 119446.055556 # average ReadReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264813.059381 # average WriteInvalidateReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::total 264813.059381 # average WriteInvalidateReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 119446.055556 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 119446.055556 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 119446.055556 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 119446.055556 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 55542 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 124978.106838 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 124978.106838 # average ReadReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183644.388417 # average WriteInvalidateReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::total 183644.388417 # average WriteInvalidateReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 124978.106838 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 124978.106838 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 124978.106838 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 124978.106838 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 22952 # number of cycles access was blocked
1280c1264
< system.iocache.blocked::no_mshrs 7161 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3496 # number of cycles access was blocked
1282c1266
< system.iocache.avg_blocked_cycles::no_mshrs 7.756179 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 6.565217 # average number of cycles each access was blocked
1296,1303c1280,1287
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 15781377 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 15781377 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7708930273 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7708930273 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 15781377 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 15781377 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 15781377 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 15781377 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 16937877 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 16937877 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4768676336 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4768676336 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 16937877 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 16937877 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 16937877 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 16937877 # number of overall MSHR miss cycles
1312,1319c1296,1303
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67441.782051 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 67441.782051 # average ReadReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212812.783597 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212812.783597 # average WriteInvalidateReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 67441.782051 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 67441.782051 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 67441.782051 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 67441.782051 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72384.089744 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 72384.089744 # average ReadReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131644.112633 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131644.112633 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 72384.089744 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 72384.089744 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 72384.089744 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 72384.089744 # average overall mshr miss latency
1321,1325c1305,1309
< system.membus.trans_dist::ReadReq 71749 # Transaction distribution
< system.membus.trans_dist::ReadResp 71749 # Transaction distribution
< system.membus.trans_dist::WriteReq 27607 # Transaction distribution
< system.membus.trans_dist::WriteResp 27607 # Transaction distribution
< system.membus.trans_dist::Writeback 124418 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 71726 # Transaction distribution
> system.membus.trans_dist::ReadResp 71726 # Transaction distribution
> system.membus.trans_dist::WriteReq 27583 # Transaction distribution
> system.membus.trans_dist::WriteResp 27583 # Transaction distribution
> system.membus.trans_dist::Writeback 124578 # Transaction distribution
1328c1312
< system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 4604 # Transaction distribution
1330,1333c1314,1317
< system.membus.trans_dist::UpgradeResp 4598 # Transaction distribution
< system.membus.trans_dist::ReadExReq 129351 # Transaction distribution
< system.membus.trans_dist::ReadExResp 129351 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::UpgradeResp 4606 # Transaction distribution
> system.membus.trans_dist::ReadExReq 129395 # Transaction distribution
> system.membus.trans_dist::ReadExResp 129395 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
1336,1337c1320,1321
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446451 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554083 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446695 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554255 # Packet count per connected master and slave (bytes)
1340,1341c1324,1325
< system.membus.pkt_count::total 662970 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 663142 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
1344,1345c1328,1329
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16510296 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16674077 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16522776 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16686485 # Cumulative packet size per connected master and slave (bytes)
1348,1350c1332,1334
< system.membus.pkt_size::total 21309533 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 506 # Total snoops (count)
< system.membus.snoop_fanout::samples 332202 # Request fanout histogram
---
> system.membus.pkt_size::total 21321941 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 504 # Total snoops (count)
> system.membus.snoop_fanout::samples 332271 # Request fanout histogram
1355c1339
< system.membus.snoop_fanout::1 332202 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 332271 100.00% 100.00% # Request fanout histogram
1360,1361c1344,1345
< system.membus.snoop_fanout::total 332202 # Request fanout histogram
< system.membus.reqLayer0.occupancy 87413000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 332271 # Request fanout histogram
> system.membus.reqLayer0.occupancy 90362500 # Layer occupancy (ticks)
1363c1347
< system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
1365c1349
< system.membus.reqLayer2.occupancy 1709000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 1704000 # Layer occupancy (ticks)
1367,1371c1351,1355
< system.membus.reqLayer5.occupancy 1674431500 # Layer occupancy (ticks)
< system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
< system.membus.respLayer2.occupancy 1690391904 # Layer occupancy (ticks)
< system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
< system.membus.respLayer3.occupancy 38335495 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 1022735199 # Layer occupancy (ticks)
> system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
> system.membus.respLayer2.occupancy 997821410 # Layer occupancy (ticks)
> system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
> system.membus.respLayer3.occupancy 37468495 # Layer occupancy (ticks)