3,5c3,5
< sim_seconds 2.852223 # Number of seconds simulated
< sim_ticks 2852222670000 # Number of ticks simulated
< final_tick 2852222670000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.852237 # Number of seconds simulated
> sim_ticks 2852237227000 # Number of ticks simulated
> final_tick 2852237227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 166317 # Simulator instruction rate (inst/s)
< host_op_rate 201081 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 4259610797 # Simulator tick rate (ticks/s)
< host_mem_usage 558772 # Number of bytes of host memory used
< host_seconds 669.60 # Real time elapsed on the host
< sim_insts 111365458 # Number of instructions simulated
< sim_ops 134642914 # Number of ops (including micro ops) simulated
---
> host_inst_rate 157725 # Simulator instruction rate (inst/s)
> host_op_rate 190692 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 4039440180 # Simulator tick rate (ticks/s)
> host_mem_usage 566224 # Number of bytes of host memory used
> host_seconds 706.10 # Real time elapsed on the host
> sim_insts 111368950 # Number of instructions simulated
> sim_ops 134647110 # Number of ops (including micro ops) simulated
15a16,18
> system.physmem.bytes_read::cpu.dtb.walker 6208 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 10897572 # Number of bytes read from this memory
17,24c20,23
< system.physmem.bytes_read::cpu.dtb.walker 6464 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 10896868 # Number of bytes read from this memory
< system.physmem.bytes_read::total 10904484 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1667584 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1667584 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 5681792 # Number of bytes written to this memory
< system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 10904868 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1667392 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1667392 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 5682816 # Number of bytes written to this memory
26c25,29
< system.physmem.bytes_written::total 8017652 # Number of bytes written to this memory
---
> system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
> system.physmem.bytes_written::total 8018676 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.dtb.walker 97 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 170794 # Number of read requests responded to by this memory
28,33c31,32
< system.physmem.num_reads::cpu.dtb.walker 101 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 170783 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 170902 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 88778 # Number of write requests responded to by this memory
< system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 170908 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 88794 # Number of write requests responded to by this memory
35c34,38
< system.physmem.num_writes::total 129383 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 129399 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 2177 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 3820710 # Total read bandwidth from this memory (bytes/s)
37,44c40,43
< system.physmem.bw_read::cpu.dtb.walker 2266 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 67 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 3820483 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 3823153 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 584661 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 584661 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1992058 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::realview.ide 812817 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 3823268 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 584591 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 584591 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1992407 # Write bandwidth from this memory (bytes/s)
46,62c45,62
< system.physmem.bw_write::total 2811019 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1992058 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 813154 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 2266 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 67 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 3826627 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 6634172 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 170902 # Number of read requests accepted
< system.physmem.writeReqs 129383 # Number of write requests accepted
< system.physmem.readBursts 170902 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 129383 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 10927488 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 10240 # Total number of bytes read from write queue
< system.physmem.bytesWritten 8031232 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 10904484 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 8017652 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 160 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_write::realview.ide 812813 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 2811364 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1992407 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 2177 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 3826854 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 813150 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 6634632 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 170908 # Number of read requests accepted
> system.physmem.writeReqs 129399 # Number of write requests accepted
> system.physmem.readBursts 170908 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 129399 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 10927552 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 10560 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8032256 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 10904868 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 8018676 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 165 # Number of DRAM read bursts serviced by the write queue
64,80c64,80
< system.physmem.neitherReadNorWriteReqs 4593 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 10513 # Per bank write bursts
< system.physmem.perBankRdBursts::1 10240 # Per bank write bursts
< system.physmem.perBankRdBursts::2 10772 # Per bank write bursts
< system.physmem.perBankRdBursts::3 10550 # Per bank write bursts
< system.physmem.perBankRdBursts::4 13501 # Per bank write bursts
< system.physmem.perBankRdBursts::5 10124 # Per bank write bursts
< system.physmem.perBankRdBursts::6 11177 # Per bank write bursts
< system.physmem.perBankRdBursts::7 10891 # Per bank write bursts
< system.physmem.perBankRdBursts::8 10227 # Per bank write bursts
< system.physmem.perBankRdBursts::9 10892 # Per bank write bursts
< system.physmem.perBankRdBursts::10 10093 # Per bank write bursts
< system.physmem.perBankRdBursts::11 9609 # Per bank write bursts
< system.physmem.perBankRdBursts::12 10331 # Per bank write bursts
< system.physmem.perBankRdBursts::13 11217 # Per bank write bursts
< system.physmem.perBankRdBursts::14 10288 # Per bank write bursts
< system.physmem.perBankRdBursts::15 10317 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 4597 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 10514 # Per bank write bursts
> system.physmem.perBankRdBursts::1 10246 # Per bank write bursts
> system.physmem.perBankRdBursts::2 10769 # Per bank write bursts
> system.physmem.perBankRdBursts::3 10552 # Per bank write bursts
> system.physmem.perBankRdBursts::4 13499 # Per bank write bursts
> system.physmem.perBankRdBursts::5 10126 # Per bank write bursts
> system.physmem.perBankRdBursts::6 11178 # Per bank write bursts
> system.physmem.perBankRdBursts::7 10889 # Per bank write bursts
> system.physmem.perBankRdBursts::8 10228 # Per bank write bursts
> system.physmem.perBankRdBursts::9 10887 # Per bank write bursts
> system.physmem.perBankRdBursts::10 10100 # Per bank write bursts
> system.physmem.perBankRdBursts::11 9610 # Per bank write bursts
> system.physmem.perBankRdBursts::12 10315 # Per bank write bursts
> system.physmem.perBankRdBursts::13 11222 # Per bank write bursts
> system.physmem.perBankRdBursts::14 10292 # Per bank write bursts
> system.physmem.perBankRdBursts::15 10316 # Per bank write bursts
82,85c82,85
< system.physmem.perBankWrBursts::1 7662 # Per bank write bursts
< system.physmem.perBankWrBursts::2 8408 # Per bank write bursts
< system.physmem.perBankWrBursts::3 8127 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7860 # Per bank write bursts
---
> system.physmem.perBankWrBursts::1 7667 # Per bank write bursts
> system.physmem.perBankWrBursts::2 8410 # Per bank write bursts
> system.physmem.perBankWrBursts::3 8128 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7856 # Per bank write bursts
87,91c87,91
< system.physmem.perBankWrBursts::6 8206 # Per bank write bursts
< system.physmem.perBankWrBursts::7 8039 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7784 # Per bank write bursts
< system.physmem.perBankWrBursts::9 8077 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7518 # Per bank write bursts
---
> system.physmem.perBankWrBursts::6 8209 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8042 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7786 # Per bank write bursts
> system.physmem.perBankWrBursts::9 8073 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7525 # Per bank write bursts
93,95c93,95
< system.physmem.perBankWrBursts::12 7767 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8402 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7544 # Per bank write bursts
---
> system.physmem.perBankWrBursts::12 7760 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8405 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7549 # Per bank write bursts
98,99c98,99
< system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
< system.physmem.totGap 2852222186000 # Total gap between requests
---
> system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
> system.physmem.totGap 2852236741500 # Total gap between requests
106c106
< system.physmem.readPktSize::6 170347 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 170353 # Read request sizes (log2)
113,115c113,115
< system.physmem.writePktSize::6 125002 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 164585 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 6110 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 125018 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 164527 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 6169 # What read queue length does an incoming req see
161,174c161,174
< system.physmem.wrQLenPdf::15 1982 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2519 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 6120 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 6597 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6634 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 7213 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7428 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 7985 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8522 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 9334 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 8728 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8242 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7692 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 7486 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 1957 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2508 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 6099 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6612 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6647 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 7189 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7393 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 7933 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 8489 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 9295 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 8700 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 8234 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7658 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7495 # What write queue length does an incoming req see
176,199c176,199
< system.physmem.wrQLenPdf::30 6557 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6577 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6482 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 199 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 169 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 170 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 123 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 118 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 118 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 128 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 116 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 126 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 132 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 123 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 114 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 104 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 47 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::30 6543 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6568 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6500 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 212 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 209 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 203 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 177 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 179 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 174 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 155 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 154 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 113 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 114 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 125 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 109 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 102 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 79 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 51 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 42 # What write queue length does an incoming req see
201,227c201,227
< system.physmem.wrQLenPdf::55 33 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 11 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 60830 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 311.666217 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 184.364711 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 329.290387 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 22259 36.59% 36.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14417 23.70% 60.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6771 11.13% 71.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3560 5.85% 77.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2627 4.32% 81.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1563 2.57% 84.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1081 1.78% 85.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1081 1.78% 87.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7471 12.28% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 60830 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6311 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 27.051339 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 576.967682 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6309 99.97% 99.97% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::55 30 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 35 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 34 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 60829 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 311.689227 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 184.313026 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 329.369125 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 22276 36.62% 36.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 14416 23.70% 60.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6737 11.08% 71.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3572 5.87% 77.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2597 4.27% 81.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1607 2.64% 84.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1084 1.78% 85.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1076 1.77% 87.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7464 12.27% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 60829 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6321 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 27.008859 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 576.510415 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6319 99.97% 99.97% # Reads before turning the bus around for writes
230,269c230,267
< system.physmem.rdPerTurnAround::total 6311 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6311 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 19.884012 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.375867 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 11.802704 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5533 87.67% 87.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 35 0.55% 88.23% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 30 0.48% 88.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 215 3.41% 92.11% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 199 3.15% 95.26% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 15 0.24% 95.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 17 0.27% 95.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 19 0.30% 96.07% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 19 0.30% 96.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 6 0.10% 96.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 3 0.05% 96.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 4 0.06% 96.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 155 2.46% 99.03% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 5 0.08% 99.11% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 6 0.10% 99.21% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 3 0.05% 99.26% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 12 0.19% 99.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 2 0.03% 99.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 1 0.02% 99.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 7 0.11% 99.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 1 0.02% 99.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 3 0.05% 99.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 1 0.02% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 5 0.08% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 2 0.03% 99.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 1 0.02% 99.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 6 0.10% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 1 0.02% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 3 0.05% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6311 # Writes before turning the bus around for reads
< system.physmem.totQLat 1715938250 # Total ticks spent queuing
< system.physmem.totMemAccLat 4917350750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 853710000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 10049.89 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 6321 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6321 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 19.855086 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.377929 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 11.560499 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5522 87.36% 87.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 41 0.65% 88.01% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 34 0.54% 88.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 217 3.43% 91.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 214 3.39% 95.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 10 0.16% 95.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 16 0.25% 95.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 20 0.32% 96.09% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 24 0.38% 96.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 4 0.06% 96.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 2 0.03% 96.57% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 2 0.03% 96.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 162 2.56% 99.16% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 4 0.06% 99.22% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 5 0.08% 99.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 3 0.05% 99.35% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 12 0.19% 99.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 1 0.02% 99.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 1 0.02% 99.57% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 7 0.11% 99.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 2 0.03% 99.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 1 0.02% 99.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 5 0.08% 99.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 2 0.03% 99.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 1 0.02% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 7 0.11% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6321 # Writes before turning the bus around for reads
> system.physmem.totQLat 1722371500 # Total ticks spent queuing
> system.physmem.totMemAccLat 4923802750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 853715000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 10087.51 # Average queueing delay per DRAM burst
271c269
< system.physmem.avgMemAccLat 28799.89 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 28837.51 # Average memory access latency per DRAM burst
281,283c279,281
< system.physmem.avgWrQLen 23.21 # Average write queue length when enqueuing
< system.physmem.readRowHits 140944 # Number of row buffer hits during reads
< system.physmem.writeRowHits 94455 # Number of row buffer hits during writes
---
> system.physmem.avgWrQLen 26.39 # Average write queue length when enqueuing
> system.physmem.readRowHits 140948 # Number of row buffer hits during reads
> system.physmem.writeRowHits 94469 # Number of row buffer hits during writes
285,286c283,284
< system.physmem.writeRowHitRate 75.25 # Row buffer hit rate for writes
< system.physmem.avgGap 9498383.82 # Average gap between requests
---
> system.physmem.writeRowHitRate 75.26 # Row buffer hit rate for writes
> system.physmem.avgGap 9497736.45 # Average gap between requests
288,289c286,287
< system.physmem.memoryStateTime::IDLE 2712510439500 # Time in different power states
< system.physmem.memoryStateTime::REF 95241900000 # Time in different power states
---
> system.physmem.memoryStateTime::IDLE 2712717626000 # Time in different power states
> system.physmem.memoryStateTime::REF 95242420000 # Time in different power states
291c289
< system.physmem.memoryStateTime::ACT 44470242000 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 44277091000 # Time in different power states
293,310c291,308
< system.physmem.actEnergy::0 234798480 # Energy for activate commands per rank (pJ)
< system.physmem.actEnergy::1 225076320 # Energy for activate commands per rank (pJ)
< system.physmem.preEnergy::0 128114250 # Energy for precharge commands per rank (pJ)
< system.physmem.preEnergy::1 122809500 # Energy for precharge commands per rank (pJ)
< system.physmem.readEnergy::0 684590400 # Energy for read commands per rank (pJ)
< system.physmem.readEnergy::1 647189400 # Energy for read commands per rank (pJ)
< system.physmem.writeEnergy::0 410650560 # Energy for write commands per rank (pJ)
< system.physmem.writeEnergy::1 402511680 # Energy for write commands per rank (pJ)
< system.physmem.refreshEnergy::0 186293156400 # Energy for refresh commands per rank (pJ)
< system.physmem.refreshEnergy::1 186293156400 # Energy for refresh commands per rank (pJ)
< system.physmem.actBackEnergy::0 83147145165 # Energy for active background per rank (pJ)
< system.physmem.actBackEnergy::1 82654300080 # Energy for active background per rank (pJ)
< system.physmem.preBackEnergy::0 1638396165000 # Energy for precharge background per rank (pJ)
< system.physmem.preBackEnergy::1 1638828485250 # Energy for precharge background per rank (pJ)
< system.physmem.totalEnergy::0 1909294620255 # Total energy per rank (pJ)
< system.physmem.totalEnergy::1 1909173528630 # Total energy per rank (pJ)
< system.physmem.averagePower::0 669.406404 # Core power per rank (mW)
< system.physmem.averagePower::1 669.363949 # Core power per rank (mW)
---
> system.physmem.actEnergy::0 234707760 # Energy for activate commands per rank (pJ)
> system.physmem.actEnergy::1 225159480 # Energy for activate commands per rank (pJ)
> system.physmem.preEnergy::0 128064750 # Energy for precharge commands per rank (pJ)
> system.physmem.preEnergy::1 122854875 # Energy for precharge commands per rank (pJ)
> system.physmem.readEnergy::0 684629400 # Energy for read commands per rank (pJ)
> system.physmem.readEnergy::1 647158200 # Energy for read commands per rank (pJ)
> system.physmem.writeEnergy::0 410715360 # Energy for write commands per rank (pJ)
> system.physmem.writeEnergy::1 402550560 # Energy for write commands per rank (pJ)
> system.physmem.refreshEnergy::0 186294173520 # Energy for refresh commands per rank (pJ)
> system.physmem.refreshEnergy::1 186294173520 # Energy for refresh commands per rank (pJ)
> system.physmem.actBackEnergy::0 83068916085 # Energy for active background per rank (pJ)
> system.physmem.actBackEnergy::1 82611072135 # Energy for active background per rank (pJ)
> system.physmem.preBackEnergy::0 1638474130500 # Energy for precharge background per rank (pJ)
> system.physmem.preBackEnergy::1 1638875748000 # Energy for precharge background per rank (pJ)
> system.physmem.totalEnergy::0 1909295337375 # Total energy per rank (pJ)
> system.physmem.totalEnergy::1 1909178716770 # Total energy per rank (pJ)
> system.physmem.averagePower::0 669.403001 # Core power per rank (mW)
> system.physmem.averagePower::1 669.362113 # Core power per rank (mW)
323,405d320
< system.membus.trans_dist::ReadReq 71842 # Transaction distribution
< system.membus.trans_dist::ReadResp 71842 # Transaction distribution
< system.membus.trans_dist::WriteReq 27607 # Transaction distribution
< system.membus.trans_dist::WriteResp 27607 # Transaction distribution
< system.membus.trans_dist::Writeback 88778 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 4591 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 4593 # Transaction distribution
< system.membus.trans_dist::ReadExReq 129869 # Transaction distribution
< system.membus.trans_dist::ReadExResp 129869 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 448500 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 556132 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 628829 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16602840 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16766621 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 19085917 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 219 # Total snoops (count)
< system.membus.snoop_fanout::samples 297178 # Request fanout histogram
< system.membus.snoop_fanout::mean 1 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::1 297178 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 1 # Request fanout histogram
< system.membus.snoop_fanout::max_value 1 # Request fanout histogram
< system.membus.snoop_fanout::total 297178 # Request fanout histogram
< system.membus.reqLayer0.occupancy 87065000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
< system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
< system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
< system.membus.reqLayer2.occupancy 1712000 # Layer occupancy (ticks)
< system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
< system.membus.reqLayer5.occupancy 1386132250 # Layer occupancy (ticks)
< system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
< system.membus.respLayer2.occupancy 1718569157 # Layer occupancy (ticks)
< system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
< system.membus.respLayer3.occupancy 38335749 # Layer occupancy (ticks)
< system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
< system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
< system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
< system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
< system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
< system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
< system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
< system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
< system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
< system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
< system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
< system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
< system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
< system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
< system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
< system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
< system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
< system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
< system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
< system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
< system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
< system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
< system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
< system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
< system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
< system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
< system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
< system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
< system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
< system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
< system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
< system.realview.ethernet.droppedPackets 0 # number of packets dropped
412,519c327,331
< system.iobus.trans_dist::ReadReq 30195 # Transaction distribution
< system.iobus.trans_dist::ReadResp 30195 # Transaction distribution
< system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
< system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
< system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
< system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
< system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
< system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
< system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
< system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
< system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
< system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
< system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
< system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
< system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
< system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
< system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer27.occupancy 326584849 # Layer occupancy (ticks)
< system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
< system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
< system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
< system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
< system.iobus.respLayer3.occupancy 36809251 # Layer occupancy (ticks)
< system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
< system.cpu_clk_domain.clock 500 # Clock period in ticks
< system.cpu.branchPred.lookups 30769128 # Number of BP lookups
< system.cpu.branchPred.condPredicted 16730733 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 2480939 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 18423796 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 13205412 # Number of BTB hits
---
> system.cpu.branchPred.lookups 30773662 # Number of BP lookups
> system.cpu.branchPred.condPredicted 16735793 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 2481146 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 18414792 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 13204104 # Number of BTB hits
521,523c333,336
< system.cpu.branchPred.BTBHitPct 71.675848 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 7765211 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 1476374 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 71.703791 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 7765871 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 1476448 # Number of incorrect RAS predictions.
> system.cpu_clk_domain.clock 500 # Clock period in ticks
547,550c360,363
< system.cpu.dtb.read_hits 24572928 # DTB read hits
< system.cpu.dtb.read_misses 58429 # DTB read misses
< system.cpu.dtb.write_hits 19368405 # DTB write hits
< system.cpu.dtb.write_misses 5913 # DTB write misses
---
> system.cpu.dtb.read_hits 24574985 # DTB read hits
> system.cpu.dtb.read_misses 58557 # DTB read misses
> system.cpu.dtb.write_hits 19368965 # DTB write hits
> system.cpu.dtb.write_misses 5915 # DTB write misses
555,557c368,370
< system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB
< system.cpu.dtb.align_faults 1245 # Number of TLB faults due to alignment restrictions
< system.cpu.dtb.prefetch_faults 1816 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.flush_entries 4353 # Number of entries that have been flushed from TLB
> system.cpu.dtb.align_faults 1231 # Number of TLB faults due to alignment restrictions
> system.cpu.dtb.prefetch_faults 1821 # Number of TLB faults due to prefetch
559,561c372,374
< system.cpu.dtb.perms_faults 752 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 24631357 # DTB read accesses
< system.cpu.dtb.write_accesses 19374318 # DTB write accesses
---
> system.cpu.dtb.perms_faults 755 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 24633542 # DTB read accesses
> system.cpu.dtb.write_accesses 19374880 # DTB write accesses
563,565c376,378
< system.cpu.dtb.hits 43941333 # DTB hits
< system.cpu.dtb.misses 64342 # DTB misses
< system.cpu.dtb.accesses 44005675 # DTB accesses
---
> system.cpu.dtb.hits 43943950 # DTB hits
> system.cpu.dtb.misses 64472 # DTB misses
> system.cpu.dtb.accesses 44008422 # DTB accesses
587,588c400,401
< system.cpu.itb.inst_hits 57038768 # ITB inst hits
< system.cpu.itb.inst_misses 5411 # ITB inst misses
---
> system.cpu.itb.inst_hits 57039019 # ITB inst hits
> system.cpu.itb.inst_misses 5418 # ITB inst misses
597c410
< system.cpu.itb.flush_entries 2977 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_entries 2981 # Number of entries that have been flushed from TLB
601c414
< system.cpu.itb.perms_faults 8664 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 8633 # Number of TLB faults due to permissions restrictions
604,608c417,421
< system.cpu.itb.inst_accesses 57044179 # ITB inst accesses
< system.cpu.itb.hits 57038768 # DTB hits
< system.cpu.itb.misses 5411 # DTB misses
< system.cpu.itb.accesses 57044179 # DTB accesses
< system.cpu.numCycles 313347638 # number of cpu cycles simulated
---
> system.cpu.itb.inst_accesses 57044437 # ITB inst accesses
> system.cpu.itb.hits 57039019 # DTB hits
> system.cpu.itb.misses 5418 # DTB misses
> system.cpu.itb.accesses 57044437 # DTB accesses
> system.cpu.numCycles 313379229 # number of cpu cycles simulated
611,613c424,426
< system.cpu.committedInsts 111365458 # Number of instructions committed
< system.cpu.committedOps 134642914 # Number of ops (including micro ops) committed
< system.cpu.discardedOps 7897593 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.committedInsts 111368950 # Number of instructions committed
> system.cpu.committedOps 134647110 # Number of ops (including micro ops) committed
> system.cpu.discardedOps 7900477 # Number of ops (including micro ops) which were discarded before commit
615,617c428,430
< system.cpu.quiesceCycles 5391144295 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.cpi 2.813688 # CPI: cycles per instruction
< system.cpu.ipc 0.355405 # IPC: instructions per cycle
---
> system.cpu.quiesceCycles 5391141904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.cpi 2.813883 # CPI: cycles per instruction
> system.cpu.ipc 0.355381 # IPC: instructions per cycle
620,626c433,606
< system.cpu.tickCycles 224151816 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 89195822 # Total number of cycles that the object has spent stopped
< system.cpu.icache.tags.replacements 2897350 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.427915 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 54131849 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 2897862 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 18.679926 # Average number of references to valid blocks.
---
> system.cpu.tickCycles 224160135 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 89219094 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 841413 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.953450 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 42452187 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 841925 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 50.422766 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 279721250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.inst 511.953450 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 357 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 175172385 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 175172385 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.inst 23318882 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23318882 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.inst 18212211 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 18212211 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.inst 457846 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 457846 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.inst 460333 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 460333 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.inst 41531093 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 41531093 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.inst 41531093 # number of overall hits
> system.cpu.dcache.overall_hits::total 41531093 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.inst 583694 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 583694 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.inst 541327 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 541327 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.inst 8314 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 8314 # number of LoadLockedReq misses
> system.cpu.dcache.StoreCondReq_misses::cpu.inst 2 # number of StoreCondReq misses
> system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
> system.cpu.dcache.demand_misses::cpu.inst 1125021 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1125021 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.inst 1125021 # number of overall misses
> system.cpu.dcache.overall_misses::total 1125021 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 8654598086 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 8654598086 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21588798306 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 21588798306 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 117927750 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 117927750 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 52502 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 52502 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 30243396392 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 30243396392 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 30243396392 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 30243396392 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.inst 23902576 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23902576 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.inst 18753538 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 18753538 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 466160 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 466160 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.inst 460335 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 460335 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.inst 42656114 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42656114 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.inst 42656114 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 42656114 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.024420 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.024420 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.028865 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.028865 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.017835 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017835 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000004 # miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.inst 0.026374 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.026374 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.inst 0.026374 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.026374 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14827.286362 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14827.286362 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39881.251639 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 39881.251639 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14184.237431 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14184.237431 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 26251 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26251 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26882.517208 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 26882.517208 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26882.517208 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 26882.517208 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 697938 # number of writebacks
> system.cpu.dcache.writebacks::total 697938 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 45858 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 45858 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 242707 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 242707 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.inst 288565 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 288565 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.inst 288565 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 288565 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 537836 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 537836 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 298620 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 298620 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 8314 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 8314 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 2 # number of StoreCondReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.inst 836456 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 836456 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.inst 836456 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 836456 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6884995145 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6884995145 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 11268709155 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 11268709155 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 101270250 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 101270250 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 48498 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48498 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 18153704300 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 18153704300 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 18153704300 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 18153704300 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5790985000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790985000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 4439182000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439182000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 10230167000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230167000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.022501 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022501 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015923 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015923 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.017835 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017835 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.019609 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.019609 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019609 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.019609 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12801.290998 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12801.290998 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37735.949216 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37735.949216 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12180.689199 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12180.689199 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 24249 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24249 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21703.119232 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 21703.119232 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21703.119232 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 21703.119232 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
> system.cpu.icache.tags.replacements 2897611 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.427780 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 54131846 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 2898123 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 18.678243 # Average number of references to valid blocks.
628,630c608,610
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.427915 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.998883 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.998883 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.427780 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.998882 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.998882 # Average percentage of cache occupancy
632,634c612,614
< system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 200 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id
636,673c616,653
< system.cpu.icache.tags.tag_accesses 59927594 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 59927594 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 54131849 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 54131849 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 54131849 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 54131849 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 54131849 # number of overall hits
< system.cpu.icache.overall_hits::total 54131849 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 2897873 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 2897873 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 2897873 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 2897873 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 2897873 # number of overall misses
< system.cpu.icache.overall_misses::total 2897873 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 39140139756 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 39140139756 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 39140139756 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 39140139756 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 39140139756 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 39140139756 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 57029722 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 57029722 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 57029722 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 57029722 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 57029722 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 57029722 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050813 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.050813 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.050813 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.050813 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.050813 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.050813 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.506240 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13506.506240 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.506240 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13506.506240 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.506240 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13506.506240 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 59928115 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 59928115 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 54131846 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 54131846 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 54131846 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 54131846 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 54131846 # number of overall hits
> system.cpu.icache.overall_hits::total 54131846 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 2898135 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 2898135 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 2898135 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 2898135 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 2898135 # number of overall misses
> system.cpu.icache.overall_misses::total 2898135 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 39145708027 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 39145708027 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 39145708027 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 39145708027 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 39145708027 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 39145708027 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 57029981 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 57029981 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 57029981 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 57029981 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 57029981 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 57029981 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050818 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.050818 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.050818 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.050818 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.050818 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.050818 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13507.206540 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13507.206540 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13507.206540 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13507.206540 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13507.206540 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13507.206540 # average overall miss latency
682,693c662,673
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897873 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 2897873 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 2897873 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 2897873 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 2897873 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 2897873 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33334905244 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 33334905244 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33334905244 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 33334905244 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33334905244 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 33334905244 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2898135 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 2898135 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 2898135 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 2898135 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 2898135 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 2898135 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33339952973 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 33339952973 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33339952973 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 33339952973 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33339952973 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 33339952973 # number of overall MSHR miss cycles
698,709c678,689
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050813 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050813 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050813 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.050813 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050813 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.050813 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11503.231937 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11503.231937 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11503.231937 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11503.231937 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11503.231937 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11503.231937 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050818 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050818 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050818 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.050818 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050818 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.050818 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11503.933727 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11503.933727 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11503.933727 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11503.933727 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11503.933727 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11503.933727 # average overall mshr miss latency
715,768c695,699
< system.cpu.toL2Bus.trans_dist::ReadReq 3575187 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 3575091 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 697424 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36234 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2818 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2820 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 295755 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 295755 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5801712 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2503299 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15293 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 155961 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 8476265 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185653696 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98670557 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 19168 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 276272 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 284619693 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 60174 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 4573282 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5.007974 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.088941 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 4536814 99.20% 99.20% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 36468 0.80% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 4573282 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 3010555155 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
< system.cpu.toL2Bus.snoopLayer0.occupancy 208500 # Layer occupancy (ticks)
< system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer0.occupancy 4356749506 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 1339516197 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer2.occupancy 10501000 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer3.occupancy 86895250 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
< system.cpu.l2cache.tags.replacements 97514 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65073.344541 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4041263 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 162774 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 24.827448 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 97521 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65074.207270 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4042767 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 162784 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 24.835162 # Average number of references to valid blocks.
770,775c701,706
< system.cpu.l2cache.tags.occ_blocks::writebacks 47542.577135 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 54.389093 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.009502 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 17476.368811 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.725442 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000830 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 47538.276045 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 53.278527 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000399 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 17482.652299 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.725377 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000813 # Average percentage of cache occupancy
777,782c708,713
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.266668 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.992940 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 44 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65216 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 44 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.266764 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.992954 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 40 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65223 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 40 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
784,796c715,727
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2322 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6967 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55801 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995117 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 36568997 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 36568997 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68967 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4789 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 3405854 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 3479610 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 697424 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 697424 # number of Writeback hits
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2327 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6958 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55810 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995224 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 36581031 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 36581031 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69052 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4779 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 3406716 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 3480547 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 697938 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 697938 # number of Writeback hits
799,814c730,745
< system.cpu.l2cache.ReadExReq_hits::cpu.inst 164068 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 164068 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 68967 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 4789 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 3569922 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 3643678 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 68967 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 4789 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 3569922 # number of overall hits
< system.cpu.l2cache.overall_hits::total 3643678 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 101 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.inst 37534 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 37638 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2773 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 2773 # number of UpgradeReq misses
---
> system.cpu.l2cache.ReadExReq_hits::cpu.inst 164104 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 164104 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 69052 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 4779 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 3570820 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 3644651 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 69052 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 4779 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 3570820 # number of overall hits
> system.cpu.l2cache.overall_hits::total 3644651 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 97 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.inst 37533 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 37632 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2776 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 2776 # number of UpgradeReq misses
817,852c748,783
< system.cpu.l2cache.ReadExReq_misses::cpu.inst 131687 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 131687 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 101 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.inst 169221 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 169325 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 101 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.inst 169221 # number of overall misses
< system.cpu.l2cache.overall_misses::total 169325 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 7803500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 223500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2773793750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 2781820750 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 1024956 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 1024956 # number of UpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst 46998 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9263576682 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 9263576682 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 7803500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 223500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 12037370432 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 12045397432 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 7803500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 223500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 12037370432 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 12045397432 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69068 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4792 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 3443388 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 3517248 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 697424 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 697424 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2818 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2818 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_misses::cpu.inst 131700 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 131700 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 97 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 169233 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 169332 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 97 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 169233 # number of overall misses
> system.cpu.l2cache.overall_misses::total 169332 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 7518750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2779279750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 2786947500 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 1021956 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 1021956 # number of UpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst 46498 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46498 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9264906431 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 9264906431 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 7518750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 12044186181 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 12051853931 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 7518750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 12044186181 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 12051853931 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69149 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4781 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 3444249 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 3518179 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 697938 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 697938 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2821 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2821 # number of UpgradeReq accesses(hits+misses)
855,870c786,801
< system.cpu.l2cache.ReadExReq_accesses::cpu.inst 295755 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 295755 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69068 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 4792 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 3739143 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 3813003 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69068 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 4792 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 3739143 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 3813003 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001462 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000626 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010900 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.010701 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.984031 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984031 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.inst 295804 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 295804 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69149 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 4781 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 3740053 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 3813983 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69149 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 4781 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 3740053 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 3813983 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001403 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000418 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010897 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.010696 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.984048 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984048 # miss rate for UpgradeReq accesses
873,883c804,814
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.445257 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.445257 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001462 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000626 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.045257 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.044407 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001462 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000626 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.045257 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.044407 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77262.376238 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.445227 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.445227 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001403 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000418 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.045249 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.044398 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001403 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000418 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.045249 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.044398 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77512.886598 # average ReadReq miss latency
885,893c816,824
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73900.829914 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 73909.898241 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 369.619906 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 369.619906 # average UpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst 23499 # average SCUpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23499 # average SCUpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70345.415128 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70345.415128 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77262.376238 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74048.963579 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 74057.916135 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 368.139769 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 368.139769 # average UpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst 23249 # average SCUpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23249 # average SCUpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70348.568193 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70348.568193 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77512.886598 # average overall miss latency
895,897c826,828
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71134.022562 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 71137.737676 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77262.376238 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71169.252929 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 71172.926151 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77512.886598 # average overall miss latency
899,900c830,831
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71134.022562 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 71137.737676 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71169.252929 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 71172.926151 # average overall miss latency
909,910c840,841
< system.cpu.l2cache.writebacks::writebacks 88778 # number of writebacks
< system.cpu.l2cache.writebacks::total 88778 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 88794 # number of writebacks
> system.cpu.l2cache.writebacks::total 88794 # number of writebacks
917,922c848,853
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 101 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 37366 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 37470 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2773 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 2773 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 97 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 37365 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 37464 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2776 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 2776 # number of UpgradeReq MSHR misses
925,940c856,871
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 131687 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 131687 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 101 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 169053 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 169157 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 101 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 169053 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 169157 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 6559500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 187500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2294945750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2301692750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 27763773 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27763773 # number of UpgradeReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 131700 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 131700 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 97 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 169065 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 169164 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 97 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 169065 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 169164 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 6323250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2300603500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2307051750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 27795276 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27795276 # number of UpgradeReq MSHR miss cycles
943,964c874,895
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7581141318 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7581141318 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 6559500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 187500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9876087068 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 9882834068 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 6559500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 187500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9876087068 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 9882834068 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5545310750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545310750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 4106655500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4106655500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 9651966250 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9651966250 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001462 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000626 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010852 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010653 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.984031 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984031 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7582295069 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7582295069 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 6323250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9882898569 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 9889346819 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 6323250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9882898569 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 9889346819 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5545290750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545290750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 4106643000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4106643000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 9651933750 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9651933750 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001403 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000418 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010849 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010649 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.984048 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984048 # mshr miss rate for UpgradeReq accesses
967,977c898,908
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.445257 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.445257 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001462 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000626 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.045212 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.044363 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001462 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000626 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.045212 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.044363 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64945.544554 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.445227 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.445227 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001403 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000418 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.045204 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.044354 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001403 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000418 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.045204 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.044354 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65188.144330 # average ReadReq mshr miss latency
979,982c910,913
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61418.020393 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61427.615426 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10012.179228 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10012.179228 # average UpgradeReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61571.082564 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61580.497277 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10012.707493 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10012.707493 # average UpgradeReq mshr miss latency
985,987c916,918
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57569.398027 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57569.398027 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64945.544554 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57572.475847 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57572.475847 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65188.144330 # average overall mshr miss latency
989,991c920,922
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58420.063933 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58424.032514 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64945.544554 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58456.206601 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58460.114557 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65188.144330 # average overall mshr miss latency
993,994c924,925
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58420.063933 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58424.032514 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58456.206601 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58460.114557 # average overall mshr miss latency
1002,1168c933,1083
< system.cpu.dcache.tags.replacements 840767 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.953448 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 42450068 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 841279 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 50.458965 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 279721250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.inst 511.953448 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 358 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 175160699 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 175160699 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.inst 23317429 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23317429 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.inst 18211581 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 18211581 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.inst 457826 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 457826 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.inst 460320 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 460320 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.inst 41529010 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 41529010 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.inst 41529010 # number of overall hits
< system.cpu.dcache.overall_hits::total 41529010 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.inst 583115 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 583115 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.inst 541259 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 541259 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.inst 8317 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 8317 # number of LoadLockedReq misses
< system.cpu.dcache.StoreCondReq_misses::cpu.inst 2 # number of StoreCondReq misses
< system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
< system.cpu.dcache.demand_misses::cpu.inst 1124374 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1124374 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.inst 1124374 # number of overall misses
< system.cpu.dcache.overall_misses::total 1124374 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 8642422585 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 8642422585 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21588022799 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 21588022799 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 117987000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 117987000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 53002 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 30230445384 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 30230445384 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 30230445384 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 30230445384 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.inst 23900544 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23900544 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.inst 18752840 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 18752840 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 466143 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 466143 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.inst 460322 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 460322 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.inst 42653384 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42653384 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.inst 42653384 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 42653384 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.024398 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.024398 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.028863 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.028863 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.017842 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017842 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000004 # miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.inst 0.026361 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.026361 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.inst 0.026361 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.026361 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14821.128911 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14821.128911 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39884.829257 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 39884.829257 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14186.245040 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14186.245040 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 26501 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26886.467834 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 26886.467834 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26886.467834 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 26886.467834 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 697424 # number of writebacks
< system.cpu.dcache.writebacks::total 697424 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 45879 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 45879 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 242691 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 242691 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.inst 288570 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 288570 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.inst 288570 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 288570 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 537236 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 537236 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 298568 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 298568 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 8317 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 8317 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 2 # number of StoreCondReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.inst 835804 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 835804 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.inst 835804 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 835804 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6874982646 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6874982646 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 11266915159 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11266915159 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 101324000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 101324000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 48998 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 18141897805 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 18141897805 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 18141897805 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 18141897805 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5791016000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791016000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 4439188000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439188000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 10230204000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230204000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.022478 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022478 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015921 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015921 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.017842 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017842 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.019595 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.019595 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019595 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.019595 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12796.950774 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12796.950774 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37736.512818 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37736.512818 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12182.758206 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12182.758206 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 24499 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21705.923644 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 21705.923644 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21705.923644 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 21705.923644 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.toL2Bus.trans_dist::ReadReq 3576313 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 3576217 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 697938 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2821 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2823 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 295804 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 295804 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5802238 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2505111 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15298 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 156293 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 8478940 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185670592 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98744797 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 19124 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 276596 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 284711109 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 60360 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 4574965 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5.007969 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.088914 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 4538506 99.20% 99.20% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 36459 0.80% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 4574965 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 3011909666 # Layer occupancy (ticks)
> system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
> system.cpu.toL2Bus.snoopLayer0.occupancy 208500 # Layer occupancy (ticks)
> system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer0.occupancy 4357140777 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer1.occupancy 1340495452 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer2.occupancy 10517000 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer3.occupancy 87146500 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
> system.iobus.trans_dist::ReadReq 30195 # Transaction distribution
> system.iobus.trans_dist::ReadResp 30195 # Transaction distribution
> system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
> system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
> system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
> system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
> system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
> system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
> system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
> system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
> system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
> system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
> system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
> system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
> system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
> system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
> system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks)
> system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
> system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
> system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
> system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
> system.iobus.respLayer3.occupancy 36804753 # Layer occupancy (ticks)
> system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1170c1085
< system.iocache.tags.tagsinuse 1.031475 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.031563 # Cycle average of tags in use
1175,1177c1090,1092
< system.iocache.tags.occ_blocks::realview.ide 1.031475 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.064467 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.064467 # Average percentage of cache occupancy
---
> system.iocache.tags.occ_blocks::realview.ide 1.031563 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.064473 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.064473 # Average percentage of cache occupancy
1191,1196c1106,1111
< system.iocache.ReadReq_miss_latency::realview.ide 27954377 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 27954377 # number of ReadReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 27954377 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 27954377 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 27954377 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 27954377 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 27956377 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 27956377 # number of ReadReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 27956377 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 27956377 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 27956377 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 27956377 # number of overall miss cycles
1211,1216c1126,1131
< system.iocache.ReadReq_avg_miss_latency::realview.ide 119463.149573 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 119463.149573 # average ReadReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 119463.149573 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 119463.149573 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 119463.149573 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 119463.149573 # average overall miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 119471.696581 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 119471.696581 # average ReadReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 119471.696581 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 119471.696581 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 119471.696581 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 119471.696581 # average overall miss latency
1231,1238c1146,1153
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 15785377 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 15785377 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2212496723 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2212496723 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 15785377 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 15785377 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 15785377 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 15785377 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 15787377 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 15787377 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2211427725 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2211427725 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 15787377 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 15787377 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 15787377 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 15787377 # number of overall MSHR miss cycles
1245,1246c1160,1161
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67458.876068 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 67458.876068 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67467.423077 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 67467.423077 # average ReadReq mshr miss latency
1249,1252c1164,1167
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 67458.876068 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 67458.876068 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 67458.876068 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 67458.876068 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 67467.423077 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 67467.423077 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 67467.423077 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 67467.423077 # average overall mshr miss latency
1253a1169,1251
> system.membus.trans_dist::ReadReq 71836 # Transaction distribution
> system.membus.trans_dist::ReadResp 71836 # Transaction distribution
> system.membus.trans_dist::WriteReq 27607 # Transaction distribution
> system.membus.trans_dist::WriteResp 27607 # Transaction distribution
> system.membus.trans_dist::Writeback 88794 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 4595 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 4597 # Transaction distribution
> system.membus.trans_dist::ReadExReq 129881 # Transaction distribution
> system.membus.trans_dist::ReadExResp 129881 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 448536 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 556168 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 628865 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16604248 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16768029 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 19087325 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 219 # Total snoops (count)
> system.membus.snoop_fanout::samples 297195 # Request fanout histogram
> system.membus.snoop_fanout::mean 1 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::1 297195 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 1 # Request fanout histogram
> system.membus.snoop_fanout::max_value 1 # Request fanout histogram
> system.membus.snoop_fanout::total 297195 # Request fanout histogram
> system.membus.reqLayer0.occupancy 87032500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
> system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
> system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
> system.membus.reqLayer2.occupancy 1706500 # Layer occupancy (ticks)
> system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
> system.membus.reqLayer5.occupancy 1386266250 # Layer occupancy (ticks)
> system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
> system.membus.respLayer2.occupancy 1718628403 # Layer occupancy (ticks)
> system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
> system.membus.respLayer3.occupancy 38334247 # Layer occupancy (ticks)
> system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
> system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
> system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
> system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
> system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
> system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
> system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
> system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
> system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
> system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
> system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
> system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
> system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
> system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
> system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
> system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
> system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
> system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
> system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
> system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
> system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
> system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
> system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
> system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
> system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
> system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
> system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
> system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
> system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
> system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
> system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
> system.realview.ethernet.droppedPackets 0 # number of packets dropped