3,5c3,5
< sim_seconds 2.852200 # Number of seconds simulated
< sim_ticks 2852200332000 # Number of ticks simulated
< final_tick 2852200332000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.852223 # Number of seconds simulated
> sim_ticks 2852222670000 # Number of ticks simulated
> final_tick 2852222670000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 169178 # Simulator instruction rate (inst/s)
< host_op_rate 204545 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 4322499487 # Simulator tick rate (ticks/s)
< host_mem_usage 558640 # Number of bytes of host memory used
< host_seconds 659.85 # Real time elapsed on the host
< sim_insts 111631963 # Number of instructions simulated
< sim_ops 134968701 # Number of ops (including micro ops) simulated
---
> host_inst_rate 166317 # Simulator instruction rate (inst/s)
> host_op_rate 201081 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 4259610797 # Simulator tick rate (ticks/s)
> host_mem_usage 558772 # Number of bytes of host memory used
> host_seconds 669.60 # Real time elapsed on the host
> sim_insts 111365458 # Number of instructions simulated
> sim_ops 134642914 # Number of ops (including micro ops) simulated
17,23c17,23
< system.physmem.bytes_read::cpu.dtb.walker 6592 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 10875428 # Number of bytes read from this memory
< system.physmem.bytes_read::total 10883108 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1665536 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1665536 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 5669632 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu.dtb.walker 6464 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 10896868 # Number of bytes read from this memory
> system.physmem.bytes_read::total 10904484 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1667584 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1667584 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 5681792 # Number of bytes written to this memory
26c26
< system.physmem.bytes_written::total 8005492 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 8017652 # Number of bytes written to this memory
28,32c28,32
< system.physmem.num_reads::cpu.dtb.walker 103 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 170448 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 170568 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 88588 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu.dtb.walker 101 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 170783 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 170902 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 88778 # Number of write requests responded to by this memory
35c35
< system.physmem.num_writes::total 129193 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 129383 # Number of write requests responded to by this memory
37,44c37,44
< system.physmem.bw_read::cpu.dtb.walker 2311 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 3812996 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 3815688 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 583948 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 583948 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1987810 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::realview.ide 812824 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.dtb.walker 2266 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 67 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 3820483 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 3823153 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 584661 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 584661 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1992058 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::realview.ide 812817 # Write bandwidth from this memory (bytes/s)
46,96c46,96
< system.physmem.bw_write::total 2806778 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1987810 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 813160 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 2311 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 3819140 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 6622466 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 170568 # Number of read requests accepted
< system.physmem.writeReqs 129193 # Number of write requests accepted
< system.physmem.readBursts 170568 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 129193 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 10907008 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue
< system.physmem.bytesWritten 8019264 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 10883108 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 8005492 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 4599 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 10529 # Per bank write bursts
< system.physmem.perBankRdBursts::1 10427 # Per bank write bursts
< system.physmem.perBankRdBursts::2 10726 # Per bank write bursts
< system.physmem.perBankRdBursts::3 10519 # Per bank write bursts
< system.physmem.perBankRdBursts::4 13519 # Per bank write bursts
< system.physmem.perBankRdBursts::5 10191 # Per bank write bursts
< system.physmem.perBankRdBursts::6 11164 # Per bank write bursts
< system.physmem.perBankRdBursts::7 10885 # Per bank write bursts
< system.physmem.perBankRdBursts::8 10359 # Per bank write bursts
< system.physmem.perBankRdBursts::9 10882 # Per bank write bursts
< system.physmem.perBankRdBursts::10 10112 # Per bank write bursts
< system.physmem.perBankRdBursts::11 9441 # Per bank write bursts
< system.physmem.perBankRdBursts::12 10326 # Per bank write bursts
< system.physmem.perBankRdBursts::13 11222 # Per bank write bursts
< system.physmem.perBankRdBursts::14 10031 # Per bank write bursts
< system.physmem.perBankRdBursts::15 10089 # Per bank write bursts
< system.physmem.perBankWrBursts::0 7745 # Per bank write bursts
< system.physmem.perBankWrBursts::1 7827 # Per bank write bursts
< system.physmem.perBankWrBursts::2 8372 # Per bank write bursts
< system.physmem.perBankWrBursts::3 8091 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7875 # Per bank write bursts
< system.physmem.perBankWrBursts::5 7401 # Per bank write bursts
< system.physmem.perBankWrBursts::6 8203 # Per bank write bursts
< system.physmem.perBankWrBursts::7 8042 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7896 # Per bank write bursts
< system.physmem.perBankWrBursts::9 8173 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7527 # Per bank write bursts
< system.physmem.perBankWrBursts::11 7251 # Per bank write bursts
< system.physmem.perBankWrBursts::12 7760 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8405 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7350 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7383 # Per bank write bursts
---
> system.physmem.bw_write::total 2811019 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1992058 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 813154 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 2266 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 67 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 3826627 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 6634172 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 170902 # Number of read requests accepted
> system.physmem.writeReqs 129383 # Number of write requests accepted
> system.physmem.readBursts 170902 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 129383 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 10927488 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 10240 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8031232 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 10904484 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 8017652 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 160 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 3869 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 4593 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 10513 # Per bank write bursts
> system.physmem.perBankRdBursts::1 10240 # Per bank write bursts
> system.physmem.perBankRdBursts::2 10772 # Per bank write bursts
> system.physmem.perBankRdBursts::3 10550 # Per bank write bursts
> system.physmem.perBankRdBursts::4 13501 # Per bank write bursts
> system.physmem.perBankRdBursts::5 10124 # Per bank write bursts
> system.physmem.perBankRdBursts::6 11177 # Per bank write bursts
> system.physmem.perBankRdBursts::7 10891 # Per bank write bursts
> system.physmem.perBankRdBursts::8 10227 # Per bank write bursts
> system.physmem.perBankRdBursts::9 10892 # Per bank write bursts
> system.physmem.perBankRdBursts::10 10093 # Per bank write bursts
> system.physmem.perBankRdBursts::11 9609 # Per bank write bursts
> system.physmem.perBankRdBursts::12 10331 # Per bank write bursts
> system.physmem.perBankRdBursts::13 11217 # Per bank write bursts
> system.physmem.perBankRdBursts::14 10288 # Per bank write bursts
> system.physmem.perBankRdBursts::15 10317 # Per bank write bursts
> system.physmem.perBankWrBursts::0 7730 # Per bank write bursts
> system.physmem.perBankWrBursts::1 7662 # Per bank write bursts
> system.physmem.perBankWrBursts::2 8408 # Per bank write bursts
> system.physmem.perBankWrBursts::3 8127 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7860 # Per bank write bursts
> system.physmem.perBankWrBursts::5 7340 # Per bank write bursts
> system.physmem.perBankWrBursts::6 8206 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8039 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7784 # Per bank write bursts
> system.physmem.perBankWrBursts::9 8077 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7518 # Per bank write bursts
> system.physmem.perBankWrBursts::11 7421 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7767 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8402 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7544 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7603 # Per bank write bursts
98,99c98,99
< system.physmem.numWrRetry 3 # Number of times write queue was full causing retry
< system.physmem.totGap 2852199845000 # Total gap between requests
---
> system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
> system.physmem.totGap 2852222186000 # Total gap between requests
106c106
< system.physmem.readPktSize::6 170013 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 170347 # Read request sizes (log2)
113,116c113,116
< system.physmem.writePktSize::6 124812 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 163493 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 6879 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 125002 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 164585 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 6110 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see
161,164c161,164
< system.physmem.wrQLenPdf::15 1958 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2501 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 6140 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 6615 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 1982 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2519 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 6120 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6597 # What write queue length does an incoming req see
166,198c166,198
< system.physmem.wrQLenPdf::20 7214 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7429 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 7947 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8437 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 9213 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 8656 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8187 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7664 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 7435 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 6716 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6560 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6537 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6495 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 246 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 222 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 214 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 200 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 189 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 194 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 177 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 149 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 145 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 131 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 114 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 87 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 83 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 65 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 49 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 40 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 38 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::20 7213 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7428 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 7985 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 8522 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 9334 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 8728 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 8242 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7692 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7486 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 6726 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6557 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6577 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6482 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 199 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 169 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 170 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 123 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 118 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 118 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 128 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 116 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 126 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 132 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 123 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 114 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 104 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 47 # What write queue length does an incoming req see
200,205c200,205
< system.physmem.wrQLenPdf::54 40 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 40 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 40 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 31 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 15 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 33 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see
208,227c208,227
< system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 60576 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 312.437401 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 184.644234 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 330.251922 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 22086 36.46% 36.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14485 23.91% 60.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6694 11.05% 71.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3534 5.83% 77.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2501 4.13% 81.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1624 2.68% 84.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1087 1.79% 85.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1062 1.75% 87.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7503 12.39% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 60576 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6291 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 27.088221 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 577.877413 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6289 99.97% 99.97% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 60830 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 311.666217 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 184.364711 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 329.290387 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 22259 36.59% 36.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 14417 23.70% 60.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6771 11.13% 71.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3560 5.85% 77.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2627 4.32% 81.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1563 2.57% 84.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1081 1.78% 85.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1081 1.78% 87.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7471 12.28% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 60830 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6311 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 27.051339 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 576.967682 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6309 99.97% 99.97% # Reads before turning the bus around for writes
230,262c230,261
< system.physmem.rdPerTurnAround::total 6291 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6291 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 19.917501 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.380102 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 11.942111 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5514 87.65% 87.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 46 0.73% 88.38% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 31 0.49% 88.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 207 3.29% 92.16% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 183 2.91% 95.07% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 14 0.22% 95.29% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 17 0.27% 95.57% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 17 0.27% 95.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 30 0.48% 96.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 7 0.11% 96.42% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 4 0.06% 96.49% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 3 0.05% 96.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 154 2.45% 98.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 3 0.05% 99.03% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 2 0.03% 99.06% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 4 0.06% 99.13% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 21 0.33% 99.46% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 1 0.02% 99.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 3 0.05% 99.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 1 0.02% 99.54% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 6 0.10% 99.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 2 0.03% 99.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 3 0.05% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 1 0.02% 99.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 2 0.03% 99.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 2 0.03% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 1 0.02% 99.81% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 2 0.03% 99.84% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 6311 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6311 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 19.884012 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.375867 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 11.802704 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5533 87.67% 87.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 35 0.55% 88.23% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 30 0.48% 88.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 215 3.41% 92.11% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 199 3.15% 95.26% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 15 0.24% 95.50% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 17 0.27% 95.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 19 0.30% 96.07% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 19 0.30% 96.37% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 6 0.10% 96.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 3 0.05% 96.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 4 0.06% 96.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 155 2.46% 99.03% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 5 0.08% 99.11% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 6 0.10% 99.21% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 3 0.05% 99.26% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 12 0.19% 99.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 2 0.03% 99.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 1 0.02% 99.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 7 0.11% 99.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 1 0.02% 99.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 3 0.05% 99.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 1 0.02% 99.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 5 0.08% 99.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 2 0.03% 99.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 1 0.02% 99.84% # Writes before turning the bus around for reads
264,270c263,269
< system.physmem.wrPerTurnAround::132-135 2 0.03% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6291 # Writes before turning the bus around for reads
< system.physmem.totQLat 1680738000 # Total ticks spent queuing
< system.physmem.totMemAccLat 4876150500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 852110000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 9862.21 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::136-139 1 0.02% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 3 0.05% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6311 # Writes before turning the bus around for reads
> system.physmem.totQLat 1715938250 # Total ticks spent queuing
> system.physmem.totMemAccLat 4917350750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 853710000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 10049.89 # Average queueing delay per DRAM burst
272,274c271,273
< system.physmem.avgMemAccLat 28612.21 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 3.82 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28799.89 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 3.83 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 2.82 # Average achieved write bandwidth in MiByte/s
281,290c280,289
< system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing
< system.physmem.readRowHits 140727 # Number of row buffer hits during reads
< system.physmem.writeRowHits 94419 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 82.58 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 75.34 # Row buffer hit rate for writes
< system.physmem.avgGap 9514913.03 # Average gap between requests
< system.physmem.pageHitRate 79.51 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 2713226080000 # Time in different power states
< system.physmem.memoryStateTime::REF 95241120000 # Time in different power states
---
> system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 23.21 # Average write queue length when enqueuing
> system.physmem.readRowHits 140944 # Number of row buffer hits during reads
> system.physmem.writeRowHits 94455 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 75.25 # Row buffer hit rate for writes
> system.physmem.avgGap 9498383.82 # Average gap between requests
> system.physmem.pageHitRate 79.46 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 2712510439500 # Time in different power states
> system.physmem.memoryStateTime::REF 95241900000 # Time in different power states
292c291
< system.physmem.memoryStateTime::ACT 43733042000 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 44470242000 # Time in different power states
294,325c293,324
< system.physmem.actEnergy::0 234125640 # Energy for activate commands per rank (pJ)
< system.physmem.actEnergy::1 223828920 # Energy for activate commands per rank (pJ)
< system.physmem.preEnergy::0 127747125 # Energy for precharge commands per rank (pJ)
< system.physmem.preEnergy::1 122128875 # Energy for precharge commands per rank (pJ)
< system.physmem.readEnergy::0 686088000 # Energy for read commands per rank (pJ)
< system.physmem.readEnergy::1 643195800 # Energy for read commands per rank (pJ)
< system.physmem.writeEnergy::0 411842880 # Energy for write commands per rank (pJ)
< system.physmem.writeEnergy::1 400107600 # Energy for write commands per rank (pJ)
< system.physmem.refreshEnergy::0 186291630720 # Energy for refresh commands per rank (pJ)
< system.physmem.refreshEnergy::1 186291630720 # Energy for refresh commands per rank (pJ)
< system.physmem.actBackEnergy::0 82872817560 # Energy for active background per rank (pJ)
< system.physmem.actBackEnergy::1 82165704345 # Energy for active background per rank (pJ)
< system.physmem.preBackEnergy::0 1638622788000 # Energy for precharge background per rank (pJ)
< system.physmem.preBackEnergy::1 1639243062750 # Energy for precharge background per rank (pJ)
< system.physmem.totalEnergy::0 1909247039925 # Total energy per rank (pJ)
< system.physmem.totalEnergy::1 1909089659010 # Total energy per rank (pJ)
< system.physmem.averagePower::0 669.395204 # Core power per rank (mW)
< system.physmem.averagePower::1 669.340025 # Core power per rank (mW)
< system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory
< system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory
< system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory
< system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
< system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
< system.realview.nvmem.bw_read::cpu.inst 180 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_read::total 180 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::cpu.inst 180 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::total 180 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_total::cpu.inst 180 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bw_total::total 180 # Total bandwidth to/from this memory (bytes/s)
< system.membus.trans_dist::ReadReq 71824 # Transaction distribution
< system.membus.trans_dist::ReadResp 71824 # Transaction distribution
---
> system.physmem.actEnergy::0 234798480 # Energy for activate commands per rank (pJ)
> system.physmem.actEnergy::1 225076320 # Energy for activate commands per rank (pJ)
> system.physmem.preEnergy::0 128114250 # Energy for precharge commands per rank (pJ)
> system.physmem.preEnergy::1 122809500 # Energy for precharge commands per rank (pJ)
> system.physmem.readEnergy::0 684590400 # Energy for read commands per rank (pJ)
> system.physmem.readEnergy::1 647189400 # Energy for read commands per rank (pJ)
> system.physmem.writeEnergy::0 410650560 # Energy for write commands per rank (pJ)
> system.physmem.writeEnergy::1 402511680 # Energy for write commands per rank (pJ)
> system.physmem.refreshEnergy::0 186293156400 # Energy for refresh commands per rank (pJ)
> system.physmem.refreshEnergy::1 186293156400 # Energy for refresh commands per rank (pJ)
> system.physmem.actBackEnergy::0 83147145165 # Energy for active background per rank (pJ)
> system.physmem.actBackEnergy::1 82654300080 # Energy for active background per rank (pJ)
> system.physmem.preBackEnergy::0 1638396165000 # Energy for precharge background per rank (pJ)
> system.physmem.preBackEnergy::1 1638828485250 # Energy for precharge background per rank (pJ)
> system.physmem.totalEnergy::0 1909294620255 # Total energy per rank (pJ)
> system.physmem.totalEnergy::1 1909173528630 # Total energy per rank (pJ)
> system.physmem.averagePower::0 669.406404 # Core power per rank (mW)
> system.physmem.averagePower::1 669.363949 # Core power per rank (mW)
> system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu.inst 448 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
> system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
> system.realview.nvmem.bw_read::cpu.inst 157 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::total 157 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu.inst 157 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::total 157 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu.inst 157 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::total 157 # Total bandwidth to/from this memory (bytes/s)
> system.membus.trans_dist::ReadReq 71842 # Transaction distribution
> system.membus.trans_dist::ReadResp 71842 # Transaction distribution
328c327
< system.membus.trans_dist::Writeback 88588 # Transaction distribution
---
> system.membus.trans_dist::Writeback 88778 # Transaction distribution
331c330
< system.membus.trans_dist::UpgradeReq 4597 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 4591 # Transaction distribution
333,335c332,334
< system.membus.trans_dist::UpgradeResp 4599 # Transaction distribution
< system.membus.trans_dist::ReadExReq 129554 # Transaction distribution
< system.membus.trans_dist::ReadExResp 129554 # Transaction distribution
---
> system.membus.trans_dist::UpgradeResp 4593 # Transaction distribution
> system.membus.trans_dist::ReadExReq 129869 # Transaction distribution
> system.membus.trans_dist::ReadExResp 129869 # Transaction distribution
337c336
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
339,340c338,339
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447654 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 555288 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 448500 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 556132 # Packet count per connected master and slave (bytes)
343c342
< system.membus.pkt_count::total 627985 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 628829 # Packet count per connected master and slave (bytes)
345c344
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
347,348c346,347
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16569304 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16733149 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16602840 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16766621 # Cumulative packet size per connected master and slave (bytes)
351c350
< system.membus.pkt_size::total 19052445 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 19085917 # Cumulative packet size per connected master and slave (bytes)
353c352
< system.membus.snoop_fanout::samples 296652 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 297178 # Request fanout histogram
358c357
< system.membus.snoop_fanout::1 296652 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 297178 100.00% 100.00% # Request fanout histogram
363,364c362,363
< system.membus.snoop_fanout::total 296652 # Request fanout histogram
< system.membus.reqLayer0.occupancy 87220000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 297178 # Request fanout histogram
> system.membus.reqLayer0.occupancy 87065000 # Layer occupancy (ticks)
366c365
< system.membus.reqLayer1.occupancy 11500 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
368c367
< system.membus.reqLayer2.occupancy 1713500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 1712000 # Layer occupancy (ticks)
370c369
< system.membus.reqLayer5.occupancy 1383760500 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 1386132250 # Layer occupancy (ticks)
372c371
< system.membus.respLayer2.occupancy 1715299901 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 1718569157 # Layer occupancy (ticks)
374c373
< system.membus.respLayer3.occupancy 38332500 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 38335749 # Layer occupancy (ticks)
507c506
< system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 326584849 # Layer occupancy (ticks)
513c512
< system.iobus.respLayer3.occupancy 36805500 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 36809251 # Layer occupancy (ticks)
516,520c515,519
< system.cpu.branchPred.lookups 30761849 # Number of BP lookups
< system.cpu.branchPred.condPredicted 16759561 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 2494541 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 18376022 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 13249221 # Number of BTB hits
---
> system.cpu.branchPred.lookups 30769128 # Number of BP lookups
> system.cpu.branchPred.condPredicted 16730733 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 2480939 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 18423796 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 13205412 # Number of BTB hits
522,524c521,523
< system.cpu.branchPred.BTBHitPct 72.100594 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 7712174 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 1491943 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 71.675848 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 7765211 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 1476374 # Number of incorrect RAS predictions.
548,551c547,550
< system.cpu.dtb.read_hits 24631139 # DTB read hits
< system.cpu.dtb.read_misses 58263 # DTB read misses
< system.cpu.dtb.write_hits 19400231 # DTB write hits
< system.cpu.dtb.write_misses 6058 # DTB write misses
---
> system.cpu.dtb.read_hits 24572928 # DTB read hits
> system.cpu.dtb.read_misses 58429 # DTB read misses
> system.cpu.dtb.write_hits 19368405 # DTB write hits
> system.cpu.dtb.write_misses 5913 # DTB write misses
556,558c555,557
< system.cpu.dtb.flush_entries 4344 # Number of entries that have been flushed from TLB
< system.cpu.dtb.align_faults 1249 # Number of TLB faults due to alignment restrictions
< system.cpu.dtb.prefetch_faults 1789 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB
> system.cpu.dtb.align_faults 1245 # Number of TLB faults due to alignment restrictions
> system.cpu.dtb.prefetch_faults 1816 # Number of TLB faults due to prefetch
560,562c559,561
< system.cpu.dtb.perms_faults 740 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 24689402 # DTB read accesses
< system.cpu.dtb.write_accesses 19406289 # DTB write accesses
---
> system.cpu.dtb.perms_faults 752 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 24631357 # DTB read accesses
> system.cpu.dtb.write_accesses 19374318 # DTB write accesses
564,566c563,565
< system.cpu.dtb.hits 44031370 # DTB hits
< system.cpu.dtb.misses 64321 # DTB misses
< system.cpu.dtb.accesses 44095691 # DTB accesses
---
> system.cpu.dtb.hits 43941333 # DTB hits
> system.cpu.dtb.misses 64342 # DTB misses
> system.cpu.dtb.accesses 44005675 # DTB accesses
588,589c587,588
< system.cpu.itb.inst_hits 57062578 # ITB inst hits
< system.cpu.itb.inst_misses 5424 # ITB inst misses
---
> system.cpu.itb.inst_hits 57038768 # ITB inst hits
> system.cpu.itb.inst_misses 5411 # ITB inst misses
598c597
< system.cpu.itb.flush_entries 2982 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_entries 2977 # Number of entries that have been flushed from TLB
602c601
< system.cpu.itb.perms_faults 8630 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 8664 # Number of TLB faults due to permissions restrictions
605,609c604,608
< system.cpu.itb.inst_accesses 57068002 # ITB inst accesses
< system.cpu.itb.hits 57062578 # DTB hits
< system.cpu.itb.misses 5424 # DTB misses
< system.cpu.itb.accesses 57068002 # DTB accesses
< system.cpu.numCycles 313219225 # number of cpu cycles simulated
---
> system.cpu.itb.inst_accesses 57044179 # ITB inst accesses
> system.cpu.itb.hits 57038768 # DTB hits
> system.cpu.itb.misses 5411 # DTB misses
> system.cpu.itb.accesses 57044179 # DTB accesses
> system.cpu.numCycles 313347638 # number of cpu cycles simulated
612,614c611,613
< system.cpu.committedInsts 111631963 # Number of instructions committed
< system.cpu.committedOps 134968701 # Number of ops (including micro ops) committed
< system.cpu.discardedOps 7932752 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.committedInsts 111365458 # Number of instructions committed
> system.cpu.committedOps 134642914 # Number of ops (including micro ops) committed
> system.cpu.discardedOps 7897593 # Number of ops (including micro ops) which were discarded before commit
616,618c615,617
< system.cpu.quiesceCycles 5391228164 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.cpi 2.805820 # CPI: cycles per instruction
< system.cpu.ipc 0.356402 # IPC: instructions per cycle
---
> system.cpu.quiesceCycles 5391144295 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.cpi 2.813688 # CPI: cycles per instruction
> system.cpu.ipc 0.355405 # IPC: instructions per cycle
621,629c620,628
< system.cpu.tickCycles 224159041 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 89060184 # Total number of cycles that the object has spent stopped
< system.cpu.icache.tags.replacements 2896816 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.427908 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 54156207 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 2897328 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 18.691776 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 15213008250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.427908 # Average occupied blocks per requestor
---
> system.cpu.tickCycles 224151816 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 89195822 # Total number of cycles that the object has spent stopped
> system.cpu.icache.tags.replacements 2897350 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.427915 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 54131849 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 2897862 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 18.679926 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 15213015250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.427915 # Average occupied blocks per requestor
633,635c632,634
< system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 200 # Occupied blocks per task id
637,674c636,673
< system.cpu.icache.tags.tag_accesses 59950884 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 59950884 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 54156207 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 54156207 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 54156207 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 54156207 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 54156207 # number of overall hits
< system.cpu.icache.overall_hits::total 54156207 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 2897339 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 2897339 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 2897339 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 2897339 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 2897339 # number of overall misses
< system.cpu.icache.overall_misses::total 2897339 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 39126605503 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 39126605503 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 39126605503 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 39126605503 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 39126605503 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 39126605503 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 57053546 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 57053546 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 57053546 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 57053546 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 57053546 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 57053546 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050783 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.050783 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.050783 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.050783 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.050783 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.050783 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.324314 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13504.324314 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.324314 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13504.324314 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.324314 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13504.324314 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 59927594 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 59927594 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 54131849 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 54131849 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 54131849 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 54131849 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 54131849 # number of overall hits
> system.cpu.icache.overall_hits::total 54131849 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 2897873 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 2897873 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 2897873 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 2897873 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 2897873 # number of overall misses
> system.cpu.icache.overall_misses::total 2897873 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 39140139756 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 39140139756 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 39140139756 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 39140139756 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 39140139756 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 39140139756 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 57029722 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 57029722 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 57029722 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 57029722 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 57029722 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 57029722 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050813 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.050813 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.050813 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.050813 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.050813 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.050813 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.506240 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13506.506240 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.506240 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13506.506240 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.506240 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13506.506240 # average overall miss latency
683,710c682,709
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897339 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 2897339 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 2897339 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 2897339 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 2897339 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 2897339 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33322439497 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 33322439497 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33322439497 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 33322439497 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33322439497 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 33322439497 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 222173750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 222173750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 222173750 # number of overall MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::total 222173750 # number of overall MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050783 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050783 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050783 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.050783 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050783 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.050783 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11501.049583 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11501.049583 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11501.049583 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11501.049583 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11501.049583 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11501.049583 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897873 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 2897873 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 2897873 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 2897873 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 2897873 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 2897873 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33334905244 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 33334905244 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33334905244 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 33334905244 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33334905244 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 33334905244 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 222062750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 222062750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 222062750 # number of overall MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::total 222062750 # number of overall MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050813 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050813 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050813 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.050813 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050813 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.050813 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11503.231937 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11503.231937 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11503.231937 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11503.231937 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11503.231937 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11503.231937 # average overall mshr miss latency
716,717c715,716
< system.cpu.toL2Bus.trans_dist::ReadReq 3575425 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 3575329 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 3575187 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 3575091 # Transaction distribution
720,722c719,721
< system.cpu.toL2Bus.trans_dist::Writeback 697864 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2819 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 697424 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36234 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2818 # Transaction distribution
724,740c723,739
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2821 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 295691 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 295691 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5800652 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2504517 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15250 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 156288 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 8476707 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185619904 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98723549 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18892 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 276412 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 284638757 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 60515 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 4573888 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5.007972 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.088927 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2820 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 295755 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 295755 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5801712 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2503299 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15293 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 155961 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 8476265 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185653696 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98670557 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 19168 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 276272 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 284619693 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 60174 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 4573282 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5.007974 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.088941 # Request fanout histogram
747,748c746,747
< system.cpu.toL2Bus.snoop_fanout::5 4537427 99.20% 99.20% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 36461 0.80% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::5 4536814 99.20% 99.20% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 36468 0.80% 100.00% # Request fanout histogram
752,753c751,752
< system.cpu.toL2Bus.snoop_fanout::total 4573888 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 3011299661 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 4573282 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 3010555155 # Layer occupancy (ticks)
757c756
< system.cpu.toL2Bus.respLayer0.occupancy 4355950753 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 4356749506 # Layer occupancy (ticks)
759c758
< system.cpu.toL2Bus.respLayer1.occupancy 1340010456 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1339516197 # Layer occupancy (ticks)
761c760
< system.cpu.toL2Bus.respLayer2.occupancy 10527250 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 10501000 # Layer occupancy (ticks)
763c762
< system.cpu.toL2Bus.respLayer3.occupancy 87188750 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 86895250 # Layer occupancy (ticks)
765,776c764,775
< system.cpu.l2cache.tags.replacements 97184 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65075.712435 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4041226 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 162444 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 24.877656 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 93442219500 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 47462.018914 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 55.401726 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.009455 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 17558.282340 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.724213 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000845 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.replacements 97514 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65073.344541 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4041263 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 162774 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 24.827448 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 93462601500 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 47542.577135 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 54.389093 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.009502 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 17476.368811 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.725442 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000830 # Average percentage of cache occupancy
778,797c777,796
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.267918 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.992977 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65213 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2308 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6976 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55798 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995071 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 36570721 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 36570721 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69000 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4721 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 3405800 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 3479521 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 697864 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 697864 # number of Writeback hits
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.266668 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.992940 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 44 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65216 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 44 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2322 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6967 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55801 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995117 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 36568997 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 36568997 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68967 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4789 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 3405854 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 3479610 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 697424 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 697424 # number of Writeback hits
800,815c799,814
< system.cpu.l2cache.ReadExReq_hits::cpu.inst 164314 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 164314 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 69000 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 4721 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 3570114 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 3643835 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 69000 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 4721 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 3570114 # number of overall hits
< system.cpu.l2cache.overall_hits::total 3643835 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 103 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.inst 37510 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 37615 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2774 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 2774 # number of UpgradeReq misses
---
> system.cpu.l2cache.ReadExReq_hits::cpu.inst 164068 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 164068 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 68967 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 4789 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 3569922 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 3643678 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 68967 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 4789 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 3569922 # number of overall hits
> system.cpu.l2cache.overall_hits::total 3643678 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 101 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.inst 37534 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 37638 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2773 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 2773 # number of UpgradeReq misses
818,853c817,852
< system.cpu.l2cache.ReadExReq_misses::cpu.inst 131377 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 131377 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 103 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.inst 168887 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 168992 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 103 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.inst 168887 # number of overall misses
< system.cpu.l2cache.overall_misses::total 168992 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 7796000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 163250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2760094000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 2768053250 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 998957 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 998957 # number of UpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst 46498 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46498 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9221968427 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 9221968427 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 7796000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 163250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 11982062427 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 11990021677 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 7796000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 163250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 11982062427 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 11990021677 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69103 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4723 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 3443310 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 3517136 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 697864 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 697864 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2819 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2819 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_misses::cpu.inst 131687 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 131687 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 101 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 169221 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 169325 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 101 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 169221 # number of overall misses
> system.cpu.l2cache.overall_misses::total 169325 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 7803500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 223500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2773793750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 2781820750 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 1024956 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 1024956 # number of UpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst 46998 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9263576682 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 9263576682 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 7803500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 223500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 12037370432 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 12045397432 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 7803500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 223500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 12037370432 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 12045397432 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69068 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4792 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 3443388 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 3517248 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 697424 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 697424 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2818 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2818 # number of UpgradeReq accesses(hits+misses)
856,871c855,870
< system.cpu.l2cache.ReadExReq_accesses::cpu.inst 295691 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 295691 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69103 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 4723 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 3739001 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 3812827 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69103 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 4723 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 3739001 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 3812827 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001491 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000423 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010894 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.010695 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.984037 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984037 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.inst 295755 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 295755 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69068 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 4792 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 3739143 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 3813003 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69068 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 4792 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 3739143 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 3813003 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001462 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000626 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010900 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.010701 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.984031 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984031 # miss rate for UpgradeReq accesses
874,901c873,900
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.444305 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.444305 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001491 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000423 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.045169 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.044322 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001491 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000423 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.045169 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.044322 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 75689.320388 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 81625 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73582.884564 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 73589.080154 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 360.114275 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 360.114275 # average UpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst 23249 # average SCUpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23249 # average SCUpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70194.694863 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70194.694863 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 75689.320388 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 81625 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70947.215754 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 70950.232419 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 75689.320388 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 81625 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70947.215754 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 70950.232419 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.445257 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.445257 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001462 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000626 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.045257 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.044407 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001462 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000626 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.045257 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.044407 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77262.376238 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74500 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73900.829914 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 73909.898241 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 369.619906 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 369.619906 # average UpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst 23499 # average SCUpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23499 # average SCUpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70345.415128 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70345.415128 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77262.376238 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71134.022562 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 71137.737676 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77262.376238 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71134.022562 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 71137.737676 # average overall miss latency
910,923c909,922
< system.cpu.l2cache.writebacks::writebacks 88588 # number of writebacks
< system.cpu.l2cache.writebacks::total 88588 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 165 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 165 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 165 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 165 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 103 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 37345 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 37450 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2774 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 2774 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.writebacks::writebacks 88778 # number of writebacks
> system.cpu.l2cache.writebacks::total 88778 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 168 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 168 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 168 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 168 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 168 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 168 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 101 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 37366 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 37470 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2773 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 2773 # number of UpgradeReq MSHR misses
926,941c925,940
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 131377 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 131377 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 103 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 168722 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 168827 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 103 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 168722 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 168827 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 6531000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 138750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2281377500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2288047250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 27781774 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27781774 # number of UpgradeReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 131687 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 131687 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 101 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 169053 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 169157 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 101 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 169053 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 169157 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 6559500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 187500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2294945750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2301692750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 27763773 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27763773 # number of UpgradeReq MSHR miss cycles
944,965c943,964
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7543603073 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7543603073 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 6531000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 138750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9824980573 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 9831650323 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 6531000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 138750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9824980573 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 9831650323 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5545609250 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545609250 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 4106796000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4106796000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 9652405250 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652405250 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001491 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000423 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010846 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010648 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.984037 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984037 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7581141318 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7581141318 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 6559500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 187500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9876087068 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 9882834068 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 6559500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 187500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9876087068 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 9882834068 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5545310750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545310750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 4106655500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4106655500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 9651966250 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9651966250 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001462 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000626 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010852 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010653 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.984031 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984031 # mshr miss rate for UpgradeReq accesses
968,983c967,982
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.444305 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.444305 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001491 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000423 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.045125 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.044279 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001491 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000423 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.045125 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.044279 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 63407.766990 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 69375 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61089.235507 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61096.054740 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10015.059120 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10015.059120 # average UpgradeReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.445257 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.445257 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001462 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000626 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.045212 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.044363 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001462 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000626 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.045212 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.044363 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64945.544554 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61418.020393 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61427.615426 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10012.179228 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10012.179228 # average UpgradeReq mshr miss latency
986,995c985,994
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57419.510820 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57419.510820 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 63407.766990 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 69375 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58231.769259 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58235.059102 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 63407.766990 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 69375 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58231.769259 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58235.059102 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57569.398027 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57569.398027 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64945.544554 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58420.063933 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58424.032514 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64945.544554 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58420.063933 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58424.032514 # average overall mshr miss latency
1003,1009c1002,1008
< system.cpu.dcache.tags.replacements 841153 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.953397 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 42536757 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 841665 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 50.538821 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 279806250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.inst 511.953397 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.replacements 840767 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.953448 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 42450068 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 841279 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 50.458965 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 279721250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.inst 511.953448 # Average occupied blocks per requestor
1013,1014c1012,1013
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 350 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 358 # Occupied blocks per task id
1017,1036c1016,1035
< system.cpu.dcache.tags.tag_accesses 175509435 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 175509435 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.inst 23374617 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23374617 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.inst 18241170 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 18241170 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.inst 457775 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 457775 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.inst 460281 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 460281 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.inst 41615787 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 41615787 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.inst 41615787 # number of overall hits
< system.cpu.dcache.overall_hits::total 41615787 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.inst 583566 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 583566 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.inst 541192 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 541192 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.inst 8333 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 8333 # number of LoadLockedReq misses
---
> system.cpu.dcache.tags.tag_accesses 175160699 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 175160699 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.inst 23317429 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23317429 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.inst 18211581 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 18211581 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.inst 457826 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 457826 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.inst 460320 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 460320 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.inst 41529010 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 41529010 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.inst 41529010 # number of overall hits
> system.cpu.dcache.overall_hits::total 41529010 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.inst 583115 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 583115 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.inst 541259 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 541259 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.inst 8317 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 8317 # number of LoadLockedReq misses
1039,1072c1038,1071
< system.cpu.dcache.demand_misses::cpu.inst 1124758 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1124758 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.inst 1124758 # number of overall misses
< system.cpu.dcache.overall_misses::total 1124758 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 8637456588 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 8637456588 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21531074313 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 21531074313 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 117993250 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 117993250 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 52502 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 52502 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 30168530901 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 30168530901 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 30168530901 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 30168530901 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.inst 23958183 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23958183 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.inst 18782362 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 18782362 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 466108 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 466108 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.inst 460283 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 460283 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.inst 42740545 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 42740545 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.inst 42740545 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 42740545 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.024358 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.024358 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.028814 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.028814 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.017878 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017878 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_misses::cpu.inst 1124374 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1124374 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.inst 1124374 # number of overall misses
> system.cpu.dcache.overall_misses::total 1124374 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 8642422585 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 8642422585 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21588022799 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 21588022799 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 117987000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 117987000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 53002 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 30230445384 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 30230445384 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 30230445384 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 30230445384 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.inst 23900544 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23900544 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.inst 18752840 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 18752840 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 466143 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 466143 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.inst 460322 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 460322 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.inst 42653384 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 42653384 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.inst 42653384 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 42653384 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.024398 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.024398 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.028863 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.028863 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.017842 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017842 # miss rate for LoadLockedReq accesses
1075,1090c1074,1089
< system.cpu.dcache.demand_miss_rate::cpu.inst 0.026316 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.026316 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.inst 0.026316 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.026316 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14801.164886 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14801.164886 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39784.539152 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 39784.539152 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14159.756390 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14159.756390 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 26251 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26251 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26822.241674 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 26822.241674 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26822.241674 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 26822.241674 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.inst 0.026361 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.026361 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.inst 0.026361 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.026361 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14821.128911 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14821.128911 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39884.829257 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 39884.829257 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14186.245040 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14186.245040 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 26501 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26886.467834 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 26886.467834 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26886.467834 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 26886.467834 # average overall miss latency
1099,1114c1098,1113
< system.cpu.dcache.writebacks::writebacks 697864 # number of writebacks
< system.cpu.dcache.writebacks::total 697864 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 45894 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 45894 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 242687 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 242687 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.inst 288581 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 288581 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.inst 288581 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 288581 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 537672 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 537672 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 298505 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 298505 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 8333 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 8333 # number of LoadLockedReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 697424 # number of writebacks
> system.cpu.dcache.writebacks::total 697424 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 45879 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 45879 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 242691 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 242691 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.inst 288570 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 288570 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.inst 288570 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 288570 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 537236 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 537236 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 298568 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 298568 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 8317 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 8317 # number of LoadLockedReq MSHR misses
1117,1144c1116,1143
< system.cpu.dcache.demand_mshr_misses::cpu.inst 836177 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 836177 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.inst 836177 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 836177 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6873353393 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6873353393 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 11227746403 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11227746403 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 101298750 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 101298750 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 48498 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48498 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 18101099796 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 18101099796 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 18101099796 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 18101099796 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5791247750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791247750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 4439329000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439329000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 10230576750 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230576750 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.022442 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022442 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015893 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015893 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.017878 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017878 # mshr miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_mshr_misses::cpu.inst 835804 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 835804 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.inst 835804 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 835804 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6874982646 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6874982646 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 11266915159 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 11266915159 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 101324000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 101324000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 48998 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 18141897805 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 18141897805 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 18141897805 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 18141897805 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5791016000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791016000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 4439188000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439188000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 10230204000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230204000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.022478 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022478 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015921 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015921 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.017842 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017842 # mshr miss rate for LoadLockedReq accesses
1147,1162c1146,1161
< system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.019564 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.019564 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019564 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.019564 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12783.543486 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12783.543486 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37613.260759 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37613.260759 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12156.336253 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12156.336253 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 24249 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24249 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21647.449997 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 21647.449997 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21647.449997 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 21647.449997 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.019595 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.019595 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019595 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.019595 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12796.950774 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12796.950774 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37736.512818 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37736.512818 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12182.758206 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12182.758206 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 24499 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21705.923644 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 21705.923644 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21705.923644 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 21705.923644 # average overall mshr miss latency
1171c1170
< system.iocache.tags.tagsinuse 1.031370 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.031475 # Cycle average of tags in use
1175,1178c1174,1177
< system.iocache.tags.warmup_cycle 269945589000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 1.031370 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.064461 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.064461 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 269946820000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 1.031475 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.064467 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.064467 # Average percentage of cache occupancy
1192,1197c1191,1196
< system.iocache.ReadReq_miss_latency::realview.ide 27970377 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 27970377 # number of ReadReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 27970377 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 27970377 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 27970377 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 27970377 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 27954377 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 27954377 # number of ReadReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 27954377 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 27954377 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 27954377 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 27954377 # number of overall miss cycles
1212,1217c1211,1216
< system.iocache.ReadReq_avg_miss_latency::realview.ide 119531.525641 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 119531.525641 # average ReadReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 119531.525641 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 119531.525641 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 119531.525641 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 119531.525641 # average overall miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 119463.149573 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 119463.149573 # average ReadReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 119463.149573 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 119463.149573 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 119463.149573 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 119463.149573 # average overall miss latency
1232,1239c1231,1238
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 15801377 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 15801377 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2215530472 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2215530472 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 15801377 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 15801377 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 15801377 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 15801377 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 15785377 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 15785377 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2212496723 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2212496723 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 15785377 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 15785377 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 15785377 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 15785377 # number of overall MSHR miss cycles
1246,1247c1245,1246
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67527.252137 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 67527.252137 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67458.876068 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 67458.876068 # average ReadReq mshr miss latency
1250,1253c1249,1252
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 67527.252137 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 67527.252137 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 67527.252137 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 67527.252137 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 67458.876068 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 67458.876068 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 67458.876068 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 67458.876068 # average overall mshr miss latency