3,5c3,5
< sim_seconds 2.566439 # Number of seconds simulated
< sim_ticks 2566439177500 # Number of ticks simulated
< final_tick 2566439177500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.566404 # Number of seconds simulated
> sim_ticks 2566404096500 # Number of ticks simulated
> final_tick 2566404096500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 109798 # Simulator instruction rate (inst/s)
< host_op_rate 132178 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 4650508258 # Simulator tick rate (ticks/s)
< host_mem_usage 408644 # Number of bytes of host memory used
< host_seconds 551.86 # Real time elapsed on the host
< sim_insts 60593470 # Number of instructions simulated
< sim_ops 72944147 # Number of ops (including micro ops) simulated
---
> host_inst_rate 108919 # Simulator instruction rate (inst/s)
> host_op_rate 131120 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 4613194748 # Simulator tick rate (ticks/s)
> host_mem_usage 411228 # Number of bytes of host memory used
> host_seconds 556.32 # Real time elapsed on the host
> sim_insts 60593541 # Number of instructions simulated
> sim_ops 72944224 # Number of ops (including micro ops) simulated
29c29
< system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.dtb.walker 1664 # Number of bytes read from this memory
31,35c31,35
< system.physmem.bytes_read::cpu.inst 10079960 # Number of bytes read from this memory
< system.physmem.bytes_read::total 131191960 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1001344 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1001344 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 3811328 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu.inst 10080024 # Number of bytes read from this memory
> system.physmem.bytes_read::total 131192344 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1001408 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1001408 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 3810496 # Number of bytes written to this memory
37c37
< system.physmem.bytes_written::total 6827400 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 6826568 # Number of bytes written to this memory
39c39
< system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.dtb.walker 26 # Number of read requests responded to by this memory
41,43c41,43
< system.physmem.num_reads::cpu.inst 157525 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 15296364 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 59552 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 157526 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 15296370 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 59539 # Number of write requests responded to by this memory
45,47c45,47
< system.physmem.num_writes::total 813570 # Number of write requests responded to by this memory
< system.physmem.bw_read::realview.clcd 47190103 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.dtb.walker 524 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 813557 # Number of write requests responded to by this memory
> system.physmem.bw_read::realview.clcd 47190748 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.dtb.walker 648 # Total read bandwidth from this memory (bytes/s)
49,58c49,58
< system.physmem.bw_read::cpu.inst 3927605 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 51118281 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 390169 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 390169 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1485065 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu.inst 1175197 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 2660262 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1485065 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.clcd 47190103 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 524 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 3927684 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 51119130 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 390199 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 390199 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1484761 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu.inst 1175213 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 2659974 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1484761 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.clcd 47190748 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 648 # Total bandwidth to/from this memory (bytes/s)
60,75c60,75
< system.physmem.bw_total::cpu.inst 5102802 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 53778543 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 15296364 # Number of read requests accepted
< system.physmem.writeReqs 813570 # Number of write requests accepted
< system.physmem.readBursts 15296364 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 813570 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 978868736 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 98560 # Total number of bytes read from write queue
< system.physmem.bytesWritten 6836224 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 131191960 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 6827400 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 1540 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 706728 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 4670 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 955903 # Per bank write bursts
< system.physmem.perBankRdBursts::1 955584 # Per bank write bursts
---
> system.physmem.bw_total::cpu.inst 5102897 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 53779104 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 15296370 # Number of read requests accepted
> system.physmem.writeReqs 813557 # Number of write requests accepted
> system.physmem.readBursts 15296370 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 813557 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 978862336 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 105344 # Total number of bytes read from write queue
> system.physmem.bytesWritten 6837568 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 131192344 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 6826568 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 1646 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 706692 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 4678 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 955907 # Per bank write bursts
> system.physmem.perBankRdBursts::1 955585 # Per bank write bursts
77,105c77,105
< system.physmem.perBankRdBursts::3 955912 # Per bank write bursts
< system.physmem.perBankRdBursts::4 957606 # Per bank write bursts
< system.physmem.perBankRdBursts::5 955733 # Per bank write bursts
< system.physmem.perBankRdBursts::6 955604 # Per bank write bursts
< system.physmem.perBankRdBursts::7 955438 # Per bank write bursts
< system.physmem.perBankRdBursts::8 956293 # Per bank write bursts
< system.physmem.perBankRdBursts::9 955954 # Per bank write bursts
< system.physmem.perBankRdBursts::10 955536 # Per bank write bursts
< system.physmem.perBankRdBursts::11 955097 # Per bank write bursts
< system.physmem.perBankRdBursts::12 956286 # Per bank write bursts
< system.physmem.perBankRdBursts::13 955995 # Per bank write bursts
< system.physmem.perBankRdBursts::14 956150 # Per bank write bursts
< system.physmem.perBankRdBursts::15 956022 # Per bank write bursts
< system.physmem.perBankWrBursts::0 6610 # Per bank write bursts
< system.physmem.perBankWrBursts::1 6419 # Per bank write bursts
< system.physmem.perBankWrBursts::2 6537 # Per bank write bursts
< system.physmem.perBankWrBursts::3 6577 # Per bank write bursts
< system.physmem.perBankWrBursts::4 6482 # Per bank write bursts
< system.physmem.perBankWrBursts::5 6744 # Per bank write bursts
< system.physmem.perBankWrBursts::6 6779 # Per bank write bursts
< system.physmem.perBankWrBursts::7 6682 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7031 # Per bank write bursts
< system.physmem.perBankWrBursts::9 6794 # Per bank write bursts
< system.physmem.perBankWrBursts::10 6476 # Per bank write bursts
< system.physmem.perBankWrBursts::11 6093 # Per bank write bursts
< system.physmem.perBankWrBursts::12 7096 # Per bank write bursts
< system.physmem.perBankWrBursts::13 6664 # Per bank write bursts
< system.physmem.perBankWrBursts::14 6987 # Per bank write bursts
< system.physmem.perBankWrBursts::15 6845 # Per bank write bursts
---
> system.physmem.perBankRdBursts::3 955918 # Per bank write bursts
> system.physmem.perBankRdBursts::4 957666 # Per bank write bursts
> system.physmem.perBankRdBursts::5 955713 # Per bank write bursts
> system.physmem.perBankRdBursts::6 955586 # Per bank write bursts
> system.physmem.perBankRdBursts::7 955417 # Per bank write bursts
> system.physmem.perBankRdBursts::8 956298 # Per bank write bursts
> system.physmem.perBankRdBursts::9 955963 # Per bank write bursts
> system.physmem.perBankRdBursts::10 955537 # Per bank write bursts
> system.physmem.perBankRdBursts::11 955091 # Per bank write bursts
> system.physmem.perBankRdBursts::12 956282 # Per bank write bursts
> system.physmem.perBankRdBursts::13 955994 # Per bank write bursts
> system.physmem.perBankRdBursts::14 956147 # Per bank write bursts
> system.physmem.perBankRdBursts::15 955909 # Per bank write bursts
> system.physmem.perBankWrBursts::0 6629 # Per bank write bursts
> system.physmem.perBankWrBursts::1 6411 # Per bank write bursts
> system.physmem.perBankWrBursts::2 6529 # Per bank write bursts
> system.physmem.perBankWrBursts::3 6576 # Per bank write bursts
> system.physmem.perBankWrBursts::4 6489 # Per bank write bursts
> system.physmem.perBankWrBursts::5 6741 # Per bank write bursts
> system.physmem.perBankWrBursts::6 6778 # Per bank write bursts
> system.physmem.perBankWrBursts::7 6680 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7055 # Per bank write bursts
> system.physmem.perBankWrBursts::9 6798 # Per bank write bursts
> system.physmem.perBankWrBursts::10 6471 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6090 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7091 # Per bank write bursts
> system.physmem.perBankWrBursts::13 6663 # Per bank write bursts
> system.physmem.perBankWrBursts::14 6989 # Per bank write bursts
> system.physmem.perBankWrBursts::15 6847 # Per bank write bursts
108c108
< system.physmem.totGap 2566437420000 # Total gap between requests
---
> system.physmem.totGap 2566402308000 # Total gap between requests
115c115
< system.physmem.readPktSize::6 157520 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 157526 # Read request sizes (log2)
122,141c122,141
< system.physmem.writePktSize::6 59552 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 1111382 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 958419 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 963594 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 1074014 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 973771 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 1037292 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 2691805 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 2600171 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 3390697 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 128159 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 109522 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 101552 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 98177 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 19262 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 18514 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 18294 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 197 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 59539 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1111407 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 958360 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 963566 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 1076065 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 974438 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 1039000 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 2689873 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 2594671 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 3384839 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 130586 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 112191 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 103349 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 100054 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 19345 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 18516 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 18281 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 177 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
170,180c170,180
< system.physmem.wrQLenPdf::15 3800 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3820 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 6181 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 6199 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6202 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6201 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6201 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 6202 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 6203 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 6202 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 6203 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 3792 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3809 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 6174 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6203 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6208 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6202 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6205 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6207 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 6209 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 6206 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 6205 # What write queue length does an incoming req see
182,188c182,188
< system.physmem.wrQLenPdf::27 6206 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6200 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 6204 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6199 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6201 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6199 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::27 6214 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6205 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 6202 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6203 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6202 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6201 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
219,254c219,257
< system.physmem.bytesPerActivate::samples 1014534 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 971.583959 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 905.812030 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 204.103928 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 21965 2.17% 2.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 22634 2.23% 4.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 8771 0.86% 5.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2477 0.24% 5.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2600 0.26% 5.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1707 0.17% 5.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 8766 0.86% 6.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1031 0.10% 6.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 944583 93.11% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1014534 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6199 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 2467.302629 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 115861.516346 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-524287 6194 99.92% 99.92% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 6199 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6199 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.231166 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.203067 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 0.975146 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 2381 38.41% 38.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 18 0.29% 38.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 3787 61.09% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 12 0.19% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6199 # Writes before turning the bus around for reads
< system.physmem.totQLat 394563558000 # Total ticks spent queuing
< system.physmem.totMemAccLat 681341508000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 76474120000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 25797.20 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 1014578 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 971.536840 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 905.616961 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 204.240777 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 22129 2.18% 2.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 22531 2.22% 4.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 8793 0.87% 5.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2465 0.24% 5.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2547 0.25% 5.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1763 0.17% 5.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 8722 0.86% 6.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 969 0.10% 6.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 944659 93.11% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1014578 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6201 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 2466.490405 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 89690.748368 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-262143 6195 99.90% 99.90% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.94% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.95% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.97% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::2.62144e+06-2.88358e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::6.02931e+06-6.29146e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 6201 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6201 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.228995 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.200624 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 0.980358 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 2397 38.66% 38.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 13 0.21% 38.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 3771 60.81% 99.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 16 0.26% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 3 0.05% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6201 # Writes before turning the bus around for reads
> system.physmem.totQLat 395011426750 # Total ticks spent queuing
> system.physmem.totMemAccLat 681787501750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 76473620000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 25826.65 # Average queueing delay per DRAM burst
256c259
< system.physmem.avgMemAccLat 44547.20 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 44576.65 # Average memory access latency per DRAM burst
265,268c268,271
< system.physmem.avgRdQLen 6.61 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 26.40 # Average write queue length when enqueuing
< system.physmem.readRowHits 14297661 # Number of row buffer hits during reads
< system.physmem.writeRowHits 89445 # Number of row buffer hits during writes
---
> system.physmem.avgRdQLen 6.27 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 24.27 # Average write queue length when enqueuing
> system.physmem.readRowHits 14297539 # Number of row buffer hits during reads
> system.physmem.writeRowHits 89444 # Number of row buffer hits during writes
270,271c273,274
< system.physmem.writeRowHitRate 83.72 # Row buffer hit rate for writes
< system.physmem.avgGap 159307.76 # Average gap between requests
---
> system.physmem.writeRowHitRate 83.70 # Row buffer hit rate for writes
> system.physmem.avgGap 159305.64 # Average gap between requests
273,274c276,277
< system.physmem.memoryStateTime::IDLE 2209628504250 # Time in different power states
< system.physmem.memoryStateTime::REF 85698860000 # Time in different power states
---
> system.physmem.memoryStateTime::IDLE 2209544766500 # Time in different power states
> system.physmem.memoryStateTime::REF 85697820000 # Time in different power states
276c279
< system.physmem.memoryStateTime::ACT 271106544500 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 271160177250 # Time in different power states
278,280c281,282
< system.membus.throughput 54713053 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 16348871 # Transaction distribution
< system.membus.trans_dist::ReadResp 16348871 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 16348869 # Transaction distribution
> system.membus.trans_dist::ReadResp 16348869 # Transaction distribution
283,288c285,290
< system.membus.trans_dist::Writeback 59552 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 4670 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 4670 # Transaction distribution
< system.membus.trans_dist::ReadExReq 131585 # Transaction distribution
< system.membus.trans_dist::ReadExResp 131585 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383068 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::Writeback 59539 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 4678 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 4678 # Transaction distribution
> system.membus.trans_dist::ReadExReq 131592 # Transaction distribution
> system.membus.trans_dist::ReadExResp 131592 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383066 # Packet count per connected master and slave (bytes)
292,293c294,295
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1892024 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4278902 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1892039 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4278915 # Packet count per connected master and slave (bytes)
296,308c298,320
< system.membus.pkt_count::total 34556534 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390502 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 256 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7600 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16908832 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19307194 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 140417722 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 140417722 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 1781248000 # Layer occupancy (ticks)
---
> system.membus.pkt_count::total 34556547 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390498 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 256 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7600 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16908384 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19306742 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 140417270 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 219423 # Request fanout histogram
> system.membus.snoop_fanout::mean 1 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::1 219423 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 1 # Request fanout histogram
> system.membus.snoop_fanout::max_value 1 # Request fanout histogram
> system.membus.snoop_fanout::total 219423 # Request fanout histogram
> system.membus.reqLayer0.occupancy 1783264500 # Layer occupancy (ticks)
312c324
< system.membus.reqLayer2.occupancy 3519500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 3414000 # Layer occupancy (ticks)
316c328
< system.membus.reqLayer6.occupancy 17618629000 # Layer occupancy (ticks)
---
> system.membus.reqLayer6.occupancy 17618330500 # Layer occupancy (ticks)
318c330
< system.membus.respLayer1.occupancy 4827707725 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 4827152764 # Layer occupancy (ticks)
320c332
< system.membus.respLayer2.occupancy 37448813750 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 37437958000 # Layer occupancy (ticks)
328,330c340,341
< system.iobus.throughput 48121550 # Throughput (bytes/s)
< system.iobus.trans_dist::ReadReq 16322172 # Transaction distribution
< system.iobus.trans_dist::ReadResp 16322172 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 16322171 # Transaction distribution
> system.iobus.trans_dist::ReadResp 16322171 # Transaction distribution
334c345
< system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes)
356c367
< system.iobus.pkt_count_system.bridge.master::total 2383068 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 2383066 # Packet count per connected master and slave (bytes)
359,387c370,397
< system.iobus.pkt_count::total 32660700 # Packet count per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1048 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::total 2390502 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::total 123501030 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.data_through_bus 123501030 # Total data (bytes)
---
> system.iobus.pkt_count::total 32660698 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1048 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::total 2390498 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 123501026 # Cumulative packet size per connected master and slave (bytes)
390c400
< system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks)
434,436c444,446
< system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
< system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
< system.iobus.respLayer0.occupancy 2374890000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks)
> system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
> system.iobus.respLayer0.occupancy 2374888000 # Layer occupancy (ticks)
438c448
< system.iobus.respLayer1.occupancy 38181688250 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 38185527000 # Layer occupancy (ticks)
441,445c451,455
< system.cpu.branchPred.lookups 12541574 # Number of BP lookups
< system.cpu.branchPred.condPredicted 9090690 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 1061681 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 8536244 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 6183587 # Number of BTB hits
---
> system.cpu.branchPred.lookups 12550628 # Number of BP lookups
> system.cpu.branchPred.condPredicted 9093116 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 1061685 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 8575859 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 6183324 # Number of BTB hits
447,449c457,459
< system.cpu.branchPred.BTBHitPct 72.439202 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1558068 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 139509 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 72.101512 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1560078 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 139853 # Number of incorrect RAS predictions.
473,476c483,486
< system.cpu.dtb.read_hits 13629654 # DTB read hits
< system.cpu.dtb.read_misses 33608 # DTB read misses
< system.cpu.dtb.write_hits 11376786 # DTB write hits
< system.cpu.dtb.write_misses 3775 # DTB write misses
---
> system.cpu.dtb.read_hits 13629467 # DTB read hits
> system.cpu.dtb.read_misses 33605 # DTB read misses
> system.cpu.dtb.write_hits 11376627 # DTB write hits
> system.cpu.dtb.write_misses 3703 # DTB write misses
481,483c491,493
< system.cpu.dtb.flush_entries 3449 # Number of entries that have been flushed from TLB
< system.cpu.dtb.align_faults 1586 # Number of TLB faults due to alignment restrictions
< system.cpu.dtb.prefetch_faults 251 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.flush_entries 3447 # Number of entries that have been flushed from TLB
> system.cpu.dtb.align_faults 1539 # Number of TLB faults due to alignment restrictions
> system.cpu.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch
486,487c496,497
< system.cpu.dtb.read_accesses 13663262 # DTB read accesses
< system.cpu.dtb.write_accesses 11380561 # DTB write accesses
---
> system.cpu.dtb.read_accesses 13663072 # DTB read accesses
> system.cpu.dtb.write_accesses 11380330 # DTB write accesses
489,491c499,501
< system.cpu.dtb.hits 25006440 # DTB hits
< system.cpu.dtb.misses 37383 # DTB misses
< system.cpu.dtb.accesses 25043823 # DTB accesses
---
> system.cpu.dtb.hits 25006094 # DTB hits
> system.cpu.dtb.misses 37308 # DTB misses
> system.cpu.dtb.accesses 25043402 # DTB accesses
513,514c523,524
< system.cpu.itb.inst_hits 22903214 # ITB inst hits
< system.cpu.itb.inst_misses 9061 # ITB inst misses
---
> system.cpu.itb.inst_hits 22908933 # ITB inst hits
> system.cpu.itb.inst_misses 9079 # ITB inst misses
523c533
< system.cpu.itb.flush_entries 2388 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_entries 2384 # Number of entries that have been flushed from TLB
527c537
< system.cpu.itb.perms_faults 5760 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 5702 # Number of TLB faults due to permissions restrictions
530,534c540,544
< system.cpu.itb.inst_accesses 22912275 # ITB inst accesses
< system.cpu.itb.hits 22903214 # DTB hits
< system.cpu.itb.misses 9061 # DTB misses
< system.cpu.itb.accesses 22912275 # DTB accesses
< system.cpu.numCycles 572663270 # number of cpu cycles simulated
---
> system.cpu.itb.inst_accesses 22918012 # ITB inst accesses
> system.cpu.itb.hits 22908933 # DTB hits
> system.cpu.itb.misses 9079 # DTB misses
> system.cpu.itb.accesses 22918012 # DTB accesses
> system.cpu.numCycles 572551547 # number of cpu cycles simulated
537,539c547,549
< system.cpu.committedInsts 60593470 # Number of instructions committed
< system.cpu.committedOps 72944147 # Number of ops (including micro ops) committed
< system.cpu.discardedOps 3225433 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.committedInsts 60593541 # Number of instructions committed
> system.cpu.committedOps 72944224 # Number of ops (including micro ops) committed
> system.cpu.discardedOps 3228444 # Number of ops (including micro ops) which were discarded before commit
541,543c551,553
< system.cpu.quiesceCycles 4562060973 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.cpi 9.450907 # CPI: cycles per instruction
< system.cpu.ipc 0.105810 # IPC: instructions per cycle
---
> system.cpu.quiesceCycles 4562038068 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.cpi 9.449052 # CPI: cycles per instruction
> system.cpu.ipc 0.105831 # IPC: instructions per cycle
546,556c556,566
< system.cpu.tickCycles 466702382 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 105960888 # Total number of cycles that the object has spent stopped
< system.cpu.icache.tags.replacements 1529303 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.463660 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 21367406 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1529815 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 13.967314 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 9992606000 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.463660 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.998952 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.998952 # Average percentage of cache occupancy
---
> system.cpu.tickCycles 466653116 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 105898431 # Total number of cycles that the object has spent stopped
> system.cpu.icache.tags.replacements 1529478 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.463685 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 21373010 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1529990 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 13.969379 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 9990881000 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.463685 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.998953 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.998953 # Average percentage of cache occupancy
558,560c568,570
< system.cpu.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 190 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id
563,600c573,610
< system.cpu.icache.tags.tag_accesses 24427037 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 24427037 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 21367406 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 21367406 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 21367406 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 21367406 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 21367406 # number of overall hits
< system.cpu.icache.overall_hits::total 21367406 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1529816 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1529816 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1529816 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1529816 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1529816 # number of overall misses
< system.cpu.icache.overall_misses::total 1529816 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 20677210137 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 20677210137 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 20677210137 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 20677210137 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 20677210137 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 20677210137 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 22897222 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 22897222 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 22897222 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 22897222 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 22897222 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 22897222 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.066812 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.066812 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.066812 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.066812 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.066812 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.066812 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13516.141900 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13516.141900 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13516.141900 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13516.141900 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13516.141900 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13516.141900 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 24432991 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 24432991 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 21373010 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 21373010 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 21373010 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 21373010 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 21373010 # number of overall hits
> system.cpu.icache.overall_hits::total 21373010 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1529991 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1529991 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1529991 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1529991 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1529991 # number of overall misses
> system.cpu.icache.overall_misses::total 1529991 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 20681368889 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 20681368889 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 20681368889 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 20681368889 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 20681368889 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 20681368889 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 22903001 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 22903001 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 22903001 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 22903001 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 22903001 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 22903001 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.066803 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.066803 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.066803 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.066803 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.066803 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.066803 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13517.314082 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13517.314082 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13517.314082 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13517.314082 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13517.314082 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13517.314082 # average overall miss latency
609,620c619,630
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1529816 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1529816 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1529816 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1529816 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1529816 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1529816 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17611902863 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 17611902863 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17611902863 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 17611902863 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17611902863 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 17611902863 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1529991 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1529991 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1529991 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1529991 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1529991 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1529991 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17615727111 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 17615727111 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17615727111 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 17615727111 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17615727111 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 17615727111 # number of overall MSHR miss cycles
625,636c635,646
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.066812 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.066812 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.066812 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11512.432125 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11512.432125 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11512.432125 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11512.432125 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11512.432125 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11512.432125 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066803 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.066803 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066803 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.066803 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066803 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.066803 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11513.614859 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11513.614859 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11513.614859 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11513.614859 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11513.614859 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11513.614859 # average overall mshr miss latency
642,644c652,653
< system.cpu.toL2Bus.throughput 71285625 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 3182019 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 3182018 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 3182062 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 3182061 # Transaction distribution
647,664c656,687
< system.cpu.toL2Bus.trans_dist::Writeback 600964 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2972 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2972 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 247467 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 247467 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3062398 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5774016 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 28971 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 100817 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 8966202 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 97936512 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84584698 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43908 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 166616 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 182731734 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 182731734 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 218488 # Total snoop data (bytes)
< system.cpu.toL2Bus.reqLayer0.occupancy 3381194945 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.trans_dist::Writeback 600919 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2980 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2980 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 247461 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 247461 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3062730 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5773755 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 28972 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 100548 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 8966005 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 97946560 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84574454 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43804 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 165736 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 182730554 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 26649 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 2846983 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 2846983 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 2846983 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 3381152937 # Layer occupancy (ticks)
666c689
< system.cpu.toL2Bus.respLayer0.occupancy 2301585887 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2301840639 # Layer occupancy (ticks)
668c691
< system.cpu.toL2Bus.respLayer1.occupancy 2547997212 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2547807667 # Layer occupancy (ticks)
670c693
< system.cpu.toL2Bus.respLayer2.occupancy 18000487 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 18027487 # Layer occupancy (ticks)
672c695
< system.cpu.toL2Bus.respLayer3.occupancy 59164999 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 59116998 # Layer occupancy (ticks)
674,681c697,704
< system.cpu.l2cache.tags.replacements 65085 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 51558.734735 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2407104 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 130473 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 18.449058 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 2524856942500 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 36497.819876 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.059887 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.replacements 65091 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 51567.943403 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2406935 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 130479 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 18.446915 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 2524835361000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 36492.360835 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 17.402377 # Average occupied blocks per requestor
683,685c706,708
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 15046.854396 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.556913 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000215 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 15058.179616 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.556829 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000266 # Average percentage of cache occupancy
687,691c710,714
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.229597 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.786724 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65374 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.229770 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.786864 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 15 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65373 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id
693,706c716,729
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2560 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6585 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56117 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997528 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 22967155 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 22967155 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 41633 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10975 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 1892880 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1945488 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 600964 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 600964 # number of Writeback hits
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2561 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6578 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56121 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000229 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997513 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 22965227 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 22965227 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 41408 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10949 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 1892934 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1945291 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 600919 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 600919 # number of Writeback hits
709,719c732,742
< system.cpu.l2cache.ReadExReq_hits::cpu.inst 114159 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 114159 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 41633 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 10975 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 2007039 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2059647 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 41633 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 10975 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 2007039 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2059647 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses
---
> system.cpu.l2cache.ReadExReq_hits::cpu.inst 114146 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 114146 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 41408 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 10949 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 2007080 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2059437 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 41408 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 10949 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 2007080 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2059437 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 26 # number of ReadReq misses
721,727c744,750
< system.cpu.l2cache.ReadReq_misses::cpu.inst 23661 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 23684 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2947 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 2947 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.inst 133308 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 133308 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 23655 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 23683 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2955 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 2955 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.inst 133315 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 133315 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 26 # number of demand (read+write) misses
729,731c752,754
< system.cpu.l2cache.demand_misses::cpu.inst 156969 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 156992 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 156970 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 156998 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 26 # number of overall misses
733,735c756,758
< system.cpu.l2cache.overall_misses::cpu.inst 156969 # number of overall misses
< system.cpu.l2cache.overall_misses::total 156992 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1631500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.overall_misses::cpu.inst 156970 # number of overall misses
> system.cpu.l2cache.overall_misses::total 156998 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2068000 # number of ReadReq miss cycles
737,743c760,766
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1700660750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 1702441750 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 347985 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 347985 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9353977027 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 9353977027 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1631500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1704040750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1706258250 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 348485 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 348485 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9355155027 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 9355155027 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2068000 # number of demand (read+write) miss cycles
745,747c768,770
< system.cpu.l2cache.demand_miss_latency::cpu.inst 11054637777 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 11056418777 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1631500 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 11059195777 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 11061413277 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2068000 # number of overall miss cycles
749,785c772,808
< system.cpu.l2cache.overall_miss_latency::cpu.inst 11054637777 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 11056418777 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 41654 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10977 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 1916541 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 1969172 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 600964 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 600964 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2972 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2972 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.inst 247467 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 247467 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 41654 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 10977 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 2164008 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2216639 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 41654 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 10977 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 2164008 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2216639 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000504 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000182 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012346 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.012027 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.991588 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991588 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.538690 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.538690 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000504 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000182 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.072536 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.070824 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000504 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000182 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.072536 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.070824 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77690.476190 # average ReadReq miss latency
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 11059195777 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 11061413277 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 41434 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10951 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 1916589 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 1968974 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 600919 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 600919 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2980 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2980 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.inst 247461 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 247461 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 41434 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 10951 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 2164050 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2216435 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 41434 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 10951 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 2164050 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2216435 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000628 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000183 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012342 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.012028 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.991611 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991611 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.538731 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.538731 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000628 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000183 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.072535 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.070834 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000628 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000183 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.072535 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.070834 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79538.461538 # average ReadReq miss latency
787,793c810,816
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71876.114704 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 71881.512836 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 118.081099 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 118.081099 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70168.159653 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70168.159653 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77690.476190 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72037.233143 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 72045.697336 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 117.930626 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 117.930626 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70173.311533 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70173.311533 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79538.461538 # average overall miss latency
795,797c818,820
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70425.611280 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 70426.638154 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77690.476190 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70454.200019 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 70455.759163 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79538.461538 # average overall miss latency
799,800c822,823
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70425.611280 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 70426.638154 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70454.200019 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 70455.759163 # average overall miss latency
809,810c832,833
< system.cpu.l2cache.writebacks::writebacks 59552 # number of writebacks
< system.cpu.l2cache.writebacks::total 59552 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 59539 # number of writebacks
> system.cpu.l2cache.writebacks::total 59539 # number of writebacks
817c840
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 26 # number of ReadReq MSHR misses
819,825c842,848
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 23592 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 23615 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2947 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 2947 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 133308 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 133308 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 23586 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 23614 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2955 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 2955 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 133315 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 133315 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 26 # number of demand (read+write) MSHR misses
827,829c850,852
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 156900 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 156923 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 156901 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 156929 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 26 # number of overall MSHR misses
831,833c854,856
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 156900 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 156923 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1370000 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 156901 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 156929 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1746000 # number of ReadReq MSHR miss cycles
835,841c858,864
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1400834750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1402329750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 29473947 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29473947 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7655220473 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7655220473 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1370000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1404219250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1406090250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 29553955 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29553955 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7656846473 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7656846473 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1746000 # number of demand (read+write) MSHR miss cycles
843,845c866,868
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9056055223 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 9057550223 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1370000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9061065723 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 9062936723 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1746000 # number of overall MSHR miss cycles
847,871c870,894
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9056055223 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 9057550223 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 167362107250 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167362107250 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 16707879855 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16707879855 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 184069987105 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184069987105 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000504 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000182 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012310 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011992 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.991588 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991588 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.538690 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.538690 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000504 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000182 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.072504 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.070793 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000504 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000182 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.072504 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.070793 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65238.095238 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9061065723 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 9062936723 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 167363942750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167363942750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 16707802808 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16707802808 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 184071745558 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184071745558 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000628 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012306 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011993 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.991611 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991611 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.538731 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.538731 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000628 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.072503 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.070802 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000628 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.072503 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.070802 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67153.846154 # average ReadReq mshr miss latency
873,879c896,902
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59377.532638 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59383.008681 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10001.339328 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.339328 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57425.064310 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57425.064310 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65238.095238 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59536.133723 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59544.772169 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10001.338409 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.338409 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57434.245756 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57434.245756 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67153.846154 # average overall mshr miss latency
881,883c904,906
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57718.643869 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57719.711088 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65238.095238 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57750.210152 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57751.828680 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67153.846154 # average overall mshr miss latency
885,886c908,909
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57718.643869 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57719.711088 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57750.210152 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57751.828680 # average overall mshr miss latency
894c917
< system.cpu.dcache.tags.replacements 635561 # number of replacements
---
> system.cpu.dcache.tags.replacements 635446 # number of replacements
896,898c919,921
< system.cpu.dcache.tags.total_refs 21828853 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 636073 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 34.318157 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 21828831 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 635958 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 34.324328 # Average number of references to valid blocks.
904,905c927,928
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id
908,915c931,938
< system.cpu.dcache.tags.tag_accesses 91724261 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 91724261 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.inst 11595405 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 11595405 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.inst 9746069 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 9746069 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.inst 236744 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 236744 # number of LoadLockedReq hits
---
> system.cpu.dcache.tags.tag_accesses 91723842 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 91723842 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.inst 11595412 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 11595412 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.inst 9746012 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 9746012 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.inst 236764 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 236764 # number of LoadLockedReq hits
918,945c941,968
< system.cpu.dcache.demand_hits::cpu.inst 21341474 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 21341474 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.inst 21341474 # number of overall hits
< system.cpu.dcache.overall_hits::total 21341474 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.inst 458732 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 458732 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.inst 476614 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 476614 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.inst 10870 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 10870 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.inst 935346 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 935346 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.inst 935346 # number of overall misses
< system.cpu.dcache.overall_misses::total 935346 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6943170934 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 6943170934 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 22231593506 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 22231593506 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 151835000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 151835000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 29174764440 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 29174764440 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 29174764440 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 29174764440 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.inst 12054137 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 12054137 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.inst 10222683 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 10222683 # number of WriteReq accesses(hits+misses)
---
> system.cpu.dcache.demand_hits::cpu.inst 21341424 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 21341424 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.inst 21341424 # number of overall hits
> system.cpu.dcache.overall_hits::total 21341424 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.inst 458657 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 458657 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.inst 476663 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 476663 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.inst 10850 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 10850 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.inst 935320 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 935320 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.inst 935320 # number of overall misses
> system.cpu.dcache.overall_misses::total 935320 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6947637684 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 6947637684 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 22233411759 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 22233411759 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 151795500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 151795500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 29181049443 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 29181049443 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 29181049443 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 29181049443 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.inst 12054069 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 12054069 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.inst 10222675 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 10222675 # number of WriteReq accesses(hits+misses)
950,973c973,996
< system.cpu.dcache.demand_accesses::cpu.inst 22276820 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 22276820 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.inst 22276820 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 22276820 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.038056 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.038056 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.046623 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.046623 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.043899 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043899 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.inst 0.041987 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.041987 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.inst 0.041987 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.041987 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15135.571388 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 15135.571388 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46644.860424 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 46644.860424 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13968.261270 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13968.261270 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 31191.414129 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 31191.414129 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 31191.414129 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 31191.414129 # average overall miss latency
---
> system.cpu.dcache.demand_accesses::cpu.inst 22276744 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 22276744 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.inst 22276744 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 22276744 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.038050 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.038050 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.046628 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.046628 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.043818 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043818 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.inst 0.041986 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.041986 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.inst 0.041986 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.041986 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15147.785129 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 15147.785129 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46643.879972 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 46643.879972 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13990.368664 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13990.368664 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 31199.000816 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 31199.000816 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 31199.000816 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 31199.000816 # average overall miss latency
982,1021c1005,1044
< system.cpu.dcache.writebacks::writebacks 600964 # number of writebacks
< system.cpu.dcache.writebacks::total 600964 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 80923 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 80923 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 226176 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 226176 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 72 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 72 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.inst 307099 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 307099 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.inst 307099 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 307099 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 377809 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 377809 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 250438 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 250438 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 10798 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 10798 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.inst 628247 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 628247 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.inst 628247 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 628247 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4823958811 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4823958811 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10813361832 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 10813361832 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 129211000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 129211000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15637320643 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 15637320643 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 15637320643 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 15637320643 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182632094750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182632094750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058171145 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058171145 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208690265895 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 208690265895 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.031343 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031343 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.writebacks::writebacks 600919 # number of writebacks
> system.cpu.dcache.writebacks::total 600919 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 80937 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 80937 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 226224 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 226224 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 71 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 71 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.inst 307161 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 307161 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.inst 307161 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 307161 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 377720 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 377720 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 250439 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 250439 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 10779 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 10779 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.inst 628159 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 628159 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.inst 628159 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 628159 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4824316311 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4824316311 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10814527330 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 10814527330 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 129220000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 129220000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15638843641 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 15638843641 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 15638843641 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 15638843641 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182633838500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182633838500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058035692 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058035692 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208691874192 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 208691874192 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.031335 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031335 # mshr miss rate for ReadReq accesses
1024,1039c1047,1062
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043608 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043608 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.028202 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.028202 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.028202 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.028202 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12768.247477 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12768.247477 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 43177.799823 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43177.799823 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11966.197444 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11966.197444 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24890.402410 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 24890.402410 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24890.402410 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 24890.402410 # average overall mshr miss latency
---
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043531 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043531 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.028198 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.028198 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.028198 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.028198 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12772.202454 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12772.202454 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 43182.281234 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43182.281234 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11988.125058 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11988.125058 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24896.313897 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 24896.313897 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24896.313897 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 24896.313897 # average overall mshr miss latency
1063,1066c1086,1089
< system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736623648250 # number of ReadReq MSHR uncacheable cycles
< system.iocache.ReadReq_mshr_uncacheable_latency::total 1736623648250 # number of ReadReq MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736623648250 # number of overall MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::total 1736623648250 # number of overall MSHR uncacheable cycles
---
> system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1737063641000 # number of ReadReq MSHR uncacheable cycles
> system.iocache.ReadReq_mshr_uncacheable_latency::total 1737063641000 # number of ReadReq MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1737063641000 # number of overall MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::total 1737063641000 # number of overall MSHR uncacheable cycles