1 2---------- Begin Simulation Statistics ----------
| 1 2---------- Begin Simulation Statistics ----------
|
3sim_seconds 2.852200 # Number of seconds simulated 4sim_ticks 2852200332000 # Number of ticks simulated 5final_tick 2852200332000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
| 3sim_seconds 2.852223 # Number of seconds simulated 4sim_ticks 2852222670000 # Number of ticks simulated 5final_tick 2852222670000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
6sim_freq 1000000000000 # Frequency of simulated ticks
| 6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 169178 # Simulator instruction rate (inst/s) 8host_op_rate 204545 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4322499487 # Simulator tick rate (ticks/s) 10host_mem_usage 558640 # Number of bytes of host memory used 11host_seconds 659.85 # Real time elapsed on the host 12sim_insts 111631963 # Number of instructions simulated 13sim_ops 134968701 # Number of ops (including micro ops) simulated
| 7host_inst_rate 166317 # Simulator instruction rate (inst/s) 8host_op_rate 201081 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4259610797 # Simulator tick rate (ticks/s) 10host_mem_usage 558772 # Number of bytes of host memory used 11host_seconds 669.60 # Real time elapsed on the host 12sim_insts 111365458 # Number of instructions simulated 13sim_ops 134642914 # Number of ops (including micro ops) simulated
|
14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
17system.physmem.bytes_read::cpu.dtb.walker 6592 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 10875428 # Number of bytes read from this memory 20system.physmem.bytes_read::total 10883108 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 1665536 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 1665536 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 5669632 # Number of bytes written to this memory
| 17system.physmem.bytes_read::cpu.dtb.walker 6464 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 10896868 # Number of bytes read from this memory 20system.physmem.bytes_read::total 10904484 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 1667584 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 1667584 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 5681792 # Number of bytes written to this memory
|
24system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.inst 17524 # Number of bytes written to this memory
| 24system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.inst 17524 # Number of bytes written to this memory
|
26system.physmem.bytes_written::total 8005492 # Number of bytes written to this memory
| 26system.physmem.bytes_written::total 8017652 # Number of bytes written to this memory
|
27system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
| 27system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
28system.physmem.num_reads::cpu.dtb.walker 103 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 170448 # Number of read requests responded to by this memory 31system.physmem.num_reads::total 170568 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 88588 # Number of write requests responded to by this memory
| 28system.physmem.num_reads::cpu.dtb.walker 101 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 170783 # Number of read requests responded to by this memory 31system.physmem.num_reads::total 170902 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 88778 # Number of write requests responded to by this memory
|
33system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.inst 4381 # Number of write requests responded to by this memory
| 33system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.inst 4381 # Number of write requests responded to by this memory
|
35system.physmem.num_writes::total 129193 # Number of write requests responded to by this memory
| 35system.physmem.num_writes::total 129383 # Number of write requests responded to by this memory
|
36system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
| 36system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
|
37system.physmem.bw_read::cpu.dtb.walker 2311 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 3812996 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::total 3815688 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu.inst 583948 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::total 583948 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_write::writebacks 1987810 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::realview.ide 812824 # Write bandwidth from this memory (bytes/s)
| 37system.physmem.bw_read::cpu.dtb.walker 2266 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 67 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 3820483 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::total 3823153 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu.inst 584661 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::total 584661 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_write::writebacks 1992058 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::realview.ide 812817 # Write bandwidth from this memory (bytes/s)
|
45system.physmem.bw_write::cpu.inst 6144 # Write bandwidth from this memory (bytes/s)
| 45system.physmem.bw_write::cpu.inst 6144 # Write bandwidth from this memory (bytes/s)
|
46system.physmem.bw_write::total 2806778 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1987810 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::realview.ide 813160 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 2311 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 3819140 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::total 6622466 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 170568 # Number of read requests accepted 54system.physmem.writeReqs 129193 # Number of write requests accepted 55system.physmem.readBursts 170568 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 129193 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 10907008 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue 59system.physmem.bytesWritten 8019264 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 10883108 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 8005492 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue 63system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one 64system.physmem.neitherReadNorWriteReqs 4599 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 10529 # Per bank write bursts 66system.physmem.perBankRdBursts::1 10427 # Per bank write bursts 67system.physmem.perBankRdBursts::2 10726 # Per bank write bursts 68system.physmem.perBankRdBursts::3 10519 # Per bank write bursts 69system.physmem.perBankRdBursts::4 13519 # Per bank write bursts 70system.physmem.perBankRdBursts::5 10191 # Per bank write bursts 71system.physmem.perBankRdBursts::6 11164 # Per bank write bursts 72system.physmem.perBankRdBursts::7 10885 # Per bank write bursts 73system.physmem.perBankRdBursts::8 10359 # Per bank write bursts 74system.physmem.perBankRdBursts::9 10882 # Per bank write bursts 75system.physmem.perBankRdBursts::10 10112 # Per bank write bursts 76system.physmem.perBankRdBursts::11 9441 # Per bank write bursts 77system.physmem.perBankRdBursts::12 10326 # Per bank write bursts 78system.physmem.perBankRdBursts::13 11222 # Per bank write bursts 79system.physmem.perBankRdBursts::14 10031 # Per bank write bursts 80system.physmem.perBankRdBursts::15 10089 # Per bank write bursts 81system.physmem.perBankWrBursts::0 7745 # Per bank write bursts 82system.physmem.perBankWrBursts::1 7827 # Per bank write bursts 83system.physmem.perBankWrBursts::2 8372 # Per bank write bursts 84system.physmem.perBankWrBursts::3 8091 # Per bank write bursts 85system.physmem.perBankWrBursts::4 7875 # Per bank write bursts 86system.physmem.perBankWrBursts::5 7401 # Per bank write bursts 87system.physmem.perBankWrBursts::6 8203 # Per bank write bursts 88system.physmem.perBankWrBursts::7 8042 # Per bank write bursts 89system.physmem.perBankWrBursts::8 7896 # Per bank write bursts 90system.physmem.perBankWrBursts::9 8173 # Per bank write bursts 91system.physmem.perBankWrBursts::10 7527 # Per bank write bursts 92system.physmem.perBankWrBursts::11 7251 # Per bank write bursts 93system.physmem.perBankWrBursts::12 7760 # Per bank write bursts 94system.physmem.perBankWrBursts::13 8405 # Per bank write bursts 95system.physmem.perBankWrBursts::14 7350 # Per bank write bursts 96system.physmem.perBankWrBursts::15 7383 # Per bank write bursts
| 46system.physmem.bw_write::total 2811019 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1992058 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::realview.ide 813154 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 2266 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 67 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 3826627 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::total 6634172 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 170902 # Number of read requests accepted 54system.physmem.writeReqs 129383 # Number of write requests accepted 55system.physmem.readBursts 170902 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 129383 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 10927488 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 10240 # Total number of bytes read from write queue 59system.physmem.bytesWritten 8031232 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 10904484 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 8017652 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 160 # Number of DRAM read bursts serviced by the write queue 63system.physmem.mergedWrBursts 3869 # Number of DRAM write bursts merged with an existing one 64system.physmem.neitherReadNorWriteReqs 4593 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 10513 # Per bank write bursts 66system.physmem.perBankRdBursts::1 10240 # Per bank write bursts 67system.physmem.perBankRdBursts::2 10772 # Per bank write bursts 68system.physmem.perBankRdBursts::3 10550 # Per bank write bursts 69system.physmem.perBankRdBursts::4 13501 # Per bank write bursts 70system.physmem.perBankRdBursts::5 10124 # Per bank write bursts 71system.physmem.perBankRdBursts::6 11177 # Per bank write bursts 72system.physmem.perBankRdBursts::7 10891 # Per bank write bursts 73system.physmem.perBankRdBursts::8 10227 # Per bank write bursts 74system.physmem.perBankRdBursts::9 10892 # Per bank write bursts 75system.physmem.perBankRdBursts::10 10093 # Per bank write bursts 76system.physmem.perBankRdBursts::11 9609 # Per bank write bursts 77system.physmem.perBankRdBursts::12 10331 # Per bank write bursts 78system.physmem.perBankRdBursts::13 11217 # Per bank write bursts 79system.physmem.perBankRdBursts::14 10288 # Per bank write bursts 80system.physmem.perBankRdBursts::15 10317 # Per bank write bursts 81system.physmem.perBankWrBursts::0 7730 # Per bank write bursts 82system.physmem.perBankWrBursts::1 7662 # Per bank write bursts 83system.physmem.perBankWrBursts::2 8408 # Per bank write bursts 84system.physmem.perBankWrBursts::3 8127 # Per bank write bursts 85system.physmem.perBankWrBursts::4 7860 # Per bank write bursts 86system.physmem.perBankWrBursts::5 7340 # Per bank write bursts 87system.physmem.perBankWrBursts::6 8206 # Per bank write bursts 88system.physmem.perBankWrBursts::7 8039 # Per bank write bursts 89system.physmem.perBankWrBursts::8 7784 # Per bank write bursts 90system.physmem.perBankWrBursts::9 8077 # Per bank write bursts 91system.physmem.perBankWrBursts::10 7518 # Per bank write bursts 92system.physmem.perBankWrBursts::11 7421 # Per bank write bursts 93system.physmem.perBankWrBursts::12 7767 # Per bank write bursts 94system.physmem.perBankWrBursts::13 8402 # Per bank write bursts 95system.physmem.perBankWrBursts::14 7544 # Per bank write bursts 96system.physmem.perBankWrBursts::15 7603 # Per bank write bursts
|
97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
| 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
98system.physmem.numWrRetry 3 # Number of times write queue was full causing retry 99system.physmem.totGap 2852199845000 # Total gap between requests
| 98system.physmem.numWrRetry 10 # Number of times write queue was full causing retry 99system.physmem.totGap 2852222186000 # Total gap between requests
|
100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 541 # Read request sizes (log2) 103system.physmem.readPktSize::3 14 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2)
| 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 541 # Read request sizes (log2) 103system.physmem.readPktSize::3 14 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
106system.physmem.readPktSize::6 170013 # Read request sizes (log2)
| 106system.physmem.readPktSize::6 170347 # Read request sizes (log2)
|
107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 4381 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2)
| 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 4381 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
113system.physmem.writePktSize::6 124812 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 163493 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 6879 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see
| 113system.physmem.writePktSize::6 125002 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 164585 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 6110 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see
|
117system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 146system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
| 117system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 146system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
161system.physmem.wrQLenPdf::15 1958 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 2501 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 6140 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 6615 # What write queue length does an incoming req see
| 161system.physmem.wrQLenPdf::15 1982 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 2519 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 6120 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 6597 # What write queue length does an incoming req see
|
165system.physmem.wrQLenPdf::19 6634 # What write queue length does an incoming req see
| 165system.physmem.wrQLenPdf::19 6634 # What write queue length does an incoming req see
|
166system.physmem.wrQLenPdf::20 7214 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 7429 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 7947 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 8437 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 9213 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 8656 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 8187 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 7664 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 7435 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::29 6716 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::30 6560 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 6537 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 6495 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 246 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 222 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 214 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 200 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 189 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 194 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 177 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 149 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 145 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 131 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 114 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 87 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 83 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 65 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 49 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 40 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 38 # What write queue length does an incoming req see
| 166system.physmem.wrQLenPdf::20 7213 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 7428 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 7985 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 8522 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 9334 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 8728 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 8242 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 7692 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 7486 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::29 6726 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::30 6557 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 6577 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 6482 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 199 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 169 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 170 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 123 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 118 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 118 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 128 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 116 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 126 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 132 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 123 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 114 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 104 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 47 # What write queue length does an incoming req see
|
199system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see
| 199system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see
|
200system.physmem.wrQLenPdf::54 40 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::55 40 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 40 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 31 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 15 # What write queue length does an incoming req see
| 200system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::55 33 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see
|
206system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 11 # What write queue length does an incoming req see
| 206system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 11 # What write queue length does an incoming req see
|
208system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 60576 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 312.437401 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 184.644234 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 330.251922 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 22086 36.46% 36.46% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 14485 23.91% 60.37% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 6694 11.05% 71.42% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 3534 5.83% 77.26% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 2501 4.13% 81.39% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 1624 2.68% 84.07% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 1087 1.79% 85.86% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 1062 1.75% 87.61% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 7503 12.39% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 60576 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 6291 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 27.088221 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 577.877413 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-2047 6289 99.97% 99.97% # Reads before turning the bus around for writes
| 208system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 60830 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 311.666217 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 184.364711 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 329.290387 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 22259 36.59% 36.59% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 14417 23.70% 60.29% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 6771 11.13% 71.42% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 3560 5.85% 77.28% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 2627 4.32% 81.59% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 1563 2.57% 84.16% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 1081 1.78% 85.94% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 1081 1.78% 87.72% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 7471 12.28% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 60830 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 6311 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 27.051339 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 576.967682 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-2047 6309 99.97% 99.97% # Reads before turning the bus around for writes
|
228system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes
| 228system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes
|
230system.physmem.rdPerTurnAround::total 6291 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 6291 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 19.917501 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 18.380102 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 11.942111 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-19 5514 87.65% 87.65% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::20-23 46 0.73% 88.38% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-27 31 0.49% 88.87% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-31 207 3.29% 92.16% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-35 183 2.91% 95.07% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::36-39 14 0.22% 95.29% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-43 17 0.27% 95.57% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::44-47 17 0.27% 95.84% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::48-51 30 0.48% 96.31% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::52-55 7 0.11% 96.42% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::56-59 4 0.06% 96.49% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::60-63 3 0.05% 96.53% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-67 154 2.45% 98.98% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::68-71 3 0.05% 99.03% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::72-75 2 0.03% 99.06% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::76-79 4 0.06% 99.13% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::80-83 21 0.33% 99.46% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::84-87 1 0.02% 99.48% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::88-91 3 0.05% 99.52% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::92-95 1 0.02% 99.54% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::96-99 6 0.10% 99.63% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::100-103 2 0.03% 99.67% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::104-107 3 0.05% 99.71% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::108-111 1 0.02% 99.73% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::112-115 2 0.03% 99.76% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::116-119 2 0.03% 99.79% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::120-123 1 0.02% 99.81% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::124-127 2 0.03% 99.84% # Writes before turning the bus around for reads
| 230system.physmem.rdPerTurnAround::total 6311 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 6311 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 19.884012 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 18.375867 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 11.802704 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-19 5533 87.67% 87.67% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::20-23 35 0.55% 88.23% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-27 30 0.48% 88.70% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-31 215 3.41% 92.11% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-35 199 3.15% 95.26% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::36-39 15 0.24% 95.50% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-43 17 0.27% 95.77% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::44-47 19 0.30% 96.07% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::48-51 19 0.30% 96.37% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::52-55 6 0.10% 96.47% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::56-59 3 0.05% 96.51% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::60-63 4 0.06% 96.58% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-67 155 2.46% 99.03% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::68-71 5 0.08% 99.11% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::72-75 6 0.10% 99.21% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::76-79 3 0.05% 99.26% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::80-83 12 0.19% 99.45% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::84-87 2 0.03% 99.48% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::92-95 1 0.02% 99.52% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::96-99 7 0.11% 99.64% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::100-103 1 0.02% 99.65% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::104-107 3 0.05% 99.70% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::108-111 1 0.02% 99.71% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::112-115 5 0.08% 99.79% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::116-119 2 0.03% 99.83% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::124-127 1 0.02% 99.84% # Writes before turning the bus around for reads
|
263system.physmem.wrPerTurnAround::128-131 6 0.10% 99.94% # Writes before turning the bus around for reads
| 262system.physmem.wrPerTurnAround::128-131 6 0.10% 99.94% # Writes before turning the bus around for reads
|
264system.physmem.wrPerTurnAround::132-135 2 0.03% 99.97% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::total 6291 # Writes before turning the bus around for reads 267system.physmem.totQLat 1680738000 # Total ticks spent queuing 268system.physmem.totMemAccLat 4876150500 # Total ticks spent from burst creation until serviced by the DRAM 269system.physmem.totBusLat 852110000 # Total ticks spent in databus transfers 270system.physmem.avgQLat 9862.21 # Average queueing delay per DRAM burst
| 263system.physmem.wrPerTurnAround::136-139 1 0.02% 99.95% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::140-143 3 0.05% 100.00% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::total 6311 # Writes before turning the bus around for reads 266system.physmem.totQLat 1715938250 # Total ticks spent queuing 267system.physmem.totMemAccLat 4917350750 # Total ticks spent from burst creation until serviced by the DRAM 268system.physmem.totBusLat 853710000 # Total ticks spent in databus transfers 269system.physmem.avgQLat 10049.89 # Average queueing delay per DRAM burst
|
271system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
| 270system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
272system.physmem.avgMemAccLat 28612.21 # Average memory access latency per DRAM burst 273system.physmem.avgRdBW 3.82 # Average DRAM read bandwidth in MiByte/s 274system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s
| 271system.physmem.avgMemAccLat 28799.89 # Average memory access latency per DRAM burst 272system.physmem.avgRdBW 3.83 # Average DRAM read bandwidth in MiByte/s 273system.physmem.avgWrBW 2.82 # Average achieved write bandwidth in MiByte/s
|
275system.physmem.avgRdBWSys 3.82 # Average system read bandwidth in MiByte/s 276system.physmem.avgWrBWSys 2.81 # Average system write bandwidth in MiByte/s 277system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 278system.physmem.busUtil 0.05 # Data bus utilization in percentage 279system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 280system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
| 274system.physmem.avgRdBWSys 3.82 # Average system read bandwidth in MiByte/s 275system.physmem.avgWrBWSys 2.81 # Average system write bandwidth in MiByte/s 276system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 277system.physmem.busUtil 0.05 # Data bus utilization in percentage 278system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 279system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
281system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 282system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing 283system.physmem.readRowHits 140727 # Number of row buffer hits during reads 284system.physmem.writeRowHits 94419 # Number of row buffer hits during writes 285system.physmem.readRowHitRate 82.58 # Row buffer hit rate for reads 286system.physmem.writeRowHitRate 75.34 # Row buffer hit rate for writes 287system.physmem.avgGap 9514913.03 # Average gap between requests 288system.physmem.pageHitRate 79.51 # Row buffer hit rate, read and write combined 289system.physmem.memoryStateTime::IDLE 2713226080000 # Time in different power states 290system.physmem.memoryStateTime::REF 95241120000 # Time in different power states
| 280system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 281system.physmem.avgWrQLen 23.21 # Average write queue length when enqueuing 282system.physmem.readRowHits 140944 # Number of row buffer hits during reads 283system.physmem.writeRowHits 94455 # Number of row buffer hits during writes 284system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads 285system.physmem.writeRowHitRate 75.25 # Row buffer hit rate for writes 286system.physmem.avgGap 9498383.82 # Average gap between requests 287system.physmem.pageHitRate 79.46 # Row buffer hit rate, read and write combined 288system.physmem.memoryStateTime::IDLE 2712510439500 # Time in different power states 289system.physmem.memoryStateTime::REF 95241900000 # Time in different power states
|
291system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
| 290system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
292system.physmem.memoryStateTime::ACT 43733042000 # Time in different power states
| 291system.physmem.memoryStateTime::ACT 44470242000 # Time in different power states
|
293system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
| 292system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
294system.physmem.actEnergy::0 234125640 # Energy for activate commands per rank (pJ) 295system.physmem.actEnergy::1 223828920 # Energy for activate commands per rank (pJ) 296system.physmem.preEnergy::0 127747125 # Energy for precharge commands per rank (pJ) 297system.physmem.preEnergy::1 122128875 # Energy for precharge commands per rank (pJ) 298system.physmem.readEnergy::0 686088000 # Energy for read commands per rank (pJ) 299system.physmem.readEnergy::1 643195800 # Energy for read commands per rank (pJ) 300system.physmem.writeEnergy::0 411842880 # Energy for write commands per rank (pJ) 301system.physmem.writeEnergy::1 400107600 # Energy for write commands per rank (pJ) 302system.physmem.refreshEnergy::0 186291630720 # Energy for refresh commands per rank (pJ) 303system.physmem.refreshEnergy::1 186291630720 # Energy for refresh commands per rank (pJ) 304system.physmem.actBackEnergy::0 82872817560 # Energy for active background per rank (pJ) 305system.physmem.actBackEnergy::1 82165704345 # Energy for active background per rank (pJ) 306system.physmem.preBackEnergy::0 1638622788000 # Energy for precharge background per rank (pJ) 307system.physmem.preBackEnergy::1 1639243062750 # Energy for precharge background per rank (pJ) 308system.physmem.totalEnergy::0 1909247039925 # Total energy per rank (pJ) 309system.physmem.totalEnergy::1 1909089659010 # Total energy per rank (pJ) 310system.physmem.averagePower::0 669.395204 # Core power per rank (mW) 311system.physmem.averagePower::1 669.340025 # Core power per rank (mW) 312system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory 313system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory 314system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory 315system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory 316system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 317system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 318system.realview.nvmem.bw_read::cpu.inst 180 # Total read bandwidth from this memory (bytes/s) 319system.realview.nvmem.bw_read::total 180 # Total read bandwidth from this memory (bytes/s) 320system.realview.nvmem.bw_inst_read::cpu.inst 180 # Instruction read bandwidth from this memory (bytes/s) 321system.realview.nvmem.bw_inst_read::total 180 # Instruction read bandwidth from this memory (bytes/s) 322system.realview.nvmem.bw_total::cpu.inst 180 # Total bandwidth to/from this memory (bytes/s) 323system.realview.nvmem.bw_total::total 180 # Total bandwidth to/from this memory (bytes/s) 324system.membus.trans_dist::ReadReq 71824 # Transaction distribution 325system.membus.trans_dist::ReadResp 71824 # Transaction distribution
| 293system.physmem.actEnergy::0 234798480 # Energy for activate commands per rank (pJ) 294system.physmem.actEnergy::1 225076320 # Energy for activate commands per rank (pJ) 295system.physmem.preEnergy::0 128114250 # Energy for precharge commands per rank (pJ) 296system.physmem.preEnergy::1 122809500 # Energy for precharge commands per rank (pJ) 297system.physmem.readEnergy::0 684590400 # Energy for read commands per rank (pJ) 298system.physmem.readEnergy::1 647189400 # Energy for read commands per rank (pJ) 299system.physmem.writeEnergy::0 410650560 # Energy for write commands per rank (pJ) 300system.physmem.writeEnergy::1 402511680 # Energy for write commands per rank (pJ) 301system.physmem.refreshEnergy::0 186293156400 # Energy for refresh commands per rank (pJ) 302system.physmem.refreshEnergy::1 186293156400 # Energy for refresh commands per rank (pJ) 303system.physmem.actBackEnergy::0 83147145165 # Energy for active background per rank (pJ) 304system.physmem.actBackEnergy::1 82654300080 # Energy for active background per rank (pJ) 305system.physmem.preBackEnergy::0 1638396165000 # Energy for precharge background per rank (pJ) 306system.physmem.preBackEnergy::1 1638828485250 # Energy for precharge background per rank (pJ) 307system.physmem.totalEnergy::0 1909294620255 # Total energy per rank (pJ) 308system.physmem.totalEnergy::1 1909173528630 # Total energy per rank (pJ) 309system.physmem.averagePower::0 669.406404 # Core power per rank (mW) 310system.physmem.averagePower::1 669.363949 # Core power per rank (mW) 311system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory 312system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory 313system.realview.nvmem.bytes_inst_read::cpu.inst 448 # Number of instructions bytes read from this memory 314system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory 315system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory 316system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 317system.realview.nvmem.bw_read::cpu.inst 157 # Total read bandwidth from this memory (bytes/s) 318system.realview.nvmem.bw_read::total 157 # Total read bandwidth from this memory (bytes/s) 319system.realview.nvmem.bw_inst_read::cpu.inst 157 # Instruction read bandwidth from this memory (bytes/s) 320system.realview.nvmem.bw_inst_read::total 157 # Instruction read bandwidth from this memory (bytes/s) 321system.realview.nvmem.bw_total::cpu.inst 157 # Total bandwidth to/from this memory (bytes/s) 322system.realview.nvmem.bw_total::total 157 # Total bandwidth to/from this memory (bytes/s) 323system.membus.trans_dist::ReadReq 71842 # Transaction distribution 324system.membus.trans_dist::ReadResp 71842 # Transaction distribution
|
326system.membus.trans_dist::WriteReq 27607 # Transaction distribution 327system.membus.trans_dist::WriteResp 27607 # Transaction distribution
| 325system.membus.trans_dist::WriteReq 27607 # Transaction distribution 326system.membus.trans_dist::WriteResp 27607 # Transaction distribution
|
328system.membus.trans_dist::Writeback 88588 # Transaction distribution
| 327system.membus.trans_dist::Writeback 88778 # Transaction distribution
|
329system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 330system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
| 328system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 329system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
331system.membus.trans_dist::UpgradeReq 4597 # Transaction distribution
| 330system.membus.trans_dist::UpgradeReq 4591 # Transaction distribution
|
332system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
| 331system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
333system.membus.trans_dist::UpgradeResp 4599 # Transaction distribution 334system.membus.trans_dist::ReadExReq 129554 # Transaction distribution 335system.membus.trans_dist::ReadExResp 129554 # Transaction distribution
| 332system.membus.trans_dist::UpgradeResp 4593 # Transaction distribution 333system.membus.trans_dist::ReadExReq 129869 # Transaction distribution 334system.membus.trans_dist::ReadExResp 129869 # Transaction distribution
|
336system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
| 335system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
|
337system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
| 336system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
|
338system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes)
| 337system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes)
|
339system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447654 # Packet count per connected master and slave (bytes) 340system.membus.pkt_count_system.cpu.l2cache.mem_side::total 555288 # Packet count per connected master and slave (bytes)
| 338system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 448500 # Packet count per connected master and slave (bytes) 339system.membus.pkt_count_system.cpu.l2cache.mem_side::total 556132 # Packet count per connected master and slave (bytes)
|
341system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) 342system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes)
| 340system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) 341system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes)
|
343system.membus.pkt_count::total 627985 # Packet count per connected master and slave (bytes)
| 342system.membus.pkt_count::total 628829 # Packet count per connected master and slave (bytes)
|
344system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
| 343system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
|
345system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes)
| 344system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
|
346system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes)
| 345system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes)
|
347system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16569304 # Cumulative packet size per connected master and slave (bytes) 348system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16733149 # Cumulative packet size per connected master and slave (bytes)
| 346system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16602840 # Cumulative packet size per connected master and slave (bytes) 347system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16766621 # Cumulative packet size per connected master and slave (bytes)
|
349system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 350system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
| 348system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 349system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
|
351system.membus.pkt_size::total 19052445 # Cumulative packet size per connected master and slave (bytes)
| 350system.membus.pkt_size::total 19085917 # Cumulative packet size per connected master and slave (bytes)
|
352system.membus.snoops 219 # Total snoops (count)
| 351system.membus.snoops 219 # Total snoops (count)
|
353system.membus.snoop_fanout::samples 296652 # Request fanout histogram
| 352system.membus.snoop_fanout::samples 297178 # Request fanout histogram
|
354system.membus.snoop_fanout::mean 1 # Request fanout histogram 355system.membus.snoop_fanout::stdev 0 # Request fanout histogram 356system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 357system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
| 353system.membus.snoop_fanout::mean 1 # Request fanout histogram 354system.membus.snoop_fanout::stdev 0 # Request fanout histogram 355system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 356system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
358system.membus.snoop_fanout::1 296652 100.00% 100.00% # Request fanout histogram
| 357system.membus.snoop_fanout::1 297178 100.00% 100.00% # Request fanout histogram
|
359system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 360system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 361system.membus.snoop_fanout::min_value 1 # Request fanout histogram 362system.membus.snoop_fanout::max_value 1 # Request fanout histogram
| 358system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 359system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 360system.membus.snoop_fanout::min_value 1 # Request fanout histogram 361system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
363system.membus.snoop_fanout::total 296652 # Request fanout histogram 364system.membus.reqLayer0.occupancy 87220000 # Layer occupancy (ticks)
| 362system.membus.snoop_fanout::total 297178 # Request fanout histogram 363system.membus.reqLayer0.occupancy 87065000 # Layer occupancy (ticks)
|
365system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
| 364system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
366system.membus.reqLayer1.occupancy 11500 # Layer occupancy (ticks)
| 365system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
|
367system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
| 366system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
368system.membus.reqLayer2.occupancy 1713500 # Layer occupancy (ticks)
| 367system.membus.reqLayer2.occupancy 1712000 # Layer occupancy (ticks)
|
369system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
| 368system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
370system.membus.reqLayer5.occupancy 1383760500 # Layer occupancy (ticks)
| 369system.membus.reqLayer5.occupancy 1386132250 # Layer occupancy (ticks)
|
371system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
| 370system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
372system.membus.respLayer2.occupancy 1715299901 # Layer occupancy (ticks)
| 371system.membus.respLayer2.occupancy 1718569157 # Layer occupancy (ticks)
|
373system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
| 372system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
|
374system.membus.respLayer3.occupancy 38332500 # Layer occupancy (ticks)
| 373system.membus.respLayer3.occupancy 38335749 # Layer occupancy (ticks)
|
375system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 376system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 377system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 378system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 379system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 380system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 381system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 382system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 383system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 384system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 385system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 386system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 387system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 388system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 389system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 390system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 391system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 392system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 393system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 394system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 395system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 396system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 397system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 398system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 399system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 400system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 401system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 402system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 403system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 404system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 405system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 406system.realview.ethernet.droppedPackets 0 # number of packets dropped 407system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 408system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 409system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 410system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 411system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 412system.cf0.dma_write_txs 631 # Number of DMA write transactions. 413system.iobus.trans_dist::ReadReq 30195 # Transaction distribution 414system.iobus.trans_dist::ReadResp 30195 # Transaction distribution 415system.iobus.trans_dist::WriteReq 59038 # Transaction distribution 416system.iobus.trans_dist::WriteResp 59038 # Transaction distribution 417system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) 418system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 419system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 420system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 421system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 422system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 423system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 424system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 425system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 426system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 427system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 428system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 429system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 430system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 431system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 432system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 433system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 434system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 435system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 436system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 437system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 438system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) 439system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) 440system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) 441system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) 442system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) 443system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 444system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 445system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 446system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 447system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 448system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 449system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 450system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 451system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 452system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 453system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 454system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 455system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 456system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 457system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 458system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 459system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 460system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 461system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 462system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 463system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) 464system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 465system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 466system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) 467system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) 468system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 469system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) 470system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 471system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 472system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 473system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 474system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 475system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 476system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 477system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) 478system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 479system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 480system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 481system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 482system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 483system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 484system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 485system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 486system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 487system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 488system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 489system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 490system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 491system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 492system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 493system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 494system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 495system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 496system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 497system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 498system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 499system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 500system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 501system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 502system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 503system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 504system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 505system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 506system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
| 374system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 375system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 376system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 377system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 378system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 379system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 380system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 381system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 382system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 383system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 384system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 385system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 386system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 387system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 388system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 389system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 390system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 391system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 392system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 393system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 394system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 395system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 396system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 397system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 398system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 399system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 400system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 401system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 402system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 403system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 404system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 405system.realview.ethernet.droppedPackets 0 # number of packets dropped 406system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 407system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 408system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 409system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 410system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 411system.cf0.dma_write_txs 631 # Number of DMA write transactions. 412system.iobus.trans_dist::ReadReq 30195 # Transaction distribution 413system.iobus.trans_dist::ReadResp 30195 # Transaction distribution 414system.iobus.trans_dist::WriteReq 59038 # Transaction distribution 415system.iobus.trans_dist::WriteResp 59038 # Transaction distribution 416system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) 417system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 418system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 419system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 420system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 421system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 422system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 423system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 424system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 425system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 426system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 427system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 428system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 429system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 430system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 431system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 432system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 433system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 434system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 435system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 436system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 437system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) 438system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) 439system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) 440system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) 441system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) 442system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 443system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 444system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 445system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 446system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 447system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 448system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 449system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 450system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 451system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 452system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 453system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 454system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 455system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 456system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 457system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 458system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 459system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 460system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 461system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 462system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) 463system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 464system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 465system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) 466system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) 467system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 468system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) 469system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 470system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 471system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 472system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 473system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 474system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 475system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 476system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) 477system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 478system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 479system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 480system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 481system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 482system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 483system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 484system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 485system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 486system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 487system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 488system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 489system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 490system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 491system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 492system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 493system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 494system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 495system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 496system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 497system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 498system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 499system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 500system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 501system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 502system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 503system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 504system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 505system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
507system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks)
| 506system.iobus.reqLayer27.occupancy 326584849 # Layer occupancy (ticks)
|
508system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 509system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 510system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 511system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) 512system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
| 507system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 508system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 509system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 510system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) 511system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
513system.iobus.respLayer3.occupancy 36805500 # Layer occupancy (ticks)
| 512system.iobus.respLayer3.occupancy 36809251 # Layer occupancy (ticks)
|
514system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 515system.cpu_clk_domain.clock 500 # Clock period in ticks
| 513system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 514system.cpu_clk_domain.clock 500 # Clock period in ticks
|
516system.cpu.branchPred.lookups 30761849 # Number of BP lookups 517system.cpu.branchPred.condPredicted 16759561 # Number of conditional branches predicted 518system.cpu.branchPred.condIncorrect 2494541 # Number of conditional branches incorrect 519system.cpu.branchPred.BTBLookups 18376022 # Number of BTB lookups 520system.cpu.branchPred.BTBHits 13249221 # Number of BTB hits
| 515system.cpu.branchPred.lookups 30769128 # Number of BP lookups 516system.cpu.branchPred.condPredicted 16730733 # Number of conditional branches predicted 517system.cpu.branchPred.condIncorrect 2480939 # Number of conditional branches incorrect 518system.cpu.branchPred.BTBLookups 18423796 # Number of BTB lookups 519system.cpu.branchPred.BTBHits 13205412 # Number of BTB hits
|
521system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
| 520system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
522system.cpu.branchPred.BTBHitPct 72.100594 # BTB Hit Percentage 523system.cpu.branchPred.usedRAS 7712174 # Number of times the RAS was used to get a target. 524system.cpu.branchPred.RASInCorrect 1491943 # Number of incorrect RAS predictions.
| 521system.cpu.branchPred.BTBHitPct 71.675848 # BTB Hit Percentage 522system.cpu.branchPred.usedRAS 7765211 # Number of times the RAS was used to get a target. 523system.cpu.branchPred.RASInCorrect 1476374 # Number of incorrect RAS predictions.
|
525system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 526system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 527system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 528system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 529system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 530system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 531system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 532system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 533system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 534system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 535system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 536system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 537system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 538system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 539system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 540system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 541system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 542system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 543system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 544system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 545system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 546system.cpu.dtb.inst_hits 0 # ITB inst hits 547system.cpu.dtb.inst_misses 0 # ITB inst misses
| 524system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 525system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 526system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 527system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 528system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 529system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 530system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 531system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 532system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 533system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 534system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 535system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 536system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 537system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 538system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 539system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 540system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 541system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 542system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 543system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 544system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 545system.cpu.dtb.inst_hits 0 # ITB inst hits 546system.cpu.dtb.inst_misses 0 # ITB inst misses
|
548system.cpu.dtb.read_hits 24631139 # DTB read hits 549system.cpu.dtb.read_misses 58263 # DTB read misses 550system.cpu.dtb.write_hits 19400231 # DTB write hits 551system.cpu.dtb.write_misses 6058 # DTB write misses
| 547system.cpu.dtb.read_hits 24572928 # DTB read hits 548system.cpu.dtb.read_misses 58429 # DTB read misses 549system.cpu.dtb.write_hits 19368405 # DTB write hits 550system.cpu.dtb.write_misses 5913 # DTB write misses
|
552system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 553system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 554system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 555system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
| 551system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 552system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 553system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 554system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
556system.cpu.dtb.flush_entries 4344 # Number of entries that have been flushed from TLB 557system.cpu.dtb.align_faults 1249 # Number of TLB faults due to alignment restrictions 558system.cpu.dtb.prefetch_faults 1789 # Number of TLB faults due to prefetch
| 555system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB 556system.cpu.dtb.align_faults 1245 # Number of TLB faults due to alignment restrictions 557system.cpu.dtb.prefetch_faults 1816 # Number of TLB faults due to prefetch
|
559system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
| 558system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
560system.cpu.dtb.perms_faults 740 # Number of TLB faults due to permissions restrictions 561system.cpu.dtb.read_accesses 24689402 # DTB read accesses 562system.cpu.dtb.write_accesses 19406289 # DTB write accesses
| 559system.cpu.dtb.perms_faults 752 # Number of TLB faults due to permissions restrictions 560system.cpu.dtb.read_accesses 24631357 # DTB read accesses 561system.cpu.dtb.write_accesses 19374318 # DTB write accesses
|
563system.cpu.dtb.inst_accesses 0 # ITB inst accesses
| 562system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
564system.cpu.dtb.hits 44031370 # DTB hits 565system.cpu.dtb.misses 64321 # DTB misses 566system.cpu.dtb.accesses 44095691 # DTB accesses
| 563system.cpu.dtb.hits 43941333 # DTB hits 564system.cpu.dtb.misses 64342 # DTB misses 565system.cpu.dtb.accesses 44005675 # DTB accesses
|
567system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 568system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 569system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 570system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 571system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 572system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 573system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 574system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 575system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 576system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 577system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 578system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 579system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 580system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 581system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 582system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 583system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 584system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 585system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 586system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 587system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
| 566system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 567system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 568system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 569system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 570system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 571system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 572system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 573system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 574system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 575system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 576system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 577system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 578system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 579system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 580system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 581system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 582system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 583system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 584system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 585system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 586system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
588system.cpu.itb.inst_hits 57062578 # ITB inst hits 589system.cpu.itb.inst_misses 5424 # ITB inst misses
| 587system.cpu.itb.inst_hits 57038768 # ITB inst hits 588system.cpu.itb.inst_misses 5411 # ITB inst misses
|
590system.cpu.itb.read_hits 0 # DTB read hits 591system.cpu.itb.read_misses 0 # DTB read misses 592system.cpu.itb.write_hits 0 # DTB write hits 593system.cpu.itb.write_misses 0 # DTB write misses 594system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 595system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 596system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 597system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
| 589system.cpu.itb.read_hits 0 # DTB read hits 590system.cpu.itb.read_misses 0 # DTB read misses 591system.cpu.itb.write_hits 0 # DTB write hits 592system.cpu.itb.write_misses 0 # DTB write misses 593system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 594system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 595system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 596system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
598system.cpu.itb.flush_entries 2982 # Number of entries that have been flushed from TLB
| 597system.cpu.itb.flush_entries 2977 # Number of entries that have been flushed from TLB
|
599system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 600system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 601system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
| 598system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 599system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 600system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
602system.cpu.itb.perms_faults 8630 # Number of TLB faults due to permissions restrictions
| 601system.cpu.itb.perms_faults 8664 # Number of TLB faults due to permissions restrictions
|
603system.cpu.itb.read_accesses 0 # DTB read accesses 604system.cpu.itb.write_accesses 0 # DTB write accesses
| 602system.cpu.itb.read_accesses 0 # DTB read accesses 603system.cpu.itb.write_accesses 0 # DTB write accesses
|
605system.cpu.itb.inst_accesses 57068002 # ITB inst accesses 606system.cpu.itb.hits 57062578 # DTB hits 607system.cpu.itb.misses 5424 # DTB misses 608system.cpu.itb.accesses 57068002 # DTB accesses 609system.cpu.numCycles 313219225 # number of cpu cycles simulated
| 604system.cpu.itb.inst_accesses 57044179 # ITB inst accesses 605system.cpu.itb.hits 57038768 # DTB hits 606system.cpu.itb.misses 5411 # DTB misses 607system.cpu.itb.accesses 57044179 # DTB accesses 608system.cpu.numCycles 313347638 # number of cpu cycles simulated
|
610system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 611system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
| 609system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 610system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
612system.cpu.committedInsts 111631963 # Number of instructions committed 613system.cpu.committedOps 134968701 # Number of ops (including micro ops) committed 614system.cpu.discardedOps 7932752 # Number of ops (including micro ops) which were discarded before commit
| 611system.cpu.committedInsts 111365458 # Number of instructions committed 612system.cpu.committedOps 134642914 # Number of ops (including micro ops) committed 613system.cpu.discardedOps 7897593 # Number of ops (including micro ops) which were discarded before commit
|
615system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching
| 614system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching
|
616system.cpu.quiesceCycles 5391228164 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 617system.cpu.cpi 2.805820 # CPI: cycles per instruction 618system.cpu.ipc 0.356402 # IPC: instructions per cycle
| 615system.cpu.quiesceCycles 5391144295 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 616system.cpu.cpi 2.813688 # CPI: cycles per instruction 617system.cpu.ipc 0.355405 # IPC: instructions per cycle
|
619system.cpu.kern.inst.arm 0 # number of arm instructions executed 620system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed
| 618system.cpu.kern.inst.arm 0 # number of arm instructions executed 619system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed
|
621system.cpu.tickCycles 224159041 # Number of cycles that the object actually ticked 622system.cpu.idleCycles 89060184 # Total number of cycles that the object has spent stopped 623system.cpu.icache.tags.replacements 2896816 # number of replacements 624system.cpu.icache.tags.tagsinuse 511.427908 # Cycle average of tags in use 625system.cpu.icache.tags.total_refs 54156207 # Total number of references to valid blocks. 626system.cpu.icache.tags.sampled_refs 2897328 # Sample count of references to valid blocks. 627system.cpu.icache.tags.avg_refs 18.691776 # Average number of references to valid blocks. 628system.cpu.icache.tags.warmup_cycle 15213008250 # Cycle when the warmup percentage was hit. 629system.cpu.icache.tags.occ_blocks::cpu.inst 511.427908 # Average occupied blocks per requestor
| 620system.cpu.tickCycles 224151816 # Number of cycles that the object actually ticked 621system.cpu.idleCycles 89195822 # Total number of cycles that the object has spent stopped 622system.cpu.icache.tags.replacements 2897350 # number of replacements 623system.cpu.icache.tags.tagsinuse 511.427915 # Cycle average of tags in use 624system.cpu.icache.tags.total_refs 54131849 # Total number of references to valid blocks. 625system.cpu.icache.tags.sampled_refs 2897862 # Sample count of references to valid blocks. 626system.cpu.icache.tags.avg_refs 18.679926 # Average number of references to valid blocks. 627system.cpu.icache.tags.warmup_cycle 15213015250 # Cycle when the warmup percentage was hit. 628system.cpu.icache.tags.occ_blocks::cpu.inst 511.427915 # Average occupied blocks per requestor
|
630system.cpu.icache.tags.occ_percent::cpu.inst 0.998883 # Average percentage of cache occupancy 631system.cpu.icache.tags.occ_percent::total 0.998883 # Average percentage of cache occupancy 632system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
| 629system.cpu.icache.tags.occ_percent::cpu.inst 0.998883 # Average percentage of cache occupancy 630system.cpu.icache.tags.occ_percent::total 0.998883 # Average percentage of cache occupancy 631system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
633system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 634system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id 635system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id
| 632system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 633system.cpu.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 634system.cpu.icache.tags.age_task_id_blocks_1024::2 200 # Occupied blocks per task id
|
636system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
| 635system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
637system.cpu.icache.tags.tag_accesses 59950884 # Number of tag accesses 638system.cpu.icache.tags.data_accesses 59950884 # Number of data accesses 639system.cpu.icache.ReadReq_hits::cpu.inst 54156207 # number of ReadReq hits 640system.cpu.icache.ReadReq_hits::total 54156207 # number of ReadReq hits 641system.cpu.icache.demand_hits::cpu.inst 54156207 # number of demand (read+write) hits 642system.cpu.icache.demand_hits::total 54156207 # number of demand (read+write) hits 643system.cpu.icache.overall_hits::cpu.inst 54156207 # number of overall hits 644system.cpu.icache.overall_hits::total 54156207 # number of overall hits 645system.cpu.icache.ReadReq_misses::cpu.inst 2897339 # number of ReadReq misses 646system.cpu.icache.ReadReq_misses::total 2897339 # number of ReadReq misses 647system.cpu.icache.demand_misses::cpu.inst 2897339 # number of demand (read+write) misses 648system.cpu.icache.demand_misses::total 2897339 # number of demand (read+write) misses 649system.cpu.icache.overall_misses::cpu.inst 2897339 # number of overall misses 650system.cpu.icache.overall_misses::total 2897339 # number of overall misses 651system.cpu.icache.ReadReq_miss_latency::cpu.inst 39126605503 # number of ReadReq miss cycles 652system.cpu.icache.ReadReq_miss_latency::total 39126605503 # number of ReadReq miss cycles 653system.cpu.icache.demand_miss_latency::cpu.inst 39126605503 # number of demand (read+write) miss cycles 654system.cpu.icache.demand_miss_latency::total 39126605503 # number of demand (read+write) miss cycles 655system.cpu.icache.overall_miss_latency::cpu.inst 39126605503 # number of overall miss cycles 656system.cpu.icache.overall_miss_latency::total 39126605503 # number of overall miss cycles 657system.cpu.icache.ReadReq_accesses::cpu.inst 57053546 # number of ReadReq accesses(hits+misses) 658system.cpu.icache.ReadReq_accesses::total 57053546 # number of ReadReq accesses(hits+misses) 659system.cpu.icache.demand_accesses::cpu.inst 57053546 # number of demand (read+write) accesses 660system.cpu.icache.demand_accesses::total 57053546 # number of demand (read+write) accesses 661system.cpu.icache.overall_accesses::cpu.inst 57053546 # number of overall (read+write) accesses 662system.cpu.icache.overall_accesses::total 57053546 # number of overall (read+write) accesses 663system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050783 # miss rate for ReadReq accesses 664system.cpu.icache.ReadReq_miss_rate::total 0.050783 # miss rate for ReadReq accesses 665system.cpu.icache.demand_miss_rate::cpu.inst 0.050783 # miss rate for demand accesses 666system.cpu.icache.demand_miss_rate::total 0.050783 # miss rate for demand accesses 667system.cpu.icache.overall_miss_rate::cpu.inst 0.050783 # miss rate for overall accesses 668system.cpu.icache.overall_miss_rate::total 0.050783 # miss rate for overall accesses 669system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.324314 # average ReadReq miss latency 670system.cpu.icache.ReadReq_avg_miss_latency::total 13504.324314 # average ReadReq miss latency 671system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.324314 # average overall miss latency 672system.cpu.icache.demand_avg_miss_latency::total 13504.324314 # average overall miss latency 673system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.324314 # average overall miss latency 674system.cpu.icache.overall_avg_miss_latency::total 13504.324314 # average overall miss latency
| 636system.cpu.icache.tags.tag_accesses 59927594 # Number of tag accesses 637system.cpu.icache.tags.data_accesses 59927594 # Number of data accesses 638system.cpu.icache.ReadReq_hits::cpu.inst 54131849 # number of ReadReq hits 639system.cpu.icache.ReadReq_hits::total 54131849 # number of ReadReq hits 640system.cpu.icache.demand_hits::cpu.inst 54131849 # number of demand (read+write) hits 641system.cpu.icache.demand_hits::total 54131849 # number of demand (read+write) hits 642system.cpu.icache.overall_hits::cpu.inst 54131849 # number of overall hits 643system.cpu.icache.overall_hits::total 54131849 # number of overall hits 644system.cpu.icache.ReadReq_misses::cpu.inst 2897873 # number of ReadReq misses 645system.cpu.icache.ReadReq_misses::total 2897873 # number of ReadReq misses 646system.cpu.icache.demand_misses::cpu.inst 2897873 # number of demand (read+write) misses 647system.cpu.icache.demand_misses::total 2897873 # number of demand (read+write) misses 648system.cpu.icache.overall_misses::cpu.inst 2897873 # number of overall misses 649system.cpu.icache.overall_misses::total 2897873 # number of overall misses 650system.cpu.icache.ReadReq_miss_latency::cpu.inst 39140139756 # number of ReadReq miss cycles 651system.cpu.icache.ReadReq_miss_latency::total 39140139756 # number of ReadReq miss cycles 652system.cpu.icache.demand_miss_latency::cpu.inst 39140139756 # number of demand (read+write) miss cycles 653system.cpu.icache.demand_miss_latency::total 39140139756 # number of demand (read+write) miss cycles 654system.cpu.icache.overall_miss_latency::cpu.inst 39140139756 # number of overall miss cycles 655system.cpu.icache.overall_miss_latency::total 39140139756 # number of overall miss cycles 656system.cpu.icache.ReadReq_accesses::cpu.inst 57029722 # number of ReadReq accesses(hits+misses) 657system.cpu.icache.ReadReq_accesses::total 57029722 # number of ReadReq accesses(hits+misses) 658system.cpu.icache.demand_accesses::cpu.inst 57029722 # number of demand (read+write) accesses 659system.cpu.icache.demand_accesses::total 57029722 # number of demand (read+write) accesses 660system.cpu.icache.overall_accesses::cpu.inst 57029722 # number of overall (read+write) accesses 661system.cpu.icache.overall_accesses::total 57029722 # number of overall (read+write) accesses 662system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050813 # miss rate for ReadReq accesses 663system.cpu.icache.ReadReq_miss_rate::total 0.050813 # miss rate for ReadReq accesses 664system.cpu.icache.demand_miss_rate::cpu.inst 0.050813 # miss rate for demand accesses 665system.cpu.icache.demand_miss_rate::total 0.050813 # miss rate for demand accesses 666system.cpu.icache.overall_miss_rate::cpu.inst 0.050813 # miss rate for overall accesses 667system.cpu.icache.overall_miss_rate::total 0.050813 # miss rate for overall accesses 668system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.506240 # average ReadReq miss latency 669system.cpu.icache.ReadReq_avg_miss_latency::total 13506.506240 # average ReadReq miss latency 670system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.506240 # average overall miss latency 671system.cpu.icache.demand_avg_miss_latency::total 13506.506240 # average overall miss latency 672system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.506240 # average overall miss latency 673system.cpu.icache.overall_avg_miss_latency::total 13506.506240 # average overall miss latency
|
675system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 676system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 677system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 678system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 679system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 680system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 681system.cpu.icache.fast_writes 0 # number of fast writes performed 682system.cpu.icache.cache_copies 0 # number of cache copies performed
| 674system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 675system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 676system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 677system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 678system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 679system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 680system.cpu.icache.fast_writes 0 # number of fast writes performed 681system.cpu.icache.cache_copies 0 # number of cache copies performed
|
683system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897339 # number of ReadReq MSHR misses 684system.cpu.icache.ReadReq_mshr_misses::total 2897339 # number of ReadReq MSHR misses 685system.cpu.icache.demand_mshr_misses::cpu.inst 2897339 # number of demand (read+write) MSHR misses 686system.cpu.icache.demand_mshr_misses::total 2897339 # number of demand (read+write) MSHR misses 687system.cpu.icache.overall_mshr_misses::cpu.inst 2897339 # number of overall MSHR misses 688system.cpu.icache.overall_mshr_misses::total 2897339 # number of overall MSHR misses 689system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33322439497 # number of ReadReq MSHR miss cycles 690system.cpu.icache.ReadReq_mshr_miss_latency::total 33322439497 # number of ReadReq MSHR miss cycles 691system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33322439497 # number of demand (read+write) MSHR miss cycles 692system.cpu.icache.demand_mshr_miss_latency::total 33322439497 # number of demand (read+write) MSHR miss cycles 693system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33322439497 # number of overall MSHR miss cycles 694system.cpu.icache.overall_mshr_miss_latency::total 33322439497 # number of overall MSHR miss cycles 695system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 222173750 # number of ReadReq MSHR uncacheable cycles 696system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 222173750 # number of ReadReq MSHR uncacheable cycles 697system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 222173750 # number of overall MSHR uncacheable cycles 698system.cpu.icache.overall_mshr_uncacheable_latency::total 222173750 # number of overall MSHR uncacheable cycles 699system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050783 # mshr miss rate for ReadReq accesses 700system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050783 # mshr miss rate for ReadReq accesses 701system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050783 # mshr miss rate for demand accesses 702system.cpu.icache.demand_mshr_miss_rate::total 0.050783 # mshr miss rate for demand accesses 703system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050783 # mshr miss rate for overall accesses 704system.cpu.icache.overall_mshr_miss_rate::total 0.050783 # mshr miss rate for overall accesses 705system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11501.049583 # average ReadReq mshr miss latency 706system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11501.049583 # average ReadReq mshr miss latency 707system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11501.049583 # average overall mshr miss latency 708system.cpu.icache.demand_avg_mshr_miss_latency::total 11501.049583 # average overall mshr miss latency 709system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11501.049583 # average overall mshr miss latency 710system.cpu.icache.overall_avg_mshr_miss_latency::total 11501.049583 # average overall mshr miss latency
| 682system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897873 # number of ReadReq MSHR misses 683system.cpu.icache.ReadReq_mshr_misses::total 2897873 # number of ReadReq MSHR misses 684system.cpu.icache.demand_mshr_misses::cpu.inst 2897873 # number of demand (read+write) MSHR misses 685system.cpu.icache.demand_mshr_misses::total 2897873 # number of demand (read+write) MSHR misses 686system.cpu.icache.overall_mshr_misses::cpu.inst 2897873 # number of overall MSHR misses 687system.cpu.icache.overall_mshr_misses::total 2897873 # number of overall MSHR misses 688system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33334905244 # number of ReadReq MSHR miss cycles 689system.cpu.icache.ReadReq_mshr_miss_latency::total 33334905244 # number of ReadReq MSHR miss cycles 690system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33334905244 # number of demand (read+write) MSHR miss cycles 691system.cpu.icache.demand_mshr_miss_latency::total 33334905244 # number of demand (read+write) MSHR miss cycles 692system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33334905244 # number of overall MSHR miss cycles 693system.cpu.icache.overall_mshr_miss_latency::total 33334905244 # number of overall MSHR miss cycles 694system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 222062750 # number of ReadReq MSHR uncacheable cycles 695system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 222062750 # number of ReadReq MSHR uncacheable cycles 696system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 222062750 # number of overall MSHR uncacheable cycles 697system.cpu.icache.overall_mshr_uncacheable_latency::total 222062750 # number of overall MSHR uncacheable cycles 698system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050813 # mshr miss rate for ReadReq accesses 699system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050813 # mshr miss rate for ReadReq accesses 700system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050813 # mshr miss rate for demand accesses 701system.cpu.icache.demand_mshr_miss_rate::total 0.050813 # mshr miss rate for demand accesses 702system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050813 # mshr miss rate for overall accesses 703system.cpu.icache.overall_mshr_miss_rate::total 0.050813 # mshr miss rate for overall accesses 704system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11503.231937 # average ReadReq mshr miss latency 705system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11503.231937 # average ReadReq mshr miss latency 706system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11503.231937 # average overall mshr miss latency 707system.cpu.icache.demand_avg_mshr_miss_latency::total 11503.231937 # average overall mshr miss latency 708system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11503.231937 # average overall mshr miss latency 709system.cpu.icache.overall_avg_mshr_miss_latency::total 11503.231937 # average overall mshr miss latency
|
711system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 712system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 713system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 714system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 715system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
| 710system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 711system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 712system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 713system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 714system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
716system.cpu.toL2Bus.trans_dist::ReadReq 3575425 # Transaction distribution 717system.cpu.toL2Bus.trans_dist::ReadResp 3575329 # Transaction distribution
| 715system.cpu.toL2Bus.trans_dist::ReadReq 3575187 # Transaction distribution 716system.cpu.toL2Bus.trans_dist::ReadResp 3575091 # Transaction distribution
|
718system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution 719system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution
| 717system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution 718system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution
|
720system.cpu.toL2Bus.trans_dist::Writeback 697864 # Transaction distribution 721system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution 722system.cpu.toL2Bus.trans_dist::UpgradeReq 2819 # Transaction distribution
| 719system.cpu.toL2Bus.trans_dist::Writeback 697424 # Transaction distribution 720system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36234 # Transaction distribution 721system.cpu.toL2Bus.trans_dist::UpgradeReq 2818 # Transaction distribution
|
723system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
| 722system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
724system.cpu.toL2Bus.trans_dist::UpgradeResp 2821 # Transaction distribution 725system.cpu.toL2Bus.trans_dist::ReadExReq 295691 # Transaction distribution 726system.cpu.toL2Bus.trans_dist::ReadExResp 295691 # Transaction distribution 727system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5800652 # Packet count per connected master and slave (bytes) 728system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2504517 # Packet count per connected master and slave (bytes) 729system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15250 # Packet count per connected master and slave (bytes) 730system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 156288 # Packet count per connected master and slave (bytes) 731system.cpu.toL2Bus.pkt_count::total 8476707 # Packet count per connected master and slave (bytes) 732system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185619904 # Cumulative packet size per connected master and slave (bytes) 733system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98723549 # Cumulative packet size per connected master and slave (bytes) 734system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18892 # Cumulative packet size per connected master and slave (bytes) 735system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 276412 # Cumulative packet size per connected master and slave (bytes) 736system.cpu.toL2Bus.pkt_size::total 284638757 # Cumulative packet size per connected master and slave (bytes) 737system.cpu.toL2Bus.snoops 60515 # Total snoops (count) 738system.cpu.toL2Bus.snoop_fanout::samples 4573888 # Request fanout histogram 739system.cpu.toL2Bus.snoop_fanout::mean 5.007972 # Request fanout histogram 740system.cpu.toL2Bus.snoop_fanout::stdev 0.088927 # Request fanout histogram
| 723system.cpu.toL2Bus.trans_dist::UpgradeResp 2820 # Transaction distribution 724system.cpu.toL2Bus.trans_dist::ReadExReq 295755 # Transaction distribution 725system.cpu.toL2Bus.trans_dist::ReadExResp 295755 # Transaction distribution 726system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5801712 # Packet count per connected master and slave (bytes) 727system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2503299 # Packet count per connected master and slave (bytes) 728system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15293 # Packet count per connected master and slave (bytes) 729system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 155961 # Packet count per connected master and slave (bytes) 730system.cpu.toL2Bus.pkt_count::total 8476265 # Packet count per connected master and slave (bytes) 731system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185653696 # Cumulative packet size per connected master and slave (bytes) 732system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98670557 # Cumulative packet size per connected master and slave (bytes) 733system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 19168 # Cumulative packet size per connected master and slave (bytes) 734system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 276272 # Cumulative packet size per connected master and slave (bytes) 735system.cpu.toL2Bus.pkt_size::total 284619693 # Cumulative packet size per connected master and slave (bytes) 736system.cpu.toL2Bus.snoops 60174 # Total snoops (count) 737system.cpu.toL2Bus.snoop_fanout::samples 4573282 # Request fanout histogram 738system.cpu.toL2Bus.snoop_fanout::mean 5.007974 # Request fanout histogram 739system.cpu.toL2Bus.snoop_fanout::stdev 0.088941 # Request fanout histogram
|
741system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 742system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 743system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 744system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 745system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 746system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
| 740system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 741system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 742system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 743system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 744system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 745system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
747system.cpu.toL2Bus.snoop_fanout::5 4537427 99.20% 99.20% # Request fanout histogram 748system.cpu.toL2Bus.snoop_fanout::6 36461 0.80% 100.00% # Request fanout histogram
| 746system.cpu.toL2Bus.snoop_fanout::5 4536814 99.20% 99.20% # Request fanout histogram 747system.cpu.toL2Bus.snoop_fanout::6 36468 0.80% 100.00% # Request fanout histogram
|
749system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 750system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 751system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
| 748system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 749system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 750system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
752system.cpu.toL2Bus.snoop_fanout::total 4573888 # Request fanout histogram 753system.cpu.toL2Bus.reqLayer0.occupancy 3011299661 # Layer occupancy (ticks)
| 751system.cpu.toL2Bus.snoop_fanout::total 4573282 # Request fanout histogram 752system.cpu.toL2Bus.reqLayer0.occupancy 3010555155 # Layer occupancy (ticks)
|
754system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 755system.cpu.toL2Bus.snoopLayer0.occupancy 208500 # Layer occupancy (ticks) 756system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
| 753system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 754system.cpu.toL2Bus.snoopLayer0.occupancy 208500 # Layer occupancy (ticks) 755system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
757system.cpu.toL2Bus.respLayer0.occupancy 4355950753 # Layer occupancy (ticks)
| 756system.cpu.toL2Bus.respLayer0.occupancy 4356749506 # Layer occupancy (ticks)
|
758system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
| 757system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
|
759system.cpu.toL2Bus.respLayer1.occupancy 1340010456 # Layer occupancy (ticks)
| 758system.cpu.toL2Bus.respLayer1.occupancy 1339516197 # Layer occupancy (ticks)
|
760system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
| 759system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
761system.cpu.toL2Bus.respLayer2.occupancy 10527250 # Layer occupancy (ticks)
| 760system.cpu.toL2Bus.respLayer2.occupancy 10501000 # Layer occupancy (ticks)
|
762system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
| 761system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
763system.cpu.toL2Bus.respLayer3.occupancy 87188750 # Layer occupancy (ticks)
| 762system.cpu.toL2Bus.respLayer3.occupancy 86895250 # Layer occupancy (ticks)
|
764system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
| 763system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
765system.cpu.l2cache.tags.replacements 97184 # number of replacements 766system.cpu.l2cache.tags.tagsinuse 65075.712435 # Cycle average of tags in use 767system.cpu.l2cache.tags.total_refs 4041226 # Total number of references to valid blocks. 768system.cpu.l2cache.tags.sampled_refs 162444 # Sample count of references to valid blocks. 769system.cpu.l2cache.tags.avg_refs 24.877656 # Average number of references to valid blocks. 770system.cpu.l2cache.tags.warmup_cycle 93442219500 # Cycle when the warmup percentage was hit. 771system.cpu.l2cache.tags.occ_blocks::writebacks 47462.018914 # Average occupied blocks per requestor 772system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 55.401726 # Average occupied blocks per requestor 773system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.009455 # Average occupied blocks per requestor 774system.cpu.l2cache.tags.occ_blocks::cpu.inst 17558.282340 # Average occupied blocks per requestor 775system.cpu.l2cache.tags.occ_percent::writebacks 0.724213 # Average percentage of cache occupancy 776system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000845 # Average percentage of cache occupancy
| 764system.cpu.l2cache.tags.replacements 97514 # number of replacements 765system.cpu.l2cache.tags.tagsinuse 65073.344541 # Cycle average of tags in use 766system.cpu.l2cache.tags.total_refs 4041263 # Total number of references to valid blocks. 767system.cpu.l2cache.tags.sampled_refs 162774 # Sample count of references to valid blocks. 768system.cpu.l2cache.tags.avg_refs 24.827448 # Average number of references to valid blocks. 769system.cpu.l2cache.tags.warmup_cycle 93462601500 # Cycle when the warmup percentage was hit. 770system.cpu.l2cache.tags.occ_blocks::writebacks 47542.577135 # Average occupied blocks per requestor 771system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 54.389093 # Average occupied blocks per requestor 772system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.009502 # Average occupied blocks per requestor 773system.cpu.l2cache.tags.occ_blocks::cpu.inst 17476.368811 # Average occupied blocks per requestor 774system.cpu.l2cache.tags.occ_percent::writebacks 0.725442 # Average percentage of cache occupancy 775system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000830 # Average percentage of cache occupancy
|
777system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
| 776system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
778system.cpu.l2cache.tags.occ_percent::cpu.inst 0.267918 # Average percentage of cache occupancy 779system.cpu.l2cache.tags.occ_percent::total 0.992977 # Average percentage of cache occupancy 780system.cpu.l2cache.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id 781system.cpu.l2cache.tags.occ_task_id_blocks::1024 65213 # Occupied blocks per task id 782system.cpu.l2cache.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id 783system.cpu.l2cache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 784system.cpu.l2cache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id 785system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2308 # Occupied blocks per task id 786system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6976 # Occupied blocks per task id 787system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55798 # Occupied blocks per task id 788system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id 789system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995071 # Percentage of cache occupancy per task id 790system.cpu.l2cache.tags.tag_accesses 36570721 # Number of tag accesses 791system.cpu.l2cache.tags.data_accesses 36570721 # Number of data accesses 792system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69000 # number of ReadReq hits 793system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4721 # number of ReadReq hits 794system.cpu.l2cache.ReadReq_hits::cpu.inst 3405800 # number of ReadReq hits 795system.cpu.l2cache.ReadReq_hits::total 3479521 # number of ReadReq hits 796system.cpu.l2cache.Writeback_hits::writebacks 697864 # number of Writeback hits 797system.cpu.l2cache.Writeback_hits::total 697864 # number of Writeback hits
| 777system.cpu.l2cache.tags.occ_percent::cpu.inst 0.266668 # Average percentage of cache occupancy 778system.cpu.l2cache.tags.occ_percent::total 0.992940 # Average percentage of cache occupancy 779system.cpu.l2cache.tags.occ_task_id_blocks::1023 44 # Occupied blocks per task id 780system.cpu.l2cache.tags.occ_task_id_blocks::1024 65216 # Occupied blocks per task id 781system.cpu.l2cache.tags.age_task_id_blocks_1023::4 44 # Occupied blocks per task id 782system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 783system.cpu.l2cache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id 784system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2322 # Occupied blocks per task id 785system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6967 # Occupied blocks per task id 786system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55801 # Occupied blocks per task id 787system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id 788system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995117 # Percentage of cache occupancy per task id 789system.cpu.l2cache.tags.tag_accesses 36568997 # Number of tag accesses 790system.cpu.l2cache.tags.data_accesses 36568997 # Number of data accesses 791system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68967 # number of ReadReq hits 792system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4789 # number of ReadReq hits 793system.cpu.l2cache.ReadReq_hits::cpu.inst 3405854 # number of ReadReq hits 794system.cpu.l2cache.ReadReq_hits::total 3479610 # number of ReadReq hits 795system.cpu.l2cache.Writeback_hits::writebacks 697424 # number of Writeback hits 796system.cpu.l2cache.Writeback_hits::total 697424 # number of Writeback hits
|
798system.cpu.l2cache.UpgradeReq_hits::cpu.inst 45 # number of UpgradeReq hits 799system.cpu.l2cache.UpgradeReq_hits::total 45 # number of UpgradeReq hits
| 797system.cpu.l2cache.UpgradeReq_hits::cpu.inst 45 # number of UpgradeReq hits 798system.cpu.l2cache.UpgradeReq_hits::total 45 # number of UpgradeReq hits
|
800system.cpu.l2cache.ReadExReq_hits::cpu.inst 164314 # number of ReadExReq hits 801system.cpu.l2cache.ReadExReq_hits::total 164314 # number of ReadExReq hits 802system.cpu.l2cache.demand_hits::cpu.dtb.walker 69000 # number of demand (read+write) hits 803system.cpu.l2cache.demand_hits::cpu.itb.walker 4721 # number of demand (read+write) hits 804system.cpu.l2cache.demand_hits::cpu.inst 3570114 # number of demand (read+write) hits 805system.cpu.l2cache.demand_hits::total 3643835 # number of demand (read+write) hits 806system.cpu.l2cache.overall_hits::cpu.dtb.walker 69000 # number of overall hits 807system.cpu.l2cache.overall_hits::cpu.itb.walker 4721 # number of overall hits 808system.cpu.l2cache.overall_hits::cpu.inst 3570114 # number of overall hits 809system.cpu.l2cache.overall_hits::total 3643835 # number of overall hits 810system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 103 # number of ReadReq misses 811system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 812system.cpu.l2cache.ReadReq_misses::cpu.inst 37510 # number of ReadReq misses 813system.cpu.l2cache.ReadReq_misses::total 37615 # number of ReadReq misses 814system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2774 # number of UpgradeReq misses 815system.cpu.l2cache.UpgradeReq_misses::total 2774 # number of UpgradeReq misses
| 799system.cpu.l2cache.ReadExReq_hits::cpu.inst 164068 # number of ReadExReq hits 800system.cpu.l2cache.ReadExReq_hits::total 164068 # number of ReadExReq hits 801system.cpu.l2cache.demand_hits::cpu.dtb.walker 68967 # number of demand (read+write) hits 802system.cpu.l2cache.demand_hits::cpu.itb.walker 4789 # number of demand (read+write) hits 803system.cpu.l2cache.demand_hits::cpu.inst 3569922 # number of demand (read+write) hits 804system.cpu.l2cache.demand_hits::total 3643678 # number of demand (read+write) hits 805system.cpu.l2cache.overall_hits::cpu.dtb.walker 68967 # number of overall hits 806system.cpu.l2cache.overall_hits::cpu.itb.walker 4789 # number of overall hits 807system.cpu.l2cache.overall_hits::cpu.inst 3569922 # number of overall hits 808system.cpu.l2cache.overall_hits::total 3643678 # number of overall hits 809system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 101 # number of ReadReq misses 810system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses 811system.cpu.l2cache.ReadReq_misses::cpu.inst 37534 # number of ReadReq misses 812system.cpu.l2cache.ReadReq_misses::total 37638 # number of ReadReq misses 813system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2773 # number of UpgradeReq misses 814system.cpu.l2cache.UpgradeReq_misses::total 2773 # number of UpgradeReq misses
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816system.cpu.l2cache.SCUpgradeReq_misses::cpu.inst 2 # number of SCUpgradeReq misses 817system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
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818system.cpu.l2cache.ReadExReq_misses::cpu.inst 131377 # number of ReadExReq misses 819system.cpu.l2cache.ReadExReq_misses::total 131377 # number of ReadExReq misses 820system.cpu.l2cache.demand_misses::cpu.dtb.walker 103 # number of demand (read+write) misses 821system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 822system.cpu.l2cache.demand_misses::cpu.inst 168887 # number of demand (read+write) misses 823system.cpu.l2cache.demand_misses::total 168992 # number of demand (read+write) misses 824system.cpu.l2cache.overall_misses::cpu.dtb.walker 103 # number of overall misses 825system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 826system.cpu.l2cache.overall_misses::cpu.inst 168887 # number of overall misses 827system.cpu.l2cache.overall_misses::total 168992 # number of overall misses 828system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 7796000 # number of ReadReq miss cycles 829system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 163250 # number of ReadReq miss cycles 830system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2760094000 # number of ReadReq miss cycles 831system.cpu.l2cache.ReadReq_miss_latency::total 2768053250 # number of ReadReq miss cycles 832system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 998957 # number of UpgradeReq miss cycles 833system.cpu.l2cache.UpgradeReq_miss_latency::total 998957 # number of UpgradeReq miss cycles 834system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst 46498 # number of SCUpgradeReq miss cycles 835system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46498 # number of SCUpgradeReq miss cycles 836system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9221968427 # number of ReadExReq miss cycles 837system.cpu.l2cache.ReadExReq_miss_latency::total 9221968427 # number of ReadExReq miss cycles 838system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 7796000 # number of demand (read+write) miss cycles 839system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 163250 # number of demand (read+write) miss cycles 840system.cpu.l2cache.demand_miss_latency::cpu.inst 11982062427 # number of demand (read+write) miss cycles 841system.cpu.l2cache.demand_miss_latency::total 11990021677 # number of demand (read+write) miss cycles 842system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 7796000 # number of overall miss cycles 843system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 163250 # number of overall miss cycles 844system.cpu.l2cache.overall_miss_latency::cpu.inst 11982062427 # number of overall miss cycles 845system.cpu.l2cache.overall_miss_latency::total 11990021677 # number of overall miss cycles 846system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69103 # number of ReadReq accesses(hits+misses) 847system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4723 # number of ReadReq accesses(hits+misses) 848system.cpu.l2cache.ReadReq_accesses::cpu.inst 3443310 # number of ReadReq accesses(hits+misses) 849system.cpu.l2cache.ReadReq_accesses::total 3517136 # number of ReadReq accesses(hits+misses) 850system.cpu.l2cache.Writeback_accesses::writebacks 697864 # number of Writeback accesses(hits+misses) 851system.cpu.l2cache.Writeback_accesses::total 697864 # number of Writeback accesses(hits+misses) 852system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2819 # number of UpgradeReq accesses(hits+misses) 853system.cpu.l2cache.UpgradeReq_accesses::total 2819 # number of UpgradeReq accesses(hits+misses)
| 817system.cpu.l2cache.ReadExReq_misses::cpu.inst 131687 # number of ReadExReq misses 818system.cpu.l2cache.ReadExReq_misses::total 131687 # number of ReadExReq misses 819system.cpu.l2cache.demand_misses::cpu.dtb.walker 101 # number of demand (read+write) misses 820system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses 821system.cpu.l2cache.demand_misses::cpu.inst 169221 # number of demand (read+write) misses 822system.cpu.l2cache.demand_misses::total 169325 # number of demand (read+write) misses 823system.cpu.l2cache.overall_misses::cpu.dtb.walker 101 # number of overall misses 824system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses 825system.cpu.l2cache.overall_misses::cpu.inst 169221 # number of overall misses 826system.cpu.l2cache.overall_misses::total 169325 # number of overall misses 827system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 7803500 # number of ReadReq miss cycles 828system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 223500 # number of ReadReq miss cycles 829system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2773793750 # number of ReadReq miss cycles 830system.cpu.l2cache.ReadReq_miss_latency::total 2781820750 # number of ReadReq miss cycles 831system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 1024956 # number of UpgradeReq miss cycles 832system.cpu.l2cache.UpgradeReq_miss_latency::total 1024956 # number of UpgradeReq miss cycles 833system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst 46998 # number of SCUpgradeReq miss cycles 834system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles 835system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9263576682 # number of ReadExReq miss cycles 836system.cpu.l2cache.ReadExReq_miss_latency::total 9263576682 # number of ReadExReq miss cycles 837system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 7803500 # number of demand (read+write) miss cycles 838system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 223500 # number of demand (read+write) miss cycles 839system.cpu.l2cache.demand_miss_latency::cpu.inst 12037370432 # number of demand (read+write) miss cycles 840system.cpu.l2cache.demand_miss_latency::total 12045397432 # number of demand (read+write) miss cycles 841system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 7803500 # number of overall miss cycles 842system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 223500 # number of overall miss cycles 843system.cpu.l2cache.overall_miss_latency::cpu.inst 12037370432 # number of overall miss cycles 844system.cpu.l2cache.overall_miss_latency::total 12045397432 # number of overall miss cycles 845system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69068 # number of ReadReq accesses(hits+misses) 846system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4792 # number of ReadReq accesses(hits+misses) 847system.cpu.l2cache.ReadReq_accesses::cpu.inst 3443388 # number of ReadReq accesses(hits+misses) 848system.cpu.l2cache.ReadReq_accesses::total 3517248 # number of ReadReq accesses(hits+misses) 849system.cpu.l2cache.Writeback_accesses::writebacks 697424 # number of Writeback accesses(hits+misses) 850system.cpu.l2cache.Writeback_accesses::total 697424 # number of Writeback accesses(hits+misses) 851system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2818 # number of UpgradeReq accesses(hits+misses) 852system.cpu.l2cache.UpgradeReq_accesses::total 2818 # number of UpgradeReq accesses(hits+misses)
|
854system.cpu.l2cache.SCUpgradeReq_accesses::cpu.inst 2 # number of SCUpgradeReq accesses(hits+misses) 855system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
| 853system.cpu.l2cache.SCUpgradeReq_accesses::cpu.inst 2 # number of SCUpgradeReq accesses(hits+misses) 854system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
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856system.cpu.l2cache.ReadExReq_accesses::cpu.inst 295691 # number of ReadExReq accesses(hits+misses) 857system.cpu.l2cache.ReadExReq_accesses::total 295691 # number of ReadExReq accesses(hits+misses) 858system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69103 # number of demand (read+write) accesses 859system.cpu.l2cache.demand_accesses::cpu.itb.walker 4723 # number of demand (read+write) accesses 860system.cpu.l2cache.demand_accesses::cpu.inst 3739001 # number of demand (read+write) accesses 861system.cpu.l2cache.demand_accesses::total 3812827 # number of demand (read+write) accesses 862system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69103 # number of overall (read+write) accesses 863system.cpu.l2cache.overall_accesses::cpu.itb.walker 4723 # number of overall (read+write) accesses 864system.cpu.l2cache.overall_accesses::cpu.inst 3739001 # number of overall (read+write) accesses 865system.cpu.l2cache.overall_accesses::total 3812827 # number of overall (read+write) accesses 866system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001491 # miss rate for ReadReq accesses 867system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000423 # miss rate for ReadReq accesses 868system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010894 # miss rate for ReadReq accesses 869system.cpu.l2cache.ReadReq_miss_rate::total 0.010695 # miss rate for ReadReq accesses 870system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.984037 # miss rate for UpgradeReq accesses 871system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984037 # miss rate for UpgradeReq accesses
| 855system.cpu.l2cache.ReadExReq_accesses::cpu.inst 295755 # number of ReadExReq accesses(hits+misses) 856system.cpu.l2cache.ReadExReq_accesses::total 295755 # number of ReadExReq accesses(hits+misses) 857system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69068 # number of demand (read+write) accesses 858system.cpu.l2cache.demand_accesses::cpu.itb.walker 4792 # number of demand (read+write) accesses 859system.cpu.l2cache.demand_accesses::cpu.inst 3739143 # number of demand (read+write) accesses 860system.cpu.l2cache.demand_accesses::total 3813003 # number of demand (read+write) accesses 861system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69068 # number of overall (read+write) accesses 862system.cpu.l2cache.overall_accesses::cpu.itb.walker 4792 # number of overall (read+write) accesses 863system.cpu.l2cache.overall_accesses::cpu.inst 3739143 # number of overall (read+write) accesses 864system.cpu.l2cache.overall_accesses::total 3813003 # number of overall (read+write) accesses 865system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001462 # miss rate for ReadReq accesses 866system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000626 # miss rate for ReadReq accesses 867system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010900 # miss rate for ReadReq accesses 868system.cpu.l2cache.ReadReq_miss_rate::total 0.010701 # miss rate for ReadReq accesses 869system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.984031 # miss rate for UpgradeReq accesses 870system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984031 # miss rate for UpgradeReq accesses
|
872system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst 1 # miss rate for SCUpgradeReq accesses 873system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
| 871system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst 1 # miss rate for SCUpgradeReq accesses 872system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
874system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.444305 # miss rate for ReadExReq accesses 875system.cpu.l2cache.ReadExReq_miss_rate::total 0.444305 # miss rate for ReadExReq accesses 876system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001491 # miss rate for demand accesses 877system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000423 # miss rate for demand accesses 878system.cpu.l2cache.demand_miss_rate::cpu.inst 0.045169 # miss rate for demand accesses 879system.cpu.l2cache.demand_miss_rate::total 0.044322 # miss rate for demand accesses 880system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001491 # miss rate for overall accesses 881system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000423 # miss rate for overall accesses 882system.cpu.l2cache.overall_miss_rate::cpu.inst 0.045169 # miss rate for overall accesses 883system.cpu.l2cache.overall_miss_rate::total 0.044322 # miss rate for overall accesses 884system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 75689.320388 # average ReadReq miss latency 885system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 81625 # average ReadReq miss latency 886system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73582.884564 # average ReadReq miss latency 887system.cpu.l2cache.ReadReq_avg_miss_latency::total 73589.080154 # average ReadReq miss latency 888system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 360.114275 # average UpgradeReq miss latency 889system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 360.114275 # average UpgradeReq miss latency 890system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst 23249 # average SCUpgradeReq miss latency 891system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23249 # average SCUpgradeReq miss latency 892system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70194.694863 # average ReadExReq miss latency 893system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70194.694863 # average ReadExReq miss latency 894system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 75689.320388 # average overall miss latency 895system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 81625 # average overall miss latency 896system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70947.215754 # average overall miss latency 897system.cpu.l2cache.demand_avg_miss_latency::total 70950.232419 # average overall miss latency 898system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 75689.320388 # average overall miss latency 899system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 81625 # average overall miss latency 900system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70947.215754 # average overall miss latency 901system.cpu.l2cache.overall_avg_miss_latency::total 70950.232419 # average overall miss latency
| 873system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.445257 # miss rate for ReadExReq accesses 874system.cpu.l2cache.ReadExReq_miss_rate::total 0.445257 # miss rate for ReadExReq accesses 875system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001462 # miss rate for demand accesses 876system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000626 # miss rate for demand accesses 877system.cpu.l2cache.demand_miss_rate::cpu.inst 0.045257 # miss rate for demand accesses 878system.cpu.l2cache.demand_miss_rate::total 0.044407 # miss rate for demand accesses 879system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001462 # miss rate for overall accesses 880system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000626 # miss rate for overall accesses 881system.cpu.l2cache.overall_miss_rate::cpu.inst 0.045257 # miss rate for overall accesses 882system.cpu.l2cache.overall_miss_rate::total 0.044407 # miss rate for overall accesses 883system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77262.376238 # average ReadReq miss latency 884system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74500 # average ReadReq miss latency 885system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73900.829914 # average ReadReq miss latency 886system.cpu.l2cache.ReadReq_avg_miss_latency::total 73909.898241 # average ReadReq miss latency 887system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 369.619906 # average UpgradeReq miss latency 888system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 369.619906 # average UpgradeReq miss latency 889system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst 23499 # average SCUpgradeReq miss latency 890system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23499 # average SCUpgradeReq miss latency 891system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70345.415128 # average ReadExReq miss latency 892system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70345.415128 # average ReadExReq miss latency 893system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77262.376238 # average overall miss latency 894system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74500 # average overall miss latency 895system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71134.022562 # average overall miss latency 896system.cpu.l2cache.demand_avg_miss_latency::total 71137.737676 # average overall miss latency 897system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77262.376238 # average overall miss latency 898system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74500 # average overall miss latency 899system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71134.022562 # average overall miss latency 900system.cpu.l2cache.overall_avg_miss_latency::total 71137.737676 # average overall miss latency
|
902system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 903system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 904system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 905system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 906system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 907system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 908system.cpu.l2cache.fast_writes 0 # number of fast writes performed 909system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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|
910system.cpu.l2cache.writebacks::writebacks 88588 # number of writebacks 911system.cpu.l2cache.writebacks::total 88588 # number of writebacks 912system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 165 # number of ReadReq MSHR hits 913system.cpu.l2cache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits 914system.cpu.l2cache.demand_mshr_hits::cpu.inst 165 # number of demand (read+write) MSHR hits 915system.cpu.l2cache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits 916system.cpu.l2cache.overall_mshr_hits::cpu.inst 165 # number of overall MSHR hits 917system.cpu.l2cache.overall_mshr_hits::total 165 # number of overall MSHR hits 918system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 103 # number of ReadReq MSHR misses 919system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 920system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 37345 # number of ReadReq MSHR misses 921system.cpu.l2cache.ReadReq_mshr_misses::total 37450 # number of ReadReq MSHR misses 922system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2774 # number of UpgradeReq MSHR misses 923system.cpu.l2cache.UpgradeReq_mshr_misses::total 2774 # number of UpgradeReq MSHR misses
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924system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst 2 # number of SCUpgradeReq MSHR misses 925system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
| 923system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst 2 # number of SCUpgradeReq MSHR misses 924system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
|
926system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 131377 # number of ReadExReq MSHR misses 927system.cpu.l2cache.ReadExReq_mshr_misses::total 131377 # number of ReadExReq MSHR misses 928system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 103 # number of demand (read+write) MSHR misses 929system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 930system.cpu.l2cache.demand_mshr_misses::cpu.inst 168722 # number of demand (read+write) MSHR misses 931system.cpu.l2cache.demand_mshr_misses::total 168827 # number of demand (read+write) MSHR misses 932system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 103 # number of overall MSHR misses 933system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 934system.cpu.l2cache.overall_mshr_misses::cpu.inst 168722 # number of overall MSHR misses 935system.cpu.l2cache.overall_mshr_misses::total 168827 # number of overall MSHR misses 936system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 6531000 # number of ReadReq MSHR miss cycles 937system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 138750 # number of ReadReq MSHR miss cycles 938system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2281377500 # number of ReadReq MSHR miss cycles 939system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2288047250 # number of ReadReq MSHR miss cycles 940system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 27781774 # number of UpgradeReq MSHR miss cycles 941system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27781774 # number of UpgradeReq MSHR miss cycles
| 925system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 131687 # number of ReadExReq MSHR misses 926system.cpu.l2cache.ReadExReq_mshr_misses::total 131687 # number of ReadExReq MSHR misses 927system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 101 # number of demand (read+write) MSHR misses 928system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses 929system.cpu.l2cache.demand_mshr_misses::cpu.inst 169053 # number of demand (read+write) MSHR misses 930system.cpu.l2cache.demand_mshr_misses::total 169157 # number of demand (read+write) MSHR misses 931system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 101 # number of overall MSHR misses 932system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses 933system.cpu.l2cache.overall_mshr_misses::cpu.inst 169053 # number of overall MSHR misses 934system.cpu.l2cache.overall_mshr_misses::total 169157 # number of overall MSHR misses 935system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 6559500 # number of ReadReq MSHR miss cycles 936system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 187500 # number of ReadReq MSHR miss cycles 937system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2294945750 # number of ReadReq MSHR miss cycles 938system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2301692750 # number of ReadReq MSHR miss cycles 939system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 27763773 # number of UpgradeReq MSHR miss cycles 940system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27763773 # number of UpgradeReq MSHR miss cycles
|
942system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst 20002 # number of SCUpgradeReq MSHR miss cycles 943system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
| 941system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst 20002 # number of SCUpgradeReq MSHR miss cycles 942system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
|
944system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7543603073 # number of ReadExReq MSHR miss cycles 945system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7543603073 # number of ReadExReq MSHR miss cycles 946system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 6531000 # number of demand (read+write) MSHR miss cycles 947system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 138750 # number of demand (read+write) MSHR miss cycles 948system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9824980573 # number of demand (read+write) MSHR miss cycles 949system.cpu.l2cache.demand_mshr_miss_latency::total 9831650323 # number of demand (read+write) MSHR miss cycles 950system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 6531000 # number of overall MSHR miss cycles 951system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 138750 # number of overall MSHR miss cycles 952system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9824980573 # number of overall MSHR miss cycles 953system.cpu.l2cache.overall_mshr_miss_latency::total 9831650323 # number of overall MSHR miss cycles 954system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5545609250 # number of ReadReq MSHR uncacheable cycles 955system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545609250 # number of ReadReq MSHR uncacheable cycles 956system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 4106796000 # number of WriteReq MSHR uncacheable cycles 957system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4106796000 # number of WriteReq MSHR uncacheable cycles 958system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 9652405250 # number of overall MSHR uncacheable cycles 959system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652405250 # number of overall MSHR uncacheable cycles 960system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001491 # mshr miss rate for ReadReq accesses 961system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000423 # mshr miss rate for ReadReq accesses 962system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010846 # mshr miss rate for ReadReq accesses 963system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010648 # mshr miss rate for ReadReq accesses 964system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.984037 # mshr miss rate for UpgradeReq accesses 965system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984037 # mshr miss rate for UpgradeReq accesses
| 943system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7581141318 # number of ReadExReq MSHR miss cycles 944system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7581141318 # number of ReadExReq MSHR miss cycles 945system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 6559500 # number of demand (read+write) MSHR miss cycles 946system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 187500 # number of demand (read+write) MSHR miss cycles 947system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9876087068 # number of demand (read+write) MSHR miss cycles 948system.cpu.l2cache.demand_mshr_miss_latency::total 9882834068 # number of demand (read+write) MSHR miss cycles 949system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 6559500 # number of overall MSHR miss cycles 950system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 187500 # number of overall MSHR miss cycles 951system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9876087068 # number of overall MSHR miss cycles 952system.cpu.l2cache.overall_mshr_miss_latency::total 9882834068 # number of overall MSHR miss cycles 953system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5545310750 # number of ReadReq MSHR uncacheable cycles 954system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545310750 # number of ReadReq MSHR uncacheable cycles 955system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 4106655500 # number of WriteReq MSHR uncacheable cycles 956system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4106655500 # number of WriteReq MSHR uncacheable cycles 957system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 9651966250 # number of overall MSHR uncacheable cycles 958system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9651966250 # number of overall MSHR uncacheable cycles 959system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001462 # mshr miss rate for ReadReq accesses 960system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000626 # mshr miss rate for ReadReq accesses 961system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010852 # mshr miss rate for ReadReq accesses 962system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010653 # mshr miss rate for ReadReq accesses 963system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.984031 # mshr miss rate for UpgradeReq accesses 964system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984031 # mshr miss rate for UpgradeReq accesses
|
966system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses 967system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
| 965system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses 966system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
|
968system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.444305 # mshr miss rate for ReadExReq accesses 969system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.444305 # mshr miss rate for ReadExReq accesses 970system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001491 # mshr miss rate for demand accesses 971system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000423 # mshr miss rate for demand accesses 972system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.045125 # mshr miss rate for demand accesses 973system.cpu.l2cache.demand_mshr_miss_rate::total 0.044279 # mshr miss rate for demand accesses 974system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001491 # mshr miss rate for overall accesses 975system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000423 # mshr miss rate for overall accesses 976system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.045125 # mshr miss rate for overall accesses 977system.cpu.l2cache.overall_mshr_miss_rate::total 0.044279 # mshr miss rate for overall accesses 978system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 63407.766990 # average ReadReq mshr miss latency 979system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 69375 # average ReadReq mshr miss latency 980system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61089.235507 # average ReadReq mshr miss latency 981system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61096.054740 # average ReadReq mshr miss latency 982system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10015.059120 # average UpgradeReq mshr miss latency 983system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10015.059120 # average UpgradeReq mshr miss latency
| 967system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.445257 # mshr miss rate for ReadExReq accesses 968system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.445257 # mshr miss rate for ReadExReq accesses 969system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001462 # mshr miss rate for demand accesses 970system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000626 # mshr miss rate for demand accesses 971system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.045212 # mshr miss rate for demand accesses 972system.cpu.l2cache.demand_mshr_miss_rate::total 0.044363 # mshr miss rate for demand accesses 973system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001462 # mshr miss rate for overall accesses 974system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000626 # mshr miss rate for overall accesses 975system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.045212 # mshr miss rate for overall accesses 976system.cpu.l2cache.overall_mshr_miss_rate::total 0.044363 # mshr miss rate for overall accesses 977system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64945.544554 # average ReadReq mshr miss latency 978system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency 979system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61418.020393 # average ReadReq mshr miss latency 980system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61427.615426 # average ReadReq mshr miss latency 981system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10012.179228 # average UpgradeReq mshr miss latency 982system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10012.179228 # average UpgradeReq mshr miss latency
|
984system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 10001 # average SCUpgradeReq mshr miss latency 985system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
| 983system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 10001 # average SCUpgradeReq mshr miss latency 984system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
|
986system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57419.510820 # average ReadExReq mshr miss latency 987system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57419.510820 # average ReadExReq mshr miss latency 988system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 63407.766990 # average overall mshr miss latency 989system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 69375 # average overall mshr miss latency 990system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58231.769259 # average overall mshr miss latency 991system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58235.059102 # average overall mshr miss latency 992system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 63407.766990 # average overall mshr miss latency 993system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 69375 # average overall mshr miss latency 994system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58231.769259 # average overall mshr miss latency 995system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58235.059102 # average overall mshr miss latency
| 985system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57569.398027 # average ReadExReq mshr miss latency 986system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57569.398027 # average ReadExReq mshr miss latency 987system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64945.544554 # average overall mshr miss latency 988system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 989system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58420.063933 # average overall mshr miss latency 990system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58424.032514 # average overall mshr miss latency 991system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64945.544554 # average overall mshr miss latency 992system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 993system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58420.063933 # average overall mshr miss latency 994system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58424.032514 # average overall mshr miss latency
|
996system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 997system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 998system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 999system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1000system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1001system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1002system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
| 995system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 996system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 997system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 998system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 999system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1000system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1001system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
1003system.cpu.dcache.tags.replacements 841153 # number of replacements 1004system.cpu.dcache.tags.tagsinuse 511.953397 # Cycle average of tags in use 1005system.cpu.dcache.tags.total_refs 42536757 # Total number of references to valid blocks. 1006system.cpu.dcache.tags.sampled_refs 841665 # Sample count of references to valid blocks. 1007system.cpu.dcache.tags.avg_refs 50.538821 # Average number of references to valid blocks. 1008system.cpu.dcache.tags.warmup_cycle 279806250 # Cycle when the warmup percentage was hit. 1009system.cpu.dcache.tags.occ_blocks::cpu.inst 511.953397 # Average occupied blocks per requestor
| 1002system.cpu.dcache.tags.replacements 840767 # number of replacements 1003system.cpu.dcache.tags.tagsinuse 511.953448 # Cycle average of tags in use 1004system.cpu.dcache.tags.total_refs 42450068 # Total number of references to valid blocks. 1005system.cpu.dcache.tags.sampled_refs 841279 # Sample count of references to valid blocks. 1006system.cpu.dcache.tags.avg_refs 50.458965 # Average number of references to valid blocks. 1007system.cpu.dcache.tags.warmup_cycle 279721250 # Cycle when the warmup percentage was hit. 1008system.cpu.dcache.tags.occ_blocks::cpu.inst 511.953448 # Average occupied blocks per requestor
|
1010system.cpu.dcache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy 1011system.cpu.dcache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy 1012system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
| 1009system.cpu.dcache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy 1010system.cpu.dcache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy 1011system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
1013system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 1014system.cpu.dcache.tags.age_task_id_blocks_1024::1 350 # Occupied blocks per task id
| 1012system.cpu.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 1013system.cpu.dcache.tags.age_task_id_blocks_1024::1 358 # Occupied blocks per task id
|
1015system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id 1016system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
| 1014system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id 1015system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
1017system.cpu.dcache.tags.tag_accesses 175509435 # Number of tag accesses 1018system.cpu.dcache.tags.data_accesses 175509435 # Number of data accesses 1019system.cpu.dcache.ReadReq_hits::cpu.inst 23374617 # number of ReadReq hits 1020system.cpu.dcache.ReadReq_hits::total 23374617 # number of ReadReq hits 1021system.cpu.dcache.WriteReq_hits::cpu.inst 18241170 # number of WriteReq hits 1022system.cpu.dcache.WriteReq_hits::total 18241170 # number of WriteReq hits 1023system.cpu.dcache.LoadLockedReq_hits::cpu.inst 457775 # number of LoadLockedReq hits 1024system.cpu.dcache.LoadLockedReq_hits::total 457775 # number of LoadLockedReq hits 1025system.cpu.dcache.StoreCondReq_hits::cpu.inst 460281 # number of StoreCondReq hits 1026system.cpu.dcache.StoreCondReq_hits::total 460281 # number of StoreCondReq hits 1027system.cpu.dcache.demand_hits::cpu.inst 41615787 # number of demand (read+write) hits 1028system.cpu.dcache.demand_hits::total 41615787 # number of demand (read+write) hits 1029system.cpu.dcache.overall_hits::cpu.inst 41615787 # number of overall hits 1030system.cpu.dcache.overall_hits::total 41615787 # number of overall hits 1031system.cpu.dcache.ReadReq_misses::cpu.inst 583566 # number of ReadReq misses 1032system.cpu.dcache.ReadReq_misses::total 583566 # number of ReadReq misses 1033system.cpu.dcache.WriteReq_misses::cpu.inst 541192 # number of WriteReq misses 1034system.cpu.dcache.WriteReq_misses::total 541192 # number of WriteReq misses 1035system.cpu.dcache.LoadLockedReq_misses::cpu.inst 8333 # number of LoadLockedReq misses 1036system.cpu.dcache.LoadLockedReq_misses::total 8333 # number of LoadLockedReq misses
| 1016system.cpu.dcache.tags.tag_accesses 175160699 # Number of tag accesses 1017system.cpu.dcache.tags.data_accesses 175160699 # Number of data accesses 1018system.cpu.dcache.ReadReq_hits::cpu.inst 23317429 # number of ReadReq hits 1019system.cpu.dcache.ReadReq_hits::total 23317429 # number of ReadReq hits 1020system.cpu.dcache.WriteReq_hits::cpu.inst 18211581 # number of WriteReq hits 1021system.cpu.dcache.WriteReq_hits::total 18211581 # number of WriteReq hits 1022system.cpu.dcache.LoadLockedReq_hits::cpu.inst 457826 # number of LoadLockedReq hits 1023system.cpu.dcache.LoadLockedReq_hits::total 457826 # number of LoadLockedReq hits 1024system.cpu.dcache.StoreCondReq_hits::cpu.inst 460320 # number of StoreCondReq hits 1025system.cpu.dcache.StoreCondReq_hits::total 460320 # number of StoreCondReq hits 1026system.cpu.dcache.demand_hits::cpu.inst 41529010 # number of demand (read+write) hits 1027system.cpu.dcache.demand_hits::total 41529010 # number of demand (read+write) hits 1028system.cpu.dcache.overall_hits::cpu.inst 41529010 # number of overall hits 1029system.cpu.dcache.overall_hits::total 41529010 # number of overall hits 1030system.cpu.dcache.ReadReq_misses::cpu.inst 583115 # number of ReadReq misses 1031system.cpu.dcache.ReadReq_misses::total 583115 # number of ReadReq misses 1032system.cpu.dcache.WriteReq_misses::cpu.inst 541259 # number of WriteReq misses 1033system.cpu.dcache.WriteReq_misses::total 541259 # number of WriteReq misses 1034system.cpu.dcache.LoadLockedReq_misses::cpu.inst 8317 # number of LoadLockedReq misses 1035system.cpu.dcache.LoadLockedReq_misses::total 8317 # number of LoadLockedReq misses
|
1037system.cpu.dcache.StoreCondReq_misses::cpu.inst 2 # number of StoreCondReq misses 1038system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
| 1036system.cpu.dcache.StoreCondReq_misses::cpu.inst 2 # number of StoreCondReq misses 1037system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
1039system.cpu.dcache.demand_misses::cpu.inst 1124758 # number of demand (read+write) misses 1040system.cpu.dcache.demand_misses::total 1124758 # number of demand (read+write) misses 1041system.cpu.dcache.overall_misses::cpu.inst 1124758 # number of overall misses 1042system.cpu.dcache.overall_misses::total 1124758 # number of overall misses 1043system.cpu.dcache.ReadReq_miss_latency::cpu.inst 8637456588 # number of ReadReq miss cycles 1044system.cpu.dcache.ReadReq_miss_latency::total 8637456588 # number of ReadReq miss cycles 1045system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21531074313 # number of WriteReq miss cycles 1046system.cpu.dcache.WriteReq_miss_latency::total 21531074313 # number of WriteReq miss cycles 1047system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 117993250 # number of LoadLockedReq miss cycles 1048system.cpu.dcache.LoadLockedReq_miss_latency::total 117993250 # number of LoadLockedReq miss cycles 1049system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 52502 # number of StoreCondReq miss cycles 1050system.cpu.dcache.StoreCondReq_miss_latency::total 52502 # number of StoreCondReq miss cycles 1051system.cpu.dcache.demand_miss_latency::cpu.inst 30168530901 # number of demand (read+write) miss cycles 1052system.cpu.dcache.demand_miss_latency::total 30168530901 # number of demand (read+write) miss cycles 1053system.cpu.dcache.overall_miss_latency::cpu.inst 30168530901 # number of overall miss cycles 1054system.cpu.dcache.overall_miss_latency::total 30168530901 # number of overall miss cycles 1055system.cpu.dcache.ReadReq_accesses::cpu.inst 23958183 # number of ReadReq accesses(hits+misses) 1056system.cpu.dcache.ReadReq_accesses::total 23958183 # number of ReadReq accesses(hits+misses) 1057system.cpu.dcache.WriteReq_accesses::cpu.inst 18782362 # number of WriteReq accesses(hits+misses) 1058system.cpu.dcache.WriteReq_accesses::total 18782362 # number of WriteReq accesses(hits+misses) 1059system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 466108 # number of LoadLockedReq accesses(hits+misses) 1060system.cpu.dcache.LoadLockedReq_accesses::total 466108 # number of LoadLockedReq accesses(hits+misses) 1061system.cpu.dcache.StoreCondReq_accesses::cpu.inst 460283 # number of StoreCondReq accesses(hits+misses) 1062system.cpu.dcache.StoreCondReq_accesses::total 460283 # number of StoreCondReq accesses(hits+misses) 1063system.cpu.dcache.demand_accesses::cpu.inst 42740545 # number of demand (read+write) accesses 1064system.cpu.dcache.demand_accesses::total 42740545 # number of demand (read+write) accesses 1065system.cpu.dcache.overall_accesses::cpu.inst 42740545 # number of overall (read+write) accesses 1066system.cpu.dcache.overall_accesses::total 42740545 # number of overall (read+write) accesses 1067system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.024358 # miss rate for ReadReq accesses 1068system.cpu.dcache.ReadReq_miss_rate::total 0.024358 # miss rate for ReadReq accesses 1069system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.028814 # miss rate for WriteReq accesses 1070system.cpu.dcache.WriteReq_miss_rate::total 0.028814 # miss rate for WriteReq accesses 1071system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.017878 # miss rate for LoadLockedReq accesses 1072system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017878 # miss rate for LoadLockedReq accesses
| 1038system.cpu.dcache.demand_misses::cpu.inst 1124374 # number of demand (read+write) misses 1039system.cpu.dcache.demand_misses::total 1124374 # number of demand (read+write) misses 1040system.cpu.dcache.overall_misses::cpu.inst 1124374 # number of overall misses 1041system.cpu.dcache.overall_misses::total 1124374 # number of overall misses 1042system.cpu.dcache.ReadReq_miss_latency::cpu.inst 8642422585 # number of ReadReq miss cycles 1043system.cpu.dcache.ReadReq_miss_latency::total 8642422585 # number of ReadReq miss cycles 1044system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21588022799 # number of WriteReq miss cycles 1045system.cpu.dcache.WriteReq_miss_latency::total 21588022799 # number of WriteReq miss cycles 1046system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 117987000 # number of LoadLockedReq miss cycles 1047system.cpu.dcache.LoadLockedReq_miss_latency::total 117987000 # number of LoadLockedReq miss cycles 1048system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 53002 # number of StoreCondReq miss cycles 1049system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles 1050system.cpu.dcache.demand_miss_latency::cpu.inst 30230445384 # number of demand (read+write) miss cycles 1051system.cpu.dcache.demand_miss_latency::total 30230445384 # number of demand (read+write) miss cycles 1052system.cpu.dcache.overall_miss_latency::cpu.inst 30230445384 # number of overall miss cycles 1053system.cpu.dcache.overall_miss_latency::total 30230445384 # number of overall miss cycles 1054system.cpu.dcache.ReadReq_accesses::cpu.inst 23900544 # number of ReadReq accesses(hits+misses) 1055system.cpu.dcache.ReadReq_accesses::total 23900544 # number of ReadReq accesses(hits+misses) 1056system.cpu.dcache.WriteReq_accesses::cpu.inst 18752840 # number of WriteReq accesses(hits+misses) 1057system.cpu.dcache.WriteReq_accesses::total 18752840 # number of WriteReq accesses(hits+misses) 1058system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 466143 # number of LoadLockedReq accesses(hits+misses) 1059system.cpu.dcache.LoadLockedReq_accesses::total 466143 # number of LoadLockedReq accesses(hits+misses) 1060system.cpu.dcache.StoreCondReq_accesses::cpu.inst 460322 # number of StoreCondReq accesses(hits+misses) 1061system.cpu.dcache.StoreCondReq_accesses::total 460322 # number of StoreCondReq accesses(hits+misses) 1062system.cpu.dcache.demand_accesses::cpu.inst 42653384 # number of demand (read+write) accesses 1063system.cpu.dcache.demand_accesses::total 42653384 # number of demand (read+write) accesses 1064system.cpu.dcache.overall_accesses::cpu.inst 42653384 # number of overall (read+write) accesses 1065system.cpu.dcache.overall_accesses::total 42653384 # number of overall (read+write) accesses 1066system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.024398 # miss rate for ReadReq accesses 1067system.cpu.dcache.ReadReq_miss_rate::total 0.024398 # miss rate for ReadReq accesses 1068system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.028863 # miss rate for WriteReq accesses 1069system.cpu.dcache.WriteReq_miss_rate::total 0.028863 # miss rate for WriteReq accesses 1070system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.017842 # miss rate for LoadLockedReq accesses 1071system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017842 # miss rate for LoadLockedReq accesses
|
1073system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000004 # miss rate for StoreCondReq accesses 1074system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
| 1072system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000004 # miss rate for StoreCondReq accesses 1073system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
|
1075system.cpu.dcache.demand_miss_rate::cpu.inst 0.026316 # miss rate for demand accesses 1076system.cpu.dcache.demand_miss_rate::total 0.026316 # miss rate for demand accesses 1077system.cpu.dcache.overall_miss_rate::cpu.inst 0.026316 # miss rate for overall accesses 1078system.cpu.dcache.overall_miss_rate::total 0.026316 # miss rate for overall accesses 1079system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14801.164886 # average ReadReq miss latency 1080system.cpu.dcache.ReadReq_avg_miss_latency::total 14801.164886 # average ReadReq miss latency 1081system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39784.539152 # average WriteReq miss latency 1082system.cpu.dcache.WriteReq_avg_miss_latency::total 39784.539152 # average WriteReq miss latency 1083system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14159.756390 # average LoadLockedReq miss latency 1084system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14159.756390 # average LoadLockedReq miss latency 1085system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 26251 # average StoreCondReq miss latency 1086system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26251 # average StoreCondReq miss latency 1087system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26822.241674 # average overall miss latency 1088system.cpu.dcache.demand_avg_miss_latency::total 26822.241674 # average overall miss latency 1089system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26822.241674 # average overall miss latency 1090system.cpu.dcache.overall_avg_miss_latency::total 26822.241674 # average overall miss latency
| 1074system.cpu.dcache.demand_miss_rate::cpu.inst 0.026361 # miss rate for demand accesses 1075system.cpu.dcache.demand_miss_rate::total 0.026361 # miss rate for demand accesses 1076system.cpu.dcache.overall_miss_rate::cpu.inst 0.026361 # miss rate for overall accesses 1077system.cpu.dcache.overall_miss_rate::total 0.026361 # miss rate for overall accesses 1078system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14821.128911 # average ReadReq miss latency 1079system.cpu.dcache.ReadReq_avg_miss_latency::total 14821.128911 # average ReadReq miss latency 1080system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39884.829257 # average WriteReq miss latency 1081system.cpu.dcache.WriteReq_avg_miss_latency::total 39884.829257 # average WriteReq miss latency 1082system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14186.245040 # average LoadLockedReq miss latency 1083system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14186.245040 # average LoadLockedReq miss latency 1084system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 26501 # average StoreCondReq miss latency 1085system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency 1086system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26886.467834 # average overall miss latency 1087system.cpu.dcache.demand_avg_miss_latency::total 26886.467834 # average overall miss latency 1088system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26886.467834 # average overall miss latency 1089system.cpu.dcache.overall_avg_miss_latency::total 26886.467834 # average overall miss latency
|
1091system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1092system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1093system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1094system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1095system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1096system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1097system.cpu.dcache.fast_writes 0 # number of fast writes performed 1098system.cpu.dcache.cache_copies 0 # number of cache copies performed
| 1090system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1091system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1092system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1093system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1094system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1095system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1096system.cpu.dcache.fast_writes 0 # number of fast writes performed 1097system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
1099system.cpu.dcache.writebacks::writebacks 697864 # number of writebacks 1100system.cpu.dcache.writebacks::total 697864 # number of writebacks 1101system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 45894 # number of ReadReq MSHR hits 1102system.cpu.dcache.ReadReq_mshr_hits::total 45894 # number of ReadReq MSHR hits 1103system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 242687 # number of WriteReq MSHR hits 1104system.cpu.dcache.WriteReq_mshr_hits::total 242687 # number of WriteReq MSHR hits 1105system.cpu.dcache.demand_mshr_hits::cpu.inst 288581 # number of demand (read+write) MSHR hits 1106system.cpu.dcache.demand_mshr_hits::total 288581 # number of demand (read+write) MSHR hits 1107system.cpu.dcache.overall_mshr_hits::cpu.inst 288581 # number of overall MSHR hits 1108system.cpu.dcache.overall_mshr_hits::total 288581 # number of overall MSHR hits 1109system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 537672 # number of ReadReq MSHR misses 1110system.cpu.dcache.ReadReq_mshr_misses::total 537672 # number of ReadReq MSHR misses 1111system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 298505 # number of WriteReq MSHR misses 1112system.cpu.dcache.WriteReq_mshr_misses::total 298505 # number of WriteReq MSHR misses 1113system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 8333 # number of LoadLockedReq MSHR misses 1114system.cpu.dcache.LoadLockedReq_mshr_misses::total 8333 # number of LoadLockedReq MSHR misses
| 1098system.cpu.dcache.writebacks::writebacks 697424 # number of writebacks 1099system.cpu.dcache.writebacks::total 697424 # number of writebacks 1100system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 45879 # number of ReadReq MSHR hits 1101system.cpu.dcache.ReadReq_mshr_hits::total 45879 # number of ReadReq MSHR hits 1102system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 242691 # number of WriteReq MSHR hits 1103system.cpu.dcache.WriteReq_mshr_hits::total 242691 # number of WriteReq MSHR hits 1104system.cpu.dcache.demand_mshr_hits::cpu.inst 288570 # number of demand (read+write) MSHR hits 1105system.cpu.dcache.demand_mshr_hits::total 288570 # number of demand (read+write) MSHR hits 1106system.cpu.dcache.overall_mshr_hits::cpu.inst 288570 # number of overall MSHR hits 1107system.cpu.dcache.overall_mshr_hits::total 288570 # number of overall MSHR hits 1108system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 537236 # number of ReadReq MSHR misses 1109system.cpu.dcache.ReadReq_mshr_misses::total 537236 # number of ReadReq MSHR misses 1110system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 298568 # number of WriteReq MSHR misses 1111system.cpu.dcache.WriteReq_mshr_misses::total 298568 # number of WriteReq MSHR misses 1112system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 8317 # number of LoadLockedReq MSHR misses 1113system.cpu.dcache.LoadLockedReq_mshr_misses::total 8317 # number of LoadLockedReq MSHR misses
|
1115system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 2 # number of StoreCondReq MSHR misses 1116system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
| 1114system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 2 # number of StoreCondReq MSHR misses 1115system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
|
1117system.cpu.dcache.demand_mshr_misses::cpu.inst 836177 # number of demand (read+write) MSHR misses 1118system.cpu.dcache.demand_mshr_misses::total 836177 # number of demand (read+write) MSHR misses 1119system.cpu.dcache.overall_mshr_misses::cpu.inst 836177 # number of overall MSHR misses 1120system.cpu.dcache.overall_mshr_misses::total 836177 # number of overall MSHR misses 1121system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6873353393 # number of ReadReq MSHR miss cycles 1122system.cpu.dcache.ReadReq_mshr_miss_latency::total 6873353393 # number of ReadReq MSHR miss cycles 1123system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 11227746403 # number of WriteReq MSHR miss cycles 1124system.cpu.dcache.WriteReq_mshr_miss_latency::total 11227746403 # number of WriteReq MSHR miss cycles 1125system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 101298750 # number of LoadLockedReq MSHR miss cycles 1126system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 101298750 # number of LoadLockedReq MSHR miss cycles 1127system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 48498 # number of StoreCondReq MSHR miss cycles 1128system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48498 # number of StoreCondReq MSHR miss cycles 1129system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 18101099796 # number of demand (read+write) MSHR miss cycles 1130system.cpu.dcache.demand_mshr_miss_latency::total 18101099796 # number of demand (read+write) MSHR miss cycles 1131system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 18101099796 # number of overall MSHR miss cycles 1132system.cpu.dcache.overall_mshr_miss_latency::total 18101099796 # number of overall MSHR miss cycles 1133system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5791247750 # number of ReadReq MSHR uncacheable cycles 1134system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791247750 # number of ReadReq MSHR uncacheable cycles 1135system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 4439329000 # number of WriteReq MSHR uncacheable cycles 1136system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439329000 # number of WriteReq MSHR uncacheable cycles 1137system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 10230576750 # number of overall MSHR uncacheable cycles 1138system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230576750 # number of overall MSHR uncacheable cycles 1139system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.022442 # mshr miss rate for ReadReq accesses 1140system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022442 # mshr miss rate for ReadReq accesses 1141system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015893 # mshr miss rate for WriteReq accesses 1142system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015893 # mshr miss rate for WriteReq accesses 1143system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.017878 # mshr miss rate for LoadLockedReq accesses 1144system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017878 # mshr miss rate for LoadLockedReq accesses
| 1116system.cpu.dcache.demand_mshr_misses::cpu.inst 835804 # number of demand (read+write) MSHR misses 1117system.cpu.dcache.demand_mshr_misses::total 835804 # number of demand (read+write) MSHR misses 1118system.cpu.dcache.overall_mshr_misses::cpu.inst 835804 # number of overall MSHR misses 1119system.cpu.dcache.overall_mshr_misses::total 835804 # number of overall MSHR misses 1120system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6874982646 # number of ReadReq MSHR miss cycles 1121system.cpu.dcache.ReadReq_mshr_miss_latency::total 6874982646 # number of ReadReq MSHR miss cycles 1122system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 11266915159 # number of WriteReq MSHR miss cycles 1123system.cpu.dcache.WriteReq_mshr_miss_latency::total 11266915159 # number of WriteReq MSHR miss cycles 1124system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 101324000 # number of LoadLockedReq MSHR miss cycles 1125system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 101324000 # number of LoadLockedReq MSHR miss cycles 1126system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 48998 # number of StoreCondReq MSHR miss cycles 1127system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles 1128system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 18141897805 # number of demand (read+write) MSHR miss cycles 1129system.cpu.dcache.demand_mshr_miss_latency::total 18141897805 # number of demand (read+write) MSHR miss cycles 1130system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 18141897805 # number of overall MSHR miss cycles 1131system.cpu.dcache.overall_mshr_miss_latency::total 18141897805 # number of overall MSHR miss cycles 1132system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5791016000 # number of ReadReq MSHR uncacheable cycles 1133system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791016000 # number of ReadReq MSHR uncacheable cycles 1134system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 4439188000 # number of WriteReq MSHR uncacheable cycles 1135system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439188000 # number of WriteReq MSHR uncacheable cycles 1136system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 10230204000 # number of overall MSHR uncacheable cycles 1137system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230204000 # number of overall MSHR uncacheable cycles 1138system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.022478 # mshr miss rate for ReadReq accesses 1139system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022478 # mshr miss rate for ReadReq accesses 1140system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015921 # mshr miss rate for WriteReq accesses 1141system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015921 # mshr miss rate for WriteReq accesses 1142system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.017842 # mshr miss rate for LoadLockedReq accesses 1143system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017842 # mshr miss rate for LoadLockedReq accesses
|
1145system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for StoreCondReq accesses 1146system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
| 1144system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for StoreCondReq accesses 1145system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
|
1147system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.019564 # mshr miss rate for demand accesses 1148system.cpu.dcache.demand_mshr_miss_rate::total 0.019564 # mshr miss rate for demand accesses 1149system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019564 # mshr miss rate for overall accesses 1150system.cpu.dcache.overall_mshr_miss_rate::total 0.019564 # mshr miss rate for overall accesses 1151system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12783.543486 # average ReadReq mshr miss latency 1152system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12783.543486 # average ReadReq mshr miss latency 1153system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37613.260759 # average WriteReq mshr miss latency 1154system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37613.260759 # average WriteReq mshr miss latency 1155system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12156.336253 # average LoadLockedReq mshr miss latency 1156system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12156.336253 # average LoadLockedReq mshr miss latency 1157system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 24249 # average StoreCondReq mshr miss latency 1158system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24249 # average StoreCondReq mshr miss latency 1159system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21647.449997 # average overall mshr miss latency 1160system.cpu.dcache.demand_avg_mshr_miss_latency::total 21647.449997 # average overall mshr miss latency 1161system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21647.449997 # average overall mshr miss latency 1162system.cpu.dcache.overall_avg_mshr_miss_latency::total 21647.449997 # average overall mshr miss latency
| 1146system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.019595 # mshr miss rate for demand accesses 1147system.cpu.dcache.demand_mshr_miss_rate::total 0.019595 # mshr miss rate for demand accesses 1148system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019595 # mshr miss rate for overall accesses 1149system.cpu.dcache.overall_mshr_miss_rate::total 0.019595 # mshr miss rate for overall accesses 1150system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12796.950774 # average ReadReq mshr miss latency 1151system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12796.950774 # average ReadReq mshr miss latency 1152system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37736.512818 # average WriteReq mshr miss latency 1153system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37736.512818 # average WriteReq mshr miss latency 1154system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12182.758206 # average LoadLockedReq mshr miss latency 1155system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12182.758206 # average LoadLockedReq mshr miss latency 1156system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 24499 # average StoreCondReq mshr miss latency 1157system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency 1158system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21705.923644 # average overall mshr miss latency 1159system.cpu.dcache.demand_avg_mshr_miss_latency::total 21705.923644 # average overall mshr miss latency 1160system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21705.923644 # average overall mshr miss latency 1161system.cpu.dcache.overall_avg_mshr_miss_latency::total 21705.923644 # average overall mshr miss latency
|
1163system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1164system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1165system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 1166system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1167system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1168system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1169system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1170system.iocache.tags.replacements 36424 # number of replacements
| 1162system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1163system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1164system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 1165system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1166system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1167system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1168system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1169system.iocache.tags.replacements 36424 # number of replacements
|
1171system.iocache.tags.tagsinuse 1.031370 # Cycle average of tags in use
| 1170system.iocache.tags.tagsinuse 1.031475 # Cycle average of tags in use
|
1172system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1173system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1174system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
| 1171system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1172system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1173system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
1175system.iocache.tags.warmup_cycle 269945589000 # Cycle when the warmup percentage was hit. 1176system.iocache.tags.occ_blocks::realview.ide 1.031370 # Average occupied blocks per requestor 1177system.iocache.tags.occ_percent::realview.ide 0.064461 # Average percentage of cache occupancy 1178system.iocache.tags.occ_percent::total 0.064461 # Average percentage of cache occupancy
| 1174system.iocache.tags.warmup_cycle 269946820000 # Cycle when the warmup percentage was hit. 1175system.iocache.tags.occ_blocks::realview.ide 1.031475 # Average occupied blocks per requestor 1176system.iocache.tags.occ_percent::realview.ide 0.064467 # Average percentage of cache occupancy 1177system.iocache.tags.occ_percent::total 0.064467 # Average percentage of cache occupancy
|
1179system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1180system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1181system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1182system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1183system.iocache.tags.data_accesses 328122 # Number of data accesses 1184system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 1185system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 1186system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1187system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1188system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses 1189system.iocache.demand_misses::total 234 # number of demand (read+write) misses 1190system.iocache.overall_misses::realview.ide 234 # number of overall misses 1191system.iocache.overall_misses::total 234 # number of overall misses
| 1178system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1179system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1180system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1181system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1182system.iocache.tags.data_accesses 328122 # Number of data accesses 1183system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 1184system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 1185system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1186system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1187system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses 1188system.iocache.demand_misses::total 234 # number of demand (read+write) misses 1189system.iocache.overall_misses::realview.ide 234 # number of overall misses 1190system.iocache.overall_misses::total 234 # number of overall misses
|
1192system.iocache.ReadReq_miss_latency::realview.ide 27970377 # number of ReadReq miss cycles 1193system.iocache.ReadReq_miss_latency::total 27970377 # number of ReadReq miss cycles 1194system.iocache.demand_miss_latency::realview.ide 27970377 # number of demand (read+write) miss cycles 1195system.iocache.demand_miss_latency::total 27970377 # number of demand (read+write) miss cycles 1196system.iocache.overall_miss_latency::realview.ide 27970377 # number of overall miss cycles 1197system.iocache.overall_miss_latency::total 27970377 # number of overall miss cycles
| 1191system.iocache.ReadReq_miss_latency::realview.ide 27954377 # number of ReadReq miss cycles 1192system.iocache.ReadReq_miss_latency::total 27954377 # number of ReadReq miss cycles 1193system.iocache.demand_miss_latency::realview.ide 27954377 # number of demand (read+write) miss cycles 1194system.iocache.demand_miss_latency::total 27954377 # number of demand (read+write) miss cycles 1195system.iocache.overall_miss_latency::realview.ide 27954377 # number of overall miss cycles 1196system.iocache.overall_miss_latency::total 27954377 # number of overall miss cycles
|
1198system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1199system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1200system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1201system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 1202system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses 1203system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses 1204system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses 1205system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses 1206system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1207system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1208system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1209system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1210system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1211system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
| 1197system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1198system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1199system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1200system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 1201system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses 1202system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses 1203system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses 1204system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses 1205system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1206system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1207system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1208system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1209system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1210system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
1212system.iocache.ReadReq_avg_miss_latency::realview.ide 119531.525641 # average ReadReq miss latency 1213system.iocache.ReadReq_avg_miss_latency::total 119531.525641 # average ReadReq miss latency 1214system.iocache.demand_avg_miss_latency::realview.ide 119531.525641 # average overall miss latency 1215system.iocache.demand_avg_miss_latency::total 119531.525641 # average overall miss latency 1216system.iocache.overall_avg_miss_latency::realview.ide 119531.525641 # average overall miss latency 1217system.iocache.overall_avg_miss_latency::total 119531.525641 # average overall miss latency
| 1211system.iocache.ReadReq_avg_miss_latency::realview.ide 119463.149573 # average ReadReq miss latency 1212system.iocache.ReadReq_avg_miss_latency::total 119463.149573 # average ReadReq miss latency 1213system.iocache.demand_avg_miss_latency::realview.ide 119463.149573 # average overall miss latency 1214system.iocache.demand_avg_miss_latency::total 119463.149573 # average overall miss latency 1215system.iocache.overall_avg_miss_latency::realview.ide 119463.149573 # average overall miss latency 1216system.iocache.overall_avg_miss_latency::total 119463.149573 # average overall miss latency
|
1218system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1219system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1220system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1221system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1222system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1223system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1224system.iocache.fast_writes 36224 # number of fast writes performed 1225system.iocache.cache_copies 0 # number of cache copies performed 1226system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1227system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1228system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses 1229system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses 1230system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses 1231system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
| 1217system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1218system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1219system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1220system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1221system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1222system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1223system.iocache.fast_writes 36224 # number of fast writes performed 1224system.iocache.cache_copies 0 # number of cache copies performed 1225system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1226system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1227system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses 1228system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses 1229system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses 1230system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
|
1232system.iocache.ReadReq_mshr_miss_latency::realview.ide 15801377 # number of ReadReq MSHR miss cycles 1233system.iocache.ReadReq_mshr_miss_latency::total 15801377 # number of ReadReq MSHR miss cycles 1234system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2215530472 # number of WriteInvalidateReq MSHR miss cycles 1235system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2215530472 # number of WriteInvalidateReq MSHR miss cycles 1236system.iocache.demand_mshr_miss_latency::realview.ide 15801377 # number of demand (read+write) MSHR miss cycles 1237system.iocache.demand_mshr_miss_latency::total 15801377 # number of demand (read+write) MSHR miss cycles 1238system.iocache.overall_mshr_miss_latency::realview.ide 15801377 # number of overall MSHR miss cycles 1239system.iocache.overall_mshr_miss_latency::total 15801377 # number of overall MSHR miss cycles
| 1231system.iocache.ReadReq_mshr_miss_latency::realview.ide 15785377 # number of ReadReq MSHR miss cycles 1232system.iocache.ReadReq_mshr_miss_latency::total 15785377 # number of ReadReq MSHR miss cycles 1233system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2212496723 # number of WriteInvalidateReq MSHR miss cycles 1234system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2212496723 # number of WriteInvalidateReq MSHR miss cycles 1235system.iocache.demand_mshr_miss_latency::realview.ide 15785377 # number of demand (read+write) MSHR miss cycles 1236system.iocache.demand_mshr_miss_latency::total 15785377 # number of demand (read+write) MSHR miss cycles 1237system.iocache.overall_mshr_miss_latency::realview.ide 15785377 # number of overall MSHR miss cycles 1238system.iocache.overall_mshr_miss_latency::total 15785377 # number of overall MSHR miss cycles
|
1240system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1241system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1242system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1243system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1244system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1245system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
| 1239system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1240system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1241system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1242system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1243system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1244system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
1246system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67527.252137 # average ReadReq mshr miss latency 1247system.iocache.ReadReq_avg_mshr_miss_latency::total 67527.252137 # average ReadReq mshr miss latency
| 1245system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67458.876068 # average ReadReq mshr miss latency 1246system.iocache.ReadReq_avg_mshr_miss_latency::total 67458.876068 # average ReadReq mshr miss latency
|
1248system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 1249system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
| 1247system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 1248system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
|
1250system.iocache.demand_avg_mshr_miss_latency::realview.ide 67527.252137 # average overall mshr miss latency 1251system.iocache.demand_avg_mshr_miss_latency::total 67527.252137 # average overall mshr miss latency 1252system.iocache.overall_avg_mshr_miss_latency::realview.ide 67527.252137 # average overall mshr miss latency 1253system.iocache.overall_avg_mshr_miss_latency::total 67527.252137 # average overall mshr miss latency
| 1249system.iocache.demand_avg_mshr_miss_latency::realview.ide 67458.876068 # average overall mshr miss latency 1250system.iocache.demand_avg_mshr_miss_latency::total 67458.876068 # average overall mshr miss latency 1251system.iocache.overall_avg_mshr_miss_latency::realview.ide 67458.876068 # average overall mshr miss latency 1252system.iocache.overall_avg_mshr_miss_latency::total 67458.876068 # average overall mshr miss latency
|
1254system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1255 1256---------- End Simulation Statistics ----------
| 1253system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1254 1255---------- End Simulation Statistics ----------
|