1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.858505 # Number of seconds simulated
4sim_ticks 2858505242500 # Number of ticks simulated
5final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 125507 # Simulator instruction rate (inst/s)
8host_op_rate 151748 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 3206183180 # Simulator tick rate (ticks/s)
10host_mem_usage 578080 # Number of bytes of host memory used
11host_seconds 891.56 # Real time elapsed on the host
12sim_insts 111897168 # Number of instructions simulated
13sim_ops 135292215 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.inst 1705984 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.data 9156972 # Number of bytes read from this memory
20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
21system.physmem.bytes_read::total 10871852 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 1705984 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 1705984 # Number of instructions bytes read from this memory
--- 283 unchanged lines hidden (view full) ---
307system.physmem_1.preBackEnergy 1640445162750 # Energy for precharge background per rank (pJ)
308system.physmem_1.totalEnergy 1913635982970 # Total energy per rank (pJ)
309system.physmem_1.averagePower 669.453685 # Core power per rank (mW)
310system.physmem_1.memoryStateTime::IDLE 2728879759500 # Time in different power states
311system.physmem_1.memoryStateTime::REF 95451720000 # Time in different power states
312system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
313system.physmem_1.memoryStateTime::ACT 34173617000 # Time in different power states
314system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
315system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory
316system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory
317system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory
318system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory
319system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
320system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
321system.realview.nvmem.bw_read::cpu.inst 179 # Total read bandwidth from this memory (bytes/s)
322system.realview.nvmem.bw_read::total 179 # Total read bandwidth from this memory (bytes/s)
323system.realview.nvmem.bw_inst_read::cpu.inst 179 # Instruction read bandwidth from this memory (bytes/s)
324system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s)
325system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s)
326system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s)
327system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
328system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
329system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
330system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
331system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
332system.cf0.dma_write_txs 631 # Number of DMA write transactions.
333system.cpu.branchPred.lookups 30988279 # Number of BP lookups
334system.cpu.branchPred.condPredicted 16810499 # Number of conditional branches predicted
--- 4 unchanged lines hidden (view full) ---
339system.cpu.branchPred.BTBHitPct 55.936168 # BTB Hit Percentage
340system.cpu.branchPred.usedRAS 7863209 # Number of times the RAS was used to get a target.
341system.cpu.branchPred.RASInCorrect 1506080 # Number of incorrect RAS predictions.
342system.cpu.branchPred.indirectLookups 3044381 # Number of indirect predictor lookups.
343system.cpu.branchPred.indirectHits 2857246 # Number of indirect target hits.
344system.cpu.branchPred.indirectMisses 187135 # Number of indirect misses.
345system.cpu.branchPredindirectMispredicted 108257 # Number of mispredicted indirect branches.
346system.cpu_clk_domain.clock 500 # Clock period in ticks
347system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
348system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
349system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
350system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
351system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
352system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
353system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
354system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
368system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
369system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
370system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
371system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
372system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
373system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
374system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
375system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
376system.cpu.dtb.walker.walks 66151 # Table walker walks requested
377system.cpu.dtb.walker.walksShort 66151 # Table walker walks initiated with short descriptors
378system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43510 # Level at which table walker walks with short descriptors terminate
379system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22641 # Level at which table walker walks with short descriptors terminate
380system.cpu.dtb.walker.walkWaitTime::samples 66151 # Table walker wait (enqueue to first request) latency
381system.cpu.dtb.walker.walkWaitTime::0 66151 100.00% 100.00% # Table walker wait (enqueue to first request) latency
382system.cpu.dtb.walker.walkWaitTime::total 66151 # Table walker wait (enqueue to first request) latency
383system.cpu.dtb.walker.walkCompletionTime::samples 7866 # Table walker service (enqueue to completion) latency
--- 33 unchanged lines hidden (view full) ---
417system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
418system.cpu.dtb.perms_faults 754 # Number of TLB faults due to permissions restrictions
419system.cpu.dtb.read_accesses 24770191 # DTB read accesses
420system.cpu.dtb.write_accesses 19431197 # DTB write accesses
421system.cpu.dtb.inst_accesses 0 # ITB inst accesses
422system.cpu.dtb.hits 44135237 # DTB hits
423system.cpu.dtb.misses 66151 # DTB misses
424system.cpu.dtb.accesses 44201388 # DTB accesses
425system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
426system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
427system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
428system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
429system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
430system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
431system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
432system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
446system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
447system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
448system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
449system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
450system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
451system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
452system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
453system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
454system.cpu.itb.walker.walks 5761 # Table walker walks requested
455system.cpu.itb.walker.walksShort 5761 # Table walker walks initiated with short descriptors
456system.cpu.itb.walker.walksShortTerminationLevel::Level1 327 # Level at which table walker walks with short descriptors terminate
457system.cpu.itb.walker.walksShortTerminationLevel::Level2 5434 # Level at which table walker walks with short descriptors terminate
458system.cpu.itb.walker.walkWaitTime::samples 5761 # Table walker wait (enqueue to first request) latency
459system.cpu.itb.walker.walkWaitTime::0 5761 100.00% 100.00% # Table walker wait (enqueue to first request) latency
460system.cpu.itb.walker.walkWaitTime::total 5761 # Table walker wait (enqueue to first request) latency
461system.cpu.itb.walker.walkCompletionTime::samples 3206 # Table walker service (enqueue to completion) latency
--- 33 unchanged lines hidden (view full) ---
495system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
496system.cpu.itb.perms_faults 8365 # Number of TLB faults due to permissions restrictions
497system.cpu.itb.read_accesses 0 # DTB read accesses
498system.cpu.itb.write_accesses 0 # DTB write accesses
499system.cpu.itb.inst_accesses 57339683 # ITB inst accesses
500system.cpu.itb.hits 57333922 # DTB hits
501system.cpu.itb.misses 5761 # DTB misses
502system.cpu.itb.accesses 57339683 # DTB accesses
503system.cpu.numCycles 332822103 # number of cpu cycles simulated
504system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
505system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
506system.cpu.committedInsts 111897168 # Number of instructions committed
507system.cpu.committedOps 135292215 # Number of ops (including micro ops) committed
508system.cpu.discardedOps 7734017 # Number of ops (including micro ops) which were discarded before commit
509system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching
510system.cpu.quiesceCycles 5384249089 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
--- 33 unchanged lines hidden (view full) ---
544system.cpu.op_class_0::MemWrite 20252013 14.97% 100.00% # Class of committed instruction
545system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
546system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
547system.cpu.op_class_0::total 135292215 # Class of committed instruction
548system.cpu.kern.inst.arm 0 # number of arm instructions executed
549system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed
550system.cpu.tickCycles 228131430 # Number of cycles that the object actually ticked
551system.cpu.idleCycles 104690673 # Total number of cycles that the object has spent stopped
552system.cpu.dcache.tags.replacements 842468 # number of replacements
553system.cpu.dcache.tags.tagsinuse 511.899803 # Cycle average of tags in use
554system.cpu.dcache.tags.total_refs 42541759 # Total number of references to valid blocks.
555system.cpu.dcache.tags.sampled_refs 842980 # Sample count of references to valid blocks.
556system.cpu.dcache.tags.avg_refs 50.465917 # Average number of references to valid blocks.
557system.cpu.dcache.tags.warmup_cycle 594757500 # Cycle when the warmup percentage was hit.
558system.cpu.dcache.tags.occ_blocks::cpu.data 511.899803 # Average occupied blocks per requestor
559system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy
560system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy
561system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
562system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
563system.cpu.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id
564system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id
565system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
566system.cpu.dcache.tags.tag_accesses 175934555 # Number of tag accesses
567system.cpu.dcache.tags.data_accesses 175934555 # Number of data accesses
568system.cpu.dcache.ReadReq_hits::cpu.data 23016255 # number of ReadReq hits
569system.cpu.dcache.ReadReq_hits::total 23016255 # number of ReadReq hits
570system.cpu.dcache.WriteReq_hits::cpu.data 18262413 # number of WriteReq hits
571system.cpu.dcache.WriteReq_hits::total 18262413 # number of WriteReq hits
572system.cpu.dcache.SoftPFReq_hits::cpu.data 356302 # number of SoftPFReq hits
573system.cpu.dcache.SoftPFReq_hits::total 356302 # number of SoftPFReq hits
574system.cpu.dcache.LoadLockedReq_hits::cpu.data 443705 # number of LoadLockedReq hits
575system.cpu.dcache.LoadLockedReq_hits::total 443705 # number of LoadLockedReq hits
--- 152 unchanged lines hidden (view full) ---
728system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35925.580551 # average overall mshr miss latency
729system.cpu.dcache.demand_avg_mshr_miss_latency::total 35925.580551 # average overall mshr miss latency
730system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32760.298800 # average overall mshr miss latency
731system.cpu.dcache.overall_avg_mshr_miss_latency::total 32760.298800 # average overall mshr miss latency
732system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201679.548959 # average ReadReq mshr uncacheable latency
733system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201679.548959 # average ReadReq mshr uncacheable latency
734system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106928.531280 # average overall mshr uncacheable latency
735system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106928.531280 # average overall mshr uncacheable latency
736system.cpu.icache.tags.replacements 2894371 # number of replacements
737system.cpu.icache.tags.tagsinuse 511.208818 # Cycle average of tags in use
738system.cpu.icache.tags.total_refs 54430342 # Total number of references to valid blocks.
739system.cpu.icache.tags.sampled_refs 2894883 # Sample count of references to valid blocks.
740system.cpu.icache.tags.avg_refs 18.802260 # Average number of references to valid blocks.
741system.cpu.icache.tags.warmup_cycle 18407091500 # Cycle when the warmup percentage was hit.
742system.cpu.icache.tags.occ_blocks::cpu.inst 511.208818 # Average occupied blocks per requestor
743system.cpu.icache.tags.occ_percent::cpu.inst 0.998455 # Average percentage of cache occupancy
744system.cpu.icache.tags.occ_percent::total 0.998455 # Average percentage of cache occupancy
745system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
746system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
747system.cpu.icache.tags.age_task_id_blocks_1024::1 201 # Occupied blocks per task id
748system.cpu.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id
749system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
750system.cpu.icache.tags.tag_accesses 60220131 # Number of tag accesses
751system.cpu.icache.tags.data_accesses 60220131 # Number of data accesses
752system.cpu.icache.ReadReq_hits::cpu.inst 54430342 # number of ReadReq hits
753system.cpu.icache.ReadReq_hits::total 54430342 # number of ReadReq hits
754system.cpu.icache.demand_hits::cpu.inst 54430342 # number of demand (read+write) hits
755system.cpu.icache.demand_hits::total 54430342 # number of demand (read+write) hits
756system.cpu.icache.overall_hits::cpu.inst 54430342 # number of overall hits
757system.cpu.icache.overall_hits::total 54430342 # number of overall hits
758system.cpu.icache.ReadReq_misses::cpu.inst 2894895 # number of ReadReq misses
759system.cpu.icache.ReadReq_misses::total 2894895 # number of ReadReq misses
--- 64 unchanged lines hidden (view full) ---
824system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12973.899744 # average overall mshr miss latency
825system.cpu.icache.demand_avg_mshr_miss_latency::total 12973.899744 # average overall mshr miss latency
826system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12973.899744 # average overall mshr miss latency
827system.cpu.icache.overall_avg_mshr_miss_latency::total 12973.899744 # average overall mshr miss latency
828system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average ReadReq mshr uncacheable latency
829system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129131.411108 # average ReadReq mshr uncacheable latency
830system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average overall mshr uncacheable latency
831system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129131.411108 # average overall mshr uncacheable latency
832system.cpu.l2cache.tags.replacements 96490 # number of replacements
833system.cpu.l2cache.tags.tagsinuse 65016.669962 # Cycle average of tags in use
834system.cpu.l2cache.tags.total_refs 7024998 # Total number of references to valid blocks.
835system.cpu.l2cache.tags.sampled_refs 161737 # Sample count of references to valid blocks.
836system.cpu.l2cache.tags.avg_refs 43.434700 # Average number of references to valid blocks.
837system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
838system.cpu.l2cache.tags.occ_blocks::writebacks 47281.634154 # Average occupied blocks per requestor
839system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 66.002490 # Average occupied blocks per requestor
--- 13 unchanged lines hidden (view full) ---
853system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
854system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2277 # Occupied blocks per task id
855system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6859 # Occupied blocks per task id
856system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55942 # Occupied blocks per task id
857system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000824 # Percentage of cache occupancy per task id
858system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994766 # Percentage of cache occupancy per task id
859system.cpu.l2cache.tags.tag_accesses 60430282 # Number of tag accesses
860system.cpu.l2cache.tags.data_accesses 60430282 # Number of data accesses
861system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 71969 # number of ReadReq hits
862system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4812 # number of ReadReq hits
863system.cpu.l2cache.ReadReq_hits::total 76781 # number of ReadReq hits
864system.cpu.l2cache.WritebackDirty_hits::writebacks 699681 # number of WritebackDirty hits
865system.cpu.l2cache.WritebackDirty_hits::total 699681 # number of WritebackDirty hits
866system.cpu.l2cache.WritebackClean_hits::writebacks 2843248 # number of WritebackClean hits
867system.cpu.l2cache.WritebackClean_hits::total 2843248 # number of WritebackClean hits
868system.cpu.l2cache.UpgradeReq_hits::cpu.data 49 # number of UpgradeReq hits
--- 264 unchanged lines hidden (view full) ---
1133system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100299.892695 # average overall mshr uncacheable latency
1134system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 101096.856292 # average overall mshr uncacheable latency
1135system.cpu.toL2Bus.snoop_filter.tot_requests 7506242 # Total number of requests made to the snoop filter.
1136system.cpu.toL2Bus.snoop_filter.hit_single_requests 3768367 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1137system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58373 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1138system.cpu.toL2Bus.snoop_filter.tot_snoops 592 # Total number of snoops made to the snoop filter.
1139system.cpu.toL2Bus.snoop_filter.hit_single_snoops 592 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1140system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1141system.cpu.toL2Bus.trans_dist::ReadReq 134878 # Transaction distribution
1142system.cpu.toL2Bus.trans_dist::ReadResp 3577264 # Transaction distribution
1143system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution
1144system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution
1145system.cpu.toL2Bus.trans_dist::WritebackDirty 823992 # Transaction distribution
1146system.cpu.toL2Bus.trans_dist::WritebackClean 2894371 # Transaction distribution
1147system.cpu.toL2Bus.trans_dist::CleanEvict 151399 # Transaction distribution
1148system.cpu.toL2Bus.trans_dist::UpgradeReq 2778 # Transaction distribution
--- 33 unchanged lines hidden (view full) ---
1182system.cpu.toL2Bus.respLayer0.occupancy 4348460548 # Layer occupancy (ticks)
1183system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
1184system.cpu.toL2Bus.respLayer1.occupancy 1310984681 # Layer occupancy (ticks)
1185system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1186system.cpu.toL2Bus.respLayer2.occupancy 11196996 # Layer occupancy (ticks)
1187system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1188system.cpu.toL2Bus.respLayer3.occupancy 88824919 # Layer occupancy (ticks)
1189system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1190system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
1191system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
1192system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
1193system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
1194system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
1195system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
1196system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
1197system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
--- 78 unchanged lines hidden (view full) ---
1276system.iobus.reqLayer24.occupancy 34107000 # Layer occupancy (ticks)
1277system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1278system.iobus.reqLayer25.occupancy 187147502 # Layer occupancy (ticks)
1279system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1280system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
1281system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1282system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks)
1283system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1284system.iocache.tags.replacements 36424 # number of replacements
1285system.iocache.tags.tagsinuse 1.037066 # Cycle average of tags in use
1286system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1287system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
1288system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1289system.iocache.tags.warmup_cycle 274806935000 # Cycle when the warmup percentage was hit.
1290system.iocache.tags.occ_blocks::realview.ide 1.037066 # Average occupied blocks per requestor
1291system.iocache.tags.occ_percent::realview.ide 0.064817 # Average percentage of cache occupancy
1292system.iocache.tags.occ_percent::total 0.064817 # Average percentage of cache occupancy
1293system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1294system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1295system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1296system.iocache.tags.tag_accesses 328122 # Number of tag accesses
1297system.iocache.tags.data_accesses 328122 # Number of data accesses
1298system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
1299system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
1300system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
1301system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
1302system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses
1303system.iocache.demand_misses::total 36458 # number of demand (read+write) misses
1304system.iocache.overall_misses::realview.ide 36458 # number of overall misses
1305system.iocache.overall_misses::total 36458 # number of overall misses
--- 64 unchanged lines hidden (view full) ---
1370system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74185.371795 # average ReadReq mshr miss latency
1371system.iocache.ReadReq_avg_mshr_miss_latency::total 74185.371795 # average ReadReq mshr miss latency
1372system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75539.742160 # average WriteLineReq mshr miss latency
1373system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75539.742160 # average WriteLineReq mshr miss latency
1374system.iocache.demand_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency
1375system.iocache.demand_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency
1376system.iocache.overall_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency
1377system.iocache.overall_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency
1378system.membus.trans_dist::ReadReq 34891 # Transaction distribution
1379system.membus.trans_dist::ReadResp 72400 # Transaction distribution
1380system.membus.trans_dist::WriteReq 27583 # Transaction distribution
1381system.membus.trans_dist::WriteResp 27583 # Transaction distribution
1382system.membus.trans_dist::WritebackDirty 124302 # Transaction distribution
1383system.membus.trans_dist::CleanEvict 8612 # Transaction distribution
1384system.membus.trans_dist::UpgradeReq 4581 # Transaction distribution
1385system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
--- 37 unchanged lines hidden (view full) ---
1423system.membus.reqLayer2.occupancy 1702000 # Layer occupancy (ticks)
1424system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1425system.membus.reqLayer5.occupancy 879699870 # Layer occupancy (ticks)
1426system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1427system.membus.respLayer2.occupancy 990225250 # Layer occupancy (ticks)
1428system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1429system.membus.respLayer3.occupancy 1263123 # Layer occupancy (ticks)
1430system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1431system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
1432system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
1433system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
1434system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
1435system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
1436system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
1437system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1438system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1439system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1440system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1441system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1442system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1443system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
1444system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
--- 15 unchanged lines hidden (view full) ---
1460system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1461system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1462system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1463system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1464system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1465system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1466system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
1467system.realview.ethernet.droppedPackets 0 # number of packets dropped
1468system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
1469system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
1470system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
1471system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
1472
1473---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.858505 # Number of seconds simulated
4sim_ticks 2858505242500 # Number of ticks simulated
5final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 125507 # Simulator instruction rate (inst/s)
8host_op_rate 151748 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 3206183180 # Simulator tick rate (ticks/s)
10host_mem_usage 578080 # Number of bytes of host memory used
11host_seconds 891.56 # Real time elapsed on the host
12sim_insts 111897168 # Number of instructions simulated
13sim_ops 135292215 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.inst 1705984 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.data 9156972 # Number of bytes read from this memory
20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
21system.physmem.bytes_read::total 10871852 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 1705984 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 1705984 # Number of instructions bytes read from this memory
--- 283 unchanged lines hidden (view full) ---
307system.physmem_1.preBackEnergy 1640445162750 # Energy for precharge background per rank (pJ)
308system.physmem_1.totalEnergy 1913635982970 # Total energy per rank (pJ)
309system.physmem_1.averagePower 669.453685 # Core power per rank (mW)
310system.physmem_1.memoryStateTime::IDLE 2728879759500 # Time in different power states
311system.physmem_1.memoryStateTime::REF 95451720000 # Time in different power states
312system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
313system.physmem_1.memoryStateTime::ACT 34173617000 # Time in different power states
314system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
315system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory
316system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory
317system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory
318system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory
319system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
320system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
321system.realview.nvmem.bw_read::cpu.inst 179 # Total read bandwidth from this memory (bytes/s)
322system.realview.nvmem.bw_read::total 179 # Total read bandwidth from this memory (bytes/s)
323system.realview.nvmem.bw_inst_read::cpu.inst 179 # Instruction read bandwidth from this memory (bytes/s)
324system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s)
325system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s)
326system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s)
327system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
328system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
329system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
330system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
331system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
332system.cf0.dma_write_txs 631 # Number of DMA write transactions.
333system.cpu.branchPred.lookups 30988279 # Number of BP lookups
334system.cpu.branchPred.condPredicted 16810499 # Number of conditional branches predicted
--- 4 unchanged lines hidden (view full) ---
339system.cpu.branchPred.BTBHitPct 55.936168 # BTB Hit Percentage
340system.cpu.branchPred.usedRAS 7863209 # Number of times the RAS was used to get a target.
341system.cpu.branchPred.RASInCorrect 1506080 # Number of incorrect RAS predictions.
342system.cpu.branchPred.indirectLookups 3044381 # Number of indirect predictor lookups.
343system.cpu.branchPred.indirectHits 2857246 # Number of indirect target hits.
344system.cpu.branchPred.indirectMisses 187135 # Number of indirect misses.
345system.cpu.branchPredindirectMispredicted 108257 # Number of mispredicted indirect branches.
346system.cpu_clk_domain.clock 500 # Clock period in ticks
347system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
348system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
349system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
350system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
351system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
352system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
353system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
354system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
368system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
369system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
370system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
371system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
372system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
373system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
374system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
375system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
376system.cpu.dtb.walker.walks 66151 # Table walker walks requested
377system.cpu.dtb.walker.walksShort 66151 # Table walker walks initiated with short descriptors
378system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43510 # Level at which table walker walks with short descriptors terminate
379system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22641 # Level at which table walker walks with short descriptors terminate
380system.cpu.dtb.walker.walkWaitTime::samples 66151 # Table walker wait (enqueue to first request) latency
381system.cpu.dtb.walker.walkWaitTime::0 66151 100.00% 100.00% # Table walker wait (enqueue to first request) latency
382system.cpu.dtb.walker.walkWaitTime::total 66151 # Table walker wait (enqueue to first request) latency
383system.cpu.dtb.walker.walkCompletionTime::samples 7866 # Table walker service (enqueue to completion) latency
--- 33 unchanged lines hidden (view full) ---
417system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
418system.cpu.dtb.perms_faults 754 # Number of TLB faults due to permissions restrictions
419system.cpu.dtb.read_accesses 24770191 # DTB read accesses
420system.cpu.dtb.write_accesses 19431197 # DTB write accesses
421system.cpu.dtb.inst_accesses 0 # ITB inst accesses
422system.cpu.dtb.hits 44135237 # DTB hits
423system.cpu.dtb.misses 66151 # DTB misses
424system.cpu.dtb.accesses 44201388 # DTB accesses
425system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
426system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
427system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
428system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
429system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
430system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
431system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
432system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
446system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
447system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
448system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
449system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
450system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
451system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
452system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
453system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
454system.cpu.itb.walker.walks 5761 # Table walker walks requested
455system.cpu.itb.walker.walksShort 5761 # Table walker walks initiated with short descriptors
456system.cpu.itb.walker.walksShortTerminationLevel::Level1 327 # Level at which table walker walks with short descriptors terminate
457system.cpu.itb.walker.walksShortTerminationLevel::Level2 5434 # Level at which table walker walks with short descriptors terminate
458system.cpu.itb.walker.walkWaitTime::samples 5761 # Table walker wait (enqueue to first request) latency
459system.cpu.itb.walker.walkWaitTime::0 5761 100.00% 100.00% # Table walker wait (enqueue to first request) latency
460system.cpu.itb.walker.walkWaitTime::total 5761 # Table walker wait (enqueue to first request) latency
461system.cpu.itb.walker.walkCompletionTime::samples 3206 # Table walker service (enqueue to completion) latency
--- 33 unchanged lines hidden (view full) ---
495system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
496system.cpu.itb.perms_faults 8365 # Number of TLB faults due to permissions restrictions
497system.cpu.itb.read_accesses 0 # DTB read accesses
498system.cpu.itb.write_accesses 0 # DTB write accesses
499system.cpu.itb.inst_accesses 57339683 # ITB inst accesses
500system.cpu.itb.hits 57333922 # DTB hits
501system.cpu.itb.misses 5761 # DTB misses
502system.cpu.itb.accesses 57339683 # DTB accesses
503system.cpu.numCycles 332822103 # number of cpu cycles simulated
504system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
505system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
506system.cpu.committedInsts 111897168 # Number of instructions committed
507system.cpu.committedOps 135292215 # Number of ops (including micro ops) committed
508system.cpu.discardedOps 7734017 # Number of ops (including micro ops) which were discarded before commit
509system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching
510system.cpu.quiesceCycles 5384249089 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
--- 33 unchanged lines hidden (view full) ---
544system.cpu.op_class_0::MemWrite 20252013 14.97% 100.00% # Class of committed instruction
545system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
546system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
547system.cpu.op_class_0::total 135292215 # Class of committed instruction
548system.cpu.kern.inst.arm 0 # number of arm instructions executed
549system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed
550system.cpu.tickCycles 228131430 # Number of cycles that the object actually ticked
551system.cpu.idleCycles 104690673 # Total number of cycles that the object has spent stopped
552system.cpu.dcache.tags.replacements 842468 # number of replacements
553system.cpu.dcache.tags.tagsinuse 511.899803 # Cycle average of tags in use
554system.cpu.dcache.tags.total_refs 42541759 # Total number of references to valid blocks.
555system.cpu.dcache.tags.sampled_refs 842980 # Sample count of references to valid blocks.
556system.cpu.dcache.tags.avg_refs 50.465917 # Average number of references to valid blocks.
557system.cpu.dcache.tags.warmup_cycle 594757500 # Cycle when the warmup percentage was hit.
558system.cpu.dcache.tags.occ_blocks::cpu.data 511.899803 # Average occupied blocks per requestor
559system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy
560system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy
561system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
562system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
563system.cpu.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id
564system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id
565system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
566system.cpu.dcache.tags.tag_accesses 175934555 # Number of tag accesses
567system.cpu.dcache.tags.data_accesses 175934555 # Number of data accesses
568system.cpu.dcache.ReadReq_hits::cpu.data 23016255 # number of ReadReq hits
569system.cpu.dcache.ReadReq_hits::total 23016255 # number of ReadReq hits
570system.cpu.dcache.WriteReq_hits::cpu.data 18262413 # number of WriteReq hits
571system.cpu.dcache.WriteReq_hits::total 18262413 # number of WriteReq hits
572system.cpu.dcache.SoftPFReq_hits::cpu.data 356302 # number of SoftPFReq hits
573system.cpu.dcache.SoftPFReq_hits::total 356302 # number of SoftPFReq hits
574system.cpu.dcache.LoadLockedReq_hits::cpu.data 443705 # number of LoadLockedReq hits
575system.cpu.dcache.LoadLockedReq_hits::total 443705 # number of LoadLockedReq hits
--- 152 unchanged lines hidden (view full) ---
728system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35925.580551 # average overall mshr miss latency
729system.cpu.dcache.demand_avg_mshr_miss_latency::total 35925.580551 # average overall mshr miss latency
730system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32760.298800 # average overall mshr miss latency
731system.cpu.dcache.overall_avg_mshr_miss_latency::total 32760.298800 # average overall mshr miss latency
732system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201679.548959 # average ReadReq mshr uncacheable latency
733system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201679.548959 # average ReadReq mshr uncacheable latency
734system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106928.531280 # average overall mshr uncacheable latency
735system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106928.531280 # average overall mshr uncacheable latency
736system.cpu.icache.tags.replacements 2894371 # number of replacements
737system.cpu.icache.tags.tagsinuse 511.208818 # Cycle average of tags in use
738system.cpu.icache.tags.total_refs 54430342 # Total number of references to valid blocks.
739system.cpu.icache.tags.sampled_refs 2894883 # Sample count of references to valid blocks.
740system.cpu.icache.tags.avg_refs 18.802260 # Average number of references to valid blocks.
741system.cpu.icache.tags.warmup_cycle 18407091500 # Cycle when the warmup percentage was hit.
742system.cpu.icache.tags.occ_blocks::cpu.inst 511.208818 # Average occupied blocks per requestor
743system.cpu.icache.tags.occ_percent::cpu.inst 0.998455 # Average percentage of cache occupancy
744system.cpu.icache.tags.occ_percent::total 0.998455 # Average percentage of cache occupancy
745system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
746system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
747system.cpu.icache.tags.age_task_id_blocks_1024::1 201 # Occupied blocks per task id
748system.cpu.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id
749system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
750system.cpu.icache.tags.tag_accesses 60220131 # Number of tag accesses
751system.cpu.icache.tags.data_accesses 60220131 # Number of data accesses
752system.cpu.icache.ReadReq_hits::cpu.inst 54430342 # number of ReadReq hits
753system.cpu.icache.ReadReq_hits::total 54430342 # number of ReadReq hits
754system.cpu.icache.demand_hits::cpu.inst 54430342 # number of demand (read+write) hits
755system.cpu.icache.demand_hits::total 54430342 # number of demand (read+write) hits
756system.cpu.icache.overall_hits::cpu.inst 54430342 # number of overall hits
757system.cpu.icache.overall_hits::total 54430342 # number of overall hits
758system.cpu.icache.ReadReq_misses::cpu.inst 2894895 # number of ReadReq misses
759system.cpu.icache.ReadReq_misses::total 2894895 # number of ReadReq misses
--- 64 unchanged lines hidden (view full) ---
824system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12973.899744 # average overall mshr miss latency
825system.cpu.icache.demand_avg_mshr_miss_latency::total 12973.899744 # average overall mshr miss latency
826system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12973.899744 # average overall mshr miss latency
827system.cpu.icache.overall_avg_mshr_miss_latency::total 12973.899744 # average overall mshr miss latency
828system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average ReadReq mshr uncacheable latency
829system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129131.411108 # average ReadReq mshr uncacheable latency
830system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average overall mshr uncacheable latency
831system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129131.411108 # average overall mshr uncacheable latency
832system.cpu.l2cache.tags.replacements 96490 # number of replacements
833system.cpu.l2cache.tags.tagsinuse 65016.669962 # Cycle average of tags in use
834system.cpu.l2cache.tags.total_refs 7024998 # Total number of references to valid blocks.
835system.cpu.l2cache.tags.sampled_refs 161737 # Sample count of references to valid blocks.
836system.cpu.l2cache.tags.avg_refs 43.434700 # Average number of references to valid blocks.
837system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
838system.cpu.l2cache.tags.occ_blocks::writebacks 47281.634154 # Average occupied blocks per requestor
839system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 66.002490 # Average occupied blocks per requestor
--- 13 unchanged lines hidden (view full) ---
853system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
854system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2277 # Occupied blocks per task id
855system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6859 # Occupied blocks per task id
856system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55942 # Occupied blocks per task id
857system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000824 # Percentage of cache occupancy per task id
858system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994766 # Percentage of cache occupancy per task id
859system.cpu.l2cache.tags.tag_accesses 60430282 # Number of tag accesses
860system.cpu.l2cache.tags.data_accesses 60430282 # Number of data accesses
861system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 71969 # number of ReadReq hits
862system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4812 # number of ReadReq hits
863system.cpu.l2cache.ReadReq_hits::total 76781 # number of ReadReq hits
864system.cpu.l2cache.WritebackDirty_hits::writebacks 699681 # number of WritebackDirty hits
865system.cpu.l2cache.WritebackDirty_hits::total 699681 # number of WritebackDirty hits
866system.cpu.l2cache.WritebackClean_hits::writebacks 2843248 # number of WritebackClean hits
867system.cpu.l2cache.WritebackClean_hits::total 2843248 # number of WritebackClean hits
868system.cpu.l2cache.UpgradeReq_hits::cpu.data 49 # number of UpgradeReq hits
--- 264 unchanged lines hidden (view full) ---
1133system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100299.892695 # average overall mshr uncacheable latency
1134system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 101096.856292 # average overall mshr uncacheable latency
1135system.cpu.toL2Bus.snoop_filter.tot_requests 7506242 # Total number of requests made to the snoop filter.
1136system.cpu.toL2Bus.snoop_filter.hit_single_requests 3768367 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1137system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58373 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1138system.cpu.toL2Bus.snoop_filter.tot_snoops 592 # Total number of snoops made to the snoop filter.
1139system.cpu.toL2Bus.snoop_filter.hit_single_snoops 592 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1140system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1141system.cpu.toL2Bus.trans_dist::ReadReq 134878 # Transaction distribution
1142system.cpu.toL2Bus.trans_dist::ReadResp 3577264 # Transaction distribution
1143system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution
1144system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution
1145system.cpu.toL2Bus.trans_dist::WritebackDirty 823992 # Transaction distribution
1146system.cpu.toL2Bus.trans_dist::WritebackClean 2894371 # Transaction distribution
1147system.cpu.toL2Bus.trans_dist::CleanEvict 151399 # Transaction distribution
1148system.cpu.toL2Bus.trans_dist::UpgradeReq 2778 # Transaction distribution
--- 33 unchanged lines hidden (view full) ---
1182system.cpu.toL2Bus.respLayer0.occupancy 4348460548 # Layer occupancy (ticks)
1183system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
1184system.cpu.toL2Bus.respLayer1.occupancy 1310984681 # Layer occupancy (ticks)
1185system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1186system.cpu.toL2Bus.respLayer2.occupancy 11196996 # Layer occupancy (ticks)
1187system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1188system.cpu.toL2Bus.respLayer3.occupancy 88824919 # Layer occupancy (ticks)
1189system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1190system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
1191system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
1192system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
1193system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
1194system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
1195system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
1196system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
1197system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
--- 78 unchanged lines hidden (view full) ---
1276system.iobus.reqLayer24.occupancy 34107000 # Layer occupancy (ticks)
1277system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1278system.iobus.reqLayer25.occupancy 187147502 # Layer occupancy (ticks)
1279system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1280system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
1281system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1282system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks)
1283system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1284system.iocache.tags.replacements 36424 # number of replacements
1285system.iocache.tags.tagsinuse 1.037066 # Cycle average of tags in use
1286system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1287system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
1288system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1289system.iocache.tags.warmup_cycle 274806935000 # Cycle when the warmup percentage was hit.
1290system.iocache.tags.occ_blocks::realview.ide 1.037066 # Average occupied blocks per requestor
1291system.iocache.tags.occ_percent::realview.ide 0.064817 # Average percentage of cache occupancy
1292system.iocache.tags.occ_percent::total 0.064817 # Average percentage of cache occupancy
1293system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1294system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1295system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1296system.iocache.tags.tag_accesses 328122 # Number of tag accesses
1297system.iocache.tags.data_accesses 328122 # Number of data accesses
1298system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
1299system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
1300system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
1301system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
1302system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses
1303system.iocache.demand_misses::total 36458 # number of demand (read+write) misses
1304system.iocache.overall_misses::realview.ide 36458 # number of overall misses
1305system.iocache.overall_misses::total 36458 # number of overall misses
--- 64 unchanged lines hidden (view full) ---
1370system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74185.371795 # average ReadReq mshr miss latency
1371system.iocache.ReadReq_avg_mshr_miss_latency::total 74185.371795 # average ReadReq mshr miss latency
1372system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75539.742160 # average WriteLineReq mshr miss latency
1373system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75539.742160 # average WriteLineReq mshr miss latency
1374system.iocache.demand_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency
1375system.iocache.demand_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency
1376system.iocache.overall_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency
1377system.iocache.overall_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency
1378system.membus.trans_dist::ReadReq 34891 # Transaction distribution
1379system.membus.trans_dist::ReadResp 72400 # Transaction distribution
1380system.membus.trans_dist::WriteReq 27583 # Transaction distribution
1381system.membus.trans_dist::WriteResp 27583 # Transaction distribution
1382system.membus.trans_dist::WritebackDirty 124302 # Transaction distribution
1383system.membus.trans_dist::CleanEvict 8612 # Transaction distribution
1384system.membus.trans_dist::UpgradeReq 4581 # Transaction distribution
1385system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
--- 37 unchanged lines hidden (view full) ---
1423system.membus.reqLayer2.occupancy 1702000 # Layer occupancy (ticks)
1424system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1425system.membus.reqLayer5.occupancy 879699870 # Layer occupancy (ticks)
1426system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1427system.membus.respLayer2.occupancy 990225250 # Layer occupancy (ticks)
1428system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1429system.membus.respLayer3.occupancy 1263123 # Layer occupancy (ticks)
1430system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1431system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
1432system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
1433system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
1434system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
1435system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
1436system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
1437system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1438system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1439system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1440system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1441system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1442system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1443system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
1444system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
--- 15 unchanged lines hidden (view full) ---
1460system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1461system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1462system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1463system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1464system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1465system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1466system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
1467system.realview.ethernet.droppedPackets 0 # number of packets dropped
1468system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
1469system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
1470system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
1471system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
1472
1473---------- End Simulation Statistics ----------