1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.852796 # Number of seconds simulated
4sim_ticks 2852795541500 # Number of ticks simulated
5final_tick 2852795541500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 152327 # Simulator instruction rate (inst/s)
8host_op_rate 184181 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 3876544573 # Simulator tick rate (ticks/s)
10host_mem_usage 573860 # Number of bytes of host memory used
11host_seconds 735.91 # Real time elapsed on the host
12sim_insts 112099513 # Number of instructions simulated
13sim_ops 135541235 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.dtb.walker 7488 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.inst 1672384 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.data 9151084 # Number of bytes read from this memory
20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
21system.physmem.bytes_read::total 10831980 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 1672384 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 1672384 # Number of instructions bytes read from this memory
24system.physmem.bytes_written::writebacks 7949952 # Number of bytes written to this memory
25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
26system.physmem.bytes_written::total 7967476 # Number of bytes written to this memory
27system.physmem.num_reads::cpu.dtb.walker 117 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.inst 26131 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.data 143507 # Number of read requests responded to by this memory
31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 169771 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 124218 # Number of write requests responded to by this memory
34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
35system.physmem.num_writes::total 128599 # Number of write requests responded to by this memory
36system.physmem.bw_read::cpu.dtb.walker 2625 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.inst 586226 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.data 3207760 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::total 3796970 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu.inst 586226 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 586226 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 2786723 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::total 2792866 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_total::writebacks 2786723 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.dtb.walker 2625 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.inst 586226 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.data 3213903 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::total 6589836 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.readReqs 169771 # Number of read requests accepted
55system.physmem.writeReqs 164823 # Number of write requests accepted
56system.physmem.readBursts 169771 # Number of DRAM read bursts, including those serviced by the write queue
57system.physmem.writeBursts 164823 # Number of DRAM write bursts, including those merged in the write queue
58system.physmem.bytesReadDRAM 10857344 # Total number of bytes read from DRAM
59system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue
60system.physmem.bytesWritten 9026432 # Total number of bytes written to DRAM
61system.physmem.bytesReadSys 10831980 # Total read bytes from the system interface side
62system.physmem.bytesWrittenSys 10285812 # Total written bytes from the system interface side
63system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue
64system.physmem.mergedWrBursts 23760 # Number of DRAM write bursts merged with an existing one
65system.physmem.neitherReadNorWriteReqs 4596 # Number of requests that are neither read nor write
66system.physmem.perBankRdBursts::0 10712 # Per bank write bursts
67system.physmem.perBankRdBursts::1 10437 # Per bank write bursts
68system.physmem.perBankRdBursts::2 10571 # Per bank write bursts
69system.physmem.perBankRdBursts::3 10533 # Per bank write bursts
70system.physmem.perBankRdBursts::4 13317 # Per bank write bursts
71system.physmem.perBankRdBursts::5 10551 # Per bank write bursts
72system.physmem.perBankRdBursts::6 11242 # Per bank write bursts
73system.physmem.perBankRdBursts::7 11054 # Per bank write bursts
74system.physmem.perBankRdBursts::8 10299 # Per bank write bursts
75system.physmem.perBankRdBursts::9 10415 # Per bank write bursts
76system.physmem.perBankRdBursts::10 10045 # Per bank write bursts
77system.physmem.perBankRdBursts::11 9308 # Per bank write bursts
78system.physmem.perBankRdBursts::12 10198 # Per bank write bursts
79system.physmem.perBankRdBursts::13 10751 # Per bank write bursts
80system.physmem.perBankRdBursts::14 10066 # Per bank write bursts
81system.physmem.perBankRdBursts::15 10147 # Per bank write bursts
82system.physmem.perBankWrBursts::0 8889 # Per bank write bursts
83system.physmem.perBankWrBursts::1 8834 # Per bank write bursts
84system.physmem.perBankWrBursts::2 9167 # Per bank write bursts
85system.physmem.perBankWrBursts::3 9119 # Per bank write bursts
86system.physmem.perBankWrBursts::4 8534 # Per bank write bursts
87system.physmem.perBankWrBursts::5 8844 # Per bank write bursts
88system.physmem.perBankWrBursts::6 9286 # Per bank write bursts
89system.physmem.perBankWrBursts::7 9148 # Per bank write bursts
90system.physmem.perBankWrBursts::8 9054 # Per bank write bursts
91system.physmem.perBankWrBursts::9 9024 # Per bank write bursts
92system.physmem.perBankWrBursts::10 8594 # Per bank write bursts
93system.physmem.perBankWrBursts::11 8355 # Per bank write bursts
94system.physmem.perBankWrBursts::12 8781 # Per bank write bursts
95system.physmem.perBankWrBursts::13 8812 # Per bank write bursts
96system.physmem.perBankWrBursts::14 8169 # Per bank write bursts
97system.physmem.perBankWrBursts::15 8428 # Per bank write bursts
98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
99system.physmem.numWrRetry 51 # Number of times write queue was full causing retry
100system.physmem.totGap 2852795136500 # Total gap between requests
101system.physmem.readPktSize::0 0 # Read request sizes (log2)
102system.physmem.readPktSize::1 0 # Read request sizes (log2)
103system.physmem.readPktSize::2 543 # Read request sizes (log2)
104system.physmem.readPktSize::3 14 # Read request sizes (log2)
105system.physmem.readPktSize::4 0 # Read request sizes (log2)
106system.physmem.readPktSize::5 0 # Read request sizes (log2)
107system.physmem.readPktSize::6 169214 # Read request sizes (log2)
108system.physmem.writePktSize::0 0 # Write request sizes (log2)
109system.physmem.writePktSize::1 0 # Write request sizes (log2)
110system.physmem.writePktSize::2 4381 # Write request sizes (log2)
111system.physmem.writePktSize::3 0 # Write request sizes (log2)
112system.physmem.writePktSize::4 0 # Write request sizes (log2)
113system.physmem.writePktSize::5 0 # Write request sizes (log2)
114system.physmem.writePktSize::6 160442 # Write request sizes (log2)
115system.physmem.rdQLenPdf::0 162758 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::1 6597 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::2 279 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see

--- 28 unchanged lines hidden (view full) ---

154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::15 1516 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::16 1699 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::17 5280 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::18 5852 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::19 5924 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::20 5946 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::21 6342 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::22 6398 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::23 7894 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::24 6370 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::25 6428 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::26 7866 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::27 6812 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::28 6543 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::29 8817 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::30 7197 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::31 6972 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::32 6804 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::33 1271 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::34 983 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::35 1250 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::36 2382 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::37 2008 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::38 1709 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::39 1835 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::40 2187 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::41 1851 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::42 1900 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::43 1690 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::44 1804 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::45 1636 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::46 1366 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::47 1353 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::48 1187 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::49 764 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::50 515 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::51 464 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::52 320 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::53 251 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::54 245 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::55 214 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::56 240 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::57 178 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::58 160 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::59 125 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::60 125 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::61 139 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::62 87 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::63 149 # What write queue length does an incoming req see
211system.physmem.bytesPerActivate::samples 61582 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::mean 322.881881 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::gmean 189.150015 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::stdev 338.764187 # Bytes accessed per row activation
215system.physmem.bytesPerActivate::0-127 22212 36.07% 36.07% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::128-255 14518 23.58% 59.64% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::256-383 6522 10.59% 70.23% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::384-511 3539 5.75% 75.98% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::512-639 2583 4.19% 80.18% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::640-767 1569 2.55% 82.72% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::768-895 1183 1.92% 84.64% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::896-1023 1177 1.91% 86.56% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::1024-1151 8279 13.44% 100.00% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::total 61582 # Bytes accessed per row activation
225system.physmem.rdPerTurnAround::samples 5853 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::mean 28.981890 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::stdev 585.529205 # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::0-2047 5852 99.98% 99.98% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::total 5853 # Reads before turning the bus around for writes
231system.physmem.wrPerTurnAround::samples 5853 # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::mean 24.096703 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::gmean 18.379226 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::stdev 43.965113 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::16-31 5522 94.34% 94.34% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::32-47 97 1.66% 96.00% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::48-63 18 0.31% 96.31% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::64-79 12 0.21% 96.51% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::80-95 21 0.36% 96.87% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::96-111 25 0.43% 97.30% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::112-127 23 0.39% 97.69% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::128-143 16 0.27% 97.97% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::144-159 12 0.21% 98.17% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::160-175 2 0.03% 98.21% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::176-191 16 0.27% 98.48% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::192-207 11 0.19% 98.67% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::208-223 11 0.19% 98.86% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::224-239 5 0.09% 98.94% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::240-255 1 0.02% 98.96% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::256-271 1 0.02% 98.97% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::272-287 1 0.02% 98.99% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::288-303 9 0.15% 99.15% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::304-319 6 0.10% 99.25% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::320-335 2 0.03% 99.28% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::336-351 7 0.12% 99.40% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::352-367 16 0.27% 99.68% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::368-383 1 0.02% 99.69% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::384-399 2 0.03% 99.73% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::400-415 4 0.07% 99.79% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::416-431 1 0.02% 99.81% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::432-447 3 0.05% 99.86% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::448-463 1 0.02% 99.88% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::512-527 1 0.02% 99.90% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::544-559 1 0.02% 99.91% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::560-575 2 0.03% 99.95% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::688-703 2 0.03% 99.98% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::total 5853 # Writes before turning the bus around for reads
269system.physmem.totQLat 1681739444 # Total ticks spent queuing
270system.physmem.totMemAccLat 4862601944 # Total ticks spent from burst creation until serviced by the DRAM
271system.physmem.totBusLat 848230000 # Total ticks spent in databus transfers
272system.physmem.avgQLat 9913.23 # Average queueing delay per DRAM burst
273system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
274system.physmem.avgMemAccLat 28663.23 # Average memory access latency per DRAM burst
275system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s
276system.physmem.avgWrBW 3.16 # Average achieved write bandwidth in MiByte/s
277system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s
278system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s
279system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
280system.physmem.busUtil 0.05 # Data bus utilization in percentage
281system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
282system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
283system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
284system.physmem.avgWrQLen 25.33 # Average write queue length when enqueuing
285system.physmem.readRowHits 140075 # Number of row buffer hits during reads
286system.physmem.writeRowHits 109026 # Number of row buffer hits during writes
287system.physmem.readRowHitRate 82.57 # Row buffer hit rate for reads
288system.physmem.writeRowHitRate 77.29 # Row buffer hit rate for writes
289system.physmem.avgGap 8526139.55 # Average gap between requests
290system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined
291system.physmem_0.actEnergy 241398360 # Energy for activate commands per rank (pJ)
292system.physmem_0.preEnergy 131715375 # Energy for precharge commands per rank (pJ)
293system.physmem_0.readEnergy 689652600 # Energy for read commands per rank (pJ)
294system.physmem_0.writeEnergy 465400080 # Energy for write commands per rank (pJ)
295system.physmem_0.refreshEnergy 186330281280 # Energy for refresh commands per rank (pJ)
296system.physmem_0.actBackEnergy 83595060855 # Energy for active background per rank (pJ)
297system.physmem_0.preBackEnergy 1638344286000 # Energy for precharge background per rank (pJ)
298system.physmem_0.totalEnergy 1909797794550 # Total energy per rank (pJ)
299system.physmem_0.averagePower 669.449413 # Core power per rank (mW)
300system.physmem_0.memoryStateTime::IDLE 2725393996990 # Time in different power states
301system.physmem_0.memoryStateTime::REF 95260880000 # Time in different power states
302system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
303system.physmem_0.memoryStateTime::ACT 32133948010 # Time in different power states
304system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
305system.physmem_1.actEnergy 224161560 # Energy for activate commands per rank (pJ)
306system.physmem_1.preEnergy 122310375 # Energy for precharge commands per rank (pJ)
307system.physmem_1.readEnergy 633578400 # Energy for read commands per rank (pJ)
308system.physmem_1.writeEnergy 448526160 # Energy for write commands per rank (pJ)
309system.physmem_1.refreshEnergy 186330281280 # Energy for refresh commands per rank (pJ)
310system.physmem_1.actBackEnergy 82127793645 # Energy for active background per rank (pJ)
311system.physmem_1.preBackEnergy 1639631362500 # Energy for precharge background per rank (pJ)
312system.physmem_1.totalEnergy 1909518013920 # Total energy per rank (pJ)
313system.physmem_1.averagePower 669.351340 # Core power per rank (mW)
314system.physmem_1.memoryStateTime::IDLE 2727553667240 # Time in different power states
315system.physmem_1.memoryStateTime::REF 95260880000 # Time in different power states
316system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
317system.physmem_1.memoryStateTime::ACT 29980898760 # Time in different power states
318system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
319system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory
320system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
321system.realview.nvmem.bytes_inst_read::cpu.inst 448 # Number of instructions bytes read from this memory
322system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
323system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory
324system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
325system.realview.nvmem.bw_read::cpu.inst 157 # Total read bandwidth from this memory (bytes/s)
326system.realview.nvmem.bw_read::total 157 # Total read bandwidth from this memory (bytes/s)
327system.realview.nvmem.bw_inst_read::cpu.inst 157 # Instruction read bandwidth from this memory (bytes/s)
328system.realview.nvmem.bw_inst_read::total 157 # Instruction read bandwidth from this memory (bytes/s)
329system.realview.nvmem.bw_total::cpu.inst 157 # Total bandwidth to/from this memory (bytes/s)
330system.realview.nvmem.bw_total::total 157 # Total bandwidth to/from this memory (bytes/s)
331system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
332system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
333system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
334system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
335system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
336system.cf0.dma_write_txs 631 # Number of DMA write transactions.
337system.cpu.branchPred.lookups 31028841 # Number of BP lookups
338system.cpu.branchPred.condPredicted 16848703 # Number of conditional branches predicted
339system.cpu.branchPred.condIncorrect 2523288 # Number of conditional branches incorrect
340system.cpu.branchPred.BTBLookups 18558243 # Number of BTB lookups
341system.cpu.branchPred.BTBHits 13348746 # Number of BTB hits
342system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
343system.cpu.branchPred.BTBHitPct 71.928932 # BTB Hit Percentage
344system.cpu.branchPred.usedRAS 7829101 # Number of times the RAS was used to get a target.
345system.cpu.branchPred.RASInCorrect 1515846 # Number of incorrect RAS predictions.
346system.cpu_clk_domain.clock 500 # Clock period in ticks
347system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
348system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
349system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
350system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
351system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
352system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
353system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

368system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
369system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
370system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
371system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
372system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
373system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
374system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
375system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
376system.cpu.dtb.walker.walks 66007 # Table walker walks requested
377system.cpu.dtb.walker.walksShort 66007 # Table walker walks initiated with short descriptors
378system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43361 # Level at which table walker walks with short descriptors terminate
379system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22646 # Level at which table walker walks with short descriptors terminate
380system.cpu.dtb.walker.walkWaitTime::samples 66007 # Table walker wait (enqueue to first request) latency
381system.cpu.dtb.walker.walkWaitTime::0 66007 100.00% 100.00% # Table walker wait (enqueue to first request) latency
382system.cpu.dtb.walker.walkWaitTime::total 66007 # Table walker wait (enqueue to first request) latency
383system.cpu.dtb.walker.walkCompletionTime::samples 7799 # Table walker service (enqueue to completion) latency
384system.cpu.dtb.walker.walkCompletionTime::mean 11136.363636 # Table walker service (enqueue to completion) latency
385system.cpu.dtb.walker.walkCompletionTime::gmean 8861.352080 # Table walker service (enqueue to completion) latency
386system.cpu.dtb.walker.walkCompletionTime::stdev 7418.451261 # Table walker service (enqueue to completion) latency
387system.cpu.dtb.walker.walkCompletionTime::0-16383 6073 77.87% 77.87% # Table walker service (enqueue to completion) latency
388system.cpu.dtb.walker.walkCompletionTime::16384-32767 1719 22.04% 99.91% # Table walker service (enqueue to completion) latency
389system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.92% # Table walker service (enqueue to completion) latency
390system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.97% # Table walker service (enqueue to completion) latency
391system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
392system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
393system.cpu.dtb.walker.walkCompletionTime::total 7799 # Table walker service (enqueue to completion) latency
394system.cpu.dtb.walker.walksPending::samples 262515000 # Table walker pending requests distribution
395system.cpu.dtb.walker.walksPending::0 262515000 100.00% 100.00% # Table walker pending requests distribution
396system.cpu.dtb.walker.walksPending::total 262515000 # Table walker pending requests distribution
397system.cpu.dtb.walker.walkPageSizes::4K 6423 82.36% 82.36% # Table walker page sizes translated
398system.cpu.dtb.walker.walkPageSizes::1M 1376 17.64% 100.00% # Table walker page sizes translated
399system.cpu.dtb.walker.walkPageSizes::total 7799 # Table walker page sizes translated
400system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66007 # Table walker requests started/completed, data/inst
401system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
402system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66007 # Table walker requests started/completed, data/inst
403system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7799 # Table walker requests started/completed, data/inst
404system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
405system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7799 # Table walker requests started/completed, data/inst
406system.cpu.dtb.walker.walkRequestOrigin::total 73806 # Table walker requests started/completed, data/inst
407system.cpu.dtb.inst_hits 0 # ITB inst hits
408system.cpu.dtb.inst_misses 0 # ITB inst misses
409system.cpu.dtb.read_hits 24765986 # DTB read hits
410system.cpu.dtb.read_misses 59321 # DTB read misses
411system.cpu.dtb.write_hits 19441821 # DTB write hits
412system.cpu.dtb.write_misses 6686 # DTB write misses
413system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
414system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
415system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
416system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
417system.cpu.dtb.flush_entries 4350 # Number of entries that have been flushed from TLB
418system.cpu.dtb.align_faults 1269 # Number of TLB faults due to alignment restrictions
419system.cpu.dtb.prefetch_faults 1784 # Number of TLB faults due to prefetch
420system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
421system.cpu.dtb.perms_faults 729 # Number of TLB faults due to permissions restrictions
422system.cpu.dtb.read_accesses 24825307 # DTB read accesses
423system.cpu.dtb.write_accesses 19448507 # DTB write accesses
424system.cpu.dtb.inst_accesses 0 # ITB inst accesses
425system.cpu.dtb.hits 44207807 # DTB hits
426system.cpu.dtb.misses 66007 # DTB misses
427system.cpu.dtb.accesses 44273814 # DTB accesses
428system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
429system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
430system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
431system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
432system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
433system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
434system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
435system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

449system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
450system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
451system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
452system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
453system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
454system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
455system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
456system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
457system.cpu.itb.walker.walks 5444 # Table walker walks requested
458system.cpu.itb.walker.walksShort 5444 # Table walker walks initiated with short descriptors
459system.cpu.itb.walker.walksShortTerminationLevel::Level1 317 # Level at which table walker walks with short descriptors terminate
460system.cpu.itb.walker.walksShortTerminationLevel::Level2 5127 # Level at which table walker walks with short descriptors terminate
461system.cpu.itb.walker.walkWaitTime::samples 5444 # Table walker wait (enqueue to first request) latency
462system.cpu.itb.walker.walkWaitTime::0 5444 100.00% 100.00% # Table walker wait (enqueue to first request) latency
463system.cpu.itb.walker.walkWaitTime::total 5444 # Table walker wait (enqueue to first request) latency
464system.cpu.itb.walker.walkCompletionTime::samples 3189 # Table walker service (enqueue to completion) latency
465system.cpu.itb.walker.walkCompletionTime::mean 11300.094073 # Table walker service (enqueue to completion) latency
466system.cpu.itb.walker.walkCompletionTime::gmean 9048.158428 # Table walker service (enqueue to completion) latency
467system.cpu.itb.walker.walkCompletionTime::stdev 7023.995661 # Table walker service (enqueue to completion) latency
468system.cpu.itb.walker.walkCompletionTime::0-8191 1265 39.67% 39.67% # Table walker service (enqueue to completion) latency
469system.cpu.itb.walker.walkCompletionTime::8192-16383 1207 37.85% 77.52% # Table walker service (enqueue to completion) latency
470system.cpu.itb.walker.walkCompletionTime::16384-24575 716 22.45% 99.97% # Table walker service (enqueue to completion) latency
471system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
472system.cpu.itb.walker.walkCompletionTime::total 3189 # Table walker service (enqueue to completion) latency
473system.cpu.itb.walker.walksPending::samples 262109500 # Table walker pending requests distribution
474system.cpu.itb.walker.walksPending::0 262109500 100.00% 100.00% # Table walker pending requests distribution
475system.cpu.itb.walker.walksPending::total 262109500 # Table walker pending requests distribution
476system.cpu.itb.walker.walkPageSizes::4K 2879 90.28% 90.28% # Table walker page sizes translated
477system.cpu.itb.walker.walkPageSizes::1M 310 9.72% 100.00% # Table walker page sizes translated
478system.cpu.itb.walker.walkPageSizes::total 3189 # Table walker page sizes translated
479system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
480system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5444 # Table walker requests started/completed, data/inst
481system.cpu.itb.walker.walkRequestOrigin_Requested::total 5444 # Table walker requests started/completed, data/inst
482system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
483system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3189 # Table walker requests started/completed, data/inst
484system.cpu.itb.walker.walkRequestOrigin_Completed::total 3189 # Table walker requests started/completed, data/inst
485system.cpu.itb.walker.walkRequestOrigin::total 8633 # Table walker requests started/completed, data/inst
486system.cpu.itb.inst_hits 57608448 # ITB inst hits
487system.cpu.itb.inst_misses 5444 # ITB inst misses
488system.cpu.itb.read_hits 0 # DTB read hits
489system.cpu.itb.read_misses 0 # DTB read misses
490system.cpu.itb.write_hits 0 # DTB write hits
491system.cpu.itb.write_misses 0 # DTB write misses
492system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
493system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
494system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
495system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
496system.cpu.itb.flush_entries 2978 # Number of entries that have been flushed from TLB
497system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
498system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
499system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
500system.cpu.itb.perms_faults 8408 # Number of TLB faults due to permissions restrictions
501system.cpu.itb.read_accesses 0 # DTB read accesses
502system.cpu.itb.write_accesses 0 # DTB write accesses
503system.cpu.itb.inst_accesses 57613892 # ITB inst accesses
504system.cpu.itb.hits 57608448 # DTB hits
505system.cpu.itb.misses 5444 # DTB misses
506system.cpu.itb.accesses 57613892 # DTB accesses
507system.cpu.numCycles 315454477 # number of cpu cycles simulated
508system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
509system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
510system.cpu.committedInsts 112099513 # Number of instructions committed
511system.cpu.committedOps 135541235 # Number of ops (including micro ops) committed
512system.cpu.discardedOps 7725935 # Number of ops (including micro ops) which were discarded before commit
513system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching
514system.cpu.quiesceCycles 5390197145 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
515system.cpu.cpi 2.814058 # CPI: cycles per instruction
516system.cpu.ipc 0.355359 # IPC: instructions per cycle
517system.cpu.kern.inst.arm 0 # number of arm instructions executed
518system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed
519system.cpu.tickCycles 227606231 # Number of cycles that the object actually ticked
520system.cpu.idleCycles 87848246 # Total number of cycles that the object has spent stopped
521system.cpu.dcache.tags.replacements 842088 # number of replacements
522system.cpu.dcache.tags.tagsinuse 511.947851 # Cycle average of tags in use
523system.cpu.dcache.tags.total_refs 42623753 # Total number of references to valid blocks.
524system.cpu.dcache.tags.sampled_refs 842600 # Sample count of references to valid blocks.
525system.cpu.dcache.tags.avg_refs 50.585987 # Average number of references to valid blocks.
526system.cpu.dcache.tags.warmup_cycle 313221250 # Cycle when the warmup percentage was hit.
527system.cpu.dcache.tags.occ_blocks::cpu.data 511.947851 # Average occupied blocks per requestor
528system.cpu.dcache.tags.occ_percent::cpu.data 0.999898 # Average percentage of cache occupancy
529system.cpu.dcache.tags.occ_percent::total 0.999898 # Average percentage of cache occupancy
530system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
531system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
532system.cpu.dcache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id
533system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id
534system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
535system.cpu.dcache.tags.tag_accesses 176253823 # Number of tag accesses
536system.cpu.dcache.tags.data_accesses 176253823 # Number of data accesses
537system.cpu.dcache.ReadReq_hits::cpu.data 23074723 # number of ReadReq hits
538system.cpu.dcache.ReadReq_hits::total 23074723 # number of ReadReq hits
539system.cpu.dcache.WriteReq_hits::cpu.data 18285747 # number of WriteReq hits
540system.cpu.dcache.WriteReq_hits::total 18285747 # number of WriteReq hits
541system.cpu.dcache.SoftPFReq_hits::cpu.data 356646 # number of SoftPFReq hits
542system.cpu.dcache.SoftPFReq_hits::total 356646 # number of SoftPFReq hits
543system.cpu.dcache.LoadLockedReq_hits::cpu.data 443503 # number of LoadLockedReq hits
544system.cpu.dcache.LoadLockedReq_hits::total 443503 # number of LoadLockedReq hits
545system.cpu.dcache.StoreCondReq_hits::cpu.data 460198 # number of StoreCondReq hits
546system.cpu.dcache.StoreCondReq_hits::total 460198 # number of StoreCondReq hits
547system.cpu.dcache.demand_hits::cpu.data 41360470 # number of demand (read+write) hits
548system.cpu.dcache.demand_hits::total 41360470 # number of demand (read+write) hits
549system.cpu.dcache.overall_hits::cpu.data 41717116 # number of overall hits
550system.cpu.dcache.overall_hits::total 41717116 # number of overall hits
551system.cpu.dcache.ReadReq_misses::cpu.data 491782 # number of ReadReq misses
552system.cpu.dcache.ReadReq_misses::total 491782 # number of ReadReq misses
553system.cpu.dcache.WriteReq_misses::cpu.data 547820 # number of WriteReq misses
554system.cpu.dcache.WriteReq_misses::total 547820 # number of WriteReq misses
555system.cpu.dcache.SoftPFReq_misses::cpu.data 169860 # number of SoftPFReq misses
556system.cpu.dcache.SoftPFReq_misses::total 169860 # number of SoftPFReq misses
557system.cpu.dcache.LoadLockedReq_misses::cpu.data 22518 # number of LoadLockedReq misses
558system.cpu.dcache.LoadLockedReq_misses::total 22518 # number of LoadLockedReq misses
559system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
560system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
561system.cpu.dcache.demand_misses::cpu.data 1039602 # number of demand (read+write) misses
562system.cpu.dcache.demand_misses::total 1039602 # number of demand (read+write) misses
563system.cpu.dcache.overall_misses::cpu.data 1209462 # number of overall misses
564system.cpu.dcache.overall_misses::total 1209462 # number of overall misses
565system.cpu.dcache.ReadReq_miss_latency::cpu.data 7264308005 # number of ReadReq miss cycles
566system.cpu.dcache.ReadReq_miss_latency::total 7264308005 # number of ReadReq miss cycles
567system.cpu.dcache.WriteReq_miss_latency::cpu.data 23337097788 # number of WriteReq miss cycles
568system.cpu.dcache.WriteReq_miss_latency::total 23337097788 # number of WriteReq miss cycles
569system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 285724000 # number of LoadLockedReq miss cycles
570system.cpu.dcache.LoadLockedReq_miss_latency::total 285724000 # number of LoadLockedReq miss cycles
571system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles
572system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles
573system.cpu.dcache.demand_miss_latency::cpu.data 30601405793 # number of demand (read+write) miss cycles
574system.cpu.dcache.demand_miss_latency::total 30601405793 # number of demand (read+write) miss cycles
575system.cpu.dcache.overall_miss_latency::cpu.data 30601405793 # number of overall miss cycles
576system.cpu.dcache.overall_miss_latency::total 30601405793 # number of overall miss cycles
577system.cpu.dcache.ReadReq_accesses::cpu.data 23566505 # number of ReadReq accesses(hits+misses)
578system.cpu.dcache.ReadReq_accesses::total 23566505 # number of ReadReq accesses(hits+misses)
579system.cpu.dcache.WriteReq_accesses::cpu.data 18833567 # number of WriteReq accesses(hits+misses)
580system.cpu.dcache.WriteReq_accesses::total 18833567 # number of WriteReq accesses(hits+misses)
581system.cpu.dcache.SoftPFReq_accesses::cpu.data 526506 # number of SoftPFReq accesses(hits+misses)
582system.cpu.dcache.SoftPFReq_accesses::total 526506 # number of SoftPFReq accesses(hits+misses)
583system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466021 # number of LoadLockedReq accesses(hits+misses)
584system.cpu.dcache.LoadLockedReq_accesses::total 466021 # number of LoadLockedReq accesses(hits+misses)
585system.cpu.dcache.StoreCondReq_accesses::cpu.data 460200 # number of StoreCondReq accesses(hits+misses)
586system.cpu.dcache.StoreCondReq_accesses::total 460200 # number of StoreCondReq accesses(hits+misses)
587system.cpu.dcache.demand_accesses::cpu.data 42400072 # number of demand (read+write) accesses
588system.cpu.dcache.demand_accesses::total 42400072 # number of demand (read+write) accesses
589system.cpu.dcache.overall_accesses::cpu.data 42926578 # number of overall (read+write) accesses
590system.cpu.dcache.overall_accesses::total 42926578 # number of overall (read+write) accesses
591system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020868 # miss rate for ReadReq accesses
592system.cpu.dcache.ReadReq_miss_rate::total 0.020868 # miss rate for ReadReq accesses
593system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029087 # miss rate for WriteReq accesses
594system.cpu.dcache.WriteReq_miss_rate::total 0.029087 # miss rate for WriteReq accesses
595system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322617 # miss rate for SoftPFReq accesses
596system.cpu.dcache.SoftPFReq_miss_rate::total 0.322617 # miss rate for SoftPFReq accesses
597system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048320 # miss rate for LoadLockedReq accesses
598system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048320 # miss rate for LoadLockedReq accesses
599system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
600system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
601system.cpu.dcache.demand_miss_rate::cpu.data 0.024519 # miss rate for demand accesses
602system.cpu.dcache.demand_miss_rate::total 0.024519 # miss rate for demand accesses
603system.cpu.dcache.overall_miss_rate::cpu.data 0.028175 # miss rate for overall accesses
604system.cpu.dcache.overall_miss_rate::total 0.028175 # miss rate for overall accesses
605system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14771.398719 # average ReadReq miss latency
606system.cpu.dcache.ReadReq_avg_miss_latency::total 14771.398719 # average ReadReq miss latency
607system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42599.937549 # average WriteReq miss latency
608system.cpu.dcache.WriteReq_avg_miss_latency::total 42599.937549 # average WriteReq miss latency
609system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12688.693490 # average LoadLockedReq miss latency
610system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12688.693490 # average LoadLockedReq miss latency
611system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency
612system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency
613system.cpu.dcache.demand_avg_miss_latency::cpu.data 29435.693461 # average overall miss latency
614system.cpu.dcache.demand_avg_miss_latency::total 29435.693461 # average overall miss latency
615system.cpu.dcache.overall_avg_miss_latency::cpu.data 25301.667843 # average overall miss latency
616system.cpu.dcache.overall_avg_miss_latency::total 25301.667843 # average overall miss latency
617system.cpu.dcache.blocked_cycles::no_mshrs 252 # number of cycles access was blocked
618system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
619system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
620system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
621system.cpu.dcache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked
622system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
623system.cpu.dcache.fast_writes 0 # number of fast writes performed
624system.cpu.dcache.cache_copies 0 # number of cache copies performed
625system.cpu.dcache.writebacks::writebacks 697883 # number of writebacks
626system.cpu.dcache.writebacks::total 697883 # number of writebacks
627system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74969 # number of ReadReq MSHR hits
628system.cpu.dcache.ReadReq_mshr_hits::total 74969 # number of ReadReq MSHR hits
629system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249041 # number of WriteReq MSHR hits
630system.cpu.dcache.WriteReq_mshr_hits::total 249041 # number of WriteReq MSHR hits
631system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14294 # number of LoadLockedReq MSHR hits
632system.cpu.dcache.LoadLockedReq_mshr_hits::total 14294 # number of LoadLockedReq MSHR hits
633system.cpu.dcache.demand_mshr_hits::cpu.data 324010 # number of demand (read+write) MSHR hits
634system.cpu.dcache.demand_mshr_hits::total 324010 # number of demand (read+write) MSHR hits
635system.cpu.dcache.overall_mshr_hits::cpu.data 324010 # number of overall MSHR hits
636system.cpu.dcache.overall_mshr_hits::total 324010 # number of overall MSHR hits
637system.cpu.dcache.ReadReq_mshr_misses::cpu.data 416813 # number of ReadReq MSHR misses
638system.cpu.dcache.ReadReq_mshr_misses::total 416813 # number of ReadReq MSHR misses
639system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298779 # number of WriteReq MSHR misses
640system.cpu.dcache.WriteReq_mshr_misses::total 298779 # number of WriteReq MSHR misses
641system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121645 # number of SoftPFReq MSHR misses
642system.cpu.dcache.SoftPFReq_mshr_misses::total 121645 # number of SoftPFReq MSHR misses
643system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8224 # number of LoadLockedReq MSHR misses
644system.cpu.dcache.LoadLockedReq_mshr_misses::total 8224 # number of LoadLockedReq MSHR misses
645system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
646system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
647system.cpu.dcache.demand_mshr_misses::cpu.data 715592 # number of demand (read+write) MSHR misses
648system.cpu.dcache.demand_mshr_misses::total 715592 # number of demand (read+write) MSHR misses
649system.cpu.dcache.overall_mshr_misses::cpu.data 837237 # number of overall MSHR misses
650system.cpu.dcache.overall_mshr_misses::total 837237 # number of overall MSHR misses
651system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable
652system.cpu.dcache.ReadReq_mshr_uncacheable::total 31128 # number of ReadReq MSHR uncacheable
653system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable
654system.cpu.dcache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable
655system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
656system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses
657system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5688327646 # number of ReadReq MSHR miss cycles
658system.cpu.dcache.ReadReq_mshr_miss_latency::total 5688327646 # number of ReadReq MSHR miss cycles
659system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12278776156 # number of WriteReq MSHR miss cycles
660system.cpu.dcache.WriteReq_mshr_miss_latency::total 12278776156 # number of WriteReq MSHR miss cycles
661system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1560607790 # number of SoftPFReq MSHR miss cycles
662system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1560607790 # number of SoftPFReq MSHR miss cycles
663system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 106146500 # number of LoadLockedReq MSHR miss cycles
664system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 106146500 # number of LoadLockedReq MSHR miss cycles
665system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles
666system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles
667system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17967103802 # number of demand (read+write) MSHR miss cycles
668system.cpu.dcache.demand_mshr_miss_latency::total 17967103802 # number of demand (read+write) MSHR miss cycles
669system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19527711592 # number of overall MSHR miss cycles
670system.cpu.dcache.overall_mshr_miss_latency::total 19527711592 # number of overall MSHR miss cycles
671system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5837082750 # number of ReadReq MSHR uncacheable cycles
672system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5837082750 # number of ReadReq MSHR uncacheable cycles
673system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4510053000 # number of WriteReq MSHR uncacheable cycles
674system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4510053000 # number of WriteReq MSHR uncacheable cycles
675system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10347135750 # number of overall MSHR uncacheable cycles
676system.cpu.dcache.overall_mshr_uncacheable_latency::total 10347135750 # number of overall MSHR uncacheable cycles
677system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017687 # mshr miss rate for ReadReq accesses
678system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017687 # mshr miss rate for ReadReq accesses
679system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015864 # mshr miss rate for WriteReq accesses
680system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015864 # mshr miss rate for WriteReq accesses
681system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231042 # mshr miss rate for SoftPFReq accesses
682system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231042 # mshr miss rate for SoftPFReq accesses
683system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017647 # mshr miss rate for LoadLockedReq accesses
684system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017647 # mshr miss rate for LoadLockedReq accesses
685system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
686system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
687system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016877 # mshr miss rate for demand accesses
688system.cpu.dcache.demand_mshr_miss_rate::total 0.016877 # mshr miss rate for demand accesses
689system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019504 # mshr miss rate for overall accesses
690system.cpu.dcache.overall_mshr_miss_rate::total 0.019504 # mshr miss rate for overall accesses
691system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13647.193456 # average ReadReq mshr miss latency
692system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13647.193456 # average ReadReq mshr miss latency
693system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41096.516676 # average WriteReq mshr miss latency
694system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41096.516676 # average WriteReq mshr miss latency
695system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12829.197994 # average SoftPFReq mshr miss latency
696system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12829.197994 # average SoftPFReq mshr miss latency
697system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12906.918774 # average LoadLockedReq mshr miss latency
698system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12906.918774 # average LoadLockedReq mshr miss latency
699system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81250 # average StoreCondReq mshr miss latency
700system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81250 # average StoreCondReq mshr miss latency
701system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25108.027762 # average overall mshr miss latency
702system.cpu.dcache.demand_avg_mshr_miss_latency::total 25108.027762 # average overall mshr miss latency
703system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23323.994988 # average overall mshr miss latency
704system.cpu.dcache.overall_avg_mshr_miss_latency::total 23323.994988 # average overall mshr miss latency
705system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187518.721087 # average ReadReq mshr uncacheable latency
706system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187518.721087 # average ReadReq mshr uncacheable latency
707system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163508.429105 # average WriteReq mshr uncacheable latency
708system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163508.429105 # average WriteReq mshr uncacheable latency
709system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176238.451909 # average overall mshr uncacheable latency
710system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176238.451909 # average overall mshr uncacheable latency
711system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
712system.cpu.icache.tags.replacements 2896868 # number of replacements
713system.cpu.icache.tags.tagsinuse 511.399912 # Cycle average of tags in use
714system.cpu.icache.tags.total_refs 54702268 # Total number of references to valid blocks.
715system.cpu.icache.tags.sampled_refs 2897380 # Sample count of references to valid blocks.
716system.cpu.icache.tags.avg_refs 18.879908 # Average number of references to valid blocks.
717system.cpu.icache.tags.warmup_cycle 15532248250 # Cycle when the warmup percentage was hit.
718system.cpu.icache.tags.occ_blocks::cpu.inst 511.399912 # Average occupied blocks per requestor
719system.cpu.icache.tags.occ_percent::cpu.inst 0.998828 # Average percentage of cache occupancy
720system.cpu.icache.tags.occ_percent::total 0.998828 # Average percentage of cache occupancy
721system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
722system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
723system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
724system.cpu.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id
725system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
726system.cpu.icache.tags.tag_accesses 60497051 # Number of tag accesses
727system.cpu.icache.tags.data_accesses 60497051 # Number of data accesses
728system.cpu.icache.ReadReq_hits::cpu.inst 54702268 # number of ReadReq hits
729system.cpu.icache.ReadReq_hits::total 54702268 # number of ReadReq hits
730system.cpu.icache.demand_hits::cpu.inst 54702268 # number of demand (read+write) hits
731system.cpu.icache.demand_hits::total 54702268 # number of demand (read+write) hits
732system.cpu.icache.overall_hits::cpu.inst 54702268 # number of overall hits
733system.cpu.icache.overall_hits::total 54702268 # number of overall hits
734system.cpu.icache.ReadReq_misses::cpu.inst 2897392 # number of ReadReq misses
735system.cpu.icache.ReadReq_misses::total 2897392 # number of ReadReq misses
736system.cpu.icache.demand_misses::cpu.inst 2897392 # number of demand (read+write) misses
737system.cpu.icache.demand_misses::total 2897392 # number of demand (read+write) misses
738system.cpu.icache.overall_misses::cpu.inst 2897392 # number of overall misses
739system.cpu.icache.overall_misses::total 2897392 # number of overall misses
740system.cpu.icache.ReadReq_miss_latency::cpu.inst 39291591662 # number of ReadReq miss cycles
741system.cpu.icache.ReadReq_miss_latency::total 39291591662 # number of ReadReq miss cycles
742system.cpu.icache.demand_miss_latency::cpu.inst 39291591662 # number of demand (read+write) miss cycles
743system.cpu.icache.demand_miss_latency::total 39291591662 # number of demand (read+write) miss cycles
744system.cpu.icache.overall_miss_latency::cpu.inst 39291591662 # number of overall miss cycles
745system.cpu.icache.overall_miss_latency::total 39291591662 # number of overall miss cycles
746system.cpu.icache.ReadReq_accesses::cpu.inst 57599660 # number of ReadReq accesses(hits+misses)
747system.cpu.icache.ReadReq_accesses::total 57599660 # number of ReadReq accesses(hits+misses)
748system.cpu.icache.demand_accesses::cpu.inst 57599660 # number of demand (read+write) accesses
749system.cpu.icache.demand_accesses::total 57599660 # number of demand (read+write) accesses
750system.cpu.icache.overall_accesses::cpu.inst 57599660 # number of overall (read+write) accesses
751system.cpu.icache.overall_accesses::total 57599660 # number of overall (read+write) accesses
752system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050302 # miss rate for ReadReq accesses
753system.cpu.icache.ReadReq_miss_rate::total 0.050302 # miss rate for ReadReq accesses
754system.cpu.icache.demand_miss_rate::cpu.inst 0.050302 # miss rate for demand accesses
755system.cpu.icache.demand_miss_rate::total 0.050302 # miss rate for demand accesses
756system.cpu.icache.overall_miss_rate::cpu.inst 0.050302 # miss rate for overall accesses
757system.cpu.icache.overall_miss_rate::total 0.050302 # miss rate for overall accesses
758system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13561.020277 # average ReadReq miss latency
759system.cpu.icache.ReadReq_avg_miss_latency::total 13561.020277 # average ReadReq miss latency
760system.cpu.icache.demand_avg_miss_latency::cpu.inst 13561.020277 # average overall miss latency
761system.cpu.icache.demand_avg_miss_latency::total 13561.020277 # average overall miss latency
762system.cpu.icache.overall_avg_miss_latency::cpu.inst 13561.020277 # average overall miss latency
763system.cpu.icache.overall_avg_miss_latency::total 13561.020277 # average overall miss latency
764system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
765system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
766system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
767system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
768system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
769system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
770system.cpu.icache.fast_writes 0 # number of fast writes performed
771system.cpu.icache.cache_copies 0 # number of cache copies performed
772system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897392 # number of ReadReq MSHR misses
773system.cpu.icache.ReadReq_mshr_misses::total 2897392 # number of ReadReq MSHR misses
774system.cpu.icache.demand_mshr_misses::cpu.inst 2897392 # number of demand (read+write) MSHR misses
775system.cpu.icache.demand_mshr_misses::total 2897392 # number of demand (read+write) MSHR misses
776system.cpu.icache.overall_mshr_misses::cpu.inst 2897392 # number of overall MSHR misses
777system.cpu.icache.overall_mshr_misses::total 2897392 # number of overall MSHR misses
778system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3172 # number of ReadReq MSHR uncacheable
779system.cpu.icache.ReadReq_mshr_uncacheable::total 3172 # number of ReadReq MSHR uncacheable
780system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3172 # number of overall MSHR uncacheable misses
781system.cpu.icache.overall_mshr_uncacheable_misses::total 3172 # number of overall MSHR uncacheable misses
782system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34935956838 # number of ReadReq MSHR miss cycles
783system.cpu.icache.ReadReq_mshr_miss_latency::total 34935956838 # number of ReadReq MSHR miss cycles
784system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34935956838 # number of demand (read+write) MSHR miss cycles
785system.cpu.icache.demand_mshr_miss_latency::total 34935956838 # number of demand (read+write) MSHR miss cycles
786system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34935956838 # number of overall MSHR miss cycles
787system.cpu.icache.overall_mshr_miss_latency::total 34935956838 # number of overall MSHR miss cycles
788system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 247386750 # number of ReadReq MSHR uncacheable cycles
789system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 247386750 # number of ReadReq MSHR uncacheable cycles
790system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 247386750 # number of overall MSHR uncacheable cycles
791system.cpu.icache.overall_mshr_uncacheable_latency::total 247386750 # number of overall MSHR uncacheable cycles
792system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050302 # mshr miss rate for ReadReq accesses
793system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050302 # mshr miss rate for ReadReq accesses
794system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050302 # mshr miss rate for demand accesses
795system.cpu.icache.demand_mshr_miss_rate::total 0.050302 # mshr miss rate for demand accesses
796system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050302 # mshr miss rate for overall accesses
797system.cpu.icache.overall_mshr_miss_rate::total 0.050302 # mshr miss rate for overall accesses
798system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12057.725305 # average ReadReq mshr miss latency
799system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12057.725305 # average ReadReq mshr miss latency
800system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12057.725305 # average overall mshr miss latency
801system.cpu.icache.demand_avg_mshr_miss_latency::total 12057.725305 # average overall mshr miss latency
802system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12057.725305 # average overall mshr miss latency
803system.cpu.icache.overall_avg_mshr_miss_latency::total 12057.725305 # average overall mshr miss latency
804system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77990.778689 # average ReadReq mshr uncacheable latency
805system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77990.778689 # average ReadReq mshr uncacheable latency
806system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77990.778689 # average overall mshr uncacheable latency
807system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77990.778689 # average overall mshr uncacheable latency
808system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
809system.cpu.l2cache.tags.replacements 96519 # number of replacements
810system.cpu.l2cache.tags.tagsinuse 65064.584640 # Cycle average of tags in use
811system.cpu.l2cache.tags.total_refs 4043303 # Total number of references to valid blocks.
812system.cpu.l2cache.tags.sampled_refs 161770 # Sample count of references to valid blocks.
813system.cpu.l2cache.tags.avg_refs 24.994146 # Average number of references to valid blocks.
814system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
815system.cpu.l2cache.tags.occ_blocks::writebacks 47432.807159 # Average occupied blocks per requestor
816system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 63.814603 # Average occupied blocks per requestor
817system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000383 # Average occupied blocks per requestor
818system.cpu.l2cache.tags.occ_blocks::cpu.inst 12239.354143 # Average occupied blocks per requestor
819system.cpu.l2cache.tags.occ_blocks::cpu.data 5328.608352 # Average occupied blocks per requestor
820system.cpu.l2cache.tags.occ_percent::writebacks 0.723767 # Average percentage of cache occupancy
821system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000974 # Average percentage of cache occupancy
822system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
823system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186758 # Average percentage of cache occupancy
824system.cpu.l2cache.tags.occ_percent::cpu.data 0.081308 # Average percentage of cache occupancy
825system.cpu.l2cache.tags.occ_percent::total 0.992807 # Average percentage of cache occupancy
826system.cpu.l2cache.tags.occ_task_id_blocks::1023 39 # Occupied blocks per task id
827system.cpu.l2cache.tags.occ_task_id_blocks::1024 65212 # Occupied blocks per task id
828system.cpu.l2cache.tags.age_task_id_blocks_1023::4 39 # Occupied blocks per task id
829system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
830system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
831system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2301 # Occupied blocks per task id
832system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6950 # Occupied blocks per task id
833system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55839 # Occupied blocks per task id
834system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000595 # Percentage of cache occupancy per task id
835system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995056 # Percentage of cache occupancy per task id
836system.cpu.l2cache.tags.tag_accesses 36587667 # Number of tag accesses
837system.cpu.l2cache.tags.data_accesses 36587667 # Number of data accesses
838system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 70357 # number of ReadReq hits
839system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4500 # number of ReadReq hits
840system.cpu.l2cache.ReadReq_hits::cpu.inst 2874373 # number of ReadReq hits
841system.cpu.l2cache.ReadReq_hits::cpu.data 532417 # number of ReadReq hits
842system.cpu.l2cache.ReadReq_hits::total 3481647 # number of ReadReq hits
843system.cpu.l2cache.Writeback_hits::writebacks 697883 # number of Writeback hits
844system.cpu.l2cache.Writeback_hits::total 697883 # number of Writeback hits
845system.cpu.l2cache.UpgradeReq_hits::cpu.data 51 # number of UpgradeReq hits
846system.cpu.l2cache.UpgradeReq_hits::total 51 # number of UpgradeReq hits
847system.cpu.l2cache.ReadExReq_hits::cpu.data 165019 # number of ReadExReq hits
848system.cpu.l2cache.ReadExReq_hits::total 165019 # number of ReadExReq hits
849system.cpu.l2cache.demand_hits::cpu.dtb.walker 70357 # number of demand (read+write) hits
850system.cpu.l2cache.demand_hits::cpu.itb.walker 4500 # number of demand (read+write) hits
851system.cpu.l2cache.demand_hits::cpu.inst 2874373 # number of demand (read+write) hits
852system.cpu.l2cache.demand_hits::cpu.data 697436 # number of demand (read+write) hits
853system.cpu.l2cache.demand_hits::total 3646666 # number of demand (read+write) hits
854system.cpu.l2cache.overall_hits::cpu.dtb.walker 70357 # number of overall hits
855system.cpu.l2cache.overall_hits::cpu.itb.walker 4500 # number of overall hits
856system.cpu.l2cache.overall_hits::cpu.inst 2874373 # number of overall hits
857system.cpu.l2cache.overall_hits::cpu.data 697436 # number of overall hits
858system.cpu.l2cache.overall_hits::total 3646666 # number of overall hits
859system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 117 # number of ReadReq misses
860system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses
861system.cpu.l2cache.ReadReq_misses::cpu.inst 22990 # number of ReadReq misses
862system.cpu.l2cache.ReadReq_misses::cpu.data 14260 # number of ReadReq misses
863system.cpu.l2cache.ReadReq_misses::total 37368 # number of ReadReq misses
864system.cpu.l2cache.UpgradeReq_misses::cpu.data 2783 # number of UpgradeReq misses
865system.cpu.l2cache.UpgradeReq_misses::total 2783 # number of UpgradeReq misses
866system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
867system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
868system.cpu.l2cache.ReadExReq_misses::cpu.data 130931 # number of ReadExReq misses
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1090system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60444.435687 # average overall mshr uncacheable latency
1091system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162697.509836 # average overall mshr uncacheable latency
1092system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157456.219802 # average overall mshr uncacheable latency
1093system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1094system.cpu.toL2Bus.trans_dist::ReadReq 3577827 # Transaction distribution
1095system.cpu.toL2Bus.trans_dist::ReadResp 3577732 # Transaction distribution
1096system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution
1097system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution
1098system.cpu.toL2Bus.trans_dist::Writeback 697883 # Transaction distribution
1099system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution
1100system.cpu.toL2Bus.trans_dist::UpgradeReq 2834 # Transaction distribution
1101system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1102system.cpu.toL2Bus.trans_dist::UpgradeResp 2836 # Transaction distribution
1103system.cpu.toL2Bus.trans_dist::ReadExReq 295950 # Transaction distribution
1104system.cpu.toL2Bus.trans_dist::ReadExResp 295950 # Transaction distribution
1105system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5801098 # Packet count per connected master and slave (bytes)
1106system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506371 # Packet count per connected master and slave (bytes)
1107system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15072 # Packet count per connected master and slave (bytes)
1108system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159127 # Packet count per connected master and slave (bytes)
1109system.cpu.toL2Bus.pkt_count::total 8481668 # Packet count per connected master and slave (bytes)
1110system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185634176 # Cumulative packet size per connected master and slave (bytes)
1111system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98784669 # Cumulative packet size per connected master and slave (bytes)
1112system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18004 # Cumulative packet size per connected master and slave (bytes)
1113system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 281896 # Cumulative packet size per connected master and slave (bytes)
1114system.cpu.toL2Bus.pkt_size::total 284718745 # Cumulative packet size per connected master and slave (bytes)
1115system.cpu.toL2Bus.snoops 60910 # Total snoops (count)
1116system.cpu.toL2Bus.snoop_fanout::samples 4638337 # Request fanout histogram
1117system.cpu.toL2Bus.snoop_fanout::mean 1.029260 # Request fanout histogram
1118system.cpu.toL2Bus.snoop_fanout::stdev 0.168533 # Request fanout histogram
1119system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1120system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1121system.cpu.toL2Bus.snoop_fanout::1 4502621 97.07% 97.07% # Request fanout histogram
1122system.cpu.toL2Bus.snoop_fanout::2 135716 2.93% 100.00% # Request fanout histogram
1123system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1124system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1125system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1126system.cpu.toL2Bus.snoop_fanout::total 4638337 # Request fanout histogram
1127system.cpu.toL2Bus.reqLayer0.occupancy 3012597000 # Layer occupancy (ticks)
1128system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1129system.cpu.toL2Bus.snoopLayer0.occupancy 210000 # Layer occupancy (ticks)
1130system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1131system.cpu.toL2Bus.respLayer0.occupancy 4356351412 # Layer occupancy (ticks)
1132system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
1133system.cpu.toL2Bus.respLayer1.occupancy 1341303908 # Layer occupancy (ticks)
1134system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1135system.cpu.toL2Bus.respLayer2.occupancy 10571000 # Layer occupancy (ticks)
1136system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1137system.cpu.toL2Bus.respLayer3.occupancy 88656750 # Layer occupancy (ticks)
1138system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1139system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
1140system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
1141system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
1142system.iobus.trans_dist::WriteResp 22790 # Transaction distribution
1143system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
1144system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
1145system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)

--- 80 unchanged lines hidden (view full) ---

1226system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
1227system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1228system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
1229system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1230system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
1231system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1232system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
1233system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1234system.iobus.reqLayer27.occupancy 198957934 # Layer occupancy (ticks)
1235system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1236system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
1237system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1238system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
1239system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1240system.iobus.respLayer3.occupancy 36810010 # Layer occupancy (ticks)
1241system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1242system.iocache.tags.replacements 36424 # number of replacements
1243system.iocache.tags.tagsinuse 1.031201 # Cycle average of tags in use
1244system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1245system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
1246system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1247system.iocache.tags.warmup_cycle 270527174000 # Cycle when the warmup percentage was hit.
1248system.iocache.tags.occ_blocks::realview.ide 1.031201 # Average occupied blocks per requestor
1249system.iocache.tags.occ_percent::realview.ide 0.064450 # Average percentage of cache occupancy
1250system.iocache.tags.occ_percent::total 0.064450 # Average percentage of cache occupancy
1251system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1252system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1253system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1254system.iocache.tags.tag_accesses 328122 # Number of tag accesses
1255system.iocache.tags.data_accesses 328122 # Number of data accesses
1256system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
1257system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
1258system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
1259system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
1260system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses
1261system.iocache.demand_misses::total 234 # number of demand (read+write) misses
1262system.iocache.overall_misses::realview.ide 234 # number of overall misses
1263system.iocache.overall_misses::total 234 # number of overall misses
1264system.iocache.ReadReq_miss_latency::realview.ide 29240377 # number of ReadReq miss cycles
1265system.iocache.ReadReq_miss_latency::total 29240377 # number of ReadReq miss cycles
1266system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6662157547 # number of WriteInvalidateReq miss cycles
1267system.iocache.WriteInvalidateReq_miss_latency::total 6662157547 # number of WriteInvalidateReq miss cycles
1268system.iocache.demand_miss_latency::realview.ide 29240377 # number of demand (read+write) miss cycles
1269system.iocache.demand_miss_latency::total 29240377 # number of demand (read+write) miss cycles
1270system.iocache.overall_miss_latency::realview.ide 29240377 # number of overall miss cycles
1271system.iocache.overall_miss_latency::total 29240377 # number of overall miss cycles
1272system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
1273system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
1274system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
1275system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
1276system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses
1277system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses
1278system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses
1279system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses
1280system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1281system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1282system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
1283system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1284system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1285system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1286system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1287system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1288system.iocache.ReadReq_avg_miss_latency::realview.ide 124958.876068 # average ReadReq miss latency
1289system.iocache.ReadReq_avg_miss_latency::total 124958.876068 # average ReadReq miss latency
1290system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183915.568325 # average WriteInvalidateReq miss latency
1291system.iocache.WriteInvalidateReq_avg_miss_latency::total 183915.568325 # average WriteInvalidateReq miss latency
1292system.iocache.demand_avg_miss_latency::realview.ide 124958.876068 # average overall miss latency
1293system.iocache.demand_avg_miss_latency::total 124958.876068 # average overall miss latency
1294system.iocache.overall_avg_miss_latency::realview.ide 124958.876068 # average overall miss latency
1295system.iocache.overall_avg_miss_latency::total 124958.876068 # average overall miss latency
1296system.iocache.blocked_cycles::no_mshrs 23447 # number of cycles access was blocked
1297system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1298system.iocache.blocked::no_mshrs 3545 # number of cycles access was blocked
1299system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1300system.iocache.avg_blocked_cycles::no_mshrs 6.614104 # average number of cycles each access was blocked
1301system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1302system.iocache.fast_writes 0 # number of fast writes performed
1303system.iocache.cache_copies 0 # number of cache copies performed
1304system.iocache.writebacks::writebacks 36190 # number of writebacks
1305system.iocache.writebacks::total 36190 # number of writebacks
1306system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses
1307system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses
1308system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses
1309system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses
1310system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses
1311system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses
1312system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses
1313system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
1314system.iocache.ReadReq_mshr_miss_latency::realview.ide 16932377 # number of ReadReq MSHR miss cycles
1315system.iocache.ReadReq_mshr_miss_latency::total 16932377 # number of ReadReq MSHR miss cycles
1316system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4778489567 # number of WriteInvalidateReq MSHR miss cycles
1317system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4778489567 # number of WriteInvalidateReq MSHR miss cycles
1318system.iocache.demand_mshr_miss_latency::realview.ide 16932377 # number of demand (read+write) MSHR miss cycles
1319system.iocache.demand_mshr_miss_latency::total 16932377 # number of demand (read+write) MSHR miss cycles
1320system.iocache.overall_mshr_miss_latency::realview.ide 16932377 # number of overall MSHR miss cycles
1321system.iocache.overall_mshr_miss_latency::total 16932377 # number of overall MSHR miss cycles
1322system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1323system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1324system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1325system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1326system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1327system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1328system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1329system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1330system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72360.585470 # average ReadReq mshr miss latency
1331system.iocache.ReadReq_avg_mshr_miss_latency::total 72360.585470 # average ReadReq mshr miss latency
1332system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131915.016757 # average WriteInvalidateReq mshr miss latency
1333system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131915.016757 # average WriteInvalidateReq mshr miss latency
1334system.iocache.demand_avg_mshr_miss_latency::realview.ide 72360.585470 # average overall mshr miss latency
1335system.iocache.demand_avg_mshr_miss_latency::total 72360.585470 # average overall mshr miss latency
1336system.iocache.overall_avg_mshr_miss_latency::realview.ide 72360.585470 # average overall mshr miss latency
1337system.iocache.overall_avg_mshr_miss_latency::total 72360.585470 # average overall mshr miss latency
1338system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1339system.membus.trans_dist::ReadReq 71735 # Transaction distribution
1340system.membus.trans_dist::ReadResp 71735 # Transaction distribution
1341system.membus.trans_dist::WriteReq 27583 # Transaction distribution
1342system.membus.trans_dist::WriteResp 27583 # Transaction distribution
1343system.membus.trans_dist::Writeback 124218 # Transaction distribution
1344system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
1345system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
1346system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution
1347system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1348system.membus.trans_dist::UpgradeResp 4598 # Transaction distribution
1349system.membus.trans_dist::ReadExReq 129118 # Transaction distribution
1350system.membus.trans_dist::ReadExResp 129118 # Transaction distribution
1351system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
1352system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
1353system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes)
1354system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445781 # Packet count per connected master and slave (bytes)
1355system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553341 # Packet count per connected master and slave (bytes)
1356system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes)
1357system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes)
1358system.membus.pkt_count::total 662228 # Packet count per connected master and slave (bytes)
1359system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
1360system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
1361system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes)
1362system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16482336 # Cumulative packet size per connected master and slave (bytes)
1363system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16646045 # Cumulative packet size per connected master and slave (bytes)
1364system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
1365system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
1366system.membus.pkt_size::total 21281501 # Cumulative packet size per connected master and slave (bytes)
1367system.membus.snoops 506 # Total snoops (count)
1368system.membus.snoop_fanout::samples 393527 # Request fanout histogram
1369system.membus.snoop_fanout::mean 1 # Request fanout histogram
1370system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1371system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1372system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1373system.membus.snoop_fanout::1 393527 100.00% 100.00% # Request fanout histogram
1374system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1375system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1376system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1377system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1378system.membus.snoop_fanout::total 393527 # Request fanout histogram
1379system.membus.reqLayer0.occupancy 90546500 # Layer occupancy (ticks)
1380system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1381system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
1382system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1383system.membus.reqLayer2.occupancy 1706500 # Layer occupancy (ticks)
1384system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1385system.membus.reqLayer5.occupancy 1023221651 # Layer occupancy (ticks)
1386system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1387system.membus.respLayer2.occupancy 996325444 # Layer occupancy (ticks)
1388system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1389system.membus.respLayer3.occupancy 37473990 # Layer occupancy (ticks)
1390system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1391system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1392system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1393system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1394system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1395system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1396system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1397system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR

--- 26 unchanged lines hidden ---