1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.853442 # Number of seconds simulated
4sim_ticks 2853442108500 # Number of ticks simulated
5final_tick 2853442108500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 171765 # Simulator instruction rate (inst/s)
8host_op_rate 207684 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 4374009836 # Simulator tick rate (ticks/s)
10host_mem_usage 619996 # Number of bytes of host memory used
11host_seconds 652.36 # Real time elapsed on the host
12sim_insts 112053421 # Number of instructions simulated
13sim_ops 135485276 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.dtb.walker 7296 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.inst 1671680 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.data 9169380 # Number of bytes read from this memory
20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
21system.physmem.bytes_read::total 10849380 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 1671680 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 1671680 # Number of instructions bytes read from this memory
24system.physmem.bytes_written::writebacks 7972992 # Number of bytes written to this memory
25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
26system.physmem.bytes_written::total 7990516 # Number of bytes written to this memory
27system.physmem.num_reads::cpu.dtb.walker 114 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.inst 26120 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.data 143791 # Number of read requests responded to by this memory
31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 170041 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 124578 # Number of write requests responded to by this memory
34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
35system.physmem.num_writes::total 128959 # Number of write requests responded to by this memory
36system.physmem.bw_read::cpu.dtb.walker 2557 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.inst 585847 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.data 3213445 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::total 3802208 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu.inst 585847 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 585847 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 2794166 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::cpu.data 6141 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::total 2800308 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_total::writebacks 2794166 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.dtb.walker 2557 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.inst 585847 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.data 3219587 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::total 6602516 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.readReqs 170041 # Number of read requests accepted
55system.physmem.writeReqs 165183 # Number of write requests accepted
56system.physmem.readBursts 170041 # Number of DRAM read bursts, including those serviced by the write queue
57system.physmem.writeBursts 165183 # Number of DRAM write bursts, including those merged in the write queue
58system.physmem.bytesReadDRAM 10875008 # Total number of bytes read from DRAM
59system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue
60system.physmem.bytesWritten 9072064 # Total number of bytes written to DRAM
61system.physmem.bytesReadSys 10849380 # Total read bytes from the system interface side
62system.physmem.bytesWrittenSys 10308852 # Total written bytes from the system interface side
63system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue
64system.physmem.mergedWrBursts 23407 # Number of DRAM write bursts merged with an existing one
65system.physmem.neitherReadNorWriteReqs 4604 # Number of requests that are neither read nor write
66system.physmem.perBankRdBursts::0 10431 # Per bank write bursts
67system.physmem.perBankRdBursts::1 10779 # Per bank write bursts
68system.physmem.perBankRdBursts::2 11040 # Per bank write bursts
69system.physmem.perBankRdBursts::3 10735 # Per bank write bursts
70system.physmem.perBankRdBursts::4 13061 # Per bank write bursts
71system.physmem.perBankRdBursts::5 10390 # Per bank write bursts
72system.physmem.perBankRdBursts::6 11080 # Per bank write bursts
73system.physmem.perBankRdBursts::7 11267 # Per bank write bursts
74system.physmem.perBankRdBursts::8 10153 # Per bank write bursts
75system.physmem.perBankRdBursts::9 10232 # Per bank write bursts
76system.physmem.perBankRdBursts::10 10264 # Per bank write bursts
77system.physmem.perBankRdBursts::11 9394 # Per bank write bursts
78system.physmem.perBankRdBursts::12 10277 # Per bank write bursts
79system.physmem.perBankRdBursts::13 10799 # Per bank write bursts
80system.physmem.perBankRdBursts::14 10090 # Per bank write bursts
81system.physmem.perBankRdBursts::15 9930 # Per bank write bursts
82system.physmem.perBankWrBursts::0 8676 # Per bank write bursts
83system.physmem.perBankWrBursts::1 9067 # Per bank write bursts
84system.physmem.perBankWrBursts::2 9547 # Per bank write bursts
85system.physmem.perBankWrBursts::3 9319 # Per bank write bursts
86system.physmem.perBankWrBursts::4 8434 # Per bank write bursts
87system.physmem.perBankWrBursts::5 8678 # Per bank write bursts
88system.physmem.perBankWrBursts::6 9214 # Per bank write bursts
89system.physmem.perBankWrBursts::7 9423 # Per bank write bursts
90system.physmem.perBankWrBursts::8 8918 # Per bank write bursts
91system.physmem.perBankWrBursts::9 8886 # Per bank write bursts
92system.physmem.perBankWrBursts::10 8752 # Per bank write bursts
93system.physmem.perBankWrBursts::11 8449 # Per bank write bursts
94system.physmem.perBankWrBursts::12 8824 # Per bank write bursts
95system.physmem.perBankWrBursts::13 8894 # Per bank write bursts
96system.physmem.perBankWrBursts::14 8297 # Per bank write bursts
97system.physmem.perBankWrBursts::15 8373 # Per bank write bursts
98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
99system.physmem.numWrRetry 40 # Number of times write queue was full causing retry
100system.physmem.totGap 2853441702500 # Total gap between requests
101system.physmem.readPktSize::0 0 # Read request sizes (log2)
102system.physmem.readPktSize::1 0 # Read request sizes (log2)
103system.physmem.readPktSize::2 541 # Read request sizes (log2)
104system.physmem.readPktSize::3 14 # Read request sizes (log2)
105system.physmem.readPktSize::4 0 # Read request sizes (log2)
106system.physmem.readPktSize::5 0 # Read request sizes (log2)
107system.physmem.readPktSize::6 169486 # Read request sizes (log2)
108system.physmem.writePktSize::0 0 # Write request sizes (log2)
109system.physmem.writePktSize::1 0 # Write request sizes (log2)
110system.physmem.writePktSize::2 4381 # Write request sizes (log2)
111system.physmem.writePktSize::3 0 # Write request sizes (log2)
112system.physmem.writePktSize::4 0 # Write request sizes (log2)
113system.physmem.writePktSize::5 0 # Write request sizes (log2)
114system.physmem.writePktSize::6 160802 # Write request sizes (log2)
115system.physmem.rdQLenPdf::0 163468 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::1 6406 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see

--- 28 unchanged lines hidden (view full) ---

154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::15 1516 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::16 1813 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::17 5347 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::18 6005 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::19 6027 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::20 5842 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::21 6230 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::22 6324 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::23 7720 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::24 6542 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::25 6696 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::26 7845 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::27 6904 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::28 6687 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::29 8673 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::30 7583 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::31 6877 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::32 6843 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::33 1218 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::34 1028 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::35 1305 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::36 2232 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::37 2241 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::38 1757 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::39 1803 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::40 2628 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::41 2085 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::42 1860 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::43 1791 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::44 1847 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::45 1817 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::46 1379 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::47 1327 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::48 1020 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::49 736 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::50 354 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::51 280 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::52 202 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::53 187 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::54 175 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::55 123 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::56 130 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::58 172 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::59 121 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::60 68 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::61 93 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::62 53 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::63 100 # What write queue length does an incoming req see
211system.physmem.bytesPerActivate::samples 61793 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::mean 322.802648 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::gmean 189.147121 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::stdev 338.470119 # Bytes accessed per row activation
215system.physmem.bytesPerActivate::0-127 22296 36.08% 36.08% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::128-255 14465 23.41% 59.49% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::256-383 6637 10.74% 70.23% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::384-511 3539 5.73% 75.96% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::512-639 2616 4.23% 80.19% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::640-767 1600 2.59% 82.78% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::768-895 1149 1.86% 84.64% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::896-1023 1212 1.96% 86.60% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::1024-1151 8279 13.40% 100.00% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::total 61793 # Bytes accessed per row activation
225system.physmem.rdPerTurnAround::samples 5874 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::mean 28.927818 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::stdev 584.509202 # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::0-2047 5873 99.98% 99.98% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::total 5874 # Reads before turning the bus around for writes
231system.physmem.wrPerTurnAround::samples 5873 # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::mean 24.134684 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::gmean 18.418054 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::stdev 43.798135 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::16-31 5542 94.36% 94.36% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::32-47 90 1.53% 95.90% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::48-63 17 0.29% 96.19% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::64-79 15 0.26% 96.44% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::80-95 16 0.27% 96.71% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::96-111 28 0.48% 97.19% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::112-127 28 0.48% 97.67% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::128-143 13 0.22% 97.89% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::144-159 10 0.17% 98.06% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::160-175 8 0.14% 98.20% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::176-191 17 0.29% 98.48% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::192-207 16 0.27% 98.76% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::208-223 10 0.17% 98.93% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::224-239 6 0.10% 99.03% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::256-271 3 0.05% 99.08% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::272-287 5 0.09% 99.17% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::288-303 7 0.12% 99.28% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::304-319 1 0.02% 99.30% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::320-335 5 0.09% 99.39% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::336-351 11 0.19% 99.57% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::352-367 8 0.14% 99.71% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::368-383 2 0.03% 99.74% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::384-399 3 0.05% 99.80% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::416-431 1 0.02% 99.81% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::480-495 1 0.02% 99.83% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::528-543 3 0.05% 99.88% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::544-559 1 0.02% 99.90% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::560-575 1 0.02% 99.91% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::592-607 1 0.02% 99.93% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::672-687 1 0.02% 99.95% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::688-703 1 0.02% 99.97% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::total 5873 # Writes before turning the bus around for reads
269system.physmem.totQLat 1685079736 # Total ticks spent queuing
270system.physmem.totMemAccLat 4871117236 # Total ticks spent from burst creation until serviced by the DRAM
271system.physmem.totBusLat 849610000 # Total ticks spent in databus transfers
272system.physmem.avgQLat 9916.78 # Average queueing delay per DRAM burst
273system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
274system.physmem.avgMemAccLat 28666.78 # Average memory access latency per DRAM burst
275system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s
276system.physmem.avgWrBW 3.18 # Average achieved write bandwidth in MiByte/s
277system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s
278system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s
279system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
280system.physmem.busUtil 0.05 # Data bus utilization in percentage
281system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
282system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
283system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
284system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing
285system.physmem.readRowHits 140217 # Number of row buffer hits during reads
286system.physmem.writeRowHits 109661 # Number of row buffer hits during writes
287system.physmem.readRowHitRate 82.52 # Row buffer hit rate for reads
288system.physmem.writeRowHitRate 77.35 # Row buffer hit rate for writes
289system.physmem.avgGap 8512044.79 # Average gap between requests
290system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined
291system.physmem_0.actEnergy 242267760 # Energy for activate commands per rank (pJ)
292system.physmem_0.preEnergy 132189750 # Energy for precharge commands per rank (pJ)
293system.physmem_0.readEnergy 692507400 # Energy for read commands per rank (pJ)
294system.physmem_0.writeEnergy 468860400 # Energy for write commands per rank (pJ)
295system.physmem_0.refreshEnergy 186372491760 # Energy for refresh commands per rank (pJ)
296system.physmem_0.actBackEnergy 83617160895 # Energy for active background per rank (pJ)
297system.physmem_0.preBackEnergy 1638712655250 # Energy for precharge background per rank (pJ)
298system.physmem_0.totalEnergy 1910238133215 # Total energy per rank (pJ)
299system.physmem_0.averagePower 669.452112 # Core power per rank (mW)
300system.physmem_0.memoryStateTime::IDLE 2726011845150 # Time in different power states
301system.physmem_0.memoryStateTime::REF 95282460000 # Time in different power states
302system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
303system.physmem_0.memoryStateTime::ACT 32147776350 # Time in different power states
304system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
305system.physmem_1.actEnergy 224857080 # Energy for activate commands per rank (pJ)
306system.physmem_1.preEnergy 122689875 # Energy for precharge commands per rank (pJ)
307system.physmem_1.readEnergy 632876400 # Energy for read commands per rank (pJ)
308system.physmem_1.writeEnergy 449634240 # Energy for write commands per rank (pJ)
309system.physmem_1.refreshEnergy 186372491760 # Energy for refresh commands per rank (pJ)
310system.physmem_1.actBackEnergy 82395435150 # Energy for active background per rank (pJ)
311system.physmem_1.preBackEnergy 1639784344500 # Energy for precharge background per rank (pJ)
312system.physmem_1.totalEnergy 1909982329005 # Total energy per rank (pJ)
313system.physmem_1.averagePower 669.362464 # Core power per rank (mW)
314system.physmem_1.memoryStateTime::IDLE 2727805815350 # Time in different power states
315system.physmem_1.memoryStateTime::REF 95282460000 # Time in different power states
316system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
317system.physmem_1.memoryStateTime::ACT 30353736650 # Time in different power states
318system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
319system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory
320system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
321system.realview.nvmem.bytes_inst_read::cpu.inst 448 # Number of instructions bytes read from this memory
322system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
323system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory
324system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
325system.realview.nvmem.bw_read::cpu.inst 157 # Total read bandwidth from this memory (bytes/s)
326system.realview.nvmem.bw_read::total 157 # Total read bandwidth from this memory (bytes/s)
327system.realview.nvmem.bw_inst_read::cpu.inst 157 # Instruction read bandwidth from this memory (bytes/s)
328system.realview.nvmem.bw_inst_read::total 157 # Instruction read bandwidth from this memory (bytes/s)
329system.realview.nvmem.bw_total::cpu.inst 157 # Total bandwidth to/from this memory (bytes/s)
330system.realview.nvmem.bw_total::total 157 # Total bandwidth to/from this memory (bytes/s)
331system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
332system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
333system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
334system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
335system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
336system.cf0.dma_write_txs 631 # Number of DMA write transactions.
337system.cpu.branchPred.lookups 31053109 # Number of BP lookups
338system.cpu.branchPred.condPredicted 16852863 # Number of conditional branches predicted
339system.cpu.branchPred.condIncorrect 2525514 # Number of conditional branches incorrect
340system.cpu.branchPred.BTBLookups 18620216 # Number of BTB lookups
341system.cpu.branchPred.BTBHits 13364906 # Number of BTB hits
342system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
343system.cpu.branchPred.BTBHitPct 71.776321 # BTB Hit Percentage
344system.cpu.branchPred.usedRAS 7853668 # Number of times the RAS was used to get a target.
345system.cpu.branchPred.RASInCorrect 1516989 # Number of incorrect RAS predictions.
346system.cpu_clk_domain.clock 500 # Clock period in ticks
347system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
348system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
349system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
350system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
351system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
352system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
353system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

368system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
369system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
370system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
371system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
372system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
373system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
374system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
375system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
376system.cpu.dtb.walker.walks 65844 # Table walker walks requested
377system.cpu.dtb.walker.walksShort 65844 # Table walker walks initiated with short descriptors
378system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43330 # Level at which table walker walks with short descriptors terminate
379system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22514 # Level at which table walker walks with short descriptors terminate
380system.cpu.dtb.walker.walkWaitTime::samples 65844 # Table walker wait (enqueue to first request) latency
381system.cpu.dtb.walker.walkWaitTime::0 65844 100.00% 100.00% # Table walker wait (enqueue to first request) latency
382system.cpu.dtb.walker.walkWaitTime::total 65844 # Table walker wait (enqueue to first request) latency
383system.cpu.dtb.walker.walkCompletionTime::samples 7786 # Table walker service (enqueue to completion) latency
384system.cpu.dtb.walker.walkCompletionTime::mean 11086.116106 # Table walker service (enqueue to completion) latency
385system.cpu.dtb.walker.walkCompletionTime::gmean 8821.657087 # Table walker service (enqueue to completion) latency
386system.cpu.dtb.walker.walkCompletionTime::stdev 7338.018596 # Table walker service (enqueue to completion) latency
387system.cpu.dtb.walker.walkCompletionTime::0-16383 6073 78.00% 78.00% # Table walker service (enqueue to completion) latency
388system.cpu.dtb.walker.walkCompletionTime::16384-32767 1707 21.92% 99.92% # Table walker service (enqueue to completion) latency
389system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.94% # Table walker service (enqueue to completion) latency
390system.cpu.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.97% # Table walker service (enqueue to completion) latency
391system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
392system.cpu.dtb.walker.walkCompletionTime::163840-180223 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
393system.cpu.dtb.walker.walkCompletionTime::total 7786 # Table walker service (enqueue to completion) latency
394system.cpu.dtb.walker.walksPending::samples 262515000 # Table walker pending requests distribution
395system.cpu.dtb.walker.walksPending::0 262515000 100.00% 100.00% # Table walker pending requests distribution
396system.cpu.dtb.walker.walksPending::total 262515000 # Table walker pending requests distribution
397system.cpu.dtb.walker.walkPageSizes::4K 6400 82.20% 82.20% # Table walker page sizes translated
398system.cpu.dtb.walker.walkPageSizes::1M 1386 17.80% 100.00% # Table walker page sizes translated
399system.cpu.dtb.walker.walkPageSizes::total 7786 # Table walker page sizes translated
400system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 65844 # Table walker requests started/completed, data/inst
401system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
402system.cpu.dtb.walker.walkRequestOrigin_Requested::total 65844 # Table walker requests started/completed, data/inst
403system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7786 # Table walker requests started/completed, data/inst
404system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
405system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7786 # Table walker requests started/completed, data/inst
406system.cpu.dtb.walker.walkRequestOrigin::total 73630 # Table walker requests started/completed, data/inst
407system.cpu.dtb.inst_hits 0 # ITB inst hits
408system.cpu.dtb.inst_misses 0 # ITB inst misses
409system.cpu.dtb.read_hits 24757406 # DTB read hits
410system.cpu.dtb.read_misses 59085 # DTB read misses
411system.cpu.dtb.write_hits 19449348 # DTB write hits
412system.cpu.dtb.write_misses 6759 # DTB write misses
413system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
414system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
415system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
416system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
417system.cpu.dtb.flush_entries 4357 # Number of entries that have been flushed from TLB
418system.cpu.dtb.align_faults 1268 # Number of TLB faults due to alignment restrictions
419system.cpu.dtb.prefetch_faults 1766 # Number of TLB faults due to prefetch
420system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
421system.cpu.dtb.perms_faults 739 # Number of TLB faults due to permissions restrictions
422system.cpu.dtb.read_accesses 24816491 # DTB read accesses
423system.cpu.dtb.write_accesses 19456107 # DTB write accesses
424system.cpu.dtb.inst_accesses 0 # ITB inst accesses
425system.cpu.dtb.hits 44206754 # DTB hits
426system.cpu.dtb.misses 65844 # DTB misses
427system.cpu.dtb.accesses 44272598 # DTB accesses
428system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
429system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
430system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
431system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
432system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
433system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
434system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
435system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

449system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
450system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
451system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
452system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
453system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
454system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
455system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
456system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
457system.cpu.itb.walker.walks 5446 # Table walker walks requested
458system.cpu.itb.walker.walksShort 5446 # Table walker walks initiated with short descriptors
459system.cpu.itb.walker.walksShortTerminationLevel::Level1 324 # Level at which table walker walks with short descriptors terminate
460system.cpu.itb.walker.walksShortTerminationLevel::Level2 5122 # Level at which table walker walks with short descriptors terminate
461system.cpu.itb.walker.walkWaitTime::samples 5446 # Table walker wait (enqueue to first request) latency
462system.cpu.itb.walker.walkWaitTime::0 5446 100.00% 100.00% # Table walker wait (enqueue to first request) latency
463system.cpu.itb.walker.walkWaitTime::total 5446 # Table walker wait (enqueue to first request) latency
464system.cpu.itb.walker.walkCompletionTime::samples 3184 # Table walker service (enqueue to completion) latency
465system.cpu.itb.walker.walkCompletionTime::mean 11253.454774 # Table walker service (enqueue to completion) latency
466system.cpu.itb.walker.walkCompletionTime::gmean 8989.562910 # Table walker service (enqueue to completion) latency
467system.cpu.itb.walker.walkCompletionTime::stdev 7050.042435 # Table walker service (enqueue to completion) latency
468system.cpu.itb.walker.walkCompletionTime::0-8191 1281 40.23% 40.23% # Table walker service (enqueue to completion) latency
469system.cpu.itb.walker.walkCompletionTime::8192-16383 1185 37.22% 77.45% # Table walker service (enqueue to completion) latency
470system.cpu.itb.walker.walkCompletionTime::16384-24575 717 22.52% 99.97% # Table walker service (enqueue to completion) latency
471system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
472system.cpu.itb.walker.walkCompletionTime::total 3184 # Table walker service (enqueue to completion) latency
473system.cpu.itb.walker.walksPending::samples 262109500 # Table walker pending requests distribution
474system.cpu.itb.walker.walksPending::0 262109500 100.00% 100.00% # Table walker pending requests distribution
475system.cpu.itb.walker.walksPending::total 262109500 # Table walker pending requests distribution
476system.cpu.itb.walker.walkPageSizes::4K 2875 90.30% 90.30% # Table walker page sizes translated
477system.cpu.itb.walker.walkPageSizes::1M 309 9.70% 100.00% # Table walker page sizes translated
478system.cpu.itb.walker.walkPageSizes::total 3184 # Table walker page sizes translated
479system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
480system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5446 # Table walker requests started/completed, data/inst
481system.cpu.itb.walker.walkRequestOrigin_Requested::total 5446 # Table walker requests started/completed, data/inst
482system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
483system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3184 # Table walker requests started/completed, data/inst
484system.cpu.itb.walker.walkRequestOrigin_Completed::total 3184 # Table walker requests started/completed, data/inst
485system.cpu.itb.walker.walkRequestOrigin::total 8630 # Table walker requests started/completed, data/inst
486system.cpu.itb.inst_hits 57726188 # ITB inst hits
487system.cpu.itb.inst_misses 5446 # ITB inst misses
488system.cpu.itb.read_hits 0 # DTB read hits
489system.cpu.itb.read_misses 0 # DTB read misses
490system.cpu.itb.write_hits 0 # DTB write hits
491system.cpu.itb.write_misses 0 # DTB write misses
492system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
493system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
494system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
495system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
496system.cpu.itb.flush_entries 2973 # Number of entries that have been flushed from TLB
497system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
498system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
499system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
500system.cpu.itb.perms_faults 8450 # Number of TLB faults due to permissions restrictions
501system.cpu.itb.read_accesses 0 # DTB read accesses
502system.cpu.itb.write_accesses 0 # DTB write accesses
503system.cpu.itb.inst_accesses 57731634 # ITB inst accesses
504system.cpu.itb.hits 57726188 # DTB hits
505system.cpu.itb.misses 5446 # DTB misses
506system.cpu.itb.accesses 57731634 # DTB accesses
507system.cpu.numCycles 317415724 # number of cpu cycles simulated
508system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
509system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
510system.cpu.committedInsts 112053421 # Number of instructions committed
511system.cpu.committedOps 135485276 # Number of ops (including micro ops) committed
512system.cpu.discardedOps 7764036 # Number of ops (including micro ops) which were discarded before commit
513system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching
514system.cpu.quiesceCycles 5389516808 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
515system.cpu.cpi 2.832718 # CPI: cycles per instruction
516system.cpu.ipc 0.353018 # IPC: instructions per cycle
517system.cpu.kern.inst.arm 0 # number of arm instructions executed
518system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed
519system.cpu.tickCycles 228406815 # Number of cycles that the object actually ticked
520system.cpu.idleCycles 89008909 # Total number of cycles that the object has spent stopped
521system.cpu.dcache.tags.replacements 842109 # number of replacements
522system.cpu.dcache.tags.tagsinuse 511.947879 # Cycle average of tags in use
523system.cpu.dcache.tags.total_refs 42706608 # Total number of references to valid blocks.
524system.cpu.dcache.tags.sampled_refs 842621 # Sample count of references to valid blocks.
525system.cpu.dcache.tags.avg_refs 50.683057 # Average number of references to valid blocks.
526system.cpu.dcache.tags.warmup_cycle 313221250 # Cycle when the warmup percentage was hit.
527system.cpu.dcache.tags.occ_blocks::cpu.data 511.947879 # Average occupied blocks per requestor
528system.cpu.dcache.tags.occ_percent::cpu.data 0.999898 # Average percentage of cache occupancy
529system.cpu.dcache.tags.occ_percent::total 0.999898 # Average percentage of cache occupancy
530system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
531system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
532system.cpu.dcache.tags.age_task_id_blocks_1024::1 357 # Occupied blocks per task id
533system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id
534system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
535system.cpu.dcache.tags.tag_accesses 176191359 # Number of tag accesses
536system.cpu.dcache.tags.data_accesses 176191359 # Number of data accesses
537system.cpu.dcache.ReadReq_hits::cpu.data 23499832 # number of ReadReq hits
538system.cpu.dcache.ReadReq_hits::total 23499832 # number of ReadReq hits
539system.cpu.dcache.WriteReq_hits::cpu.data 18286134 # number of WriteReq hits
540system.cpu.dcache.WriteReq_hits::total 18286134 # number of WriteReq hits
541system.cpu.dcache.LoadLockedReq_hits::cpu.data 457571 # number of LoadLockedReq hits
542system.cpu.dcache.LoadLockedReq_hits::total 457571 # number of LoadLockedReq hits
543system.cpu.dcache.StoreCondReq_hits::cpu.data 460116 # number of StoreCondReq hits
544system.cpu.dcache.StoreCondReq_hits::total 460116 # number of StoreCondReq hits
545system.cpu.dcache.demand_hits::cpu.data 41785966 # number of demand (read+write) hits
546system.cpu.dcache.demand_hits::total 41785966 # number of demand (read+write) hits
547system.cpu.dcache.overall_hits::cpu.data 41785966 # number of overall hits
548system.cpu.dcache.overall_hits::total 41785966 # number of overall hits
549system.cpu.dcache.ReadReq_misses::cpu.data 583874 # number of ReadReq misses
550system.cpu.dcache.ReadReq_misses::total 583874 # number of ReadReq misses
551system.cpu.dcache.WriteReq_misses::cpu.data 541283 # number of WriteReq misses
552system.cpu.dcache.WriteReq_misses::total 541283 # number of WriteReq misses
553system.cpu.dcache.LoadLockedReq_misses::cpu.data 8366 # number of LoadLockedReq misses
554system.cpu.dcache.LoadLockedReq_misses::total 8366 # number of LoadLockedReq misses
555system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
556system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
557system.cpu.dcache.demand_misses::cpu.data 1125157 # number of demand (read+write) misses
558system.cpu.dcache.demand_misses::total 1125157 # number of demand (read+write) misses
559system.cpu.dcache.overall_misses::cpu.data 1125157 # number of overall misses
560system.cpu.dcache.overall_misses::total 1125157 # number of overall misses
561system.cpu.dcache.ReadReq_miss_latency::cpu.data 8774452459 # number of ReadReq miss cycles
562system.cpu.dcache.ReadReq_miss_latency::total 8774452459 # number of ReadReq miss cycles
563system.cpu.dcache.WriteReq_miss_latency::cpu.data 23299729316 # number of WriteReq miss cycles
564system.cpu.dcache.WriteReq_miss_latency::total 23299729316 # number of WriteReq miss cycles
565system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 120081750 # number of LoadLockedReq miss cycles
566system.cpu.dcache.LoadLockedReq_miss_latency::total 120081750 # number of LoadLockedReq miss cycles
567system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles
568system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles
569system.cpu.dcache.demand_miss_latency::cpu.data 32074181775 # number of demand (read+write) miss cycles
570system.cpu.dcache.demand_miss_latency::total 32074181775 # number of demand (read+write) miss cycles
571system.cpu.dcache.overall_miss_latency::cpu.data 32074181775 # number of overall miss cycles
572system.cpu.dcache.overall_miss_latency::total 32074181775 # number of overall miss cycles
573system.cpu.dcache.ReadReq_accesses::cpu.data 24083706 # number of ReadReq accesses(hits+misses)
574system.cpu.dcache.ReadReq_accesses::total 24083706 # number of ReadReq accesses(hits+misses)
575system.cpu.dcache.WriteReq_accesses::cpu.data 18827417 # number of WriteReq accesses(hits+misses)
576system.cpu.dcache.WriteReq_accesses::total 18827417 # number of WriteReq accesses(hits+misses)
577system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465937 # number of LoadLockedReq accesses(hits+misses)
578system.cpu.dcache.LoadLockedReq_accesses::total 465937 # number of LoadLockedReq accesses(hits+misses)
579system.cpu.dcache.StoreCondReq_accesses::cpu.data 460118 # number of StoreCondReq accesses(hits+misses)
580system.cpu.dcache.StoreCondReq_accesses::total 460118 # number of StoreCondReq accesses(hits+misses)
581system.cpu.dcache.demand_accesses::cpu.data 42911123 # number of demand (read+write) accesses
582system.cpu.dcache.demand_accesses::total 42911123 # number of demand (read+write) accesses
583system.cpu.dcache.overall_accesses::cpu.data 42911123 # number of overall (read+write) accesses
584system.cpu.dcache.overall_accesses::total 42911123 # number of overall (read+write) accesses
585system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024244 # miss rate for ReadReq accesses
586system.cpu.dcache.ReadReq_miss_rate::total 0.024244 # miss rate for ReadReq accesses
587system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028750 # miss rate for WriteReq accesses
588system.cpu.dcache.WriteReq_miss_rate::total 0.028750 # miss rate for WriteReq accesses
589system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017955 # miss rate for LoadLockedReq accesses
590system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017955 # miss rate for LoadLockedReq accesses
591system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
592system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
593system.cpu.dcache.demand_miss_rate::cpu.data 0.026221 # miss rate for demand accesses
594system.cpu.dcache.demand_miss_rate::total 0.026221 # miss rate for demand accesses
595system.cpu.dcache.overall_miss_rate::cpu.data 0.026221 # miss rate for overall accesses
596system.cpu.dcache.overall_miss_rate::total 0.026221 # miss rate for overall accesses
597system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15027.989702 # average ReadReq miss latency
598system.cpu.dcache.ReadReq_avg_miss_latency::total 15027.989702 # average ReadReq miss latency
599system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43045.374261 # average WriteReq miss latency
600system.cpu.dcache.WriteReq_avg_miss_latency::total 43045.374261 # average WriteReq miss latency
601system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14353.544107 # average LoadLockedReq miss latency
602system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14353.544107 # average LoadLockedReq miss latency
603system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency
604system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency
605system.cpu.dcache.demand_avg_miss_latency::cpu.data 28506.405573 # average overall miss latency
606system.cpu.dcache.demand_avg_miss_latency::total 28506.405573 # average overall miss latency
607system.cpu.dcache.overall_avg_miss_latency::cpu.data 28506.405573 # average overall miss latency
608system.cpu.dcache.overall_avg_miss_latency::total 28506.405573 # average overall miss latency
609system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
610system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
611system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
612system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
613system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
614system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
615system.cpu.dcache.fast_writes 0 # number of fast writes performed
616system.cpu.dcache.cache_copies 0 # number of cache copies performed
617system.cpu.dcache.writebacks::writebacks 697919 # number of writebacks
618system.cpu.dcache.writebacks::total 697919 # number of writebacks
619system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45195 # number of ReadReq MSHR hits
620system.cpu.dcache.ReadReq_mshr_hits::total 45195 # number of ReadReq MSHR hits
621system.cpu.dcache.WriteReq_mshr_hits::cpu.data 242825 # number of WriteReq MSHR hits
622system.cpu.dcache.WriteReq_mshr_hits::total 242825 # number of WriteReq MSHR hits
623system.cpu.dcache.demand_mshr_hits::cpu.data 288020 # number of demand (read+write) MSHR hits
624system.cpu.dcache.demand_mshr_hits::total 288020 # number of demand (read+write) MSHR hits
625system.cpu.dcache.overall_mshr_hits::cpu.data 288020 # number of overall MSHR hits
626system.cpu.dcache.overall_mshr_hits::total 288020 # number of overall MSHR hits
627system.cpu.dcache.ReadReq_mshr_misses::cpu.data 538679 # number of ReadReq MSHR misses
628system.cpu.dcache.ReadReq_mshr_misses::total 538679 # number of ReadReq MSHR misses
629system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298458 # number of WriteReq MSHR misses
630system.cpu.dcache.WriteReq_mshr_misses::total 298458 # number of WriteReq MSHR misses
631system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8366 # number of LoadLockedReq MSHR misses
632system.cpu.dcache.LoadLockedReq_mshr_misses::total 8366 # number of LoadLockedReq MSHR misses
633system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
634system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
635system.cpu.dcache.demand_mshr_misses::cpu.data 837137 # number of demand (read+write) MSHR misses
636system.cpu.dcache.demand_mshr_misses::total 837137 # number of demand (read+write) MSHR misses
637system.cpu.dcache.overall_mshr_misses::cpu.data 837137 # number of overall MSHR misses
638system.cpu.dcache.overall_mshr_misses::total 837137 # number of overall MSHR misses
639system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7251218502 # number of ReadReq MSHR miss cycles
640system.cpu.dcache.ReadReq_mshr_miss_latency::total 7251218502 # number of ReadReq MSHR miss cycles
641system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12288582898 # number of WriteReq MSHR miss cycles
642system.cpu.dcache.WriteReq_mshr_miss_latency::total 12288582898 # number of WriteReq MSHR miss cycles
643system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 107501250 # number of LoadLockedReq MSHR miss cycles
644system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 107501250 # number of LoadLockedReq MSHR miss cycles
645system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles
646system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles
647system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19539801400 # number of demand (read+write) MSHR miss cycles
648system.cpu.dcache.demand_mshr_miss_latency::total 19539801400 # number of demand (read+write) MSHR miss cycles
649system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19539801400 # number of overall MSHR miss cycles
650system.cpu.dcache.overall_mshr_miss_latency::total 19539801400 # number of overall MSHR miss cycles
651system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5836783750 # number of ReadReq MSHR uncacheable cycles
652system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5836783750 # number of ReadReq MSHR uncacheable cycles
653system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4510033500 # number of WriteReq MSHR uncacheable cycles
654system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4510033500 # number of WriteReq MSHR uncacheable cycles
655system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346817250 # number of overall MSHR uncacheable cycles
656system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346817250 # number of overall MSHR uncacheable cycles
657system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.022367 # mshr miss rate for ReadReq accesses
658system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022367 # mshr miss rate for ReadReq accesses
659system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015852 # mshr miss rate for WriteReq accesses
660system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015852 # mshr miss rate for WriteReq accesses
661system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017955 # mshr miss rate for LoadLockedReq accesses
662system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017955 # mshr miss rate for LoadLockedReq accesses
663system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
664system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
665system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.019509 # mshr miss rate for demand accesses
666system.cpu.dcache.demand_mshr_miss_rate::total 0.019509 # mshr miss rate for demand accesses
667system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019509 # mshr miss rate for overall accesses
668system.cpu.dcache.overall_mshr_miss_rate::total 0.019509 # mshr miss rate for overall accesses
669system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13461.112280 # average ReadReq mshr miss latency
670system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13461.112280 # average ReadReq mshr miss latency
671system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41173.575170 # average WriteReq mshr miss latency
672system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41173.575170 # average WriteReq mshr miss latency
673system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12849.778867 # average LoadLockedReq mshr miss latency
674system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12849.778867 # average LoadLockedReq mshr miss latency
675system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81250 # average StoreCondReq mshr miss latency
676system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81250 # average StoreCondReq mshr miss latency
677system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23341.223002 # average overall mshr miss latency
678system.cpu.dcache.demand_avg_mshr_miss_latency::total 23341.223002 # average overall mshr miss latency
679system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23341.223002 # average overall mshr miss latency
680system.cpu.dcache.overall_avg_mshr_miss_latency::total 23341.223002 # average overall mshr miss latency
681system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
682system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
683system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
684system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
685system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
686system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
687system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
688system.cpu.icache.tags.replacements 2898605 # number of replacements
689system.cpu.icache.tags.tagsinuse 511.397830 # Cycle average of tags in use
690system.cpu.icache.tags.total_refs 54818221 # Total number of references to valid blocks.
691system.cpu.icache.tags.sampled_refs 2899117 # Sample count of references to valid blocks.
692system.cpu.icache.tags.avg_refs 18.908592 # Average number of references to valid blocks.
693system.cpu.icache.tags.warmup_cycle 15715014250 # Cycle when the warmup percentage was hit.
694system.cpu.icache.tags.occ_blocks::cpu.inst 511.397830 # Average occupied blocks per requestor
695system.cpu.icache.tags.occ_percent::cpu.inst 0.998824 # Average percentage of cache occupancy
696system.cpu.icache.tags.occ_percent::total 0.998824 # Average percentage of cache occupancy
697system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
698system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
699system.cpu.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id
700system.cpu.icache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id
701system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
702system.cpu.icache.tags.tag_accesses 60616478 # Number of tag accesses
703system.cpu.icache.tags.data_accesses 60616478 # Number of data accesses
704system.cpu.icache.ReadReq_hits::cpu.inst 54818221 # number of ReadReq hits
705system.cpu.icache.ReadReq_hits::total 54818221 # number of ReadReq hits
706system.cpu.icache.demand_hits::cpu.inst 54818221 # number of demand (read+write) hits
707system.cpu.icache.demand_hits::total 54818221 # number of demand (read+write) hits
708system.cpu.icache.overall_hits::cpu.inst 54818221 # number of overall hits
709system.cpu.icache.overall_hits::total 54818221 # number of overall hits
710system.cpu.icache.ReadReq_misses::cpu.inst 2899129 # number of ReadReq misses
711system.cpu.icache.ReadReq_misses::total 2899129 # number of ReadReq misses
712system.cpu.icache.demand_misses::cpu.inst 2899129 # number of demand (read+write) misses
713system.cpu.icache.demand_misses::total 2899129 # number of demand (read+write) misses
714system.cpu.icache.overall_misses::cpu.inst 2899129 # number of overall misses
715system.cpu.icache.overall_misses::total 2899129 # number of overall misses
716system.cpu.icache.ReadReq_miss_latency::cpu.inst 39309012875 # number of ReadReq miss cycles
717system.cpu.icache.ReadReq_miss_latency::total 39309012875 # number of ReadReq miss cycles
718system.cpu.icache.demand_miss_latency::cpu.inst 39309012875 # number of demand (read+write) miss cycles
719system.cpu.icache.demand_miss_latency::total 39309012875 # number of demand (read+write) miss cycles
720system.cpu.icache.overall_miss_latency::cpu.inst 39309012875 # number of overall miss cycles
721system.cpu.icache.overall_miss_latency::total 39309012875 # number of overall miss cycles
722system.cpu.icache.ReadReq_accesses::cpu.inst 57717350 # number of ReadReq accesses(hits+misses)
723system.cpu.icache.ReadReq_accesses::total 57717350 # number of ReadReq accesses(hits+misses)
724system.cpu.icache.demand_accesses::cpu.inst 57717350 # number of demand (read+write) accesses
725system.cpu.icache.demand_accesses::total 57717350 # number of demand (read+write) accesses
726system.cpu.icache.overall_accesses::cpu.inst 57717350 # number of overall (read+write) accesses
727system.cpu.icache.overall_accesses::total 57717350 # number of overall (read+write) accesses
728system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050230 # miss rate for ReadReq accesses
729system.cpu.icache.ReadReq_miss_rate::total 0.050230 # miss rate for ReadReq accesses
730system.cpu.icache.demand_miss_rate::cpu.inst 0.050230 # miss rate for demand accesses
731system.cpu.icache.demand_miss_rate::total 0.050230 # miss rate for demand accesses
732system.cpu.icache.overall_miss_rate::cpu.inst 0.050230 # miss rate for overall accesses
733system.cpu.icache.overall_miss_rate::total 0.050230 # miss rate for overall accesses
734system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13558.904373 # average ReadReq miss latency
735system.cpu.icache.ReadReq_avg_miss_latency::total 13558.904373 # average ReadReq miss latency
736system.cpu.icache.demand_avg_miss_latency::cpu.inst 13558.904373 # average overall miss latency
737system.cpu.icache.demand_avg_miss_latency::total 13558.904373 # average overall miss latency
738system.cpu.icache.overall_avg_miss_latency::cpu.inst 13558.904373 # average overall miss latency
739system.cpu.icache.overall_avg_miss_latency::total 13558.904373 # average overall miss latency
740system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
741system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
742system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
743system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
744system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
745system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
746system.cpu.icache.fast_writes 0 # number of fast writes performed
747system.cpu.icache.cache_copies 0 # number of cache copies performed
748system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2899129 # number of ReadReq MSHR misses
749system.cpu.icache.ReadReq_mshr_misses::total 2899129 # number of ReadReq MSHR misses
750system.cpu.icache.demand_mshr_misses::cpu.inst 2899129 # number of demand (read+write) MSHR misses
751system.cpu.icache.demand_mshr_misses::total 2899129 # number of demand (read+write) MSHR misses
752system.cpu.icache.overall_mshr_misses::cpu.inst 2899129 # number of overall MSHR misses
753system.cpu.icache.overall_mshr_misses::total 2899129 # number of overall MSHR misses
754system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34950907125 # number of ReadReq MSHR miss cycles
755system.cpu.icache.ReadReq_mshr_miss_latency::total 34950907125 # number of ReadReq MSHR miss cycles
756system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34950907125 # number of demand (read+write) MSHR miss cycles
757system.cpu.icache.demand_mshr_miss_latency::total 34950907125 # number of demand (read+write) MSHR miss cycles
758system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34950907125 # number of overall MSHR miss cycles
759system.cpu.icache.overall_mshr_miss_latency::total 34950907125 # number of overall MSHR miss cycles
760system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 247386750 # number of ReadReq MSHR uncacheable cycles
761system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 247386750 # number of ReadReq MSHR uncacheable cycles
762system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 247386750 # number of overall MSHR uncacheable cycles
763system.cpu.icache.overall_mshr_uncacheable_latency::total 247386750 # number of overall MSHR uncacheable cycles
764system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050230 # mshr miss rate for ReadReq accesses
765system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050230 # mshr miss rate for ReadReq accesses
766system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050230 # mshr miss rate for demand accesses
767system.cpu.icache.demand_mshr_miss_rate::total 0.050230 # mshr miss rate for demand accesses
768system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050230 # mshr miss rate for overall accesses
769system.cpu.icache.overall_mshr_miss_rate::total 0.050230 # mshr miss rate for overall accesses
770system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12055.657794 # average ReadReq mshr miss latency
771system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12055.657794 # average ReadReq mshr miss latency
772system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12055.657794 # average overall mshr miss latency
773system.cpu.icache.demand_avg_mshr_miss_latency::total 12055.657794 # average overall mshr miss latency
774system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12055.657794 # average overall mshr miss latency
775system.cpu.icache.overall_avg_mshr_miss_latency::total 12055.657794 # average overall mshr miss latency
776system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
777system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
778system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
779system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
780system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
781system.cpu.l2cache.tags.replacements 96782 # number of replacements
782system.cpu.l2cache.tags.tagsinuse 65059.413288 # Cycle average of tags in use
783system.cpu.l2cache.tags.total_refs 4045474 # Total number of references to valid blocks.
784system.cpu.l2cache.tags.sampled_refs 162031 # Sample count of references to valid blocks.
785system.cpu.l2cache.tags.avg_refs 24.967284 # Average number of references to valid blocks.
786system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
787system.cpu.l2cache.tags.occ_blocks::writebacks 47373.506796 # Average occupied blocks per requestor
788system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 67.256900 # Average occupied blocks per requestor
789system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000383 # Average occupied blocks per requestor
790system.cpu.l2cache.tags.occ_blocks::cpu.inst 12244.945403 # Average occupied blocks per requestor
791system.cpu.l2cache.tags.occ_blocks::cpu.data 5373.703806 # Average occupied blocks per requestor
792system.cpu.l2cache.tags.occ_percent::writebacks 0.722862 # Average percentage of cache occupancy
793system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001026 # Average percentage of cache occupancy
794system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
795system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186843 # Average percentage of cache occupancy
796system.cpu.l2cache.tags.occ_percent::cpu.data 0.081996 # Average percentage of cache occupancy
797system.cpu.l2cache.tags.occ_percent::total 0.992728 # Average percentage of cache occupancy
798system.cpu.l2cache.tags.occ_task_id_blocks::1023 31 # Occupied blocks per task id
799system.cpu.l2cache.tags.occ_task_id_blocks::1024 65218 # Occupied blocks per task id
800system.cpu.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id
801system.cpu.l2cache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
802system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
803system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2276 # Occupied blocks per task id
804system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6932 # Occupied blocks per task id
805system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55893 # Occupied blocks per task id
806system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000473 # Percentage of cache occupancy per task id
807system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995148 # Percentage of cache occupancy per task id
808system.cpu.l2cache.tags.tag_accesses 36598730 # Number of tag accesses
809system.cpu.l2cache.tags.data_accesses 36598730 # Number of data accesses
810system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69951 # number of ReadReq hits
811system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4476 # number of ReadReq hits
812system.cpu.l2cache.ReadReq_hits::cpu.inst 2876131 # number of ReadReq hits
813system.cpu.l2cache.ReadReq_hits::cpu.data 532779 # number of ReadReq hits
814system.cpu.l2cache.ReadReq_hits::total 3483337 # number of ReadReq hits
815system.cpu.l2cache.Writeback_hits::writebacks 697919 # number of Writeback hits
816system.cpu.l2cache.Writeback_hits::total 697919 # number of Writeback hits
817system.cpu.l2cache.UpgradeReq_hits::cpu.data 49 # number of UpgradeReq hits
818system.cpu.l2cache.UpgradeReq_hits::total 49 # number of UpgradeReq hits
819system.cpu.l2cache.ReadExReq_hits::cpu.data 164415 # number of ReadExReq hits
820system.cpu.l2cache.ReadExReq_hits::total 164415 # number of ReadExReq hits
821system.cpu.l2cache.demand_hits::cpu.dtb.walker 69951 # number of demand (read+write) hits
822system.cpu.l2cache.demand_hits::cpu.itb.walker 4476 # number of demand (read+write) hits
823system.cpu.l2cache.demand_hits::cpu.inst 2876131 # number of demand (read+write) hits
824system.cpu.l2cache.demand_hits::cpu.data 697194 # number of demand (read+write) hits
825system.cpu.l2cache.demand_hits::total 3647752 # number of demand (read+write) hits
826system.cpu.l2cache.overall_hits::cpu.dtb.walker 69951 # number of overall hits
827system.cpu.l2cache.overall_hits::cpu.itb.walker 4476 # number of overall hits
828system.cpu.l2cache.overall_hits::cpu.inst 2876131 # number of overall hits
829system.cpu.l2cache.overall_hits::cpu.data 697194 # number of overall hits
830system.cpu.l2cache.overall_hits::total 3647752 # number of overall hits
831system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 114 # number of ReadReq misses
832system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses
833system.cpu.l2cache.ReadReq_misses::cpu.inst 22980 # number of ReadReq misses
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836system.cpu.l2cache.UpgradeReq_misses::cpu.data 2807 # number of UpgradeReq misses
837system.cpu.l2cache.UpgradeReq_misses::total 2807 # number of UpgradeReq misses
838system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
839system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
840system.cpu.l2cache.ReadExReq_misses::cpu.data 131192 # number of ReadExReq misses
841system.cpu.l2cache.ReadExReq_misses::total 131192 # number of ReadExReq misses
842system.cpu.l2cache.demand_misses::cpu.dtb.walker 114 # number of demand (read+write) misses
843system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses
844system.cpu.l2cache.demand_misses::cpu.inst 22980 # number of demand (read+write) misses
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849system.cpu.l2cache.overall_misses::cpu.inst 22980 # number of overall misses
850system.cpu.l2cache.overall_misses::cpu.data 145453 # number of overall misses
851system.cpu.l2cache.overall_misses::total 168548 # number of overall misses
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853system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 82500 # number of ReadReq miss cycles
854system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1838541652 # number of ReadReq miss cycles
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857system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1092965 # number of UpgradeReq miss cycles
858system.cpu.l2cache.UpgradeReq_miss_latency::total 1092965 # number of UpgradeReq miss cycles
859system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles
860system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles
861system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10173645453 # number of ReadExReq miss cycles
862system.cpu.l2cache.ReadExReq_miss_latency::total 10173645453 # number of ReadExReq miss cycles
863system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 9734000 # number of demand (read+write) miss cycles
864system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 82500 # number of demand (read+write) miss cycles
865system.cpu.l2cache.demand_miss_latency::cpu.inst 1838541652 # number of demand (read+write) miss cycles
866system.cpu.l2cache.demand_miss_latency::cpu.data 11365377065 # number of demand (read+write) miss cycles
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869system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 82500 # number of overall miss cycles
870system.cpu.l2cache.overall_miss_latency::cpu.inst 1838541652 # number of overall miss cycles
871system.cpu.l2cache.overall_miss_latency::cpu.data 11365377065 # number of overall miss cycles
872system.cpu.l2cache.overall_miss_latency::total 13213735217 # number of overall miss cycles
873system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 70065 # number of ReadReq accesses(hits+misses)
874system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4477 # number of ReadReq accesses(hits+misses)
875system.cpu.l2cache.ReadReq_accesses::cpu.inst 2899111 # number of ReadReq accesses(hits+misses)
876system.cpu.l2cache.ReadReq_accesses::cpu.data 547040 # number of ReadReq accesses(hits+misses)
877system.cpu.l2cache.ReadReq_accesses::total 3520693 # number of ReadReq accesses(hits+misses)
878system.cpu.l2cache.Writeback_accesses::writebacks 697919 # number of Writeback accesses(hits+misses)
879system.cpu.l2cache.Writeback_accesses::total 697919 # number of Writeback accesses(hits+misses)
880system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2856 # number of UpgradeReq accesses(hits+misses)
881system.cpu.l2cache.UpgradeReq_accesses::total 2856 # number of UpgradeReq accesses(hits+misses)
882system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
883system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
884system.cpu.l2cache.ReadExReq_accesses::cpu.data 295607 # number of ReadExReq accesses(hits+misses)
885system.cpu.l2cache.ReadExReq_accesses::total 295607 # number of ReadExReq accesses(hits+misses)
886system.cpu.l2cache.demand_accesses::cpu.dtb.walker 70065 # number of demand (read+write) accesses
887system.cpu.l2cache.demand_accesses::cpu.itb.walker 4477 # number of demand (read+write) accesses
888system.cpu.l2cache.demand_accesses::cpu.inst 2899111 # number of demand (read+write) accesses
889system.cpu.l2cache.demand_accesses::cpu.data 842647 # number of demand (read+write) accesses
890system.cpu.l2cache.demand_accesses::total 3816300 # number of demand (read+write) accesses
891system.cpu.l2cache.overall_accesses::cpu.dtb.walker 70065 # number of overall (read+write) accesses
892system.cpu.l2cache.overall_accesses::cpu.itb.walker 4477 # number of overall (read+write) accesses
893system.cpu.l2cache.overall_accesses::cpu.inst 2899111 # number of overall (read+write) accesses
894system.cpu.l2cache.overall_accesses::cpu.data 842647 # number of overall (read+write) accesses
895system.cpu.l2cache.overall_accesses::total 3816300 # number of overall (read+write) accesses
896system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001627 # miss rate for ReadReq accesses
897system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000223 # miss rate for ReadReq accesses
898system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.007927 # miss rate for ReadReq accesses
899system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026069 # miss rate for ReadReq accesses
900system.cpu.l2cache.ReadReq_miss_rate::total 0.010610 # miss rate for ReadReq accesses
901system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.982843 # miss rate for UpgradeReq accesses
902system.cpu.l2cache.UpgradeReq_miss_rate::total 0.982843 # miss rate for UpgradeReq accesses
903system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
904system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
905system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.443805 # miss rate for ReadExReq accesses
906system.cpu.l2cache.ReadExReq_miss_rate::total 0.443805 # miss rate for ReadExReq accesses
907system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001627 # miss rate for demand accesses
908system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000223 # miss rate for demand accesses
909system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007927 # miss rate for demand accesses
910system.cpu.l2cache.demand_miss_rate::cpu.data 0.172614 # miss rate for demand accesses
911system.cpu.l2cache.demand_miss_rate::total 0.044165 # miss rate for demand accesses
912system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001627 # miss rate for overall accesses
913system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000223 # miss rate for overall accesses
914system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007927 # miss rate for overall accesses
915system.cpu.l2cache.overall_miss_rate::cpu.data 0.172614 # miss rate for overall accesses
916system.cpu.l2cache.overall_miss_rate::total 0.044165 # miss rate for overall accesses
917system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85385.964912 # average ReadReq miss latency
918system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82500 # average ReadReq miss latency
919system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80006.164143 # average ReadReq miss latency
920system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83565.781642 # average ReadReq miss latency
921system.cpu.l2cache.ReadReq_avg_miss_latency::total 81381.565585 # average ReadReq miss latency
922system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 389.371215 # average UpgradeReq miss latency
923system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 389.371215 # average UpgradeReq miss latency
924system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80250 # average SCUpgradeReq miss latency
925system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency
926system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77547.757889 # average ReadExReq miss latency
927system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77547.757889 # average ReadExReq miss latency
928system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85385.964912 # average overall miss latency
929system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82500 # average overall miss latency
930system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80006.164143 # average overall miss latency
931system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78137.797536 # average overall miss latency
932system.cpu.l2cache.demand_avg_miss_latency::total 78397.460765 # average overall miss latency
933system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85385.964912 # average overall miss latency
934system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82500 # average overall miss latency
935system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80006.164143 # average overall miss latency
936system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78137.797536 # average overall miss latency
937system.cpu.l2cache.overall_avg_miss_latency::total 78397.460765 # average overall miss latency
938system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
939system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
940system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
941system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
942system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
943system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
944system.cpu.l2cache.fast_writes 0 # number of fast writes performed
945system.cpu.l2cache.cache_copies 0 # number of cache copies performed
946system.cpu.l2cache.writebacks::writebacks 88388 # number of writebacks
947system.cpu.l2cache.writebacks::total 88388 # number of writebacks
948system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits
949system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 140 # number of ReadReq MSHR hits
950system.cpu.l2cache.ReadReq_mshr_hits::total 162 # number of ReadReq MSHR hits
951system.cpu.l2cache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits
952system.cpu.l2cache.demand_mshr_hits::cpu.data 140 # number of demand (read+write) MSHR hits
953system.cpu.l2cache.demand_mshr_hits::total 162 # number of demand (read+write) MSHR hits
954system.cpu.l2cache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits
955system.cpu.l2cache.overall_mshr_hits::cpu.data 140 # number of overall MSHR hits
956system.cpu.l2cache.overall_mshr_hits::total 162 # number of overall MSHR hits
957system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 114 # number of ReadReq MSHR misses
958system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses
959system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 22958 # number of ReadReq MSHR misses
960system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14121 # number of ReadReq MSHR misses
961system.cpu.l2cache.ReadReq_mshr_misses::total 37194 # number of ReadReq MSHR misses
962system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2807 # number of UpgradeReq MSHR misses
963system.cpu.l2cache.UpgradeReq_mshr_misses::total 2807 # number of UpgradeReq MSHR misses
964system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
965system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
966system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131192 # number of ReadExReq MSHR misses
967system.cpu.l2cache.ReadExReq_mshr_misses::total 131192 # number of ReadExReq MSHR misses
968system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 114 # number of demand (read+write) MSHR misses
969system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses
970system.cpu.l2cache.demand_mshr_misses::cpu.inst 22958 # number of demand (read+write) MSHR misses
971system.cpu.l2cache.demand_mshr_misses::cpu.data 145313 # number of demand (read+write) MSHR misses
972system.cpu.l2cache.demand_mshr_misses::total 168386 # number of demand (read+write) MSHR misses
973system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 114 # number of overall MSHR misses
974system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses
975system.cpu.l2cache.overall_mshr_misses::cpu.inst 22958 # number of overall MSHR misses
976system.cpu.l2cache.overall_mshr_misses::cpu.data 145313 # number of overall MSHR misses
977system.cpu.l2cache.overall_mshr_misses::total 168386 # number of overall MSHR misses
978system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 8305000 # number of ReadReq MSHR miss cycles
979system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 70000 # number of ReadReq MSHR miss cycles
980system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1550026348 # number of ReadReq MSHR miss cycles
981system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1005062888 # number of ReadReq MSHR miss cycles
982system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2563464236 # number of ReadReq MSHR miss cycles
983system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 49859307 # number of UpgradeReq MSHR miss cycles
984system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 49859307 # number of UpgradeReq MSHR miss cycles
985system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 136000 # number of SCUpgradeReq MSHR miss cycles
986system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 136000 # number of SCUpgradeReq MSHR miss cycles
987system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8531883047 # number of ReadExReq MSHR miss cycles
988system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8531883047 # number of ReadExReq MSHR miss cycles
989system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8305000 # number of demand (read+write) MSHR miss cycles
990system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 70000 # number of demand (read+write) MSHR miss cycles
991system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1550026348 # number of demand (read+write) MSHR miss cycles
992system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9536945935 # number of demand (read+write) MSHR miss cycles
993system.cpu.l2cache.demand_mshr_miss_latency::total 11095347283 # number of demand (read+write) MSHR miss cycles
994system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8305000 # number of overall MSHR miss cycles
995system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 70000 # number of overall MSHR miss cycles
996system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1550026348 # number of overall MSHR miss cycles
997system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9536945935 # number of overall MSHR miss cycles
998system.cpu.l2cache.overall_mshr_miss_latency::total 11095347283 # number of overall MSHR miss cycles
999system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 191729750 # number of ReadReq MSHR uncacheable cycles
1000system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5400527000 # number of ReadReq MSHR uncacheable cycles
1001system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5592256750 # number of ReadReq MSHR uncacheable cycles
1002system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151319000 # number of WriteReq MSHR uncacheable cycles
1003system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151319000 # number of WriteReq MSHR uncacheable cycles
1004system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 191729750 # number of overall MSHR uncacheable cycles
1005system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9551846000 # number of overall MSHR uncacheable cycles
1006system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9743575750 # number of overall MSHR uncacheable cycles
1007system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001627 # mshr miss rate for ReadReq accesses
1008system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for ReadReq accesses
1009system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007919 # mshr miss rate for ReadReq accesses
1010system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025813 # mshr miss rate for ReadReq accesses
1011system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010564 # mshr miss rate for ReadReq accesses
1012system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982843 # mshr miss rate for UpgradeReq accesses
1013system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982843 # mshr miss rate for UpgradeReq accesses
1014system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
1015system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1016system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443805 # mshr miss rate for ReadExReq accesses
1017system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443805 # mshr miss rate for ReadExReq accesses
1018system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001627 # mshr miss rate for demand accesses
1019system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for demand accesses
1020system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007919 # mshr miss rate for demand accesses
1021system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172448 # mshr miss rate for demand accesses
1022system.cpu.l2cache.demand_mshr_miss_rate::total 0.044123 # mshr miss rate for demand accesses
1023system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001627 # mshr miss rate for overall accesses
1024system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for overall accesses
1025system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007919 # mshr miss rate for overall accesses
1026system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172448 # mshr miss rate for overall accesses
1027system.cpu.l2cache.overall_mshr_miss_rate::total 0.044123 # mshr miss rate for overall accesses
1028system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72850.877193 # average ReadReq mshr miss latency
1029system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70000 # average ReadReq mshr miss latency
1030system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67515.739524 # average ReadReq mshr miss latency
1031system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71175.050492 # average ReadReq mshr miss latency
1032system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68921.445287 # average ReadReq mshr miss latency
1033system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17762.489134 # average UpgradeReq mshr miss latency
1034system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17762.489134 # average UpgradeReq mshr miss latency
1035system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68000 # average SCUpgradeReq mshr miss latency
1036system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68000 # average SCUpgradeReq mshr miss latency
1037system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65033.561856 # average ReadExReq mshr miss latency
1038system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65033.561856 # average ReadExReq mshr miss latency
1039system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72850.877193 # average overall mshr miss latency
1040system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency
1041system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67515.739524 # average overall mshr miss latency
1042system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65630.369857 # average overall mshr miss latency
1043system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65892.338336 # average overall mshr miss latency
1044system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72850.877193 # average overall mshr miss latency
1045system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency
1046system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67515.739524 # average overall mshr miss latency
1047system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65630.369857 # average overall mshr miss latency
1048system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65892.338336 # average overall mshr miss latency
1049system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
1050system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1051system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1052system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1053system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1054system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
1055system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1056system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1057system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1058system.cpu.toL2Bus.trans_dist::ReadReq 3579627 # Transaction distribution
1059system.cpu.toL2Bus.trans_dist::ReadResp 3579531 # Transaction distribution
1060system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution
1061system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution
1062system.cpu.toL2Bus.trans_dist::Writeback 697919 # Transaction distribution
1063system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution
1064system.cpu.toL2Bus.trans_dist::UpgradeReq 2856 # Transaction distribution
1065system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1066system.cpu.toL2Bus.trans_dist::UpgradeResp 2858 # Transaction distribution
1067system.cpu.toL2Bus.trans_dist::ReadExReq 295607 # Transaction distribution
1068system.cpu.toL2Bus.trans_dist::ReadExResp 295607 # Transaction distribution
1069system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5804583 # Packet count per connected master and slave (bytes)
1070system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506486 # Packet count per connected master and slave (bytes)
1071system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15045 # Packet count per connected master and slave (bytes)
1072system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158423 # Packet count per connected master and slave (bytes)
1073system.cpu.toL2Bus.pkt_count::total 8484537 # Packet count per connected master and slave (bytes)
1074system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185746048 # Cumulative packet size per connected master and slave (bytes)
1075system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98788181 # Cumulative packet size per connected master and slave (bytes)
1076system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17908 # Cumulative packet size per connected master and slave (bytes)
1077system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 280260 # Cumulative packet size per connected master and slave (bytes)
1078system.cpu.toL2Bus.pkt_size::total 284832397 # Cumulative packet size per connected master and slave (bytes)
1079system.cpu.toL2Bus.snoops 61029 # Total snoops (count)
1080system.cpu.toL2Bus.snoop_fanout::samples 4577967 # Request fanout histogram
1081system.cpu.toL2Bus.snoop_fanout::mean 3.007970 # Request fanout histogram
1082system.cpu.toL2Bus.snoop_fanout::stdev 0.088920 # Request fanout histogram
1083system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1084system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1085system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1086system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1087system.cpu.toL2Bus.snoop_fanout::3 4541479 99.20% 99.20% # Request fanout histogram
1088system.cpu.toL2Bus.snoop_fanout::4 36488 0.80% 100.00% # Request fanout histogram
1089system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1090system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1091system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
1092system.cpu.toL2Bus.snoop_fanout::total 4577967 # Request fanout histogram
1093system.cpu.toL2Bus.reqLayer0.occupancy 3013390750 # Layer occupancy (ticks)
1094system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1095system.cpu.toL2Bus.snoopLayer0.occupancy 208500 # Layer occupancy (ticks)
1096system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1097system.cpu.toL2Bus.respLayer0.occupancy 4358889625 # Layer occupancy (ticks)
1098system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
1099system.cpu.toL2Bus.respLayer1.occupancy 1341438850 # Layer occupancy (ticks)
1100system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1101system.cpu.toL2Bus.respLayer2.occupancy 10568000 # Layer occupancy (ticks)
1102system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1103system.cpu.toL2Bus.respLayer3.occupancy 88362250 # Layer occupancy (ticks)
1104system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1105system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
1106system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
1107system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
1108system.iobus.trans_dist::WriteResp 22790 # Transaction distribution
1109system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
1110system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
1111system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
1112system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
1113system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
1114system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
1115system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
1116system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
1117system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1118system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)

--- 4 unchanged lines hidden (view full) ---

1123system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
1124system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
1125system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
1126system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
1127system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
1128system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
1129system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
1130system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1131system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
1132system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
1133system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
1134system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes)
1135system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
1136system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
1137system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
1138system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
1139system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
1140system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
1141system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
1142system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1143system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)

--- 4 unchanged lines hidden (view full) ---

1148system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
1149system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
1150system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1151system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
1152system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
1153system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
1154system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
1155system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1156system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
1157system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
1158system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
1159system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes)
1160system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks)
1161system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1162system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
1163system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1164system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
1165system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1166system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
1167system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1168system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)

--- 23 unchanged lines hidden (view full) ---

1192system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
1193system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1194system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
1195system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1196system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
1197system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1198system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
1199system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1200system.iobus.reqLayer27.occupancy 198914708 # Layer occupancy (ticks)
1201system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1202system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
1203system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1204system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
1205system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1206system.iobus.respLayer3.occupancy 36809505 # Layer occupancy (ticks)
1207system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1208system.iocache.tags.replacements 36424 # number of replacements
1209system.iocache.tags.tagsinuse 1.032937 # Cycle average of tags in use
1210system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1211system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
1212system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1213system.iocache.tags.warmup_cycle 270823051000 # Cycle when the warmup percentage was hit.
1214system.iocache.tags.occ_blocks::realview.ide 1.032937 # Average occupied blocks per requestor
1215system.iocache.tags.occ_percent::realview.ide 0.064559 # Average percentage of cache occupancy
1216system.iocache.tags.occ_percent::total 0.064559 # Average percentage of cache occupancy
1217system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1218system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1219system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1220system.iocache.tags.tag_accesses 328122 # Number of tag accesses
1221system.iocache.tags.data_accesses 328122 # Number of data accesses
1222system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
1223system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
1224system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
1225system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
1226system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses
1227system.iocache.demand_misses::total 234 # number of demand (read+write) misses
1228system.iocache.overall_misses::realview.ide 234 # number of overall misses
1229system.iocache.overall_misses::total 234 # number of overall misses
1230system.iocache.ReadReq_miss_latency::realview.ide 29244877 # number of ReadReq miss cycles
1231system.iocache.ReadReq_miss_latency::total 29244877 # number of ReadReq miss cycles
1232system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6652334326 # number of WriteInvalidateReq miss cycles
1233system.iocache.WriteInvalidateReq_miss_latency::total 6652334326 # number of WriteInvalidateReq miss cycles
1234system.iocache.demand_miss_latency::realview.ide 29244877 # number of demand (read+write) miss cycles
1235system.iocache.demand_miss_latency::total 29244877 # number of demand (read+write) miss cycles
1236system.iocache.overall_miss_latency::realview.ide 29244877 # number of overall miss cycles
1237system.iocache.overall_miss_latency::total 29244877 # number of overall miss cycles
1238system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
1239system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
1240system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
1241system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
1242system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses
1243system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses
1244system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses
1245system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses
1246system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1247system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1248system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
1249system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1250system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1251system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1252system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1253system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1254system.iocache.ReadReq_avg_miss_latency::realview.ide 124978.106838 # average ReadReq miss latency
1255system.iocache.ReadReq_avg_miss_latency::total 124978.106838 # average ReadReq miss latency
1256system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183644.388417 # average WriteInvalidateReq miss latency
1257system.iocache.WriteInvalidateReq_avg_miss_latency::total 183644.388417 # average WriteInvalidateReq miss latency
1258system.iocache.demand_avg_miss_latency::realview.ide 124978.106838 # average overall miss latency
1259system.iocache.demand_avg_miss_latency::total 124978.106838 # average overall miss latency
1260system.iocache.overall_avg_miss_latency::realview.ide 124978.106838 # average overall miss latency
1261system.iocache.overall_avg_miss_latency::total 124978.106838 # average overall miss latency
1262system.iocache.blocked_cycles::no_mshrs 22952 # number of cycles access was blocked
1263system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1264system.iocache.blocked::no_mshrs 3496 # number of cycles access was blocked
1265system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1266system.iocache.avg_blocked_cycles::no_mshrs 6.565217 # average number of cycles each access was blocked
1267system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1268system.iocache.fast_writes 0 # number of fast writes performed
1269system.iocache.cache_copies 0 # number of cache copies performed
1270system.iocache.writebacks::writebacks 36190 # number of writebacks
1271system.iocache.writebacks::total 36190 # number of writebacks
1272system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses
1273system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses
1274system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses
1275system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses
1276system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses
1277system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses
1278system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses
1279system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
1280system.iocache.ReadReq_mshr_miss_latency::realview.ide 16937877 # number of ReadReq MSHR miss cycles
1281system.iocache.ReadReq_mshr_miss_latency::total 16937877 # number of ReadReq MSHR miss cycles
1282system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4768676336 # number of WriteInvalidateReq MSHR miss cycles
1283system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4768676336 # number of WriteInvalidateReq MSHR miss cycles
1284system.iocache.demand_mshr_miss_latency::realview.ide 16937877 # number of demand (read+write) MSHR miss cycles
1285system.iocache.demand_mshr_miss_latency::total 16937877 # number of demand (read+write) MSHR miss cycles
1286system.iocache.overall_mshr_miss_latency::realview.ide 16937877 # number of overall MSHR miss cycles
1287system.iocache.overall_mshr_miss_latency::total 16937877 # number of overall MSHR miss cycles
1288system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1289system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1290system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1291system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1292system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1293system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1294system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1295system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1296system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72384.089744 # average ReadReq mshr miss latency
1297system.iocache.ReadReq_avg_mshr_miss_latency::total 72384.089744 # average ReadReq mshr miss latency
1298system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131644.112633 # average WriteInvalidateReq mshr miss latency
1299system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131644.112633 # average WriteInvalidateReq mshr miss latency
1300system.iocache.demand_avg_mshr_miss_latency::realview.ide 72384.089744 # average overall mshr miss latency
1301system.iocache.demand_avg_mshr_miss_latency::total 72384.089744 # average overall mshr miss latency
1302system.iocache.overall_avg_mshr_miss_latency::realview.ide 72384.089744 # average overall mshr miss latency
1303system.iocache.overall_avg_mshr_miss_latency::total 72384.089744 # average overall mshr miss latency
1304system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1305system.membus.trans_dist::ReadReq 71726 # Transaction distribution
1306system.membus.trans_dist::ReadResp 71726 # Transaction distribution
1307system.membus.trans_dist::WriteReq 27583 # Transaction distribution
1308system.membus.trans_dist::WriteResp 27583 # Transaction distribution
1309system.membus.trans_dist::Writeback 124578 # Transaction distribution
1310system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
1311system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
1312system.membus.trans_dist::UpgradeReq 4604 # Transaction distribution
1313system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1314system.membus.trans_dist::UpgradeResp 4606 # Transaction distribution
1315system.membus.trans_dist::ReadExReq 129395 # Transaction distribution
1316system.membus.trans_dist::ReadExResp 129395 # Transaction distribution
1317system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
1318system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
1319system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes)
1320system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446695 # Packet count per connected master and slave (bytes)
1321system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554255 # Packet count per connected master and slave (bytes)
1322system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes)
1323system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes)
1324system.membus.pkt_count::total 663142 # Packet count per connected master and slave (bytes)
1325system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
1326system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
1327system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes)
1328system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16522776 # Cumulative packet size per connected master and slave (bytes)
1329system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16686485 # Cumulative packet size per connected master and slave (bytes)
1330system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
1331system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
1332system.membus.pkt_size::total 21321941 # Cumulative packet size per connected master and slave (bytes)
1333system.membus.snoops 504 # Total snoops (count)
1334system.membus.snoop_fanout::samples 332271 # Request fanout histogram
1335system.membus.snoop_fanout::mean 1 # Request fanout histogram
1336system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1337system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1338system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1339system.membus.snoop_fanout::1 332271 100.00% 100.00% # Request fanout histogram
1340system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1341system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1342system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1343system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1344system.membus.snoop_fanout::total 332271 # Request fanout histogram
1345system.membus.reqLayer0.occupancy 90362500 # Layer occupancy (ticks)
1346system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1347system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
1348system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1349system.membus.reqLayer2.occupancy 1704000 # Layer occupancy (ticks)
1350system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1351system.membus.reqLayer5.occupancy 1022735199 # Layer occupancy (ticks)
1352system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1353system.membus.respLayer2.occupancy 997821410 # Layer occupancy (ticks)
1354system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1355system.membus.respLayer3.occupancy 37468495 # Layer occupancy (ticks)
1356system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1357system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1358system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1359system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1360system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1361system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1362system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1363system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR

--- 26 unchanged lines hidden ---