Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt

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stats.txt (11860:67dee11badea)	stats.txt (11957:90bb43dfc028)
1 2---------- Begin Simulation Statistics ----------	1 2---------- Begin Simulation Statistics ----------
3sim_seconds 2.848599 # Number of seconds simulated 4sim_ticks 2848598682500 # Number of ticks simulated 5final_tick 2848598682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 262669 # Simulator instruction rate (inst/s) 8host_op_rate 318064 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5881753499 # Simulator tick rate (ticks/s) 10host_mem_usage 626168 # Number of bytes of host memory used 11host_seconds 484.31 # Real time elapsed on the host 12sim_insts 127213455 # Number of instructions simulated 13sim_ops 154041729 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 9280 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1663936 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1359352 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8597824 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 1280 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 234560 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 659412 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 325376 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 27system.physmem.bytes_read::total 12852044 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 1663936 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 234560 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 1898496 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 8978368 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 34system.physmem.bytes_written::total 8995932 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 145 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 25999 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 21764 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 134341 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 20 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.inst 3665 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.data 10324 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.l2cache.prefetcher 5084 # Number of read requests responded to by this memory 44system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 45system.physmem.num_reads::total 201358 # Number of read requests responded to by this memory 46system.physmem.num_writes::writebacks 140287 # Number of write requests responded to by this memory 47system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 49system.physmem.num_writes::total 144678 # Number of write requests responded to by this memory 50system.physmem.bw_read::cpu0.dtb.walker 3258 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.inst 584124 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.data 477200 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.l2cache.prefetcher 3018264 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.dtb.walker 449 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.inst 82342 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.data 231486 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.l2cache.prefetcher 114223 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::total 4511707 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu0.inst 584124 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::cpu1.inst 82342 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::total 666467 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_write::writebacks 3151854 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_write::cpu0.data 6152 # Write bandwidth from this memory (bytes/s) 66system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::total 3158020 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_total::writebacks 3151854 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.dtb.walker 3258 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.inst 584124 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.data 483352 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.l2cache.prefetcher 3018264 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.dtb.walker 449 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.inst 82342 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.data 231500 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.l2cache.prefetcher 114223 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::total 7669728 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.readReqs 201358 # Number of read requests accepted 81system.physmem.writeReqs 144678 # Number of write requests accepted 82system.physmem.readBursts 201358 # Number of DRAM read bursts, including those serviced by the write queue 83system.physmem.writeBursts 144678 # Number of DRAM write bursts, including those merged in the write queue 84system.physmem.bytesReadDRAM 12877760 # Total number of bytes read from DRAM 85system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue 86system.physmem.bytesWritten 9008896 # Total number of bytes written to DRAM 87system.physmem.bytesReadSys 12852044 # Total read bytes from the system interface side 88system.physmem.bytesWrittenSys 8995932 # Total written bytes from the system interface side 89system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue 90system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one 91system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 92system.physmem.perBankRdBursts::0 12337 # Per bank write bursts 93system.physmem.perBankRdBursts::1 12726 # Per bank write bursts 94system.physmem.perBankRdBursts::2 13547 # Per bank write bursts 95system.physmem.perBankRdBursts::3 13037 # Per bank write bursts 96system.physmem.perBankRdBursts::4 15119 # Per bank write bursts 97system.physmem.perBankRdBursts::5 12845 # Per bank write bursts 98system.physmem.perBankRdBursts::6 12657 # Per bank write bursts 99system.physmem.perBankRdBursts::7 13022 # Per bank write bursts 100system.physmem.perBankRdBursts::8 12280 # Per bank write bursts 101system.physmem.perBankRdBursts::9 12341 # Per bank write bursts 102system.physmem.perBankRdBursts::10 11583 # Per bank write bursts 103system.physmem.perBankRdBursts::11 10739 # Per bank write bursts 104system.physmem.perBankRdBursts::12 12026 # Per bank write bursts 105system.physmem.perBankRdBursts::13 12946 # Per bank write bursts 106system.physmem.perBankRdBursts::14 12179 # Per bank write bursts 107system.physmem.perBankRdBursts::15 11831 # Per bank write bursts 108system.physmem.perBankWrBursts::0 8873 # Per bank write bursts 109system.physmem.perBankWrBursts::1 9291 # Per bank write bursts 110system.physmem.perBankWrBursts::2 9856 # Per bank write bursts 111system.physmem.perBankWrBursts::3 9274 # Per bank write bursts 112system.physmem.perBankWrBursts::4 8405 # Per bank write bursts 113system.physmem.perBankWrBursts::5 8988 # Per bank write bursts 114system.physmem.perBankWrBursts::6 8961 # Per bank write bursts 115system.physmem.perBankWrBursts::7 9107 # Per bank write bursts 116system.physmem.perBankWrBursts::8 8695 # Per bank write bursts 117system.physmem.perBankWrBursts::9 8769 # Per bank write bursts 118system.physmem.perBankWrBursts::10 8272 # Per bank write bursts 119system.physmem.perBankWrBursts::11 7845 # Per bank write bursts 120system.physmem.perBankWrBursts::12 8751 # Per bank write bursts 121system.physmem.perBankWrBursts::13 8985 # Per bank write bursts 122system.physmem.perBankWrBursts::14 8630 # Per bank write bursts 123system.physmem.perBankWrBursts::15 8062 # Per bank write bursts 124system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 125system.physmem.numWrRetry 74 # Number of times write queue was full causing retry 126system.physmem.totGap 2848598144000 # Total gap between requests 127system.physmem.readPktSize::0 0 # Read request sizes (log2) 128system.physmem.readPktSize::1 0 # Read request sizes (log2) 129system.physmem.readPktSize::2 555 # Read request sizes (log2) 130system.physmem.readPktSize::3 28 # Read request sizes (log2) 131system.physmem.readPktSize::4 0 # Read request sizes (log2) 132system.physmem.readPktSize::5 0 # Read request sizes (log2) 133system.physmem.readPktSize::6 200775 # Read request sizes (log2) 134system.physmem.writePktSize::0 0 # Write request sizes (log2) 135system.physmem.writePktSize::1 0 # Write request sizes (log2) 136system.physmem.writePktSize::2 4391 # Write request sizes (log2) 137system.physmem.writePktSize::3 0 # Write request sizes (log2) 138system.physmem.writePktSize::4 0 # Write request sizes (log2) 139system.physmem.writePktSize::5 0 # Write request sizes (log2) 140system.physmem.writePktSize::6 140287 # Write request sizes (log2) 141system.physmem.rdQLenPdf::0 85113 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::1 63389 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::2 11790 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::3 9690 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::4 8148 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::5 6744 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::6 5598 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::7 4878 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::8 4009 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::9 1035 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::10 281 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::11 239 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::12 165 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::13 134 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 173system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::15 2537 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::16 3403 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::17 4421 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::18 5052 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::19 6114 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::20 6454 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::21 7065 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::22 7505 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::23 8553 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::24 8479 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::25 9706 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::26 10172 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::27 8910 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::28 8556 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::29 8923 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::30 9945 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::31 8410 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::32 8137 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::33 883 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::34 583 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::35 478 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::36 405 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::37 334 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::38 317 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::39 271 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::40 267 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::41 249 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::42 284 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::43 263 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::44 264 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::45 233 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::46 283 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::47 221 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::48 181 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::49 223 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::50 208 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::51 239 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::52 202 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::53 172 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::54 173 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::55 184 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::56 209 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::57 195 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::58 131 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::59 188 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::60 225 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::61 216 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::62 128 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::63 216 # What write queue length does an incoming req see 237system.physmem.bytesPerActivate::samples 88566 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::mean 247.121830 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::gmean 141.476955 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::stdev 302.598654 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::0-127 44693 50.46% 50.46% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::128-255 18724 21.14% 71.60% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::256-383 6637 7.49% 79.10% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::384-511 3795 4.28% 83.38% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::512-639 2919 3.30% 86.68% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::640-767 1572 1.77% 88.45% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::768-895 960 1.08% 89.54% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::896-1023 1024 1.16% 90.69% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::1024-1151 8242 9.31% 100.00% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::total 88566 # Bytes accessed per row activation 251system.physmem.rdPerTurnAround::samples 6985 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::mean 28.806586 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::stdev 558.021687 # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::0-2047 6983 99.97% 99.97% # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::total 6985 # Reads before turning the bus around for writes 258system.physmem.wrPerTurnAround::samples 6985 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::mean 20.152326 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::gmean 18.495944 # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::stdev 14.110349 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::16-19 5869 84.02% 84.02% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::20-23 441 6.31% 90.34% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::24-27 79 1.13% 91.47% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::28-31 44 0.63% 92.10% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::32-35 241 3.45% 95.55% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::36-39 25 0.36% 95.91% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::40-43 15 0.21% 96.12% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::44-47 10 0.14% 96.26% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::48-51 17 0.24% 96.51% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::52-55 8 0.11% 96.62% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::56-59 3 0.04% 96.66% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::60-63 7 0.10% 96.76% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::64-67 146 2.09% 98.85% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::68-71 4 0.06% 98.91% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::72-75 4 0.06% 98.97% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::76-79 6 0.09% 99.06% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::80-83 7 0.10% 99.16% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::88-91 1 0.01% 99.17% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::92-95 2 0.03% 99.20% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::96-99 3 0.04% 99.24% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::104-107 3 0.04% 99.28% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::108-111 11 0.16% 99.44% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::116-119 2 0.03% 99.47% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::124-127 2 0.03% 99.50% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::128-131 10 0.14% 99.64% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::136-139 2 0.03% 99.67% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::140-143 3 0.04% 99.71% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::144-147 3 0.04% 99.76% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::156-159 3 0.04% 99.80% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::160-163 2 0.03% 99.83% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::172-175 3 0.04% 99.87% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::176-179 1 0.01% 99.89% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::180-183 2 0.03% 99.91% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::188-191 2 0.03% 99.94% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::192-195 3 0.04% 99.99% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::240-243 1 0.01% 100.00% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::total 6985 # Writes before turning the bus around for reads 299system.physmem.totQLat 9483410947 # Total ticks spent queuing 300system.physmem.totMemAccLat 13256192197 # Total ticks spent from burst creation until serviced by the DRAM 301system.physmem.totBusLat 1006075000 # Total ticks spent in databus transfers 302system.physmem.avgQLat 47130.74 # Average queueing delay per DRAM burst 303system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 304system.physmem.avgMemAccLat 65880.74 # Average memory access latency per DRAM burst 305system.physmem.avgRdBW 4.52 # Average DRAM read bandwidth in MiByte/s 306system.physmem.avgWrBW 3.16 # Average achieved write bandwidth in MiByte/s 307system.physmem.avgRdBWSys 4.51 # Average system read bandwidth in MiByte/s 308system.physmem.avgWrBWSys 3.16 # Average system write bandwidth in MiByte/s 309system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 310system.physmem.busUtil 0.06 # Data bus utilization in percentage 311system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 312system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 313system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 314system.physmem.avgWrQLen 26.98 # Average write queue length when enqueuing 315system.physmem.readRowHits 166670 # Number of row buffer hits during reads 316system.physmem.writeRowHits 86742 # Number of row buffer hits during writes 317system.physmem.readRowHitRate 82.83 # Row buffer hit rate for reads 318system.physmem.writeRowHitRate 61.61 # Row buffer hit rate for writes 319system.physmem.avgGap 8232086.10 # Average gap between requests 320system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined 321system.physmem_0.actEnergy 334044900 # Energy for activate commands per rank (pJ) 322system.physmem_0.preEnergy 177549075 # Energy for precharge commands per rank (pJ) 323system.physmem_0.readEnergy 751770600 # Energy for read commands per rank (pJ) 324system.physmem_0.writeEnergy 379781100 # Energy for write commands per rank (pJ) 325system.physmem_0.refreshEnergy 5711234880.000001 # Energy for refresh commands per rank (pJ) 326system.physmem_0.actBackEnergy 5249821980 # Energy for active background per rank (pJ) 327system.physmem_0.preBackEnergy 307614240 # Energy for precharge background per rank (pJ) 328system.physmem_0.actPowerDownEnergy 11585671230 # Energy for active power-down per rank (pJ) 329system.physmem_0.prePowerDownEnergy 8434613280 # Energy for precharge power-down per rank (pJ) 330system.physmem_0.selfRefreshEnergy 670304268120 # Energy for self refresh per rank (pJ) 331system.physmem_0.totalEnergy 703238620035 # Total energy per rank (pJ) 332system.physmem_0.averagePower 246.871777 # Core power per rank (mW) 333system.physmem_0.totalIdleTime 2836104738853 # Total Idle time Per DRAM Rank 334system.physmem_0.memoryStateTime::IDLE 545953693 # Time in different power states 335system.physmem_0.memoryStateTime::REF 2426690000 # Time in different power states 336system.physmem_0.memoryStateTime::SREF 2788907518000 # Time in different power states 337system.physmem_0.memoryStateTime::PRE_PDN 21965166332 # Time in different power states 338system.physmem_0.memoryStateTime::ACT 9346009704 # Time in different power states 339system.physmem_0.memoryStateTime::ACT_PDN 25407344771 # Time in different power states 340system.physmem_1.actEnergy 298323480 # Energy for activate commands per rank (pJ) 341system.physmem_1.preEnergy 158558895 # Energy for precharge commands per rank (pJ) 342system.physmem_1.readEnergy 684904500 # Energy for read commands per rank (pJ) 343system.physmem_1.writeEnergy 355006980 # Energy for write commands per rank (pJ) 344system.physmem_1.refreshEnergy 5713078800.000001 # Energy for refresh commands per rank (pJ) 345system.physmem_1.actBackEnergy 5198973990 # Energy for active background per rank (pJ) 346system.physmem_1.preBackEnergy 317598720 # Energy for precharge background per rank (pJ) 347system.physmem_1.actPowerDownEnergy 10947475860 # Energy for active power-down per rank (pJ) 348system.physmem_1.prePowerDownEnergy 8696180160 # Energy for precharge power-down per rank (pJ) 349system.physmem_1.selfRefreshEnergy 670560217290 # Energy for self refresh per rank (pJ) 350system.physmem_1.totalEnergy 702932935245 # Total energy per rank (pJ) 351system.physmem_1.averagePower 246.764467 # Core power per rank (mW) 352system.physmem_1.totalIdleTime 2836364452001 # Total Idle time Per DRAM Rank 353system.physmem_1.memoryStateTime::IDLE 573854684 # Time in different power states 354system.physmem_1.memoryStateTime::REF 2428124000 # Time in different power states 355system.physmem_1.memoryStateTime::SREF 2789710596750 # Time in different power states 356system.physmem_1.memoryStateTime::PRE_PDN 22646269258 # Time in different power states 357system.physmem_1.memoryStateTime::ACT 9232187315 # Time in different power states 358system.physmem_1.memoryStateTime::ACT_PDN 24007650493 # Time in different power states 359system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 360system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory 361system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory 362system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory 363system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory 364system.realview.nvmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory 365system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory 366system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 367system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory 368system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory 369system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s) 371system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s) 372system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) 373system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s) 374system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s) 375system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) 376system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) 377system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) 378system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 379system.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 380system.bridge.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 381system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 382system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 383system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 384system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 385system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 386system.cf0.dma_write_txs 631 # Number of DMA write transactions. 387system.cpu0.branchPred.lookups 21387746 # Number of BP lookups 388system.cpu0.branchPred.condPredicted 14055793 # Number of conditional branches predicted 389system.cpu0.branchPred.condIncorrect 1067110 # Number of conditional branches incorrect 390system.cpu0.branchPred.BTBLookups 13655999 # Number of BTB lookups 391system.cpu0.branchPred.BTBHits 8982856 # Number of BTB hits 392system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 393system.cpu0.branchPred.BTBHitPct 65.779560 # BTB Hit Percentage 394system.cpu0.branchPred.usedRAS 3510572 # Number of times the RAS was used to get a target. 395system.cpu0.branchPred.RASInCorrect 218030 # Number of incorrect RAS predictions. 396system.cpu0.branchPred.indirectLookups 788067 # Number of indirect predictor lookups. 397system.cpu0.branchPred.indirectHits 592988 # Number of indirect target hits. 398system.cpu0.branchPred.indirectMisses 195079 # Number of indirect misses. 399system.cpu0.branchPredindirectMispredicted 105213 # Number of mispredicted indirect branches. 400system.cpu_clk_domain.clock 500 # Clock period in ticks 401system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 402system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 403system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 404system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 405system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 406system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 407system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 408system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 409system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 410system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 411system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 412system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 413system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 414system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 415system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 416system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 417system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 418system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 419system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 420system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 421system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 422system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 423system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 424system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 425system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 426system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 427system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 428system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 429system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 430system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 431system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 432system.cpu0.dtb.walker.walks 69629 # Table walker walks requested 433system.cpu0.dtb.walker.walksShort 69629 # Table walker walks initiated with short descriptors 434system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46094 # Level at which table walker walks with short descriptors terminate 435system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23535 # Level at which table walker walks with short descriptors terminate 436system.cpu0.dtb.walker.walkWaitTime::samples 69629 # Table walker wait (enqueue to first request) latency 437system.cpu0.dtb.walker.walkWaitTime::0 69629 100.00% 100.00% # Table walker wait (enqueue to first request) latency 438system.cpu0.dtb.walker.walkWaitTime::total 69629 # Table walker wait (enqueue to first request) latency 439system.cpu0.dtb.walker.walkCompletionTime::samples 7649 # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::mean 12135.050333 # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::gmean 10988.955041 # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::stdev 11832.363963 # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::0-65535 7639 99.87% 99.87% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6 0.08% 99.95% # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::196608-262143 2 0.03% 99.97% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.03% 100.00% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::total 7649 # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walksPending::samples 338892000 # Table walker pending requests distribution 449system.cpu0.dtb.walker.walksPending::0 338892000 100.00% 100.00% # Table walker pending requests distribution 450system.cpu0.dtb.walker.walksPending::total 338892000 # Table walker pending requests distribution 451system.cpu0.dtb.walker.walkPageSizes::4K 5959 77.91% 77.91% # Table walker page sizes translated 452system.cpu0.dtb.walker.walkPageSizes::1M 1690 22.09% 100.00% # Table walker page sizes translated 453system.cpu0.dtb.walker.walkPageSizes::total 7649 # Table walker page sizes translated 454system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 69629 # Table walker requests started/completed, data/inst 455system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 456system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 69629 # Table walker requests started/completed, data/inst 457system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7649 # Table walker requests started/completed, data/inst 458system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 459system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7649 # Table walker requests started/completed, data/inst 460system.cpu0.dtb.walker.walkRequestOrigin::total 77278 # Table walker requests started/completed, data/inst 461system.cpu0.dtb.inst_hits 0 # ITB inst hits 462system.cpu0.dtb.inst_misses 0 # ITB inst misses 463system.cpu0.dtb.read_hits 17966885 # DTB read hits 464system.cpu0.dtb.read_misses 63028 # DTB read misses 465system.cpu0.dtb.write_hits 15039551 # DTB write hits 466system.cpu0.dtb.write_misses 6601 # DTB write misses 467system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 468system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 469system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 470system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 471system.cpu0.dtb.flush_entries 3754 # Number of entries that have been flushed from TLB 472system.cpu0.dtb.align_faults 1491 # Number of TLB faults due to alignment restrictions 473system.cpu0.dtb.prefetch_faults 2059 # Number of TLB faults due to prefetch 474system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 475system.cpu0.dtb.perms_faults 586 # Number of TLB faults due to permissions restrictions 476system.cpu0.dtb.read_accesses 18029913 # DTB read accesses 477system.cpu0.dtb.write_accesses 15046152 # DTB write accesses 478system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 479system.cpu0.dtb.hits 33006436 # DTB hits 480system.cpu0.dtb.misses 69629 # DTB misses 481system.cpu0.dtb.accesses 33076065 # DTB accesses 482system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 483system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 489system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 490system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 491system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 492system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 493system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 494system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 495system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 496system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 497system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 498system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 499system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 500system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 501system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 502system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 503system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 504system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 505system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 506system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 507system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 508system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 509system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 510system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 511system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 512system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 513system.cpu0.itb.walker.walks 4318 # Table walker walks requested 514system.cpu0.itb.walker.walksShort 4318 # Table walker walks initiated with short descriptors 515system.cpu0.itb.walker.walksShortTerminationLevel::Level1 325 # Level at which table walker walks with short descriptors terminate 516system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3993 # Level at which table walker walks with short descriptors terminate 517system.cpu0.itb.walker.walkWaitTime::samples 4318 # Table walker wait (enqueue to first request) latency 518system.cpu0.itb.walker.walkWaitTime::0 4318 100.00% 100.00% # Table walker wait (enqueue to first request) latency 519system.cpu0.itb.walker.walkWaitTime::total 4318 # Table walker wait (enqueue to first request) latency 520system.cpu0.itb.walker.walkCompletionTime::samples 2683 # Table walker service (enqueue to completion) latency 521system.cpu0.itb.walker.walkCompletionTime::mean 12304.137160 # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::gmean 11560.884208 # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::stdev 4695.711947 # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::0-8191 502 18.71% 18.71% # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walkCompletionTime::8192-16383 1984 73.95% 92.66% # Table walker service (enqueue to completion) latency 526system.cpu0.itb.walker.walkCompletionTime::16384-24575 147 5.48% 98.14% # Table walker service (enqueue to completion) latency 527system.cpu0.itb.walker.walkCompletionTime::24576-32767 31 1.16% 99.29% # Table walker service (enqueue to completion) latency 528system.cpu0.itb.walker.walkCompletionTime::32768-40959 18 0.67% 99.96% # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::total 2683 # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walksPending::samples 338263500 # Table walker pending requests distribution 532system.cpu0.itb.walker.walksPending::0 338263500 100.00% 100.00% # Table walker pending requests distribution 533system.cpu0.itb.walker.walksPending::total 338263500 # Table walker pending requests distribution 534system.cpu0.itb.walker.walkPageSizes::4K 2363 88.07% 88.07% # Table walker page sizes translated 535system.cpu0.itb.walker.walkPageSizes::1M 320 11.93% 100.00% # Table walker page sizes translated 536system.cpu0.itb.walker.walkPageSizes::total 2683 # Table walker page sizes translated 537system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 538system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4318 # Table walker requests started/completed, data/inst 539system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4318 # Table walker requests started/completed, data/inst 540system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 541system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2683 # Table walker requests started/completed, data/inst 542system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2683 # Table walker requests started/completed, data/inst 543system.cpu0.itb.walker.walkRequestOrigin::total 7001 # Table walker requests started/completed, data/inst 544system.cpu0.itb.inst_hits 39752533 # ITB inst hits 545system.cpu0.itb.inst_misses 4318 # ITB inst misses 546system.cpu0.itb.read_hits 0 # DTB read hits 547system.cpu0.itb.read_misses 0 # DTB read misses 548system.cpu0.itb.write_hits 0 # DTB write hits 549system.cpu0.itb.write_misses 0 # DTB write misses 550system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 551system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 552system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 553system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 554system.cpu0.itb.flush_entries 2396 # Number of entries that have been flushed from TLB 555system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 556system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 557system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 558system.cpu0.itb.perms_faults 7865 # Number of TLB faults due to permissions restrictions 559system.cpu0.itb.read_accesses 0 # DTB read accesses 560system.cpu0.itb.write_accesses 0 # DTB write accesses 561system.cpu0.itb.inst_accesses 39756851 # ITB inst accesses 562system.cpu0.itb.hits 39752533 # DTB hits 563system.cpu0.itb.misses 4318 # DTB misses 564system.cpu0.itb.accesses 39756851 # DTB accesses 565system.cpu0.numPwrStateTransitions 3708 # Number of power state transitions 566system.cpu0.pwrStateClkGateDist::samples 1854 # Distribution of time spent in the clock gated state 567system.cpu0.pwrStateClkGateDist::mean 1488611861.955232 # Distribution of time spent in the clock gated state 568system.cpu0.pwrStateClkGateDist::stdev 23946276211.601498 # Distribution of time spent in the clock gated state 569system.cpu0.pwrStateClkGateDist::underflows 1085 58.52% 58.52% # Distribution of time spent in the clock gated state 570system.cpu0.pwrStateClkGateDist::1000-5e+10 762 41.10% 99.62% # Distribution of time spent in the clock gated state 571system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.68% # Distribution of time spent in the clock gated state 572system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.05% 99.73% # Distribution of time spent in the clock gated state 573system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state 574system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state 575system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 576system.cpu0.pwrStateClkGateDist::max_value 499963838164 # Distribution of time spent in the clock gated state 577system.cpu0.pwrStateClkGateDist::total 1854 # Distribution of time spent in the clock gated state 578system.cpu0.pwrStateResidencyTicks::ON 88712290435 # Cumulative time (in ticks) in various power states 579system.cpu0.pwrStateResidencyTicks::CLK_GATED 2759886392065 # Cumulative time (in ticks) in various power states 580system.cpu0.numCycles 177427128 # number of cpu cycles simulated 581system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 582system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 583system.cpu0.committedInsts 82154396 # Number of instructions committed 584system.cpu0.committedOps 98918766 # Number of ops (including micro ops) committed 585system.cpu0.discardedOps 5358225 # Number of ops (including micro ops) which were discarded before commit 586system.cpu0.numFetchSuspends 1854 # Number of times Execute suspended instruction fetching 587system.cpu0.quiesceCycles 5519798084 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 588system.cpu0.cpi 2.159679 # CPI: cycles per instruction 589system.cpu0.ipc 0.463032 # IPC: instructions per cycle 590system.cpu0.op_class_0::No_OpClass 2315 0.00% 0.00% # Class of committed instruction 591system.cpu0.op_class_0::IntAlu 65610842 66.33% 66.33% # Class of committed instruction 592system.cpu0.op_class_0::IntMult 94061 0.10% 66.43% # Class of committed instruction 593system.cpu0.op_class_0::IntDiv 0 0.00% 66.43% # Class of committed instruction 594system.cpu0.op_class_0::FloatAdd 0 0.00% 66.43% # Class of committed instruction 595system.cpu0.op_class_0::FloatCmp 0 0.00% 66.43% # Class of committed instruction 596system.cpu0.op_class_0::FloatCvt 0 0.00% 66.43% # Class of committed instruction 597system.cpu0.op_class_0::FloatMult 0 0.00% 66.43% # Class of committed instruction 598system.cpu0.op_class_0::FloatMultAcc 0 0.00% 66.43% # Class of committed instruction 599system.cpu0.op_class_0::FloatDiv 0 0.00% 66.43% # Class of committed instruction 600system.cpu0.op_class_0::FloatMisc 0 0.00% 66.43% # Class of committed instruction 601system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.43% # Class of committed instruction 602system.cpu0.op_class_0::SimdAdd 0 0.00% 66.43% # Class of committed instruction 603system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.43% # Class of committed instruction 604system.cpu0.op_class_0::SimdAlu 0 0.00% 66.43% # Class of committed instruction 605system.cpu0.op_class_0::SimdCmp 0 0.00% 66.43% # Class of committed instruction 606system.cpu0.op_class_0::SimdCvt 0 0.00% 66.43% # Class of committed instruction 607system.cpu0.op_class_0::SimdMisc 0 0.00% 66.43% # Class of committed instruction 608system.cpu0.op_class_0::SimdMult 0 0.00% 66.43% # Class of committed instruction 609system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.43% # Class of committed instruction 610system.cpu0.op_class_0::SimdShift 0 0.00% 66.43% # Class of committed instruction 611system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.43% # Class of committed instruction 612system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.43% # Class of committed instruction 613system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.43% # Class of committed instruction 614system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.43% # Class of committed instruction 615system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.43% # Class of committed instruction 616system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.43% # Class of committed instruction 617system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.43% # Class of committed instruction 618system.cpu0.op_class_0::SimdFloatMisc 8175 0.01% 66.43% # Class of committed instruction 619system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.43% # Class of committed instruction 620system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.43% # Class of committed instruction 621system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.43% # Class of committed instruction 622system.cpu0.op_class_0::MemRead 17407324 17.60% 84.03% # Class of committed instruction 623system.cpu0.op_class_0::MemWrite 15784753 15.96% 99.99% # Class of committed instruction 624system.cpu0.op_class_0::FloatMemRead 2708 0.00% 99.99% # Class of committed instruction 625system.cpu0.op_class_0::FloatMemWrite 8588 0.01% 100.00% # Class of committed instruction 626system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 627system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 628system.cpu0.op_class_0::total 98918766 # Class of committed instruction 629system.cpu0.kern.inst.arm 0 # number of arm instructions executed 630system.cpu0.kern.inst.quiesce 1854 # number of quiesce instructions executed 631system.cpu0.tickCycles 124478065 # Number of cycles that the object actually ticked 632system.cpu0.idleCycles 52949063 # Total number of cycles that the object has spent stopped 633system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 634system.cpu0.dcache.tags.replacements 756000 # number of replacements 635system.cpu0.dcache.tags.tagsinuse 495.989536 # Cycle average of tags in use 636system.cpu0.dcache.tags.total_refs 31503611 # Total number of references to valid blocks. 637system.cpu0.dcache.tags.sampled_refs 756512 # Sample count of references to valid blocks. 638system.cpu0.dcache.tags.avg_refs 41.643240 # Average number of references to valid blocks. 639system.cpu0.dcache.tags.warmup_cycle 356904000 # Cycle when the warmup percentage was hit. 640system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.989536 # Average occupied blocks per requestor 641system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968730 # Average percentage of cache occupancy 642system.cpu0.dcache.tags.occ_percent::total 0.968730 # Average percentage of cache occupancy 643system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 644system.cpu0.dcache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id 645system.cpu0.dcache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id 646system.cpu0.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id 647system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 648system.cpu0.dcache.tags.tag_accesses 66089687 # Number of tag accesses 649system.cpu0.dcache.tags.data_accesses 66089687 # Number of data accesses 650system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 651system.cpu0.dcache.ReadReq_hits::cpu0.data 16428136 # number of ReadReq hits 652system.cpu0.dcache.ReadReq_hits::total 16428136 # number of ReadReq hits 653system.cpu0.dcache.WriteReq_hits::cpu0.data 13890443 # number of WriteReq hits 654system.cpu0.dcache.WriteReq_hits::total 13890443 # number of WriteReq hits 655system.cpu0.dcache.SoftPFReq_hits::cpu0.data 328324 # number of SoftPFReq hits 656system.cpu0.dcache.SoftPFReq_hits::total 328324 # number of SoftPFReq hits 657system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374119 # number of LoadLockedReq hits 658system.cpu0.dcache.LoadLockedReq_hits::total 374119 # number of LoadLockedReq hits 659system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370195 # number of StoreCondReq hits 660system.cpu0.dcache.StoreCondReq_hits::total 370195 # number of StoreCondReq hits 661system.cpu0.dcache.demand_hits::cpu0.data 30318579 # number of demand (read+write) hits 662system.cpu0.dcache.demand_hits::total 30318579 # number of demand (read+write) hits 663system.cpu0.dcache.overall_hits::cpu0.data 30646903 # number of overall hits 664system.cpu0.dcache.overall_hits::total 30646903 # number of overall hits 665system.cpu0.dcache.ReadReq_misses::cpu0.data 460755 # number of ReadReq misses 666system.cpu0.dcache.ReadReq_misses::total 460755 # number of ReadReq misses 667system.cpu0.dcache.WriteReq_misses::cpu0.data 603639 # number of WriteReq misses 668system.cpu0.dcache.WriteReq_misses::total 603639 # number of WriteReq misses 669system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141924 # number of SoftPFReq misses 670system.cpu0.dcache.SoftPFReq_misses::total 141924 # number of SoftPFReq misses 671system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21489 # number of LoadLockedReq misses 672system.cpu0.dcache.LoadLockedReq_misses::total 21489 # number of LoadLockedReq misses 673system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20512 # number of StoreCondReq misses 674system.cpu0.dcache.StoreCondReq_misses::total 20512 # number of StoreCondReq misses 675system.cpu0.dcache.demand_misses::cpu0.data 1064394 # number of demand (read+write) misses 676system.cpu0.dcache.demand_misses::total 1064394 # number of demand (read+write) misses 677system.cpu0.dcache.overall_misses::cpu0.data 1206318 # number of overall misses 678system.cpu0.dcache.overall_misses::total 1206318 # number of overall misses 679system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6676359500 # number of ReadReq miss cycles 680system.cpu0.dcache.ReadReq_miss_latency::total 6676359500 # number of ReadReq miss cycles 681system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11544866500 # number of WriteReq miss cycles 682system.cpu0.dcache.WriteReq_miss_latency::total 11544866500 # number of WriteReq miss cycles 683system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336675500 # number of LoadLockedReq miss cycles 684system.cpu0.dcache.LoadLockedReq_miss_latency::total 336675500 # number of LoadLockedReq miss cycles 685system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 485473000 # number of StoreCondReq miss cycles 686system.cpu0.dcache.StoreCondReq_miss_latency::total 485473000 # number of StoreCondReq miss cycles 687system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 539500 # number of StoreCondFailReq miss cycles 688system.cpu0.dcache.StoreCondFailReq_miss_latency::total 539500 # number of StoreCondFailReq miss cycles 689system.cpu0.dcache.demand_miss_latency::cpu0.data 18221226000 # number of demand (read+write) miss cycles 690system.cpu0.dcache.demand_miss_latency::total 18221226000 # number of demand (read+write) miss cycles 691system.cpu0.dcache.overall_miss_latency::cpu0.data 18221226000 # number of overall miss cycles 692system.cpu0.dcache.overall_miss_latency::total 18221226000 # number of overall miss cycles 693system.cpu0.dcache.ReadReq_accesses::cpu0.data 16888891 # number of ReadReq accesses(hits+misses) 694system.cpu0.dcache.ReadReq_accesses::total 16888891 # number of ReadReq accesses(hits+misses) 695system.cpu0.dcache.WriteReq_accesses::cpu0.data 14494082 # number of WriteReq accesses(hits+misses) 696system.cpu0.dcache.WriteReq_accesses::total 14494082 # number of WriteReq accesses(hits+misses) 697system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 470248 # number of SoftPFReq accesses(hits+misses) 698system.cpu0.dcache.SoftPFReq_accesses::total 470248 # number of SoftPFReq accesses(hits+misses) 699system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 395608 # number of LoadLockedReq accesses(hits+misses) 700system.cpu0.dcache.LoadLockedReq_accesses::total 395608 # number of LoadLockedReq accesses(hits+misses) 701system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 390707 # number of StoreCondReq accesses(hits+misses) 702system.cpu0.dcache.StoreCondReq_accesses::total 390707 # number of StoreCondReq accesses(hits+misses) 703system.cpu0.dcache.demand_accesses::cpu0.data 31382973 # number of demand (read+write) accesses 704system.cpu0.dcache.demand_accesses::total 31382973 # number of demand (read+write) accesses 705system.cpu0.dcache.overall_accesses::cpu0.data 31853221 # number of overall (read+write) accesses 706system.cpu0.dcache.overall_accesses::total 31853221 # number of overall (read+write) accesses 707system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027282 # miss rate for ReadReq accesses 708system.cpu0.dcache.ReadReq_miss_rate::total 0.027282 # miss rate for ReadReq accesses 709system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041647 # miss rate for WriteReq accesses 710system.cpu0.dcache.WriteReq_miss_rate::total 0.041647 # miss rate for WriteReq accesses 711system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301807 # miss rate for SoftPFReq accesses 712system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301807 # miss rate for SoftPFReq accesses 713system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054319 # miss rate for LoadLockedReq accesses 714system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054319 # miss rate for LoadLockedReq accesses 715system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052500 # miss rate for StoreCondReq accesses 716system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052500 # miss rate for StoreCondReq accesses 717system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033916 # miss rate for demand accesses 718system.cpu0.dcache.demand_miss_rate::total 0.033916 # miss rate for demand accesses 719system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037871 # miss rate for overall accesses 720system.cpu0.dcache.overall_miss_rate::total 0.037871 # miss rate for overall accesses 721system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14490.042430 # average ReadReq miss latency 722system.cpu0.dcache.ReadReq_avg_miss_latency::total 14490.042430 # average ReadReq miss latency 723system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19125.448323 # average WriteReq miss latency 724system.cpu0.dcache.WriteReq_avg_miss_latency::total 19125.448323 # average WriteReq miss latency 725system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15667.341430 # average LoadLockedReq miss latency 726system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15667.341430 # average LoadLockedReq miss latency 727system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23667.755460 # average StoreCondReq miss latency 728system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23667.755460 # average StoreCondReq miss latency 729system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 730system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 731system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17118.873274 # average overall miss latency 732system.cpu0.dcache.demand_avg_miss_latency::total 17118.873274 # average overall miss latency 733system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15104.828080 # average overall miss latency 734system.cpu0.dcache.overall_avg_miss_latency::total 15104.828080 # average overall miss latency 735system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 736system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 737system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 738system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 739system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 740system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 741system.cpu0.dcache.writebacks::writebacks 756000 # number of writebacks 742system.cpu0.dcache.writebacks::total 756000 # number of writebacks 743system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 45822 # number of ReadReq MSHR hits 744system.cpu0.dcache.ReadReq_mshr_hits::total 45822 # number of ReadReq MSHR hits 745system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266133 # number of WriteReq MSHR hits 746system.cpu0.dcache.WriteReq_mshr_hits::total 266133 # number of WriteReq MSHR hits 747system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14947 # number of LoadLockedReq MSHR hits 748system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14947 # number of LoadLockedReq MSHR hits 749system.cpu0.dcache.demand_mshr_hits::cpu0.data 311955 # number of demand (read+write) MSHR hits 750system.cpu0.dcache.demand_mshr_hits::total 311955 # number of demand (read+write) MSHR hits 751system.cpu0.dcache.overall_mshr_hits::cpu0.data 311955 # number of overall MSHR hits 752system.cpu0.dcache.overall_mshr_hits::total 311955 # number of overall MSHR hits 753system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 414933 # number of ReadReq MSHR misses 754system.cpu0.dcache.ReadReq_mshr_misses::total 414933 # number of ReadReq MSHR misses 755system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337506 # number of WriteReq MSHR misses 756system.cpu0.dcache.WriteReq_mshr_misses::total 337506 # number of WriteReq MSHR misses 757system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 108299 # number of SoftPFReq MSHR misses 758system.cpu0.dcache.SoftPFReq_mshr_misses::total 108299 # number of SoftPFReq MSHR misses 759system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6542 # number of LoadLockedReq MSHR misses 760system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6542 # number of LoadLockedReq MSHR misses 761system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20512 # number of StoreCondReq MSHR misses 762system.cpu0.dcache.StoreCondReq_mshr_misses::total 20512 # number of StoreCondReq MSHR misses 763system.cpu0.dcache.demand_mshr_misses::cpu0.data 752439 # number of demand (read+write) MSHR misses 764system.cpu0.dcache.demand_mshr_misses::total 752439 # number of demand (read+write) MSHR misses 765system.cpu0.dcache.overall_mshr_misses::cpu0.data 860738 # number of overall MSHR misses 766system.cpu0.dcache.overall_mshr_misses::total 860738 # number of overall MSHR misses 767system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20603 # number of ReadReq MSHR uncacheable 768system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20603 # number of ReadReq MSHR uncacheable 769system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19302 # number of WriteReq MSHR uncacheable 770system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19302 # number of WriteReq MSHR uncacheable 771system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39905 # number of overall MSHR uncacheable misses 772system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39905 # number of overall MSHR uncacheable misses 773system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5470255000 # number of ReadReq MSHR miss cycles 774system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5470255000 # number of ReadReq MSHR miss cycles 775system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6299771000 # number of WriteReq MSHR miss cycles 776system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6299771000 # number of WriteReq MSHR miss cycles 777system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1751643500 # number of SoftPFReq MSHR miss cycles 778system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1751643500 # number of SoftPFReq MSHR miss cycles 779system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104376500 # number of LoadLockedReq MSHR miss cycles 780system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104376500 # number of LoadLockedReq MSHR miss cycles 781system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 464977000 # number of StoreCondReq MSHR miss cycles 782system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 464977000 # number of StoreCondReq MSHR miss cycles 783system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 523500 # number of StoreCondFailReq MSHR miss cycles 784system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 523500 # number of StoreCondFailReq MSHR miss cycles 785system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11770026000 # number of demand (read+write) MSHR miss cycles 786system.cpu0.dcache.demand_mshr_miss_latency::total 11770026000 # number of demand (read+write) MSHR miss cycles 787system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13521669500 # number of overall MSHR miss cycles 788system.cpu0.dcache.overall_mshr_miss_latency::total 13521669500 # number of overall MSHR miss cycles 789system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4611679000 # number of ReadReq MSHR uncacheable cycles 790system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4611679000 # number of ReadReq MSHR uncacheable cycles 791system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4611679000 # number of overall MSHR uncacheable cycles 792system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4611679000 # number of overall MSHR uncacheable cycles 793system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024568 # mshr miss rate for ReadReq accesses 794system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024568 # mshr miss rate for ReadReq accesses 795system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023286 # mshr miss rate for WriteReq accesses 796system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023286 # mshr miss rate for WriteReq accesses 797system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230302 # mshr miss rate for SoftPFReq accesses 798system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.230302 # mshr miss rate for SoftPFReq accesses 799system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016537 # mshr miss rate for LoadLockedReq accesses 800system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016537 # mshr miss rate for LoadLockedReq accesses 801system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052500 # mshr miss rate for StoreCondReq accesses 802system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052500 # mshr miss rate for StoreCondReq accesses 803system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023976 # mshr miss rate for demand accesses 804system.cpu0.dcache.demand_mshr_miss_rate::total 0.023976 # mshr miss rate for demand accesses 805system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027022 # mshr miss rate for overall accesses 806system.cpu0.dcache.overall_mshr_miss_rate::total 0.027022 # mshr miss rate for overall accesses 807system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13183.465764 # average ReadReq mshr miss latency 808system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13183.465764 # average ReadReq mshr miss latency 809system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18665.656314 # average WriteReq mshr miss latency 810system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18665.656314 # average WriteReq mshr miss latency 811system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16174.142882 # average SoftPFReq mshr miss latency 812system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16174.142882 # average SoftPFReq mshr miss latency 813system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15954.830327 # average LoadLockedReq mshr miss latency 814system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15954.830327 # average LoadLockedReq mshr miss latency 815system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22668.535491 # average StoreCondReq mshr miss latency 816system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22668.535491 # average StoreCondReq mshr miss latency 817system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 818system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 819system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15642.498595 # average overall mshr miss latency 820system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15642.498595 # average overall mshr miss latency 821system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15709.390662 # average overall mshr miss latency 822system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15709.390662 # average overall mshr miss latency 823system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223835.315245 # average ReadReq mshr uncacheable latency 824system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223835.315245 # average ReadReq mshr uncacheable latency 825system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115566.445308 # average overall mshr uncacheable latency 826system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115566.445308 # average overall mshr uncacheable latency 827system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 828system.cpu0.icache.tags.replacements 2036864 # number of replacements 829system.cpu0.icache.tags.tagsinuse 511.774783 # Cycle average of tags in use 830system.cpu0.icache.tags.total_refs 37707013 # Total number of references to valid blocks. 831system.cpu0.icache.tags.sampled_refs 2037376 # Sample count of references to valid blocks. 832system.cpu0.icache.tags.avg_refs 18.507636 # Average number of references to valid blocks. 833system.cpu0.icache.tags.warmup_cycle 6575306000 # Cycle when the warmup percentage was hit. 834system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774783 # Average occupied blocks per requestor 835system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999560 # Average percentage of cache occupancy 836system.cpu0.icache.tags.occ_percent::total 0.999560 # Average percentage of cache occupancy 837system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 838system.cpu0.icache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id 839system.cpu0.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id 840system.cpu0.icache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id 841system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 842system.cpu0.icache.tags.tag_accesses 81526207 # Number of tag accesses 843system.cpu0.icache.tags.data_accesses 81526207 # Number of data accesses 844system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 845system.cpu0.icache.ReadReq_hits::cpu0.inst 37707013 # number of ReadReq hits 846system.cpu0.icache.ReadReq_hits::total 37707013 # number of ReadReq hits 847system.cpu0.icache.demand_hits::cpu0.inst 37707013 # number of demand (read+write) hits 848system.cpu0.icache.demand_hits::total 37707013 # number of demand (read+write) hits 849system.cpu0.icache.overall_hits::cpu0.inst 37707013 # number of overall hits 850system.cpu0.icache.overall_hits::total 37707013 # number of overall hits 851system.cpu0.icache.ReadReq_misses::cpu0.inst 2037394 # number of ReadReq misses 852system.cpu0.icache.ReadReq_misses::total 2037394 # number of ReadReq misses 853system.cpu0.icache.demand_misses::cpu0.inst 2037394 # number of demand (read+write) misses 854system.cpu0.icache.demand_misses::total 2037394 # number of demand (read+write) misses 855system.cpu0.icache.overall_misses::cpu0.inst 2037394 # number of overall misses 856system.cpu0.icache.overall_misses::total 2037394 # number of overall misses 857system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20429568000 # number of ReadReq miss cycles 858system.cpu0.icache.ReadReq_miss_latency::total 20429568000 # number of ReadReq miss cycles 859system.cpu0.icache.demand_miss_latency::cpu0.inst 20429568000 # number of demand (read+write) miss cycles 860system.cpu0.icache.demand_miss_latency::total 20429568000 # number of demand (read+write) miss cycles 861system.cpu0.icache.overall_miss_latency::cpu0.inst 20429568000 # number of overall miss cycles 862system.cpu0.icache.overall_miss_latency::total 20429568000 # number of overall miss cycles 863system.cpu0.icache.ReadReq_accesses::cpu0.inst 39744407 # number of ReadReq accesses(hits+misses) 864system.cpu0.icache.ReadReq_accesses::total 39744407 # number of ReadReq accesses(hits+misses) 865system.cpu0.icache.demand_accesses::cpu0.inst 39744407 # number of demand (read+write) accesses 866system.cpu0.icache.demand_accesses::total 39744407 # number of demand (read+write) accesses 867system.cpu0.icache.overall_accesses::cpu0.inst 39744407 # number of overall (read+write) accesses 868system.cpu0.icache.overall_accesses::total 39744407 # number of overall (read+write) accesses 869system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051262 # miss rate for ReadReq accesses 870system.cpu0.icache.ReadReq_miss_rate::total 0.051262 # miss rate for ReadReq accesses 871system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051262 # miss rate for demand accesses 872system.cpu0.icache.demand_miss_rate::total 0.051262 # miss rate for demand accesses 873system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051262 # miss rate for overall accesses 874system.cpu0.icache.overall_miss_rate::total 0.051262 # miss rate for overall accesses 875system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10027.303506 # average ReadReq miss latency 876system.cpu0.icache.ReadReq_avg_miss_latency::total 10027.303506 # average ReadReq miss latency 877system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10027.303506 # average overall miss latency 878system.cpu0.icache.demand_avg_miss_latency::total 10027.303506 # average overall miss latency 879system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10027.303506 # average overall miss latency 880system.cpu0.icache.overall_avg_miss_latency::total 10027.303506 # average overall miss latency 881system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 882system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 883system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 884system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 885system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 886system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 887system.cpu0.icache.writebacks::writebacks 2036864 # number of writebacks 888system.cpu0.icache.writebacks::total 2036864 # number of writebacks 889system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2037394 # number of ReadReq MSHR misses 890system.cpu0.icache.ReadReq_mshr_misses::total 2037394 # number of ReadReq MSHR misses 891system.cpu0.icache.demand_mshr_misses::cpu0.inst 2037394 # number of demand (read+write) MSHR misses 892system.cpu0.icache.demand_mshr_misses::total 2037394 # number of demand (read+write) MSHR misses 893system.cpu0.icache.overall_mshr_misses::cpu0.inst 2037394 # number of overall MSHR misses 894system.cpu0.icache.overall_mshr_misses::total 2037394 # number of overall MSHR misses 895system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable 896system.cpu0.icache.ReadReq_mshr_uncacheable::total 3277 # number of ReadReq MSHR uncacheable 897system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses 898system.cpu0.icache.overall_mshr_uncacheable_misses::total 3277 # number of overall MSHR uncacheable misses 899system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19410871500 # number of ReadReq MSHR miss cycles 900system.cpu0.icache.ReadReq_mshr_miss_latency::total 19410871500 # number of ReadReq MSHR miss cycles 901system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19410871500 # number of demand (read+write) MSHR miss cycles 902system.cpu0.icache.demand_mshr_miss_latency::total 19410871500 # number of demand (read+write) MSHR miss cycles 903system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19410871500 # number of overall MSHR miss cycles 904system.cpu0.icache.overall_mshr_miss_latency::total 19410871500 # number of overall MSHR miss cycles 905system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 323882000 # number of ReadReq MSHR uncacheable cycles 906system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 323882000 # number of ReadReq MSHR uncacheable cycles 907system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 323882000 # number of overall MSHR uncacheable cycles 908system.cpu0.icache.overall_mshr_uncacheable_latency::total 323882000 # number of overall MSHR uncacheable cycles 909system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.051262 # mshr miss rate for ReadReq accesses 910system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.051262 # mshr miss rate for ReadReq accesses 911system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.051262 # mshr miss rate for demand accesses 912system.cpu0.icache.demand_mshr_miss_rate::total 0.051262 # mshr miss rate for demand accesses 913system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.051262 # mshr miss rate for overall accesses 914system.cpu0.icache.overall_mshr_miss_rate::total 0.051262 # mshr miss rate for overall accesses 915system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9527.303752 # average ReadReq mshr miss latency 916system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9527.303752 # average ReadReq mshr miss latency 917system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9527.303752 # average overall mshr miss latency 918system.cpu0.icache.demand_avg_mshr_miss_latency::total 9527.303752 # average overall mshr miss latency 919system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9527.303752 # average overall mshr miss latency 920system.cpu0.icache.overall_avg_mshr_miss_latency::total 9527.303752 # average overall mshr miss latency 921system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979 # average ReadReq mshr uncacheable latency 922system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98834.909979 # average ReadReq mshr uncacheable latency 923system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979 # average overall mshr uncacheable latency 924system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98834.909979 # average overall mshr uncacheable latency 925system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 926system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927829 # number of hwpf issued 927system.cpu0.l2cache.prefetcher.pfIdentified 1927948 # number of prefetch candidates identified 928system.cpu0.l2cache.prefetcher.pfBufferHit 103 # number of redundant prefetches already in prefetch queue 929system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 930system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 931system.cpu0.l2cache.prefetcher.pfSpanPage 243748 # number of prefetches not generated due to page crossing 932system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 933system.cpu0.l2cache.tags.replacements 297127 # number of replacements 934system.cpu0.l2cache.tags.tagsinuse 15638.814401 # Cycle average of tags in use 935system.cpu0.l2cache.tags.total_refs 2702273 # Total number of references to valid blocks. 936system.cpu0.l2cache.tags.sampled_refs 312734 # Sample count of references to valid blocks. 937system.cpu0.l2cache.tags.avg_refs 8.640803 # Average number of references to valid blocks. 938system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 939system.cpu0.l2cache.tags.occ_blocks::writebacks 14568.839087 # Average occupied blocks per requestor 940system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.655947 # Average occupied blocks per requestor 941system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.055478 # Average occupied blocks per requestor 942system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1008.263889 # Average occupied blocks per requestor 943system.cpu0.l2cache.tags.occ_percent::writebacks 0.889211 # Average percentage of cache occupancy 944system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003763 # Average percentage of cache occupancy 945system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000003 # Average percentage of cache occupancy 946system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.061540 # Average percentage of cache occupancy 947system.cpu0.l2cache.tags.occ_percent::total 0.954517 # Average percentage of cache occupancy 948system.cpu0.l2cache.tags.occ_task_id_blocks::1022 252 # Occupied blocks per task id 949system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id 950system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15345 # Occupied blocks per task id 951system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id 952system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 32 # Occupied blocks per task id 953system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 142 # Occupied blocks per task id 954system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 72 # Occupied blocks per task id 955system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 956system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id 957system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 958system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 959system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 251 # Occupied blocks per task id 960system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1191 # Occupied blocks per task id 961system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7256 # Occupied blocks per task id 962system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5870 # Occupied blocks per task id 963system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 777 # Occupied blocks per task id 964system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.015381 # Percentage of cache occupancy per task id 965system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id 966system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.936584 # Percentage of cache occupancy per task id 967system.cpu0.l2cache.tags.tag_accesses 95152070 # Number of tag accesses 968system.cpu0.l2cache.tags.data_accesses 95152070 # Number of data accesses 969system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 970system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 82993 # number of ReadReq hits 971system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5634 # number of ReadReq hits 972system.cpu0.l2cache.ReadReq_hits::total 88627 # number of ReadReq hits 973system.cpu0.l2cache.WritebackDirty_hits::writebacks 506169 # number of WritebackDirty hits 974system.cpu0.l2cache.WritebackDirty_hits::total 506169 # number of WritebackDirty hits 975system.cpu0.l2cache.WritebackClean_hits::writebacks 2242578 # number of WritebackClean hits 976system.cpu0.l2cache.WritebackClean_hits::total 2242578 # number of WritebackClean hits 977system.cpu0.l2cache.ReadExReq_hits::cpu0.data 235126 # number of ReadExReq hits 978system.cpu0.l2cache.ReadExReq_hits::total 235126 # number of ReadExReq hits 979system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1941946 # number of ReadCleanReq hits 980system.cpu0.l2cache.ReadCleanReq_hits::total 1941946 # number of ReadCleanReq hits 981system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 414577 # number of ReadSharedReq hits 982system.cpu0.l2cache.ReadSharedReq_hits::total 414577 # number of ReadSharedReq hits 983system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 82993 # number of demand (read+write) hits 984system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5634 # number of demand (read+write) hits 985system.cpu0.l2cache.demand_hits::cpu0.inst 1941946 # number of demand (read+write) hits 986system.cpu0.l2cache.demand_hits::cpu0.data 649703 # number of demand (read+write) hits 987system.cpu0.l2cache.demand_hits::total 2680276 # number of demand (read+write) hits 988system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 82993 # number of overall hits 989system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5634 # number of overall hits 990system.cpu0.l2cache.overall_hits::cpu0.inst 1941946 # number of overall hits 991system.cpu0.l2cache.overall_hits::cpu0.data 649703 # number of overall hits 992system.cpu0.l2cache.overall_hits::total 2680276 # number of overall hits 993system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 792 # number of ReadReq misses 994system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 89 # number of ReadReq misses 995system.cpu0.l2cache.ReadReq_misses::total 881 # number of ReadReq misses 996system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 56686 # number of UpgradeReq misses 997system.cpu0.l2cache.UpgradeReq_misses::total 56686 # number of UpgradeReq misses 998system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20512 # number of SCUpgradeReq misses 999system.cpu0.l2cache.SCUpgradeReq_misses::total 20512 # number of SCUpgradeReq misses 1000system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45703 # number of ReadExReq misses 1001system.cpu0.l2cache.ReadExReq_misses::total 45703 # number of ReadExReq misses 1002system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 95448 # number of ReadCleanReq misses 1003system.cpu0.l2cache.ReadCleanReq_misses::total 95448 # number of ReadCleanReq misses 1004system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 115192 # number of ReadSharedReq misses 1005system.cpu0.l2cache.ReadSharedReq_misses::total 115192 # number of ReadSharedReq misses 1006system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 792 # number of demand (read+write) misses 1007system.cpu0.l2cache.demand_misses::cpu0.itb.walker 89 # number of demand (read+write) misses 1008system.cpu0.l2cache.demand_misses::cpu0.inst 95448 # number of demand (read+write) misses 1009system.cpu0.l2cache.demand_misses::cpu0.data 160895 # number of demand (read+write) misses 1010system.cpu0.l2cache.demand_misses::total 257224 # number of demand (read+write) misses 1011system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 792 # number of overall misses 1012system.cpu0.l2cache.overall_misses::cpu0.itb.walker 89 # number of overall misses 1013system.cpu0.l2cache.overall_misses::cpu0.inst 95448 # number of overall misses 1014system.cpu0.l2cache.overall_misses::cpu0.data 160895 # number of overall misses 1015system.cpu0.l2cache.overall_misses::total 257224 # number of overall misses 1016system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 39518000 # number of ReadReq miss cycles 1017system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2258000 # number of ReadReq miss cycles 1018system.cpu0.l2cache.ReadReq_miss_latency::total 41776000 # number of ReadReq miss cycles 1019system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 46480500 # number of UpgradeReq miss cycles 1020system.cpu0.l2cache.UpgradeReq_miss_latency::total 46480500 # number of UpgradeReq miss cycles 1021system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 11233000 # number of SCUpgradeReq miss cycles 1022system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 11233000 # number of SCUpgradeReq miss cycles 1023system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 499500 # number of SCUpgradeFailReq miss cycles 1024system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 499500 # number of SCUpgradeFailReq miss cycles 1025system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2934504499 # number of ReadExReq miss cycles 1026system.cpu0.l2cache.ReadExReq_miss_latency::total 2934504499 # number of ReadExReq miss cycles 1027system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 4610090000 # number of ReadCleanReq miss cycles 1028system.cpu0.l2cache.ReadCleanReq_miss_latency::total 4610090000 # number of ReadCleanReq miss cycles 1029system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3801275499 # number of ReadSharedReq miss cycles 1030system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3801275499 # number of ReadSharedReq miss cycles 1031system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 39518000 # number of demand (read+write) miss cycles 1032system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2258000 # number of demand (read+write) miss cycles 1033system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4610090000 # number of demand (read+write) miss cycles 1034system.cpu0.l2cache.demand_miss_latency::cpu0.data 6735779998 # number of demand (read+write) miss cycles 1035system.cpu0.l2cache.demand_miss_latency::total 11387645998 # number of demand (read+write) miss cycles 1036system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 39518000 # number of overall miss cycles 1037system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2258000 # number of overall miss cycles 1038system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4610090000 # number of overall miss cycles 1039system.cpu0.l2cache.overall_miss_latency::cpu0.data 6735779998 # number of overall miss cycles 1040system.cpu0.l2cache.overall_miss_latency::total 11387645998 # number of overall miss cycles 1041system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 83785 # number of ReadReq accesses(hits+misses) 1042system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5723 # number of ReadReq accesses(hits+misses) 1043system.cpu0.l2cache.ReadReq_accesses::total 89508 # number of ReadReq accesses(hits+misses) 1044system.cpu0.l2cache.WritebackDirty_accesses::writebacks 506169 # number of WritebackDirty accesses(hits+misses) 1045system.cpu0.l2cache.WritebackDirty_accesses::total 506169 # number of WritebackDirty accesses(hits+misses) 1046system.cpu0.l2cache.WritebackClean_accesses::writebacks 2242578 # number of WritebackClean accesses(hits+misses) 1047system.cpu0.l2cache.WritebackClean_accesses::total 2242578 # number of WritebackClean accesses(hits+misses) 1048system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56686 # number of UpgradeReq accesses(hits+misses) 1049system.cpu0.l2cache.UpgradeReq_accesses::total 56686 # number of UpgradeReq accesses(hits+misses) 1050system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20512 # number of SCUpgradeReq accesses(hits+misses) 1051system.cpu0.l2cache.SCUpgradeReq_accesses::total 20512 # number of SCUpgradeReq accesses(hits+misses) 1052system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 280829 # number of ReadExReq accesses(hits+misses) 1053system.cpu0.l2cache.ReadExReq_accesses::total 280829 # number of ReadExReq accesses(hits+misses) 1054system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 2037394 # number of ReadCleanReq accesses(hits+misses) 1055system.cpu0.l2cache.ReadCleanReq_accesses::total 2037394 # number of ReadCleanReq accesses(hits+misses) 1056system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 529769 # number of ReadSharedReq accesses(hits+misses) 1057system.cpu0.l2cache.ReadSharedReq_accesses::total 529769 # number of ReadSharedReq accesses(hits+misses) 1058system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 83785 # number of demand (read+write) accesses 1059system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5723 # number of demand (read+write) accesses 1060system.cpu0.l2cache.demand_accesses::cpu0.inst 2037394 # number of demand (read+write) accesses 1061system.cpu0.l2cache.demand_accesses::cpu0.data 810598 # number of demand (read+write) accesses 1062system.cpu0.l2cache.demand_accesses::total 2937500 # number of demand (read+write) accesses 1063system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 83785 # number of overall (read+write) accesses 1064system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5723 # number of overall (read+write) accesses 1065system.cpu0.l2cache.overall_accesses::cpu0.inst 2037394 # number of overall (read+write) accesses 1066system.cpu0.l2cache.overall_accesses::cpu0.data 810598 # number of overall (read+write) accesses 1067system.cpu0.l2cache.overall_accesses::total 2937500 # number of overall (read+write) accesses 1068system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009453 # miss rate for ReadReq accesses 1069system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.015551 # miss rate for ReadReq accesses 1070system.cpu0.l2cache.ReadReq_miss_rate::total 0.009843 # miss rate for ReadReq accesses 1071system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 1072system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1073system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1074system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1075system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.162743 # miss rate for ReadExReq accesses 1076system.cpu0.l2cache.ReadExReq_miss_rate::total 0.162743 # miss rate for ReadExReq accesses 1077system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.046848 # miss rate for ReadCleanReq accesses 1078system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.046848 # miss rate for ReadCleanReq accesses 1079system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.217438 # miss rate for ReadSharedReq accesses 1080system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.217438 # miss rate for ReadSharedReq accesses 1081system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009453 # miss rate for demand accesses 1082system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.015551 # miss rate for demand accesses 1083system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.046848 # miss rate for demand accesses 1084system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.198489 # miss rate for demand accesses 1085system.cpu0.l2cache.demand_miss_rate::total 0.087566 # miss rate for demand accesses 1086system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009453 # miss rate for overall accesses 1087system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.015551 # miss rate for overall accesses 1088system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.046848 # miss rate for overall accesses 1089system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.198489 # miss rate for overall accesses 1090system.cpu0.l2cache.overall_miss_rate::total 0.087566 # miss rate for overall accesses 1091system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 49896.464646 # average ReadReq miss latency 1092system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 25370.786517 # average ReadReq miss latency 1093system.cpu0.l2cache.ReadReq_avg_miss_latency::total 47418.842225 # average ReadReq miss latency 1094system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 819.964365 # average UpgradeReq miss latency 1095system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 819.964365 # average UpgradeReq miss latency 1096system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 547.630655 # average SCUpgradeReq miss latency 1097system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 547.630655 # average SCUpgradeReq miss latency 1098system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency 1099system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 1100system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 64208.137300 # average ReadExReq miss latency 1101system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 64208.137300 # average ReadExReq miss latency 1102system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 48299.492918 # average ReadCleanReq miss latency 1103system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 48299.492918 # average ReadCleanReq miss latency 1104system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32999.474781 # average ReadSharedReq miss latency 1105system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32999.474781 # average ReadSharedReq miss latency 1106system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 49896.464646 # average overall miss latency 1107system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 25370.786517 # average overall miss latency 1108system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 48299.492918 # average overall miss latency 1109system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41864.445744 # average overall miss latency 1110system.cpu0.l2cache.demand_avg_miss_latency::total 44271.319931 # average overall miss latency 1111system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 49896.464646 # average overall miss latency 1112system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 25370.786517 # average overall miss latency 1113system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 48299.492918 # average overall miss latency 1114system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41864.445744 # average overall miss latency 1115system.cpu0.l2cache.overall_avg_miss_latency::total 44271.319931 # average overall miss latency 1116system.cpu0.l2cache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked 1117system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1118system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 1119system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1120system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked 1121system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1122system.cpu0.l2cache.unused_prefetches 10950 # number of HardPF blocks evicted w/o reference 1123system.cpu0.l2cache.writebacks::writebacks 237127 # number of writebacks 1124system.cpu0.l2cache.writebacks::total 237127 # number of writebacks 1125system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 1126system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1127system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3260 # number of ReadExReq MSHR hits 1128system.cpu0.l2cache.ReadExReq_mshr_hits::total 3260 # number of ReadExReq MSHR hits 1129system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 60 # number of ReadCleanReq MSHR hits 1130system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 60 # number of ReadCleanReq MSHR hits 1131system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 437 # number of ReadSharedReq MSHR hits 1132system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 437 # number of ReadSharedReq MSHR hits 1133system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 1134system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 60 # number of demand (read+write) MSHR hits 1135system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3697 # number of demand (read+write) MSHR hits 1136system.cpu0.l2cache.demand_mshr_hits::total 3758 # number of demand (read+write) MSHR hits 1137system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 1138system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 60 # number of overall MSHR hits 1139system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3697 # number of overall MSHR hits 1140system.cpu0.l2cache.overall_mshr_hits::total 3758 # number of overall MSHR hits 1141system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 791 # number of ReadReq MSHR misses 1142system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 89 # number of ReadReq MSHR misses 1143system.cpu0.l2cache.ReadReq_mshr_misses::total 880 # number of ReadReq MSHR misses 1144system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 267610 # number of HardPFReq MSHR misses 1145system.cpu0.l2cache.HardPFReq_mshr_misses::total 267610 # number of HardPFReq MSHR misses 1146system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 56686 # number of UpgradeReq MSHR misses 1147system.cpu0.l2cache.UpgradeReq_mshr_misses::total 56686 # number of UpgradeReq MSHR misses 1148system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20512 # number of SCUpgradeReq MSHR misses 1149system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20512 # number of SCUpgradeReq MSHR misses 1150system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42443 # number of ReadExReq MSHR misses 1151system.cpu0.l2cache.ReadExReq_mshr_misses::total 42443 # number of ReadExReq MSHR misses 1152system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 95388 # number of ReadCleanReq MSHR misses 1153system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 95388 # number of ReadCleanReq MSHR misses 1154system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 114755 # number of ReadSharedReq MSHR misses 1155system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 114755 # number of ReadSharedReq MSHR misses 1156system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 791 # number of demand (read+write) MSHR misses 1157system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 89 # number of demand (read+write) MSHR misses 1158system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 95388 # number of demand (read+write) MSHR misses 1159system.cpu0.l2cache.demand_mshr_misses::cpu0.data 157198 # number of demand (read+write) MSHR misses 1160system.cpu0.l2cache.demand_mshr_misses::total 253466 # number of demand (read+write) MSHR misses 1161system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 791 # number of overall MSHR misses 1162system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 89 # number of overall MSHR misses 1163system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 95388 # number of overall MSHR misses 1164system.cpu0.l2cache.overall_mshr_misses::cpu0.data 157198 # number of overall MSHR misses 1165system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 267610 # number of overall MSHR misses 1166system.cpu0.l2cache.overall_mshr_misses::total 521076 # number of overall MSHR misses 1167system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable 1168system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20603 # number of ReadReq MSHR uncacheable 1169system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23880 # number of ReadReq MSHR uncacheable 1170system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19302 # number of WriteReq MSHR uncacheable 1171system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19302 # number of WriteReq MSHR uncacheable 1172system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses 1173system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39905 # number of overall MSHR uncacheable misses 1174system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 43182 # number of overall MSHR uncacheable misses 1175system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 34749000 # number of ReadReq MSHR miss cycles 1176system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1724000 # number of ReadReq MSHR miss cycles 1177system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 36473000 # number of ReadReq MSHR miss cycles 1178system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17027732697 # number of HardPFReq MSHR miss cycles 1179system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17027732697 # number of HardPFReq MSHR miss cycles 1180system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 983576499 # number of UpgradeReq MSHR miss cycles 1181system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 983576499 # number of UpgradeReq MSHR miss cycles 1182system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 310242000 # number of SCUpgradeReq MSHR miss cycles 1183system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 310242000 # number of SCUpgradeReq MSHR miss cycles 1184system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 403500 # number of SCUpgradeFailReq MSHR miss cycles 1185system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 403500 # number of SCUpgradeFailReq MSHR miss cycles 1186system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2182275999 # number of ReadExReq MSHR miss cycles 1187system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2182275999 # number of ReadExReq MSHR miss cycles 1188system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 4035832000 # number of ReadCleanReq MSHR miss cycles 1189system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 4035832000 # number of ReadCleanReq MSHR miss cycles 1190system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 3088712499 # number of ReadSharedReq MSHR miss cycles 1191system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 3088712499 # number of ReadSharedReq MSHR miss cycles 1192system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 34749000 # number of demand (read+write) MSHR miss cycles 1193system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1724000 # number of demand (read+write) MSHR miss cycles 1194system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 4035832000 # number of demand (read+write) MSHR miss cycles 1195system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5270988498 # number of demand (read+write) MSHR miss cycles 1196system.cpu0.l2cache.demand_mshr_miss_latency::total 9343293498 # number of demand (read+write) MSHR miss cycles 1197system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 34749000 # number of overall MSHR miss cycles 1198system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1724000 # number of overall MSHR miss cycles 1199system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 4035832000 # number of overall MSHR miss cycles 1200system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5270988498 # number of overall MSHR miss cycles 1201system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17027732697 # number of overall MSHR miss cycles 1202system.cpu0.l2cache.overall_mshr_miss_latency::total 26371026195 # number of overall MSHR miss cycles 1203system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 297666000 # number of ReadReq MSHR uncacheable cycles 1204system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4446739000 # number of ReadReq MSHR uncacheable cycles 1205system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4744405000 # number of ReadReq MSHR uncacheable cycles 1206system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 297666000 # number of overall MSHR uncacheable cycles 1207system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4446739000 # number of overall MSHR uncacheable cycles 1208system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4744405000 # number of overall MSHR uncacheable cycles 1209system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009441 # mshr miss rate for ReadReq accesses 1210system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015551 # mshr miss rate for ReadReq accesses 1211system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009832 # mshr miss rate for ReadReq accesses 1212system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1213system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1214system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1215system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1216system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1217system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1218system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.151135 # mshr miss rate for ReadExReq accesses 1219system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.151135 # mshr miss rate for ReadExReq accesses 1220system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.046819 # mshr miss rate for ReadCleanReq accesses 1221system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.046819 # mshr miss rate for ReadCleanReq accesses 1222system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.216613 # mshr miss rate for ReadSharedReq accesses 1223system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.216613 # mshr miss rate for ReadSharedReq accesses 1224system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009441 # mshr miss rate for demand accesses 1225system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015551 # mshr miss rate for demand accesses 1226system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.046819 # mshr miss rate for demand accesses 1227system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.193928 # mshr miss rate for demand accesses 1228system.cpu0.l2cache.demand_mshr_miss_rate::total 0.086286 # mshr miss rate for demand accesses 1229system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009441 # mshr miss rate for overall accesses 1230system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015551 # mshr miss rate for overall accesses 1231system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.046819 # mshr miss rate for overall accesses 1232system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.193928 # mshr miss rate for overall accesses 1233system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1234system.cpu0.l2cache.overall_mshr_miss_rate::total 0.177388 # mshr miss rate for overall accesses 1235system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 43930.467762 # average ReadReq mshr miss latency 1236system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19370.786517 # average ReadReq mshr miss latency 1237system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 41446.590909 # average ReadReq mshr miss latency 1238system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63628.910343 # average HardPFReq mshr miss latency 1239system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63628.910343 # average HardPFReq mshr miss latency 1240system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17351.312476 # average UpgradeReq mshr miss latency 1241system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17351.312476 # average UpgradeReq mshr miss latency 1242system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15124.902496 # average SCUpgradeReq mshr miss latency 1243system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15124.902496 # average SCUpgradeReq mshr miss latency 1244system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency 1245system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 1246system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 51416.629338 # average ReadExReq mshr miss latency 1247system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 51416.629338 # average ReadExReq mshr miss latency 1248system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42309.640626 # average ReadCleanReq mshr miss latency 1249system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42309.640626 # average ReadCleanReq mshr miss latency 1250system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26915.711725 # average ReadSharedReq mshr miss latency 1251system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26915.711725 # average ReadSharedReq mshr miss latency 1252system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 43930.467762 # average overall mshr miss latency 1253system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19370.786517 # average overall mshr miss latency 1254system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42309.640626 # average overall mshr miss latency 1255system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33530.887785 # average overall mshr miss latency 1256system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36862.117594 # average overall mshr miss latency 1257system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 43930.467762 # average overall mshr miss latency 1258system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19370.786517 # average overall mshr miss latency 1259system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42309.640626 # average overall mshr miss latency 1260system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33530.887785 # average overall mshr miss latency 1261system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63628.910343 # average overall mshr miss latency 1262system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50608.790647 # average overall mshr miss latency 1263system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average ReadReq mshr uncacheable latency 1264system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215829.684997 # average ReadReq mshr uncacheable latency 1265system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198676.926298 # average ReadReq mshr uncacheable latency 1266system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average overall mshr uncacheable latency 1267system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111433.128681 # average overall mshr uncacheable latency 1268system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109869.968969 # average overall mshr uncacheable latency 1269system.cpu0.toL2Bus.snoop_filter.tot_requests 5741859 # Total number of requests made to the snoop filter. 1270system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2893899 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1271system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44137 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1272system.cpu0.toL2Bus.snoop_filter.tot_snoops 221175 # Total number of snoops made to the snoop filter. 1273system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 217002 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1274system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4173 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1275system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 1276system.cpu0.toL2Bus.trans_dist::ReadReq 125397 # Transaction distribution 1277system.cpu0.toL2Bus.trans_dist::ReadResp 2741625 # Transaction distribution 1278system.cpu0.toL2Bus.trans_dist::WriteReq 19302 # Transaction distribution 1279system.cpu0.toL2Bus.trans_dist::WriteResp 19302 # Transaction distribution 1280system.cpu0.toL2Bus.trans_dist::WritebackDirty 743607 # Transaction distribution 1281system.cpu0.toL2Bus.trans_dist::WritebackClean 2286693 # Transaction distribution 1282system.cpu0.toL2Bus.trans_dist::CleanEvict 110010 # Transaction distribution 1283system.cpu0.toL2Bus.trans_dist::HardPFReq 316910 # Transaction distribution 1284system.cpu0.toL2Bus.trans_dist::UpgradeReq 86864 # Transaction distribution 1285system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42906 # Transaction distribution 1286system.cpu0.toL2Bus.trans_dist::UpgradeResp 113874 # Transaction distribution 1287system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution 1288system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 31 # Transaction distribution 1289system.cpu0.toL2Bus.trans_dist::ReadExReq 299874 # Transaction distribution 1290system.cpu0.toL2Bus.trans_dist::ReadExResp 296474 # Transaction distribution 1291system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2037394 # Transaction distribution 1292system.cpu0.toL2Bus.trans_dist::ReadSharedReq 616815 # Transaction distribution 1293system.cpu0.toL2Bus.trans_dist::InvalidateReq 3112 # Transaction distribution 1294system.cpu0.toL2Bus.trans_dist::InvalidateResp 13 # Transaction distribution 1295system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6118205 # Packet count per connected master and slave (bytes) 1296system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2712873 # Packet count per connected master and slave (bytes) 1297system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14034 # Packet count per connected master and slave (bytes) 1298system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 176949 # Packet count per connected master and slave (bytes) 1299system.cpu0.toL2Bus.pkt_count::total 9022061 # Packet count per connected master and slave (bytes) 1300system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 260962176 # Cumulative packet size per connected master and slave (bytes) 1301system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104517534 # Cumulative packet size per connected master and slave (bytes) 1302system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22892 # Cumulative packet size per connected master and slave (bytes) 1303system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 335140 # Cumulative packet size per connected master and slave (bytes) 1304system.cpu0.toL2Bus.pkt_size::total 365837742 # Cumulative packet size per connected master and slave (bytes) 1305system.cpu0.toL2Bus.snoops 939630 # Total snoops (count) 1306system.cpu0.toL2Bus.snoopTraffic 19388808 # Total snoop traffic (bytes) 1307system.cpu0.toL2Bus.snoop_fanout::samples 3896038 # Request fanout histogram 1308system.cpu0.toL2Bus.snoop_fanout::mean 0.075284 # Request fanout histogram 1309system.cpu0.toL2Bus.snoop_fanout::stdev 0.267877 # Request fanout histogram 1310system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1311system.cpu0.toL2Bus.snoop_fanout::0 3606903 92.58% 92.58% # Request fanout histogram 1312system.cpu0.toL2Bus.snoop_fanout::1 284962 7.31% 99.89% # Request fanout histogram 1313system.cpu0.toL2Bus.snoop_fanout::2 4173 0.11% 100.00% # Request fanout histogram 1314system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1315system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1316system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1317system.cpu0.toL2Bus.snoop_fanout::total 3896038 # Request fanout histogram 1318system.cpu0.toL2Bus.reqLayer0.occupancy 5733869996 # Layer occupancy (ticks) 1319system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1320system.cpu0.toL2Bus.snoopLayer0.occupancy 115563972 # Layer occupancy (ticks) 1321system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1322system.cpu0.toL2Bus.respLayer0.occupancy 3061282943 # Layer occupancy (ticks) 1323system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1324system.cpu0.toL2Bus.respLayer1.occupancy 1285797933 # Layer occupancy (ticks) 1325system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1326system.cpu0.toL2Bus.respLayer2.occupancy 8314992 # Layer occupancy (ticks) 1327system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1328system.cpu0.toL2Bus.respLayer3.occupancy 93182962 # Layer occupancy (ticks) 1329system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1330system.cpu1.branchPred.lookups 18647514 # Number of BP lookups 1331system.cpu1.branchPred.condPredicted 5782822 # Number of conditional branches predicted 1332system.cpu1.branchPred.condIncorrect 870887 # Number of conditional branches incorrect 1333system.cpu1.branchPred.BTBLookups 9511803 # Number of BTB lookups 1334system.cpu1.branchPred.BTBHits 3428026 # Number of BTB hits 1335system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1336system.cpu1.branchPred.BTBHitPct 36.039708 # BTB Hit Percentage 1337system.cpu1.branchPred.usedRAS 8548256 # Number of times the RAS was used to get a target. 1338system.cpu1.branchPred.RASInCorrect 712976 # Number of incorrect RAS predictions. 1339system.cpu1.branchPred.indirectLookups 3551521 # Number of indirect predictor lookups. 1340system.cpu1.branchPred.indirectHits 3498978 # Number of indirect target hits. 1341system.cpu1.branchPred.indirectMisses 52543 # Number of indirect misses. 1342system.cpu1.branchPredindirectMispredicted 17984 # Number of mispredicted indirect branches. 1343system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 1344system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1345system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1346system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1347system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1348system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1349system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1350system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1351system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1352system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1353system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1354system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1355system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1356system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1357system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1358system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1359system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1360system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1361system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1362system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1363system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1364system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1365system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1366system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1367system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1368system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1369system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1370system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1371system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1372system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1373system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 1374system.cpu1.dtb.walker.walks 22971 # Table walker walks requested 1375system.cpu1.dtb.walker.walksShort 22971 # Table walker walks initiated with short descriptors 1376system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19558 # Level at which table walker walks with short descriptors terminate 1377system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3413 # Level at which table walker walks with short descriptors terminate 1378system.cpu1.dtb.walker.walkWaitTime::samples 22971 # Table walker wait (enqueue to first request) latency 1379system.cpu1.dtb.walker.walkWaitTime::0 22971 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1380system.cpu1.dtb.walker.walkWaitTime::total 22971 # Table walker wait (enqueue to first request) latency 1381system.cpu1.dtb.walker.walkCompletionTime::samples 1848 # Table walker service (enqueue to completion) latency 1382system.cpu1.dtb.walker.walkCompletionTime::mean 12803.300866 # Table walker service (enqueue to completion) latency 1383system.cpu1.dtb.walker.walkCompletionTime::gmean 11525.814953 # Table walker service (enqueue to completion) latency 1384system.cpu1.dtb.walker.walkCompletionTime::stdev 15800.491207 # Table walker service (enqueue to completion) latency 1385system.cpu1.dtb.walker.walkCompletionTime::0-65535 1844 99.78% 99.78% # Table walker service (enqueue to completion) latency 1386system.cpu1.dtb.walker.walkCompletionTime::65536-131071 3 0.16% 99.95% # Table walker service (enqueue to completion) latency 1387system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.05% 100.00% # Table walker service (enqueue to completion) latency 1388system.cpu1.dtb.walker.walkCompletionTime::total 1848 # Table walker service (enqueue to completion) latency 1389system.cpu1.dtb.walker.walksPending::samples -1978443032 # Table walker pending requests distribution 1390system.cpu1.dtb.walker.walksPending::0 -1978443032 100.00% 100.00% # Table walker pending requests distribution 1391system.cpu1.dtb.walker.walksPending::total -1978443032 # Table walker pending requests distribution 1392system.cpu1.dtb.walker.walkPageSizes::4K 1308 70.78% 70.78% # Table walker page sizes translated 1393system.cpu1.dtb.walker.walkPageSizes::1M 540 29.22% 100.00% # Table walker page sizes translated 1394system.cpu1.dtb.walker.walkPageSizes::total 1848 # Table walker page sizes translated 1395system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 22971 # Table walker requests started/completed, data/inst 1396system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1397system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 22971 # Table walker requests started/completed, data/inst 1398system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1848 # Table walker requests started/completed, data/inst 1399system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1400system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1848 # Table walker requests started/completed, data/inst 1401system.cpu1.dtb.walker.walkRequestOrigin::total 24819 # Table walker requests started/completed, data/inst 1402system.cpu1.dtb.inst_hits 0 # ITB inst hits 1403system.cpu1.dtb.inst_misses 0 # ITB inst misses 1404system.cpu1.dtb.read_hits 10530339 # DTB read hits 1405system.cpu1.dtb.read_misses 20830 # DTB read misses 1406system.cpu1.dtb.write_hits 6472980 # DTB write hits 1407system.cpu1.dtb.write_misses 2141 # DTB write misses 1408system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1409system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1410system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1411system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1412system.cpu1.dtb.flush_entries 1623 # Number of entries that have been flushed from TLB 1413system.cpu1.dtb.align_faults 116 # Number of TLB faults due to alignment restrictions 1414system.cpu1.dtb.prefetch_faults 297 # Number of TLB faults due to prefetch 1415system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1416system.cpu1.dtb.perms_faults 184 # Number of TLB faults due to permissions restrictions 1417system.cpu1.dtb.read_accesses 10551169 # DTB read accesses 1418system.cpu1.dtb.write_accesses 6475121 # DTB write accesses 1419system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1420system.cpu1.dtb.hits 17003319 # DTB hits 1421system.cpu1.dtb.misses 22971 # DTB misses 1422system.cpu1.dtb.accesses 17026290 # DTB accesses 1423system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 1424system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1425system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1426system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1427system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1428system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1429system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1430system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1431system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1432system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1433system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1434system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1435system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1436system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1437system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1438system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1439system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1440system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1441system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1442system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1443system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1444system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1445system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1446system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1447system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1448system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1449system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1450system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1451system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1452system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1453system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 1454system.cpu1.itb.walker.walks 2051 # Table walker walks requested 1455system.cpu1.itb.walker.walksShort 2051 # Table walker walks initiated with short descriptors 1456system.cpu1.itb.walker.walksShortTerminationLevel::Level1 145 # Level at which table walker walks with short descriptors terminate 1457system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1906 # Level at which table walker walks with short descriptors terminate 1458system.cpu1.itb.walker.walkWaitTime::samples 2051 # Table walker wait (enqueue to first request) latency 1459system.cpu1.itb.walker.walkWaitTime::0 2051 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1460system.cpu1.itb.walker.walkWaitTime::total 2051 # Table walker wait (enqueue to first request) latency 1461system.cpu1.itb.walker.walkCompletionTime::samples 830 # Table walker service (enqueue to completion) latency 1462system.cpu1.itb.walker.walkCompletionTime::mean 12046.987952 # Table walker service (enqueue to completion) latency 1463system.cpu1.itb.walker.walkCompletionTime::gmean 11480.071390 # Table walker service (enqueue to completion) latency 1464system.cpu1.itb.walker.walkCompletionTime::stdev 4509.628818 # Table walker service (enqueue to completion) latency 1465system.cpu1.itb.walker.walkCompletionTime::4096-8191 126 15.18% 15.18% # Table walker service (enqueue to completion) latency 1466system.cpu1.itb.walker.walkCompletionTime::8192-12287 555 66.87% 82.05% # Table walker service (enqueue to completion) latency 1467system.cpu1.itb.walker.walkCompletionTime::12288-16383 85 10.24% 92.29% # Table walker service (enqueue to completion) latency 1468system.cpu1.itb.walker.walkCompletionTime::16384-20479 14 1.69% 93.98% # Table walker service (enqueue to completion) latency 1469system.cpu1.itb.walker.walkCompletionTime::20480-24575 22 2.65% 96.63% # Table walker service (enqueue to completion) latency 1470system.cpu1.itb.walker.walkCompletionTime::24576-28671 18 2.17% 98.80% # Table walker service (enqueue to completion) latency 1471system.cpu1.itb.walker.walkCompletionTime::28672-32767 6 0.72% 99.52% # Table walker service (enqueue to completion) latency 1472system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 99.64% # Table walker service (enqueue to completion) latency 1473system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.36% 100.00% # Table walker service (enqueue to completion) latency 1474system.cpu1.itb.walker.walkCompletionTime::total 830 # Table walker service (enqueue to completion) latency 1475system.cpu1.itb.walker.walksPending::samples -1979056532 # Table walker pending requests distribution 1476system.cpu1.itb.walker.walksPending::0 -1979056532 100.00% 100.00% # Table walker pending requests distribution 1477system.cpu1.itb.walker.walksPending::total -1979056532 # Table walker pending requests distribution 1478system.cpu1.itb.walker.walkPageSizes::4K 695 83.73% 83.73% # Table walker page sizes translated 1479system.cpu1.itb.walker.walkPageSizes::1M 135 16.27% 100.00% # Table walker page sizes translated 1480system.cpu1.itb.walker.walkPageSizes::total 830 # Table walker page sizes translated 1481system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1482system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2051 # Table walker requests started/completed, data/inst 1483system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2051 # Table walker requests started/completed, data/inst 1484system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1485system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 830 # Table walker requests started/completed, data/inst 1486system.cpu1.itb.walker.walkRequestOrigin_Completed::total 830 # Table walker requests started/completed, data/inst 1487system.cpu1.itb.walker.walkRequestOrigin::total 2881 # Table walker requests started/completed, data/inst 1488system.cpu1.itb.inst_hits 38623354 # ITB inst hits 1489system.cpu1.itb.inst_misses 2051 # ITB inst misses 1490system.cpu1.itb.read_hits 0 # DTB read hits 1491system.cpu1.itb.read_misses 0 # DTB read misses 1492system.cpu1.itb.write_hits 0 # DTB write hits 1493system.cpu1.itb.write_misses 0 # DTB write misses 1494system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1495system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1496system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1497system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1498system.cpu1.itb.flush_entries 830 # Number of entries that have been flushed from TLB 1499system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1500system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1501system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1502system.cpu1.itb.perms_faults 1040 # Number of TLB faults due to permissions restrictions 1503system.cpu1.itb.read_accesses 0 # DTB read accesses 1504system.cpu1.itb.write_accesses 0 # DTB write accesses 1505system.cpu1.itb.inst_accesses 38625405 # ITB inst accesses 1506system.cpu1.itb.hits 38623354 # DTB hits 1507system.cpu1.itb.misses 2051 # DTB misses 1508system.cpu1.itb.accesses 38625405 # DTB accesses 1509system.cpu1.numPwrStateTransitions 5477 # Number of power state transitions 1510system.cpu1.pwrStateClkGateDist::samples 2739 # Distribution of time spent in the clock gated state 1511system.cpu1.pwrStateClkGateDist::mean 1019571073.706097 # Distribution of time spent in the clock gated state 1512system.cpu1.pwrStateClkGateDist::stdev 25827442882.959442 # Distribution of time spent in the clock gated state 1513system.cpu1.pwrStateClkGateDist::underflows 1941 70.87% 70.87% # Distribution of time spent in the clock gated state 1514system.cpu1.pwrStateClkGateDist::1000-5e+10 794 28.99% 99.85% # Distribution of time spent in the clock gated state 1515system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state 1516system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 1517system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 1518system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state 1519system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 1520system.cpu1.pwrStateClkGateDist::max_value 949980394548 # Distribution of time spent in the clock gated state 1521system.cpu1.pwrStateClkGateDist::total 2739 # Distribution of time spent in the clock gated state 1522system.cpu1.pwrStateResidencyTicks::ON 55993511619 # Cumulative time (in ticks) in various power states 1523system.cpu1.pwrStateResidencyTicks::CLK_GATED 2792605170881 # Cumulative time (in ticks) in various power states 1524system.cpu1.numCycles 111990488 # number of cpu cycles simulated 1525system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1526system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1527system.cpu1.committedInsts 45059059 # Number of instructions committed 1528system.cpu1.committedOps 55122963 # Number of ops (including micro ops) committed 1529system.cpu1.discardedOps 4849343 # Number of ops (including micro ops) which were discarded before commit 1530system.cpu1.numFetchSuspends 2739 # Number of times Execute suspended instruction fetching 1531system.cpu1.quiesceCycles 5584538446 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1532system.cpu1.cpi 2.485416 # CPI: cycles per instruction 1533system.cpu1.ipc 0.402347 # IPC: instructions per cycle 1534system.cpu1.op_class_0::No_OpClass 24 0.00% 0.00% # Class of committed instruction 1535system.cpu1.op_class_0::IntAlu 38107074 69.13% 69.13% # Class of committed instruction 1536system.cpu1.op_class_0::IntMult 43629 0.08% 69.21% # Class of committed instruction 1537system.cpu1.op_class_0::IntDiv 0 0.00% 69.21% # Class of committed instruction 1538system.cpu1.op_class_0::FloatAdd 0 0.00% 69.21% # Class of committed instruction 1539system.cpu1.op_class_0::FloatCmp 0 0.00% 69.21% # Class of committed instruction 1540system.cpu1.op_class_0::FloatCvt 0 0.00% 69.21% # Class of committed instruction 1541system.cpu1.op_class_0::FloatMult 0 0.00% 69.21% # Class of committed instruction 1542system.cpu1.op_class_0::FloatMultAcc 0 0.00% 69.21% # Class of committed instruction 1543system.cpu1.op_class_0::FloatDiv 0 0.00% 69.21% # Class of committed instruction 1544system.cpu1.op_class_0::FloatMisc 0 0.00% 69.21% # Class of committed instruction 1545system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.21% # Class of committed instruction 1546system.cpu1.op_class_0::SimdAdd 0 0.00% 69.21% # Class of committed instruction 1547system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.21% # Class of committed instruction 1548system.cpu1.op_class_0::SimdAlu 0 0.00% 69.21% # Class of committed instruction 1549system.cpu1.op_class_0::SimdCmp 0 0.00% 69.21% # Class of committed instruction 1550system.cpu1.op_class_0::SimdCvt 0 0.00% 69.21% # Class of committed instruction 1551system.cpu1.op_class_0::SimdMisc 0 0.00% 69.21% # Class of committed instruction 1552system.cpu1.op_class_0::SimdMult 0 0.00% 69.21% # Class of committed instruction 1553system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.21% # Class of committed instruction 1554system.cpu1.op_class_0::SimdShift 0 0.00% 69.21% # Class of committed instruction 1555system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.21% # Class of committed instruction 1556system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.21% # Class of committed instruction 1557system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.21% # Class of committed instruction 1558system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.21% # Class of committed instruction 1559system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.21% # Class of committed instruction 1560system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.21% # Class of committed instruction 1561system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.21% # Class of committed instruction 1562system.cpu1.op_class_0::SimdFloatMisc 3226 0.01% 69.22% # Class of committed instruction 1563system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.22% # Class of committed instruction 1564system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.22% # Class of committed instruction 1565system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.22% # Class of committed instruction 1566system.cpu1.op_class_0::MemRead 10387367 18.84% 88.06% # Class of committed instruction 1567system.cpu1.op_class_0::MemWrite 6581643 11.94% 100.00% # Class of committed instruction 1568system.cpu1.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction 1569system.cpu1.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction 1570system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1571system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1572system.cpu1.op_class_0::total 55122963 # Class of committed instruction 1573system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1574system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed 1575system.cpu1.tickCycles 90184958 # Number of cycles that the object actually ticked 1576system.cpu1.idleCycles 21805530 # Total number of cycles that the object has spent stopped 1577system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 1578system.cpu1.dcache.tags.replacements 157661 # number of replacements 1579system.cpu1.dcache.tags.tagsinuse 475.726390 # Cycle average of tags in use 1580system.cpu1.dcache.tags.total_refs 16648746 # Total number of references to valid blocks. 1581system.cpu1.dcache.tags.sampled_refs 158020 # Sample count of references to valid blocks. 1582system.cpu1.dcache.tags.avg_refs 105.358474 # Average number of references to valid blocks. 1583system.cpu1.dcache.tags.warmup_cycle 91198641000 # Cycle when the warmup percentage was hit. 1584system.cpu1.dcache.tags.occ_blocks::cpu1.data 475.726390 # Average occupied blocks per requestor 1585system.cpu1.dcache.tags.occ_percent::cpu1.data 0.929153 # Average percentage of cache occupancy 1586system.cpu1.dcache.tags.occ_percent::total 0.929153 # Average percentage of cache occupancy 1587system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id 1588system.cpu1.dcache.tags.age_task_id_blocks_1024::2 284 # Occupied blocks per task id 1589system.cpu1.dcache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id 1590system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id 1591system.cpu1.dcache.tags.tag_accesses 34039754 # Number of tag accesses 1592system.cpu1.dcache.tags.data_accesses 34039754 # Number of data accesses 1593system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 1594system.cpu1.dcache.ReadReq_hits::cpu1.data 10204486 # number of ReadReq hits 1595system.cpu1.dcache.ReadReq_hits::total 10204486 # number of ReadReq hits 1596system.cpu1.dcache.WriteReq_hits::cpu1.data 6223411 # number of WriteReq hits 1597system.cpu1.dcache.WriteReq_hits::total 6223411 # number of WriteReq hits 1598system.cpu1.dcache.SoftPFReq_hits::cpu1.data 43300 # number of SoftPFReq hits 1599system.cpu1.dcache.SoftPFReq_hits::total 43300 # number of SoftPFReq hits 1600system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 71256 # number of LoadLockedReq hits 1601system.cpu1.dcache.LoadLockedReq_hits::total 71256 # number of LoadLockedReq hits 1602system.cpu1.dcache.StoreCondReq_hits::cpu1.data 62645 # number of StoreCondReq hits 1603system.cpu1.dcache.StoreCondReq_hits::total 62645 # number of StoreCondReq hits 1604system.cpu1.dcache.demand_hits::cpu1.data 16427897 # number of demand (read+write) hits 1605system.cpu1.dcache.demand_hits::total 16427897 # number of demand (read+write) hits 1606system.cpu1.dcache.overall_hits::cpu1.data 16471197 # number of overall hits 1607system.cpu1.dcache.overall_hits::total 16471197 # number of overall hits 1608system.cpu1.dcache.ReadReq_misses::cpu1.data 127390 # number of ReadReq misses 1609system.cpu1.dcache.ReadReq_misses::total 127390 # number of ReadReq misses 1610system.cpu1.dcache.WriteReq_misses::cpu1.data 122263 # number of WriteReq misses 1611system.cpu1.dcache.WriteReq_misses::total 122263 # number of WriteReq misses 1612system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24165 # number of SoftPFReq misses 1613system.cpu1.dcache.SoftPFReq_misses::total 24165 # number of SoftPFReq misses 1614system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16525 # number of LoadLockedReq misses 1615system.cpu1.dcache.LoadLockedReq_misses::total 16525 # number of LoadLockedReq misses 1616system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23356 # number of StoreCondReq misses 1617system.cpu1.dcache.StoreCondReq_misses::total 23356 # number of StoreCondReq misses 1618system.cpu1.dcache.demand_misses::cpu1.data 249653 # number of demand (read+write) misses 1619system.cpu1.dcache.demand_misses::total 249653 # number of demand (read+write) misses 1620system.cpu1.dcache.overall_misses::cpu1.data 273818 # number of overall misses 1621system.cpu1.dcache.overall_misses::total 273818 # number of overall misses 1622system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2191208500 # number of ReadReq miss cycles 1623system.cpu1.dcache.ReadReq_miss_latency::total 2191208500 # number of ReadReq miss cycles 1624system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3801376500 # number of WriteReq miss cycles 1625system.cpu1.dcache.WriteReq_miss_latency::total 3801376500 # number of WriteReq miss cycles 1626system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 322530000 # number of LoadLockedReq miss cycles 1627system.cpu1.dcache.LoadLockedReq_miss_latency::total 322530000 # number of LoadLockedReq miss cycles 1628system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 548226000 # number of StoreCondReq miss cycles 1629system.cpu1.dcache.StoreCondReq_miss_latency::total 548226000 # number of StoreCondReq miss cycles 1630system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 650000 # number of StoreCondFailReq miss cycles 1631system.cpu1.dcache.StoreCondFailReq_miss_latency::total 650000 # number of StoreCondFailReq miss cycles 1632system.cpu1.dcache.demand_miss_latency::cpu1.data 5992585000 # number of demand (read+write) miss cycles 1633system.cpu1.dcache.demand_miss_latency::total 5992585000 # number of demand (read+write) miss cycles 1634system.cpu1.dcache.overall_miss_latency::cpu1.data 5992585000 # number of overall miss cycles 1635system.cpu1.dcache.overall_miss_latency::total 5992585000 # number of overall miss cycles 1636system.cpu1.dcache.ReadReq_accesses::cpu1.data 10331876 # number of ReadReq accesses(hits+misses) 1637system.cpu1.dcache.ReadReq_accesses::total 10331876 # number of ReadReq accesses(hits+misses) 1638system.cpu1.dcache.WriteReq_accesses::cpu1.data 6345674 # number of WriteReq accesses(hits+misses) 1639system.cpu1.dcache.WriteReq_accesses::total 6345674 # number of WriteReq accesses(hits+misses) 1640system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 67465 # number of SoftPFReq accesses(hits+misses) 1641system.cpu1.dcache.SoftPFReq_accesses::total 67465 # number of SoftPFReq accesses(hits+misses) 1642system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87781 # number of LoadLockedReq accesses(hits+misses) 1643system.cpu1.dcache.LoadLockedReq_accesses::total 87781 # number of LoadLockedReq accesses(hits+misses) 1644system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 86001 # number of StoreCondReq accesses(hits+misses) 1645system.cpu1.dcache.StoreCondReq_accesses::total 86001 # number of StoreCondReq accesses(hits+misses) 1646system.cpu1.dcache.demand_accesses::cpu1.data 16677550 # number of demand (read+write) accesses 1647system.cpu1.dcache.demand_accesses::total 16677550 # number of demand (read+write) accesses 1648system.cpu1.dcache.overall_accesses::cpu1.data 16745015 # number of overall (read+write) accesses 1649system.cpu1.dcache.overall_accesses::total 16745015 # number of overall (read+write) accesses 1650system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.012330 # miss rate for ReadReq accesses 1651system.cpu1.dcache.ReadReq_miss_rate::total 0.012330 # miss rate for ReadReq accesses 1652system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.019267 # miss rate for WriteReq accesses 1653system.cpu1.dcache.WriteReq_miss_rate::total 0.019267 # miss rate for WriteReq accesses 1654system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.358186 # miss rate for SoftPFReq accesses 1655system.cpu1.dcache.SoftPFReq_miss_rate::total 0.358186 # miss rate for SoftPFReq accesses 1656system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.188253 # miss rate for LoadLockedReq accesses 1657system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.188253 # miss rate for LoadLockedReq accesses 1658system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.271578 # miss rate for StoreCondReq accesses 1659system.cpu1.dcache.StoreCondReq_miss_rate::total 0.271578 # miss rate for StoreCondReq accesses 1660system.cpu1.dcache.demand_miss_rate::cpu1.data 0.014969 # miss rate for demand accesses 1661system.cpu1.dcache.demand_miss_rate::total 0.014969 # miss rate for demand accesses 1662system.cpu1.dcache.overall_miss_rate::cpu1.data 0.016352 # miss rate for overall accesses 1663system.cpu1.dcache.overall_miss_rate::total 0.016352 # miss rate for overall accesses 1664system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17200.788916 # average ReadReq miss latency 1665system.cpu1.dcache.ReadReq_avg_miss_latency::total 17200.788916 # average ReadReq miss latency 1666system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31091.798009 # average WriteReq miss latency 1667system.cpu1.dcache.WriteReq_avg_miss_latency::total 31091.798009 # average WriteReq miss latency 1668system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19517.700454 # average LoadLockedReq miss latency 1669system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19517.700454 # average LoadLockedReq miss latency 1670system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23472.598048 # average StoreCondReq miss latency 1671system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23472.598048 # average StoreCondReq miss latency 1672system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1673system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1674system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24003.657076 # average overall miss latency 1675system.cpu1.dcache.demand_avg_miss_latency::total 24003.657076 # average overall miss latency 1676system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21885.285116 # average overall miss latency 1677system.cpu1.dcache.overall_avg_miss_latency::total 21885.285116 # average overall miss latency 1678system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1679system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1680system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1681system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1682system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1683system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1684system.cpu1.dcache.writebacks::writebacks 157661 # number of writebacks 1685system.cpu1.dcache.writebacks::total 157661 # number of writebacks 1686system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 4447 # number of ReadReq MSHR hits 1687system.cpu1.dcache.ReadReq_mshr_hits::total 4447 # number of ReadReq MSHR hits 1688system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 42267 # number of WriteReq MSHR hits 1689system.cpu1.dcache.WriteReq_mshr_hits::total 42267 # number of WriteReq MSHR hits 1690system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11747 # number of LoadLockedReq MSHR hits 1691system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11747 # number of LoadLockedReq MSHR hits 1692system.cpu1.dcache.demand_mshr_hits::cpu1.data 46714 # number of demand (read+write) MSHR hits 1693system.cpu1.dcache.demand_mshr_hits::total 46714 # number of demand (read+write) MSHR hits 1694system.cpu1.dcache.overall_mshr_hits::cpu1.data 46714 # number of overall MSHR hits 1695system.cpu1.dcache.overall_mshr_hits::total 46714 # number of overall MSHR hits 1696system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 122943 # number of ReadReq MSHR misses 1697system.cpu1.dcache.ReadReq_mshr_misses::total 122943 # number of ReadReq MSHR misses 1698system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79996 # number of WriteReq MSHR misses 1699system.cpu1.dcache.WriteReq_mshr_misses::total 79996 # number of WriteReq MSHR misses 1700system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23657 # number of SoftPFReq MSHR misses 1701system.cpu1.dcache.SoftPFReq_mshr_misses::total 23657 # number of SoftPFReq MSHR misses 1702system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4778 # number of LoadLockedReq MSHR misses 1703system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4778 # number of LoadLockedReq MSHR misses 1704system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23356 # number of StoreCondReq MSHR misses 1705system.cpu1.dcache.StoreCondReq_mshr_misses::total 23356 # number of StoreCondReq MSHR misses 1706system.cpu1.dcache.demand_mshr_misses::cpu1.data 202939 # number of demand (read+write) MSHR misses 1707system.cpu1.dcache.demand_mshr_misses::total 202939 # number of demand (read+write) MSHR misses 1708system.cpu1.dcache.overall_mshr_misses::cpu1.data 226596 # number of overall MSHR misses 1709system.cpu1.dcache.overall_mshr_misses::total 226596 # number of overall MSHR misses 1710system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14406 # number of ReadReq MSHR uncacheable 1711system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14406 # number of ReadReq MSHR uncacheable 1712system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11728 # number of WriteReq MSHR uncacheable 1713system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11728 # number of WriteReq MSHR uncacheable 1714system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26134 # number of overall MSHR uncacheable misses 1715system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26134 # number of overall MSHR uncacheable misses 1716system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1987288500 # number of ReadReq MSHR miss cycles 1717system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1987288500 # number of ReadReq MSHR miss cycles 1718system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2305734500 # number of WriteReq MSHR miss cycles 1719system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2305734500 # number of WriteReq MSHR miss cycles 1720system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 418963500 # number of SoftPFReq MSHR miss cycles 1721system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 418963500 # number of SoftPFReq MSHR miss cycles 1722system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86008500 # number of LoadLockedReq MSHR miss cycles 1723system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86008500 # number of LoadLockedReq MSHR miss cycles 1724system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 524885000 # number of StoreCondReq MSHR miss cycles 1725system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 524885000 # number of StoreCondReq MSHR miss cycles 1726system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 635000 # number of StoreCondFailReq MSHR miss cycles 1727system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 635000 # number of StoreCondFailReq MSHR miss cycles 1728system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4293023000 # number of demand (read+write) MSHR miss cycles 1729system.cpu1.dcache.demand_mshr_miss_latency::total 4293023000 # number of demand (read+write) MSHR miss cycles 1730system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4711986500 # number of overall MSHR miss cycles 1731system.cpu1.dcache.overall_mshr_miss_latency::total 4711986500 # number of overall MSHR miss cycles 1732system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2490253500 # number of ReadReq MSHR uncacheable cycles 1733system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2490253500 # number of ReadReq MSHR uncacheable cycles 1734system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2490253500 # number of overall MSHR uncacheable cycles 1735system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2490253500 # number of overall MSHR uncacheable cycles 1736system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.011899 # mshr miss rate for ReadReq accesses 1737system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.011899 # mshr miss rate for ReadReq accesses 1738system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012606 # mshr miss rate for WriteReq accesses 1739system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.012606 # mshr miss rate for WriteReq accesses 1740system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.350656 # mshr miss rate for SoftPFReq accesses 1741system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.350656 # mshr miss rate for SoftPFReq accesses 1742system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054431 # mshr miss rate for LoadLockedReq accesses 1743system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054431 # mshr miss rate for LoadLockedReq accesses 1744system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.271578 # mshr miss rate for StoreCondReq accesses 1745system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.271578 # mshr miss rate for StoreCondReq accesses 1746system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.012168 # mshr miss rate for demand accesses 1747system.cpu1.dcache.demand_mshr_miss_rate::total 0.012168 # mshr miss rate for demand accesses 1748system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.013532 # mshr miss rate for overall accesses 1749system.cpu1.dcache.overall_mshr_miss_rate::total 0.013532 # mshr miss rate for overall accesses 1750system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16164.307850 # average ReadReq mshr miss latency 1751system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16164.307850 # average ReadReq mshr miss latency 1752system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28823.122406 # average WriteReq mshr miss latency 1753system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28823.122406 # average WriteReq mshr miss latency 1754system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17709.916727 # average SoftPFReq mshr miss latency 1755system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17709.916727 # average SoftPFReq mshr miss latency 1756system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18000.941817 # average LoadLockedReq mshr miss latency 1757system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18000.941817 # average LoadLockedReq mshr miss latency 1758system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22473.240281 # average StoreCondReq mshr miss latency 1759system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22473.240281 # average StoreCondReq mshr miss latency 1760system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1761system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1762system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21154.253249 # average overall mshr miss latency 1763system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21154.253249 # average overall mshr miss latency 1764system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20794.658776 # average overall mshr miss latency 1765system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20794.658776 # average overall mshr miss latency 1766system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172862.244898 # average ReadReq mshr uncacheable latency 1767system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172862.244898 # average ReadReq mshr uncacheable latency 1768system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95287.881687 # average overall mshr uncacheable latency 1769system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95287.881687 # average overall mshr uncacheable latency 1770system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 1771system.cpu1.icache.tags.replacements 872875 # number of replacements 1772system.cpu1.icache.tags.tagsinuse 499.208474 # Cycle average of tags in use 1773system.cpu1.icache.tags.total_refs 37748872 # Total number of references to valid blocks. 1774system.cpu1.icache.tags.sampled_refs 873387 # Sample count of references to valid blocks. 1775system.cpu1.icache.tags.avg_refs 43.221243 # Average number of references to valid blocks. 1776system.cpu1.icache.tags.warmup_cycle 72896771000 # Cycle when the warmup percentage was hit. 1777system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.208474 # Average occupied blocks per requestor 1778system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975017 # Average percentage of cache occupancy 1779system.cpu1.icache.tags.occ_percent::total 0.975017 # Average percentage of cache occupancy 1780system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1781system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id 1782system.cpu1.icache.tags.age_task_id_blocks_1024::3 48 # Occupied blocks per task id 1783system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 1784system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1785system.cpu1.icache.tags.tag_accesses 78117905 # Number of tag accesses 1786system.cpu1.icache.tags.data_accesses 78117905 # Number of data accesses 1787system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 1788system.cpu1.icache.ReadReq_hits::cpu1.inst 37748872 # number of ReadReq hits 1789system.cpu1.icache.ReadReq_hits::total 37748872 # number of ReadReq hits 1790system.cpu1.icache.demand_hits::cpu1.inst 37748872 # number of demand (read+write) hits 1791system.cpu1.icache.demand_hits::total 37748872 # number of demand (read+write) hits 1792system.cpu1.icache.overall_hits::cpu1.inst 37748872 # number of overall hits 1793system.cpu1.icache.overall_hits::total 37748872 # number of overall hits 1794system.cpu1.icache.ReadReq_misses::cpu1.inst 873387 # number of ReadReq misses 1795system.cpu1.icache.ReadReq_misses::total 873387 # number of ReadReq misses 1796system.cpu1.icache.demand_misses::cpu1.inst 873387 # number of demand (read+write) misses 1797system.cpu1.icache.demand_misses::total 873387 # number of demand (read+write) misses 1798system.cpu1.icache.overall_misses::cpu1.inst 873387 # number of overall misses 1799system.cpu1.icache.overall_misses::total 873387 # number of overall misses 1800system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8011666500 # number of ReadReq miss cycles 1801system.cpu1.icache.ReadReq_miss_latency::total 8011666500 # number of ReadReq miss cycles 1802system.cpu1.icache.demand_miss_latency::cpu1.inst 8011666500 # number of demand (read+write) miss cycles 1803system.cpu1.icache.demand_miss_latency::total 8011666500 # number of demand (read+write) miss cycles 1804system.cpu1.icache.overall_miss_latency::cpu1.inst 8011666500 # number of overall miss cycles 1805system.cpu1.icache.overall_miss_latency::total 8011666500 # number of overall miss cycles 1806system.cpu1.icache.ReadReq_accesses::cpu1.inst 38622259 # number of ReadReq accesses(hits+misses) 1807system.cpu1.icache.ReadReq_accesses::total 38622259 # number of ReadReq accesses(hits+misses) 1808system.cpu1.icache.demand_accesses::cpu1.inst 38622259 # number of demand (read+write) accesses 1809system.cpu1.icache.demand_accesses::total 38622259 # number of demand (read+write) accesses 1810system.cpu1.icache.overall_accesses::cpu1.inst 38622259 # number of overall (read+write) accesses 1811system.cpu1.icache.overall_accesses::total 38622259 # number of overall (read+write) accesses 1812system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022614 # miss rate for ReadReq accesses 1813system.cpu1.icache.ReadReq_miss_rate::total 0.022614 # miss rate for ReadReq accesses 1814system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022614 # miss rate for demand accesses 1815system.cpu1.icache.demand_miss_rate::total 0.022614 # miss rate for demand accesses 1816system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022614 # miss rate for overall accesses 1817system.cpu1.icache.overall_miss_rate::total 0.022614 # miss rate for overall accesses 1818system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9173.100241 # average ReadReq miss latency 1819system.cpu1.icache.ReadReq_avg_miss_latency::total 9173.100241 # average ReadReq miss latency 1820system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9173.100241 # average overall miss latency 1821system.cpu1.icache.demand_avg_miss_latency::total 9173.100241 # average overall miss latency 1822system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9173.100241 # average overall miss latency 1823system.cpu1.icache.overall_avg_miss_latency::total 9173.100241 # average overall miss latency 1824system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1825system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1826system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1827system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1828system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1829system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1830system.cpu1.icache.writebacks::writebacks 872875 # number of writebacks 1831system.cpu1.icache.writebacks::total 872875 # number of writebacks 1832system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 873387 # number of ReadReq MSHR misses 1833system.cpu1.icache.ReadReq_mshr_misses::total 873387 # number of ReadReq MSHR misses 1834system.cpu1.icache.demand_mshr_misses::cpu1.inst 873387 # number of demand (read+write) MSHR misses 1835system.cpu1.icache.demand_mshr_misses::total 873387 # number of demand (read+write) MSHR misses 1836system.cpu1.icache.overall_mshr_misses::cpu1.inst 873387 # number of overall MSHR misses 1837system.cpu1.icache.overall_mshr_misses::total 873387 # number of overall MSHR misses 1838system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 1839system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable 1840system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 1841system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses 1842system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7574973000 # number of ReadReq MSHR miss cycles 1843system.cpu1.icache.ReadReq_mshr_miss_latency::total 7574973000 # number of ReadReq MSHR miss cycles 1844system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7574973000 # number of demand (read+write) MSHR miss cycles 1845system.cpu1.icache.demand_mshr_miss_latency::total 7574973000 # number of demand (read+write) MSHR miss cycles 1846system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7574973000 # number of overall MSHR miss cycles 1847system.cpu1.icache.overall_mshr_miss_latency::total 7574973000 # number of overall MSHR miss cycles 1848system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11042500 # number of ReadReq MSHR uncacheable cycles 1849system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 11042500 # number of ReadReq MSHR uncacheable cycles 1850system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 11042500 # number of overall MSHR uncacheable cycles 1851system.cpu1.icache.overall_mshr_uncacheable_latency::total 11042500 # number of overall MSHR uncacheable cycles 1852system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022614 # mshr miss rate for ReadReq accesses 1853system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022614 # mshr miss rate for ReadReq accesses 1854system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022614 # mshr miss rate for demand accesses 1855system.cpu1.icache.demand_mshr_miss_rate::total 0.022614 # mshr miss rate for demand accesses 1856system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022614 # mshr miss rate for overall accesses 1857system.cpu1.icache.overall_mshr_miss_rate::total 0.022614 # mshr miss rate for overall accesses 1858system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8673.100241 # average ReadReq mshr miss latency 1859system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8673.100241 # average ReadReq mshr miss latency 1860system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8673.100241 # average overall mshr miss latency 1861system.cpu1.icache.demand_avg_mshr_miss_latency::total 8673.100241 # average overall mshr miss latency 1862system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8673.100241 # average overall mshr miss latency 1863system.cpu1.icache.overall_avg_mshr_miss_latency::total 8673.100241 # average overall mshr miss latency 1864system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98593.750000 # average ReadReq mshr uncacheable latency 1865system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 98593.750000 # average ReadReq mshr uncacheable latency 1866system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98593.750000 # average overall mshr uncacheable latency 1867system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 98593.750000 # average overall mshr uncacheable latency 1868system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 1869system.cpu1.l2cache.prefetcher.num_hwpf_issued 118852 # number of hwpf issued 1870system.cpu1.l2cache.prefetcher.pfIdentified 118852 # number of prefetch candidates identified 1871system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 1872system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1873system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1874system.cpu1.l2cache.prefetcher.pfSpanPage 49172 # number of prefetches not generated due to page crossing 1875system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 1876system.cpu1.l2cache.tags.replacements 37377 # number of replacements 1877system.cpu1.l2cache.tags.tagsinuse 14753.834184 # Cycle average of tags in use 1878system.cpu1.l2cache.tags.total_refs 946442 # Total number of references to valid blocks. 1879system.cpu1.l2cache.tags.sampled_refs 52088 # Sample count of references to valid blocks. 1880system.cpu1.l2cache.tags.avg_refs 18.170058 # Average number of references to valid blocks. 1881system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1882system.cpu1.l2cache.tags.occ_blocks::writebacks 14422.597482 # Average occupied blocks per requestor 1883system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 42.225036 # Average occupied blocks per requestor 1884system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.137350 # Average occupied blocks per requestor 1885system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 287.874316 # Average occupied blocks per requestor 1886system.cpu1.l2cache.tags.occ_percent::writebacks 0.880285 # Average percentage of cache occupancy 1887system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002577 # Average percentage of cache occupancy 1888system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000069 # Average percentage of cache occupancy 1889system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.017570 # Average percentage of cache occupancy 1890system.cpu1.l2cache.tags.occ_percent::total 0.900503 # Average percentage of cache occupancy 1891system.cpu1.l2cache.tags.occ_task_id_blocks::1022 261 # Occupied blocks per task id 1892system.cpu1.l2cache.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id 1893system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14372 # Occupied blocks per task id 1894system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id 1895system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 24 # Occupied blocks per task id 1896system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 234 # Occupied blocks per task id 1897system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1898system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id 1899system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 53 # Occupied blocks per task id 1900system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1285 # Occupied blocks per task id 1901system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2929 # Occupied blocks per task id 1902system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10158 # Occupied blocks per task id 1903system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.015930 # Percentage of cache occupancy per task id 1904system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004761 # Percentage of cache occupancy per task id 1905system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.877197 # Percentage of cache occupancy per task id 1906system.cpu1.l2cache.tags.tag_accesses 35693220 # Number of tag accesses 1907system.cpu1.l2cache.tags.data_accesses 35693220 # Number of data accesses 1908system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 1909system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 23446 # number of ReadReq hits 1910system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2580 # number of ReadReq hits 1911system.cpu1.l2cache.ReadReq_hits::total 26026 # number of ReadReq hits 1912system.cpu1.l2cache.WritebackDirty_hits::writebacks 95283 # number of WritebackDirty hits 1913system.cpu1.l2cache.WritebackDirty_hits::total 95283 # number of WritebackDirty hits 1914system.cpu1.l2cache.WritebackClean_hits::writebacks 916386 # number of WritebackClean hits 1915system.cpu1.l2cache.WritebackClean_hits::total 916386 # number of WritebackClean hits 1916system.cpu1.l2cache.ReadExReq_hits::cpu1.data 18220 # number of ReadExReq hits 1917system.cpu1.l2cache.ReadExReq_hits::total 18220 # number of ReadExReq hits 1918system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 844850 # number of ReadCleanReq hits 1919system.cpu1.l2cache.ReadCleanReq_hits::total 844850 # number of ReadCleanReq hits 1920system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 81639 # number of ReadSharedReq hits 1921system.cpu1.l2cache.ReadSharedReq_hits::total 81639 # number of ReadSharedReq hits 1922system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 23446 # number of demand (read+write) hits 1923system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2580 # number of demand (read+write) hits 1924system.cpu1.l2cache.demand_hits::cpu1.inst 844850 # number of demand (read+write) hits 1925system.cpu1.l2cache.demand_hits::cpu1.data 99859 # number of demand (read+write) hits 1926system.cpu1.l2cache.demand_hits::total 970735 # number of demand (read+write) hits 1927system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 23446 # number of overall hits 1928system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2580 # number of overall hits 1929system.cpu1.l2cache.overall_hits::cpu1.inst 844850 # number of overall hits 1930system.cpu1.l2cache.overall_hits::cpu1.data 99859 # number of overall hits 1931system.cpu1.l2cache.overall_hits::total 970735 # number of overall hits 1932system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 823 # number of ReadReq misses 1933system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 297 # number of ReadReq misses 1934system.cpu1.l2cache.ReadReq_misses::total 1120 # number of ReadReq misses 1935system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29230 # number of UpgradeReq misses 1936system.cpu1.l2cache.UpgradeReq_misses::total 29230 # number of UpgradeReq misses 1937system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23356 # number of SCUpgradeReq misses 1938system.cpu1.l2cache.SCUpgradeReq_misses::total 23356 # number of SCUpgradeReq misses 1939system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32546 # number of ReadExReq misses 1940system.cpu1.l2cache.ReadExReq_misses::total 32546 # number of ReadExReq misses 1941system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 28537 # number of ReadCleanReq misses 1942system.cpu1.l2cache.ReadCleanReq_misses::total 28537 # number of ReadCleanReq misses 1943system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69739 # number of ReadSharedReq misses 1944system.cpu1.l2cache.ReadSharedReq_misses::total 69739 # number of ReadSharedReq misses 1945system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 823 # number of demand (read+write) misses 1946system.cpu1.l2cache.demand_misses::cpu1.itb.walker 297 # number of demand (read+write) misses 1947system.cpu1.l2cache.demand_misses::cpu1.inst 28537 # number of demand (read+write) misses 1948system.cpu1.l2cache.demand_misses::cpu1.data 102285 # number of demand (read+write) misses 1949system.cpu1.l2cache.demand_misses::total 131942 # number of demand (read+write) misses 1950system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 823 # number of overall misses 1951system.cpu1.l2cache.overall_misses::cpu1.itb.walker 297 # number of overall misses 1952system.cpu1.l2cache.overall_misses::cpu1.inst 28537 # number of overall misses 1953system.cpu1.l2cache.overall_misses::cpu1.data 102285 # number of overall misses 1954system.cpu1.l2cache.overall_misses::total 131942 # number of overall misses 1955system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 21253500 # number of ReadReq miss cycles 1956system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5882500 # number of ReadReq miss cycles 1957system.cpu1.l2cache.ReadReq_miss_latency::total 27136000 # number of ReadReq miss cycles 1958system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 7496000 # number of UpgradeReq miss cycles 1959system.cpu1.l2cache.UpgradeReq_miss_latency::total 7496000 # number of UpgradeReq miss cycles 1960system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 16835000 # number of SCUpgradeReq miss cycles 1961system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 16835000 # number of SCUpgradeReq miss cycles 1962system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 611000 # number of SCUpgradeFailReq miss cycles 1963system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 611000 # number of SCUpgradeFailReq miss cycles 1964system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1439672500 # number of ReadExReq miss cycles 1965system.cpu1.l2cache.ReadExReq_miss_latency::total 1439672500 # number of ReadExReq miss cycles 1966system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1146878000 # number of ReadCleanReq miss cycles 1967system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1146878000 # number of ReadCleanReq miss cycles 1968system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1720708495 # number of ReadSharedReq miss cycles 1969system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1720708495 # number of ReadSharedReq miss cycles 1970system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 21253500 # number of demand (read+write) miss cycles 1971system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5882500 # number of demand (read+write) miss cycles 1972system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1146878000 # number of demand (read+write) miss cycles 1973system.cpu1.l2cache.demand_miss_latency::cpu1.data 3160380995 # number of demand (read+write) miss cycles 1974system.cpu1.l2cache.demand_miss_latency::total 4334394995 # number of demand (read+write) miss cycles 1975system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 21253500 # number of overall miss cycles 1976system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5882500 # number of overall miss cycles 1977system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1146878000 # number of overall miss cycles 1978system.cpu1.l2cache.overall_miss_latency::cpu1.data 3160380995 # number of overall miss cycles 1979system.cpu1.l2cache.overall_miss_latency::total 4334394995 # number of overall miss cycles 1980system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 24269 # number of ReadReq accesses(hits+misses) 1981system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2877 # number of ReadReq accesses(hits+misses) 1982system.cpu1.l2cache.ReadReq_accesses::total 27146 # number of ReadReq accesses(hits+misses) 1983system.cpu1.l2cache.WritebackDirty_accesses::writebacks 95283 # number of WritebackDirty accesses(hits+misses) 1984system.cpu1.l2cache.WritebackDirty_accesses::total 95283 # number of WritebackDirty accesses(hits+misses) 1985system.cpu1.l2cache.WritebackClean_accesses::writebacks 916386 # number of WritebackClean accesses(hits+misses) 1986system.cpu1.l2cache.WritebackClean_accesses::total 916386 # number of WritebackClean accesses(hits+misses) 1987system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29230 # number of UpgradeReq accesses(hits+misses) 1988system.cpu1.l2cache.UpgradeReq_accesses::total 29230 # number of UpgradeReq accesses(hits+misses) 1989system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23356 # number of SCUpgradeReq accesses(hits+misses) 1990system.cpu1.l2cache.SCUpgradeReq_accesses::total 23356 # number of SCUpgradeReq accesses(hits+misses) 1991system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50766 # number of ReadExReq accesses(hits+misses) 1992system.cpu1.l2cache.ReadExReq_accesses::total 50766 # number of ReadExReq accesses(hits+misses) 1993system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 873387 # number of ReadCleanReq accesses(hits+misses) 1994system.cpu1.l2cache.ReadCleanReq_accesses::total 873387 # number of ReadCleanReq accesses(hits+misses) 1995system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 151378 # number of ReadSharedReq accesses(hits+misses) 1996system.cpu1.l2cache.ReadSharedReq_accesses::total 151378 # number of ReadSharedReq accesses(hits+misses) 1997system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 24269 # number of demand (read+write) accesses 1998system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2877 # number of demand (read+write) accesses 1999system.cpu1.l2cache.demand_accesses::cpu1.inst 873387 # number of demand (read+write) accesses 2000system.cpu1.l2cache.demand_accesses::cpu1.data 202144 # number of demand (read+write) accesses 2001system.cpu1.l2cache.demand_accesses::total 1102677 # number of demand (read+write) accesses 2002system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 24269 # number of overall (read+write) accesses 2003system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2877 # number of overall (read+write) accesses 2004system.cpu1.l2cache.overall_accesses::cpu1.inst 873387 # number of overall (read+write) accesses 2005system.cpu1.l2cache.overall_accesses::cpu1.data 202144 # number of overall (read+write) accesses 2006system.cpu1.l2cache.overall_accesses::total 1102677 # number of overall (read+write) accesses 2007system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.033912 # miss rate for ReadReq accesses 2008system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.103233 # miss rate for ReadReq accesses 2009system.cpu1.l2cache.ReadReq_miss_rate::total 0.041258 # miss rate for ReadReq accesses 2010system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2011system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2012system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2013system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2014system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.641098 # miss rate for ReadExReq accesses 2015system.cpu1.l2cache.ReadExReq_miss_rate::total 0.641098 # miss rate for ReadExReq accesses 2016system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.032674 # miss rate for ReadCleanReq accesses 2017system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.032674 # miss rate for ReadCleanReq accesses 2018system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.460694 # miss rate for ReadSharedReq accesses 2019system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.460694 # miss rate for ReadSharedReq accesses 2020system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.033912 # miss rate for demand accesses 2021system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.103233 # miss rate for demand accesses 2022system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.032674 # miss rate for demand accesses 2023system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.506001 # miss rate for demand accesses 2024system.cpu1.l2cache.demand_miss_rate::total 0.119656 # miss rate for demand accesses 2025system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.033912 # miss rate for overall accesses 2026system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.103233 # miss rate for overall accesses 2027system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.032674 # miss rate for overall accesses 2028system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.506001 # miss rate for overall accesses 2029system.cpu1.l2cache.overall_miss_rate::total 0.119656 # miss rate for overall accesses 2030system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25824.422843 # average ReadReq miss latency 2031system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19806.397306 # average ReadReq miss latency 2032system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24228.571429 # average ReadReq miss latency 2033system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 256.448854 # average UpgradeReq miss latency 2034system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 256.448854 # average UpgradeReq miss latency 2035system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 720.799794 # average SCUpgradeReq miss latency 2036system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 720.799794 # average SCUpgradeReq miss latency 2037system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency 2038system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 2039system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44235.005838 # average ReadExReq miss latency 2040system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44235.005838 # average ReadExReq miss latency 2041system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40189.157935 # average ReadCleanReq miss latency 2042system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40189.157935 # average ReadCleanReq miss latency 2043system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 24673.547011 # average ReadSharedReq miss latency 2044system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 24673.547011 # average ReadSharedReq miss latency 2045system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25824.422843 # average overall miss latency 2046system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19806.397306 # average overall miss latency 2047system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40189.157935 # average overall miss latency 2048system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30897.795327 # average overall miss latency 2049system.cpu1.l2cache.demand_avg_miss_latency::total 32850.760145 # average overall miss latency 2050system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25824.422843 # average overall miss latency 2051system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19806.397306 # average overall miss latency 2052system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40189.157935 # average overall miss latency 2053system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30897.795327 # average overall miss latency 2054system.cpu1.l2cache.overall_avg_miss_latency::total 32850.760145 # average overall miss latency 2055system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2056system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2057system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2058system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2059system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2060system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2061system.cpu1.l2cache.unused_prefetches 596 # number of HardPF blocks evicted w/o reference 2062system.cpu1.l2cache.writebacks::writebacks 29159 # number of writebacks 2063system.cpu1.l2cache.writebacks::total 29159 # number of writebacks 2064system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 3 # number of ReadReq MSHR hits 2065system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 3 # number of ReadReq MSHR hits 2066system.cpu1.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 2067system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 174 # number of ReadExReq MSHR hits 2068system.cpu1.l2cache.ReadExReq_mshr_hits::total 174 # number of ReadExReq MSHR hits 2069system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 5 # number of ReadCleanReq MSHR hits 2070system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits 2071system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 44 # number of ReadSharedReq MSHR hits 2072system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 44 # number of ReadSharedReq MSHR hits 2073system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 3 # number of demand (read+write) MSHR hits 2074system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 3 # number of demand (read+write) MSHR hits 2075system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits 2076system.cpu1.l2cache.demand_mshr_hits::cpu1.data 218 # number of demand (read+write) MSHR hits 2077system.cpu1.l2cache.demand_mshr_hits::total 229 # number of demand (read+write) MSHR hits 2078system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 3 # number of overall MSHR hits 2079system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 3 # number of overall MSHR hits 2080system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits 2081system.cpu1.l2cache.overall_mshr_hits::cpu1.data 218 # number of overall MSHR hits 2082system.cpu1.l2cache.overall_mshr_hits::total 229 # number of overall MSHR hits 2083system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 820 # number of ReadReq MSHR misses 2084system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 294 # number of ReadReq MSHR misses 2085system.cpu1.l2cache.ReadReq_mshr_misses::total 1114 # number of ReadReq MSHR misses 2086system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 19637 # number of HardPFReq MSHR misses 2087system.cpu1.l2cache.HardPFReq_mshr_misses::total 19637 # number of HardPFReq MSHR misses 2088system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29230 # number of UpgradeReq MSHR misses 2089system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29230 # number of UpgradeReq MSHR misses 2090system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23356 # number of SCUpgradeReq MSHR misses 2091system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23356 # number of SCUpgradeReq MSHR misses 2092system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 32372 # number of ReadExReq MSHR misses 2093system.cpu1.l2cache.ReadExReq_mshr_misses::total 32372 # number of ReadExReq MSHR misses 2094system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 28532 # number of ReadCleanReq MSHR misses 2095system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 28532 # number of ReadCleanReq MSHR misses 2096system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69695 # number of ReadSharedReq MSHR misses 2097system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69695 # number of ReadSharedReq MSHR misses 2098system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 820 # number of demand (read+write) MSHR misses 2099system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 294 # number of demand (read+write) MSHR misses 2100system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 28532 # number of demand (read+write) MSHR misses 2101system.cpu1.l2cache.demand_mshr_misses::cpu1.data 102067 # number of demand (read+write) MSHR misses 2102system.cpu1.l2cache.demand_mshr_misses::total 131713 # number of demand (read+write) MSHR misses 2103system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 820 # number of overall MSHR misses 2104system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 294 # number of overall MSHR misses 2105system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 28532 # number of overall MSHR misses 2106system.cpu1.l2cache.overall_mshr_misses::cpu1.data 102067 # number of overall MSHR misses 2107system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 19637 # number of overall MSHR misses 2108system.cpu1.l2cache.overall_mshr_misses::total 151350 # number of overall MSHR misses 2109system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 2110system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14406 # number of ReadReq MSHR uncacheable 2111system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14518 # number of ReadReq MSHR uncacheable 2112system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11728 # number of WriteReq MSHR uncacheable 2113system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11728 # number of WriteReq MSHR uncacheable 2114system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 2115system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26134 # number of overall MSHR uncacheable misses 2116system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26246 # number of overall MSHR uncacheable misses 2117system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 16302000 # number of ReadReq MSHR miss cycles 2118system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4074000 # number of ReadReq MSHR miss cycles 2119system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 20376000 # number of ReadReq MSHR miss cycles 2120system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 732946008 # number of HardPFReq MSHR miss cycles 2121system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 732946008 # number of HardPFReq MSHR miss cycles 2122system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 445433500 # number of UpgradeReq MSHR miss cycles 2123system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 445433500 # number of UpgradeReq MSHR miss cycles 2124system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 348598000 # number of SCUpgradeReq MSHR miss cycles 2125system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 348598000 # number of SCUpgradeReq MSHR miss cycles 2126system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 521000 # number of SCUpgradeFailReq MSHR miss cycles 2127system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 521000 # number of SCUpgradeFailReq MSHR miss cycles 2128system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1224744500 # number of ReadExReq MSHR miss cycles 2129system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1224744500 # number of ReadExReq MSHR miss cycles 2130system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 975419000 # number of ReadCleanReq MSHR miss cycles 2131system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 975419000 # number of ReadCleanReq MSHR miss cycles 2132system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1300674995 # number of ReadSharedReq MSHR miss cycles 2133system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1300674995 # number of ReadSharedReq MSHR miss cycles 2134system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 16302000 # number of demand (read+write) MSHR miss cycles 2135system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4074000 # number of demand (read+write) MSHR miss cycles 2136system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 975419000 # number of demand (read+write) MSHR miss cycles 2137system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2525419495 # number of demand (read+write) MSHR miss cycles 2138system.cpu1.l2cache.demand_mshr_miss_latency::total 3521214495 # number of demand (read+write) MSHR miss cycles 2139system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 16302000 # number of overall MSHR miss cycles 2140system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4074000 # number of overall MSHR miss cycles 2141system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 975419000 # number of overall MSHR miss cycles 2142system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2525419495 # number of overall MSHR miss cycles 2143system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 732946008 # number of overall MSHR miss cycles 2144system.cpu1.l2cache.overall_mshr_miss_latency::total 4254160503 # number of overall MSHR miss cycles 2145system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10146500 # number of ReadReq MSHR uncacheable cycles 2146system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2374983500 # number of ReadReq MSHR uncacheable cycles 2147system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2385130000 # number of ReadReq MSHR uncacheable cycles 2148system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10146500 # number of overall MSHR uncacheable cycles 2149system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2374983500 # number of overall MSHR uncacheable cycles 2150system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2385130000 # number of overall MSHR uncacheable cycles 2151system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.033788 # mshr miss rate for ReadReq accesses 2152system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.102190 # mshr miss rate for ReadReq accesses 2153system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041037 # mshr miss rate for ReadReq accesses 2154system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2155system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2156system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2157system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2158system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2159system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2160system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.637671 # mshr miss rate for ReadExReq accesses 2161system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.637671 # mshr miss rate for ReadExReq accesses 2162system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.032668 # mshr miss rate for ReadCleanReq accesses 2163system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.032668 # mshr miss rate for ReadCleanReq accesses 2164system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.460404 # mshr miss rate for ReadSharedReq accesses 2165system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.460404 # mshr miss rate for ReadSharedReq accesses 2166system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.033788 # mshr miss rate for demand accesses 2167system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.102190 # mshr miss rate for demand accesses 2168system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.032668 # mshr miss rate for demand accesses 2169system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.504922 # mshr miss rate for demand accesses 2170system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119448 # mshr miss rate for demand accesses 2171system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.033788 # mshr miss rate for overall accesses 2172system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.102190 # mshr miss rate for overall accesses 2173system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.032668 # mshr miss rate for overall accesses 2174system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.504922 # mshr miss rate for overall accesses 2175system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2176system.cpu1.l2cache.overall_mshr_miss_rate::total 0.137257 # mshr miss rate for overall accesses 2177system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19880.487805 # average ReadReq mshr miss latency 2178system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13857.142857 # average ReadReq mshr miss latency 2179system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18290.843806 # average ReadReq mshr miss latency 2180system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37324.744513 # average HardPFReq mshr miss latency 2181system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37324.744513 # average HardPFReq mshr miss latency 2182system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15238.915498 # average UpgradeReq mshr miss latency 2183system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15238.915498 # average UpgradeReq mshr miss latency 2184system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14925.415311 # average SCUpgradeReq mshr miss latency 2185system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14925.415311 # average SCUpgradeReq mshr miss latency 2186system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency 2187system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 2188system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37833.451748 # average ReadExReq mshr miss latency 2189system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37833.451748 # average ReadExReq mshr miss latency 2190system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34186.842843 # average ReadCleanReq mshr miss latency 2191system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34186.842843 # average ReadCleanReq mshr miss latency 2192system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18662.386039 # average ReadSharedReq mshr miss latency 2193system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18662.386039 # average ReadSharedReq mshr miss latency 2194system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19880.487805 # average overall mshr miss latency 2195system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13857.142857 # average overall mshr miss latency 2196system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34186.842843 # average overall mshr miss latency 2197system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24742.762058 # average overall mshr miss latency 2198system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26733.993569 # average overall mshr miss latency 2199system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19880.487805 # average overall mshr miss latency 2200system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13857.142857 # average overall mshr miss latency 2201system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34186.842843 # average overall mshr miss latency 2202system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24742.762058 # average overall mshr miss latency 2203system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37324.744513 # average overall mshr miss latency 2204system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28108.097146 # average overall mshr miss latency 2205system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90593.750000 # average ReadReq mshr uncacheable latency 2206system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164860.717756 # average ReadReq mshr uncacheable latency 2207system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164287.780686 # average ReadReq mshr uncacheable latency 2208system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90593.750000 # average overall mshr uncacheable latency 2209system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90877.152369 # average overall mshr uncacheable latency 2210system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90875.943001 # average overall mshr uncacheable latency 2211system.cpu1.toL2Bus.snoop_filter.tot_requests 2165902 # Total number of requests made to the snoop filter. 2212system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1090398 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2213system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2214system.cpu1.toL2Bus.snoop_filter.tot_snoops 115909 # Total number of snoops made to the snoop filter. 2215system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 108045 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2216system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 7864 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2217system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 2218system.cpu1.toL2Bus.trans_dist::ReadReq 44859 # Transaction distribution 2219system.cpu1.toL2Bus.trans_dist::ReadResp 1106447 # Transaction distribution 2220system.cpu1.toL2Bus.trans_dist::WriteReq 11728 # Transaction distribution 2221system.cpu1.toL2Bus.trans_dist::WriteResp 11728 # Transaction distribution 2222system.cpu1.toL2Bus.trans_dist::WritebackDirty 126621 # Transaction distribution 2223system.cpu1.toL2Bus.trans_dist::WritebackClean 935252 # Transaction distribution 2224system.cpu1.toL2Bus.trans_dist::CleanEvict 26571 # Transaction distribution 2225system.cpu1.toL2Bus.trans_dist::HardPFReq 23763 # Transaction distribution 2226system.cpu1.toL2Bus.trans_dist::UpgradeReq 71775 # Transaction distribution 2227system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41777 # Transaction distribution 2228system.cpu1.toL2Bus.trans_dist::UpgradeResp 84685 # Transaction distribution 2229system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution 2230system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 31 # Transaction distribution 2231system.cpu1.toL2Bus.trans_dist::ReadExReq 58060 # Transaction distribution 2232system.cpu1.toL2Bus.trans_dist::ReadExResp 55427 # Transaction distribution 2233system.cpu1.toL2Bus.trans_dist::ReadCleanReq 873387 # Transaction distribution 2234system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263309 # Transaction distribution 2235system.cpu1.toL2Bus.trans_dist::InvalidateReq 71 # Transaction distribution 2236system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2619873 # Packet count per connected master and slave (bytes) 2237system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 793002 # Packet count per connected master and slave (bytes) 2238system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6834 # Packet count per connected master and slave (bytes) 2239system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50653 # Packet count per connected master and slave (bytes) 2240system.cpu1.toL2Bus.pkt_count::total 3470362 # Packet count per connected master and slave (bytes) 2241system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 111767936 # Cumulative packet size per connected master and slave (bytes) 2242system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25786238 # Cumulative packet size per connected master and slave (bytes) 2243system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11508 # Cumulative packet size per connected master and slave (bytes) 2244system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 97076 # Cumulative packet size per connected master and slave (bytes) 2245system.cpu1.toL2Bus.pkt_size::total 137662758 # Cumulative packet size per connected master and slave (bytes) 2246system.cpu1.toL2Bus.snoops 338759 # Total snoops (count) 2247system.cpu1.toL2Bus.snoopTraffic 4674348 # Total snoop traffic (bytes) 2248system.cpu1.toL2Bus.snoop_fanout::samples 1446654 # Request fanout histogram 2249system.cpu1.toL2Bus.snoop_fanout::mean 0.103615 # Request fanout histogram 2250system.cpu1.toL2Bus.snoop_fanout::stdev 0.322104 # Request fanout histogram 2251system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2252system.cpu1.toL2Bus.snoop_fanout::0 1304623 90.18% 90.18% # Request fanout histogram 2253system.cpu1.toL2Bus.snoop_fanout::1 134167 9.27% 99.46% # Request fanout histogram 2254system.cpu1.toL2Bus.snoop_fanout::2 7864 0.54% 100.00% # Request fanout histogram 2255system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2256system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2257system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2258system.cpu1.toL2Bus.snoop_fanout::total 1446654 # Request fanout histogram 2259system.cpu1.toL2Bus.reqLayer0.occupancy 2144021494 # Layer occupancy (ticks) 2260system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2261system.cpu1.toL2Bus.snoopLayer0.occupancy 78336814 # Layer occupancy (ticks) 2262system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2263system.cpu1.toL2Bus.respLayer0.occupancy 1310300396 # Layer occupancy (ticks) 2264system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2265system.cpu1.toL2Bus.respLayer1.occupancy 351676729 # Layer occupancy (ticks) 2266system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2267system.cpu1.toL2Bus.respLayer2.occupancy 3959994 # Layer occupancy (ticks) 2268system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2269system.cpu1.toL2Bus.respLayer3.occupancy 26397473 # Layer occupancy (ticks) 2270system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2271system.iobus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 2272system.iobus.trans_dist::ReadReq 31009 # Transaction distribution 2273system.iobus.trans_dist::ReadResp 31009 # Transaction distribution 2274system.iobus.trans_dist::WriteReq 59424 # Transaction distribution 2275system.iobus.trans_dist::WriteResp 59424 # Transaction distribution 2276system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes) 2277system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2278system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2279system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2280system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2281system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2282system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2283system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2284system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2285system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2286system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2287system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2288system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2289system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2290system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2291system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2292system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2293system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2294system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2295system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes) 2296system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) 2297system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) 2298system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) 2299system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes) 2300system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2301system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2302system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2303system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2304system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2305system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2306system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2307system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2308system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2309system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2310system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2311system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2312system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2313system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2314system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2315system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2316system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2317system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2318system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes) 2319system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) 2320system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) 2321system.iobus.pkt_size::total 2483988 # Cumulative packet size per connected master and slave (bytes) 2322system.iobus.reqLayer0.occupancy 48425501 # Layer occupancy (ticks) 2323system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2324system.iobus.reqLayer1.occupancy 110500 # Layer occupancy (ticks) 2325system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2326system.iobus.reqLayer2.occupancy 324500 # Layer occupancy (ticks) 2327system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2328system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) 2329system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2330system.iobus.reqLayer4.occupancy 12500 # Layer occupancy (ticks) 2331system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2332system.iobus.reqLayer7.occupancy 88500 # Layer occupancy (ticks) 2333system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2334system.iobus.reqLayer8.occupancy 621000 # Layer occupancy (ticks) 2335system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2336system.iobus.reqLayer10.occupancy 19500 # Layer occupancy (ticks) 2337system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2338system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) 2339system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2340system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 2341system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2342system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 2343system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2344system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks) 2345system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2346system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) 2347system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2348system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 2349system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2350system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2351system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2352system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2353system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2354system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) 2355system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2356system.iobus.reqLayer23.occupancy 6370500 # Layer occupancy (ticks) 2357system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2358system.iobus.reqLayer24.occupancy 39055001 # Layer occupancy (ticks) 2359system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2360system.iobus.reqLayer25.occupancy 187730317 # Layer occupancy (ticks) 2361system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2362system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks) 2363system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2364system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) 2365system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2366system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 2367system.iocache.tags.replacements 36449 # number of replacements 2368system.iocache.tags.tagsinuse 14.472713 # Cycle average of tags in use 2369system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2370system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. 2371system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2372system.iocache.tags.warmup_cycle 271902155000 # Cycle when the warmup percentage was hit. 2373system.iocache.tags.occ_blocks::realview.ide 14.472713 # Average occupied blocks per requestor 2374system.iocache.tags.occ_percent::realview.ide 0.904545 # Average percentage of cache occupancy 2375system.iocache.tags.occ_percent::total 0.904545 # Average percentage of cache occupancy 2376system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2377system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2378system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2379system.iocache.tags.tag_accesses 328203 # Number of tag accesses 2380system.iocache.tags.data_accesses 328203 # Number of data accesses 2381system.iocache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 2382system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses 2383system.iocache.ReadReq_misses::total 243 # number of ReadReq misses 2384system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2385system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2386system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses 2387system.iocache.demand_misses::total 36467 # number of demand (read+write) misses 2388system.iocache.overall_misses::realview.ide 36467 # number of overall misses 2389system.iocache.overall_misses::total 36467 # number of overall misses 2390system.iocache.ReadReq_miss_latency::realview.ide 32482877 # number of ReadReq miss cycles 2391system.iocache.ReadReq_miss_latency::total 32482877 # number of ReadReq miss cycles 2392system.iocache.WriteLineReq_miss_latency::realview.ide 4347292440 # number of WriteLineReq miss cycles 2393system.iocache.WriteLineReq_miss_latency::total 4347292440 # number of WriteLineReq miss cycles 2394system.iocache.demand_miss_latency::realview.ide 4379775317 # number of demand (read+write) miss cycles 2395system.iocache.demand_miss_latency::total 4379775317 # number of demand (read+write) miss cycles 2396system.iocache.overall_miss_latency::realview.ide 4379775317 # number of overall miss cycles 2397system.iocache.overall_miss_latency::total 4379775317 # number of overall miss cycles 2398system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) 2399system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) 2400system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2401system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2402system.iocache.demand_accesses::realview.ide 36467 # number of demand (read+write) accesses 2403system.iocache.demand_accesses::total 36467 # number of demand (read+write) accesses 2404system.iocache.overall_accesses::realview.ide 36467 # number of overall (read+write) accesses 2405system.iocache.overall_accesses::total 36467 # number of overall (read+write) accesses 2406system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2407system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2408system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2409system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2410system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2411system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2412system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2413system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2414system.iocache.ReadReq_avg_miss_latency::realview.ide 133674.390947 # average ReadReq miss latency 2415system.iocache.ReadReq_avg_miss_latency::total 133674.390947 # average ReadReq miss latency 2416system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120011.385822 # average WriteLineReq miss latency 2417system.iocache.WriteLineReq_avg_miss_latency::total 120011.385822 # average WriteLineReq miss latency 2418system.iocache.demand_avg_miss_latency::realview.ide 120102.430060 # average overall miss latency 2419system.iocache.demand_avg_miss_latency::total 120102.430060 # average overall miss latency 2420system.iocache.overall_avg_miss_latency::realview.ide 120102.430060 # average overall miss latency 2421system.iocache.overall_avg_miss_latency::total 120102.430060 # average overall miss latency 2422system.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked 2423system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2424system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked 2425system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2426system.iocache.avg_blocked_cycles::no_mshrs 3.500000 # average number of cycles each access was blocked 2427system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2428system.iocache.writebacks::writebacks 36206 # number of writebacks 2429system.iocache.writebacks::total 36206 # number of writebacks 2430system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses 2431system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses 2432system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2433system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2434system.iocache.demand_mshr_misses::realview.ide 36467 # number of demand (read+write) MSHR misses 2435system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses 2436system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses 2437system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses 2438system.iocache.ReadReq_mshr_miss_latency::realview.ide 20332877 # number of ReadReq MSHR miss cycles 2439system.iocache.ReadReq_mshr_miss_latency::total 20332877 # number of ReadReq MSHR miss cycles 2440system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2534226880 # number of WriteLineReq MSHR miss cycles 2441system.iocache.WriteLineReq_mshr_miss_latency::total 2534226880 # number of WriteLineReq MSHR miss cycles 2442system.iocache.demand_mshr_miss_latency::realview.ide 2554559757 # number of demand (read+write) MSHR miss cycles 2443system.iocache.demand_mshr_miss_latency::total 2554559757 # number of demand (read+write) MSHR miss cycles 2444system.iocache.overall_mshr_miss_latency::realview.ide 2554559757 # number of overall MSHR miss cycles 2445system.iocache.overall_mshr_miss_latency::total 2554559757 # number of overall MSHR miss cycles 2446system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2447system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2448system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2449system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2450system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2451system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2452system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2453system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2454system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 83674.390947 # average ReadReq mshr miss latency 2455system.iocache.ReadReq_avg_mshr_miss_latency::total 83674.390947 # average ReadReq mshr miss latency 2456system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69959.885159 # average WriteLineReq mshr miss latency 2457system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69959.885159 # average WriteLineReq mshr miss latency 2458system.iocache.demand_avg_mshr_miss_latency::realview.ide 70051.272575 # average overall mshr miss latency 2459system.iocache.demand_avg_mshr_miss_latency::total 70051.272575 # average overall mshr miss latency 2460system.iocache.overall_avg_mshr_miss_latency::realview.ide 70051.272575 # average overall mshr miss latency 2461system.iocache.overall_avg_mshr_miss_latency::total 70051.272575 # average overall mshr miss latency 2462system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 2463system.l2c.tags.replacements 143599 # number of replacements 2464system.l2c.tags.tagsinuse 65154.346859 # Cycle average of tags in use 2465system.l2c.tags.total_refs 605481 # Total number of references to valid blocks. 2466system.l2c.tags.sampled_refs 209069 # Sample count of references to valid blocks. 2467system.l2c.tags.avg_refs 2.896082 # Average number of references to valid blocks. 2468system.l2c.tags.warmup_cycle 94462980000 # Cycle when the warmup percentage was hit. 2469system.l2c.tags.occ_blocks::writebacks 6720.710891 # Average occupied blocks per requestor 2470system.l2c.tags.occ_blocks::cpu0.dtb.walker 87.363500 # Average occupied blocks per requestor 2471system.l2c.tags.occ_blocks::cpu0.itb.walker 0.029896 # Average occupied blocks per requestor 2472system.l2c.tags.occ_blocks::cpu0.inst 8711.779777 # Average occupied blocks per requestor 2473system.l2c.tags.occ_blocks::cpu0.data 6725.180439 # Average occupied blocks per requestor 2474system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34970.113845 # Average occupied blocks per requestor 2475system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.660518 # Average occupied blocks per requestor 2476system.l2c.tags.occ_blocks::cpu1.inst 2224.966255 # Average occupied blocks per requestor 2477system.l2c.tags.occ_blocks::cpu1.data 3446.409233 # Average occupied blocks per requestor 2478system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2253.132505 # Average occupied blocks per requestor 2479system.l2c.tags.occ_percent::writebacks 0.102550 # Average percentage of cache occupancy 2480system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001333 # Average percentage of cache occupancy 2481system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 2482system.l2c.tags.occ_percent::cpu0.inst 0.132931 # Average percentage of cache occupancy 2483system.l2c.tags.occ_percent::cpu0.data 0.102618 # Average percentage of cache occupancy 2484system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.533602 # Average percentage of cache occupancy 2485system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000224 # Average percentage of cache occupancy 2486system.l2c.tags.occ_percent::cpu1.inst 0.033950 # Average percentage of cache occupancy 2487system.l2c.tags.occ_percent::cpu1.data 0.052588 # Average percentage of cache occupancy 2488system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034380 # Average percentage of cache occupancy 2489system.l2c.tags.occ_percent::total 0.994176 # Average percentage of cache occupancy 2490system.l2c.tags.occ_task_id_blocks::1022 32778 # Occupied blocks per task id 2491system.l2c.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id 2492system.l2c.tags.occ_task_id_blocks::1024 32633 # Occupied blocks per task id 2493system.l2c.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id 2494system.l2c.tags.age_task_id_blocks_1022::3 5072 # Occupied blocks per task id 2495system.l2c.tags.age_task_id_blocks_1022::4 27569 # Occupied blocks per task id 2496system.l2c.tags.age_task_id_blocks_1023::4 59 # Occupied blocks per task id 2497system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 2498system.l2c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 2499system.l2c.tags.age_task_id_blocks_1024::2 123 # Occupied blocks per task id 2500system.l2c.tags.age_task_id_blocks_1024::3 1691 # Occupied blocks per task id 2501system.l2c.tags.age_task_id_blocks_1024::4 30817 # Occupied blocks per task id 2502system.l2c.tags.occ_task_id_percent::1022 0.500153 # Percentage of cache occupancy per task id 2503system.l2c.tags.occ_task_id_percent::1023 0.000900 # Percentage of cache occupancy per task id 2504system.l2c.tags.occ_task_id_percent::1024 0.497940 # Percentage of cache occupancy per task id 2505system.l2c.tags.tag_accesses 6803015 # Number of tag accesses 2506system.l2c.tags.data_accesses 6803015 # Number of data accesses 2507system.l2c.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 2508system.l2c.WritebackDirty_hits::writebacks 266286 # number of WritebackDirty hits 2509system.l2c.WritebackDirty_hits::total 266286 # number of WritebackDirty hits 2510system.l2c.UpgradeReq_hits::cpu0.data 43645 # number of UpgradeReq hits 2511system.l2c.UpgradeReq_hits::cpu1.data 4461 # number of UpgradeReq hits 2512system.l2c.UpgradeReq_hits::total 48106 # number of UpgradeReq hits 2513system.l2c.SCUpgradeReq_hits::cpu0.data 3017 # number of SCUpgradeReq hits 2514system.l2c.SCUpgradeReq_hits::cpu1.data 2129 # number of SCUpgradeReq hits 2515system.l2c.SCUpgradeReq_hits::total 5146 # number of SCUpgradeReq hits 2516system.l2c.ReadExReq_hits::cpu0.data 4448 # number of ReadExReq hits 2517system.l2c.ReadExReq_hits::cpu1.data 1231 # number of ReadExReq hits 2518system.l2c.ReadExReq_hits::total 5679 # number of ReadExReq hits 2519system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 477 # number of ReadSharedReq hits 2520system.l2c.ReadSharedReq_hits::cpu0.itb.walker 86 # number of ReadSharedReq hits 2521system.l2c.ReadSharedReq_hits::cpu0.inst 72650 # number of ReadSharedReq hits 2522system.l2c.ReadSharedReq_hits::cpu0.data 65777 # number of ReadSharedReq hits 2523system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 48761 # number of ReadSharedReq hits 2524system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 80 # number of ReadSharedReq hits 2525system.l2c.ReadSharedReq_hits::cpu1.itb.walker 9 # number of ReadSharedReq hits 2526system.l2c.ReadSharedReq_hits::cpu1.inst 24965 # number of ReadSharedReq hits 2527system.l2c.ReadSharedReq_hits::cpu1.data 8445 # number of ReadSharedReq hits 2528system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3652 # number of ReadSharedReq hits 2529system.l2c.ReadSharedReq_hits::total 224902 # number of ReadSharedReq hits 2530system.l2c.demand_hits::cpu0.dtb.walker 477 # number of demand (read+write) hits 2531system.l2c.demand_hits::cpu0.itb.walker 86 # number of demand (read+write) hits 2532system.l2c.demand_hits::cpu0.inst 72650 # number of demand (read+write) hits 2533system.l2c.demand_hits::cpu0.data 70225 # number of demand (read+write) hits 2534system.l2c.demand_hits::cpu0.l2cache.prefetcher 48761 # number of demand (read+write) hits 2535system.l2c.demand_hits::cpu1.dtb.walker 80 # number of demand (read+write) hits 2536system.l2c.demand_hits::cpu1.itb.walker 9 # number of demand (read+write) hits 2537system.l2c.demand_hits::cpu1.inst 24965 # number of demand (read+write) hits 2538system.l2c.demand_hits::cpu1.data 9676 # number of demand (read+write) hits 2539system.l2c.demand_hits::cpu1.l2cache.prefetcher 3652 # number of demand (read+write) hits 2540system.l2c.demand_hits::total 230581 # number of demand (read+write) hits 2541system.l2c.overall_hits::cpu0.dtb.walker 477 # number of overall hits 2542system.l2c.overall_hits::cpu0.itb.walker 86 # number of overall hits 2543system.l2c.overall_hits::cpu0.inst 72650 # number of overall hits 2544system.l2c.overall_hits::cpu0.data 70225 # number of overall hits 2545system.l2c.overall_hits::cpu0.l2cache.prefetcher 48761 # number of overall hits 2546system.l2c.overall_hits::cpu1.dtb.walker 80 # number of overall hits 2547system.l2c.overall_hits::cpu1.itb.walker 9 # number of overall hits 2548system.l2c.overall_hits::cpu1.inst 24965 # number of overall hits 2549system.l2c.overall_hits::cpu1.data 9676 # number of overall hits 2550system.l2c.overall_hits::cpu1.l2cache.prefetcher 3652 # number of overall hits 2551system.l2c.overall_hits::total 230581 # number of overall hits 2552system.l2c.UpgradeReq_misses::cpu0.data 459 # number of UpgradeReq misses 2553system.l2c.UpgradeReq_misses::cpu1.data 178 # number of UpgradeReq misses 2554system.l2c.UpgradeReq_misses::total 637 # number of UpgradeReq misses 2555system.l2c.SCUpgradeReq_misses::cpu0.data 57 # number of SCUpgradeReq misses 2556system.l2c.SCUpgradeReq_misses::cpu1.data 62 # number of SCUpgradeReq misses 2557system.l2c.SCUpgradeReq_misses::total 119 # number of SCUpgradeReq misses 2558system.l2c.ReadExReq_misses::cpu0.data 11423 # number of ReadExReq misses 2559system.l2c.ReadExReq_misses::cpu1.data 8564 # number of ReadExReq misses 2560system.l2c.ReadExReq_misses::total 19987 # number of ReadExReq misses 2561system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 145 # number of ReadSharedReq misses 2562system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses 2563system.l2c.ReadSharedReq_misses::cpu0.inst 22738 # number of ReadSharedReq misses 2564system.l2c.ReadSharedReq_misses::cpu0.data 9967 # number of ReadSharedReq misses 2565system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134498 # number of ReadSharedReq misses 2566system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 20 # number of ReadSharedReq misses 2567system.l2c.ReadSharedReq_misses::cpu1.inst 3567 # number of ReadSharedReq misses 2568system.l2c.ReadSharedReq_misses::cpu1.data 1751 # number of ReadSharedReq misses 2569system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5084 # number of ReadSharedReq misses 2570system.l2c.ReadSharedReq_misses::total 177771 # number of ReadSharedReq misses 2571system.l2c.demand_misses::cpu0.dtb.walker 145 # number of demand (read+write) misses 2572system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses 2573system.l2c.demand_misses::cpu0.inst 22738 # number of demand (read+write) misses 2574system.l2c.demand_misses::cpu0.data 21390 # number of demand (read+write) misses 2575system.l2c.demand_misses::cpu0.l2cache.prefetcher 134498 # number of demand (read+write) misses 2576system.l2c.demand_misses::cpu1.dtb.walker 20 # number of demand (read+write) misses 2577system.l2c.demand_misses::cpu1.inst 3567 # number of demand (read+write) misses 2578system.l2c.demand_misses::cpu1.data 10315 # number of demand (read+write) misses 2579system.l2c.demand_misses::cpu1.l2cache.prefetcher 5084 # number of demand (read+write) misses 2580system.l2c.demand_misses::total 197758 # number of demand (read+write) misses 2581system.l2c.overall_misses::cpu0.dtb.walker 145 # number of overall misses 2582system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses 2583system.l2c.overall_misses::cpu0.inst 22738 # number of overall misses 2584system.l2c.overall_misses::cpu0.data 21390 # number of overall misses 2585system.l2c.overall_misses::cpu0.l2cache.prefetcher 134498 # number of overall misses 2586system.l2c.overall_misses::cpu1.dtb.walker 20 # number of overall misses 2587system.l2c.overall_misses::cpu1.inst 3567 # number of overall misses 2588system.l2c.overall_misses::cpu1.data 10315 # number of overall misses 2589system.l2c.overall_misses::cpu1.l2cache.prefetcher 5084 # number of overall misses 2590system.l2c.overall_misses::total 197758 # number of overall misses 2591system.l2c.UpgradeReq_miss_latency::cpu0.data 8555500 # number of UpgradeReq miss cycles 2592system.l2c.UpgradeReq_miss_latency::cpu1.data 760000 # number of UpgradeReq miss cycles 2593system.l2c.UpgradeReq_miss_latency::total 9315500 # number of UpgradeReq miss cycles 2594system.l2c.SCUpgradeReq_miss_latency::cpu0.data 567000 # number of SCUpgradeReq miss cycles 2595system.l2c.SCUpgradeReq_miss_latency::cpu1.data 122000 # number of SCUpgradeReq miss cycles 2596system.l2c.SCUpgradeReq_miss_latency::total 689000 # number of SCUpgradeReq miss cycles 2597system.l2c.ReadExReq_miss_latency::cpu0.data 1593574000 # number of ReadExReq miss cycles 2598system.l2c.ReadExReq_miss_latency::cpu1.data 815318500 # number of ReadExReq miss cycles 2599system.l2c.ReadExReq_miss_latency::total 2408892500 # number of ReadExReq miss cycles 2600system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 22107500 # number of ReadSharedReq miss cycles 2601system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 90000 # number of ReadSharedReq miss cycles 2602system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2317227000 # number of ReadSharedReq miss cycles 2603system.l2c.ReadSharedReq_miss_latency::cpu0.data 1217018500 # number of ReadSharedReq miss cycles 2604system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 16177990963 # number of ReadSharedReq miss cycles 2605system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 4552500 # number of ReadSharedReq miss cycles 2606system.l2c.ReadSharedReq_miss_latency::cpu1.inst 377306500 # number of ReadSharedReq miss cycles 2607system.l2c.ReadSharedReq_miss_latency::cpu1.data 262293500 # number of ReadSharedReq miss cycles 2608system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 655902831 # number of ReadSharedReq miss cycles 2609system.l2c.ReadSharedReq_miss_latency::total 21034489294 # number of ReadSharedReq miss cycles 2610system.l2c.demand_miss_latency::cpu0.dtb.walker 22107500 # number of demand (read+write) miss cycles 2611system.l2c.demand_miss_latency::cpu0.itb.walker 90000 # number of demand (read+write) miss cycles 2612system.l2c.demand_miss_latency::cpu0.inst 2317227000 # number of demand (read+write) miss cycles 2613system.l2c.demand_miss_latency::cpu0.data 2810592500 # number of demand (read+write) miss cycles 2614system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 16177990963 # number of demand (read+write) miss cycles 2615system.l2c.demand_miss_latency::cpu1.dtb.walker 4552500 # number of demand (read+write) miss cycles 2616system.l2c.demand_miss_latency::cpu1.inst 377306500 # number of demand (read+write) miss cycles 2617system.l2c.demand_miss_latency::cpu1.data 1077612000 # number of demand (read+write) miss cycles 2618system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 655902831 # number of demand (read+write) miss cycles 2619system.l2c.demand_miss_latency::total 23443381794 # number of demand (read+write) miss cycles 2620system.l2c.overall_miss_latency::cpu0.dtb.walker 22107500 # number of overall miss cycles 2621system.l2c.overall_miss_latency::cpu0.itb.walker 90000 # number of overall miss cycles 2622system.l2c.overall_miss_latency::cpu0.inst 2317227000 # number of overall miss cycles 2623system.l2c.overall_miss_latency::cpu0.data 2810592500 # number of overall miss cycles 2624system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 16177990963 # number of overall miss cycles 2625system.l2c.overall_miss_latency::cpu1.dtb.walker 4552500 # number of overall miss cycles 2626system.l2c.overall_miss_latency::cpu1.inst 377306500 # number of overall miss cycles 2627system.l2c.overall_miss_latency::cpu1.data 1077612000 # number of overall miss cycles 2628system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 655902831 # number of overall miss cycles 2629system.l2c.overall_miss_latency::total 23443381794 # number of overall miss cycles 2630system.l2c.WritebackDirty_accesses::writebacks 266286 # number of WritebackDirty accesses(hits+misses) 2631system.l2c.WritebackDirty_accesses::total 266286 # number of WritebackDirty accesses(hits+misses) 2632system.l2c.UpgradeReq_accesses::cpu0.data 44104 # number of UpgradeReq accesses(hits+misses) 2633system.l2c.UpgradeReq_accesses::cpu1.data 4639 # number of UpgradeReq accesses(hits+misses) 2634system.l2c.UpgradeReq_accesses::total 48743 # number of UpgradeReq accesses(hits+misses) 2635system.l2c.SCUpgradeReq_accesses::cpu0.data 3074 # number of SCUpgradeReq accesses(hits+misses) 2636system.l2c.SCUpgradeReq_accesses::cpu1.data 2191 # number of SCUpgradeReq accesses(hits+misses) 2637system.l2c.SCUpgradeReq_accesses::total 5265 # number of SCUpgradeReq accesses(hits+misses) 2638system.l2c.ReadExReq_accesses::cpu0.data 15871 # number of ReadExReq accesses(hits+misses) 2639system.l2c.ReadExReq_accesses::cpu1.data 9795 # number of ReadExReq accesses(hits+misses) 2640system.l2c.ReadExReq_accesses::total 25666 # number of ReadExReq accesses(hits+misses) 2641system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 622 # number of ReadSharedReq accesses(hits+misses) 2642system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 87 # number of ReadSharedReq accesses(hits+misses) 2643system.l2c.ReadSharedReq_accesses::cpu0.inst 95388 # number of ReadSharedReq accesses(hits+misses) 2644system.l2c.ReadSharedReq_accesses::cpu0.data 75744 # number of ReadSharedReq accesses(hits+misses) 2645system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 183259 # number of ReadSharedReq accesses(hits+misses) 2646system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 100 # number of ReadSharedReq accesses(hits+misses) 2647system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 9 # number of ReadSharedReq accesses(hits+misses) 2648system.l2c.ReadSharedReq_accesses::cpu1.inst 28532 # number of ReadSharedReq accesses(hits+misses) 2649system.l2c.ReadSharedReq_accesses::cpu1.data 10196 # number of ReadSharedReq accesses(hits+misses) 2650system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8736 # number of ReadSharedReq accesses(hits+misses) 2651system.l2c.ReadSharedReq_accesses::total 402673 # number of ReadSharedReq accesses(hits+misses) 2652system.l2c.demand_accesses::cpu0.dtb.walker 622 # number of demand (read+write) accesses 2653system.l2c.demand_accesses::cpu0.itb.walker 87 # number of demand (read+write) accesses 2654system.l2c.demand_accesses::cpu0.inst 95388 # number of demand (read+write) accesses 2655system.l2c.demand_accesses::cpu0.data 91615 # number of demand (read+write) accesses 2656system.l2c.demand_accesses::cpu0.l2cache.prefetcher 183259 # number of demand (read+write) accesses 2657system.l2c.demand_accesses::cpu1.dtb.walker 100 # number of demand (read+write) accesses 2658system.l2c.demand_accesses::cpu1.itb.walker 9 # number of demand (read+write) accesses 2659system.l2c.demand_accesses::cpu1.inst 28532 # number of demand (read+write) accesses 2660system.l2c.demand_accesses::cpu1.data 19991 # number of demand (read+write) accesses 2661system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8736 # number of demand (read+write) accesses 2662system.l2c.demand_accesses::total 428339 # number of demand (read+write) accesses 2663system.l2c.overall_accesses::cpu0.dtb.walker 622 # number of overall (read+write) accesses 2664system.l2c.overall_accesses::cpu0.itb.walker 87 # number of overall (read+write) accesses 2665system.l2c.overall_accesses::cpu0.inst 95388 # number of overall (read+write) accesses 2666system.l2c.overall_accesses::cpu0.data 91615 # number of overall (read+write) accesses 2667system.l2c.overall_accesses::cpu0.l2cache.prefetcher 183259 # number of overall (read+write) accesses 2668system.l2c.overall_accesses::cpu1.dtb.walker 100 # number of overall (read+write) accesses 2669system.l2c.overall_accesses::cpu1.itb.walker 9 # number of overall (read+write) accesses 2670system.l2c.overall_accesses::cpu1.inst 28532 # number of overall (read+write) accesses 2671system.l2c.overall_accesses::cpu1.data 19991 # number of overall (read+write) accesses 2672system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8736 # number of overall (read+write) accesses 2673system.l2c.overall_accesses::total 428339 # number of overall (read+write) accesses 2674system.l2c.UpgradeReq_miss_rate::cpu0.data 0.010407 # miss rate for UpgradeReq accesses 2675system.l2c.UpgradeReq_miss_rate::cpu1.data 0.038370 # miss rate for UpgradeReq accesses 2676system.l2c.UpgradeReq_miss_rate::total 0.013069 # miss rate for UpgradeReq accesses 2677system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.018543 # miss rate for SCUpgradeReq accesses 2678system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.028298 # miss rate for SCUpgradeReq accesses 2679system.l2c.SCUpgradeReq_miss_rate::total 0.022602 # miss rate for SCUpgradeReq accesses 2680system.l2c.ReadExReq_miss_rate::cpu0.data 0.719740 # miss rate for ReadExReq accesses 2681system.l2c.ReadExReq_miss_rate::cpu1.data 0.874324 # miss rate for ReadExReq accesses 2682system.l2c.ReadExReq_miss_rate::total 0.778735 # miss rate for ReadExReq accesses 2683system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.233119 # miss rate for ReadSharedReq accesses 2684system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.011494 # miss rate for ReadSharedReq accesses 2685system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.238374 # miss rate for ReadSharedReq accesses 2686system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.131588 # miss rate for ReadSharedReq accesses 2687system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.733923 # miss rate for ReadSharedReq accesses 2688system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.200000 # miss rate for ReadSharedReq accesses 2689system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.125018 # miss rate for ReadSharedReq accesses 2690system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.171734 # miss rate for ReadSharedReq accesses 2691system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.581960 # miss rate for ReadSharedReq accesses 2692system.l2c.ReadSharedReq_miss_rate::total 0.441477 # miss rate for ReadSharedReq accesses 2693system.l2c.demand_miss_rate::cpu0.dtb.walker 0.233119 # miss rate for demand accesses 2694system.l2c.demand_miss_rate::cpu0.itb.walker 0.011494 # miss rate for demand accesses 2695system.l2c.demand_miss_rate::cpu0.inst 0.238374 # miss rate for demand accesses 2696system.l2c.demand_miss_rate::cpu0.data 0.233477 # miss rate for demand accesses 2697system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.733923 # miss rate for demand accesses 2698system.l2c.demand_miss_rate::cpu1.dtb.walker 0.200000 # miss rate for demand accesses 2699system.l2c.demand_miss_rate::cpu1.inst 0.125018 # miss rate for demand accesses 2700system.l2c.demand_miss_rate::cpu1.data 0.515982 # miss rate for demand accesses 2701system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.581960 # miss rate for demand accesses 2702system.l2c.demand_miss_rate::total 0.461686 # miss rate for demand accesses 2703system.l2c.overall_miss_rate::cpu0.dtb.walker 0.233119 # miss rate for overall accesses 2704system.l2c.overall_miss_rate::cpu0.itb.walker 0.011494 # miss rate for overall accesses 2705system.l2c.overall_miss_rate::cpu0.inst 0.238374 # miss rate for overall accesses 2706system.l2c.overall_miss_rate::cpu0.data 0.233477 # miss rate for overall accesses 2707system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.733923 # miss rate for overall accesses 2708system.l2c.overall_miss_rate::cpu1.dtb.walker 0.200000 # miss rate for overall accesses 2709system.l2c.overall_miss_rate::cpu1.inst 0.125018 # miss rate for overall accesses 2710system.l2c.overall_miss_rate::cpu1.data 0.515982 # miss rate for overall accesses 2711system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.581960 # miss rate for overall accesses 2712system.l2c.overall_miss_rate::total 0.461686 # miss rate for overall accesses 2713system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 18639.433551 # average UpgradeReq miss latency 2714system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4269.662921 # average UpgradeReq miss latency 2715system.l2c.UpgradeReq_avg_miss_latency::total 14624.018838 # average UpgradeReq miss latency 2716system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 9947.368421 # average SCUpgradeReq miss latency 2717system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1967.741935 # average SCUpgradeReq miss latency 2718system.l2c.SCUpgradeReq_avg_miss_latency::total 5789.915966 # average SCUpgradeReq miss latency 2719system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139505.734045 # average ReadExReq miss latency 2720system.l2c.ReadExReq_avg_miss_latency::cpu1.data 95203.000934 # average ReadExReq miss latency 2721system.l2c.ReadExReq_avg_miss_latency::total 120522.964927 # average ReadExReq miss latency 2722system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 152465.517241 # average ReadSharedReq miss latency 2723system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90000 # average ReadSharedReq miss latency 2724system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 101909.886534 # average ReadSharedReq miss latency 2725system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 122104.795826 # average ReadSharedReq miss latency 2726system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 120284.249305 # average ReadSharedReq miss latency 2727system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 227625 # average ReadSharedReq miss latency 2728system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 105776.983459 # average ReadSharedReq miss latency 2729system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 149796.402056 # average ReadSharedReq miss latency 2730system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 129013.145358 # average ReadSharedReq miss latency 2731system.l2c.ReadSharedReq_avg_miss_latency::total 118323.513363 # average ReadSharedReq miss latency 2732system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 152465.517241 # average overall miss latency 2733system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency 2734system.l2c.demand_avg_miss_latency::cpu0.inst 101909.886534 # average overall miss latency 2735system.l2c.demand_avg_miss_latency::cpu0.data 131397.498831 # average overall miss latency 2736system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 120284.249305 # average overall miss latency 2737system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 227625 # average overall miss latency 2738system.l2c.demand_avg_miss_latency::cpu1.inst 105776.983459 # average overall miss latency 2739system.l2c.demand_avg_miss_latency::cpu1.data 104470.382937 # average overall miss latency 2740system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 129013.145358 # average overall miss latency 2741system.l2c.demand_avg_miss_latency::total 118545.807472 # average overall miss latency 2742system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 152465.517241 # average overall miss latency 2743system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency 2744system.l2c.overall_avg_miss_latency::cpu0.inst 101909.886534 # average overall miss latency 2745system.l2c.overall_avg_miss_latency::cpu0.data 131397.498831 # average overall miss latency 2746system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 120284.249305 # average overall miss latency 2747system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 227625 # average overall miss latency 2748system.l2c.overall_avg_miss_latency::cpu1.inst 105776.983459 # average overall miss latency 2749system.l2c.overall_avg_miss_latency::cpu1.data 104470.382937 # average overall miss latency 2750system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 129013.145358 # average overall miss latency 2751system.l2c.overall_avg_miss_latency::total 118545.807472 # average overall miss latency 2752system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2753system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2754system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2755system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2756system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2757system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2758system.l2c.writebacks::writebacks 104081 # number of writebacks 2759system.l2c.writebacks::total 104081 # number of writebacks 2760system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits 2761system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 1 # number of ReadSharedReq MSHR hits 2762system.l2c.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits 2763system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits 2764system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits 2765system.l2c.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 2766system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits 2767system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits 2768system.l2c.overall_mshr_hits::total 6 # number of overall MSHR hits 2769system.l2c.CleanEvict_mshr_misses::writebacks 4309 # number of CleanEvict MSHR misses 2770system.l2c.CleanEvict_mshr_misses::total 4309 # number of CleanEvict MSHR misses 2771system.l2c.UpgradeReq_mshr_misses::cpu0.data 459 # number of UpgradeReq MSHR misses 2772system.l2c.UpgradeReq_mshr_misses::cpu1.data 178 # number of UpgradeReq MSHR misses 2773system.l2c.UpgradeReq_mshr_misses::total 637 # number of UpgradeReq MSHR misses 2774system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 57 # number of SCUpgradeReq MSHR misses 2775system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 62 # number of SCUpgradeReq MSHR misses 2776system.l2c.SCUpgradeReq_mshr_misses::total 119 # number of SCUpgradeReq MSHR misses 2777system.l2c.ReadExReq_mshr_misses::cpu0.data 11423 # number of ReadExReq MSHR misses 2778system.l2c.ReadExReq_mshr_misses::cpu1.data 8564 # number of ReadExReq MSHR misses 2779system.l2c.ReadExReq_mshr_misses::total 19987 # number of ReadExReq MSHR misses 2780system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 145 # number of ReadSharedReq MSHR misses 2781system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1 # number of ReadSharedReq MSHR misses 2782system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 22733 # number of ReadSharedReq MSHR misses 2783system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9967 # number of ReadSharedReq MSHR misses 2784system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134498 # number of ReadSharedReq MSHR misses 2785system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 20 # number of ReadSharedReq MSHR misses 2786system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 3566 # number of ReadSharedReq MSHR misses 2787system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1751 # number of ReadSharedReq MSHR misses 2788system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5084 # number of ReadSharedReq MSHR misses 2789system.l2c.ReadSharedReq_mshr_misses::total 177765 # number of ReadSharedReq MSHR misses 2790system.l2c.demand_mshr_misses::cpu0.dtb.walker 145 # number of demand (read+write) MSHR misses 2791system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses 2792system.l2c.demand_mshr_misses::cpu0.inst 22733 # number of demand (read+write) MSHR misses 2793system.l2c.demand_mshr_misses::cpu0.data 21390 # number of demand (read+write) MSHR misses 2794system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134498 # number of demand (read+write) MSHR misses 2795system.l2c.demand_mshr_misses::cpu1.dtb.walker 20 # number of demand (read+write) MSHR misses 2796system.l2c.demand_mshr_misses::cpu1.inst 3566 # number of demand (read+write) MSHR misses 2797system.l2c.demand_mshr_misses::cpu1.data 10315 # number of demand (read+write) MSHR misses 2798system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5084 # number of demand (read+write) MSHR misses 2799system.l2c.demand_mshr_misses::total 197752 # number of demand (read+write) MSHR misses 2800system.l2c.overall_mshr_misses::cpu0.dtb.walker 145 # number of overall MSHR misses 2801system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses 2802system.l2c.overall_mshr_misses::cpu0.inst 22733 # number of overall MSHR misses 2803system.l2c.overall_mshr_misses::cpu0.data 21390 # number of overall MSHR misses 2804system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134498 # number of overall MSHR misses 2805system.l2c.overall_mshr_misses::cpu1.dtb.walker 20 # number of overall MSHR misses 2806system.l2c.overall_mshr_misses::cpu1.inst 3566 # number of overall MSHR misses 2807system.l2c.overall_mshr_misses::cpu1.data 10315 # number of overall MSHR misses 2808system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5084 # number of overall MSHR misses 2809system.l2c.overall_mshr_misses::total 197752 # number of overall MSHR misses 2810system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable 2811system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20603 # number of ReadReq MSHR uncacheable 2812system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 2813system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14403 # number of ReadReq MSHR uncacheable 2814system.l2c.ReadReq_mshr_uncacheable::total 38395 # number of ReadReq MSHR uncacheable 2815system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19302 # number of WriteReq MSHR uncacheable 2816system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11728 # number of WriteReq MSHR uncacheable 2817system.l2c.WriteReq_mshr_uncacheable::total 31030 # number of WriteReq MSHR uncacheable 2818system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses 2819system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39905 # number of overall MSHR uncacheable misses 2820system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 2821system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26131 # number of overall MSHR uncacheable misses 2822system.l2c.overall_mshr_uncacheable_misses::total 69425 # number of overall MSHR uncacheable misses 2823system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 10236500 # number of UpgradeReq MSHR miss cycles 2824system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3909500 # number of UpgradeReq MSHR miss cycles 2825system.l2c.UpgradeReq_mshr_miss_latency::total 14146000 # number of UpgradeReq MSHR miss cycles 2826system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1509500 # number of SCUpgradeReq MSHR miss cycles 2827system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1453000 # number of SCUpgradeReq MSHR miss cycles 2828system.l2c.SCUpgradeReq_mshr_miss_latency::total 2962500 # number of SCUpgradeReq MSHR miss cycles 2829system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1479344000 # number of ReadExReq MSHR miss cycles 2830system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 729678500 # number of ReadExReq MSHR miss cycles 2831system.l2c.ReadExReq_mshr_miss_latency::total 2209022500 # number of ReadExReq MSHR miss cycles 2832system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 20657500 # number of ReadSharedReq MSHR miss cycles 2833system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 80000 # number of ReadSharedReq MSHR miss cycles 2834system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2089156001 # number of ReadSharedReq MSHR miss cycles 2835system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1117348500 # number of ReadSharedReq MSHR miss cycles 2836system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14833007471 # number of ReadSharedReq MSHR miss cycles 2837system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 4352500 # number of ReadSharedReq MSHR miss cycles 2838system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 341582500 # number of ReadSharedReq MSHR miss cycles 2839system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 244783001 # number of ReadSharedReq MSHR miss cycles 2840system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 605061833 # number of ReadSharedReq MSHR miss cycles 2841system.l2c.ReadSharedReq_mshr_miss_latency::total 19256029306 # number of ReadSharedReq MSHR miss cycles 2842system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 20657500 # number of demand (read+write) MSHR miss cycles 2843system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000 # number of demand (read+write) MSHR miss cycles 2844system.l2c.demand_mshr_miss_latency::cpu0.inst 2089156001 # number of demand (read+write) MSHR miss cycles 2845system.l2c.demand_mshr_miss_latency::cpu0.data 2596692500 # number of demand (read+write) MSHR miss cycles 2846system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14833007471 # number of demand (read+write) MSHR miss cycles 2847system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 4352500 # number of demand (read+write) MSHR miss cycles 2848system.l2c.demand_mshr_miss_latency::cpu1.inst 341582500 # number of demand (read+write) MSHR miss cycles 2849system.l2c.demand_mshr_miss_latency::cpu1.data 974461501 # number of demand (read+write) MSHR miss cycles 2850system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 605061833 # number of demand (read+write) MSHR miss cycles 2851system.l2c.demand_mshr_miss_latency::total 21465051806 # number of demand (read+write) MSHR miss cycles 2852system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 20657500 # number of overall MSHR miss cycles 2853system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 # number of overall MSHR miss cycles 2854system.l2c.overall_mshr_miss_latency::cpu0.inst 2089156001 # number of overall MSHR miss cycles 2855system.l2c.overall_mshr_miss_latency::cpu0.data 2596692500 # number of overall MSHR miss cycles 2856system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14833007471 # number of overall MSHR miss cycles 2857system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 4352500 # number of overall MSHR miss cycles 2858system.l2c.overall_mshr_miss_latency::cpu1.inst 341582500 # number of overall MSHR miss cycles 2859system.l2c.overall_mshr_miss_latency::cpu1.data 974461501 # number of overall MSHR miss cycles 2860system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 605061833 # number of overall MSHR miss cycles 2861system.l2c.overall_mshr_miss_latency::total 21465051806 # number of overall MSHR miss cycles 2862system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 228848500 # number of ReadReq MSHR uncacheable cycles 2863system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4075847000 # number of ReadReq MSHR uncacheable cycles 2864system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7794500 # number of ReadReq MSHR uncacheable cycles 2865system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2115657500 # number of ReadReq MSHR uncacheable cycles 2866system.l2c.ReadReq_mshr_uncacheable_latency::total 6428147500 # number of ReadReq MSHR uncacheable cycles 2867system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 228848500 # number of overall MSHR uncacheable cycles 2868system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4075847000 # number of overall MSHR uncacheable cycles 2869system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7794500 # number of overall MSHR uncacheable cycles 2870system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2115657500 # number of overall MSHR uncacheable cycles 2871system.l2c.overall_mshr_uncacheable_latency::total 6428147500 # number of overall MSHR uncacheable cycles 2872system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2873system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2874system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.010407 # mshr miss rate for UpgradeReq accesses 2875system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.038370 # mshr miss rate for UpgradeReq accesses 2876system.l2c.UpgradeReq_mshr_miss_rate::total 0.013069 # mshr miss rate for UpgradeReq accesses 2877system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.018543 # mshr miss rate for SCUpgradeReq accesses 2878system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.028298 # mshr miss rate for SCUpgradeReq accesses 2879system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.022602 # mshr miss rate for SCUpgradeReq accesses 2880system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.719740 # mshr miss rate for ReadExReq accesses 2881system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.874324 # mshr miss rate for ReadExReq accesses 2882system.l2c.ReadExReq_mshr_miss_rate::total 0.778735 # mshr miss rate for ReadExReq accesses 2883system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.233119 # mshr miss rate for ReadSharedReq accesses 2884system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for ReadSharedReq accesses 2885system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.238321 # mshr miss rate for ReadSharedReq accesses 2886system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.131588 # mshr miss rate for ReadSharedReq accesses 2887system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733923 # mshr miss rate for ReadSharedReq accesses 2888system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.200000 # mshr miss rate for ReadSharedReq accesses 2889system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.124982 # mshr miss rate for ReadSharedReq accesses 2890system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.171734 # mshr miss rate for ReadSharedReq accesses 2891system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581960 # mshr miss rate for ReadSharedReq accesses 2892system.l2c.ReadSharedReq_mshr_miss_rate::total 0.441462 # mshr miss rate for ReadSharedReq accesses 2893system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.233119 # mshr miss rate for demand accesses 2894system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for demand accesses 2895system.l2c.demand_mshr_miss_rate::cpu0.inst 0.238321 # mshr miss rate for demand accesses 2896system.l2c.demand_mshr_miss_rate::cpu0.data 0.233477 # mshr miss rate for demand accesses 2897system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733923 # mshr miss rate for demand accesses 2898system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.200000 # mshr miss rate for demand accesses 2899system.l2c.demand_mshr_miss_rate::cpu1.inst 0.124982 # mshr miss rate for demand accesses 2900system.l2c.demand_mshr_miss_rate::cpu1.data 0.515982 # mshr miss rate for demand accesses 2901system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581960 # mshr miss rate for demand accesses 2902system.l2c.demand_mshr_miss_rate::total 0.461672 # mshr miss rate for demand accesses 2903system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.233119 # mshr miss rate for overall accesses 2904system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for overall accesses 2905system.l2c.overall_mshr_miss_rate::cpu0.inst 0.238321 # mshr miss rate for overall accesses 2906system.l2c.overall_mshr_miss_rate::cpu0.data 0.233477 # mshr miss rate for overall accesses 2907system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733923 # mshr miss rate for overall accesses 2908system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.200000 # mshr miss rate for overall accesses 2909system.l2c.overall_mshr_miss_rate::cpu1.inst 0.124982 # mshr miss rate for overall accesses 2910system.l2c.overall_mshr_miss_rate::cpu1.data 0.515982 # mshr miss rate for overall accesses 2911system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581960 # mshr miss rate for overall accesses 2912system.l2c.overall_mshr_miss_rate::total 0.461672 # mshr miss rate for overall accesses 2913system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22301.742919 # average UpgradeReq mshr miss latency 2914system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21963.483146 # average UpgradeReq mshr miss latency 2915system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22207.221350 # average UpgradeReq mshr miss latency 2916system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26482.456140 # average SCUpgradeReq mshr miss latency 2917system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23435.483871 # average SCUpgradeReq mshr miss latency 2918system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24894.957983 # average SCUpgradeReq mshr miss latency 2919system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129505.734045 # average ReadExReq mshr miss latency 2920system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 85203.000934 # average ReadExReq mshr miss latency 2921system.l2c.ReadExReq_avg_mshr_miss_latency::total 110522.964927 # average ReadExReq mshr miss latency 2922system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 142465.517241 # average ReadSharedReq mshr miss latency 2923system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average ReadSharedReq mshr miss latency 2924system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 91899.705318 # average ReadSharedReq mshr miss latency 2925system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 112104.795826 # average ReadSharedReq mshr miss latency 2926system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110284.223342 # average ReadSharedReq mshr miss latency 2927system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 217625 # average ReadSharedReq mshr miss latency 2928system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 95788.698822 # average ReadSharedReq mshr miss latency 2929system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 139796.117076 # average ReadSharedReq mshr miss latency 2930system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119012.949056 # average ReadSharedReq mshr miss latency 2931system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108322.950558 # average ReadSharedReq mshr miss latency 2932system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 142465.517241 # average overall mshr miss latency 2933system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency 2934system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 91899.705318 # average overall mshr miss latency 2935system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121397.498831 # average overall mshr miss latency 2936system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110284.223342 # average overall mshr miss latency 2937system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 217625 # average overall mshr miss latency 2938system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 95788.698822 # average overall mshr miss latency 2939system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94470.334561 # average overall mshr miss latency 2940system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119012.949056 # average overall mshr miss latency 2941system.l2c.demand_avg_mshr_miss_latency::total 108545.308295 # average overall mshr miss latency 2942system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 142465.517241 # average overall mshr miss latency 2943system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency 2944system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 91899.705318 # average overall mshr miss latency 2945system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121397.498831 # average overall mshr miss latency 2946system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110284.223342 # average overall mshr miss latency 2947system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 217625 # average overall mshr miss latency 2948system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 95788.698822 # average overall mshr miss latency 2949system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94470.334561 # average overall mshr miss latency 2950system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119012.949056 # average overall mshr miss latency 2951system.l2c.overall_avg_mshr_miss_latency::total 108545.308295 # average overall mshr miss latency 2952system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average ReadReq mshr uncacheable latency 2953system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197827.840606 # average ReadReq mshr uncacheable latency 2954system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69593.750000 # average ReadReq mshr uncacheable latency 2955system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146890.057627 # average ReadReq mshr uncacheable latency 2956system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167421.474150 # average ReadReq mshr uncacheable latency 2957system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average overall mshr uncacheable latency 2958system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102138.754542 # average overall mshr uncacheable latency 2959system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69593.750000 # average overall mshr uncacheable latency 2960system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80963.510773 # average overall mshr uncacheable latency 2961system.l2c.overall_avg_mshr_uncacheable_latency::total 92591.249550 # average overall mshr uncacheable latency 2962system.membus.snoop_filter.tot_requests 513996 # Total number of requests made to the snoop filter. 2963system.membus.snoop_filter.hit_single_requests 285885 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2964system.membus.snoop_filter.hit_multi_requests 629 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2965system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2966system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2967system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2968system.membus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 2969system.membus.trans_dist::ReadReq 38395 # Transaction distribution 2970system.membus.trans_dist::ReadResp 216403 # Transaction distribution 2971system.membus.trans_dist::WriteReq 31030 # Transaction distribution 2972system.membus.trans_dist::WriteResp 31030 # Transaction distribution 2973system.membus.trans_dist::WritebackDirty 140287 # Transaction distribution 2974system.membus.trans_dist::CleanEvict 19048 # Transaction distribution 2975system.membus.trans_dist::UpgradeReq 61128 # Transaction distribution 2976system.membus.trans_dist::SCUpgradeReq 38691 # Transaction distribution 2977system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 2978system.membus.trans_dist::ReadExReq 40497 # Transaction distribution 2979system.membus.trans_dist::ReadExResp 19965 # Transaction distribution 2980system.membus.trans_dist::ReadSharedReq 178008 # Transaction distribution 2981system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2982system.membus.trans_dist::InvalidateResp 4238 # Transaction distribution 2983system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes) 2984system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) 2985system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14192 # Packet count per connected master and slave (bytes) 2986system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 655043 # Packet count per connected master and slave (bytes) 2987system.membus.pkt_count_system.l2c.mem_side::total 777209 # Packet count per connected master and slave (bytes) 2988system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72931 # Packet count per connected master and slave (bytes) 2989system.membus.pkt_count_system.iocache.mem_side::total 72931 # Packet count per connected master and slave (bytes) 2990system.membus.pkt_count::total 850140 # Packet count per connected master and slave (bytes) 2991system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes) 2992system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) 2993system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28384 # Cumulative packet size per connected master and slave (bytes) 2994system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19529832 # Cumulative packet size per connected master and slave (bytes) 2995system.membus.pkt_size_system.l2c.mem_side::total 19722372 # Cumulative packet size per connected master and slave (bytes) 2996system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 2997system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) 2998system.membus.pkt_size::total 22040516 # Cumulative packet size per connected master and slave (bytes) 2999system.membus.snoops 124379 # Total snoops (count) 3000system.membus.snoopTraffic 36224 # Total snoop traffic (bytes) 3001system.membus.snoop_fanout::samples 423974 # Request fanout histogram 3002system.membus.snoop_fanout::mean 0.011487 # Request fanout histogram 3003system.membus.snoop_fanout::stdev 0.106558 # Request fanout histogram 3004system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3005system.membus.snoop_fanout::0 419104 98.85% 98.85% # Request fanout histogram 3006system.membus.snoop_fanout::1 4870 1.15% 100.00% # Request fanout histogram 3007system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3008system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3009system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3010system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3011system.membus.snoop_fanout::total 423974 # Request fanout histogram 3012system.membus.reqLayer0.occupancy 95170998 # Layer occupancy (ticks) 3013system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3014system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) 3015system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3016system.membus.reqLayer2.occupancy 12519499 # Layer occupancy (ticks) 3017system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3018system.membus.reqLayer5.occupancy 1006886251 # Layer occupancy (ticks) 3019system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3020system.membus.respLayer2.occupancy 1152568025 # Layer occupancy (ticks) 3021system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3022system.membus.respLayer3.occupancy 6725047 # Layer occupancy (ticks) 3023system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3024system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3025system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3026system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3027system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3028system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3029system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3030system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3031system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3032system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3033system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3034system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3035system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3036system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3037system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3038system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3039system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3040system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3041system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3042system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3043system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3044system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3045system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3046system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3047system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3048system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3049system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3050system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3051system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3052system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3053system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3054system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3055system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3056system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3057system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3058system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3059system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3060system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3061system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3062system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3063system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3064system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3065system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3066system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3067system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3068system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3069system.realview.ethernet.droppedPackets 0 # number of packets dropped 3070system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3071system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3072system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3073system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3074system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3075system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3076system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3077system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3078system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3079system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3080system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3081system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3082system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3083system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3084system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3085system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3086system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3087system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3088system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3089system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3090system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3091system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3092system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3093system.toL2Bus.snoop_filter.tot_requests 1101165 # Total number of requests made to the snoop filter. 3094system.toL2Bus.snoop_filter.hit_single_requests 567136 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3095system.toL2Bus.snoop_filter.hit_multi_requests 209084 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3096system.toL2Bus.snoop_filter.tot_snoops 30878 # Total number of snoops made to the snoop filter. 3097system.toL2Bus.snoop_filter.hit_single_snoops 29463 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3098system.toL2Bus.snoop_filter.hit_multi_snoops 1415 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3099system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states 3100system.toL2Bus.trans_dist::ReadReq 38398 # Transaction distribution 3101system.toL2Bus.trans_dist::ReadResp 558656 # Transaction distribution 3102system.toL2Bus.trans_dist::WriteReq 31030 # Transaction distribution 3103system.toL2Bus.trans_dist::WriteResp 31030 # Transaction distribution 3104system.toL2Bus.trans_dist::WritebackDirty 370367 # Transaction distribution 3105system.toL2Bus.trans_dist::CleanEvict 149733 # Transaction distribution 3106system.toL2Bus.trans_dist::UpgradeReq 109212 # Transaction distribution 3107system.toL2Bus.trans_dist::SCUpgradeReq 43837 # Transaction distribution 3108system.toL2Bus.trans_dist::UpgradeResp 153049 # Transaction distribution 3109system.toL2Bus.trans_dist::SCUpgradeFailReq 31 # Transaction distribution 3110system.toL2Bus.trans_dist::UpgradeFailResp 31 # Transaction distribution 3111system.toL2Bus.trans_dist::ReadExReq 51538 # Transaction distribution 3112system.toL2Bus.trans_dist::ReadExResp 51538 # Transaction distribution 3113system.toL2Bus.trans_dist::ReadSharedReq 520262 # Transaction distribution 3114system.toL2Bus.trans_dist::InvalidateReq 4298 # Transaction distribution 3115system.toL2Bus.trans_dist::InvalidateResp 3081 # Transaction distribution 3116system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1372035 # Packet count per connected master and slave (bytes) 3117system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 353597 # Packet count per connected master and slave (bytes) 3118system.toL2Bus.pkt_count::total 1725632 # Packet count per connected master and slave (bytes) 3119system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 39251474 # Cumulative packet size per connected master and slave (bytes) 3120system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5647218 # Cumulative packet size per connected master and slave (bytes) 3121system.toL2Bus.pkt_size::total 44898692 # Cumulative packet size per connected master and slave (bytes) 3122system.toL2Bus.snoops 393768 # Total snoops (count) 3123system.toL2Bus.snoopTraffic 15844428 # Total snoop traffic (bytes) 3124system.toL2Bus.snoop_fanout::samples 942231 # Request fanout histogram 3125system.toL2Bus.snoop_fanout::mean 0.393753 # Request fanout histogram 3126system.toL2Bus.snoop_fanout::stdev 0.491645 # Request fanout histogram 3127system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3128system.toL2Bus.snoop_fanout::0 572640 60.77% 60.77% # Request fanout histogram 3129system.toL2Bus.snoop_fanout::1 368176 39.07% 99.85% # Request fanout histogram 3130system.toL2Bus.snoop_fanout::2 1415 0.15% 100.00% # Request fanout histogram 3131system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3132system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3133system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3134system.toL2Bus.snoop_fanout::total 942231 # Request fanout histogram 3135system.toL2Bus.reqLayer0.occupancy 939495440 # Layer occupancy (ticks) 3136system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3137system.toL2Bus.snoopLayer0.occupancy 1962409 # Layer occupancy (ticks) 3138system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3139system.toL2Bus.respLayer0.occupancy 733983819 # Layer occupancy (ticks) 3140system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3141system.toL2Bus.respLayer1.occupancy 257943151 # Layer occupancy (ticks) 3142system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)	3sim_seconds 2.848624 4sim_ticks 2848623849000 5final_tick 2848623849000 6sim_freq 1000000000000 7host_inst_rate 254983 8host_op_rate 308756 9host_tick_rate 5710154970 10host_mem_usage 634664 11host_seconds 498.87 12sim_insts 127203067 13sim_ops 154028798 14system.voltage_domain.voltage 1 15system.clk_domain.clock 1000 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2848623849000 17system.physmem.bytes_read::cpu0.dtb.walker 9536 18system.physmem.bytes_read::cpu0.itb.walker 64 19system.physmem.bytes_read::cpu0.inst 1667584 20system.physmem.bytes_read::cpu0.data 1358648 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8591232 22system.physmem.bytes_read::cpu1.dtb.walker 1280 23system.physmem.bytes_read::cpu1.inst 234816 24system.physmem.bytes_read::cpu1.data 662164 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 335296 26system.physmem.bytes_read::realview.ide 960 27system.physmem.bytes_read::total 12861580 28system.physmem.bytes_inst_read::cpu0.inst 1667584 29system.physmem.bytes_inst_read::cpu1.inst 234816 30system.physmem.bytes_inst_read::total 1902400 31system.physmem.bytes_written::writebacks 8982016 32system.physmem.bytes_written::cpu0.data 17524 33system.physmem.bytes_written::cpu1.data 40 34system.physmem.bytes_written::total 8999580 35system.physmem.num_reads::cpu0.dtb.walker 149 36system.physmem.num_reads::cpu0.itb.walker 1 37system.physmem.num_reads::cpu0.inst 26056 38system.physmem.num_reads::cpu0.data 21753 39system.physmem.num_reads::cpu0.l2cache.prefetcher 134238 40system.physmem.num_reads::cpu1.dtb.walker 20 41system.physmem.num_reads::cpu1.inst 3669 42system.physmem.num_reads::cpu1.data 10367 43system.physmem.num_reads::cpu1.l2cache.prefetcher 5239 44system.physmem.num_reads::realview.ide 15 45system.physmem.num_reads::total 201507 46system.physmem.num_writes::writebacks 140344 47system.physmem.num_writes::cpu0.data 4381 48system.physmem.num_writes::cpu1.data 10 49system.physmem.num_writes::total 144735 50system.physmem.bw_read::cpu0.dtb.walker 3348 51system.physmem.bw_read::cpu0.itb.walker 22 52system.physmem.bw_read::cpu0.inst 585400 53system.physmem.bw_read::cpu0.data 476949 54system.physmem.bw_read::cpu0.l2cache.prefetcher 3015924 55system.physmem.bw_read::cpu1.dtb.walker 449 56system.physmem.bw_read::cpu1.inst 82431 57system.physmem.bw_read::cpu1.data 232450 58system.physmem.bw_read::cpu1.l2cache.prefetcher 117705 59system.physmem.bw_read::realview.ide 337 60system.physmem.bw_read::total 4515015 61system.physmem.bw_inst_read::cpu0.inst 585400 62system.physmem.bw_inst_read::cpu1.inst 82431 63system.physmem.bw_inst_read::total 667831 64system.physmem.bw_write::writebacks 3153107 65system.physmem.bw_write::cpu0.data 6152 66system.physmem.bw_write::cpu1.data 14 67system.physmem.bw_write::total 3159273 68system.physmem.bw_total::writebacks 3153107 69system.physmem.bw_total::cpu0.dtb.walker 3348 70system.physmem.bw_total::cpu0.itb.walker 22 71system.physmem.bw_total::cpu0.inst 585400 72system.physmem.bw_total::cpu0.data 483101 73system.physmem.bw_total::cpu0.l2cache.prefetcher 3015924 74system.physmem.bw_total::cpu1.dtb.walker 449 75system.physmem.bw_total::cpu1.inst 82431 76system.physmem.bw_total::cpu1.data 232465 77system.physmem.bw_total::cpu1.l2cache.prefetcher 117705 78system.physmem.bw_total::realview.ide 337 79system.physmem.bw_total::total 7674288 80system.physmem.readReqs 201507 81system.physmem.writeReqs 144735 82system.physmem.readBursts 201507 83system.physmem.writeBursts 144735 84system.physmem.bytesReadDRAM 12886784 85system.physmem.bytesReadWrQ 9664 86system.physmem.bytesWritten 9012160 87system.physmem.bytesReadSys 12861580 88system.physmem.bytesWrittenSys 8999580 89system.physmem.servicedByWrQ 151 90system.physmem.mergedWrBursts 3896 91system.physmem.neitherReadNorWriteReqs 0 92system.physmem.perBankRdBursts::0 12371 93system.physmem.perBankRdBursts::1 12729 94system.physmem.perBankRdBursts::2 13637 95system.physmem.perBankRdBursts::3 13176 96system.physmem.perBankRdBursts::4 15206 97system.physmem.perBankRdBursts::5 12912 98system.physmem.perBankRdBursts::6 12737 99system.physmem.perBankRdBursts::7 12939 100system.physmem.perBankRdBursts::8 12121 101system.physmem.perBankRdBursts::9 12358 102system.physmem.perBankRdBursts::10 11582 103system.physmem.perBankRdBursts::11 10807 104system.physmem.perBankRdBursts::12 12020 105system.physmem.perBankRdBursts::13 12909 106system.physmem.perBankRdBursts::14 12059 107system.physmem.perBankRdBursts::15 11793 108system.physmem.perBankWrBursts::0 8805 109system.physmem.perBankWrBursts::1 9304 110system.physmem.perBankWrBursts::2 9936 111system.physmem.perBankWrBursts::3 9418 112system.physmem.perBankWrBursts::4 8548 113system.physmem.perBankWrBursts::5 9131 114system.physmem.perBankWrBursts::6 8974 115system.physmem.perBankWrBursts::7 9071 116system.physmem.perBankWrBursts::8 8560 117system.physmem.perBankWrBursts::9 8780 118system.physmem.perBankWrBursts::10 8271 119system.physmem.perBankWrBursts::11 7900 120system.physmem.perBankWrBursts::12 8752 121system.physmem.perBankWrBursts::13 8928 122system.physmem.perBankWrBursts::14 8529 123system.physmem.perBankWrBursts::15 7908 124system.physmem.numRdRetry 0 125system.physmem.numWrRetry 81 126system.physmem.totGap 2848623293000 127system.physmem.readPktSize::0 0 128system.physmem.readPktSize::1 0 129system.physmem.readPktSize::2 555 130system.physmem.readPktSize::3 28 131system.physmem.readPktSize::4 0 132system.physmem.readPktSize::5 0 133system.physmem.readPktSize::6 200924 134system.physmem.writePktSize::0 0 135system.physmem.writePktSize::1 0 136system.physmem.writePktSize::2 4391 137system.physmem.writePktSize::3 0 138system.physmem.writePktSize::4 0 139system.physmem.writePktSize::5 0 140system.physmem.writePktSize::6 140344 141system.physmem.rdQLenPdf::0 85231 142system.physmem.rdQLenPdf::1 63458 143system.physmem.rdQLenPdf::2 11762 144system.physmem.rdQLenPdf::3 9672 145system.physmem.rdQLenPdf::4 8125 146system.physmem.rdQLenPdf::5 6741 147system.physmem.rdQLenPdf::6 5582 148system.physmem.rdQLenPdf::7 4883 149system.physmem.rdQLenPdf::8 4010 150system.physmem.rdQLenPdf::9 1041 151system.physmem.rdQLenPdf::10 301 152system.physmem.rdQLenPdf::11 244 153system.physmem.rdQLenPdf::12 163 154system.physmem.rdQLenPdf::13 133 155system.physmem.rdQLenPdf::14 4 156system.physmem.rdQLenPdf::15 2 157system.physmem.rdQLenPdf::16 1 158system.physmem.rdQLenPdf::17 1 159system.physmem.rdQLenPdf::18 1 160system.physmem.rdQLenPdf::19 1 161system.physmem.rdQLenPdf::20 0 162system.physmem.rdQLenPdf::21 0 163system.physmem.rdQLenPdf::22 0 164system.physmem.rdQLenPdf::23 0 165system.physmem.rdQLenPdf::24 0 166system.physmem.rdQLenPdf::25 0 167system.physmem.rdQLenPdf::26 0 168system.physmem.rdQLenPdf::27 0 169system.physmem.rdQLenPdf::28 0 170system.physmem.rdQLenPdf::29 0 171system.physmem.rdQLenPdf::30 0 172system.physmem.rdQLenPdf::31 0 173system.physmem.wrQLenPdf::0 1 174system.physmem.wrQLenPdf::1 1 175system.physmem.wrQLenPdf::2 1 176system.physmem.wrQLenPdf::3 1 177system.physmem.wrQLenPdf::4 1 178system.physmem.wrQLenPdf::5 1 179system.physmem.wrQLenPdf::6 1 180system.physmem.wrQLenPdf::7 1 181system.physmem.wrQLenPdf::8 1 182system.physmem.wrQLenPdf::9 1 183system.physmem.wrQLenPdf::10 1 184system.physmem.wrQLenPdf::11 1 185system.physmem.wrQLenPdf::12 1 186system.physmem.wrQLenPdf::13 1 187system.physmem.wrQLenPdf::14 1 188system.physmem.wrQLenPdf::15 2579 189system.physmem.wrQLenPdf::16 3466 190system.physmem.wrQLenPdf::17 4465 191system.physmem.wrQLenPdf::18 5100 192system.physmem.wrQLenPdf::19 6081 193system.physmem.wrQLenPdf::20 6495 194system.physmem.wrQLenPdf::21 7105 195system.physmem.wrQLenPdf::22 7482 196system.physmem.wrQLenPdf::23 8550 197system.physmem.wrQLenPdf::24 8454 198system.physmem.wrQLenPdf::25 9694 199system.physmem.wrQLenPdf::26 10241 200system.physmem.wrQLenPdf::27 8890 201system.physmem.wrQLenPdf::28 8481 202system.physmem.wrQLenPdf::29 8847 203system.physmem.wrQLenPdf::30 9999 204system.physmem.wrQLenPdf::31 8358 205system.physmem.wrQLenPdf::32 8021 206system.physmem.wrQLenPdf::33 878 207system.physmem.wrQLenPdf::34 529 208system.physmem.wrQLenPdf::35 472 209system.physmem.wrQLenPdf::36 388 210system.physmem.wrQLenPdf::37 315 211system.physmem.wrQLenPdf::38 296 212system.physmem.wrQLenPdf::39 291 213system.physmem.wrQLenPdf::40 294 214system.physmem.wrQLenPdf::41 261 215system.physmem.wrQLenPdf::42 323 216system.physmem.wrQLenPdf::43 287 217system.physmem.wrQLenPdf::44 247 218system.physmem.wrQLenPdf::45 264 219system.physmem.wrQLenPdf::46 292 220system.physmem.wrQLenPdf::47 229 221system.physmem.wrQLenPdf::48 187 222system.physmem.wrQLenPdf::49 201 223system.physmem.wrQLenPdf::50 190 224system.physmem.wrQLenPdf::51 167 225system.physmem.wrQLenPdf::52 232 226system.physmem.wrQLenPdf::53 203 227system.physmem.wrQLenPdf::54 172 228system.physmem.wrQLenPdf::55 242 229system.physmem.wrQLenPdf::56 262 230system.physmem.wrQLenPdf::57 203 231system.physmem.wrQLenPdf::58 150 232system.physmem.wrQLenPdf::59 219 233system.physmem.wrQLenPdf::60 213 234system.physmem.wrQLenPdf::61 193 235system.physmem.wrQLenPdf::62 95 236system.physmem.wrQLenPdf::63 221 237system.physmem.bytesPerActivate::samples 88702 238system.physmem.bytesPerActivate::mean 246.880025 239system.physmem.bytesPerActivate::gmean 141.304455 240system.physmem.bytesPerActivate::stdev 302.553851 241system.physmem.bytesPerActivate::0-127 44832 50.54% 50.54% 242system.physmem.bytesPerActivate::128-255 18757 21.15% 71.69% 243system.physmem.bytesPerActivate::256-383 6580 7.42% 79.11% 244system.physmem.bytesPerActivate::384-511 3817 4.30% 83.41% 245system.physmem.bytesPerActivate::512-639 2913 3.28% 86.69% 246system.physmem.bytesPerActivate::640-767 1571 1.77% 88.46% 247system.physmem.bytesPerActivate::768-895 958 1.08% 89.54% 248system.physmem.bytesPerActivate::896-1023 1010 1.14% 90.68% 249system.physmem.bytesPerActivate::1024-1151 8264 9.32% 100.00% 250system.physmem.bytesPerActivate::total 88702 251system.physmem.rdPerTurnAround::samples 6978 252system.physmem.rdPerTurnAround::mean 28.854256 253system.physmem.rdPerTurnAround::stdev 558.300170 254system.physmem.rdPerTurnAround::0-2047 6976 99.97% 99.97% 255system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% 256system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% 257system.physmem.rdPerTurnAround::total 6978 258system.physmem.wrPerTurnAround::samples 6978 259system.physmem.wrPerTurnAround::mean 20.179851 260system.physmem.wrPerTurnAround::gmean 18.509497 261system.physmem.wrPerTurnAround::stdev 14.198077 262system.physmem.wrPerTurnAround::16-19 5875 84.19% 84.19% 263system.physmem.wrPerTurnAround::20-23 429 6.15% 90.34% 264system.physmem.wrPerTurnAround::24-27 69 0.99% 91.33% 265system.physmem.wrPerTurnAround::28-31 52 0.75% 92.08% 266system.physmem.wrPerTurnAround::32-35 247 3.54% 95.61% 267system.physmem.wrPerTurnAround::36-39 18 0.26% 95.87% 268system.physmem.wrPerTurnAround::40-43 20 0.29% 96.16% 269system.physmem.wrPerTurnAround::44-47 11 0.16% 96.32% 270system.physmem.wrPerTurnAround::48-51 9 0.13% 96.45% 271system.physmem.wrPerTurnAround::52-55 5 0.07% 96.52% 272system.physmem.wrPerTurnAround::56-59 7 0.10% 96.62% 273system.physmem.wrPerTurnAround::60-63 12 0.17% 96.79% 274system.physmem.wrPerTurnAround::64-67 142 2.03% 98.82% 275system.physmem.wrPerTurnAround::68-71 6 0.09% 98.91% 276system.physmem.wrPerTurnAround::72-75 4 0.06% 98.97% 277system.physmem.wrPerTurnAround::76-79 6 0.09% 99.05% 278system.physmem.wrPerTurnAround::80-83 7 0.10% 99.15% 279system.physmem.wrPerTurnAround::84-87 2 0.03% 99.18% 280system.physmem.wrPerTurnAround::88-91 1 0.01% 99.20% 281system.physmem.wrPerTurnAround::96-99 3 0.04% 99.24% 282system.physmem.wrPerTurnAround::100-103 1 0.01% 99.25% 283system.physmem.wrPerTurnAround::104-107 1 0.01% 99.27% 284system.physmem.wrPerTurnAround::108-111 6 0.09% 99.36% 285system.physmem.wrPerTurnAround::112-115 2 0.03% 99.38% 286system.physmem.wrPerTurnAround::116-119 2 0.03% 99.41% 287system.physmem.wrPerTurnAround::120-123 1 0.01% 99.43% 288system.physmem.wrPerTurnAround::124-127 2 0.03% 99.46% 289system.physmem.wrPerTurnAround::128-131 12 0.17% 99.63% 290system.physmem.wrPerTurnAround::132-135 1 0.01% 99.64% 291system.physmem.wrPerTurnAround::136-139 2 0.03% 99.67% 292system.physmem.wrPerTurnAround::140-143 4 0.06% 99.73% 293system.physmem.wrPerTurnAround::144-147 1 0.01% 99.74% 294system.physmem.wrPerTurnAround::148-151 1 0.01% 99.76% 295system.physmem.wrPerTurnAround::152-155 1 0.01% 99.77% 296system.physmem.wrPerTurnAround::156-159 1 0.01% 99.79% 297system.physmem.wrPerTurnAround::160-163 1 0.01% 99.80% 298system.physmem.wrPerTurnAround::172-175 1 0.01% 99.81% 299system.physmem.wrPerTurnAround::176-179 4 0.06% 99.87% 300system.physmem.wrPerTurnAround::180-183 1 0.01% 99.89% 301system.physmem.wrPerTurnAround::188-191 3 0.04% 99.93% 302system.physmem.wrPerTurnAround::192-195 5 0.07% 100.00% 303system.physmem.wrPerTurnAround::total 6978 304system.physmem.totQLat 9469337826 305system.physmem.totMemAccLat 13244762826 306system.physmem.totBusLat 1006780000 307system.physmem.avgQLat 47027.84 308system.physmem.avgBusLat 5000.00 309system.physmem.avgMemAccLat 65777.84 310system.physmem.avgRdBW 4.52 311system.physmem.avgWrBW 3.16 312system.physmem.avgRdBWSys 4.52 313system.physmem.avgWrBWSys 3.16 314system.physmem.peakBW 12800.00 315system.physmem.busUtil 0.06 316system.physmem.busUtilRead 0.04 317system.physmem.busUtilWrite 0.02 318system.physmem.avgRdQLen 1.02 319system.physmem.avgWrQLen 23.84 320system.physmem.readRowHits 166772 321system.physmem.writeRowHits 86694 322system.physmem.readRowHitRate 82.82 323system.physmem.writeRowHitRate 61.56 324system.physmem.avgGap 8227260.97 325system.physmem.pageHitRate 74.07 326system.physmem_0.actEnergy 335508600 327system.physmem_0.preEnergy 178319460 328system.physmem_0.readEnergy 754747980 329system.physmem_0.writeEnergy 382036140 330system.physmem_0.refreshEnergy 5719839840.000001 331system.physmem_0.actBackEnergy 5271880410 332system.physmem_0.preBackEnergy 306187680 333system.physmem_0.actPowerDownEnergy 11707194090 334system.physmem_0.prePowerDownEnergy 8394624000 335system.physmem_0.selfRefreshEnergy 670253357385 336system.physmem_0.totalEnergy 703305764505 337system.physmem_0.averagePower 246.893167 338system.physmem_0.totalIdleTime 2836258686816 339system.physmem_0.memoryStateTime::IDLE 539863955 340system.physmem_0.memoryStateTime::REF 2430282000 341system.physmem_0.memoryStateTime::SREF 2788726076750 342system.physmem_0.memoryStateTime::PRE_PDN 21860979078 343system.physmem_0.memoryStateTime::ACT 9392787729 344system.physmem_0.memoryStateTime::ACT_PDN 25673859488 345system.physmem_1.actEnergy 297845100 346system.physmem_1.preEnergy 158304630 347system.physmem_1.readEnergy 682933860 348system.physmem_1.writeEnergy 353018160 349system.physmem_1.refreshEnergy 5672512560.000001 350system.physmem_1.actBackEnergy 5217863790 351system.physmem_1.preBackEnergy 312588960 352system.physmem_1.actPowerDownEnergy 10775465250 353system.physmem_1.prePowerDownEnergy 8663500800 354system.physmem_1.selfRefreshEnergy 670664327850 355system.physmem_1.totalEnergy 702800898300 356system.physmem_1.averagePower 246.715936 357system.physmem_1.totalIdleTime 2836361418343 358system.physmem_1.memoryStateTime::IDLE 561410191 359system.physmem_1.memoryStateTime::REF 2410880000 360system.physmem_1.memoryStateTime::SREF 2790169885500 361system.physmem_1.memoryStateTime::PRE_PDN 22561142782 362system.physmem_1.memoryStateTime::ACT 9290058466 363system.physmem_1.memoryStateTime::ACT_PDN 23630472061 364system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848623849000 365system.realview.nvmem.bytes_read::cpu0.inst 512 366system.realview.nvmem.bytes_read::cpu1.inst 832 367system.realview.nvmem.bytes_read::total 1344 368system.realview.nvmem.bytes_inst_read::cpu0.inst 512 369system.realview.nvmem.bytes_inst_read::cpu1.inst 832 370system.realview.nvmem.bytes_inst_read::total 1344 371system.realview.nvmem.num_reads::cpu0.inst 8 372system.realview.nvmem.num_reads::cpu1.inst 13 373system.realview.nvmem.num_reads::total 21 374system.realview.nvmem.bw_read::cpu0.inst 180 375system.realview.nvmem.bw_read::cpu1.inst 292 376system.realview.nvmem.bw_read::total 472 377system.realview.nvmem.bw_inst_read::cpu0.inst 180 378system.realview.nvmem.bw_inst_read::cpu1.inst 292 379system.realview.nvmem.bw_inst_read::total 472 380system.realview.nvmem.bw_total::cpu0.inst 180 381system.realview.nvmem.bw_total::cpu1.inst 292 382system.realview.nvmem.bw_total::total 472 383system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848623849000 384system.pwrStateResidencyTicks::UNDEFINED 2848623849000 385system.bridge.pwrStateResidencyTicks::UNDEFINED 2848623849000 386system.cf0.dma_read_full_pages 0 387system.cf0.dma_read_bytes 1024 388system.cf0.dma_read_txs 1 389system.cf0.dma_write_full_pages 540 390system.cf0.dma_write_bytes 2318336 391system.cf0.dma_write_txs 631 392system.cpu0.branchPred.lookups 21379739 393system.cpu0.branchPred.condPredicted 14048750 394system.cpu0.branchPred.condIncorrect 1066195 395system.cpu0.branchPred.BTBLookups 13664725 396system.cpu0.branchPred.BTBHits 8978756 397system.cpu0.branchPred.BTBCorrect 0 398system.cpu0.branchPred.BTBHitPct 65.707550 399system.cpu0.branchPred.usedRAS 3515588 400system.cpu0.branchPred.RASInCorrect 217948 401system.cpu0.branchPred.indirectLookups 787162 402system.cpu0.branchPred.indirectHits 592512 403system.cpu0.branchPred.indirectMisses 194650 404system.cpu0.branchPredindirectMispredicted 105179 405system.cpu_clk_domain.clock 500 406system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848623849000 407system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 408system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 409system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 410system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 411system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 412system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 413system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 414system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 415system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 416system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 417system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 418system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 419system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 420system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 421system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 422system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 423system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 424system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 425system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 426system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 427system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 428system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 429system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 430system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 431system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 432system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 433system.cpu0.dstage2_mmu.stage2_tlb.hits 0 434system.cpu0.dstage2_mmu.stage2_tlb.misses 0 435system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 436system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848623849000 437system.cpu0.dtb.walker.walks 69389 438system.cpu0.dtb.walker.walksShort 69389 439system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46163 440system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23226 441system.cpu0.dtb.walker.walkWaitTime::samples 69389 442system.cpu0.dtb.walker.walkWaitTime::0 69389 100.00% 100.00% 443system.cpu0.dtb.walker.walkWaitTime::total 69389 444system.cpu0.dtb.walker.walkCompletionTime::samples 7614 445system.cpu0.dtb.walker.walkCompletionTime::mean 12248.161282 446system.cpu0.dtb.walker.walkCompletionTime::gmean 11230.175404 447system.cpu0.dtb.walker.walkCompletionTime::stdev 9547.601051 448system.cpu0.dtb.walker.walkCompletionTime::0-65535 7604 99.87% 99.87% 449system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6 0.08% 99.95% 450system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1 0.01% 99.96% 451system.cpu0.dtb.walker.walkCompletionTime::196608-262143 2 0.03% 99.99% 452system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00% 453system.cpu0.dtb.walker.walkCompletionTime::total 7614 454system.cpu0.dtb.walker.walksPending::samples 338892000 455system.cpu0.dtb.walker.walksPending::0 338892000 100.00% 100.00% 456system.cpu0.dtb.walker.walksPending::total 338892000 457system.cpu0.dtb.walker.walkPageSizes::4K 5921 77.76% 77.76% 458system.cpu0.dtb.walker.walkPageSizes::1M 1693 22.24% 100.00% 459system.cpu0.dtb.walker.walkPageSizes::total 7614 460system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 69389 461system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 462system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 69389 463system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7614 464system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 465system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7614 466system.cpu0.dtb.walker.walkRequestOrigin::total 77003 467system.cpu0.dtb.inst_hits 0 468system.cpu0.dtb.inst_misses 0 469system.cpu0.dtb.read_hits 17963765 470system.cpu0.dtb.read_misses 62780 471system.cpu0.dtb.write_hits 15037845 472system.cpu0.dtb.write_misses 6609 473system.cpu0.dtb.flush_tlb 66 474system.cpu0.dtb.flush_tlb_mva 917 475system.cpu0.dtb.flush_tlb_mva_asid 0 476system.cpu0.dtb.flush_tlb_asid 0 477system.cpu0.dtb.flush_entries 3754 478system.cpu0.dtb.align_faults 1496 479system.cpu0.dtb.prefetch_faults 2044 480system.cpu0.dtb.domain_faults 0 481system.cpu0.dtb.perms_faults 601 482system.cpu0.dtb.read_accesses 18026545 483system.cpu0.dtb.write_accesses 15044454 484system.cpu0.dtb.inst_accesses 0 485system.cpu0.dtb.hits 33001610 486system.cpu0.dtb.misses 69389 487system.cpu0.dtb.accesses 33070999 488system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848623849000 489system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 490system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 491system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 492system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 493system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 494system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 495system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 496system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 497system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 498system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 499system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 500system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 501system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 502system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 503system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 504system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 505system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 506system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 507system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 508system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 509system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 510system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 511system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 512system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 513system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 514system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 515system.cpu0.istage2_mmu.stage2_tlb.hits 0 516system.cpu0.istage2_mmu.stage2_tlb.misses 0 517system.cpu0.istage2_mmu.stage2_tlb.accesses 0 518system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848623849000 519system.cpu0.itb.walker.walks 4330 520system.cpu0.itb.walker.walksShort 4330 521system.cpu0.itb.walker.walksShortTerminationLevel::Level1 325 522system.cpu0.itb.walker.walksShortTerminationLevel::Level2 4005 523system.cpu0.itb.walker.walkWaitTime::samples 4330 524system.cpu0.itb.walker.walkWaitTime::0 4330 100.00% 100.00% 525system.cpu0.itb.walker.walkWaitTime::total 4330 526system.cpu0.itb.walker.walkCompletionTime::samples 2695 527system.cpu0.itb.walker.walkCompletionTime::mean 12512.059369 528system.cpu0.itb.walker.walkCompletionTime::gmean 11831.555276 529system.cpu0.itb.walker.walkCompletionTime::stdev 4578.031613 530system.cpu0.itb.walker.walkCompletionTime::0-8191 443 16.44% 16.44% 531system.cpu0.itb.walker.walkCompletionTime::8192-16383 2044 75.84% 92.28% 532system.cpu0.itb.walker.walkCompletionTime::16384-24575 157 5.83% 98.11% 533system.cpu0.itb.walker.walkCompletionTime::24576-32767 32 1.19% 99.29% 534system.cpu0.itb.walker.walkCompletionTime::32768-40959 18 0.67% 99.96% 535system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% 536system.cpu0.itb.walker.walkCompletionTime::total 2695 537system.cpu0.itb.walker.walksPending::samples 338263500 538system.cpu0.itb.walker.walksPending::0 338263500 100.00% 100.00% 539system.cpu0.itb.walker.walksPending::total 338263500 540system.cpu0.itb.walker.walkPageSizes::4K 2375 88.13% 88.13% 541system.cpu0.itb.walker.walkPageSizes::1M 320 11.87% 100.00% 542system.cpu0.itb.walker.walkPageSizes::total 2695 543system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 544system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4330 545system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4330 546system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 547system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2695 548system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2695 549system.cpu0.itb.walker.walkRequestOrigin::total 7025 550system.cpu0.itb.inst_hits 39749039 551system.cpu0.itb.inst_misses 4330 552system.cpu0.itb.read_hits 0 553system.cpu0.itb.read_misses 0 554system.cpu0.itb.write_hits 0 555system.cpu0.itb.write_misses 0 556system.cpu0.itb.flush_tlb 66 557system.cpu0.itb.flush_tlb_mva 917 558system.cpu0.itb.flush_tlb_mva_asid 0 559system.cpu0.itb.flush_tlb_asid 0 560system.cpu0.itb.flush_entries 2403 561system.cpu0.itb.align_faults 0 562system.cpu0.itb.prefetch_faults 0 563system.cpu0.itb.domain_faults 0 564system.cpu0.itb.perms_faults 7919 565system.cpu0.itb.read_accesses 0 566system.cpu0.itb.write_accesses 0 567system.cpu0.itb.inst_accesses 39753369 568system.cpu0.itb.hits 39749039 569system.cpu0.itb.misses 4330 570system.cpu0.itb.accesses 39753369 571system.cpu0.numPwrStateTransitions 3708 572system.cpu0.pwrStateClkGateDist::samples 1854 573system.cpu0.pwrStateClkGateDist::mean 1488624916.645631 574system.cpu0.pwrStateClkGateDist::stdev 23946318823.517799 575system.cpu0.pwrStateClkGateDist::underflows 1085 58.52% 58.52% 576system.cpu0.pwrStateClkGateDist::1000-5e+10 762 41.10% 99.62% 577system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.68% 578system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.05% 99.73% 579system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% 580system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% 581system.cpu0.pwrStateClkGateDist::min_value 501 582system.cpu0.pwrStateClkGateDist::max_value 499964387468 583system.cpu0.pwrStateClkGateDist::total 1854 584system.cpu0.pwrStateResidencyTicks::ON 88713253539 585system.cpu0.pwrStateResidencyTicks::CLK_GATED 2759910595461 586system.cpu0.numCycles 177429053 587system.cpu0.numWorkItemsStarted 0 588system.cpu0.numWorkItemsCompleted 0 589system.cpu0.committedInsts 82144744 590system.cpu0.committedOps 98906656 591system.cpu0.discardedOps 5353018 592system.cpu0.numFetchSuspends 1854 593system.cpu0.quiesceCycles 5519845971 594system.cpu0.cpi 2.159956 595system.cpu0.ipc 0.462972 596system.cpu0.op_class_0::No_OpClass 2315 0.00% 0.00% 597system.cpu0.op_class_0::IntAlu 65602827 66.33% 66.33% 598system.cpu0.op_class_0::IntMult 94044 0.10% 66.43% 599system.cpu0.op_class_0::IntDiv 0 0.00% 66.43% 600system.cpu0.op_class_0::FloatAdd 0 0.00% 66.43% 601system.cpu0.op_class_0::FloatCmp 0 0.00% 66.43% 602system.cpu0.op_class_0::FloatCvt 0 0.00% 66.43% 603system.cpu0.op_class_0::FloatMult 0 0.00% 66.43% 604system.cpu0.op_class_0::FloatMultAcc 0 0.00% 66.43% 605system.cpu0.op_class_0::FloatDiv 0 0.00% 66.43% 606system.cpu0.op_class_0::FloatMisc 0 0.00% 66.43% 607system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.43% 608system.cpu0.op_class_0::SimdAdd 0 0.00% 66.43% 609system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.43% 610system.cpu0.op_class_0::SimdAlu 0 0.00% 66.43% 611system.cpu0.op_class_0::SimdCmp 0 0.00% 66.43% 612system.cpu0.op_class_0::SimdCvt 0 0.00% 66.43% 613system.cpu0.op_class_0::SimdMisc 0 0.00% 66.43% 614system.cpu0.op_class_0::SimdMult 0 0.00% 66.43% 615system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.43% 616system.cpu0.op_class_0::SimdShift 0 0.00% 66.43% 617system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.43% 618system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.43% 619system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.43% 620system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.43% 621system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.43% 622system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.43% 623system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.43% 624system.cpu0.op_class_0::SimdFloatMisc 8167 0.01% 66.43% 625system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.43% 626system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.43% 627system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.43% 628system.cpu0.op_class_0::MemRead 17404847 17.60% 84.03% 629system.cpu0.op_class_0::MemWrite 15783224 15.96% 99.99% 630system.cpu0.op_class_0::FloatMemRead 2708 0.00% 99.99% 631system.cpu0.op_class_0::FloatMemWrite 8524 0.01% 100.00% 632system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% 633system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% 634system.cpu0.op_class_0::total 98906656 635system.cpu0.kern.inst.arm 0 636system.cpu0.kern.inst.quiesce 1854 637system.cpu0.tickCycles 124456621 638system.cpu0.idleCycles 52972432 639system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848623849000 640system.cpu0.dcache.tags.replacements 756405 641system.cpu0.dcache.tags.tagsinuse 496.635860 642system.cpu0.dcache.tags.total_refs 31498556 643system.cpu0.dcache.tags.sampled_refs 756917 644system.cpu0.dcache.tags.avg_refs 41.614280 645system.cpu0.dcache.tags.warmup_cycle 356904000 646system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.635860 647system.cpu0.dcache.tags.occ_percent::cpu0.data 0.969992 648system.cpu0.dcache.tags.occ_percent::total 0.969992 649system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 650system.cpu0.dcache.tags.age_task_id_blocks_1024::0 108 651system.cpu0.dcache.tags.age_task_id_blocks_1024::1 343 652system.cpu0.dcache.tags.age_task_id_blocks_1024::2 61 653system.cpu0.dcache.tags.occ_task_id_percent::1024 1 654system.cpu0.dcache.tags.tag_accesses 66081221 655system.cpu0.dcache.tags.data_accesses 66081221 656system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848623849000 657system.cpu0.dcache.ReadReq_hits::cpu0.data 16424804 658system.cpu0.dcache.ReadReq_hits::total 16424804 659system.cpu0.dcache.WriteReq_hits::cpu0.data 13888667 660system.cpu0.dcache.WriteReq_hits::total 13888667 661system.cpu0.dcache.SoftPFReq_hits::cpu0.data 328295 662system.cpu0.dcache.SoftPFReq_hits::total 328295 663system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374149 664system.cpu0.dcache.LoadLockedReq_hits::total 374149 665system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370236 666system.cpu0.dcache.StoreCondReq_hits::total 370236 667system.cpu0.dcache.demand_hits::cpu0.data 30313471 668system.cpu0.dcache.demand_hits::total 30313471 669system.cpu0.dcache.overall_hits::cpu0.data 30641766 670system.cpu0.dcache.overall_hits::total 30641766 671system.cpu0.dcache.ReadReq_misses::cpu0.data 461281 672system.cpu0.dcache.ReadReq_misses::total 461281 673system.cpu0.dcache.WriteReq_misses::cpu0.data 603910 674system.cpu0.dcache.WriteReq_misses::total 603910 675system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141881 676system.cpu0.dcache.SoftPFReq_misses::total 141881 677system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21430 678system.cpu0.dcache.LoadLockedReq_misses::total 21430 679system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20444 680system.cpu0.dcache.StoreCondReq_misses::total 20444 681system.cpu0.dcache.demand_misses::cpu0.data 1065191 682system.cpu0.dcache.demand_misses::total 1065191 683system.cpu0.dcache.overall_misses::cpu0.data 1207072 684system.cpu0.dcache.overall_misses::total 1207072 685system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6678483000 686system.cpu0.dcache.ReadReq_miss_latency::total 6678483000 687system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11547811000 688system.cpu0.dcache.WriteReq_miss_latency::total 11547811000 689system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336788000 690system.cpu0.dcache.LoadLockedReq_miss_latency::total 336788000 691system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 483606000 692system.cpu0.dcache.StoreCondReq_miss_latency::total 483606000 693system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 634500 694system.cpu0.dcache.StoreCondFailReq_miss_latency::total 634500 695system.cpu0.dcache.demand_miss_latency::cpu0.data 18226294000 696system.cpu0.dcache.demand_miss_latency::total 18226294000 697system.cpu0.dcache.overall_miss_latency::cpu0.data 18226294000 698system.cpu0.dcache.overall_miss_latency::total 18226294000 699system.cpu0.dcache.ReadReq_accesses::cpu0.data 16886085 700system.cpu0.dcache.ReadReq_accesses::total 16886085 701system.cpu0.dcache.WriteReq_accesses::cpu0.data 14492577 702system.cpu0.dcache.WriteReq_accesses::total 14492577 703system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 470176 704system.cpu0.dcache.SoftPFReq_accesses::total 470176 705system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 395579 706system.cpu0.dcache.LoadLockedReq_accesses::total 395579 707system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 390680 708system.cpu0.dcache.StoreCondReq_accesses::total 390680 709system.cpu0.dcache.demand_accesses::cpu0.data 31378662 710system.cpu0.dcache.demand_accesses::total 31378662 711system.cpu0.dcache.overall_accesses::cpu0.data 31848838 712system.cpu0.dcache.overall_accesses::total 31848838 713system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027317 714system.cpu0.dcache.ReadReq_miss_rate::total 0.027317 715system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041670 716system.cpu0.dcache.WriteReq_miss_rate::total 0.041670 717system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301761 718system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301761 719system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054174 720system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054174 721system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052329 722system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052329 723system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033946 724system.cpu0.dcache.demand_miss_rate::total 0.033946 725system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037900 726system.cpu0.dcache.overall_miss_rate::total 0.037900 727system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14478.122880 728system.cpu0.dcache.ReadReq_avg_miss_latency::total 14478.122880 729system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19121.741650 730system.cpu0.dcache.WriteReq_avg_miss_latency::total 19121.741650 731system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15715.725618 732system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15715.725618 733system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23655.155547 734system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23655.155547 735system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf 736system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf 737system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17110.822378 738system.cpu0.dcache.demand_avg_miss_latency::total 17110.822378 739system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15099.591408 740system.cpu0.dcache.overall_avg_miss_latency::total 15099.591408 741system.cpu0.dcache.blocked_cycles::no_mshrs 0 742system.cpu0.dcache.blocked_cycles::no_targets 0 743system.cpu0.dcache.blocked::no_mshrs 0 744system.cpu0.dcache.blocked::no_targets 0 745system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan 746system.cpu0.dcache.avg_blocked_cycles::no_targets nan 747system.cpu0.dcache.writebacks::writebacks 756405 748system.cpu0.dcache.writebacks::total 756405 749system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 46004 750system.cpu0.dcache.ReadReq_mshr_hits::total 46004 751system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266244 752system.cpu0.dcache.WriteReq_mshr_hits::total 266244 753system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14893 754system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14893 755system.cpu0.dcache.demand_mshr_hits::cpu0.data 312248 756system.cpu0.dcache.demand_mshr_hits::total 312248 757system.cpu0.dcache.overall_mshr_hits::cpu0.data 312248 758system.cpu0.dcache.overall_mshr_hits::total 312248 759system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 415277 760system.cpu0.dcache.ReadReq_mshr_misses::total 415277 761system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337666 762system.cpu0.dcache.WriteReq_mshr_misses::total 337666 763system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 108256 764system.cpu0.dcache.SoftPFReq_mshr_misses::total 108256 765system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6537 766system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6537 767system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20444 768system.cpu0.dcache.StoreCondReq_mshr_misses::total 20444 769system.cpu0.dcache.demand_mshr_misses::cpu0.data 752943 770system.cpu0.dcache.demand_mshr_misses::total 752943 771system.cpu0.dcache.overall_mshr_misses::cpu0.data 861199 772system.cpu0.dcache.overall_mshr_misses::total 861199 773system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20583 774system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20583 775system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19292 776system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19292 777system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39875 778system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39875 779system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5475832500 780system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5475832500 781system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6297373500 782system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6297373500 783system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1755672500 784system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1755672500 785system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104037500 786system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104037500 787system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 463180000 788system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 463180000 789system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 616500 790system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 616500 791system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11773206000 792system.cpu0.dcache.demand_mshr_miss_latency::total 11773206000 793system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13528878500 794system.cpu0.dcache.overall_mshr_miss_latency::total 13528878500 795system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4608535500 796system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4608535500 797system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4608535500 798system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4608535500 799system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024593 800system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024593 801system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023299 802system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023299 803system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230246 804system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.230246 805system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016525 806system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016525 807system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052329 808system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052329 809system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023995 810system.cpu0.dcache.demand_mshr_miss_rate::total 0.023995 811system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027040 812system.cpu0.dcache.overall_mshr_miss_rate::total 0.027040 813system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13185.975867 814system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13185.975867 815system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18649.711549 816system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18649.711549 817system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16217.784696 818system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16217.784696 819system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15915.175157 820system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15915.175157 821system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22656.036001 822system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22656.036001 823system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf 824system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf 825system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15636.251350 826system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15636.251350 827system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15709.352310 828system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15709.352310 829system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223900.087451 830system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223900.087451 831system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115574.557994 832system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115574.557994 833system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848623849000 834system.cpu0.icache.tags.replacements 2037202 835system.cpu0.icache.tags.tagsinuse 511.775063 836system.cpu0.icache.tags.total_refs 37703101 837system.cpu0.icache.tags.sampled_refs 2037714 838system.cpu0.icache.tags.avg_refs 18.502646 839system.cpu0.icache.tags.warmup_cycle 6575306000 840system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.775063 841system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999561 842system.cpu0.icache.tags.occ_percent::total 0.999561 843system.cpu0.icache.tags.occ_task_id_blocks::1024 512 844system.cpu0.icache.tags.age_task_id_blocks_1024::0 146 845system.cpu0.icache.tags.age_task_id_blocks_1024::1 264 846system.cpu0.icache.tags.age_task_id_blocks_1024::2 102 847system.cpu0.icache.tags.occ_task_id_percent::1024 1 848system.cpu0.icache.tags.tag_accesses 81519385 849system.cpu0.icache.tags.data_accesses 81519385 850system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848623849000 851system.cpu0.icache.ReadReq_hits::cpu0.inst 37703101 852system.cpu0.icache.ReadReq_hits::total 37703101 853system.cpu0.icache.demand_hits::cpu0.inst 37703101 854system.cpu0.icache.demand_hits::total 37703101 855system.cpu0.icache.overall_hits::cpu0.inst 37703101 856system.cpu0.icache.overall_hits::total 37703101 857system.cpu0.icache.ReadReq_misses::cpu0.inst 2037728 858system.cpu0.icache.ReadReq_misses::total 2037728 859system.cpu0.icache.demand_misses::cpu0.inst 2037728 860system.cpu0.icache.demand_misses::total 2037728 861system.cpu0.icache.overall_misses::cpu0.inst 2037728 862system.cpu0.icache.overall_misses::total 2037728 863system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20440936500 864system.cpu0.icache.ReadReq_miss_latency::total 20440936500 865system.cpu0.icache.demand_miss_latency::cpu0.inst 20440936500 866system.cpu0.icache.demand_miss_latency::total 20440936500 867system.cpu0.icache.overall_miss_latency::cpu0.inst 20440936500 868system.cpu0.icache.overall_miss_latency::total 20440936500 869system.cpu0.icache.ReadReq_accesses::cpu0.inst 39740829 870system.cpu0.icache.ReadReq_accesses::total 39740829 871system.cpu0.icache.demand_accesses::cpu0.inst 39740829 872system.cpu0.icache.demand_accesses::total 39740829 873system.cpu0.icache.overall_accesses::cpu0.inst 39740829 874system.cpu0.icache.overall_accesses::total 39740829 875system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051275 876system.cpu0.icache.ReadReq_miss_rate::total 0.051275 877system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051275 878system.cpu0.icache.demand_miss_rate::total 0.051275 879system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051275 880system.cpu0.icache.overall_miss_rate::total 0.051275 881system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10031.238958 882system.cpu0.icache.ReadReq_avg_miss_latency::total 10031.238958 883system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10031.238958 884system.cpu0.icache.demand_avg_miss_latency::total 10031.238958 885system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10031.238958 886system.cpu0.icache.overall_avg_miss_latency::total 10031.238958 887system.cpu0.icache.blocked_cycles::no_mshrs 0 888system.cpu0.icache.blocked_cycles::no_targets 0 889system.cpu0.icache.blocked::no_mshrs 0 890system.cpu0.icache.blocked::no_targets 0 891system.cpu0.icache.avg_blocked_cycles::no_mshrs nan 892system.cpu0.icache.avg_blocked_cycles::no_targets nan 893system.cpu0.icache.writebacks::writebacks 2037202 894system.cpu0.icache.writebacks::total 2037202 895system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2037728 896system.cpu0.icache.ReadReq_mshr_misses::total 2037728 897system.cpu0.icache.demand_mshr_misses::cpu0.inst 2037728 898system.cpu0.icache.demand_mshr_misses::total 2037728 899system.cpu0.icache.overall_mshr_misses::cpu0.inst 2037728 900system.cpu0.icache.overall_mshr_misses::total 2037728 901system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3277 902system.cpu0.icache.ReadReq_mshr_uncacheable::total 3277 903system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3277 904system.cpu0.icache.overall_mshr_uncacheable_misses::total 3277 905system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19422073000 906system.cpu0.icache.ReadReq_mshr_miss_latency::total 19422073000 907system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19422073000 908system.cpu0.icache.demand_mshr_miss_latency::total 19422073000 909system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19422073000 910system.cpu0.icache.overall_mshr_miss_latency::total 19422073000 911system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 323882000 912system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 323882000 913system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 323882000 914system.cpu0.icache.overall_mshr_uncacheable_latency::total 323882000 915system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.051275 916system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.051275 917system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.051275 918system.cpu0.icache.demand_mshr_miss_rate::total 0.051275 919system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.051275 920system.cpu0.icache.overall_mshr_miss_rate::total 0.051275 921system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9531.239204 922system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9531.239204 923system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9531.239204 924system.cpu0.icache.demand_avg_mshr_miss_latency::total 9531.239204 925system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9531.239204 926system.cpu0.icache.overall_avg_mshr_miss_latency::total 9531.239204 927system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979 928system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98834.909979 929system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979 930system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98834.909979 931system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848623849000 932system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927472 933system.cpu0.l2cache.prefetcher.pfIdentified 1927591 934system.cpu0.l2cache.prefetcher.pfBufferHit 103 935system.cpu0.l2cache.prefetcher.pfInCache 0 936system.cpu0.l2cache.prefetcher.pfRemovedFull 0 937system.cpu0.l2cache.prefetcher.pfSpanPage 244225 938system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848623849000 939system.cpu0.l2cache.tags.replacements 297417 940system.cpu0.l2cache.tags.tagsinuse 15628.878129 941system.cpu0.l2cache.tags.total_refs 2702548 942system.cpu0.l2cache.tags.sampled_refs 313030 943system.cpu0.l2cache.tags.avg_refs 8.633511 944system.cpu0.l2cache.tags.warmup_cycle 0 945system.cpu0.l2cache.tags.occ_blocks::writebacks 14526.448544 946system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 64.513494 947system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.067121 948system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1037.848970 949system.cpu0.l2cache.tags.occ_percent::writebacks 0.886624 950system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003938 951system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 952system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063345 953system.cpu0.l2cache.tags.occ_percent::total 0.953911 954system.cpu0.l2cache.tags.occ_task_id_blocks::1022 248 955system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 956system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15359 957system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 5 958system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 30 959system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 157 960system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 56 961system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 962system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 963system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 964system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 240 965system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1189 966system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7272 967system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5800 968system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 858 969system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.015137 970system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 971system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.937439 972system.cpu0.l2cache.tags.tag_accesses 95173701 973system.cpu0.l2cache.tags.data_accesses 95173701 974system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2848623849000 975system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 82675 976system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5812 977system.cpu0.l2cache.ReadReq_hits::total 88487 978system.cpu0.l2cache.WritebackDirty_hits::writebacks 506400 979system.cpu0.l2cache.WritebackDirty_hits::total 506400 980system.cpu0.l2cache.WritebackClean_hits::writebacks 2243097 981system.cpu0.l2cache.WritebackClean_hits::total 2243097 982system.cpu0.l2cache.ReadExReq_hits::cpu0.data 235078 983system.cpu0.l2cache.ReadExReq_hits::total 235078 984system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1942100 985system.cpu0.l2cache.ReadCleanReq_hits::total 1942100 986system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 414660 987system.cpu0.l2cache.ReadSharedReq_hits::total 414660 988system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 82675 989system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5812 990system.cpu0.l2cache.demand_hits::cpu0.inst 1942100 991system.cpu0.l2cache.demand_hits::cpu0.data 649738 992system.cpu0.l2cache.demand_hits::total 2680325 993system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 82675 994system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5812 995system.cpu0.l2cache.overall_hits::cpu0.inst 1942100 996system.cpu0.l2cache.overall_hits::cpu0.data 649738 997system.cpu0.l2cache.overall_hits::total 2680325 998system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 788 999system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 88 1000system.cpu0.l2cache.ReadReq_misses::total 876 1001system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 56733 1002system.cpu0.l2cache.UpgradeReq_misses::total 56733 1003system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20444 1004system.cpu0.l2cache.SCUpgradeReq_misses::total 20444 1005system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45864 1006system.cpu0.l2cache.ReadExReq_misses::total 45864 1007system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 95628 1008system.cpu0.l2cache.ReadCleanReq_misses::total 95628 1009system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 115406 1010system.cpu0.l2cache.ReadSharedReq_misses::total 115406 1011system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 788 1012system.cpu0.l2cache.demand_misses::cpu0.itb.walker 88 1013system.cpu0.l2cache.demand_misses::cpu0.inst 95628 1014system.cpu0.l2cache.demand_misses::cpu0.data 161270 1015system.cpu0.l2cache.demand_misses::total 257774 1016system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 788 1017system.cpu0.l2cache.overall_misses::cpu0.itb.walker 88 1018system.cpu0.l2cache.overall_misses::cpu0.inst 95628 1019system.cpu0.l2cache.overall_misses::cpu0.data 161270 1020system.cpu0.l2cache.overall_misses::total 257774 1021system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 38430500 1022system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2144000 1023system.cpu0.l2cache.ReadReq_miss_latency::total 40574500 1024system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 46515500 1025system.cpu0.l2cache.UpgradeReq_miss_latency::total 46515500 1026system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 11588000 1027system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 11588000 1028system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 589500 1029system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 589500 1030system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2931053499 1031system.cpu0.l2cache.ReadExReq_miss_latency::total 2931053499 1032system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 4619846000 1033system.cpu0.l2cache.ReadCleanReq_miss_latency::total 4619846000 1034system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3809640999 1035system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3809640999 1036system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 38430500 1037system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2144000 1038system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4619846000 1039system.cpu0.l2cache.demand_miss_latency::cpu0.data 6740694498 1040system.cpu0.l2cache.demand_miss_latency::total 11401114998 1041system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 38430500 1042system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2144000 1043system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4619846000 1044system.cpu0.l2cache.overall_miss_latency::cpu0.data 6740694498 1045system.cpu0.l2cache.overall_miss_latency::total 11401114998 1046system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 83463 1047system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5900 1048system.cpu0.l2cache.ReadReq_accesses::total 89363 1049system.cpu0.l2cache.WritebackDirty_accesses::writebacks 506400 1050system.cpu0.l2cache.WritebackDirty_accesses::total 506400 1051system.cpu0.l2cache.WritebackClean_accesses::writebacks 2243097 1052system.cpu0.l2cache.WritebackClean_accesses::total 2243097 1053system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56733 1054system.cpu0.l2cache.UpgradeReq_accesses::total 56733 1055system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20444 1056system.cpu0.l2cache.SCUpgradeReq_accesses::total 20444 1057system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 280942 1058system.cpu0.l2cache.ReadExReq_accesses::total 280942 1059system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 2037728 1060system.cpu0.l2cache.ReadCleanReq_accesses::total 2037728 1061system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 530066 1062system.cpu0.l2cache.ReadSharedReq_accesses::total 530066 1063system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 83463 1064system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5900 1065system.cpu0.l2cache.demand_accesses::cpu0.inst 2037728 1066system.cpu0.l2cache.demand_accesses::cpu0.data 811008 1067system.cpu0.l2cache.demand_accesses::total 2938099 1068system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 83463 1069system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5900 1070system.cpu0.l2cache.overall_accesses::cpu0.inst 2037728 1071system.cpu0.l2cache.overall_accesses::cpu0.data 811008 1072system.cpu0.l2cache.overall_accesses::total 2938099 1073system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009441 1074system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.014915 1075system.cpu0.l2cache.ReadReq_miss_rate::total 0.009803 1076system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 1077system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 1078system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 1079system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 1080system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.163251 1081system.cpu0.l2cache.ReadExReq_miss_rate::total 0.163251 1082system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.046929 1083system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.046929 1084system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.217720 1085system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.217720 1086system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009441 1087system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.014915 1088system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.046929 1089system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.198851 1090system.cpu0.l2cache.demand_miss_rate::total 0.087735 1091system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009441 1092system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.014915 1093system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.046929 1094system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.198851 1095system.cpu0.l2cache.overall_miss_rate::total 0.087735 1096system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 48769.670051 1097system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24363.636364 1098system.cpu0.l2cache.ReadReq_avg_miss_latency::total 46317.922374 1099system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 819.901997 1100system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 819.901997 1101system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 566.816670 1102system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 566.816670 1103system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf 1104system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf 1105system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63907.498234 1106system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63907.498234 1107system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 48310.599406 1108system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 48310.599406 1109system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33010.770662 1110system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33010.770662 1111system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 48769.670051 1112system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24363.636364 1113system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 48310.599406 1114system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41797.572382 1115system.cpu0.l2cache.demand_avg_miss_latency::total 44229.111540 1116system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 48769.670051 1117system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24363.636364 1118system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 48310.599406 1119system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41797.572382 1120system.cpu0.l2cache.overall_avg_miss_latency::total 44229.111540 1121system.cpu0.l2cache.blocked_cycles::no_mshrs 3 1122system.cpu0.l2cache.blocked_cycles::no_targets 0 1123system.cpu0.l2cache.blocked::no_mshrs 1 1124system.cpu0.l2cache.blocked::no_targets 0 1125system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 3 1126system.cpu0.l2cache.avg_blocked_cycles::no_targets nan 1127system.cpu0.l2cache.unused_prefetches 10997 1128system.cpu0.l2cache.writebacks::writebacks 236911 1129system.cpu0.l2cache.writebacks::total 236911 1130system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 1131system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 1132system.cpu0.l2cache.ReadReq_mshr_hits::total 2 1133system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3224 1134system.cpu0.l2cache.ReadExReq_mshr_hits::total 3224 1135system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 63 1136system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 63 1137system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 416 1138system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 416 1139system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 1140system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 1141system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 63 1142system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3640 1143system.cpu0.l2cache.demand_mshr_hits::total 3705 1144system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 1145system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 1146system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 63 1147system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3640 1148system.cpu0.l2cache.overall_mshr_hits::total 3705 1149system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 787 1150system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 87 1151system.cpu0.l2cache.ReadReq_mshr_misses::total 874 1152system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 267712 1153system.cpu0.l2cache.HardPFReq_mshr_misses::total 267712 1154system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 56733 1155system.cpu0.l2cache.UpgradeReq_mshr_misses::total 56733 1156system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20444 1157system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20444 1158system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42640 1159system.cpu0.l2cache.ReadExReq_mshr_misses::total 42640 1160system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 95565 1161system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 95565 1162system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 114990 1163system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 114990 1164system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 787 1165system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 87 1166system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 95565 1167system.cpu0.l2cache.demand_mshr_misses::cpu0.data 157630 1168system.cpu0.l2cache.demand_mshr_misses::total 254069 1169system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 787 1170system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 87 1171system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 95565 1172system.cpu0.l2cache.overall_mshr_misses::cpu0.data 157630 1173system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 267712 1174system.cpu0.l2cache.overall_mshr_misses::total 521781 1175system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3277 1176system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20583 1177system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23860 1178system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19292 1179system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19292 1180system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3277 1181system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39875 1182system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 43152 1183system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 33685500 1184system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1610000 1185system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 35295500 1186system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16994507487 1187system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16994507487 1188system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 984458499 1189system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 984458499 1190system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 308957999 1191system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 308957999 1192system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 481500 1193system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 481500 1194system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2181877499 1195system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2181877499 1196system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 4044466000 1197system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 4044466000 1198system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 3095831499 1199system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 3095831499 1200system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 33685500 1201system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1610000 1202system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 4044466000 1203system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5277708998 1204system.cpu0.l2cache.demand_mshr_miss_latency::total 9357470498 1205system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 33685500 1206system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1610000 1207system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 4044466000 1208system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5277708998 1209system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16994507487 1210system.cpu0.l2cache.overall_mshr_miss_latency::total 26351977985 1211system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 297666000 1212system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4443759500 1213system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4741425500 1214system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 297666000 1215system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4443759500 1216system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4741425500 1217system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009429 1218system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.014746 1219system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009780 1220system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf 1221system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf 1222system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 1223system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 1224system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 1225system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 1226system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.151775 1227system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.151775 1228system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.046898 1229system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.046898 1230system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.216935 1231system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.216935 1232system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009429 1233system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.014746 1234system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.046898 1235system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.194363 1236system.cpu0.l2cache.demand_mshr_miss_rate::total 0.086474 1237system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009429 1238system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.014746 1239system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.046898 1240system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.194363 1241system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf 1242system.cpu0.l2cache.overall_mshr_miss_rate::total 0.177591 1243system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 42802.414231 1244system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18505.747126 1245system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 40383.867277 1246system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63480.559284 1247system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63480.559284 1248system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17352.484427 1249system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17352.484427 1250system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15112.404569 1251system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15112.404569 1252system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf 1253system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf 1254system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 51169.734967 1255system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 51169.734967 1256system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42321.624026 1257system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42321.624026 1258system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26922.615001 1259system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26922.615001 1260system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 42802.414231 1261system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18505.747126 1262system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42321.624026 1263system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33481.627850 1264system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36830.429915 1265system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 42802.414231 1266system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18505.747126 1267system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42321.624026 1268system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33481.627850 1269system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63480.559284 1270system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50503.904866 1271system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 1272system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215894.646067 1273system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198718.587594 1274system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 1275system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111442.244514 1276system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109877.305803 1277system.cpu0.toL2Bus.snoop_filter.tot_requests 5743921 1278system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2895216 1279system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44126 1280system.cpu0.toL2Bus.snoop_filter.tot_snoops 221019 1281system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 216830 1282system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4189 1283system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848623849000 1284system.cpu0.toL2Bus.trans_dist::ReadReq 124852 1285system.cpu0.toL2Bus.trans_dist::ReadResp 2741615 1286system.cpu0.toL2Bus.trans_dist::WriteReq 19292 1287system.cpu0.toL2Bus.trans_dist::WriteResp 19292 1288system.cpu0.toL2Bus.trans_dist::WritebackDirty 743621 1289system.cpu0.toL2Bus.trans_dist::WritebackClean 2287205 1290system.cpu0.toL2Bus.trans_dist::CleanEvict 110575 1291system.cpu0.toL2Bus.trans_dist::HardPFReq 317039 1292system.cpu0.toL2Bus.trans_dist::UpgradeReq 86991 1293system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42833 1294system.cpu0.toL2Bus.trans_dist::UpgradeResp 113881 1295system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 13 1296system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 31 1297system.cpu0.toL2Bus.trans_dist::ReadExReq 299988 1298system.cpu0.toL2Bus.trans_dist::ReadExResp 296595 1299system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2037728 1300system.cpu0.toL2Bus.trans_dist::ReadSharedReq 617206 1301system.cpu0.toL2Bus.trans_dist::InvalidateReq 3167 1302system.cpu0.toL2Bus.trans_dist::InvalidateResp 12 1303system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6119211 1304system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2713935 1305system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14235 1306system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 176078 1307system.cpu0.toL2Bus.pkt_count::total 9023459 1308system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 261005184 1309system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104563972 1310system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 23600 1311system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 333852 1312system.cpu0.toL2Bus.pkt_size::total 365926608 1313system.cpu0.toL2Bus.snoops 939889 1314system.cpu0.toL2Bus.snoopTraffic 19367640 1315system.cpu0.toL2Bus.snoop_fanout::samples 3896905 1316system.cpu0.toL2Bus.snoop_fanout::mean 0.075382 1317system.cpu0.toL2Bus.snoop_fanout::stdev 0.268048 1318system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% 1319system.cpu0.toL2Bus.snoop_fanout::0 3607336 92.57% 92.57% 1320system.cpu0.toL2Bus.snoop_fanout::1 285380 7.32% 99.89% 1321system.cpu0.toL2Bus.snoop_fanout::2 4189 0.11% 100.00% 1322system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% 1323system.cpu0.toL2Bus.snoop_fanout::min_value 0 1324system.cpu0.toL2Bus.snoop_fanout::max_value 2 1325system.cpu0.toL2Bus.snoop_fanout::total 3896905 1326system.cpu0.toL2Bus.reqLayer0.occupancy 5735062996 1327system.cpu0.toL2Bus.reqLayer0.utilization 0.2 1328system.cpu0.toL2Bus.snoopLayer0.occupancy 115443960 1329system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 1330system.cpu0.toL2Bus.respLayer0.occupancy 3061810390 1331system.cpu0.toL2Bus.respLayer0.utilization 0.1 1332system.cpu0.toL2Bus.respLayer1.occupancy 1286359474 1333system.cpu0.toL2Bus.respLayer1.utilization 0.0 1334system.cpu0.toL2Bus.respLayer2.occupancy 8343483 1335system.cpu0.toL2Bus.respLayer2.utilization 0.0 1336system.cpu0.toL2Bus.respLayer3.occupancy 92635958 1337system.cpu0.toL2Bus.respLayer3.utilization 0.0 1338system.cpu1.branchPred.lookups 18642416 1339system.cpu1.branchPred.condPredicted 5780300 1340system.cpu1.branchPred.condIncorrect 870028 1341system.cpu1.branchPred.BTBLookups 9493986 1342system.cpu1.branchPred.BTBHits 3424862 1343system.cpu1.branchPred.BTBCorrect 0 1344system.cpu1.branchPred.BTBHitPct 36.074016 1345system.cpu1.branchPred.usedRAS 8548372 1346system.cpu1.branchPred.RASInCorrect 713031 1347system.cpu1.branchPred.indirectLookups 3551810 1348system.cpu1.branchPred.indirectHits 3499174 1349system.cpu1.branchPred.indirectMisses 52636 1350system.cpu1.branchPredindirectMispredicted 18015 1351system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848623849000 1352system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 1353system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 1354system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 1355system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 1356system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 1357system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 1358system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 1359system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 1360system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 1361system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 1362system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 1363system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 1364system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 1365system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 1366system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 1367system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 1368system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 1369system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 1370system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 1371system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 1372system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 1373system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 1374system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 1375system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 1376system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 1377system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 1378system.cpu1.dstage2_mmu.stage2_tlb.hits 0 1379system.cpu1.dstage2_mmu.stage2_tlb.misses 0 1380system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 1381system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848623849000 1382system.cpu1.dtb.walker.walks 23296 1383system.cpu1.dtb.walker.walksShort 23296 1384system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19754 1385system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3542 1386system.cpu1.dtb.walker.walkWaitTime::samples 23296 1387system.cpu1.dtb.walker.walkWaitTime::0 23296 100.00% 100.00% 1388system.cpu1.dtb.walker.walkWaitTime::total 23296 1389system.cpu1.dtb.walker.walkCompletionTime::samples 1833 1390system.cpu1.dtb.walker.walkCompletionTime::mean 12785.870158 1391system.cpu1.dtb.walker.walkCompletionTime::gmean 11578.247782 1392system.cpu1.dtb.walker.walkCompletionTime::stdev 15610.872723 1393system.cpu1.dtb.walker.walkCompletionTime::0-65535 1830 99.84% 99.84% 1394system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2 0.11% 99.95% 1395system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.05% 100.00% 1396system.cpu1.dtb.walker.walkCompletionTime::total 1833 1397system.cpu1.dtb.walker.walksPending::samples -1978443032 1398system.cpu1.dtb.walker.walksPending::0 -1978443032 100.00% 100.00% 1399system.cpu1.dtb.walker.walksPending::total -1978443032 1400system.cpu1.dtb.walker.walkPageSizes::4K 1317 71.85% 71.85% 1401system.cpu1.dtb.walker.walkPageSizes::1M 516 28.15% 100.00% 1402system.cpu1.dtb.walker.walkPageSizes::total 1833 1403system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 23296 1404system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 1405system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 23296 1406system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1833 1407system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 1408system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1833 1409system.cpu1.dtb.walker.walkRequestOrigin::total 25129 1410system.cpu1.dtb.inst_hits 0 1411system.cpu1.dtb.inst_misses 0 1412system.cpu1.dtb.read_hits 10529198 1413system.cpu1.dtb.read_misses 21069 1414system.cpu1.dtb.write_hits 6472938 1415system.cpu1.dtb.write_misses 2227 1416system.cpu1.dtb.flush_tlb 66 1417system.cpu1.dtb.flush_tlb_mva 917 1418system.cpu1.dtb.flush_tlb_mva_asid 0 1419system.cpu1.dtb.flush_tlb_asid 0 1420system.cpu1.dtb.flush_entries 1638 1421system.cpu1.dtb.align_faults 128 1422system.cpu1.dtb.prefetch_faults 280 1423system.cpu1.dtb.domain_faults 0 1424system.cpu1.dtb.perms_faults 174 1425system.cpu1.dtb.read_accesses 10550267 1426system.cpu1.dtb.write_accesses 6475165 1427system.cpu1.dtb.inst_accesses 0 1428system.cpu1.dtb.hits 17002136 1429system.cpu1.dtb.misses 23296 1430system.cpu1.dtb.accesses 17025432 1431system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848623849000 1432system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 1433system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 1434system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 1435system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 1436system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 1437system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 1438system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 1439system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 1440system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 1441system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 1442system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 1443system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 1444system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 1445system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 1446system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 1447system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 1448system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 1449system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 1450system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 1451system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 1452system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 1453system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 1454system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 1455system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 1456system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 1457system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 1458system.cpu1.istage2_mmu.stage2_tlb.hits 0 1459system.cpu1.istage2_mmu.stage2_tlb.misses 0 1460system.cpu1.istage2_mmu.stage2_tlb.accesses 0 1461system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848623849000 1462system.cpu1.itb.walker.walks 2043 1463system.cpu1.itb.walker.walksShort 2043 1464system.cpu1.itb.walker.walksShortTerminationLevel::Level1 145 1465system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1898 1466system.cpu1.itb.walker.walkWaitTime::samples 2043 1467system.cpu1.itb.walker.walkWaitTime::0 2043 100.00% 100.00% 1468system.cpu1.itb.walker.walkWaitTime::total 2043 1469system.cpu1.itb.walker.walkCompletionTime::samples 839 1470system.cpu1.itb.walker.walkCompletionTime::mean 11990.464839 1471system.cpu1.itb.walker.walkCompletionTime::gmean 11429.168642 1472system.cpu1.itb.walker.walkCompletionTime::stdev 4526.562247 1473system.cpu1.itb.walker.walkCompletionTime::4096-8191 132 15.73% 15.73% 1474system.cpu1.itb.walker.walkCompletionTime::8192-12287 566 67.46% 83.19% 1475system.cpu1.itb.walker.walkCompletionTime::12288-16383 80 9.54% 92.73% 1476system.cpu1.itb.walker.walkCompletionTime::16384-20479 15 1.79% 94.52% 1477system.cpu1.itb.walker.walkCompletionTime::20480-24575 16 1.91% 96.42% 1478system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 2.50% 98.93% 1479system.cpu1.itb.walker.walkCompletionTime::28672-32767 4 0.48% 99.40% 1480system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 99.52% 1481system.cpu1.itb.walker.walkCompletionTime::40960-45055 4 0.48% 100.00% 1482system.cpu1.itb.walker.walkCompletionTime::total 839 1483system.cpu1.itb.walker.walksPending::samples -1979056532 1484system.cpu1.itb.walker.walksPending::0 -1979056532 100.00% 100.00% 1485system.cpu1.itb.walker.walksPending::total -1979056532 1486system.cpu1.itb.walker.walkPageSizes::4K 704 83.91% 83.91% 1487system.cpu1.itb.walker.walkPageSizes::1M 135 16.09% 100.00% 1488system.cpu1.itb.walker.walkPageSizes::total 839 1489system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 1490system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2043 1491system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2043 1492system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 1493system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 839 1494system.cpu1.itb.walker.walkRequestOrigin_Completed::total 839 1495system.cpu1.itb.walker.walkRequestOrigin::total 2882 1496system.cpu1.itb.inst_hits 38615960 1497system.cpu1.itb.inst_misses 2043 1498system.cpu1.itb.read_hits 0 1499system.cpu1.itb.read_misses 0 1500system.cpu1.itb.write_hits 0 1501system.cpu1.itb.write_misses 0 1502system.cpu1.itb.flush_tlb 66 1503system.cpu1.itb.flush_tlb_mva 917 1504system.cpu1.itb.flush_tlb_mva_asid 0 1505system.cpu1.itb.flush_tlb_asid 0 1506system.cpu1.itb.flush_entries 839 1507system.cpu1.itb.align_faults 0 1508system.cpu1.itb.prefetch_faults 0 1509system.cpu1.itb.domain_faults 0 1510system.cpu1.itb.perms_faults 1023 1511system.cpu1.itb.read_accesses 0 1512system.cpu1.itb.write_accesses 0 1513system.cpu1.itb.inst_accesses 38618003 1514system.cpu1.itb.hits 38615960 1515system.cpu1.itb.misses 2043 1516system.cpu1.itb.accesses 38618003 1517system.cpu1.numPwrStateTransitions 5477 1518system.cpu1.pwrStateClkGateDist::samples 2739 1519system.cpu1.pwrStateClkGateDist::mean 1019579687.534502 1520system.cpu1.pwrStateClkGateDist::stdev 25827377354.972477 1521system.cpu1.pwrStateClkGateDist::underflows 1941 70.87% 70.87% 1522system.cpu1.pwrStateClkGateDist::1000-5e+10 794 28.99% 99.85% 1523system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% 1524system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% 1525system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% 1526system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% 1527system.cpu1.pwrStateClkGateDist::min_value 501 1528system.cpu1.pwrStateClkGateDist::max_value 949980339048 1529system.cpu1.pwrStateClkGateDist::total 2739 1530system.cpu1.pwrStateResidencyTicks::ON 55995084843 1531system.cpu1.pwrStateResidencyTicks::CLK_GATED 2792628764157 1532system.cpu1.numCycles 111993643 1533system.cpu1.numWorkItemsStarted 0 1534system.cpu1.numWorkItemsCompleted 0 1535system.cpu1.committedInsts 45058323 1536system.cpu1.committedOps 55122142 1537system.cpu1.discardedOps 4846390 1538system.cpu1.numFetchSuspends 2739 1539system.cpu1.quiesceCycles 5584580714 1540system.cpu1.cpi 2.485526 1541system.cpu1.ipc 0.402329 1542system.cpu1.op_class_0::No_OpClass 24 0.00% 0.00% 1543system.cpu1.op_class_0::IntAlu 38106633 69.13% 69.13% 1544system.cpu1.op_class_0::IntMult 43626 0.08% 69.21% 1545system.cpu1.op_class_0::IntDiv 0 0.00% 69.21% 1546system.cpu1.op_class_0::FloatAdd 0 0.00% 69.21% 1547system.cpu1.op_class_0::FloatCmp 0 0.00% 69.21% 1548system.cpu1.op_class_0::FloatCvt 0 0.00% 69.21% 1549system.cpu1.op_class_0::FloatMult 0 0.00% 69.21% 1550system.cpu1.op_class_0::FloatMultAcc 0 0.00% 69.21% 1551system.cpu1.op_class_0::FloatDiv 0 0.00% 69.21% 1552system.cpu1.op_class_0::FloatMisc 0 0.00% 69.21% 1553system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.21% 1554system.cpu1.op_class_0::SimdAdd 0 0.00% 69.21% 1555system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.21% 1556system.cpu1.op_class_0::SimdAlu 0 0.00% 69.21% 1557system.cpu1.op_class_0::SimdCmp 0 0.00% 69.21% 1558system.cpu1.op_class_0::SimdCvt 0 0.00% 69.21% 1559system.cpu1.op_class_0::SimdMisc 0 0.00% 69.21% 1560system.cpu1.op_class_0::SimdMult 0 0.00% 69.21% 1561system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.21% 1562system.cpu1.op_class_0::SimdShift 0 0.00% 69.21% 1563system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.21% 1564system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.21% 1565system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.21% 1566system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.21% 1567system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.21% 1568system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.21% 1569system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.21% 1570system.cpu1.op_class_0::SimdFloatMisc 3226 0.01% 69.22% 1571system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.22% 1572system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.22% 1573system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.22% 1574system.cpu1.op_class_0::MemRead 10387182 18.84% 88.06% 1575system.cpu1.op_class_0::MemWrite 6581451 11.94% 100.00% 1576system.cpu1.op_class_0::FloatMemRead 0 0.00% 100.00% 1577system.cpu1.op_class_0::FloatMemWrite 0 0.00% 100.00% 1578system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% 1579system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% 1580system.cpu1.op_class_0::total 55122142 1581system.cpu1.kern.inst.arm 0 1582system.cpu1.kern.inst.quiesce 2739 1583system.cpu1.tickCycles 90175152 1584system.cpu1.idleCycles 21818491 1585system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848623849000 1586system.cpu1.dcache.tags.replacements 157331 1587system.cpu1.dcache.tags.tagsinuse 476.847164 1588system.cpu1.dcache.tags.total_refs 16649796 1589system.cpu1.dcache.tags.sampled_refs 157683 1590system.cpu1.dcache.tags.avg_refs 105.590305 1591system.cpu1.dcache.tags.warmup_cycle 91198641000 1592system.cpu1.dcache.tags.occ_blocks::cpu1.data 476.847164 1593system.cpu1.dcache.tags.occ_percent::cpu1.data 0.931342 1594system.cpu1.dcache.tags.occ_percent::total 0.931342 1595system.cpu1.dcache.tags.occ_task_id_blocks::1024 352 1596system.cpu1.dcache.tags.age_task_id_blocks_1024::2 281 1597system.cpu1.dcache.tags.age_task_id_blocks_1024::3 71 1598system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500 1599system.cpu1.dcache.tags.tag_accesses 34038904 1600system.cpu1.dcache.tags.data_accesses 34038904 1601system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848623849000 1602system.cpu1.dcache.ReadReq_hits::cpu1.data 10204478 1603system.cpu1.dcache.ReadReq_hits::total 10204478 1604system.cpu1.dcache.WriteReq_hits::cpu1.data 6223179 1605system.cpu1.dcache.WriteReq_hits::total 6223179 1606system.cpu1.dcache.SoftPFReq_hits::cpu1.data 43363 1607system.cpu1.dcache.SoftPFReq_hits::total 43363 1608system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 71238 1609system.cpu1.dcache.LoadLockedReq_hits::total 71238 1610system.cpu1.dcache.StoreCondReq_hits::cpu1.data 62639 1611system.cpu1.dcache.StoreCondReq_hits::total 62639 1612system.cpu1.dcache.demand_hits::cpu1.data 16427657 1613system.cpu1.dcache.demand_hits::total 16427657 1614system.cpu1.dcache.overall_hits::cpu1.data 16471020 1615system.cpu1.dcache.overall_hits::total 16471020 1616system.cpu1.dcache.ReadReq_misses::cpu1.data 127297 1617system.cpu1.dcache.ReadReq_misses::total 127297 1618system.cpu1.dcache.WriteReq_misses::cpu1.data 122320 1619system.cpu1.dcache.WriteReq_misses::total 122320 1620system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24104 1621system.cpu1.dcache.SoftPFReq_misses::total 24104 1622system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16534 1623system.cpu1.dcache.LoadLockedReq_misses::total 16534 1624system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23351 1625system.cpu1.dcache.StoreCondReq_misses::total 23351 1626system.cpu1.dcache.demand_misses::cpu1.data 249617 1627system.cpu1.dcache.demand_misses::total 249617 1628system.cpu1.dcache.overall_misses::cpu1.data 273721 1629system.cpu1.dcache.overall_misses::total 273721 1630system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2189061000 1631system.cpu1.dcache.ReadReq_miss_latency::total 2189061000 1632system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3812195000 1633system.cpu1.dcache.WriteReq_miss_latency::total 3812195000 1634system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 322706000 1635system.cpu1.dcache.LoadLockedReq_miss_latency::total 322706000 1636system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 548331500 1637system.cpu1.dcache.StoreCondReq_miss_latency::total 548331500 1638system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 559500 1639system.cpu1.dcache.StoreCondFailReq_miss_latency::total 559500 1640system.cpu1.dcache.demand_miss_latency::cpu1.data 6001256000 1641system.cpu1.dcache.demand_miss_latency::total 6001256000 1642system.cpu1.dcache.overall_miss_latency::cpu1.data 6001256000 1643system.cpu1.dcache.overall_miss_latency::total 6001256000 1644system.cpu1.dcache.ReadReq_accesses::cpu1.data 10331775 1645system.cpu1.dcache.ReadReq_accesses::total 10331775 1646system.cpu1.dcache.WriteReq_accesses::cpu1.data 6345499 1647system.cpu1.dcache.WriteReq_accesses::total 6345499 1648system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 67467 1649system.cpu1.dcache.SoftPFReq_accesses::total 67467 1650system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87772 1651system.cpu1.dcache.LoadLockedReq_accesses::total 87772 1652system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85990 1653system.cpu1.dcache.StoreCondReq_accesses::total 85990 1654system.cpu1.dcache.demand_accesses::cpu1.data 16677274 1655system.cpu1.dcache.demand_accesses::total 16677274 1656system.cpu1.dcache.overall_accesses::cpu1.data 16744741 1657system.cpu1.dcache.overall_accesses::total 16744741 1658system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.012321 1659system.cpu1.dcache.ReadReq_miss_rate::total 0.012321 1660system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.019277 1661system.cpu1.dcache.WriteReq_miss_rate::total 0.019277 1662system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.357271 1663system.cpu1.dcache.SoftPFReq_miss_rate::total 0.357271 1664system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.188374 1665system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.188374 1666system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.271555 1667system.cpu1.dcache.StoreCondReq_miss_rate::total 0.271555 1668system.cpu1.dcache.demand_miss_rate::cpu1.data 0.014967 1669system.cpu1.dcache.demand_miss_rate::total 0.014967 1670system.cpu1.dcache.overall_miss_rate::cpu1.data 0.016347 1671system.cpu1.dcache.overall_miss_rate::total 0.016347 1672system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17196.485385 1673system.cpu1.dcache.ReadReq_avg_miss_latency::total 17196.485385 1674system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31165.753761 1675system.cpu1.dcache.WriteReq_avg_miss_latency::total 31165.753761 1676system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19517.721060 1677system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19517.721060 1678system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23482.142092 1679system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23482.142092 1680system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf 1681system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf 1682system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24041.856124 1683system.cpu1.dcache.demand_avg_miss_latency::total 24041.856124 1684system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21924.718966 1685system.cpu1.dcache.overall_avg_miss_latency::total 21924.718966 1686system.cpu1.dcache.blocked_cycles::no_mshrs 0 1687system.cpu1.dcache.blocked_cycles::no_targets 0 1688system.cpu1.dcache.blocked::no_mshrs 0 1689system.cpu1.dcache.blocked::no_targets 0 1690system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan 1691system.cpu1.dcache.avg_blocked_cycles::no_targets nan 1692system.cpu1.dcache.writebacks::writebacks 157331 1693system.cpu1.dcache.writebacks::total 157331 1694system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 4468 1695system.cpu1.dcache.ReadReq_mshr_hits::total 4468 1696system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 42295 1697system.cpu1.dcache.WriteReq_mshr_hits::total 42295 1698system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11754 1699system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11754 1700system.cpu1.dcache.demand_mshr_hits::cpu1.data 46763 1701system.cpu1.dcache.demand_mshr_hits::total 46763 1702system.cpu1.dcache.overall_mshr_hits::cpu1.data 46763 1703system.cpu1.dcache.overall_mshr_hits::total 46763 1704system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 122829 1705system.cpu1.dcache.ReadReq_mshr_misses::total 122829 1706system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 80025 1707system.cpu1.dcache.WriteReq_mshr_misses::total 80025 1708system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23596 1709system.cpu1.dcache.SoftPFReq_mshr_misses::total 23596 1710system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4780 1711system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4780 1712system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23351 1713system.cpu1.dcache.StoreCondReq_mshr_misses::total 23351 1714system.cpu1.dcache.demand_mshr_misses::cpu1.data 202854 1715system.cpu1.dcache.demand_mshr_misses::total 202854 1716system.cpu1.dcache.overall_mshr_misses::cpu1.data 226450 1717system.cpu1.dcache.overall_mshr_misses::total 226450 1718system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14406 1719system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14406 1720system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11728 1721system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11728 1722system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26134 1723system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26134 1724system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1984683000 1725system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1984683000 1726system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2311631500 1727system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2311631500 1728system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 417855500 1729system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 417855500 1730system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86123500 1731system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86123500 1732system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 524993500 1733system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 524993500 1734system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 546500 1735system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 546500 1736system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4296314500 1737system.cpu1.dcache.demand_mshr_miss_latency::total 4296314500 1738system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4714170000 1739system.cpu1.dcache.overall_mshr_miss_latency::total 4714170000 1740system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2490233000 1741system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2490233000 1742system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2490233000 1743system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2490233000 1744system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.011888 1745system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.011888 1746system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012611 1747system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.012611 1748system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.349741 1749system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.349741 1750system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054459 1751system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054459 1752system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.271555 1753system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.271555 1754system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.012163 1755system.cpu1.dcache.demand_mshr_miss_rate::total 0.012163 1756system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.013524 1757system.cpu1.dcache.overall_mshr_miss_rate::total 0.013524 1758system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16158.097843 1759system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16158.097843 1760system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28886.366760 1761system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28886.366760 1762system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17708.743007 1763system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17708.743007 1764system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18017.468619 1765system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18017.468619 1766system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22482.698814 1767system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22482.698814 1768system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf 1769system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf 1770system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21179.343272 1771system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21179.343272 1772system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20817.708103 1773system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20817.708103 1774system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172860.821880 1775system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172860.821880 1776system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95287.097268 1777system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95287.097268 1778system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848623849000 1779system.cpu1.icache.tags.replacements 872942 1780system.cpu1.icache.tags.tagsinuse 499.208587 1781system.cpu1.icache.tags.total_refs 37741446 1782system.cpu1.icache.tags.sampled_refs 873454 1783system.cpu1.icache.tags.avg_refs 43.209426 1784system.cpu1.icache.tags.warmup_cycle 72896771000 1785system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.208587 1786system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975017 1787system.cpu1.icache.tags.occ_percent::total 0.975017 1788system.cpu1.icache.tags.occ_task_id_blocks::1024 512 1789system.cpu1.icache.tags.age_task_id_blocks_1024::2 464 1790system.cpu1.icache.tags.age_task_id_blocks_1024::3 47 1791system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 1792system.cpu1.icache.tags.occ_task_id_percent::1024 1 1793system.cpu1.icache.tags.tag_accesses 78103254 1794system.cpu1.icache.tags.data_accesses 78103254 1795system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848623849000 1796system.cpu1.icache.ReadReq_hits::cpu1.inst 37741446 1797system.cpu1.icache.ReadReq_hits::total 37741446 1798system.cpu1.icache.demand_hits::cpu1.inst 37741446 1799system.cpu1.icache.demand_hits::total 37741446 1800system.cpu1.icache.overall_hits::cpu1.inst 37741446 1801system.cpu1.icache.overall_hits::total 37741446 1802system.cpu1.icache.ReadReq_misses::cpu1.inst 873454 1803system.cpu1.icache.ReadReq_misses::total 873454 1804system.cpu1.icache.demand_misses::cpu1.inst 873454 1805system.cpu1.icache.demand_misses::total 873454 1806system.cpu1.icache.overall_misses::cpu1.inst 873454 1807system.cpu1.icache.overall_misses::total 873454 1808system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8016929000 1809system.cpu1.icache.ReadReq_miss_latency::total 8016929000 1810system.cpu1.icache.demand_miss_latency::cpu1.inst 8016929000 1811system.cpu1.icache.demand_miss_latency::total 8016929000 1812system.cpu1.icache.overall_miss_latency::cpu1.inst 8016929000 1813system.cpu1.icache.overall_miss_latency::total 8016929000 1814system.cpu1.icache.ReadReq_accesses::cpu1.inst 38614900 1815system.cpu1.icache.ReadReq_accesses::total 38614900 1816system.cpu1.icache.demand_accesses::cpu1.inst 38614900 1817system.cpu1.icache.demand_accesses::total 38614900 1818system.cpu1.icache.overall_accesses::cpu1.inst 38614900 1819system.cpu1.icache.overall_accesses::total 38614900 1820system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022620 1821system.cpu1.icache.ReadReq_miss_rate::total 0.022620 1822system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022620 1823system.cpu1.icache.demand_miss_rate::total 0.022620 1824system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022620 1825system.cpu1.icache.overall_miss_rate::total 0.022620 1826system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9178.421531 1827system.cpu1.icache.ReadReq_avg_miss_latency::total 9178.421531 1828system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9178.421531 1829system.cpu1.icache.demand_avg_miss_latency::total 9178.421531 1830system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9178.421531 1831system.cpu1.icache.overall_avg_miss_latency::total 9178.421531 1832system.cpu1.icache.blocked_cycles::no_mshrs 0 1833system.cpu1.icache.blocked_cycles::no_targets 0 1834system.cpu1.icache.blocked::no_mshrs 0 1835system.cpu1.icache.blocked::no_targets 0 1836system.cpu1.icache.avg_blocked_cycles::no_mshrs nan 1837system.cpu1.icache.avg_blocked_cycles::no_targets nan 1838system.cpu1.icache.writebacks::writebacks 872942 1839system.cpu1.icache.writebacks::total 872942 1840system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 873454 1841system.cpu1.icache.ReadReq_mshr_misses::total 873454 1842system.cpu1.icache.demand_mshr_misses::cpu1.inst 873454 1843system.cpu1.icache.demand_mshr_misses::total 873454 1844system.cpu1.icache.overall_mshr_misses::cpu1.inst 873454 1845system.cpu1.icache.overall_mshr_misses::total 873454 1846system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 1847system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 1848system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 1849system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 1850system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7580202000 1851system.cpu1.icache.ReadReq_mshr_miss_latency::total 7580202000 1852system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7580202000 1853system.cpu1.icache.demand_mshr_miss_latency::total 7580202000 1854system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7580202000 1855system.cpu1.icache.overall_mshr_miss_latency::total 7580202000 1856system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11042500 1857system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 11042500 1858system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 11042500 1859system.cpu1.icache.overall_mshr_uncacheable_latency::total 11042500 1860system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022620 1861system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022620 1862system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022620 1863system.cpu1.icache.demand_mshr_miss_rate::total 0.022620 1864system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022620 1865system.cpu1.icache.overall_mshr_miss_rate::total 0.022620 1866system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8678.421531 1867system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8678.421531 1868system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8678.421531 1869system.cpu1.icache.demand_avg_mshr_miss_latency::total 8678.421531 1870system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8678.421531 1871system.cpu1.icache.overall_avg_mshr_miss_latency::total 8678.421531 1872system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98593.750000 1873system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 98593.750000 1874system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98593.750000 1875system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 98593.750000 1876system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848623849000 1877system.cpu1.l2cache.prefetcher.num_hwpf_issued 118133 1878system.cpu1.l2cache.prefetcher.pfIdentified 118165 1879system.cpu1.l2cache.prefetcher.pfBufferHit 27 1880system.cpu1.l2cache.prefetcher.pfInCache 0 1881system.cpu1.l2cache.prefetcher.pfRemovedFull 0 1882system.cpu1.l2cache.prefetcher.pfSpanPage 48899 1883system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848623849000 1884system.cpu1.l2cache.tags.replacements 37449 1885system.cpu1.l2cache.tags.tagsinuse 14754.261242 1886system.cpu1.l2cache.tags.total_refs 949403 1887system.cpu1.l2cache.tags.sampled_refs 52157 1888system.cpu1.l2cache.tags.avg_refs 18.202792 1889system.cpu1.l2cache.tags.warmup_cycle 0 1890system.cpu1.l2cache.tags.occ_blocks::writebacks 14416.237404 1891system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 38.337553 1892system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.132408 1893system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 298.553878 1894system.cpu1.l2cache.tags.occ_percent::writebacks 0.879897 1895system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002340 1896system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000069 1897system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.018222 1898system.cpu1.l2cache.tags.occ_percent::total 0.900529 1899system.cpu1.l2cache.tags.occ_task_id_blocks::1022 263 1900system.cpu1.l2cache.tags.occ_task_id_blocks::1023 80 1901system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14365 1902system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2 1903system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 22 1904system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 239 1905system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 1906system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 1907system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 58 1908system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1288 1909system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2922 1910system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10155 1911system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.016052 1912system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004883 1913system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.876770 1914system.cpu1.l2cache.tags.tag_accesses 35693448 1915system.cpu1.l2cache.tags.data_accesses 35693448 1916system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2848623849000 1917system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 23875 1918system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2548 1919system.cpu1.l2cache.ReadReq_hits::total 26423 1920system.cpu1.l2cache.WritebackDirty_hits::writebacks 95204 1921system.cpu1.l2cache.WritebackDirty_hits::total 95204 1922system.cpu1.l2cache.WritebackClean_hits::writebacks 916199 1923system.cpu1.l2cache.WritebackClean_hits::total 916199 1924system.cpu1.l2cache.ReadExReq_hits::cpu1.data 18135 1925system.cpu1.l2cache.ReadExReq_hits::total 18135 1926system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 844876 1927system.cpu1.l2cache.ReadCleanReq_hits::total 844876 1928system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 81478 1929system.cpu1.l2cache.ReadSharedReq_hits::total 81478 1930system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 23875 1931system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2548 1932system.cpu1.l2cache.demand_hits::cpu1.inst 844876 1933system.cpu1.l2cache.demand_hits::cpu1.data 99613 1934system.cpu1.l2cache.demand_hits::total 970912 1935system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 23875 1936system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2548 1937system.cpu1.l2cache.overall_hits::cpu1.inst 844876 1938system.cpu1.l2cache.overall_hits::cpu1.data 99613 1939system.cpu1.l2cache.overall_hits::total 970912 1940system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 800 1941system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 289 1942system.cpu1.l2cache.ReadReq_misses::total 1089 1943system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29346 1944system.cpu1.l2cache.UpgradeReq_misses::total 29346 1945system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23351 1946system.cpu1.l2cache.SCUpgradeReq_misses::total 23351 1947system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32545 1948system.cpu1.l2cache.ReadExReq_misses::total 32545 1949system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 28578 1950system.cpu1.l2cache.ReadCleanReq_misses::total 28578 1951system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69726 1952system.cpu1.l2cache.ReadSharedReq_misses::total 69726 1953system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 800 1954system.cpu1.l2cache.demand_misses::cpu1.itb.walker 289 1955system.cpu1.l2cache.demand_misses::cpu1.inst 28578 1956system.cpu1.l2cache.demand_misses::cpu1.data 102271 1957system.cpu1.l2cache.demand_misses::total 131938 1958system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 800 1959system.cpu1.l2cache.overall_misses::cpu1.itb.walker 289 1960system.cpu1.l2cache.overall_misses::cpu1.inst 28578 1961system.cpu1.l2cache.overall_misses::cpu1.data 102271 1962system.cpu1.l2cache.overall_misses::total 131938 1963system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 20317000 1964system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5721500 1965system.cpu1.l2cache.ReadReq_miss_latency::total 26038500 1966system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 7548500 1967system.cpu1.l2cache.UpgradeReq_miss_latency::total 7548500 1968system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 16857000 1969system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 16857000 1970system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 525500 1971system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 525500 1972system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1443665500 1973system.cpu1.l2cache.ReadExReq_miss_latency::total 1443665500 1974system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1151971000 1975system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1151971000 1976system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1718484993 1977system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1718484993 1978system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 20317000 1979system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5721500 1980system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1151971000 1981system.cpu1.l2cache.demand_miss_latency::cpu1.data 3162150493 1982system.cpu1.l2cache.demand_miss_latency::total 4340159993 1983system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 20317000 1984system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5721500 1985system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1151971000 1986system.cpu1.l2cache.overall_miss_latency::cpu1.data 3162150493 1987system.cpu1.l2cache.overall_miss_latency::total 4340159993 1988system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 24675 1989system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2837 1990system.cpu1.l2cache.ReadReq_accesses::total 27512 1991system.cpu1.l2cache.WritebackDirty_accesses::writebacks 95204 1992system.cpu1.l2cache.WritebackDirty_accesses::total 95204 1993system.cpu1.l2cache.WritebackClean_accesses::writebacks 916199 1994system.cpu1.l2cache.WritebackClean_accesses::total 916199 1995system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29346 1996system.cpu1.l2cache.UpgradeReq_accesses::total 29346 1997system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23351 1998system.cpu1.l2cache.SCUpgradeReq_accesses::total 23351 1999system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50680 2000system.cpu1.l2cache.ReadExReq_accesses::total 50680 2001system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 873454 2002system.cpu1.l2cache.ReadCleanReq_accesses::total 873454 2003system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 151204 2004system.cpu1.l2cache.ReadSharedReq_accesses::total 151204 2005system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 24675 2006system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2837 2007system.cpu1.l2cache.demand_accesses::cpu1.inst 873454 2008system.cpu1.l2cache.demand_accesses::cpu1.data 201884 2009system.cpu1.l2cache.demand_accesses::total 1102850 2010system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 24675 2011system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2837 2012system.cpu1.l2cache.overall_accesses::cpu1.inst 873454 2013system.cpu1.l2cache.overall_accesses::cpu1.data 201884 2014system.cpu1.l2cache.overall_accesses::total 1102850 2015system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.032421 2016system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.101868 2017system.cpu1.l2cache.ReadReq_miss_rate::total 0.039583 2018system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 2019system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 2020system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 2021system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 2022system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.642167 2023system.cpu1.l2cache.ReadExReq_miss_rate::total 0.642167 2024system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.032718 2025system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.032718 2026system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.461139 2027system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.461139 2028system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.032421 2029system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.101868 2030system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.032718 2031system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.506583 2032system.cpu1.l2cache.demand_miss_rate::total 0.119634 2033system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.032421 2034system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.101868 2035system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.032718 2036system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.506583 2037system.cpu1.l2cache.overall_miss_rate::total 0.119634 2038system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25396.250000 2039system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19797.577855 2040system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23910.468320 2041system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 257.224153 2042system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 257.224153 2043system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 721.896279 2044system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 721.896279 2045system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf 2046system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf 2047system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44359.056691 2048system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44359.056691 2049system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40309.713766 2050system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40309.713766 2051system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 24646.258110 2052system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 24646.258110 2053system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25396.250000 2054system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19797.577855 2055system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40309.713766 2056system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30919.327014 2057system.cpu1.l2cache.demand_avg_miss_latency::total 32895.450841 2058system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25396.250000 2059system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19797.577855 2060system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40309.713766 2061system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30919.327014 2062system.cpu1.l2cache.overall_avg_miss_latency::total 32895.450841 2063system.cpu1.l2cache.blocked_cycles::no_mshrs 0 2064system.cpu1.l2cache.blocked_cycles::no_targets 0 2065system.cpu1.l2cache.blocked::no_mshrs 0 2066system.cpu1.l2cache.blocked::no_targets 0 2067system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan 2068system.cpu1.l2cache.avg_blocked_cycles::no_targets nan 2069system.cpu1.l2cache.unused_prefetches 608 2070system.cpu1.l2cache.writebacks::writebacks 29316 2071system.cpu1.l2cache.writebacks::total 29316 2072system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 3 2073system.cpu1.l2cache.ReadReq_mshr_hits::total 3 2074system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 183 2075system.cpu1.l2cache.ReadExReq_mshr_hits::total 183 2076system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 9 2077system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 9 2078system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 42 2079system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 42 2080system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 3 2081system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 9 2082system.cpu1.l2cache.demand_mshr_hits::cpu1.data 225 2083system.cpu1.l2cache.demand_mshr_hits::total 237 2084system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 3 2085system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 9 2086system.cpu1.l2cache.overall_mshr_hits::cpu1.data 225 2087system.cpu1.l2cache.overall_mshr_hits::total 237 2088system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 800 2089system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 286 2090system.cpu1.l2cache.ReadReq_mshr_misses::total 1086 2091system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 19599 2092system.cpu1.l2cache.HardPFReq_mshr_misses::total 19599 2093system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29346 2094system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29346 2095system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23351 2096system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23351 2097system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 32362 2098system.cpu1.l2cache.ReadExReq_mshr_misses::total 32362 2099system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 28569 2100system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 28569 2101system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69684 2102system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69684 2103system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 800 2104system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 286 2105system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 28569 2106system.cpu1.l2cache.demand_mshr_misses::cpu1.data 102046 2107system.cpu1.l2cache.demand_mshr_misses::total 131701 2108system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 800 2109system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 286 2110system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 28569 2111system.cpu1.l2cache.overall_mshr_misses::cpu1.data 102046 2112system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 19599 2113system.cpu1.l2cache.overall_mshr_misses::total 151300 2114system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 2115system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14406 2116system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14518 2117system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11728 2118system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11728 2119system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 2120system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26134 2121system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26246 2122system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 15517000 2123system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3959500 2124system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 19476500 2125system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 753093878 2126system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 753093878 2127system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 447116000 2128system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 447116000 2129system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 348719500 2130system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 348719500 2131system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 447500 2132system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 447500 2133system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1228645000 2134system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1228645000 2135system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 980270500 2136system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 980270500 2137system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1298411493 2138system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1298411493 2139system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 15517000 2140system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3959500 2141system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 980270500 2142system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2527056493 2143system.cpu1.l2cache.demand_mshr_miss_latency::total 3526803493 2144system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 15517000 2145system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3959500 2146system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 980270500 2147system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2527056493 2148system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 753093878 2149system.cpu1.l2cache.overall_mshr_miss_latency::total 4279897371 2150system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10146500 2151system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2374963000 2152system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2385109500 2153system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10146500 2154system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2374963000 2155system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2385109500 2156system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.032421 2157system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.100811 2158system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.039474 2159system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf 2160system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf 2161system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 2162system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 2163system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 2164system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 2165system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.638556 2166system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.638556 2167system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.032708 2168system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.032708 2169system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.460861 2170system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.460861 2171system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.032421 2172system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.100811 2173system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.032708 2174system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.505468 2175system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119419 2176system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.032421 2177system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.100811 2178system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.032708 2179system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.505468 2180system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf 2181system.cpu1.l2cache.overall_mshr_miss_rate::total 0.137190 2182system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19396.250000 2183system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13844.405594 2184system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17934.162063 2185system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38425.117506 2186system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38425.117506 2187system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15236.011722 2188system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15236.011722 2189system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14933.814398 2190system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14933.814398 2191system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf 2192system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf 2193system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37965.669613 2194system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37965.669613 2195system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34312.384053 2196system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34312.384053 2197system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18632.849621 2198system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18632.849621 2199system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19396.250000 2200system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13844.405594 2201system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34312.384053 2202system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24763.895626 2203system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26778.866470 2204system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19396.250000 2205system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13844.405594 2206system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34312.384053 2207system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24763.895626 2208system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38425.117506 2209system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28287.490886 2210system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90593.750000 2211system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164859.294738 2212system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164286.368646 2213system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90593.750000 2214system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90876.367950 2215system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90875.161929 2216system.cpu1.toL2Bus.snoop_filter.tot_requests 2165698 2217system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1090387 2218system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18868 2219system.cpu1.toL2Bus.snoop_filter.tot_snoops 115904 2220system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 107947 2221system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 7957 2222system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848623849000 2223system.cpu1.toL2Bus.trans_dist::ReadReq 45297 2224system.cpu1.toL2Bus.trans_dist::ReadResp 1106851 2225system.cpu1.toL2Bus.trans_dist::WriteReq 11728 2226system.cpu1.toL2Bus.trans_dist::WriteResp 11728 2227system.cpu1.toL2Bus.trans_dist::WritebackDirty 126681 2228system.cpu1.toL2Bus.trans_dist::WritebackClean 935068 2229system.cpu1.toL2Bus.trans_dist::CleanEvict 26505 2230system.cpu1.toL2Bus.trans_dist::HardPFReq 23783 2231system.cpu1.toL2Bus.trans_dist::UpgradeReq 72033 2232system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41786 2233system.cpu1.toL2Bus.trans_dist::UpgradeResp 84874 2234system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 18 2235system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 31 2236system.cpu1.toL2Bus.trans_dist::ReadExReq 57990 2237system.cpu1.toL2Bus.trans_dist::ReadExResp 55336 2238system.cpu1.toL2Bus.trans_dist::ReadCleanReq 873454 2239system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263190 2240system.cpu1.toL2Bus.trans_dist::InvalidateReq 83 2241system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2620074 2242system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 792520 2243system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6778 2244system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 51513 2245system.cpu1.toL2Bus.pkt_count::total 3470885 2246system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 111776512 2247system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25752830 2248system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11348 2249system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 98700 2250system.cpu1.toL2Bus.pkt_size::total 137639390 2251system.cpu1.toL2Bus.snoops 339311 2252system.cpu1.toL2Bus.snoopTraffic 4688012 2253system.cpu1.toL2Bus.snoop_fanout::samples 1447344 2254system.cpu1.toL2Bus.snoop_fanout::mean 0.103724 2255system.cpu1.toL2Bus.snoop_fanout::stdev 0.322430 2256system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% 2257system.cpu1.toL2Bus.snoop_fanout::0 1305176 90.18% 90.18% 2258system.cpu1.toL2Bus.snoop_fanout::1 134211 9.27% 99.45% 2259system.cpu1.toL2Bus.snoop_fanout::2 7957 0.55% 100.00% 2260system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% 2261system.cpu1.toL2Bus.snoop_fanout::min_value 0 2262system.cpu1.toL2Bus.snoop_fanout::max_value 2 2263system.cpu1.toL2Bus.snoop_fanout::total 1447344 2264system.cpu1.toL2Bus.reqLayer0.occupancy 2143805992 2265system.cpu1.toL2Bus.reqLayer0.utilization 0.1 2266system.cpu1.toL2Bus.snoopLayer0.occupancy 78479642 2267system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 2268system.cpu1.toL2Bus.respLayer0.occupancy 1310404888 2269system.cpu1.toL2Bus.respLayer0.utilization 0.0 2270system.cpu1.toL2Bus.respLayer1.occupancy 351319768 2271system.cpu1.toL2Bus.respLayer1.utilization 0.0 2272system.cpu1.toL2Bus.respLayer2.occupancy 3943495 2273system.cpu1.toL2Bus.respLayer2.utilization 0.0 2274system.cpu1.toL2Bus.respLayer3.occupancy 26851972 2275system.cpu1.toL2Bus.respLayer3.utilization 0.0 2276system.iobus.pwrStateResidencyTicks::UNDEFINED 2848623849000 2277system.iobus.trans_dist::ReadReq 31007 2278system.iobus.trans_dist::ReadResp 31007 2279system.iobus.trans_dist::WriteReq 59424 2280system.iobus.trans_dist::WriteResp 59424 2281system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 2282system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 2283system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 2284system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 2285system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 2286system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 2287system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 2288system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 2289system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 2290system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 2291system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 2292system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 2293system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 2294system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 2295system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 2296system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 2297system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 2298system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 2299system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 2300system.iobus.pkt_count_system.bridge.master::total 107912 2301system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72950 2302system.iobus.pkt_count_system.realview.ide.dma::total 72950 2303system.iobus.pkt_count::total 180862 2304system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 2305system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 2306system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 2307system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 2308system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 2309system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 2310system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 2311system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 2312system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 2313system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 2314system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 2315system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 2316system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 2317system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 2318system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 2319system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 2320system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 2321system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 2322system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 2323system.iobus.pkt_size_system.bridge.master::total 162802 2324system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321240 2325system.iobus.pkt_size_system.realview.ide.dma::total 2321240 2326system.iobus.pkt_size::total 2484042 2327system.iobus.reqLayer0.occupancy 48434001 2328system.iobus.reqLayer0.utilization 0.0 2329system.iobus.reqLayer1.occupancy 110500 2330system.iobus.reqLayer1.utilization 0.0 2331system.iobus.reqLayer2.occupancy 324500 2332system.iobus.reqLayer2.utilization 0.0 2333system.iobus.reqLayer3.occupancy 28500 2334system.iobus.reqLayer3.utilization 0.0 2335system.iobus.reqLayer4.occupancy 12500 2336system.iobus.reqLayer4.utilization 0.0 2337system.iobus.reqLayer7.occupancy 85500 2338system.iobus.reqLayer7.utilization 0.0 2339system.iobus.reqLayer8.occupancy 602500 2340system.iobus.reqLayer8.utilization 0.0 2341system.iobus.reqLayer10.occupancy 19500 2342system.iobus.reqLayer10.utilization 0.0 2343system.iobus.reqLayer13.occupancy 11000 2344system.iobus.reqLayer13.utilization 0.0 2345system.iobus.reqLayer14.occupancy 8500 2346system.iobus.reqLayer14.utilization 0.0 2347system.iobus.reqLayer15.occupancy 8500 2348system.iobus.reqLayer15.utilization 0.0 2349system.iobus.reqLayer16.occupancy 47500 2350system.iobus.reqLayer16.utilization 0.0 2351system.iobus.reqLayer17.occupancy 9500 2352system.iobus.reqLayer17.utilization 0.0 2353system.iobus.reqLayer18.occupancy 8000 2354system.iobus.reqLayer18.utilization 0.0 2355system.iobus.reqLayer19.occupancy 2500 2356system.iobus.reqLayer19.utilization 0.0 2357system.iobus.reqLayer20.occupancy 9000 2358system.iobus.reqLayer20.utilization 0.0 2359system.iobus.reqLayer21.occupancy 8500 2360system.iobus.reqLayer21.utilization 0.0 2361system.iobus.reqLayer23.occupancy 6368000 2362system.iobus.reqLayer23.utilization 0.0 2363system.iobus.reqLayer24.occupancy 39055001 2364system.iobus.reqLayer24.utilization 0.0 2365system.iobus.reqLayer25.occupancy 187796294 2366system.iobus.reqLayer25.utilization 0.0 2367system.iobus.respLayer0.occupancy 84712000 2368system.iobus.respLayer0.utilization 0.0 2369system.iobus.respLayer3.occupancy 36774000 2370system.iobus.respLayer3.utilization 0.0 2371system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848623849000 2372system.iocache.tags.replacements 36457 2373system.iocache.tags.tagsinuse 14.472725 2374system.iocache.tags.total_refs 0 2375system.iocache.tags.sampled_refs 36473 2376system.iocache.tags.avg_refs 0 2377system.iocache.tags.warmup_cycle 271902155000 2378system.iocache.tags.occ_blocks::realview.ide 14.472725 2379system.iocache.tags.occ_percent::realview.ide 0.904545 2380system.iocache.tags.occ_percent::total 0.904545 2381system.iocache.tags.occ_task_id_blocks::1023 16 2382system.iocache.tags.age_task_id_blocks_1023::3 16 2383system.iocache.tags.occ_task_id_percent::1023 1 2384system.iocache.tags.tag_accesses 328275 2385system.iocache.tags.data_accesses 328275 2386system.iocache.pwrStateResidencyTicks::UNDEFINED 2848623849000 2387system.iocache.ReadReq_misses::realview.ide 251 2388system.iocache.ReadReq_misses::total 251 2389system.iocache.WriteLineReq_misses::realview.ide 36224 2390system.iocache.WriteLineReq_misses::total 36224 2391system.iocache.demand_misses::realview.ide 36475 2392system.iocache.demand_misses::total 36475 2393system.iocache.overall_misses::realview.ide 36475 2394system.iocache.overall_misses::total 36475 2395system.iocache.ReadReq_miss_latency::realview.ide 33525875 2396system.iocache.ReadReq_miss_latency::total 33525875 2397system.iocache.WriteLineReq_miss_latency::realview.ide 4369037419 2398system.iocache.WriteLineReq_miss_latency::total 4369037419 2399system.iocache.demand_miss_latency::realview.ide 4402563294 2400system.iocache.demand_miss_latency::total 4402563294 2401system.iocache.overall_miss_latency::realview.ide 4402563294 2402system.iocache.overall_miss_latency::total 4402563294 2403system.iocache.ReadReq_accesses::realview.ide 251 2404system.iocache.ReadReq_accesses::total 251 2405system.iocache.WriteLineReq_accesses::realview.ide 36224 2406system.iocache.WriteLineReq_accesses::total 36224 2407system.iocache.demand_accesses::realview.ide 36475 2408system.iocache.demand_accesses::total 36475 2409system.iocache.overall_accesses::realview.ide 36475 2410system.iocache.overall_accesses::total 36475 2411system.iocache.ReadReq_miss_rate::realview.ide 1 2412system.iocache.ReadReq_miss_rate::total 1 2413system.iocache.WriteLineReq_miss_rate::realview.ide 1 2414system.iocache.WriteLineReq_miss_rate::total 1 2415system.iocache.demand_miss_rate::realview.ide 1 2416system.iocache.demand_miss_rate::total 1 2417system.iocache.overall_miss_rate::realview.ide 1 2418system.iocache.overall_miss_rate::total 1 2419system.iocache.ReadReq_avg_miss_latency::realview.ide 133569.223108 2420system.iocache.ReadReq_avg_miss_latency::total 133569.223108 2421system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120611.677866 2422system.iocache.WriteLineReq_avg_miss_latency::total 120611.677866 2423system.iocache.demand_avg_miss_latency::realview.ide 120700.844249 2424system.iocache.demand_avg_miss_latency::total 120700.844249 2425system.iocache.overall_avg_miss_latency::realview.ide 120700.844249 2426system.iocache.overall_avg_miss_latency::total 120700.844249 2427system.iocache.blocked_cycles::no_mshrs 498 2428system.iocache.blocked_cycles::no_targets 0 2429system.iocache.blocked::no_mshrs 4 2430system.iocache.blocked::no_targets 0 2431system.iocache.avg_blocked_cycles::no_mshrs 124.500000 2432system.iocache.avg_blocked_cycles::no_targets nan 2433system.iocache.writebacks::writebacks 36206 2434system.iocache.writebacks::total 36206 2435system.iocache.ReadReq_mshr_misses::realview.ide 251 2436system.iocache.ReadReq_mshr_misses::total 251 2437system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 2438system.iocache.WriteLineReq_mshr_misses::total 36224 2439system.iocache.demand_mshr_misses::realview.ide 36475 2440system.iocache.demand_mshr_misses::total 36475 2441system.iocache.overall_mshr_misses::realview.ide 36475 2442system.iocache.overall_mshr_misses::total 36475 2443system.iocache.ReadReq_mshr_miss_latency::realview.ide 20975875 2444system.iocache.ReadReq_mshr_miss_latency::total 20975875 2445system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2555943544 2446system.iocache.WriteLineReq_mshr_miss_latency::total 2555943544 2447system.iocache.demand_mshr_miss_latency::realview.ide 2576919419 2448system.iocache.demand_mshr_miss_latency::total 2576919419 2449system.iocache.overall_mshr_miss_latency::realview.ide 2576919419 2450system.iocache.overall_mshr_miss_latency::total 2576919419 2451system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 2452system.iocache.ReadReq_mshr_miss_rate::total 1 2453system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 2454system.iocache.WriteLineReq_mshr_miss_rate::total 1 2455system.iocache.demand_mshr_miss_rate::realview.ide 1 2456system.iocache.demand_mshr_miss_rate::total 1 2457system.iocache.overall_mshr_miss_rate::realview.ide 1 2458system.iocache.overall_mshr_miss_rate::total 1 2459system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 83569.223108 2460system.iocache.ReadReq_avg_mshr_miss_latency::total 83569.223108 2461system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70559.395539 2462system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70559.395539 2463system.iocache.demand_avg_mshr_miss_latency::realview.ide 70648.921700 2464system.iocache.demand_avg_mshr_miss_latency::total 70648.921700 2465system.iocache.overall_avg_mshr_miss_latency::realview.ide 70648.921700 2466system.iocache.overall_avg_mshr_miss_latency::total 70648.921700 2467system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848623849000 2468system.l2c.tags.replacements 143741 2469system.l2c.tags.tagsinuse 65154.311033 2470system.l2c.tags.total_refs 605938 2471system.l2c.tags.sampled_refs 209220 2472system.l2c.tags.avg_refs 2.896176 2473system.l2c.tags.warmup_cycle 94462980000 2474system.l2c.tags.occ_blocks::writebacks 6696.148123 2475system.l2c.tags.occ_blocks::cpu0.dtb.walker 85.662080 2476system.l2c.tags.occ_blocks::cpu0.itb.walker 0.029895 2477system.l2c.tags.occ_blocks::cpu0.inst 8724.046305 2478system.l2c.tags.occ_blocks::cpu0.data 6708.264318 2479system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34991.261911 2480system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.950937 2481system.l2c.tags.occ_blocks::cpu1.inst 2215.206936 2482system.l2c.tags.occ_blocks::cpu1.data 3461.157373 2483system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2257.583155 2484system.l2c.tags.occ_percent::writebacks 0.102175 2485system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001307 2486system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 2487system.l2c.tags.occ_percent::cpu0.inst 0.133118 2488system.l2c.tags.occ_percent::cpu0.data 0.102360 2489system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.533924 2490system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000228 2491system.l2c.tags.occ_percent::cpu1.inst 0.033801 2492system.l2c.tags.occ_percent::cpu1.data 0.052813 2493system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034448 2494system.l2c.tags.occ_percent::total 0.994176 2495system.l2c.tags.occ_task_id_blocks::1022 32741 2496system.l2c.tags.occ_task_id_blocks::1023 70 2497system.l2c.tags.occ_task_id_blocks::1024 32668 2498system.l2c.tags.age_task_id_blocks_1022::2 135 2499system.l2c.tags.age_task_id_blocks_1022::3 5068 2500system.l2c.tags.age_task_id_blocks_1022::4 27538 2501system.l2c.tags.age_task_id_blocks_1023::3 1 2502system.l2c.tags.age_task_id_blocks_1023::4 69 2503system.l2c.tags.age_task_id_blocks_1024::0 4 2504system.l2c.tags.age_task_id_blocks_1024::1 1 2505system.l2c.tags.age_task_id_blocks_1024::2 118 2506system.l2c.tags.age_task_id_blocks_1024::3 1804 2507system.l2c.tags.age_task_id_blocks_1024::4 30741 2508system.l2c.tags.occ_task_id_percent::1022 0.499588 2509system.l2c.tags.occ_task_id_percent::1023 0.001068 2510system.l2c.tags.occ_task_id_percent::1024 0.498474 2511system.l2c.tags.tag_accesses 6808442 2512system.l2c.tags.data_accesses 6808442 2513system.l2c.pwrStateResidencyTicks::UNDEFINED 2848623849000 2514system.l2c.WritebackDirty_hits::writebacks 266227 2515system.l2c.WritebackDirty_hits::total 266227 2516system.l2c.UpgradeReq_hits::cpu0.data 43718 2517system.l2c.UpgradeReq_hits::cpu1.data 4453 2518system.l2c.UpgradeReq_hits::total 48171 2519system.l2c.SCUpgradeReq_hits::cpu0.data 2952 2520system.l2c.SCUpgradeReq_hits::cpu1.data 2121 2521system.l2c.SCUpgradeReq_hits::total 5073 2522system.l2c.ReadExReq_hits::cpu0.data 4385 2523system.l2c.ReadExReq_hits::cpu1.data 1232 2524system.l2c.ReadExReq_hits::total 5617 2525system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 478 2526system.l2c.ReadSharedReq_hits::cpu0.itb.walker 82 2527system.l2c.ReadSharedReq_hits::cpu0.inst 72769 2528system.l2c.ReadSharedReq_hits::cpu0.data 66048 2529system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 48713 2530system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 82 2531system.l2c.ReadSharedReq_hits::cpu1.itb.walker 9 2532system.l2c.ReadSharedReq_hits::cpu1.inst 24997 2533system.l2c.ReadSharedReq_hits::cpu1.data 8438 2534system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3692 2535system.l2c.ReadSharedReq_hits::total 225308 2536system.l2c.demand_hits::cpu0.dtb.walker 478 2537system.l2c.demand_hits::cpu0.itb.walker 82 2538system.l2c.demand_hits::cpu0.inst 72769 2539system.l2c.demand_hits::cpu0.data 70433 2540system.l2c.demand_hits::cpu0.l2cache.prefetcher 48713 2541system.l2c.demand_hits::cpu1.dtb.walker 82 2542system.l2c.demand_hits::cpu1.itb.walker 9 2543system.l2c.demand_hits::cpu1.inst 24997 2544system.l2c.demand_hits::cpu1.data 9670 2545system.l2c.demand_hits::cpu1.l2cache.prefetcher 3692 2546system.l2c.demand_hits::total 230925 2547system.l2c.overall_hits::cpu0.dtb.walker 478 2548system.l2c.overall_hits::cpu0.itb.walker 82 2549system.l2c.overall_hits::cpu0.inst 72769 2550system.l2c.overall_hits::cpu0.data 70433 2551system.l2c.overall_hits::cpu0.l2cache.prefetcher 48713 2552system.l2c.overall_hits::cpu1.dtb.walker 82 2553system.l2c.overall_hits::cpu1.itb.walker 9 2554system.l2c.overall_hits::cpu1.inst 24997 2555system.l2c.overall_hits::cpu1.data 9670 2556system.l2c.overall_hits::cpu1.l2cache.prefetcher 3692 2557system.l2c.overall_hits::total 230925 2558system.l2c.UpgradeReq_misses::cpu0.data 467 2559system.l2c.UpgradeReq_misses::cpu1.data 174 2560system.l2c.UpgradeReq_misses::total 641 2561system.l2c.SCUpgradeReq_misses::cpu0.data 50 2562system.l2c.SCUpgradeReq_misses::cpu1.data 72 2563system.l2c.SCUpgradeReq_misses::total 122 2564system.l2c.ReadExReq_misses::cpu0.data 11403 2565system.l2c.ReadExReq_misses::cpu1.data 8599 2566system.l2c.ReadExReq_misses::total 20002 2567system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 149 2568system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 2569system.l2c.ReadSharedReq_misses::cpu0.inst 22795 2570system.l2c.ReadSharedReq_misses::cpu0.data 9975 2571system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134395 2572system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 20 2573system.l2c.ReadSharedReq_misses::cpu1.inst 3572 2574system.l2c.ReadSharedReq_misses::cpu1.data 1758 2575system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5239 2576system.l2c.ReadSharedReq_misses::total 177904 2577system.l2c.demand_misses::cpu0.dtb.walker 149 2578system.l2c.demand_misses::cpu0.itb.walker 1 2579system.l2c.demand_misses::cpu0.inst 22795 2580system.l2c.demand_misses::cpu0.data 21378 2581system.l2c.demand_misses::cpu0.l2cache.prefetcher 134395 2582system.l2c.demand_misses::cpu1.dtb.walker 20 2583system.l2c.demand_misses::cpu1.inst 3572 2584system.l2c.demand_misses::cpu1.data 10357 2585system.l2c.demand_misses::cpu1.l2cache.prefetcher 5239 2586system.l2c.demand_misses::total 197906 2587system.l2c.overall_misses::cpu0.dtb.walker 149 2588system.l2c.overall_misses::cpu0.itb.walker 1 2589system.l2c.overall_misses::cpu0.inst 22795 2590system.l2c.overall_misses::cpu0.data 21378 2591system.l2c.overall_misses::cpu0.l2cache.prefetcher 134395 2592system.l2c.overall_misses::cpu1.dtb.walker 20 2593system.l2c.overall_misses::cpu1.inst 3572 2594system.l2c.overall_misses::cpu1.data 10357 2595system.l2c.overall_misses::cpu1.l2cache.prefetcher 5239 2596system.l2c.overall_misses::total 197906 2597system.l2c.UpgradeReq_miss_latency::cpu0.data 8660500 2598system.l2c.UpgradeReq_miss_latency::cpu1.data 789500 2599system.l2c.UpgradeReq_miss_latency::total 9450000 2600system.l2c.SCUpgradeReq_miss_latency::cpu0.data 536500 2601system.l2c.SCUpgradeReq_miss_latency::cpu1.data 199000 2602system.l2c.SCUpgradeReq_miss_latency::total 735500 2603system.l2c.ReadExReq_miss_latency::cpu0.data 1591551500 2604system.l2c.ReadExReq_miss_latency::cpu1.data 819698500 2605system.l2c.ReadExReq_miss_latency::total 2411250000 2606system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 21194000 2607system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 90000 2608system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2323515000 2609system.l2c.ReadSharedReq_miss_latency::cpu0.data 1219999500 2610system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 16143455282 2611system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 4023000 2612system.l2c.ReadSharedReq_miss_latency::cpu1.inst 381119000 2613system.l2c.ReadSharedReq_miss_latency::cpu1.data 259897000 2614system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 675104910 2615system.l2c.ReadSharedReq_miss_latency::total 21028397692 2616system.l2c.demand_miss_latency::cpu0.dtb.walker 21194000 2617system.l2c.demand_miss_latency::cpu0.itb.walker 90000 2618system.l2c.demand_miss_latency::cpu0.inst 2323515000 2619system.l2c.demand_miss_latency::cpu0.data 2811551000 2620system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 16143455282 2621system.l2c.demand_miss_latency::cpu1.dtb.walker 4023000 2622system.l2c.demand_miss_latency::cpu1.inst 381119000 2623system.l2c.demand_miss_latency::cpu1.data 1079595500 2624system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 675104910 2625system.l2c.demand_miss_latency::total 23439647692 2626system.l2c.overall_miss_latency::cpu0.dtb.walker 21194000 2627system.l2c.overall_miss_latency::cpu0.itb.walker 90000 2628system.l2c.overall_miss_latency::cpu0.inst 2323515000 2629system.l2c.overall_miss_latency::cpu0.data 2811551000 2630system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 16143455282 2631system.l2c.overall_miss_latency::cpu1.dtb.walker 4023000 2632system.l2c.overall_miss_latency::cpu1.inst 381119000 2633system.l2c.overall_miss_latency::cpu1.data 1079595500 2634system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 675104910 2635system.l2c.overall_miss_latency::total 23439647692 2636system.l2c.WritebackDirty_accesses::writebacks 266227 2637system.l2c.WritebackDirty_accesses::total 266227 2638system.l2c.UpgradeReq_accesses::cpu0.data 44185 2639system.l2c.UpgradeReq_accesses::cpu1.data 4627 2640system.l2c.UpgradeReq_accesses::total 48812 2641system.l2c.SCUpgradeReq_accesses::cpu0.data 3002 2642system.l2c.SCUpgradeReq_accesses::cpu1.data 2193 2643system.l2c.SCUpgradeReq_accesses::total 5195 2644system.l2c.ReadExReq_accesses::cpu0.data 15788 2645system.l2c.ReadExReq_accesses::cpu1.data 9831 2646system.l2c.ReadExReq_accesses::total 25619 2647system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 627 2648system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 83 2649system.l2c.ReadSharedReq_accesses::cpu0.inst 95564 2650system.l2c.ReadSharedReq_accesses::cpu0.data 76023 2651system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 183108 2652system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 102 2653system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 9 2654system.l2c.ReadSharedReq_accesses::cpu1.inst 28569 2655system.l2c.ReadSharedReq_accesses::cpu1.data 10196 2656system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8931 2657system.l2c.ReadSharedReq_accesses::total 403212 2658system.l2c.demand_accesses::cpu0.dtb.walker 627 2659system.l2c.demand_accesses::cpu0.itb.walker 83 2660system.l2c.demand_accesses::cpu0.inst 95564 2661system.l2c.demand_accesses::cpu0.data 91811 2662system.l2c.demand_accesses::cpu0.l2cache.prefetcher 183108 2663system.l2c.demand_accesses::cpu1.dtb.walker 102 2664system.l2c.demand_accesses::cpu1.itb.walker 9 2665system.l2c.demand_accesses::cpu1.inst 28569 2666system.l2c.demand_accesses::cpu1.data 20027 2667system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8931 2668system.l2c.demand_accesses::total 428831 2669system.l2c.overall_accesses::cpu0.dtb.walker 627 2670system.l2c.overall_accesses::cpu0.itb.walker 83 2671system.l2c.overall_accesses::cpu0.inst 95564 2672system.l2c.overall_accesses::cpu0.data 91811 2673system.l2c.overall_accesses::cpu0.l2cache.prefetcher 183108 2674system.l2c.overall_accesses::cpu1.dtb.walker 102 2675system.l2c.overall_accesses::cpu1.itb.walker 9 2676system.l2c.overall_accesses::cpu1.inst 28569 2677system.l2c.overall_accesses::cpu1.data 20027 2678system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8931 2679system.l2c.overall_accesses::total 428831 2680system.l2c.UpgradeReq_miss_rate::cpu0.data 0.010569 2681system.l2c.UpgradeReq_miss_rate::cpu1.data 0.037605 2682system.l2c.UpgradeReq_miss_rate::total 0.013132 2683system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.016656 2684system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.032832 2685system.l2c.SCUpgradeReq_miss_rate::total 0.023484 2686system.l2c.ReadExReq_miss_rate::cpu0.data 0.722257 2687system.l2c.ReadExReq_miss_rate::cpu1.data 0.874682 2688system.l2c.ReadExReq_miss_rate::total 0.780749 2689system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.237640 2690system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.012048 2691system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.238531 2692system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.131210 2693system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.733966 2694system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.196078 2695system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.125031 2696system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.172421 2697system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.586608 2698system.l2c.ReadSharedReq_miss_rate::total 0.441217 2699system.l2c.demand_miss_rate::cpu0.dtb.walker 0.237640 2700system.l2c.demand_miss_rate::cpu0.itb.walker 0.012048 2701system.l2c.demand_miss_rate::cpu0.inst 0.238531 2702system.l2c.demand_miss_rate::cpu0.data 0.232848 2703system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.733966 2704system.l2c.demand_miss_rate::cpu1.dtb.walker 0.196078 2705system.l2c.demand_miss_rate::cpu1.inst 0.125031 2706system.l2c.demand_miss_rate::cpu1.data 0.517152 2707system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.586608 2708system.l2c.demand_miss_rate::total 0.461501 2709system.l2c.overall_miss_rate::cpu0.dtb.walker 0.237640 2710system.l2c.overall_miss_rate::cpu0.itb.walker 0.012048 2711system.l2c.overall_miss_rate::cpu0.inst 0.238531 2712system.l2c.overall_miss_rate::cpu0.data 0.232848 2713system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.733966 2714system.l2c.overall_miss_rate::cpu1.dtb.walker 0.196078 2715system.l2c.overall_miss_rate::cpu1.inst 0.125031 2716system.l2c.overall_miss_rate::cpu1.data 0.517152 2717system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.586608 2718system.l2c.overall_miss_rate::total 0.461501 2719system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 18544.967880 2720system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4537.356322 2721system.l2c.UpgradeReq_avg_miss_latency::total 14742.589704 2722system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 10730 2723system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2763.888889 2724system.l2c.SCUpgradeReq_avg_miss_latency::total 6028.688525 2725system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139573.050952 2726system.l2c.ReadExReq_avg_miss_latency::cpu1.data 95324.863356 2727system.l2c.ReadExReq_avg_miss_latency::total 120550.444956 2728system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 142241.610738 2729system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90000 2730system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 101930.905900 2731system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 122305.714286 2732system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 120119.463388 2733system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 201150 2734system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 106696.248600 2735system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 147836.746303 2736system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 128861.406757 2737system.l2c.ReadSharedReq_avg_miss_latency::total 118200.814439 2738system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 142241.610738 2739system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90000 2740system.l2c.demand_avg_miss_latency::cpu0.inst 101930.905900 2741system.l2c.demand_avg_miss_latency::cpu0.data 131516.091309 2742system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 120119.463388 2743system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 201150 2744system.l2c.demand_avg_miss_latency::cpu1.inst 106696.248600 2745system.l2c.demand_avg_miss_latency::cpu1.data 104238.244665 2746system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 128861.406757 2747system.l2c.demand_avg_miss_latency::total 118438.287328 2748system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 142241.610738 2749system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90000 2750system.l2c.overall_avg_miss_latency::cpu0.inst 101930.905900 2751system.l2c.overall_avg_miss_latency::cpu0.data 131516.091309 2752system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 120119.463388 2753system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 201150 2754system.l2c.overall_avg_miss_latency::cpu1.inst 106696.248600 2755system.l2c.overall_avg_miss_latency::cpu1.data 104238.244665 2756system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 128861.406757 2757system.l2c.overall_avg_miss_latency::total 118438.287328 2758system.l2c.blocked_cycles::no_mshrs 546 2759system.l2c.blocked_cycles::no_targets 0 2760system.l2c.blocked::no_mshrs 2 2761system.l2c.blocked::no_targets 0 2762system.l2c.avg_blocked_cycles::no_mshrs 273 2763system.l2c.avg_blocked_cycles::no_targets nan 2764system.l2c.writebacks::writebacks 104138 2765system.l2c.writebacks::total 104138 2766system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 2767system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 2 2768system.l2c.ReadSharedReq_mshr_hits::total 7 2769system.l2c.demand_mshr_hits::cpu0.inst 5 2770system.l2c.demand_mshr_hits::cpu1.inst 2 2771system.l2c.demand_mshr_hits::total 7 2772system.l2c.overall_mshr_hits::cpu0.inst 5 2773system.l2c.overall_mshr_hits::cpu1.inst 2 2774system.l2c.overall_mshr_hits::total 7 2775system.l2c.CleanEvict_mshr_misses::writebacks 4255 2776system.l2c.CleanEvict_mshr_misses::total 4255 2777system.l2c.UpgradeReq_mshr_misses::cpu0.data 467 2778system.l2c.UpgradeReq_mshr_misses::cpu1.data 174 2779system.l2c.UpgradeReq_mshr_misses::total 641 2780system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 50 2781system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 72 2782system.l2c.SCUpgradeReq_mshr_misses::total 122 2783system.l2c.ReadExReq_mshr_misses::cpu0.data 11403 2784system.l2c.ReadExReq_mshr_misses::cpu1.data 8599 2785system.l2c.ReadExReq_mshr_misses::total 20002 2786system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 149 2787system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1 2788system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 22790 2789system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9975 2790system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134395 2791system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 20 2792system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 3570 2793system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1758 2794system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5239 2795system.l2c.ReadSharedReq_mshr_misses::total 177897 2796system.l2c.demand_mshr_misses::cpu0.dtb.walker 149 2797system.l2c.demand_mshr_misses::cpu0.itb.walker 1 2798system.l2c.demand_mshr_misses::cpu0.inst 22790 2799system.l2c.demand_mshr_misses::cpu0.data 21378 2800system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134395 2801system.l2c.demand_mshr_misses::cpu1.dtb.walker 20 2802system.l2c.demand_mshr_misses::cpu1.inst 3570 2803system.l2c.demand_mshr_misses::cpu1.data 10357 2804system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5239 2805system.l2c.demand_mshr_misses::total 197899 2806system.l2c.overall_mshr_misses::cpu0.dtb.walker 149 2807system.l2c.overall_mshr_misses::cpu0.itb.walker 1 2808system.l2c.overall_mshr_misses::cpu0.inst 22790 2809system.l2c.overall_mshr_misses::cpu0.data 21378 2810system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134395 2811system.l2c.overall_mshr_misses::cpu1.dtb.walker 20 2812system.l2c.overall_mshr_misses::cpu1.inst 3570 2813system.l2c.overall_mshr_misses::cpu1.data 10357 2814system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5239 2815system.l2c.overall_mshr_misses::total 197899 2816system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3277 2817system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20583 2818system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 2819system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14403 2820system.l2c.ReadReq_mshr_uncacheable::total 38375 2821system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19292 2822system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11728 2823system.l2c.WriteReq_mshr_uncacheable::total 31020 2824system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3277 2825system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39875 2826system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 2827system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26131 2828system.l2c.overall_mshr_uncacheable_misses::total 69395 2829system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 10374500 2830system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3853500 2831system.l2c.UpgradeReq_mshr_miss_latency::total 14228000 2832system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1334000 2833system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1691000 2834system.l2c.SCUpgradeReq_mshr_miss_latency::total 3025000 2835system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1477521500 2836system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 733708500 2837system.l2c.ReadExReq_mshr_miss_latency::total 2211230000 2838system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 19704000 2839system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 80000 2840system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2094874500 2841system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1120249500 2842system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14799502289 2843system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 3823000 2844system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 345333500 2845system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 242316501 2846system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 622713912 2847system.l2c.ReadSharedReq_mshr_miss_latency::total 19248597202 2848system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 19704000 2849system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000 2850system.l2c.demand_mshr_miss_latency::cpu0.inst 2094874500 2851system.l2c.demand_mshr_miss_latency::cpu0.data 2597771000 2852system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14799502289 2853system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 3823000 2854system.l2c.demand_mshr_miss_latency::cpu1.inst 345333500 2855system.l2c.demand_mshr_miss_latency::cpu1.data 976025001 2856system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 622713912 2857system.l2c.demand_mshr_miss_latency::total 21459827202 2858system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 19704000 2859system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 2860system.l2c.overall_mshr_miss_latency::cpu0.inst 2094874500 2861system.l2c.overall_mshr_miss_latency::cpu0.data 2597771000 2862system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14799502289 2863system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 3823000 2864system.l2c.overall_mshr_miss_latency::cpu1.inst 345333500 2865system.l2c.overall_mshr_miss_latency::cpu1.data 976025001 2866system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 622713912 2867system.l2c.overall_mshr_miss_latency::total 21459827202 2868system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 228848500 2869system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4073216000 2870system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7794500 2871system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2115640500 2872system.l2c.ReadReq_mshr_uncacheable_latency::total 6425499500 2873system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 228848500 2874system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4073216000 2875system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7794500 2876system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2115640500 2877system.l2c.overall_mshr_uncacheable_latency::total 6425499500 2878system.l2c.CleanEvict_mshr_miss_rate::writebacks inf 2879system.l2c.CleanEvict_mshr_miss_rate::total inf 2880system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.010569 2881system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.037605 2882system.l2c.UpgradeReq_mshr_miss_rate::total 0.013132 2883system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.016656 2884system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.032832 2885system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.023484 2886system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.722257 2887system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.874682 2888system.l2c.ReadExReq_mshr_miss_rate::total 0.780749 2889system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.237640 2890system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.012048 2891system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.238479 2892system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.131210 2893system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733966 2894system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.196078 2895system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.124961 2896system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.172421 2897system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.586608 2898system.l2c.ReadSharedReq_mshr_miss_rate::total 0.441200 2899system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.237640 2900system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.012048 2901system.l2c.demand_mshr_miss_rate::cpu0.inst 0.238479 2902system.l2c.demand_mshr_miss_rate::cpu0.data 0.232848 2903system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733966 2904system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.196078 2905system.l2c.demand_mshr_miss_rate::cpu1.inst 0.124961 2906system.l2c.demand_mshr_miss_rate::cpu1.data 0.517152 2907system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.586608 2908system.l2c.demand_mshr_miss_rate::total 0.461485 2909system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.237640 2910system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012048 2911system.l2c.overall_mshr_miss_rate::cpu0.inst 0.238479 2912system.l2c.overall_mshr_miss_rate::cpu0.data 0.232848 2913system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733966 2914system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.196078 2915system.l2c.overall_mshr_miss_rate::cpu1.inst 0.124961 2916system.l2c.overall_mshr_miss_rate::cpu1.data 0.517152 2917system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.586608 2918system.l2c.overall_mshr_miss_rate::total 0.461485 2919system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22215.203426 2920system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22146.551724 2921system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22196.567863 2922system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26680 2923system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23486.111111 2924system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24795.081967 2925system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129573.050952 2926system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 85324.863356 2927system.l2c.ReadExReq_avg_mshr_miss_latency::total 110550.444956 2928system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132241.610738 2929system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80000 2930system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 91920.776656 2931system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 112305.714286 2932system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110119.441118 2933system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 191150 2934system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 96732.072829 2935system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 137836.462457 2936system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 118861.216263 2937system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108200.797102 2938system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132241.610738 2939system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000 2940system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 91920.776656 2941system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121516.091309 2942system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110119.441118 2943system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 191150 2944system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 96732.072829 2945system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94238.196485 2946system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 118861.216263 2947system.l2c.demand_avg_mshr_miss_latency::total 108438.280143 2948system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132241.610738 2949system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000 2950system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 91920.776656 2951system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121516.091309 2952system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110119.441118 2953system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 191150 2954system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 96732.072829 2955system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94238.196485 2956system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 118861.216263 2957system.l2c.overall_avg_mshr_miss_latency::total 108438.280143 2958system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 2959system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197892.241170 2960system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69593.750000 2961system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146888.877317 2962system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167439.726384 2963system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 2964system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102149.617555 2965system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69593.750000 2966system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80962.860204 2967system.l2c.overall_avg_mshr_uncacheable_latency::total 92593.119101 2968system.membus.snoop_filter.tot_requests 514509 2969system.membus.snoop_filter.hit_single_requests 286339 2970system.membus.snoop_filter.hit_multi_requests 635 2971system.membus.snoop_filter.tot_snoops 0 2972system.membus.snoop_filter.hit_single_snoops 0 2973system.membus.snoop_filter.hit_multi_snoops 0 2974system.membus.pwrStateResidencyTicks::UNDEFINED 2848623849000 2975system.membus.trans_dist::ReadReq 38375 2976system.membus.trans_dist::ReadResp 216523 2977system.membus.trans_dist::WriteReq 31020 2978system.membus.trans_dist::WriteResp 31020 2979system.membus.trans_dist::WritebackDirty 140344 2980system.membus.trans_dist::CleanEvict 19042 2981system.membus.trans_dist::UpgradeReq 61413 2982system.membus.trans_dist::SCUpgradeReq 38691 2983system.membus.trans_dist::UpgradeResp 2 2984system.membus.trans_dist::ReadExReq 40527 2985system.membus.trans_dist::ReadExResp 19982 2986system.membus.trans_dist::ReadSharedReq 178148 2987system.membus.trans_dist::InvalidateReq 36224 2988system.membus.trans_dist::InvalidateResp 4303 2989system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 2990system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 2991system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14152 2992system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 655682 2993system.membus.pkt_count_system.l2c.mem_side::total 777788 2994system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72947 2995system.membus.pkt_count_system.iocache.mem_side::total 72947 2996system.membus.pkt_count::total 850735 2997system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162802 2998system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 2999system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28304 3000system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19543016 3001system.membus.pkt_size_system.l2c.mem_side::total 19735466 3002system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 3003system.membus.pkt_size_system.iocache.mem_side::total 2318144 3004system.membus.pkt_size::total 22053610 3005system.membus.snoops 124745 3006system.membus.snoopTraffic 36736 3007system.membus.snoop_fanout::samples 424399 3008system.membus.snoop_fanout::mean 0.011640 3009system.membus.snoop_fanout::stdev 0.107259 3010system.membus.snoop_fanout::underflows 0 0.00% 0.00% 3011system.membus.snoop_fanout::0 419459 98.84% 98.84% 3012system.membus.snoop_fanout::1 4940 1.16% 100.00% 3013system.membus.snoop_fanout::2 0 0.00% 100.00% 3014system.membus.snoop_fanout::overflows 0 0.00% 100.00% 3015system.membus.snoop_fanout::min_value 0 3016system.membus.snoop_fanout::max_value 1 3017system.membus.snoop_fanout::total 424399 3018system.membus.reqLayer0.occupancy 95155498 3019system.membus.reqLayer0.utilization 0.0 3020system.membus.reqLayer1.occupancy 23328 3021system.membus.reqLayer1.utilization 0.0 3022system.membus.reqLayer2.occupancy 12482999 3023system.membus.reqLayer2.utilization 0.0 3024system.membus.reqLayer5.occupancy 1007290019 3025system.membus.reqLayer5.utilization 0.0 3026system.membus.respLayer2.occupancy 1153319410 3027system.membus.respLayer2.utilization 0.0 3028system.membus.respLayer3.occupancy 6842240 3029system.membus.respLayer3.utilization 0.0 3030system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848623849000 3031system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848623849000 3032system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848623849000 3033system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848623849000 3034system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848623849000 3035system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848623849000 3036system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848623849000 3037system.realview.dcc.osc_cpu.clock 16667 3038system.realview.dcc.osc_ddr.clock 25000 3039system.realview.dcc.osc_hsbm.clock 25000 3040system.realview.dcc.osc_pxl.clock 42105 3041system.realview.dcc.osc_smb.clock 20000 3042system.realview.dcc.osc_sys.clock 16667 3043system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848623849000 3044system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848623849000 3045system.realview.ethernet.descDMAReads 0 3046system.realview.ethernet.descDMAWrites 0 3047system.realview.ethernet.descDmaReadBytes 0 3048system.realview.ethernet.descDmaWriteBytes 0 3049system.realview.ethernet.postedSwi 0 3050system.realview.ethernet.coalescedSwi nan 3051system.realview.ethernet.totalSwi 0 3052system.realview.ethernet.postedRxIdle 0 3053system.realview.ethernet.coalescedRxIdle nan 3054system.realview.ethernet.totalRxIdle 0 3055system.realview.ethernet.postedRxOk 0 3056system.realview.ethernet.coalescedRxOk nan 3057system.realview.ethernet.totalRxOk 0 3058system.realview.ethernet.postedRxDesc 0 3059system.realview.ethernet.coalescedRxDesc nan 3060system.realview.ethernet.totalRxDesc 0 3061system.realview.ethernet.postedTxOk 0 3062system.realview.ethernet.coalescedTxOk nan 3063system.realview.ethernet.totalTxOk 0 3064system.realview.ethernet.postedTxIdle 0 3065system.realview.ethernet.coalescedTxIdle nan 3066system.realview.ethernet.totalTxIdle 0 3067system.realview.ethernet.postedTxDesc 0 3068system.realview.ethernet.coalescedTxDesc nan 3069system.realview.ethernet.totalTxDesc 0 3070system.realview.ethernet.postedRxOrn 0 3071system.realview.ethernet.coalescedRxOrn nan 3072system.realview.ethernet.totalRxOrn 0 3073system.realview.ethernet.coalescedTotal nan 3074system.realview.ethernet.postedInterrupts 0 3075system.realview.ethernet.droppedPackets 0 3076system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848623849000 3077system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848623849000 3078system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848623849000 3079system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848623849000 3080system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848623849000 3081system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848623849000 3082system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848623849000 3083system.realview.mcc.osc_clcd.clock 42105 3084system.realview.mcc.osc_mcc.clock 20000 3085system.realview.mcc.osc_peripheral.clock 41667 3086system.realview.mcc.osc_system_bus.clock 41667 3087system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848623849000 3088system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848623849000 3089system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848623849000 3090system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848623849000 3091system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848623849000 3092system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848623849000 3093system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848623849000 3094system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848623849000 3095system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848623849000 3096system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848623849000 3097system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848623849000 3098system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848623849000 3099system.toL2Bus.snoop_filter.tot_requests 1102536 3100system.toL2Bus.snoop_filter.hit_single_requests 568062 3101system.toL2Bus.snoop_filter.hit_multi_requests 209231 3102system.toL2Bus.snoop_filter.tot_snoops 30967 3103system.toL2Bus.snoop_filter.hit_single_snoops 29546 3104system.toL2Bus.snoop_filter.hit_multi_snoops 1421 3105system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848623849000 3106system.toL2Bus.trans_dist::ReadReq 38378 3107system.toL2Bus.trans_dist::ReadResp 559335 3108system.toL2Bus.trans_dist::WriteReq 31020 3109system.toL2Bus.trans_dist::WriteResp 31020 3110system.toL2Bus.trans_dist::WritebackDirty 370365 3111system.toL2Bus.trans_dist::CleanEvict 150278 3112system.toL2Bus.trans_dist::UpgradeReq 109564 3113system.toL2Bus.trans_dist::SCUpgradeReq 43764 3114system.toL2Bus.trans_dist::UpgradeResp 153328 3115system.toL2Bus.trans_dist::SCUpgradeFailReq 31 3116system.toL2Bus.trans_dist::UpgradeFailResp 31 3117system.toL2Bus.trans_dist::ReadExReq 51537 3118system.toL2Bus.trans_dist::ReadExResp 51537 3119system.toL2Bus.trans_dist::ReadSharedReq 520961 3120system.toL2Bus.trans_dist::InvalidateReq 4360 3121system.toL2Bus.trans_dist::InvalidateResp 3146 3122system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1373233 3123system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 354273 3124system.toL2Bus.pkt_count::total 1727506 3125system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 39252280 3126system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5674546 3127system.toL2Bus.pkt_size::total 44926826 3128system.toL2Bus.snoops 394531 3129system.toL2Bus.snoopTraffic 15861260 3130system.toL2Bus.snoop_fanout::samples 943382 3131system.toL2Bus.snoop_fanout::mean 0.393790 3132system.toL2Bus.snoop_fanout::stdev 0.491663 3133system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% 3134system.toL2Bus.snoop_fanout::0 573309 60.77% 60.77% 3135system.toL2Bus.snoop_fanout::1 368652 39.08% 99.85% 3136system.toL2Bus.snoop_fanout::2 1421 0.15% 100.00% 3137system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% 3138system.toL2Bus.snoop_fanout::min_value 0 3139system.toL2Bus.snoop_fanout::max_value 2 3140system.toL2Bus.snoop_fanout::total 943382 3141system.toL2Bus.reqLayer0.occupancy 940189543 3142system.toL2Bus.reqLayer0.utilization 0.0 3143system.toL2Bus.snoopLayer0.occupancy 1999903 3144system.toL2Bus.snoopLayer0.utilization 0.0 3145system.toL2Bus.respLayer0.occupancy 734750712 3146system.toL2Bus.respLayer0.utilization 0.0 3147system.toL2Bus.respLayer1.occupancy 258376523 3148system.toL2Bus.respLayer1.utilization 0.0
3143 3144---------- End Simulation Statistics ----------	3149 3150---------- End Simulation Statistics ----------