| stats.txt (11530:6e143fd2cabf) | stats.txt (11547:dd6dfd38b6c2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.847227 # Number of seconds simulated 4sim_ticks 2847227406000 # Number of ticks simulated 5final_tick 2847227406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.847227 # Number of seconds simulated 4sim_ticks 2847227406000 # Number of ticks simulated 5final_tick 2847227406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 262523 # Simulator instruction rate (inst/s) 8host_op_rate 317894 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5870765699 # Simulator tick rate (ticks/s) 10host_mem_usage 664268 # Number of bytes of host memory used 11host_seconds 484.98 # Real time elapsed on the host | 7host_inst_rate 166460 # Simulator instruction rate (inst/s) 8host_op_rate 201569 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3722516357 # Simulator tick rate (ticks/s) 10host_mem_usage 624360 # Number of bytes of host memory used 11host_seconds 764.87 # Real time elapsed on the host |
| 12sim_insts 127319545 # Number of instructions simulated 13sim_ops 154173476 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 7488 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1647744 # Number of bytes read from this memory --- 431 unchanged lines hidden (view full) --- 451system.cpu0.dtb.read_hits 17339981 # DTB read hits 452system.cpu0.dtb.read_misses 61941 # DTB read misses 453system.cpu0.dtb.write_hits 14540400 # DTB write hits 454system.cpu0.dtb.write_misses 6479 # DTB write misses 455system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 456system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 457system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 458system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 12sim_insts 127319545 # Number of instructions simulated 13sim_ops 154173476 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 7488 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1647744 # Number of bytes read from this memory --- 431 unchanged lines hidden (view full) --- 451system.cpu0.dtb.read_hits 17339981 # DTB read hits 452system.cpu0.dtb.read_misses 61941 # DTB read misses 453system.cpu0.dtb.write_hits 14540400 # DTB write hits 454system.cpu0.dtb.write_misses 6479 # DTB write misses 455system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 456system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 457system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 458system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 459system.cpu0.dtb.flush_entries 3513 # Number of entries that have been flushed from TLB | 459system.cpu0.dtb.flush_entries 3449 # Number of entries that have been flushed from TLB |
| 460system.cpu0.dtb.align_faults 1354 # Number of TLB faults due to alignment restrictions 461system.cpu0.dtb.prefetch_faults 1959 # Number of TLB faults due to prefetch 462system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 463system.cpu0.dtb.perms_faults 521 # Number of TLB faults due to permissions restrictions 464system.cpu0.dtb.read_accesses 17401922 # DTB read accesses 465system.cpu0.dtb.write_accesses 14546879 # DTB write accesses 466system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 467system.cpu0.dtb.hits 31880381 # DTB hits --- 67 unchanged lines hidden (view full) --- 535system.cpu0.itb.read_hits 0 # DTB read hits 536system.cpu0.itb.read_misses 0 # DTB read misses 537system.cpu0.itb.write_hits 0 # DTB write hits 538system.cpu0.itb.write_misses 0 # DTB write misses 539system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 540system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 541system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 542system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 460system.cpu0.dtb.align_faults 1354 # Number of TLB faults due to alignment restrictions 461system.cpu0.dtb.prefetch_faults 1959 # Number of TLB faults due to prefetch 462system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 463system.cpu0.dtb.perms_faults 521 # Number of TLB faults due to permissions restrictions 464system.cpu0.dtb.read_accesses 17401922 # DTB read accesses 465system.cpu0.dtb.write_accesses 14546879 # DTB write accesses 466system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 467system.cpu0.dtb.hits 31880381 # DTB hits --- 67 unchanged lines hidden (view full) --- 535system.cpu0.itb.read_hits 0 # DTB read hits 536system.cpu0.itb.read_misses 0 # DTB read misses 537system.cpu0.itb.write_hits 0 # DTB write hits 538system.cpu0.itb.write_misses 0 # DTB write misses 539system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 540system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 541system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 542system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 543system.cpu0.itb.flush_entries 2216 # Number of entries that have been flushed from TLB | 543system.cpu0.itb.flush_entries 2152 # Number of entries that have been flushed from TLB |
| 544system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 545system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 546system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 547system.cpu0.itb.perms_faults 6955 # Number of TLB faults due to permissions restrictions 548system.cpu0.itb.read_accesses 0 # DTB read accesses 549system.cpu0.itb.write_accesses 0 # DTB write accesses 550system.cpu0.itb.inst_accesses 38610243 # ITB inst accesses 551system.cpu0.itb.hits 38606266 # DTB hits --- 849 unchanged lines hidden (view full) --- 1401system.cpu1.dtb.read_hits 11185393 # DTB read hits 1402system.cpu1.dtb.read_misses 25019 # DTB read misses 1403system.cpu1.dtb.write_hits 6992115 # DTB write hits 1404system.cpu1.dtb.write_misses 1955 # DTB write misses 1405system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1406system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1407system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1408system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 544system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 545system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 546system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 547system.cpu0.itb.perms_faults 6955 # Number of TLB faults due to permissions restrictions 548system.cpu0.itb.read_accesses 0 # DTB read accesses 549system.cpu0.itb.write_accesses 0 # DTB write accesses 550system.cpu0.itb.inst_accesses 38610243 # ITB inst accesses 551system.cpu0.itb.hits 38606266 # DTB hits --- 849 unchanged lines hidden (view full) --- 1401system.cpu1.dtb.read_hits 11185393 # DTB read hits 1402system.cpu1.dtb.read_misses 25019 # DTB read misses 1403system.cpu1.dtb.write_hits 6992115 # DTB write hits 1404system.cpu1.dtb.write_misses 1955 # DTB write misses 1405system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1406system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1407system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1408system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1409system.cpu1.dtb.flush_entries 2060 # Number of entries that have been flushed from TLB | 1409system.cpu1.dtb.flush_entries 1996 # Number of entries that have been flushed from TLB |
| 1410system.cpu1.dtb.align_faults 164 # Number of TLB faults due to alignment restrictions 1411system.cpu1.dtb.prefetch_faults 367 # Number of TLB faults due to prefetch 1412system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1413system.cpu1.dtb.perms_faults 283 # Number of TLB faults due to permissions restrictions 1414system.cpu1.dtb.read_accesses 11210412 # DTB read accesses 1415system.cpu1.dtb.write_accesses 6994070 # DTB write accesses 1416system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1417system.cpu1.dtb.hits 18177508 # DTB hits --- 72 unchanged lines hidden (view full) --- 1490system.cpu1.itb.read_hits 0 # DTB read hits 1491system.cpu1.itb.read_misses 0 # DTB read misses 1492system.cpu1.itb.write_hits 0 # DTB write hits 1493system.cpu1.itb.write_misses 0 # DTB write misses 1494system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1495system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1496system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1497system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1410system.cpu1.dtb.align_faults 164 # Number of TLB faults due to alignment restrictions 1411system.cpu1.dtb.prefetch_faults 367 # Number of TLB faults due to prefetch 1412system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1413system.cpu1.dtb.perms_faults 283 # Number of TLB faults due to permissions restrictions 1414system.cpu1.dtb.read_accesses 11210412 # DTB read accesses 1415system.cpu1.dtb.write_accesses 6994070 # DTB write accesses 1416system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1417system.cpu1.dtb.hits 18177508 # DTB hits --- 72 unchanged lines hidden (view full) --- 1490system.cpu1.itb.read_hits 0 # DTB read hits 1491system.cpu1.itb.read_misses 0 # DTB read misses 1492system.cpu1.itb.write_hits 0 # DTB write hits 1493system.cpu1.itb.write_misses 0 # DTB write misses 1494system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1495system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1496system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1497system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1498system.cpu1.itb.flush_entries 1166 # Number of entries that have been flushed from TLB | 1498system.cpu1.itb.flush_entries 1102 # Number of entries that have been flushed from TLB |
| 1499system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1500system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1501system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1502system.cpu1.itb.perms_faults 1819 # Number of TLB faults due to permissions restrictions 1503system.cpu1.itb.read_accesses 0 # DTB read accesses 1504system.cpu1.itb.write_accesses 0 # DTB write accesses 1505system.cpu1.itb.inst_accesses 39605220 # ITB inst accesses 1506system.cpu1.itb.hits 39602800 # DTB hits --- 1620 unchanged lines hidden --- | 1499system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1500system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1501system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1502system.cpu1.itb.perms_faults 1819 # Number of TLB faults due to permissions restrictions 1503system.cpu1.itb.read_accesses 0 # DTB read accesses 1504system.cpu1.itb.write_accesses 0 # DTB write accesses 1505system.cpu1.itb.inst_accesses 39605220 # ITB inst accesses 1506system.cpu1.itb.hits 39602800 # DTB hits --- 1620 unchanged lines hidden --- |