| stats.txt (11507:be6065c1d8d2) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.847227 # Number of seconds simulated 4sim_ticks 2847227406000 # Number of ticks simulated 5final_tick 2847227406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.847227 # Number of seconds simulated 4sim_ticks 2847227406000 # Number of ticks simulated 5final_tick 2847227406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 111277 # Simulator instruction rate (inst/s) 8host_op_rate 134747 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2488466073 # Simulator tick rate (ticks/s) 10host_mem_usage 617520 # Number of bytes of host memory used 11host_seconds 1144.17 # Real time elapsed on the host | 7host_inst_rate 262523 # Simulator instruction rate (inst/s) 8host_op_rate 317894 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5870765699 # Simulator tick rate (ticks/s) 10host_mem_usage 664268 # Number of bytes of host memory used 11host_seconds 484.98 # Real time elapsed on the host |
| 12sim_insts 127319545 # Number of instructions simulated 13sim_ops 154173476 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 127319545 # Number of instructions simulated 13sim_ops 154173476 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu0.dtb.walker 7488 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1647744 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1317552 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8353536 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 217280 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 643604 # Number of bytes read from this memory --- 312 unchanged lines hidden (view full) --- 336system.physmem_1.preBackEnergy 1635612802500 # Energy for precharge background per rank (pJ) 337system.physmem_1.totalEnergy 1906215727380 # Total energy per rank (pJ) 338system.physmem_1.averagePower 669.500294 # Core power per rank (mW) 339system.physmem_1.memoryStateTime::IDLE 2720864046511 # Time in different power states 340system.physmem_1.memoryStateTime::REF 95074980000 # Time in different power states 341system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 342system.physmem_1.memoryStateTime::ACT 31288281989 # Time in different power states 343system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu0.dtb.walker 7488 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1647744 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1317552 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8353536 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 217280 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 643604 # Number of bytes read from this memory --- 312 unchanged lines hidden (view full) --- 337system.physmem_1.preBackEnergy 1635612802500 # Energy for precharge background per rank (pJ) 338system.physmem_1.totalEnergy 1906215727380 # Total energy per rank (pJ) 339system.physmem_1.averagePower 669.500294 # Core power per rank (mW) 340system.physmem_1.memoryStateTime::IDLE 2720864046511 # Time in different power states 341system.physmem_1.memoryStateTime::REF 95074980000 # Time in different power states 342system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 343system.physmem_1.memoryStateTime::ACT 31288281989 # Time in different power states 344system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 345system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 344system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory 345system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory 346system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory 347system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory 348system.realview.nvmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory 349system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory 350system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 351system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory 352system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory 353system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s) 355system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) 360system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) 361system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) | 346system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory 347system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory 348system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory 349system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory 350system.realview.nvmem.bytes_inst_read::cpu1.inst 832 # Number of instructions bytes read from this memory 351system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory 352system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory 353system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory 354system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory 355system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s) 360system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) 362system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) 363system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) |
| 364system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 365system.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 366system.bridge.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 362system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 363system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 364system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 365system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 366system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 367system.cf0.dma_write_txs 631 # Number of DMA write transactions. 368system.cpu0.branchPred.lookups 20737076 # Number of BP lookups 369system.cpu0.branchPred.condPredicted 13605991 # Number of conditional branches predicted --- 4 unchanged lines hidden (view full) --- 374system.cpu0.branchPred.BTBHitPct 66.064807 # BTB Hit Percentage 375system.cpu0.branchPred.usedRAS 3399643 # Number of times the RAS was used to get a target. 376system.cpu0.branchPred.RASInCorrect 216094 # Number of incorrect RAS predictions. 377system.cpu0.branchPred.indirectLookups 760668 # Number of indirect predictor lookups. 378system.cpu0.branchPred.indirectHits 581758 # Number of indirect target hits. 379system.cpu0.branchPred.indirectMisses 178910 # Number of indirect misses. 380system.cpu0.branchPredindirectMispredicted 99353 # Number of mispredicted indirect branches. 381system.cpu_clk_domain.clock 500 # Clock period in ticks | 367system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 368system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 369system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 370system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 371system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 372system.cf0.dma_write_txs 631 # Number of DMA write transactions. 373system.cpu0.branchPred.lookups 20737076 # Number of BP lookups 374system.cpu0.branchPred.condPredicted 13605991 # Number of conditional branches predicted --- 4 unchanged lines hidden (view full) --- 379system.cpu0.branchPred.BTBHitPct 66.064807 # BTB Hit Percentage 380system.cpu0.branchPred.usedRAS 3399643 # Number of times the RAS was used to get a target. 381system.cpu0.branchPred.RASInCorrect 216094 # Number of incorrect RAS predictions. 382system.cpu0.branchPred.indirectLookups 760668 # Number of indirect predictor lookups. 383system.cpu0.branchPred.indirectHits 581758 # Number of indirect target hits. 384system.cpu0.branchPred.indirectMisses 178910 # Number of indirect misses. 385system.cpu0.branchPredindirectMispredicted 99353 # Number of mispredicted indirect branches. 386system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 387system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 382system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 383system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 384system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 403system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 404system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 405system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 406system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 407system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 408system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 409system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 410system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 409system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 410system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 411system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 412system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 413system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 414system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 415system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 416system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 417system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 411system.cpu0.dtb.walker.walks 68420 # Table walker walks requested 412system.cpu0.dtb.walker.walksShort 68420 # Table walker walks initiated with short descriptors 413system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46092 # Level at which table walker walks with short descriptors terminate 414system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22328 # Level at which table walker walks with short descriptors terminate 415system.cpu0.dtb.walker.walkWaitTime::samples 68420 # Table walker wait (enqueue to first request) latency 416system.cpu0.dtb.walker.walkWaitTime::0 68420 100.00% 100.00% # Table walker wait (enqueue to first request) latency 417system.cpu0.dtb.walker.walkWaitTime::total 68420 # Table walker wait (enqueue to first request) latency 418system.cpu0.dtb.walker.walkCompletionTime::samples 6777 # Table walker service (enqueue to completion) latency --- 36 unchanged lines hidden (view full) --- 455system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 456system.cpu0.dtb.perms_faults 521 # Number of TLB faults due to permissions restrictions 457system.cpu0.dtb.read_accesses 17401922 # DTB read accesses 458system.cpu0.dtb.write_accesses 14546879 # DTB write accesses 459system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 460system.cpu0.dtb.hits 31880381 # DTB hits 461system.cpu0.dtb.misses 68420 # DTB misses 462system.cpu0.dtb.accesses 31948801 # DTB accesses | 418system.cpu0.dtb.walker.walks 68420 # Table walker walks requested 419system.cpu0.dtb.walker.walksShort 68420 # Table walker walks initiated with short descriptors 420system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46092 # Level at which table walker walks with short descriptors terminate 421system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22328 # Level at which table walker walks with short descriptors terminate 422system.cpu0.dtb.walker.walkWaitTime::samples 68420 # Table walker wait (enqueue to first request) latency 423system.cpu0.dtb.walker.walkWaitTime::0 68420 100.00% 100.00% # Table walker wait (enqueue to first request) latency 424system.cpu0.dtb.walker.walkWaitTime::total 68420 # Table walker wait (enqueue to first request) latency 425system.cpu0.dtb.walker.walkCompletionTime::samples 6777 # Table walker service (enqueue to completion) latency --- 36 unchanged lines hidden (view full) --- 462system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 463system.cpu0.dtb.perms_faults 521 # Number of TLB faults due to permissions restrictions 464system.cpu0.dtb.read_accesses 17401922 # DTB read accesses 465system.cpu0.dtb.write_accesses 14546879 # DTB write accesses 466system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 467system.cpu0.dtb.hits 31880381 # DTB hits 468system.cpu0.dtb.misses 68420 # DTB misses 469system.cpu0.dtb.accesses 31948801 # DTB accesses |
| 470system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 463system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 464system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 465system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 466system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 467system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 468system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 469system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 470system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 484system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 485system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 486system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 487system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 488system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 489system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 490system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 491system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 471system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 472system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 473system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 474system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 475system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 476system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 477system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 478system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 492system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 493system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 494system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 495system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 496system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 497system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 498system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 499system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 500system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 492system.cpu0.itb.walker.walks 3977 # Table walker walks requested 493system.cpu0.itb.walker.walksShort 3977 # Table walker walks initiated with short descriptors 494system.cpu0.itb.walker.walksShortTerminationLevel::Level1 304 # Level at which table walker walks with short descriptors terminate 495system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3673 # Level at which table walker walks with short descriptors terminate 496system.cpu0.itb.walker.walkWaitTime::samples 3977 # Table walker wait (enqueue to first request) latency 497system.cpu0.itb.walker.walkWaitTime::0 3977 100.00% 100.00% # Table walker wait (enqueue to first request) latency 498system.cpu0.itb.walker.walkWaitTime::total 3977 # Table walker wait (enqueue to first request) latency 499system.cpu0.itb.walker.walkCompletionTime::samples 2411 # Table walker service (enqueue to completion) latency --- 37 unchanged lines hidden (view full) --- 537system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 538system.cpu0.itb.perms_faults 6955 # Number of TLB faults due to permissions restrictions 539system.cpu0.itb.read_accesses 0 # DTB read accesses 540system.cpu0.itb.write_accesses 0 # DTB write accesses 541system.cpu0.itb.inst_accesses 38610243 # ITB inst accesses 542system.cpu0.itb.hits 38606266 # DTB hits 543system.cpu0.itb.misses 3977 # DTB misses 544system.cpu0.itb.accesses 38610243 # DTB accesses | 501system.cpu0.itb.walker.walks 3977 # Table walker walks requested 502system.cpu0.itb.walker.walksShort 3977 # Table walker walks initiated with short descriptors 503system.cpu0.itb.walker.walksShortTerminationLevel::Level1 304 # Level at which table walker walks with short descriptors terminate 504system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3673 # Level at which table walker walks with short descriptors terminate 505system.cpu0.itb.walker.walkWaitTime::samples 3977 # Table walker wait (enqueue to first request) latency 506system.cpu0.itb.walker.walkWaitTime::0 3977 100.00% 100.00% # Table walker wait (enqueue to first request) latency 507system.cpu0.itb.walker.walkWaitTime::total 3977 # Table walker wait (enqueue to first request) latency 508system.cpu0.itb.walker.walkCompletionTime::samples 2411 # Table walker service (enqueue to completion) latency --- 37 unchanged lines hidden (view full) --- 546system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 547system.cpu0.itb.perms_faults 6955 # Number of TLB faults due to permissions restrictions 548system.cpu0.itb.read_accesses 0 # DTB read accesses 549system.cpu0.itb.write_accesses 0 # DTB write accesses 550system.cpu0.itb.inst_accesses 38610243 # ITB inst accesses 551system.cpu0.itb.hits 38606266 # DTB hits 552system.cpu0.itb.misses 3977 # DTB misses 553system.cpu0.itb.accesses 38610243 # DTB accesses |
| 554system.cpu0.numPwrStateTransitions 3704 # Number of power state transitions 555system.cpu0.pwrStateClkGateDist::samples 1852 # Distribution of time spent in the clock gated state 556system.cpu0.pwrStateClkGateDist::mean 1492233091.644168 # Distribution of time spent in the clock gated state 557system.cpu0.pwrStateClkGateDist::stdev 23940880637.068275 # Distribution of time spent in the clock gated state 558system.cpu0.pwrStateClkGateDist::underflows 1073 57.94% 57.94% # Distribution of time spent in the clock gated state 559system.cpu0.pwrStateClkGateDist::1000-5e+10 772 41.68% 99.62% # Distribution of time spent in the clock gated state 560system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.68% # Distribution of time spent in the clock gated state 561system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.05% 99.73% # Distribution of time spent in the clock gated state 562system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state 563system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state 564system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 565system.cpu0.pwrStateClkGateDist::max_value 499965331660 # Distribution of time spent in the clock gated state 566system.cpu0.pwrStateClkGateDist::total 1852 # Distribution of time spent in the clock gated state 567system.cpu0.pwrStateResidencyTicks::ON 83611720275 # Cumulative time (in ticks) in various power states 568system.cpu0.pwrStateResidencyTicks::CLK_GATED 2763615685725 # Cumulative time (in ticks) in various power states |
|
| 545system.cpu0.numCycles 167224982 # number of cpu cycles simulated 546system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 547system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 548system.cpu0.committedInsts 79715648 # Number of instructions committed 549system.cpu0.committedOps 95927461 # Number of ops (including micro ops) committed 550system.cpu0.discardedOps 5237247 # Number of ops (including micro ops) which were discarded before commit 551system.cpu0.numFetchSuspends 1849 # Number of times Execute suspended instruction fetching 552system.cpu0.quiesceCycles 5527254348 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt --- 33 unchanged lines hidden (view full) --- 586system.cpu0.op_class_0::MemWrite 15283265 15.93% 100.00% # Class of committed instruction 587system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 588system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 589system.cpu0.op_class_0::total 95927461 # Class of committed instruction 590system.cpu0.kern.inst.arm 0 # number of arm instructions executed 591system.cpu0.kern.inst.quiesce 1852 # number of quiesce instructions executed 592system.cpu0.tickCycles 128530134 # Number of cycles that the object actually ticked 593system.cpu0.idleCycles 38694848 # Total number of cycles that the object has spent stopped | 569system.cpu0.numCycles 167224982 # number of cpu cycles simulated 570system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 571system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 572system.cpu0.committedInsts 79715648 # Number of instructions committed 573system.cpu0.committedOps 95927461 # Number of ops (including micro ops) committed 574system.cpu0.discardedOps 5237247 # Number of ops (including micro ops) which were discarded before commit 575system.cpu0.numFetchSuspends 1849 # Number of times Execute suspended instruction fetching 576system.cpu0.quiesceCycles 5527254348 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt --- 33 unchanged lines hidden (view full) --- 610system.cpu0.op_class_0::MemWrite 15283265 15.93% 100.00% # Class of committed instruction 611system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 612system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 613system.cpu0.op_class_0::total 95927461 # Class of committed instruction 614system.cpu0.kern.inst.arm 0 # number of arm instructions executed 615system.cpu0.kern.inst.quiesce 1852 # number of quiesce instructions executed 616system.cpu0.tickCycles 128530134 # Number of cycles that the object actually ticked 617system.cpu0.idleCycles 38694848 # Total number of cycles that the object has spent stopped |
| 618system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 594system.cpu0.dcache.tags.replacements 715130 # number of replacements 595system.cpu0.dcache.tags.tagsinuse 500.249385 # Cycle average of tags in use 596system.cpu0.dcache.tags.total_refs 30394670 # Total number of references to valid blocks. 597system.cpu0.dcache.tags.sampled_refs 715642 # Sample count of references to valid blocks. 598system.cpu0.dcache.tags.avg_refs 42.471892 # Average number of references to valid blocks. 599system.cpu0.dcache.tags.warmup_cycle 356009000 # Cycle when the warmup percentage was hit. 600system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.249385 # Average occupied blocks per requestor 601system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977050 # Average percentage of cache occupancy 602system.cpu0.dcache.tags.occ_percent::total 0.977050 # Average percentage of cache occupancy 603system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 604system.cpu0.dcache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id 605system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id 606system.cpu0.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id 607system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 608system.cpu0.dcache.tags.tag_accesses 63780153 # Number of tag accesses 609system.cpu0.dcache.tags.data_accesses 63780153 # Number of data accesses | 619system.cpu0.dcache.tags.replacements 715130 # number of replacements 620system.cpu0.dcache.tags.tagsinuse 500.249385 # Cycle average of tags in use 621system.cpu0.dcache.tags.total_refs 30394670 # Total number of references to valid blocks. 622system.cpu0.dcache.tags.sampled_refs 715642 # Sample count of references to valid blocks. 623system.cpu0.dcache.tags.avg_refs 42.471892 # Average number of references to valid blocks. 624system.cpu0.dcache.tags.warmup_cycle 356009000 # Cycle when the warmup percentage was hit. 625system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.249385 # Average occupied blocks per requestor 626system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977050 # Average percentage of cache occupancy 627system.cpu0.dcache.tags.occ_percent::total 0.977050 # Average percentage of cache occupancy 628system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 629system.cpu0.dcache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id 630system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id 631system.cpu0.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id 632system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 633system.cpu0.dcache.tags.tag_accesses 63780153 # Number of tag accesses 634system.cpu0.dcache.tags.data_accesses 63780153 # Number of data accesses |
| 635system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 610system.cpu0.dcache.ReadReq_hits::cpu0.data 15810332 # number of ReadReq hits 611system.cpu0.dcache.ReadReq_hits::total 15810332 # number of ReadReq hits 612system.cpu0.dcache.WriteReq_hits::cpu0.data 13424812 # number of WriteReq hits 613system.cpu0.dcache.WriteReq_hits::total 13424812 # number of WriteReq hits 614system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320440 # number of SoftPFReq hits 615system.cpu0.dcache.SoftPFReq_hits::total 320440 # number of SoftPFReq hits 616system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365226 # number of LoadLockedReq hits 617system.cpu0.dcache.LoadLockedReq_hits::total 365226 # number of LoadLockedReq hits --- 160 unchanged lines hidden (view full) --- 778system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14462.348703 # average overall mshr miss latency 779system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14462.348703 # average overall mshr miss latency 780system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14685.205630 # average overall mshr miss latency 781system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14685.205630 # average overall mshr miss latency 782system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 224330.935601 # average ReadReq mshr uncacheable latency 783system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 224330.935601 # average ReadReq mshr uncacheable latency 784system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115836.194348 # average overall mshr uncacheable latency 785system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115836.194348 # average overall mshr uncacheable latency | 636system.cpu0.dcache.ReadReq_hits::cpu0.data 15810332 # number of ReadReq hits 637system.cpu0.dcache.ReadReq_hits::total 15810332 # number of ReadReq hits 638system.cpu0.dcache.WriteReq_hits::cpu0.data 13424812 # number of WriteReq hits 639system.cpu0.dcache.WriteReq_hits::total 13424812 # number of WriteReq hits 640system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320440 # number of SoftPFReq hits 641system.cpu0.dcache.SoftPFReq_hits::total 320440 # number of SoftPFReq hits 642system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365226 # number of LoadLockedReq hits 643system.cpu0.dcache.LoadLockedReq_hits::total 365226 # number of LoadLockedReq hits --- 160 unchanged lines hidden (view full) --- 804system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14462.348703 # average overall mshr miss latency 805system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14462.348703 # average overall mshr miss latency 806system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14685.205630 # average overall mshr miss latency 807system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14685.205630 # average overall mshr miss latency 808system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 224330.935601 # average ReadReq mshr uncacheable latency 809system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 224330.935601 # average ReadReq mshr uncacheable latency 810system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115836.194348 # average overall mshr uncacheable latency 811system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115836.194348 # average overall mshr uncacheable latency |
| 812system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 786system.cpu0.icache.tags.replacements 1962004 # number of replacements 787system.cpu0.icache.tags.tagsinuse 511.774944 # Cycle average of tags in use 788system.cpu0.icache.tags.total_refs 36636559 # Total number of references to valid blocks. 789system.cpu0.icache.tags.sampled_refs 1962516 # Sample count of references to valid blocks. 790system.cpu0.icache.tags.avg_refs 18.668158 # Average number of references to valid blocks. 791system.cpu0.icache.tags.warmup_cycle 6612168000 # Cycle when the warmup percentage was hit. 792system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774944 # Average occupied blocks per requestor 793system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999560 # Average percentage of cache occupancy 794system.cpu0.icache.tags.occ_percent::total 0.999560 # Average percentage of cache occupancy 795system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 796system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id 797system.cpu0.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id 798system.cpu0.icache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id 799system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 800system.cpu0.icache.tags.tag_accesses 79160710 # Number of tag accesses 801system.cpu0.icache.tags.data_accesses 79160710 # Number of data accesses | 813system.cpu0.icache.tags.replacements 1962004 # number of replacements 814system.cpu0.icache.tags.tagsinuse 511.774944 # Cycle average of tags in use 815system.cpu0.icache.tags.total_refs 36636559 # Total number of references to valid blocks. 816system.cpu0.icache.tags.sampled_refs 1962516 # Sample count of references to valid blocks. 817system.cpu0.icache.tags.avg_refs 18.668158 # Average number of references to valid blocks. 818system.cpu0.icache.tags.warmup_cycle 6612168000 # Cycle when the warmup percentage was hit. 819system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774944 # Average occupied blocks per requestor 820system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999560 # Average percentage of cache occupancy 821system.cpu0.icache.tags.occ_percent::total 0.999560 # Average percentage of cache occupancy 822system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 823system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id 824system.cpu0.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id 825system.cpu0.icache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id 826system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 827system.cpu0.icache.tags.tag_accesses 79160710 # Number of tag accesses 828system.cpu0.icache.tags.data_accesses 79160710 # Number of data accesses |
| 829system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 802system.cpu0.icache.ReadReq_hits::cpu0.inst 36636559 # number of ReadReq hits 803system.cpu0.icache.ReadReq_hits::total 36636559 # number of ReadReq hits 804system.cpu0.icache.demand_hits::cpu0.inst 36636559 # number of demand (read+write) hits 805system.cpu0.icache.demand_hits::total 36636559 # number of demand (read+write) hits 806system.cpu0.icache.overall_hits::cpu0.inst 36636559 # number of overall hits 807system.cpu0.icache.overall_hits::total 36636559 # number of overall hits 808system.cpu0.icache.ReadReq_misses::cpu0.inst 1962531 # number of ReadReq misses 809system.cpu0.icache.ReadReq_misses::total 1962531 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 874system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9057.810042 # average overall mshr miss latency 875system.cpu0.icache.demand_avg_mshr_miss_latency::total 9057.810042 # average overall mshr miss latency 876system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9057.810042 # average overall mshr miss latency 877system.cpu0.icache.overall_avg_mshr_miss_latency::total 9057.810042 # average overall mshr miss latency 878system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92626.848362 # average ReadReq mshr uncacheable latency 879system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92626.848362 # average ReadReq mshr uncacheable latency 880system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92626.848362 # average overall mshr uncacheable latency 881system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92626.848362 # average overall mshr uncacheable latency | 830system.cpu0.icache.ReadReq_hits::cpu0.inst 36636559 # number of ReadReq hits 831system.cpu0.icache.ReadReq_hits::total 36636559 # number of ReadReq hits 832system.cpu0.icache.demand_hits::cpu0.inst 36636559 # number of demand (read+write) hits 833system.cpu0.icache.demand_hits::total 36636559 # number of demand (read+write) hits 834system.cpu0.icache.overall_hits::cpu0.inst 36636559 # number of overall hits 835system.cpu0.icache.overall_hits::total 36636559 # number of overall hits 836system.cpu0.icache.ReadReq_misses::cpu0.inst 1962531 # number of ReadReq misses 837system.cpu0.icache.ReadReq_misses::total 1962531 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 902system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9057.810042 # average overall mshr miss latency 903system.cpu0.icache.demand_avg_mshr_miss_latency::total 9057.810042 # average overall mshr miss latency 904system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9057.810042 # average overall mshr miss latency 905system.cpu0.icache.overall_avg_mshr_miss_latency::total 9057.810042 # average overall mshr miss latency 906system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92626.848362 # average ReadReq mshr uncacheable latency 907system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92626.848362 # average ReadReq mshr uncacheable latency 908system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92626.848362 # average overall mshr uncacheable latency 909system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92626.848362 # average overall mshr uncacheable latency |
| 910system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 882system.cpu0.l2cache.prefetcher.num_hwpf_issued 1841200 # number of hwpf issued 883system.cpu0.l2cache.prefetcher.pfIdentified 1841258 # number of prefetch candidates identified 884system.cpu0.l2cache.prefetcher.pfBufferHit 51 # number of redundant prefetches already in prefetch queue 885system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 886system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 887system.cpu0.l2cache.prefetcher.pfSpanPage 233630 # number of prefetches not generated due to page crossing | 911system.cpu0.l2cache.prefetcher.num_hwpf_issued 1841200 # number of hwpf issued 912system.cpu0.l2cache.prefetcher.pfIdentified 1841258 # number of prefetch candidates identified 913system.cpu0.l2cache.prefetcher.pfBufferHit 51 # number of redundant prefetches already in prefetch queue 914system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 915system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 916system.cpu0.l2cache.prefetcher.pfSpanPage 233630 # number of prefetches not generated due to page crossing |
| 917system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 888system.cpu0.l2cache.tags.replacements 298119 # number of replacements 889system.cpu0.l2cache.tags.tagsinuse 16125.660847 # Cycle average of tags in use 890system.cpu0.l2cache.tags.total_refs 4682482 # Total number of references to valid blocks. 891system.cpu0.l2cache.tags.sampled_refs 314209 # Sample count of references to valid blocks. 892system.cpu0.l2cache.tags.avg_refs 14.902444 # Average number of references to valid blocks. 893system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 894system.cpu0.l2cache.tags.occ_blocks::writebacks 14756.008973 # Average occupied blocks per requestor 895system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.059574 # Average occupied blocks per requestor --- 19 unchanged lines hidden (view full) --- 915system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4162 # Occupied blocks per task id 916system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7775 # Occupied blocks per task id 917system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2779 # Occupied blocks per task id 918system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.058899 # Percentage of cache occupancy per task id 919system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id 920system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.922546 # Percentage of cache occupancy per task id 921system.cpu0.l2cache.tags.tag_accesses 89320549 # Number of tag accesses 922system.cpu0.l2cache.tags.data_accesses 89320549 # Number of data accesses | 918system.cpu0.l2cache.tags.replacements 298119 # number of replacements 919system.cpu0.l2cache.tags.tagsinuse 16125.660847 # Cycle average of tags in use 920system.cpu0.l2cache.tags.total_refs 4682482 # Total number of references to valid blocks. 921system.cpu0.l2cache.tags.sampled_refs 314209 # Sample count of references to valid blocks. 922system.cpu0.l2cache.tags.avg_refs 14.902444 # Average number of references to valid blocks. 923system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 924system.cpu0.l2cache.tags.occ_blocks::writebacks 14756.008973 # Average occupied blocks per requestor 925system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.059574 # Average occupied blocks per requestor --- 19 unchanged lines hidden (view full) --- 945system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4162 # Occupied blocks per task id 946system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7775 # Occupied blocks per task id 947system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2779 # Occupied blocks per task id 948system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.058899 # Percentage of cache occupancy per task id 949system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id 950system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.922546 # Percentage of cache occupancy per task id 951system.cpu0.l2cache.tags.tag_accesses 89320549 # Number of tag accesses 952system.cpu0.l2cache.tags.data_accesses 89320549 # Number of data accesses |
| 953system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 923system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 82730 # number of ReadReq hits 924system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5417 # number of ReadReq hits 925system.cpu0.l2cache.ReadReq_hits::total 88147 # number of ReadReq hits 926system.cpu0.l2cache.WritebackDirty_hits::writebacks 481961 # number of WritebackDirty hits 927system.cpu0.l2cache.WritebackDirty_hits::total 481961 # number of WritebackDirty hits 928system.cpu0.l2cache.WritebackClean_hits::writebacks 2152508 # number of WritebackClean hits 929system.cpu0.l2cache.WritebackClean_hits::total 2152508 # number of WritebackClean hits 930system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits --- 297 unchanged lines hidden (view full) --- 1228system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111702.278773 # average overall mshr uncacheable latency 1229system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109545.363206 # average overall mshr uncacheable latency 1230system.cpu0.toL2Bus.snoop_filter.tot_requests 5508026 # Total number of requests made to the snoop filter. 1231system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2775137 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1232system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42660 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1233system.cpu0.toL2Bus.snoop_filter.tot_snoops 346625 # Total number of snoops made to the snoop filter. 1234system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 340732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1235system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5893 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 954system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 82730 # number of ReadReq hits 955system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5417 # number of ReadReq hits 956system.cpu0.l2cache.ReadReq_hits::total 88147 # number of ReadReq hits 957system.cpu0.l2cache.WritebackDirty_hits::writebacks 481961 # number of WritebackDirty hits 958system.cpu0.l2cache.WritebackDirty_hits::total 481961 # number of WritebackDirty hits 959system.cpu0.l2cache.WritebackClean_hits::writebacks 2152508 # number of WritebackClean hits 960system.cpu0.l2cache.WritebackClean_hits::total 2152508 # number of WritebackClean hits 961system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits --- 297 unchanged lines hidden (view full) --- 1259system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111702.278773 # average overall mshr uncacheable latency 1260system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109545.363206 # average overall mshr uncacheable latency 1261system.cpu0.toL2Bus.snoop_filter.tot_requests 5508026 # Total number of requests made to the snoop filter. 1262system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2775137 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1263system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42660 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1264system.cpu0.toL2Bus.snoop_filter.tot_snoops 346625 # Total number of snoops made to the snoop filter. 1265system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 340732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1266system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5893 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1267system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 1236system.cpu0.toL2Bus.trans_dist::ReadReq 122459 # Transaction distribution 1237system.cpu0.toL2Bus.trans_dist::ReadResp 2635557 # Transaction distribution 1238system.cpu0.toL2Bus.trans_dist::WriteReq 19271 # Transaction distribution 1239system.cpu0.toL2Bus.trans_dist::WriteResp 19271 # Transaction distribution 1240system.cpu0.toL2Bus.trans_dist::WritebackDirty 716131 # Transaction distribution 1241system.cpu0.toL2Bus.trans_dist::WritebackClean 2195168 # Transaction distribution 1242system.cpu0.toL2Bus.trans_dist::CleanEvict 240019 # Transaction distribution 1243system.cpu0.toL2Bus.trans_dist::HardPFReq 309687 # Transaction distribution --- 49 unchanged lines hidden (view full) --- 1293system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1294system.cpu1.branchPred.BTBHitPct 37.018689 # BTB Hit Percentage 1295system.cpu1.branchPred.usedRAS 8699112 # Number of times the RAS was used to get a target. 1296system.cpu1.branchPred.RASInCorrect 707232 # Number of incorrect RAS predictions. 1297system.cpu1.branchPred.indirectLookups 3579063 # Number of indirect predictor lookups. 1298system.cpu1.branchPred.indirectHits 3516137 # Number of indirect target hits. 1299system.cpu1.branchPred.indirectMisses 62926 # Number of indirect misses. 1300system.cpu1.branchPredindirectMispredicted 23615 # Number of mispredicted indirect branches. | 1268system.cpu0.toL2Bus.trans_dist::ReadReq 122459 # Transaction distribution 1269system.cpu0.toL2Bus.trans_dist::ReadResp 2635557 # Transaction distribution 1270system.cpu0.toL2Bus.trans_dist::WriteReq 19271 # Transaction distribution 1271system.cpu0.toL2Bus.trans_dist::WriteResp 19271 # Transaction distribution 1272system.cpu0.toL2Bus.trans_dist::WritebackDirty 716131 # Transaction distribution 1273system.cpu0.toL2Bus.trans_dist::WritebackClean 2195168 # Transaction distribution 1274system.cpu0.toL2Bus.trans_dist::CleanEvict 240019 # Transaction distribution 1275system.cpu0.toL2Bus.trans_dist::HardPFReq 309687 # Transaction distribution --- 49 unchanged lines hidden (view full) --- 1325system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1326system.cpu1.branchPred.BTBHitPct 37.018689 # BTB Hit Percentage 1327system.cpu1.branchPred.usedRAS 8699112 # Number of times the RAS was used to get a target. 1328system.cpu1.branchPred.RASInCorrect 707232 # Number of incorrect RAS predictions. 1329system.cpu1.branchPred.indirectLookups 3579063 # Number of indirect predictor lookups. 1330system.cpu1.branchPred.indirectHits 3516137 # Number of indirect target hits. 1331system.cpu1.branchPred.indirectMisses 62926 # Number of indirect misses. 1332system.cpu1.branchPredindirectMispredicted 23615 # Number of mispredicted indirect branches. |
| 1333system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 1301system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1302system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1303system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1304system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1305system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1306system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1307system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1308system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1322system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1323system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1324system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1325system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1326system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1327system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1328system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1329system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1334system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1335system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1336system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1337system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1338system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1339system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1340system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1341system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1355system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1356system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1357system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1358system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1359system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1360system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1361system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1362system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1363system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 1330system.cpu1.dtb.walker.walks 26974 # Table walker walks requested 1331system.cpu1.dtb.walker.walksShort 26974 # Table walker walks initiated with short descriptors 1332system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 20087 # Level at which table walker walks with short descriptors terminate 1333system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6887 # Level at which table walker walks with short descriptors terminate 1334system.cpu1.dtb.walker.walkWaitTime::samples 26974 # Table walker wait (enqueue to first request) latency 1335system.cpu1.dtb.walker.walkWaitTime::0 26974 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1336system.cpu1.dtb.walker.walkWaitTime::total 26974 # Table walker wait (enqueue to first request) latency 1337system.cpu1.dtb.walker.walkCompletionTime::samples 2714 # Table walker service (enqueue to completion) latency --- 40 unchanged lines hidden (view full) --- 1378system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1379system.cpu1.dtb.perms_faults 283 # Number of TLB faults due to permissions restrictions 1380system.cpu1.dtb.read_accesses 11210412 # DTB read accesses 1381system.cpu1.dtb.write_accesses 6994070 # DTB write accesses 1382system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1383system.cpu1.dtb.hits 18177508 # DTB hits 1384system.cpu1.dtb.misses 26974 # DTB misses 1385system.cpu1.dtb.accesses 18204482 # DTB accesses | 1364system.cpu1.dtb.walker.walks 26974 # Table walker walks requested 1365system.cpu1.dtb.walker.walksShort 26974 # Table walker walks initiated with short descriptors 1366system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 20087 # Level at which table walker walks with short descriptors terminate 1367system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6887 # Level at which table walker walks with short descriptors terminate 1368system.cpu1.dtb.walker.walkWaitTime::samples 26974 # Table walker wait (enqueue to first request) latency 1369system.cpu1.dtb.walker.walkWaitTime::0 26974 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1370system.cpu1.dtb.walker.walkWaitTime::total 26974 # Table walker wait (enqueue to first request) latency 1371system.cpu1.dtb.walker.walkCompletionTime::samples 2714 # Table walker service (enqueue to completion) latency --- 40 unchanged lines hidden (view full) --- 1412system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1413system.cpu1.dtb.perms_faults 283 # Number of TLB faults due to permissions restrictions 1414system.cpu1.dtb.read_accesses 11210412 # DTB read accesses 1415system.cpu1.dtb.write_accesses 6994070 # DTB write accesses 1416system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1417system.cpu1.dtb.hits 18177508 # DTB hits 1418system.cpu1.dtb.misses 26974 # DTB misses 1419system.cpu1.dtb.accesses 18204482 # DTB accesses |
| 1420system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 1386system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1387system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1388system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1389system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1390system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1391system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1392system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1393system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1407system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1408system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1409system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1410system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1411system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1412system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1413system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1414system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1421system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1422system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1423system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1424system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1425system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1426system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1427system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1428system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1442system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1443system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1444system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1445system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1446system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1447system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1448system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1449system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1450system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 1415system.cpu1.itb.walker.walks 2420 # Table walker walks requested 1416system.cpu1.itb.walker.walksShort 2420 # Table walker walks initiated with short descriptors 1417system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate 1418system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2239 # Level at which table walker walks with short descriptors terminate 1419system.cpu1.itb.walker.walkWaitTime::samples 2420 # Table walker wait (enqueue to first request) latency 1420system.cpu1.itb.walker.walkWaitTime::0 2420 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1421system.cpu1.itb.walker.walkWaitTime::total 2420 # Table walker wait (enqueue to first request) latency 1422system.cpu1.itb.walker.walkCompletionTime::samples 1133 # Table walker service (enqueue to completion) latency --- 42 unchanged lines hidden (view full) --- 1465system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1466system.cpu1.itb.perms_faults 1819 # Number of TLB faults due to permissions restrictions 1467system.cpu1.itb.read_accesses 0 # DTB read accesses 1468system.cpu1.itb.write_accesses 0 # DTB write accesses 1469system.cpu1.itb.inst_accesses 39605220 # ITB inst accesses 1470system.cpu1.itb.hits 39602800 # DTB hits 1471system.cpu1.itb.misses 2420 # DTB misses 1472system.cpu1.itb.accesses 39605220 # DTB accesses | 1451system.cpu1.itb.walker.walks 2420 # Table walker walks requested 1452system.cpu1.itb.walker.walksShort 2420 # Table walker walks initiated with short descriptors 1453system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate 1454system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2239 # Level at which table walker walks with short descriptors terminate 1455system.cpu1.itb.walker.walkWaitTime::samples 2420 # Table walker wait (enqueue to first request) latency 1456system.cpu1.itb.walker.walkWaitTime::0 2420 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1457system.cpu1.itb.walker.walkWaitTime::total 2420 # Table walker wait (enqueue to first request) latency 1458system.cpu1.itb.walker.walkCompletionTime::samples 1133 # Table walker service (enqueue to completion) latency --- 42 unchanged lines hidden (view full) --- 1501system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1502system.cpu1.itb.perms_faults 1819 # Number of TLB faults due to permissions restrictions 1503system.cpu1.itb.read_accesses 0 # DTB read accesses 1504system.cpu1.itb.write_accesses 0 # DTB write accesses 1505system.cpu1.itb.inst_accesses 39605220 # ITB inst accesses 1506system.cpu1.itb.hits 39602800 # DTB hits 1507system.cpu1.itb.misses 2420 # DTB misses 1508system.cpu1.itb.accesses 39605220 # DTB accesses |
| 1509system.cpu1.numPwrStateTransitions 5553 # Number of power state transitions 1510system.cpu1.pwrStateClkGateDist::samples 2777 # Distribution of time spent in the clock gated state 1511system.cpu1.pwrStateClkGateDist::mean 1004505001.039251 # Distribution of time spent in the clock gated state 1512system.cpu1.pwrStateClkGateDist::stdev 25654466824.490025 # Distribution of time spent in the clock gated state 1513system.cpu1.pwrStateClkGateDist::underflows 1974 71.08% 71.08% # Distribution of time spent in the clock gated state 1514system.cpu1.pwrStateClkGateDist::1000-5e+10 799 28.77% 99.86% # Distribution of time spent in the clock gated state 1515system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state 1516system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 1517system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 1518system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state 1519system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 1520system.cpu1.pwrStateClkGateDist::max_value 949981296504 # Distribution of time spent in the clock gated state 1521system.cpu1.pwrStateClkGateDist::total 2777 # Distribution of time spent in the clock gated state 1522system.cpu1.pwrStateResidencyTicks::ON 57717018114 # Cumulative time (in ticks) in various power states 1523system.cpu1.pwrStateResidencyTicks::CLK_GATED 2789510387886 # Cumulative time (in ticks) in various power states |
|
| 1473system.cpu1.numCycles 115435582 # number of cpu cycles simulated 1474system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1475system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1476system.cpu1.committedInsts 47603897 # Number of instructions committed 1477system.cpu1.committedOps 58246015 # Number of ops (including micro ops) committed 1478system.cpu1.discardedOps 5049538 # Number of ops (including micro ops) which were discarded before commit 1479system.cpu1.numFetchSuspends 2772 # Number of times Execute suspended instruction fetching 1480system.cpu1.quiesceCycles 5578401245 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt --- 33 unchanged lines hidden (view full) --- 1514system.cpu1.op_class_0::MemWrite 7107919 12.20% 100.00% # Class of committed instruction 1515system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1516system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1517system.cpu1.op_class_0::total 58246015 # Class of committed instruction 1518system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1519system.cpu1.kern.inst.quiesce 2777 # number of quiesce instructions executed 1520system.cpu1.tickCycles 97896037 # Number of cycles that the object actually ticked 1521system.cpu1.idleCycles 17539545 # Total number of cycles that the object has spent stopped | 1524system.cpu1.numCycles 115435582 # number of cpu cycles simulated 1525system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1526system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1527system.cpu1.committedInsts 47603897 # Number of instructions committed 1528system.cpu1.committedOps 58246015 # Number of ops (including micro ops) committed 1529system.cpu1.discardedOps 5049538 # Number of ops (including micro ops) which were discarded before commit 1530system.cpu1.numFetchSuspends 2772 # Number of times Execute suspended instruction fetching 1531system.cpu1.quiesceCycles 5578401245 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt --- 33 unchanged lines hidden (view full) --- 1565system.cpu1.op_class_0::MemWrite 7107919 12.20% 100.00% # Class of committed instruction 1566system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1567system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1568system.cpu1.op_class_0::total 58246015 # Class of committed instruction 1569system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1570system.cpu1.kern.inst.quiesce 2777 # number of quiesce instructions executed 1571system.cpu1.tickCycles 97896037 # Number of cycles that the object actually ticked 1572system.cpu1.idleCycles 17539545 # Total number of cycles that the object has spent stopped |
| 1573system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 1522system.cpu1.dcache.tags.replacements 196286 # number of replacements 1523system.cpu1.dcache.tags.tagsinuse 471.109798 # Cycle average of tags in use 1524system.cpu1.dcache.tags.total_refs 17737294 # Total number of references to valid blocks. 1525system.cpu1.dcache.tags.sampled_refs 196629 # Sample count of references to valid blocks. 1526system.cpu1.dcache.tags.avg_refs 90.206907 # Average number of references to valid blocks. 1527system.cpu1.dcache.tags.warmup_cycle 91177108000 # Cycle when the warmup percentage was hit. 1528system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.109798 # Average occupied blocks per requestor 1529system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920136 # Average percentage of cache occupancy 1530system.cpu1.dcache.tags.occ_percent::total 0.920136 # Average percentage of cache occupancy 1531system.cpu1.dcache.tags.occ_task_id_blocks::1024 343 # Occupied blocks per task id 1532system.cpu1.dcache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id 1533system.cpu1.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id 1534system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id 1535system.cpu1.dcache.tags.tag_accesses 36398755 # Number of tag accesses 1536system.cpu1.dcache.tags.data_accesses 36398755 # Number of data accesses | 1574system.cpu1.dcache.tags.replacements 196286 # number of replacements 1575system.cpu1.dcache.tags.tagsinuse 471.109798 # Cycle average of tags in use 1576system.cpu1.dcache.tags.total_refs 17737294 # Total number of references to valid blocks. 1577system.cpu1.dcache.tags.sampled_refs 196629 # Sample count of references to valid blocks. 1578system.cpu1.dcache.tags.avg_refs 90.206907 # Average number of references to valid blocks. 1579system.cpu1.dcache.tags.warmup_cycle 91177108000 # Cycle when the warmup percentage was hit. 1580system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.109798 # Average occupied blocks per requestor 1581system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920136 # Average percentage of cache occupancy 1582system.cpu1.dcache.tags.occ_percent::total 0.920136 # Average percentage of cache occupancy 1583system.cpu1.dcache.tags.occ_task_id_blocks::1024 343 # Occupied blocks per task id 1584system.cpu1.dcache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id 1585system.cpu1.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id 1586system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id 1587system.cpu1.dcache.tags.tag_accesses 36398755 # Number of tag accesses 1588system.cpu1.dcache.tags.data_accesses 36398755 # Number of data accesses |
| 1589system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 1537system.cpu1.dcache.ReadReq_hits::cpu1.data 10795076 # number of ReadReq hits 1538system.cpu1.dcache.ReadReq_hits::total 10795076 # number of ReadReq hits 1539system.cpu1.dcache.WriteReq_hits::cpu1.data 6704752 # number of WriteReq hits 1540system.cpu1.dcache.WriteReq_hits::total 6704752 # number of WriteReq hits 1541system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50350 # number of SoftPFReq hits 1542system.cpu1.dcache.SoftPFReq_hits::total 50350 # number of SoftPFReq hits 1543system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80171 # number of LoadLockedReq hits 1544system.cpu1.dcache.LoadLockedReq_hits::total 80171 # number of LoadLockedReq hits --- 160 unchanged lines hidden (view full) --- 1705system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18737.126355 # average overall mshr miss latency 1706system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18737.126355 # average overall mshr miss latency 1707system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18629.486399 # average overall mshr miss latency 1708system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18629.486399 # average overall mshr miss latency 1709system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171920.653078 # average ReadReq mshr uncacheable latency 1710system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171920.653078 # average ReadReq mshr uncacheable latency 1711system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94713.295394 # average overall mshr uncacheable latency 1712system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 94713.295394 # average overall mshr uncacheable latency | 1590system.cpu1.dcache.ReadReq_hits::cpu1.data 10795076 # number of ReadReq hits 1591system.cpu1.dcache.ReadReq_hits::total 10795076 # number of ReadReq hits 1592system.cpu1.dcache.WriteReq_hits::cpu1.data 6704752 # number of WriteReq hits 1593system.cpu1.dcache.WriteReq_hits::total 6704752 # number of WriteReq hits 1594system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50350 # number of SoftPFReq hits 1595system.cpu1.dcache.SoftPFReq_hits::total 50350 # number of SoftPFReq hits 1596system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80171 # number of LoadLockedReq hits 1597system.cpu1.dcache.LoadLockedReq_hits::total 80171 # number of LoadLockedReq hits --- 160 unchanged lines hidden (view full) --- 1758system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18737.126355 # average overall mshr miss latency 1759system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18737.126355 # average overall mshr miss latency 1760system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18629.486399 # average overall mshr miss latency 1761system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18629.486399 # average overall mshr miss latency 1762system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171920.653078 # average ReadReq mshr uncacheable latency 1763system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171920.653078 # average ReadReq mshr uncacheable latency 1764system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94713.295394 # average overall mshr uncacheable latency 1765system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 94713.295394 # average overall mshr uncacheable latency |
| 1766system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 1713system.cpu1.icache.tags.replacements 946364 # number of replacements 1714system.cpu1.icache.tags.tagsinuse 499.210861 # Cycle average of tags in use 1715system.cpu1.icache.tags.total_refs 38654025 # Total number of references to valid blocks. 1716system.cpu1.icache.tags.sampled_refs 946876 # Sample count of references to valid blocks. 1717system.cpu1.icache.tags.avg_refs 40.822690 # Average number of references to valid blocks. 1718system.cpu1.icache.tags.warmup_cycle 72815756000 # Cycle when the warmup percentage was hit. 1719system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.210861 # Average occupied blocks per requestor 1720system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975021 # Average percentage of cache occupancy 1721system.cpu1.icache.tags.occ_percent::total 0.975021 # Average percentage of cache occupancy 1722system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1723system.cpu1.icache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id 1724system.cpu1.icache.tags.age_task_id_blocks_1024::3 50 # Occupied blocks per task id 1725system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1726system.cpu1.icache.tags.tag_accesses 80148678 # Number of tag accesses 1727system.cpu1.icache.tags.data_accesses 80148678 # Number of data accesses | 1767system.cpu1.icache.tags.replacements 946364 # number of replacements 1768system.cpu1.icache.tags.tagsinuse 499.210861 # Cycle average of tags in use 1769system.cpu1.icache.tags.total_refs 38654025 # Total number of references to valid blocks. 1770system.cpu1.icache.tags.sampled_refs 946876 # Sample count of references to valid blocks. 1771system.cpu1.icache.tags.avg_refs 40.822690 # Average number of references to valid blocks. 1772system.cpu1.icache.tags.warmup_cycle 72815756000 # Cycle when the warmup percentage was hit. 1773system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.210861 # Average occupied blocks per requestor 1774system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975021 # Average percentage of cache occupancy 1775system.cpu1.icache.tags.occ_percent::total 0.975021 # Average percentage of cache occupancy 1776system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1777system.cpu1.icache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id 1778system.cpu1.icache.tags.age_task_id_blocks_1024::3 50 # Occupied blocks per task id 1779system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1780system.cpu1.icache.tags.tag_accesses 80148678 # Number of tag accesses 1781system.cpu1.icache.tags.data_accesses 80148678 # Number of data accesses |
| 1782system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 1728system.cpu1.icache.ReadReq_hits::cpu1.inst 38654025 # number of ReadReq hits 1729system.cpu1.icache.ReadReq_hits::total 38654025 # number of ReadReq hits 1730system.cpu1.icache.demand_hits::cpu1.inst 38654025 # number of demand (read+write) hits 1731system.cpu1.icache.demand_hits::total 38654025 # number of demand (read+write) hits 1732system.cpu1.icache.overall_hits::cpu1.inst 38654025 # number of overall hits 1733system.cpu1.icache.overall_hits::total 38654025 # number of overall hits 1734system.cpu1.icache.ReadReq_misses::cpu1.inst 946876 # number of ReadReq misses 1735system.cpu1.icache.ReadReq_misses::total 946876 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 1800system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average overall mshr miss latency 1801system.cpu1.icache.demand_avg_mshr_miss_latency::total 8291.747811 # average overall mshr miss latency 1802system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average overall mshr miss latency 1803system.cpu1.icache.overall_avg_mshr_miss_latency::total 8291.747811 # average overall mshr miss latency 1804system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429 # average ReadReq mshr uncacheable latency 1805system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 93522.321429 # average ReadReq mshr uncacheable latency 1806system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429 # average overall mshr uncacheable latency 1807system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 93522.321429 # average overall mshr uncacheable latency | 1783system.cpu1.icache.ReadReq_hits::cpu1.inst 38654025 # number of ReadReq hits 1784system.cpu1.icache.ReadReq_hits::total 38654025 # number of ReadReq hits 1785system.cpu1.icache.demand_hits::cpu1.inst 38654025 # number of demand (read+write) hits 1786system.cpu1.icache.demand_hits::total 38654025 # number of demand (read+write) hits 1787system.cpu1.icache.overall_hits::cpu1.inst 38654025 # number of overall hits 1788system.cpu1.icache.overall_hits::total 38654025 # number of overall hits 1789system.cpu1.icache.ReadReq_misses::cpu1.inst 946876 # number of ReadReq misses 1790system.cpu1.icache.ReadReq_misses::total 946876 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 1855system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average overall mshr miss latency 1856system.cpu1.icache.demand_avg_mshr_miss_latency::total 8291.747811 # average overall mshr miss latency 1857system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average overall mshr miss latency 1858system.cpu1.icache.overall_avg_mshr_miss_latency::total 8291.747811 # average overall mshr miss latency 1859system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429 # average ReadReq mshr uncacheable latency 1860system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 93522.321429 # average ReadReq mshr uncacheable latency 1861system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429 # average overall mshr uncacheable latency 1862system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 93522.321429 # average overall mshr uncacheable latency |
| 1863system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 1808system.cpu1.l2cache.prefetcher.num_hwpf_issued 199879 # number of hwpf issued 1809system.cpu1.l2cache.prefetcher.pfIdentified 199934 # number of prefetch candidates identified 1810system.cpu1.l2cache.prefetcher.pfBufferHit 48 # number of redundant prefetches already in prefetch queue 1811system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1812system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1813system.cpu1.l2cache.prefetcher.pfSpanPage 58626 # number of prefetches not generated due to page crossing | 1864system.cpu1.l2cache.prefetcher.num_hwpf_issued 199879 # number of hwpf issued 1865system.cpu1.l2cache.prefetcher.pfIdentified 199934 # number of prefetch candidates identified 1866system.cpu1.l2cache.prefetcher.pfBufferHit 48 # number of redundant prefetches already in prefetch queue 1867system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1868system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1869system.cpu1.l2cache.prefetcher.pfSpanPage 58626 # number of prefetches not generated due to page crossing |
| 1870system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 1814system.cpu1.l2cache.tags.replacements 53638 # number of replacements 1815system.cpu1.l2cache.tags.tagsinuse 15286.424872 # Cycle average of tags in use 1816system.cpu1.l2cache.tags.total_refs 2058198 # Total number of references to valid blocks. 1817system.cpu1.l2cache.tags.sampled_refs 68366 # Sample count of references to valid blocks. 1818system.cpu1.l2cache.tags.avg_refs 30.105579 # Average number of references to valid blocks. 1819system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1820system.cpu1.l2cache.tags.occ_blocks::writebacks 14816.571197 # Average occupied blocks per requestor 1821system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 39.116539 # Average occupied blocks per requestor --- 16 unchanged lines hidden (view full) --- 1838system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id 1839system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5681 # Occupied blocks per task id 1840system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7813 # Occupied blocks per task id 1841system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.055359 # Percentage of cache occupancy per task id 1842system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002747 # Percentage of cache occupancy per task id 1843system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.840820 # Percentage of cache occupancy per task id 1844system.cpu1.l2cache.tags.tag_accesses 38543839 # Number of tag accesses 1845system.cpu1.l2cache.tags.data_accesses 38543839 # Number of data accesses | 1871system.cpu1.l2cache.tags.replacements 53638 # number of replacements 1872system.cpu1.l2cache.tags.tagsinuse 15286.424872 # Cycle average of tags in use 1873system.cpu1.l2cache.tags.total_refs 2058198 # Total number of references to valid blocks. 1874system.cpu1.l2cache.tags.sampled_refs 68366 # Sample count of references to valid blocks. 1875system.cpu1.l2cache.tags.avg_refs 30.105579 # Average number of references to valid blocks. 1876system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1877system.cpu1.l2cache.tags.occ_blocks::writebacks 14816.571197 # Average occupied blocks per requestor 1878system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 39.116539 # Average occupied blocks per requestor --- 16 unchanged lines hidden (view full) --- 1895system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id 1896system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5681 # Occupied blocks per task id 1897system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7813 # Occupied blocks per task id 1898system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.055359 # Percentage of cache occupancy per task id 1899system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002747 # Percentage of cache occupancy per task id 1900system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.840820 # Percentage of cache occupancy per task id 1901system.cpu1.l2cache.tags.tag_accesses 38543839 # Number of tag accesses 1902system.cpu1.l2cache.tags.data_accesses 38543839 # Number of data accesses |
| 1903system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 1846system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 30076 # number of ReadReq hits 1847system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 3135 # number of ReadReq hits 1848system.cpu1.l2cache.ReadReq_hits::total 33211 # number of ReadReq hits 1849system.cpu1.l2cache.WritebackDirty_hits::writebacks 117792 # number of WritebackDirty hits 1850system.cpu1.l2cache.WritebackDirty_hits::total 117792 # number of WritebackDirty hits 1851system.cpu1.l2cache.WritebackClean_hits::writebacks 1004693 # number of WritebackClean hits 1852system.cpu1.l2cache.WritebackClean_hits::total 1004693 # number of WritebackClean hits 1853system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28032 # number of ReadExReq hits --- 285 unchanged lines hidden (view full) --- 2139system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90303.930181 # average overall mshr uncacheable latency 2140system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90283.562790 # average overall mshr uncacheable latency 2141system.cpu1.toL2Bus.snoop_filter.tot_requests 2394243 # Total number of requests made to the snoop filter. 2142system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1206431 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2143system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20164 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2144system.cpu1.toL2Bus.snoop_filter.tot_snoops 192169 # Total number of snoops made to the snoop filter. 2145system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 190372 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2146system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1797 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1904system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 30076 # number of ReadReq hits 1905system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 3135 # number of ReadReq hits 1906system.cpu1.l2cache.ReadReq_hits::total 33211 # number of ReadReq hits 1907system.cpu1.l2cache.WritebackDirty_hits::writebacks 117792 # number of WritebackDirty hits 1908system.cpu1.l2cache.WritebackDirty_hits::total 117792 # number of WritebackDirty hits 1909system.cpu1.l2cache.WritebackClean_hits::writebacks 1004693 # number of WritebackClean hits 1910system.cpu1.l2cache.WritebackClean_hits::total 1004693 # number of WritebackClean hits 1911system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28032 # number of ReadExReq hits --- 285 unchanged lines hidden (view full) --- 2197system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90303.930181 # average overall mshr uncacheable latency 2198system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90283.562790 # average overall mshr uncacheable latency 2199system.cpu1.toL2Bus.snoop_filter.tot_requests 2394243 # Total number of requests made to the snoop filter. 2200system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1206431 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2201system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20164 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2202system.cpu1.toL2Bus.snoop_filter.tot_snoops 192169 # Total number of snoops made to the snoop filter. 2203system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 190372 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2204system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1797 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 2205system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 2147system.cpu1.toL2Bus.trans_dist::ReadReq 53056 # Transaction distribution 2148system.cpu1.toL2Bus.trans_dist::ReadResp 1216172 # Transaction distribution 2149system.cpu1.toL2Bus.trans_dist::WriteReq 11758 # Transaction distribution 2150system.cpu1.toL2Bus.trans_dist::WriteResp 11758 # Transaction distribution 2151system.cpu1.toL2Bus.trans_dist::WritebackDirty 154274 # Transaction distribution 2152system.cpu1.toL2Bus.trans_dist::WritebackClean 1024857 # Transaction distribution 2153system.cpu1.toL2Bus.trans_dist::CleanEvict 118852 # Transaction distribution 2154system.cpu1.toL2Bus.trans_dist::HardPFReq 31456 # Transaction distribution --- 36 unchanged lines hidden (view full) --- 2191system.cpu1.toL2Bus.respLayer0.occupancy 1420645672 # Layer occupancy (ticks) 2192system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2193system.cpu1.toL2Bus.respLayer1.occupancy 410383006 # Layer occupancy (ticks) 2194system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2195system.cpu1.toL2Bus.respLayer2.occupancy 4659998 # Layer occupancy (ticks) 2196system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2197system.cpu1.toL2Bus.respLayer3.occupancy 33872477 # Layer occupancy (ticks) 2198system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2206system.cpu1.toL2Bus.trans_dist::ReadReq 53056 # Transaction distribution 2207system.cpu1.toL2Bus.trans_dist::ReadResp 1216172 # Transaction distribution 2208system.cpu1.toL2Bus.trans_dist::WriteReq 11758 # Transaction distribution 2209system.cpu1.toL2Bus.trans_dist::WriteResp 11758 # Transaction distribution 2210system.cpu1.toL2Bus.trans_dist::WritebackDirty 154274 # Transaction distribution 2211system.cpu1.toL2Bus.trans_dist::WritebackClean 1024857 # Transaction distribution 2212system.cpu1.toL2Bus.trans_dist::CleanEvict 118852 # Transaction distribution 2213system.cpu1.toL2Bus.trans_dist::HardPFReq 31456 # Transaction distribution --- 36 unchanged lines hidden (view full) --- 2250system.cpu1.toL2Bus.respLayer0.occupancy 1420645672 # Layer occupancy (ticks) 2251system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2252system.cpu1.toL2Bus.respLayer1.occupancy 410383006 # Layer occupancy (ticks) 2253system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2254system.cpu1.toL2Bus.respLayer2.occupancy 4659998 # Layer occupancy (ticks) 2255system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2256system.cpu1.toL2Bus.respLayer3.occupancy 33872477 # Layer occupancy (ticks) 2257system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2258system.iobus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 2199system.iobus.trans_dist::ReadReq 31003 # Transaction distribution 2200system.iobus.trans_dist::ReadResp 31003 # Transaction distribution 2201system.iobus.trans_dist::WriteReq 59422 # Transaction distribution 2202system.iobus.trans_dist::WriteResp 59422 # Transaction distribution 2203system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) 2204system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2205system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2206system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 78 unchanged lines hidden (view full) --- 2285system.iobus.reqLayer24.occupancy 33143500 # Layer occupancy (ticks) 2286system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2287system.iobus.reqLayer25.occupancy 187679851 # Layer occupancy (ticks) 2288system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2289system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) 2290system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2291system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) 2292system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 2259system.iobus.trans_dist::ReadReq 31003 # Transaction distribution 2260system.iobus.trans_dist::ReadResp 31003 # Transaction distribution 2261system.iobus.trans_dist::WriteReq 59422 # Transaction distribution 2262system.iobus.trans_dist::WriteResp 59422 # Transaction distribution 2263system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) 2264system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2265system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2266system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 78 unchanged lines hidden (view full) --- 2345system.iobus.reqLayer24.occupancy 33143500 # Layer occupancy (ticks) 2346system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2347system.iobus.reqLayer25.occupancy 187679851 # Layer occupancy (ticks) 2348system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2349system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) 2350system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2351system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) 2352system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2353system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 2293system.iocache.tags.replacements 36449 # number of replacements 2294system.iocache.tags.tagsinuse 14.476064 # Cycle average of tags in use 2295system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2296system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. 2297system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2298system.iocache.tags.warmup_cycle 271175186000 # Cycle when the warmup percentage was hit. 2299system.iocache.tags.occ_blocks::realview.ide 14.476064 # Average occupied blocks per requestor 2300system.iocache.tags.occ_percent::realview.ide 0.904754 # Average percentage of cache occupancy 2301system.iocache.tags.occ_percent::total 0.904754 # Average percentage of cache occupancy 2302system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2303system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2304system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2305system.iocache.tags.tag_accesses 328203 # Number of tag accesses 2306system.iocache.tags.data_accesses 328203 # Number of data accesses | 2354system.iocache.tags.replacements 36449 # number of replacements 2355system.iocache.tags.tagsinuse 14.476064 # Cycle average of tags in use 2356system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2357system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. 2358system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2359system.iocache.tags.warmup_cycle 271175186000 # Cycle when the warmup percentage was hit. 2360system.iocache.tags.occ_blocks::realview.ide 14.476064 # Average occupied blocks per requestor 2361system.iocache.tags.occ_percent::realview.ide 0.904754 # Average percentage of cache occupancy 2362system.iocache.tags.occ_percent::total 0.904754 # Average percentage of cache occupancy 2363system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2364system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2365system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2366system.iocache.tags.tag_accesses 328203 # Number of tag accesses 2367system.iocache.tags.data_accesses 328203 # Number of data accesses |
| 2368system.iocache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 2307system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses 2308system.iocache.ReadReq_misses::total 243 # number of ReadReq misses 2309system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2310system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2311system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses 2312system.iocache.demand_misses::total 36467 # number of demand (read+write) misses 2313system.iocache.overall_misses::realview.ide 36467 # number of overall misses 2314system.iocache.overall_misses::total 36467 # number of overall misses --- 64 unchanged lines hidden (view full) --- 2379system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80505.666667 # average ReadReq mshr miss latency 2380system.iocache.ReadReq_avg_mshr_miss_latency::total 80505.666667 # average ReadReq mshr miss latency 2381system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68680.814432 # average WriteLineReq mshr miss latency 2382system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68680.814432 # average WriteLineReq mshr miss latency 2383system.iocache.demand_avg_mshr_miss_latency::realview.ide 68759.610031 # average overall mshr miss latency 2384system.iocache.demand_avg_mshr_miss_latency::total 68759.610031 # average overall mshr miss latency 2385system.iocache.overall_avg_mshr_miss_latency::realview.ide 68759.610031 # average overall mshr miss latency 2386system.iocache.overall_avg_mshr_miss_latency::total 68759.610031 # average overall mshr miss latency | 2369system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses 2370system.iocache.ReadReq_misses::total 243 # number of ReadReq misses 2371system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2372system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2373system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses 2374system.iocache.demand_misses::total 36467 # number of demand (read+write) misses 2375system.iocache.overall_misses::realview.ide 36467 # number of overall misses 2376system.iocache.overall_misses::total 36467 # number of overall misses --- 64 unchanged lines hidden (view full) --- 2441system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80505.666667 # average ReadReq mshr miss latency 2442system.iocache.ReadReq_avg_mshr_miss_latency::total 80505.666667 # average ReadReq mshr miss latency 2443system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68680.814432 # average WriteLineReq mshr miss latency 2444system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68680.814432 # average WriteLineReq mshr miss latency 2445system.iocache.demand_avg_mshr_miss_latency::realview.ide 68759.610031 # average overall mshr miss latency 2446system.iocache.demand_avg_mshr_miss_latency::total 68759.610031 # average overall mshr miss latency 2447system.iocache.overall_avg_mshr_miss_latency::realview.ide 68759.610031 # average overall mshr miss latency 2448system.iocache.overall_avg_mshr_miss_latency::total 68759.610031 # average overall mshr miss latency |
| 2449system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 2387system.l2c.tags.replacements 131721 # number of replacements 2388system.l2c.tags.tagsinuse 63119.316885 # Cycle average of tags in use 2389system.l2c.tags.total_refs 480965 # Total number of references to valid blocks. 2390system.l2c.tags.sampled_refs 195649 # Sample count of references to valid blocks. 2391system.l2c.tags.avg_refs 2.458305 # Average number of references to valid blocks. 2392system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2393system.l2c.tags.occ_blocks::writebacks 13508.912510 # Average occupied blocks per requestor 2394system.l2c.tags.occ_blocks::cpu0.dtb.walker 74.990696 # Average occupied blocks per requestor --- 29 unchanged lines hidden (view full) --- 2424system.l2c.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id 2425system.l2c.tags.age_task_id_blocks_1024::3 3689 # Occupied blocks per task id 2426system.l2c.tags.age_task_id_blocks_1024::4 32199 # Occupied blocks per task id 2427system.l2c.tags.occ_task_id_percent::1022 0.419968 # Percentage of cache occupancy per task id 2428system.l2c.tags.occ_task_id_percent::1023 0.001205 # Percentage of cache occupancy per task id 2429system.l2c.tags.occ_task_id_percent::1024 0.554291 # Percentage of cache occupancy per task id 2430system.l2c.tags.tag_accesses 6440622 # Number of tag accesses 2431system.l2c.tags.data_accesses 6440622 # Number of data accesses | 2450system.l2c.tags.replacements 131721 # number of replacements 2451system.l2c.tags.tagsinuse 63119.316885 # Cycle average of tags in use 2452system.l2c.tags.total_refs 480965 # Total number of references to valid blocks. 2453system.l2c.tags.sampled_refs 195649 # Sample count of references to valid blocks. 2454system.l2c.tags.avg_refs 2.458305 # Average number of references to valid blocks. 2455system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2456system.l2c.tags.occ_blocks::writebacks 13508.912510 # Average occupied blocks per requestor 2457system.l2c.tags.occ_blocks::cpu0.dtb.walker 74.990696 # Average occupied blocks per requestor --- 29 unchanged lines hidden (view full) --- 2487system.l2c.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id 2488system.l2c.tags.age_task_id_blocks_1024::3 3689 # Occupied blocks per task id 2489system.l2c.tags.age_task_id_blocks_1024::4 32199 # Occupied blocks per task id 2490system.l2c.tags.occ_task_id_percent::1022 0.419968 # Percentage of cache occupancy per task id 2491system.l2c.tags.occ_task_id_percent::1023 0.001205 # Percentage of cache occupancy per task id 2492system.l2c.tags.occ_task_id_percent::1024 0.554291 # Percentage of cache occupancy per task id 2493system.l2c.tags.tag_accesses 6440622 # Number of tag accesses 2494system.l2c.tags.data_accesses 6440622 # Number of data accesses |
| 2495system.l2c.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 2432system.l2c.WritebackDirty_hits::writebacks 269250 # number of WritebackDirty hits 2433system.l2c.WritebackDirty_hits::total 269250 # number of WritebackDirty hits 2434system.l2c.UpgradeReq_hits::cpu0.data 33826 # number of UpgradeReq hits 2435system.l2c.UpgradeReq_hits::cpu1.data 2712 # number of UpgradeReq hits 2436system.l2c.UpgradeReq_hits::total 36538 # number of UpgradeReq hits 2437system.l2c.SCUpgradeReq_hits::cpu0.data 2202 # number of SCUpgradeReq hits 2438system.l2c.SCUpgradeReq_hits::cpu1.data 1074 # number of SCUpgradeReq hits 2439system.l2c.SCUpgradeReq_hits::total 3276 # number of SCUpgradeReq hits --- 441 unchanged lines hidden (view full) --- 2881system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80396.501050 # average overall mshr uncacheable latency 2882system.l2c.overall_avg_mshr_uncacheable_latency::total 92143.139439 # average overall mshr uncacheable latency 2883system.membus.snoop_filter.tot_requests 526346 # Total number of requests made to the snoop filter. 2884system.membus.snoop_filter.hit_single_requests 301567 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2885system.membus.snoop_filter.hit_multi_requests 567 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2886system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2887system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2888system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 2496system.l2c.WritebackDirty_hits::writebacks 269250 # number of WritebackDirty hits 2497system.l2c.WritebackDirty_hits::total 269250 # number of WritebackDirty hits 2498system.l2c.UpgradeReq_hits::cpu0.data 33826 # number of UpgradeReq hits 2499system.l2c.UpgradeReq_hits::cpu1.data 2712 # number of UpgradeReq hits 2500system.l2c.UpgradeReq_hits::total 36538 # number of UpgradeReq hits 2501system.l2c.SCUpgradeReq_hits::cpu0.data 2202 # number of SCUpgradeReq hits 2502system.l2c.SCUpgradeReq_hits::cpu1.data 1074 # number of SCUpgradeReq hits 2503system.l2c.SCUpgradeReq_hits::total 3276 # number of SCUpgradeReq hits --- 441 unchanged lines hidden (view full) --- 2945system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80396.501050 # average overall mshr uncacheable latency 2946system.l2c.overall_avg_mshr_uncacheable_latency::total 92143.139439 # average overall mshr uncacheable latency 2947system.membus.snoop_filter.tot_requests 526346 # Total number of requests made to the snoop filter. 2948system.membus.snoop_filter.hit_single_requests 301567 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2949system.membus.snoop_filter.hit_multi_requests 567 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2950system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2951system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2952system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 2953system.membus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 2889system.membus.trans_dist::ReadReq 38557 # Transaction distribution 2890system.membus.trans_dist::ReadResp 213679 # Transaction distribution 2891system.membus.trans_dist::WriteReq 31029 # Transaction distribution 2892system.membus.trans_dist::WriteResp 31029 # Transaction distribution 2893system.membus.trans_dist::WritebackDirty 138659 # Transaction distribution 2894system.membus.trans_dist::CleanEvict 18543 # Transaction distribution 2895system.membus.trans_dist::UpgradeReq 76988 # Transaction distribution 2896system.membus.trans_dist::SCUpgradeReq 41072 # Transaction distribution --- 38 unchanged lines hidden (view full) --- 2935system.membus.reqLayer2.occupancy 12314999 # Layer occupancy (ticks) 2936system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2937system.membus.reqLayer5.occupancy 1002605728 # Layer occupancy (ticks) 2938system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 2939system.membus.respLayer2.occupancy 1133893717 # Layer occupancy (ticks) 2940system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2941system.membus.respLayer3.occupancy 1318131 # Layer occupancy (ticks) 2942system.membus.respLayer3.utilization 0.0 # Layer utilization (%) | 2954system.membus.trans_dist::ReadReq 38557 # Transaction distribution 2955system.membus.trans_dist::ReadResp 213679 # Transaction distribution 2956system.membus.trans_dist::WriteReq 31029 # Transaction distribution 2957system.membus.trans_dist::WriteResp 31029 # Transaction distribution 2958system.membus.trans_dist::WritebackDirty 138659 # Transaction distribution 2959system.membus.trans_dist::CleanEvict 18543 # Transaction distribution 2960system.membus.trans_dist::UpgradeReq 76988 # Transaction distribution 2961system.membus.trans_dist::SCUpgradeReq 41072 # Transaction distribution --- 38 unchanged lines hidden (view full) --- 3000system.membus.reqLayer2.occupancy 12314999 # Layer occupancy (ticks) 3001system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3002system.membus.reqLayer5.occupancy 1002605728 # Layer occupancy (ticks) 3003system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3004system.membus.respLayer2.occupancy 1133893717 # Layer occupancy (ticks) 3005system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3006system.membus.respLayer3.occupancy 1318131 # Layer occupancy (ticks) 3007system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 3008system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3009system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3010system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3011system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3012system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3013system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3014system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 2943system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 2944system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 2945system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 2946system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 2947system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 2948system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 3015system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3016system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3017system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3018system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3019system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3020system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 3021system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3022system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 2949system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2950system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2951system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2952system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2953system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2954system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2955system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 2956system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 2972system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2973system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2974system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2975system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2976system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2977system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2978system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2979system.realview.ethernet.droppedPackets 0 # number of packets dropped | 3023system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3024system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3025system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3026system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3027system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3028system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3029system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3030system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 3046system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3047system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3048system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3049system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3050system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3051system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3052system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3053system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 3054system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3055system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3056system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3057system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3058system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3059system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3060system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 2980system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 2981system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 2982system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 2983system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 3061system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3062system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3063system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3064system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 3065system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3066system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3067system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3068system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3069system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3070system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3071system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3072system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3073system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3074system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3075system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states 3076system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 2984system.toL2Bus.snoop_filter.tot_requests 1068358 # Total number of requests made to the snoop filter. 2985system.toL2Bus.snoop_filter.hit_single_requests 578478 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2986system.toL2Bus.snoop_filter.hit_multi_requests 169754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2987system.toL2Bus.snoop_filter.tot_snoops 19773 # Total number of snoops made to the snoop filter. 2988system.toL2Bus.snoop_filter.hit_single_snoops 18732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2989system.toL2Bus.snoop_filter.hit_multi_snoops 1041 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 3077system.toL2Bus.snoop_filter.tot_requests 1068358 # Total number of requests made to the snoop filter. 3078system.toL2Bus.snoop_filter.hit_single_requests 578478 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3079system.toL2Bus.snoop_filter.hit_multi_requests 169754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3080system.toL2Bus.snoop_filter.tot_snoops 19773 # Total number of snoops made to the snoop filter. 3081system.toL2Bus.snoop_filter.hit_single_snoops 18732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3082system.toL2Bus.snoop_filter.hit_multi_snoops 1041 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 3083system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states |
|
| 2990system.toL2Bus.trans_dist::ReadReq 38560 # Transaction distribution 2991system.toL2Bus.trans_dist::ReadResp 513452 # Transaction distribution 2992system.toL2Bus.trans_dist::WriteReq 31029 # Transaction distribution 2993system.toL2Bus.trans_dist::WriteResp 31029 # Transaction distribution 2994system.toL2Bus.trans_dist::WritebackDirty 371703 # Transaction distribution 2995system.toL2Bus.trans_dist::CleanEvict 144260 # Transaction distribution 2996system.toL2Bus.trans_dist::UpgradeReq 113415 # Transaction distribution 2997system.toL2Bus.trans_dist::SCUpgradeReq 44348 # Transaction distribution --- 35 unchanged lines hidden --- | 3084system.toL2Bus.trans_dist::ReadReq 38560 # Transaction distribution 3085system.toL2Bus.trans_dist::ReadResp 513452 # Transaction distribution 3086system.toL2Bus.trans_dist::WriteReq 31029 # Transaction distribution 3087system.toL2Bus.trans_dist::WriteResp 31029 # Transaction distribution 3088system.toL2Bus.trans_dist::WritebackDirty 371703 # Transaction distribution 3089system.toL2Bus.trans_dist::CleanEvict 144260 # Transaction distribution 3090system.toL2Bus.trans_dist::UpgradeReq 113415 # Transaction distribution 3091system.toL2Bus.trans_dist::SCUpgradeReq 44348 # Transaction distribution --- 35 unchanged lines hidden --- |