| stats.txt (11502:e273e86a873d) | stats.txt (11507:be6065c1d8d2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.847227 # Number of seconds simulated 4sim_ticks 2847227406000 # Number of ticks simulated 5final_tick 2847227406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.847227 # Number of seconds simulated 4sim_ticks 2847227406000 # Number of ticks simulated 5final_tick 2847227406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 172654 # Simulator instruction rate (inst/s) 8host_op_rate 209070 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3861033235 # Simulator tick rate (ticks/s) 10host_mem_usage 617124 # Number of bytes of host memory used 11host_seconds 737.43 # Real time elapsed on the host | 7host_inst_rate 111277 # Simulator instruction rate (inst/s) 8host_op_rate 134747 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2488466073 # Simulator tick rate (ticks/s) 10host_mem_usage 617520 # Number of bytes of host memory used 11host_seconds 1144.17 # Real time elapsed on the host |
| 12sim_insts 127319545 # Number of instructions simulated 13sim_ops 154173476 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 7488 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1647744 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1317552 # Number of bytes read from this memory --- 416 unchanged lines hidden (view full) --- 436system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 437system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 68420 # Table walker requests started/completed, data/inst 438system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6777 # Table walker requests started/completed, data/inst 439system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 440system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6777 # Table walker requests started/completed, data/inst 441system.cpu0.dtb.walker.walkRequestOrigin::total 75197 # Table walker requests started/completed, data/inst 442system.cpu0.dtb.inst_hits 0 # ITB inst hits 443system.cpu0.dtb.inst_misses 0 # ITB inst misses | 12sim_insts 127319545 # Number of instructions simulated 13sim_ops 154173476 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 7488 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1647744 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1317552 # Number of bytes read from this memory --- 416 unchanged lines hidden (view full) --- 436system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 437system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 68420 # Table walker requests started/completed, data/inst 438system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6777 # Table walker requests started/completed, data/inst 439system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 440system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6777 # Table walker requests started/completed, data/inst 441system.cpu0.dtb.walker.walkRequestOrigin::total 75197 # Table walker requests started/completed, data/inst 442system.cpu0.dtb.inst_hits 0 # ITB inst hits 443system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 444system.cpu0.dtb.read_hits 17339980 # DTB read hits | 444system.cpu0.dtb.read_hits 17339981 # DTB read hits |
| 445system.cpu0.dtb.read_misses 61941 # DTB read misses | 445system.cpu0.dtb.read_misses 61941 # DTB read misses |
| 446system.cpu0.dtb.write_hits 14540399 # DTB write hits | 446system.cpu0.dtb.write_hits 14540400 # DTB write hits |
| 447system.cpu0.dtb.write_misses 6479 # DTB write misses 448system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 449system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 450system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 451system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 452system.cpu0.dtb.flush_entries 3513 # Number of entries that have been flushed from TLB 453system.cpu0.dtb.align_faults 1354 # Number of TLB faults due to alignment restrictions 454system.cpu0.dtb.prefetch_faults 1959 # Number of TLB faults due to prefetch 455system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 456system.cpu0.dtb.perms_faults 521 # Number of TLB faults due to permissions restrictions | 447system.cpu0.dtb.write_misses 6479 # DTB write misses 448system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 449system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 450system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 451system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 452system.cpu0.dtb.flush_entries 3513 # Number of entries that have been flushed from TLB 453system.cpu0.dtb.align_faults 1354 # Number of TLB faults due to alignment restrictions 454system.cpu0.dtb.prefetch_faults 1959 # Number of TLB faults due to prefetch 455system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 456system.cpu0.dtb.perms_faults 521 # Number of TLB faults due to permissions restrictions |
| 457system.cpu0.dtb.read_accesses 17401921 # DTB read accesses 458system.cpu0.dtb.write_accesses 14546878 # DTB write accesses | 457system.cpu0.dtb.read_accesses 17401922 # DTB read accesses 458system.cpu0.dtb.write_accesses 14546879 # DTB write accesses |
| 459system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 459system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 460system.cpu0.dtb.hits 31880379 # DTB hits | 460system.cpu0.dtb.hits 31880381 # DTB hits |
| 461system.cpu0.dtb.misses 68420 # DTB misses | 461system.cpu0.dtb.misses 68420 # DTB misses |
| 462system.cpu0.dtb.accesses 31948799 # DTB accesses | 462system.cpu0.dtb.accesses 31948801 # DTB accesses |
| 463system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 464system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 465system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 466system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 467system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 468system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 469system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 470system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 117 unchanged lines hidden (view full) --- 588system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 589system.cpu0.op_class_0::total 95927461 # Class of committed instruction 590system.cpu0.kern.inst.arm 0 # number of arm instructions executed 591system.cpu0.kern.inst.quiesce 1852 # number of quiesce instructions executed 592system.cpu0.tickCycles 128530134 # Number of cycles that the object actually ticked 593system.cpu0.idleCycles 38694848 # Total number of cycles that the object has spent stopped 594system.cpu0.dcache.tags.replacements 715130 # number of replacements 595system.cpu0.dcache.tags.tagsinuse 500.249385 # Cycle average of tags in use | 463system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 464system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 465system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 466system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 467system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 468system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 469system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 470system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 117 unchanged lines hidden (view full) --- 588system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 589system.cpu0.op_class_0::total 95927461 # Class of committed instruction 590system.cpu0.kern.inst.arm 0 # number of arm instructions executed 591system.cpu0.kern.inst.quiesce 1852 # number of quiesce instructions executed 592system.cpu0.tickCycles 128530134 # Number of cycles that the object actually ticked 593system.cpu0.idleCycles 38694848 # Total number of cycles that the object has spent stopped 594system.cpu0.dcache.tags.replacements 715130 # number of replacements 595system.cpu0.dcache.tags.tagsinuse 500.249385 # Cycle average of tags in use |
| 596system.cpu0.dcache.tags.total_refs 30394668 # Total number of references to valid blocks. | 596system.cpu0.dcache.tags.total_refs 30394670 # Total number of references to valid blocks. |
| 597system.cpu0.dcache.tags.sampled_refs 715642 # Sample count of references to valid blocks. | 597system.cpu0.dcache.tags.sampled_refs 715642 # Sample count of references to valid blocks. |
| 598system.cpu0.dcache.tags.avg_refs 42.471890 # Average number of references to valid blocks. | 598system.cpu0.dcache.tags.avg_refs 42.471892 # Average number of references to valid blocks. |
| 599system.cpu0.dcache.tags.warmup_cycle 356009000 # Cycle when the warmup percentage was hit. 600system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.249385 # Average occupied blocks per requestor 601system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977050 # Average percentage of cache occupancy 602system.cpu0.dcache.tags.occ_percent::total 0.977050 # Average percentage of cache occupancy 603system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 604system.cpu0.dcache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id 605system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id 606system.cpu0.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id 607system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 599system.cpu0.dcache.tags.warmup_cycle 356009000 # Cycle when the warmup percentage was hit. 600system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.249385 # Average occupied blocks per requestor 601system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977050 # Average percentage of cache occupancy 602system.cpu0.dcache.tags.occ_percent::total 0.977050 # Average percentage of cache occupancy 603system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 604system.cpu0.dcache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id 605system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id 606system.cpu0.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id 607system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 608system.cpu0.dcache.tags.tag_accesses 63780149 # Number of tag accesses 609system.cpu0.dcache.tags.data_accesses 63780149 # Number of data accesses 610system.cpu0.dcache.ReadReq_hits::cpu0.data 15810331 # number of ReadReq hits 611system.cpu0.dcache.ReadReq_hits::total 15810331 # number of ReadReq hits 612system.cpu0.dcache.WriteReq_hits::cpu0.data 13424811 # number of WriteReq hits 613system.cpu0.dcache.WriteReq_hits::total 13424811 # number of WriteReq hits | 608system.cpu0.dcache.tags.tag_accesses 63780153 # Number of tag accesses 609system.cpu0.dcache.tags.data_accesses 63780153 # Number of data accesses 610system.cpu0.dcache.ReadReq_hits::cpu0.data 15810332 # number of ReadReq hits 611system.cpu0.dcache.ReadReq_hits::total 15810332 # number of ReadReq hits 612system.cpu0.dcache.WriteReq_hits::cpu0.data 13424812 # number of WriteReq hits 613system.cpu0.dcache.WriteReq_hits::total 13424812 # number of WriteReq hits |
| 614system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320440 # number of SoftPFReq hits 615system.cpu0.dcache.SoftPFReq_hits::total 320440 # number of SoftPFReq hits 616system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365226 # number of LoadLockedReq hits 617system.cpu0.dcache.LoadLockedReq_hits::total 365226 # number of LoadLockedReq hits 618system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361080 # number of StoreCondReq hits 619system.cpu0.dcache.StoreCondReq_hits::total 361080 # number of StoreCondReq hits | 614system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320440 # number of SoftPFReq hits 615system.cpu0.dcache.SoftPFReq_hits::total 320440 # number of SoftPFReq hits 616system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365226 # number of LoadLockedReq hits 617system.cpu0.dcache.LoadLockedReq_hits::total 365226 # number of LoadLockedReq hits 618system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361080 # number of StoreCondReq hits 619system.cpu0.dcache.StoreCondReq_hits::total 361080 # number of StoreCondReq hits |
| 620system.cpu0.dcache.demand_hits::cpu0.data 29235142 # number of demand (read+write) hits 621system.cpu0.dcache.demand_hits::total 29235142 # number of demand (read+write) hits 622system.cpu0.dcache.overall_hits::cpu0.data 29555582 # number of overall hits 623system.cpu0.dcache.overall_hits::total 29555582 # number of overall hits | 620system.cpu0.dcache.demand_hits::cpu0.data 29235144 # number of demand (read+write) hits 621system.cpu0.dcache.demand_hits::total 29235144 # number of demand (read+write) hits 622system.cpu0.dcache.overall_hits::cpu0.data 29555584 # number of overall hits 623system.cpu0.dcache.overall_hits::total 29555584 # number of overall hits |
| 624system.cpu0.dcache.ReadReq_misses::cpu0.data 463723 # number of ReadReq misses 625system.cpu0.dcache.ReadReq_misses::total 463723 # number of ReadReq misses 626system.cpu0.dcache.WriteReq_misses::cpu0.data 580901 # number of WriteReq misses 627system.cpu0.dcache.WriteReq_misses::total 580901 # number of WriteReq misses 628system.cpu0.dcache.SoftPFReq_misses::cpu0.data 136483 # number of SoftPFReq misses 629system.cpu0.dcache.SoftPFReq_misses::total 136483 # number of SoftPFReq misses 630system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21307 # number of LoadLockedReq misses 631system.cpu0.dcache.LoadLockedReq_misses::total 21307 # number of LoadLockedReq misses --- 12 unchanged lines hidden (view full) --- 644system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 497952500 # number of StoreCondReq miss cycles 645system.cpu0.dcache.StoreCondReq_miss_latency::total 497952500 # number of StoreCondReq miss cycles 646system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 229500 # number of StoreCondFailReq miss cycles 647system.cpu0.dcache.StoreCondFailReq_miss_latency::total 229500 # number of StoreCondFailReq miss cycles 648system.cpu0.dcache.demand_miss_latency::cpu0.data 16499002500 # number of demand (read+write) miss cycles 649system.cpu0.dcache.demand_miss_latency::total 16499002500 # number of demand (read+write) miss cycles 650system.cpu0.dcache.overall_miss_latency::cpu0.data 16499002500 # number of overall miss cycles 651system.cpu0.dcache.overall_miss_latency::total 16499002500 # number of overall miss cycles | 624system.cpu0.dcache.ReadReq_misses::cpu0.data 463723 # number of ReadReq misses 625system.cpu0.dcache.ReadReq_misses::total 463723 # number of ReadReq misses 626system.cpu0.dcache.WriteReq_misses::cpu0.data 580901 # number of WriteReq misses 627system.cpu0.dcache.WriteReq_misses::total 580901 # number of WriteReq misses 628system.cpu0.dcache.SoftPFReq_misses::cpu0.data 136483 # number of SoftPFReq misses 629system.cpu0.dcache.SoftPFReq_misses::total 136483 # number of SoftPFReq misses 630system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21307 # number of LoadLockedReq misses 631system.cpu0.dcache.LoadLockedReq_misses::total 21307 # number of LoadLockedReq misses --- 12 unchanged lines hidden (view full) --- 644system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 497952500 # number of StoreCondReq miss cycles 645system.cpu0.dcache.StoreCondReq_miss_latency::total 497952500 # number of StoreCondReq miss cycles 646system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 229500 # number of StoreCondFailReq miss cycles 647system.cpu0.dcache.StoreCondFailReq_miss_latency::total 229500 # number of StoreCondFailReq miss cycles 648system.cpu0.dcache.demand_miss_latency::cpu0.data 16499002500 # number of demand (read+write) miss cycles 649system.cpu0.dcache.demand_miss_latency::total 16499002500 # number of demand (read+write) miss cycles 650system.cpu0.dcache.overall_miss_latency::cpu0.data 16499002500 # number of overall miss cycles 651system.cpu0.dcache.overall_miss_latency::total 16499002500 # number of overall miss cycles |
| 652system.cpu0.dcache.ReadReq_accesses::cpu0.data 16274054 # number of ReadReq accesses(hits+misses) 653system.cpu0.dcache.ReadReq_accesses::total 16274054 # number of ReadReq accesses(hits+misses) 654system.cpu0.dcache.WriteReq_accesses::cpu0.data 14005712 # number of WriteReq accesses(hits+misses) 655system.cpu0.dcache.WriteReq_accesses::total 14005712 # number of WriteReq accesses(hits+misses) | 652system.cpu0.dcache.ReadReq_accesses::cpu0.data 16274055 # number of ReadReq accesses(hits+misses) 653system.cpu0.dcache.ReadReq_accesses::total 16274055 # number of ReadReq accesses(hits+misses) 654system.cpu0.dcache.WriteReq_accesses::cpu0.data 14005713 # number of WriteReq accesses(hits+misses) 655system.cpu0.dcache.WriteReq_accesses::total 14005713 # number of WriteReq accesses(hits+misses) |
| 656system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456923 # number of SoftPFReq accesses(hits+misses) 657system.cpu0.dcache.SoftPFReq_accesses::total 456923 # number of SoftPFReq accesses(hits+misses) 658system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386533 # number of LoadLockedReq accesses(hits+misses) 659system.cpu0.dcache.LoadLockedReq_accesses::total 386533 # number of LoadLockedReq accesses(hits+misses) 660system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381647 # number of StoreCondReq accesses(hits+misses) 661system.cpu0.dcache.StoreCondReq_accesses::total 381647 # number of StoreCondReq accesses(hits+misses) | 656system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456923 # number of SoftPFReq accesses(hits+misses) 657system.cpu0.dcache.SoftPFReq_accesses::total 456923 # number of SoftPFReq accesses(hits+misses) 658system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386533 # number of LoadLockedReq accesses(hits+misses) 659system.cpu0.dcache.LoadLockedReq_accesses::total 386533 # number of LoadLockedReq accesses(hits+misses) 660system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381647 # number of StoreCondReq accesses(hits+misses) 661system.cpu0.dcache.StoreCondReq_accesses::total 381647 # number of StoreCondReq accesses(hits+misses) |
| 662system.cpu0.dcache.demand_accesses::cpu0.data 30279766 # number of demand (read+write) accesses 663system.cpu0.dcache.demand_accesses::total 30279766 # number of demand (read+write) accesses 664system.cpu0.dcache.overall_accesses::cpu0.data 30736689 # number of overall (read+write) accesses 665system.cpu0.dcache.overall_accesses::total 30736689 # number of overall (read+write) accesses | 662system.cpu0.dcache.demand_accesses::cpu0.data 30279768 # number of demand (read+write) accesses 663system.cpu0.dcache.demand_accesses::total 30279768 # number of demand (read+write) accesses 664system.cpu0.dcache.overall_accesses::cpu0.data 30736691 # number of overall (read+write) accesses 665system.cpu0.dcache.overall_accesses::total 30736691 # number of overall (read+write) accesses |
| 666system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028495 # miss rate for ReadReq accesses 667system.cpu0.dcache.ReadReq_miss_rate::total 0.028495 # miss rate for ReadReq accesses 668system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041476 # miss rate for WriteReq accesses 669system.cpu0.dcache.WriteReq_miss_rate::total 0.041476 # miss rate for WriteReq accesses 670system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.298700 # miss rate for SoftPFReq accesses 671system.cpu0.dcache.SoftPFReq_miss_rate::total 0.298700 # miss rate for SoftPFReq accesses 672system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055123 # miss rate for LoadLockedReq accesses 673system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055123 # miss rate for LoadLockedReq accesses --- 2359 unchanged lines hidden --- | 666system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028495 # miss rate for ReadReq accesses 667system.cpu0.dcache.ReadReq_miss_rate::total 0.028495 # miss rate for ReadReq accesses 668system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041476 # miss rate for WriteReq accesses 669system.cpu0.dcache.WriteReq_miss_rate::total 0.041476 # miss rate for WriteReq accesses 670system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.298700 # miss rate for SoftPFReq accesses 671system.cpu0.dcache.SoftPFReq_miss_rate::total 0.298700 # miss rate for SoftPFReq accesses 672system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055123 # miss rate for LoadLockedReq accesses 673system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055123 # miss rate for LoadLockedReq accesses --- 2359 unchanged lines hidden --- |