| stats.txt (10848:e61f847e74fd) | stats.txt (10852:5b58b4cccfd7) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.846107 # Number of seconds simulated 4sim_ticks 2846106511000 # Number of ticks simulated 5final_tick 2846106511000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.846034 # Number of seconds simulated 4sim_ticks 2846033690500 # Number of ticks simulated 5final_tick 2846033690500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 154405 # Simulator instruction rate (inst/s) 8host_op_rate 186958 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3504377822 # Simulator tick rate (ticks/s) 10host_mem_usage 600496 # Number of bytes of host memory used 11host_seconds 812.16 # Real time elapsed on the host 12sim_insts 125401163 # Number of instructions simulated 13sim_ops 151839522 # Number of ops (including micro ops) simulated | 7host_inst_rate 166502 # Simulator instruction rate (inst/s) 8host_op_rate 201645 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3701777010 # Simulator tick rate (ticks/s) 10host_mem_usage 652712 # Number of bytes of host memory used 11host_seconds 768.83 # Real time elapsed on the host 12sim_insts 128011279 # Number of instructions simulated 13sim_ops 155030352 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu0.dtb.walker 8832 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu0.dtb.walker 8384 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu0.inst 1669760 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1336112 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8514432 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 1408 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 219648 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 604112 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 400768 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu0.inst 1665600 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1328952 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8468032 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 219456 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 635604 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 399104 # Number of bytes read from this memory |
| 25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 26system.physmem.bytes_read::total 12756096 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 1669760 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 219648 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 1889408 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 8854144 # Number of bytes written to this memory | 26system.physmem.bytes_read::total 12726924 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 1665600 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 219456 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 1885056 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 8843968 # Number of bytes written to this memory |
| 31system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory | 31system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory |
| 33system.physmem.bytes_written::total 8871708 # Number of bytes written to this memory 34system.physmem.num_reads::cpu0.dtb.walker 138 # Number of read requests responded to by this memory | 33system.physmem.bytes_written::total 8861532 # Number of bytes written to this memory 34system.physmem.num_reads::cpu0.dtb.walker 131 # Number of read requests responded to by this memory |
| 35system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory | 35system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory |
| 36system.physmem.num_reads::cpu0.inst 26090 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 21399 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.l2cache.prefetcher 133038 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.dtb.walker 22 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.inst 3432 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.data 9459 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.l2cache.prefetcher 6262 # Number of read requests responded to by this memory | 36system.physmem.num_reads::cpu0.inst 26025 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 21289 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.l2cache.prefetcher 132313 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.inst 3429 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.data 9952 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.l2cache.prefetcher 6236 # Number of read requests responded to by this memory |
| 43system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 43system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 44system.physmem.num_reads::total 199856 # Number of read requests responded to by this memory 45system.physmem.num_writes::writebacks 138346 # Number of write requests responded to by this memory | 44system.physmem.num_reads::total 199403 # Number of read requests responded to by this memory 45system.physmem.num_writes::writebacks 138187 # Number of write requests responded to by this memory |
| 46system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 47system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory | 46system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 47system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory |
| 48system.physmem.num_writes::total 142737 # Number of write requests responded to by this memory 49system.physmem.bw_read::cpu0.dtb.walker 3103 # Total read bandwidth from this memory (bytes/s) | 48system.physmem.num_writes::total 142578 # Number of write requests responded to by this memory 49system.physmem.bw_read::cpu0.dtb.walker 2946 # Total read bandwidth from this memory (bytes/s) |
| 50system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) | 50system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) |
| 51system.physmem.bw_read::cpu0.inst 586682 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.data 469453 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.l2cache.prefetcher 2991607 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.dtb.walker 495 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.inst 77175 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.data 212259 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.l2cache.prefetcher 140813 # Total read bandwidth from this memory (bytes/s) | 51system.physmem.bw_read::cpu0.inst 585236 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.data 466949 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.l2cache.prefetcher 2975380 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.dtb.walker 270 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.inst 77109 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.data 223330 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.l2cache.prefetcher 140232 # Total read bandwidth from this memory (bytes/s) |
| 58system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) | 58system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) |
| 59system.physmem.bw_read::total 4481946 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::cpu0.inst 586682 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu1.inst 77175 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::total 663857 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_write::writebacks 3110967 # Write bandwidth from this memory (bytes/s) | 59system.physmem.bw_read::total 4471811 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::cpu0.inst 585236 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu1.inst 77109 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::total 662345 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_write::writebacks 3107471 # Write bandwidth from this memory (bytes/s) |
| 64system.physmem.bw_write::cpu0.data 6157 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) | 64system.physmem.bw_write::cpu0.data 6157 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) |
| 66system.physmem.bw_write::total 3117138 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_total::writebacks 3110967 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.dtb.walker 3103 # Total bandwidth to/from this memory (bytes/s) | 66system.physmem.bw_write::total 3113643 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_total::writebacks 3107471 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.dtb.walker 2946 # Total bandwidth to/from this memory (bytes/s) |
| 69system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) | 69system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) |
| 70system.physmem.bw_total::cpu0.inst 586682 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.data 475610 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.l2cache.prefetcher 2991607 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.dtb.walker 495 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.inst 77175 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.data 212273 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.l2cache.prefetcher 140813 # Total bandwidth to/from this memory (bytes/s) | 70system.physmem.bw_total::cpu0.inst 585236 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.data 473106 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.l2cache.prefetcher 2975380 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.dtb.walker 270 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.inst 77109 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.data 223344 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.l2cache.prefetcher 140232 # Total bandwidth to/from this memory (bytes/s) |
| 77system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) | 77system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) |
| 78system.physmem.bw_total::total 7599085 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.readReqs 199856 # Number of read requests accepted 80system.physmem.writeReqs 178961 # Number of write requests accepted 81system.physmem.readBursts 199856 # Number of DRAM read bursts, including those serviced by the write queue 82system.physmem.writeBursts 178961 # Number of DRAM write bursts, including those merged in the write queue 83system.physmem.bytesReadDRAM 12785664 # Total number of bytes read from DRAM 84system.physmem.bytesReadWrQ 5120 # Total number of bytes read from write queue 85system.physmem.bytesWritten 9927488 # Total number of bytes written to DRAM 86system.physmem.bytesReadSys 12756096 # Total read bytes from the system interface side 87system.physmem.bytesWrittenSys 11190044 # Total written bytes from the system interface side 88system.physmem.servicedByWrQ 80 # Number of DRAM read bursts serviced by the write queue 89system.physmem.mergedWrBursts 23813 # Number of DRAM write bursts merged with an existing one 90system.physmem.neitherReadNorWriteReqs 14250 # Number of requests that are neither read nor write 91system.physmem.perBankRdBursts::0 12367 # Per bank write bursts 92system.physmem.perBankRdBursts::1 12533 # Per bank write bursts 93system.physmem.perBankRdBursts::2 12905 # Per bank write bursts 94system.physmem.perBankRdBursts::3 12918 # Per bank write bursts 95system.physmem.perBankRdBursts::4 15006 # Per bank write bursts 96system.physmem.perBankRdBursts::5 12397 # Per bank write bursts 97system.physmem.perBankRdBursts::6 13141 # Per bank write bursts 98system.physmem.perBankRdBursts::7 13266 # Per bank write bursts 99system.physmem.perBankRdBursts::8 12256 # Per bank write bursts 100system.physmem.perBankRdBursts::9 12318 # Per bank write bursts 101system.physmem.perBankRdBursts::10 12174 # Per bank write bursts 102system.physmem.perBankRdBursts::11 11385 # Per bank write bursts 103system.physmem.perBankRdBursts::12 11522 # Per bank write bursts 104system.physmem.perBankRdBursts::13 12342 # Per bank write bursts 105system.physmem.perBankRdBursts::14 11687 # Per bank write bursts 106system.physmem.perBankRdBursts::15 11559 # Per bank write bursts 107system.physmem.perBankWrBursts::0 9829 # Per bank write bursts 108system.physmem.perBankWrBursts::1 10209 # Per bank write bursts 109system.physmem.perBankWrBursts::2 10296 # Per bank write bursts 110system.physmem.perBankWrBursts::3 10100 # Per bank write bursts 111system.physmem.perBankWrBursts::4 9093 # Per bank write bursts 112system.physmem.perBankWrBursts::5 9584 # Per bank write bursts 113system.physmem.perBankWrBursts::6 10130 # Per bank write bursts 114system.physmem.perBankWrBursts::7 10398 # Per bank write bursts 115system.physmem.perBankWrBursts::8 9607 # Per bank write bursts 116system.physmem.perBankWrBursts::9 9596 # Per bank write bursts 117system.physmem.perBankWrBursts::10 9832 # Per bank write bursts 118system.physmem.perBankWrBursts::11 9707 # Per bank write bursts 119system.physmem.perBankWrBursts::12 9196 # Per bank write bursts 120system.physmem.perBankWrBursts::13 9428 # Per bank write bursts 121system.physmem.perBankWrBursts::14 9291 # Per bank write bursts 122system.physmem.perBankWrBursts::15 8821 # Per bank write bursts | 78system.physmem.bw_total::total 7585453 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.readReqs 199403 # Number of read requests accepted 80system.physmem.writeReqs 178802 # Number of write requests accepted 81system.physmem.readBursts 199403 # Number of DRAM read bursts, including those serviced by the write queue 82system.physmem.writeBursts 178802 # Number of DRAM write bursts, including those merged in the write queue 83system.physmem.bytesReadDRAM 12754816 # Total number of bytes read from DRAM 84system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue 85system.physmem.bytesWritten 9923392 # Total number of bytes written to DRAM 86system.physmem.bytesReadSys 12726924 # Total read bytes from the system interface side 87system.physmem.bytesWrittenSys 11179868 # Total written bytes from the system interface side 88system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue 89system.physmem.mergedWrBursts 23728 # Number of DRAM write bursts merged with an existing one 90system.physmem.neitherReadNorWriteReqs 14293 # Number of requests that are neither read nor write 91system.physmem.perBankRdBursts::0 12446 # Per bank write bursts 92system.physmem.perBankRdBursts::1 12462 # Per bank write bursts 93system.physmem.perBankRdBursts::2 12648 # Per bank write bursts 94system.physmem.perBankRdBursts::3 12635 # Per bank write bursts 95system.physmem.perBankRdBursts::4 15144 # Per bank write bursts 96system.physmem.perBankRdBursts::5 12384 # Per bank write bursts 97system.physmem.perBankRdBursts::6 13114 # Per bank write bursts 98system.physmem.perBankRdBursts::7 13234 # Per bank write bursts 99system.physmem.perBankRdBursts::8 12297 # Per bank write bursts 100system.physmem.perBankRdBursts::9 12473 # Per bank write bursts 101system.physmem.perBankRdBursts::10 12152 # Per bank write bursts 102system.physmem.perBankRdBursts::11 11219 # Per bank write bursts 103system.physmem.perBankRdBursts::12 11569 # Per bank write bursts 104system.physmem.perBankRdBursts::13 12199 # Per bank write bursts 105system.physmem.perBankRdBursts::14 11629 # Per bank write bursts 106system.physmem.perBankRdBursts::15 11689 # Per bank write bursts 107system.physmem.perBankWrBursts::0 9980 # Per bank write bursts 108system.physmem.perBankWrBursts::1 10101 # Per bank write bursts 109system.physmem.perBankWrBursts::2 10187 # Per bank write bursts 110system.physmem.perBankWrBursts::3 9953 # Per bank write bursts 111system.physmem.perBankWrBursts::4 9212 # Per bank write bursts 112system.physmem.perBankWrBursts::5 9585 # Per bank write bursts 113system.physmem.perBankWrBursts::6 10195 # Per bank write bursts 114system.physmem.perBankWrBursts::7 10328 # Per bank write bursts 115system.physmem.perBankWrBursts::8 9559 # Per bank write bursts 116system.physmem.perBankWrBursts::9 9737 # Per bank write bursts 117system.physmem.perBankWrBursts::10 9778 # Per bank write bursts 118system.physmem.perBankWrBursts::11 9524 # Per bank write bursts 119system.physmem.perBankWrBursts::12 9387 # Per bank write bursts 120system.physmem.perBankWrBursts::13 9312 # Per bank write bursts 121system.physmem.perBankWrBursts::14 9249 # Per bank write bursts 122system.physmem.perBankWrBursts::15 8966 # Per bank write bursts |
| 123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 124system.physmem.numWrRetry 44 # Number of times write queue was full causing retry | 123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 124system.physmem.numWrRetry 44 # Number of times write queue was full causing retry |
| 125system.physmem.totGap 2846106004500 # Total gap between requests | 125system.physmem.totGap 2846033184500 # Total gap between requests |
| 126system.physmem.readPktSize::0 0 # Read request sizes (log2) 127system.physmem.readPktSize::1 0 # Read request sizes (log2) | 126system.physmem.readPktSize::0 0 # Read request sizes (log2) 127system.physmem.readPktSize::1 0 # Read request sizes (log2) |
| 128system.physmem.readPktSize::2 552 # Read request sizes (log2) | 128system.physmem.readPktSize::2 555 # Read request sizes (log2) |
| 129system.physmem.readPktSize::3 28 # Read request sizes (log2) 130system.physmem.readPktSize::4 0 # Read request sizes (log2) 131system.physmem.readPktSize::5 0 # Read request sizes (log2) | 129system.physmem.readPktSize::3 28 # Read request sizes (log2) 130system.physmem.readPktSize::4 0 # Read request sizes (log2) 131system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 132system.physmem.readPktSize::6 199276 # Read request sizes (log2) | 132system.physmem.readPktSize::6 198820 # Read request sizes (log2) |
| 133system.physmem.writePktSize::0 0 # Write request sizes (log2) 134system.physmem.writePktSize::1 0 # Write request sizes (log2) 135system.physmem.writePktSize::2 4391 # Write request sizes (log2) 136system.physmem.writePktSize::3 0 # Write request sizes (log2) 137system.physmem.writePktSize::4 0 # Write request sizes (log2) 138system.physmem.writePktSize::5 0 # Write request sizes (log2) | 133system.physmem.writePktSize::0 0 # Write request sizes (log2) 134system.physmem.writePktSize::1 0 # Write request sizes (log2) 135system.physmem.writePktSize::2 4391 # Write request sizes (log2) 136system.physmem.writePktSize::3 0 # Write request sizes (log2) 137system.physmem.writePktSize::4 0 # Write request sizes (log2) 138system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 139system.physmem.writePktSize::6 174570 # Write request sizes (log2) 140system.physmem.rdQLenPdf::0 98276 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 48017 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 13343 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 9981 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 7920 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 6441 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 5383 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 4706 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 4161 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 742 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 273 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 252 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::12 151 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::13 128 # What read queue length does an incoming req see | 139system.physmem.writePktSize::6 174411 # Write request sizes (log2) 140system.physmem.rdQLenPdf::0 98514 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 48367 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 13227 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 9811 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 7788 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 6331 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 5269 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 4641 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 3767 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 751 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 267 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 262 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::12 163 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::13 134 # What read queue length does an incoming req see |
| 154system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see --- 17 unchanged lines hidden (view full) --- 179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 154system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see --- 17 unchanged lines hidden (view full) --- 179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 187system.physmem.wrQLenPdf::15 2212 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::16 2498 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::17 3704 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::18 4717 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::19 5610 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::20 6075 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::21 6457 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::22 6849 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::23 8256 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::24 7351 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::25 7669 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::26 9425 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::27 8094 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::28 8319 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::29 11216 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::30 9077 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::31 8599 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::32 8116 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::33 1353 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::34 1120 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::35 1362 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::36 2301 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::37 2267 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::38 1793 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::39 2060 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::40 2701 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::41 1815 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::42 1987 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::43 1779 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::44 1788 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::45 1635 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::46 1307 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::47 1409 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::48 1018 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::49 787 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::50 414 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::51 356 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::52 234 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::53 247 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::54 153 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::55 197 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::56 158 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::57 141 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::58 92 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::59 119 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::60 108 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::62 51 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::63 49 # What write queue length does an incoming req see 236system.physmem.bytesPerActivate::samples 90865 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::mean 249.965201 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::gmean 140.421700 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::stdev 309.995255 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::0-127 47261 52.01% 52.01% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::128-255 18080 19.90% 71.91% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::256-383 6274 6.90% 78.81% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::384-511 3625 3.99% 82.80% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::512-639 2837 3.12% 85.93% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::640-767 1606 1.77% 87.69% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::768-895 998 1.10% 88.79% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::896-1023 1046 1.15% 89.94% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::1024-1151 9138 10.06% 100.00% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::total 90865 # Bytes accessed per row activation 250system.physmem.rdPerTurnAround::samples 6548 # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::mean 30.509316 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::stdev 555.919891 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::0-2047 6546 99.97% 99.97% # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes | 187system.physmem.wrQLenPdf::15 2198 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::16 2454 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::17 3752 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::18 4705 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::19 5374 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::20 6189 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::21 6525 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::22 7029 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::23 8695 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::24 7429 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::25 7723 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::26 9022 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::27 8469 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::28 8126 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::29 10884 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::30 9022 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::31 8455 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::32 7898 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::33 1553 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::34 1175 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::35 1516 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::36 2621 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::37 2049 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::38 1870 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::39 1722 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::40 2069 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::41 1894 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::42 1948 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::43 1965 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::44 1921 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::45 1529 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::46 1415 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::47 1463 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::48 1090 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::49 724 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::50 406 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::51 387 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::52 227 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::53 226 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::54 197 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::55 201 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::56 183 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::57 139 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::58 139 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::59 144 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::60 121 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::61 96 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::62 58 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::63 62 # What write queue length does an incoming req see 236system.physmem.bytesPerActivate::samples 91619 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::mean 247.526648 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::gmean 138.939609 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::stdev 308.892335 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::0-127 48258 52.67% 52.67% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::128-255 17913 19.55% 72.22% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::256-383 6311 6.89% 79.11% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::384-511 3675 4.01% 83.12% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::512-639 2817 3.07% 86.20% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::640-767 1472 1.61% 87.80% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::768-895 1018 1.11% 88.92% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::896-1023 1004 1.10% 90.01% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::1024-1151 9151 9.99% 100.00% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::total 91619 # Bytes accessed per row activation 250system.physmem.rdPerTurnAround::samples 6524 # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::mean 30.547670 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::stdev 556.789065 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::0-2047 6523 99.98% 99.98% # Reads before turning the bus around for writes |
| 255system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes | 254system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 256system.physmem.rdPerTurnAround::total 6548 # Reads before turning the bus around for writes 257system.physmem.wrPerTurnAround::samples 6548 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::mean 23.689218 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::gmean 18.640113 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::stdev 40.676171 # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::16-31 6193 94.58% 94.58% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::32-47 92 1.41% 95.98% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::48-63 24 0.37% 96.35% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::64-79 16 0.24% 96.59% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::80-95 27 0.41% 97.01% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::96-111 36 0.55% 97.56% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::112-127 25 0.38% 97.94% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::128-143 12 0.18% 98.12% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::144-159 17 0.26% 98.38% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::160-175 3 0.05% 98.43% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::176-191 21 0.32% 98.75% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::192-207 18 0.27% 99.02% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::208-223 11 0.17% 99.19% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::224-239 3 0.05% 99.24% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::240-255 2 0.03% 99.27% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::256-271 3 0.05% 99.31% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::272-287 5 0.08% 99.39% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::288-303 1 0.02% 99.40% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::304-319 4 0.06% 99.47% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::320-335 1 0.02% 99.48% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::336-351 8 0.12% 99.60% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::352-367 9 0.14% 99.74% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::368-383 3 0.05% 99.79% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::400-415 2 0.03% 99.82% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::480-495 1 0.02% 99.83% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::512-527 3 0.05% 99.88% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::528-543 3 0.05% 99.92% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::608-623 1 0.02% 99.94% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::688-703 3 0.05% 99.98% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::912-927 1 0.02% 100.00% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::total 6548 # Writes before turning the bus around for reads 292system.physmem.totQLat 5702655246 # Total ticks spent queuing 293system.physmem.totMemAccLat 9448455246 # Total ticks spent from burst creation until serviced by the DRAM 294system.physmem.totBusLat 998880000 # Total ticks spent in databus transfers 295system.physmem.avgQLat 28545.25 # Average queueing delay per DRAM burst | 255system.physmem.rdPerTurnAround::total 6524 # Reads before turning the bus around for writes 256system.physmem.wrPerTurnAround::samples 6524 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::mean 23.766554 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::gmean 18.625948 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::stdev 41.024429 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::16-31 6179 94.71% 94.71% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::32-47 85 1.30% 96.01% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::48-63 25 0.38% 96.40% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::64-79 12 0.18% 96.58% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::80-95 31 0.48% 97.06% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::96-111 34 0.52% 97.58% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::112-127 24 0.37% 97.95% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::128-143 11 0.17% 98.11% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::144-159 15 0.23% 98.34% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::160-175 5 0.08% 98.42% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::176-191 12 0.18% 98.61% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::192-207 17 0.26% 98.87% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::208-223 13 0.20% 99.06% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::224-239 5 0.08% 99.14% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::240-255 4 0.06% 99.20% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::256-271 3 0.05% 99.25% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::272-287 4 0.06% 99.31% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::288-303 2 0.03% 99.34% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::304-319 4 0.06% 99.40% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::320-335 3 0.05% 99.45% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::336-351 3 0.05% 99.49% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::352-367 16 0.25% 99.74% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::368-383 1 0.02% 99.75% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::384-399 3 0.05% 99.80% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::480-495 2 0.03% 99.83% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::496-511 2 0.03% 99.86% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::512-527 4 0.06% 99.92% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::544-559 1 0.02% 99.94% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::560-575 1 0.02% 99.95% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::640-655 1 0.02% 99.97% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::880-895 1 0.02% 100.00% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::total 6524 # Writes before turning the bus around for reads 293system.physmem.totQLat 5653495532 # Total ticks spent queuing 294system.physmem.totMemAccLat 9390258032 # Total ticks spent from burst creation until serviced by the DRAM 295system.physmem.totBusLat 996470000 # Total ticks spent in databus transfers 296system.physmem.avgQLat 28367.62 # Average queueing delay per DRAM burst |
| 296system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 297system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 297system.physmem.avgMemAccLat 47295.25 # Average memory access latency per DRAM burst 298system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s | 298system.physmem.avgMemAccLat 47117.62 # Average memory access latency per DRAM burst 299system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s |
| 299system.physmem.avgWrBW 3.49 # Average achieved write bandwidth in MiByte/s | 300system.physmem.avgWrBW 3.49 # Average achieved write bandwidth in MiByte/s |
| 300system.physmem.avgRdBWSys 4.48 # Average system read bandwidth in MiByte/s | 301system.physmem.avgRdBWSys 4.47 # Average system read bandwidth in MiByte/s |
| 301system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s 302system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 303system.physmem.busUtil 0.06 # Data bus utilization in percentage 304system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 305system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 302system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s 303system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 304system.physmem.busUtil 0.06 # Data bus utilization in percentage 305system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 306system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| 306system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing 307system.physmem.avgWrQLen 26.22 # Average write queue length when enqueuing 308system.physmem.readRowHits 166460 # Number of row buffer hits during reads 309system.physmem.writeRowHits 97567 # Number of row buffer hits during writes 310system.physmem.readRowHitRate 83.32 # Row buffer hit rate for reads 311system.physmem.writeRowHitRate 62.89 # Row buffer hit rate for writes 312system.physmem.avgGap 7513142.24 # Average gap between requests 313system.physmem.pageHitRate 74.39 # Row buffer hit rate, read and write combined 314system.physmem_0.actEnergy 359425080 # Energy for activate commands per rank (pJ) 315system.physmem_0.preEnergy 196114875 # Energy for precharge commands per rank (pJ) 316system.physmem_0.readEnergy 815357400 # Energy for read commands per rank (pJ) 317system.physmem_0.writeEnergy 516060720 # Energy for write commands per rank (pJ) 318system.physmem_0.refreshEnergy 185893428240 # Energy for refresh commands per rank (pJ) 319system.physmem_0.actBackEnergy 83232319410 # Energy for active background per rank (pJ) 320system.physmem_0.preBackEnergy 1634649447000 # Energy for precharge background per rank (pJ) 321system.physmem_0.totalEnergy 1905662152725 # Total energy per rank (pJ) 322system.physmem_0.averagePower 669.569541 # Core power per rank (mW) 323system.physmem_0.memoryStateTime::IDLE 2719260667390 # Time in different power states 324system.physmem_0.memoryStateTime::REF 95037540000 # Time in different power states | 307system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing 308system.physmem.avgWrQLen 22.06 # Average write queue length when enqueuing 309system.physmem.readRowHits 165654 # Number of row buffer hits during reads 310system.physmem.writeRowHits 97073 # Number of row buffer hits during writes 311system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads 312system.physmem.writeRowHitRate 62.60 # Row buffer hit rate for writes 313system.physmem.avgGap 7525107.24 # Average gap between requests 314system.physmem.pageHitRate 74.14 # Row buffer hit rate, read and write combined 315system.physmem_0.actEnergy 361662840 # Energy for activate commands per rank (pJ) 316system.physmem_0.preEnergy 197335875 # Energy for precharge commands per rank (pJ) 317system.physmem_0.readEnergy 811722600 # Energy for read commands per rank (pJ) 318system.physmem_0.writeEnergy 515425680 # Energy for write commands per rank (pJ) 319system.physmem_0.refreshEnergy 185888851200 # Energy for refresh commands per rank (pJ) 320system.physmem_0.actBackEnergy 83071861560 # Energy for active background per rank (pJ) 321system.physmem_0.preBackEnergy 1634748153750 # Energy for precharge background per rank (pJ) 322system.physmem_0.totalEnergy 1905595013505 # Total energy per rank (pJ) 323system.physmem_0.averagePower 669.562437 # Core power per rank (mW) 324system.physmem_0.memoryStateTime::IDLE 2719423686494 # Time in different power states 325system.physmem_0.memoryStateTime::REF 95035200000 # Time in different power states |
| 325system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 326system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 326system.physmem_0.memoryStateTime::ACT 31802228860 # Time in different power states | 327system.physmem_0.memoryStateTime::ACT 31571473506 # Time in different power states |
| 327system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 328system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 328system.physmem_1.actEnergy 327514320 # Energy for activate commands per rank (pJ) 329system.physmem_1.preEnergy 178703250 # Energy for precharge commands per rank (pJ) 330system.physmem_1.readEnergy 742887600 # Energy for read commands per rank (pJ) 331system.physmem_1.writeEnergy 489097440 # Energy for write commands per rank (pJ) 332system.physmem_1.refreshEnergy 185893428240 # Energy for refresh commands per rank (pJ) 333system.physmem_1.actBackEnergy 82208245725 # Energy for active background per rank (pJ) 334system.physmem_1.preBackEnergy 1635547757250 # Energy for precharge background per rank (pJ) 335system.physmem_1.totalEnergy 1905387633825 # Total energy per rank (pJ) 336system.physmem_1.averagePower 669.473086 # Core power per rank (mW) 337system.physmem_1.memoryStateTime::IDLE 2720763679724 # Time in different power states 338system.physmem_1.memoryStateTime::REF 95037540000 # Time in different power states | 329system.physmem_1.actEnergy 330976800 # Energy for activate commands per rank (pJ) 330system.physmem_1.preEnergy 180592500 # Energy for precharge commands per rank (pJ) 331system.physmem_1.readEnergy 742762800 # Energy for read commands per rank (pJ) 332system.physmem_1.writeEnergy 489317760 # Energy for write commands per rank (pJ) 333system.physmem_1.refreshEnergy 185888851200 # Energy for refresh commands per rank (pJ) 334system.physmem_1.actBackEnergy 82401250860 # Energy for active background per rank (pJ) 335system.physmem_1.preBackEnergy 1635336408750 # Energy for precharge background per rank (pJ) 336system.physmem_1.totalEnergy 1905370160670 # Total energy per rank (pJ) 337system.physmem_1.averagePower 669.483431 # Core power per rank (mW) 338system.physmem_1.memoryStateTime::IDLE 2720410023695 # Time in different power states 339system.physmem_1.memoryStateTime::REF 95035200000 # Time in different power states |
| 339system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 340system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 340system.physmem_1.memoryStateTime::ACT 30305178276 # Time in different power states | 341system.physmem_1.memoryStateTime::ACT 30588353805 # Time in different power states |
| 341system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 342system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory 343system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory 344system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory 345system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory 346system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory 347system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory 348system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory --- 9 unchanged lines hidden (view full) --- 358system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) 359system.realview.nvmem.bw_total::total 427 # Total bandwidth to/from this memory (bytes/s) 360system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 361system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 362system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 363system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 364system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 365system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 342system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 343system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory 344system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory 345system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory 346system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory 347system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory 348system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory 349system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory --- 9 unchanged lines hidden (view full) --- 359system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) 360system.realview.nvmem.bw_total::total 427 # Total bandwidth to/from this memory (bytes/s) 361system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 362system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 363system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 364system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 365system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 366system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 366system.cpu0.branchPred.lookups 20636360 # Number of BP lookups 367system.cpu0.branchPred.condPredicted 13610949 # Number of conditional branches predicted 368system.cpu0.branchPred.condIncorrect 1051916 # Number of conditional branches incorrect 369system.cpu0.branchPred.BTBLookups 13187821 # Number of BTB lookups 370system.cpu0.branchPred.BTBHits 9315921 # Number of BTB hits | 367system.cpu0.branchPred.lookups 20699653 # Number of BP lookups 368system.cpu0.branchPred.condPredicted 13612367 # Number of conditional branches predicted 369system.cpu0.branchPred.condIncorrect 1051860 # Number of conditional branches incorrect 370system.cpu0.branchPred.BTBLookups 13249801 # Number of BTB lookups 371system.cpu0.branchPred.BTBHits 9339959 # Number of BTB hits |
| 371system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 372system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 372system.cpu0.branchPred.BTBHitPct 70.640336 # BTB Hit Percentage 373system.cpu0.branchPred.usedRAS 3367590 # Number of times the RAS was used to get a target. 374system.cpu0.branchPred.RASInCorrect 213586 # Number of incorrect RAS predictions. | 373system.cpu0.branchPred.BTBHitPct 70.491315 # BTB Hit Percentage 374system.cpu0.branchPred.usedRAS 3411685 # Number of times the RAS was used to get a target. 375system.cpu0.branchPred.RASInCorrect 215338 # Number of incorrect RAS predictions. |
| 375system.cpu_clk_domain.clock 500 # Clock period in ticks 376system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 377system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 378system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 379system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 380system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 381system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 382system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 397system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 398system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 399system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 400system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 401system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 402system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 403system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 404system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 376system.cpu_clk_domain.clock 500 # Clock period in ticks 377system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 378system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 379system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 380system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 381system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 382system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 383system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 398system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 399system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 400system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 401system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 402system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 403system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 404system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 405system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 405system.cpu0.dtb.walker.walks 69356 # Table walker walks requested 406system.cpu0.dtb.walker.walksShort 69356 # Table walker walks initiated with short descriptors 407system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46232 # Level at which table walker walks with short descriptors terminate 408system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23124 # Level at which table walker walks with short descriptors terminate 409system.cpu0.dtb.walker.walkWaitTime::samples 69356 # Table walker wait (enqueue to first request) latency 410system.cpu0.dtb.walker.walkWaitTime::0 69356 100.00% 100.00% # Table walker wait (enqueue to first request) latency 411system.cpu0.dtb.walker.walkWaitTime::total 69356 # Table walker wait (enqueue to first request) latency 412system.cpu0.dtb.walker.walkCompletionTime::samples 6817 # Table walker service (enqueue to completion) latency 413system.cpu0.dtb.walker.walkCompletionTime::mean 9525.708083 # Table walker service (enqueue to completion) latency 414system.cpu0.dtb.walker.walkCompletionTime::gmean 8414.892081 # Table walker service (enqueue to completion) latency 415system.cpu0.dtb.walker.walkCompletionTime::stdev 6090.769517 # Table walker service (enqueue to completion) latency 416system.cpu0.dtb.walker.walkCompletionTime::0-16383 6639 97.39% 97.39% # Table walker service (enqueue to completion) latency 417system.cpu0.dtb.walker.walkCompletionTime::16384-32767 162 2.38% 99.77% # Table walker service (enqueue to completion) latency 418system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.85% # Table walker service (enqueue to completion) latency 419system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.07% 99.93% # Table walker service (enqueue to completion) latency 420system.cpu0.dtb.walker.walkCompletionTime::98304-114687 4 0.06% 99.99% # Table walker service (enqueue to completion) latency 421system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 422system.cpu0.dtb.walker.walkCompletionTime::total 6817 # Table walker service (enqueue to completion) latency | 406system.cpu0.dtb.walker.walks 70748 # Table walker walks requested 407system.cpu0.dtb.walker.walksShort 70748 # Table walker walks initiated with short descriptors 408system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 47364 # Level at which table walker walks with short descriptors terminate 409system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23384 # Level at which table walker walks with short descriptors terminate 410system.cpu0.dtb.walker.walkWaitTime::samples 70748 # Table walker wait (enqueue to first request) latency 411system.cpu0.dtb.walker.walkWaitTime::0 70748 100.00% 100.00% # Table walker wait (enqueue to first request) latency 412system.cpu0.dtb.walker.walkWaitTime::total 70748 # Table walker wait (enqueue to first request) latency 413system.cpu0.dtb.walker.walkCompletionTime::samples 6854 # Table walker service (enqueue to completion) latency 414system.cpu0.dtb.walker.walkCompletionTime::mean 9215.640648 # Table walker service (enqueue to completion) latency 415system.cpu0.dtb.walker.walkCompletionTime::gmean 8072.361115 # Table walker service (enqueue to completion) latency 416system.cpu0.dtb.walker.walkCompletionTime::stdev 6078.265155 # Table walker service (enqueue to completion) latency 417system.cpu0.dtb.walker.walkCompletionTime::0-16383 6652 97.05% 97.05% # Table walker service (enqueue to completion) latency 418system.cpu0.dtb.walker.walkCompletionTime::16384-32767 190 2.77% 99.82% # Table walker service (enqueue to completion) latency 419system.cpu0.dtb.walker.walkCompletionTime::32768-49151 4 0.06% 99.88% # Table walker service (enqueue to completion) latency 420system.cpu0.dtb.walker.walkCompletionTime::81920-98303 6 0.09% 99.97% # Table walker service (enqueue to completion) latency 421system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 422system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 423system.cpu0.dtb.walker.walkCompletionTime::total 6854 # Table walker service (enqueue to completion) latency |
| 423system.cpu0.dtb.walker.walksPending::samples 328505000 # Table walker pending requests distribution 424system.cpu0.dtb.walker.walksPending::0 328505000 100.00% 100.00% # Table walker pending requests distribution 425system.cpu0.dtb.walker.walksPending::total 328505000 # Table walker pending requests distribution | 424system.cpu0.dtb.walker.walksPending::samples 328505000 # Table walker pending requests distribution 425system.cpu0.dtb.walker.walksPending::0 328505000 100.00% 100.00% # Table walker pending requests distribution 426system.cpu0.dtb.walker.walksPending::total 328505000 # Table walker pending requests distribution |
| 426system.cpu0.dtb.walker.walkPageSizes::4K 5248 76.98% 76.98% # Table walker page sizes translated 427system.cpu0.dtb.walker.walkPageSizes::1M 1569 23.02% 100.00% # Table walker page sizes translated 428system.cpu0.dtb.walker.walkPageSizes::total 6817 # Table walker page sizes translated 429system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 69356 # Table walker requests started/completed, data/inst | 427system.cpu0.dtb.walker.walkPageSizes::4K 5278 77.01% 77.01% # Table walker page sizes translated 428system.cpu0.dtb.walker.walkPageSizes::1M 1576 22.99% 100.00% # Table walker page sizes translated 429system.cpu0.dtb.walker.walkPageSizes::total 6854 # Table walker page sizes translated 430system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 70748 # Table walker requests started/completed, data/inst |
| 430system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 431system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 431system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 69356 # Table walker requests started/completed, data/inst 432system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6817 # Table walker requests started/completed, data/inst | 432system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 70748 # Table walker requests started/completed, data/inst 433system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6854 # Table walker requests started/completed, data/inst |
| 433system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 434system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 434system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6817 # Table walker requests started/completed, data/inst 435system.cpu0.dtb.walker.walkRequestOrigin::total 76173 # Table walker requests started/completed, data/inst | 435system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6854 # Table walker requests started/completed, data/inst 436system.cpu0.dtb.walker.walkRequestOrigin::total 77602 # Table walker requests started/completed, data/inst |
| 436system.cpu0.dtb.inst_hits 0 # ITB inst hits 437system.cpu0.dtb.inst_misses 0 # ITB inst misses | 437system.cpu0.dtb.inst_hits 0 # ITB inst hits 438system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 438system.cpu0.dtb.read_hits 17307432 # DTB read hits 439system.cpu0.dtb.read_misses 63365 # DTB read misses 440system.cpu0.dtb.write_hits 14534577 # DTB write hits 441system.cpu0.dtb.write_misses 5991 # DTB write misses | 439system.cpu0.dtb.read_hits 17365788 # DTB read hits 440system.cpu0.dtb.read_misses 64419 # DTB read misses 441system.cpu0.dtb.write_hits 14563883 # DTB write hits 442system.cpu0.dtb.write_misses 6329 # DTB write misses |
| 442system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 443system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 444system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 445system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 443system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 444system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 445system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 446system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 446system.cpu0.dtb.flush_entries 3513 # Number of entries that have been flushed from TLB 447system.cpu0.dtb.align_faults 1432 # Number of TLB faults due to alignment restrictions 448system.cpu0.dtb.prefetch_faults 1922 # Number of TLB faults due to prefetch | 447system.cpu0.dtb.flush_entries 3519 # Number of entries that have been flushed from TLB 448system.cpu0.dtb.align_faults 1310 # Number of TLB faults due to alignment restrictions 449system.cpu0.dtb.prefetch_faults 1951 # Number of TLB faults due to prefetch |
| 449system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 450system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 450system.cpu0.dtb.perms_faults 561 # Number of TLB faults due to permissions restrictions 451system.cpu0.dtb.read_accesses 17370797 # DTB read accesses 452system.cpu0.dtb.write_accesses 14540568 # DTB write accesses | 451system.cpu0.dtb.perms_faults 572 # Number of TLB faults due to permissions restrictions 452system.cpu0.dtb.read_accesses 17430207 # DTB read accesses 453system.cpu0.dtb.write_accesses 14570212 # DTB write accesses |
| 453system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 454system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 454system.cpu0.dtb.hits 31842009 # DTB hits 455system.cpu0.dtb.misses 69356 # DTB misses 456system.cpu0.dtb.accesses 31911365 # DTB accesses | 455system.cpu0.dtb.hits 31929671 # DTB hits 456system.cpu0.dtb.misses 70748 # DTB misses 457system.cpu0.dtb.accesses 32000419 # DTB accesses |
| 457system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 458system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 459system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 460system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 461system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 462system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 463system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 464system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 478system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 479system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 480system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 481system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 482system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 483system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 484system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 485system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 458system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 459system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 460system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 461system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 462system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 463system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 464system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 465system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 479system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 480system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 481system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 482system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 483system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 484system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 485system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 486system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 486system.cpu0.itb.walker.walks 3833 # Table walker walks requested 487system.cpu0.itb.walker.walksShort 3833 # Table walker walks initiated with short descriptors | 487system.cpu0.itb.walker.walks 3844 # Table walker walks requested 488system.cpu0.itb.walker.walksShort 3844 # Table walker walks initiated with short descriptors |
| 488system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate | 489system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate |
| 489system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3526 # Level at which table walker walks with short descriptors terminate 490system.cpu0.itb.walker.walkWaitTime::samples 3833 # Table walker wait (enqueue to first request) latency 491system.cpu0.itb.walker.walkWaitTime::0 3833 100.00% 100.00% # Table walker wait (enqueue to first request) latency 492system.cpu0.itb.walker.walkWaitTime::total 3833 # Table walker wait (enqueue to first request) latency 493system.cpu0.itb.walker.walkCompletionTime::samples 2411 # Table walker service (enqueue to completion) latency 494system.cpu0.itb.walker.walkCompletionTime::mean 9827.457901 # Table walker service (enqueue to completion) latency 495system.cpu0.itb.walker.walkCompletionTime::gmean 8615.260983 # Table walker service (enqueue to completion) latency 496system.cpu0.itb.walker.walkCompletionTime::stdev 5288.530479 # Table walker service (enqueue to completion) latency 497system.cpu0.itb.walker.walkCompletionTime::0-8191 893 37.04% 37.04% # Table walker service (enqueue to completion) latency 498system.cpu0.itb.walker.walkCompletionTime::8192-16383 1467 60.85% 97.88% # Table walker service (enqueue to completion) latency 499system.cpu0.itb.walker.walkCompletionTime::16384-24575 9 0.37% 98.26% # Table walker service (enqueue to completion) latency 500system.cpu0.itb.walker.walkCompletionTime::24576-32767 39 1.62% 99.88% # Table walker service (enqueue to completion) latency | 490system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3537 # Level at which table walker walks with short descriptors terminate 491system.cpu0.itb.walker.walkWaitTime::samples 3844 # Table walker wait (enqueue to first request) latency 492system.cpu0.itb.walker.walkWaitTime::0 3844 100.00% 100.00% # Table walker wait (enqueue to first request) latency 493system.cpu0.itb.walker.walkWaitTime::total 3844 # Table walker wait (enqueue to first request) latency 494system.cpu0.itb.walker.walkCompletionTime::samples 2412 # Table walker service (enqueue to completion) latency 495system.cpu0.itb.walker.walkCompletionTime::mean 9287.312604 # Table walker service (enqueue to completion) latency 496system.cpu0.itb.walker.walkCompletionTime::gmean 8105.691907 # Table walker service (enqueue to completion) latency 497system.cpu0.itb.walker.walkCompletionTime::stdev 5199.777734 # Table walker service (enqueue to completion) latency 498system.cpu0.itb.walker.walkCompletionTime::0-8191 996 41.29% 41.29% # Table walker service (enqueue to completion) latency 499system.cpu0.itb.walker.walkCompletionTime::8192-16383 1373 56.92% 98.22% # Table walker service (enqueue to completion) latency 500system.cpu0.itb.walker.walkCompletionTime::16384-24575 5 0.21% 98.42% # Table walker service (enqueue to completion) latency 501system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 99.88% # Table walker service (enqueue to completion) latency |
| 501system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.08% 99.96% # Table walker service (enqueue to completion) latency 502system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency | 502system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.08% 99.96% # Table walker service (enqueue to completion) latency 503system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency |
| 503system.cpu0.itb.walker.walkCompletionTime::total 2411 # Table walker service (enqueue to completion) latency | 504system.cpu0.itb.walker.walkCompletionTime::total 2412 # Table walker service (enqueue to completion) latency |
| 504system.cpu0.itb.walker.walksPending::samples 328041000 # Table walker pending requests distribution 505system.cpu0.itb.walker.walksPending::0 328041000 100.00% 100.00% # Table walker pending requests distribution 506system.cpu0.itb.walker.walksPending::total 328041000 # Table walker pending requests distribution | 505system.cpu0.itb.walker.walksPending::samples 328041000 # Table walker pending requests distribution 506system.cpu0.itb.walker.walksPending::0 328041000 100.00% 100.00% # Table walker pending requests distribution 507system.cpu0.itb.walker.walksPending::total 328041000 # Table walker pending requests distribution |
| 507system.cpu0.itb.walker.walkPageSizes::4K 2111 87.56% 87.56% # Table walker page sizes translated | 508system.cpu0.itb.walker.walkPageSizes::4K 2112 87.56% 87.56% # Table walker page sizes translated |
| 508system.cpu0.itb.walker.walkPageSizes::1M 300 12.44% 100.00% # Table walker page sizes translated | 509system.cpu0.itb.walker.walkPageSizes::1M 300 12.44% 100.00% # Table walker page sizes translated |
| 509system.cpu0.itb.walker.walkPageSizes::total 2411 # Table walker page sizes translated | 510system.cpu0.itb.walker.walkPageSizes::total 2412 # Table walker page sizes translated |
| 510system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 511system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 511system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3833 # Table walker requests started/completed, data/inst 512system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3833 # Table walker requests started/completed, data/inst | 512system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3844 # Table walker requests started/completed, data/inst 513system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3844 # Table walker requests started/completed, data/inst |
| 513system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 514system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 514system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2411 # Table walker requests started/completed, data/inst 515system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2411 # Table walker requests started/completed, data/inst 516system.cpu0.itb.walker.walkRequestOrigin::total 6244 # Table walker requests started/completed, data/inst 517system.cpu0.itb.inst_hits 38721907 # ITB inst hits 518system.cpu0.itb.inst_misses 3833 # ITB inst misses | 515system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2412 # Table walker requests started/completed, data/inst 516system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2412 # Table walker requests started/completed, data/inst 517system.cpu0.itb.walker.walkRequestOrigin::total 6256 # Table walker requests started/completed, data/inst 518system.cpu0.itb.inst_hits 38673096 # ITB inst hits 519system.cpu0.itb.inst_misses 3844 # ITB inst misses |
| 519system.cpu0.itb.read_hits 0 # DTB read hits 520system.cpu0.itb.read_misses 0 # DTB read misses 521system.cpu0.itb.write_hits 0 # DTB write hits 522system.cpu0.itb.write_misses 0 # DTB write misses 523system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 524system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 525system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 526system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 520system.cpu0.itb.read_hits 0 # DTB read hits 521system.cpu0.itb.read_misses 0 # DTB read misses 522system.cpu0.itb.write_hits 0 # DTB write hits 523system.cpu0.itb.write_misses 0 # DTB write misses 524system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 525system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 526system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 527system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 527system.cpu0.itb.flush_entries 2217 # Number of entries that have been flushed from TLB | 528system.cpu0.itb.flush_entries 2215 # Number of entries that have been flushed from TLB |
| 528system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 529system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 530system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 529system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 530system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 531system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 531system.cpu0.itb.perms_faults 7269 # Number of TLB faults due to permissions restrictions | 532system.cpu0.itb.perms_faults 7305 # Number of TLB faults due to permissions restrictions |
| 532system.cpu0.itb.read_accesses 0 # DTB read accesses 533system.cpu0.itb.write_accesses 0 # DTB write accesses | 533system.cpu0.itb.read_accesses 0 # DTB read accesses 534system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 534system.cpu0.itb.inst_accesses 38725740 # ITB inst accesses 535system.cpu0.itb.hits 38721907 # DTB hits 536system.cpu0.itb.misses 3833 # DTB misses 537system.cpu0.itb.accesses 38725740 # DTB accesses 538system.cpu0.numCycles 164661578 # number of cpu cycles simulated | 535system.cpu0.itb.inst_accesses 38676940 # ITB inst accesses 536system.cpu0.itb.hits 38673096 # DTB hits 537system.cpu0.itb.misses 3844 # DTB misses 538system.cpu0.itb.accesses 38676940 # DTB accesses 539system.cpu0.numCycles 164345884 # number of cpu cycles simulated |
| 539system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 540system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 540system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 541system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 541system.cpu0.committedInsts 79519346 # Number of instructions committed 542system.cpu0.committedOps 95696233 # Number of ops (including micro ops) committed 543system.cpu0.discardedOps 5042389 # Number of ops (including micro ops) which were discarded before commit 544system.cpu0.numFetchSuspends 1874 # Number of times Execute suspended instruction fetching 545system.cpu0.quiesceCycles 5527576937 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 546system.cpu0.cpi 2.070711 # CPI: cycles per instruction 547system.cpu0.ipc 0.482926 # IPC: instructions per cycle | 542system.cpu0.committedInsts 79729346 # Number of instructions committed 543system.cpu0.committedOps 95953153 # Number of ops (including micro ops) committed 544system.cpu0.discardedOps 5189304 # Number of ops (including micro ops) which were discarded before commit 545system.cpu0.numFetchSuspends 1865 # Number of times Execute suspended instruction fetching 546system.cpu0.quiesceCycles 5527748141 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 547system.cpu0.cpi 2.061297 # CPI: cycles per instruction 548system.cpu0.ipc 0.485131 # IPC: instructions per cycle |
| 548system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 549system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 549system.cpu0.kern.inst.quiesce 1879 # number of quiesce instructions executed 550system.cpu0.tickCycles 128007340 # Number of cycles that the object actually ticked 551system.cpu0.idleCycles 36654238 # Total number of cycles that the object has spent stopped 552system.cpu0.dcache.tags.replacements 714687 # number of replacements 553system.cpu0.dcache.tags.tagsinuse 500.798460 # Cycle average of tags in use 554system.cpu0.dcache.tags.total_refs 30351139 # Total number of references to valid blocks. 555system.cpu0.dcache.tags.sampled_refs 715199 # Sample count of references to valid blocks. 556system.cpu0.dcache.tags.avg_refs 42.437334 # Average number of references to valid blocks. | 550system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed 551system.cpu0.tickCycles 127709647 # Number of cycles that the object actually ticked 552system.cpu0.idleCycles 36636237 # Total number of cycles that the object has spent stopped 553system.cpu0.dcache.tags.replacements 716917 # number of replacements 554system.cpu0.dcache.tags.tagsinuse 500.984031 # Cycle average of tags in use 555system.cpu0.dcache.tags.total_refs 30425669 # Total number of references to valid blocks. 556system.cpu0.dcache.tags.sampled_refs 717429 # Sample count of references to valid blocks. 557system.cpu0.dcache.tags.avg_refs 42.409310 # Average number of references to valid blocks. |
| 557system.cpu0.dcache.tags.warmup_cycle 346166500 # Cycle when the warmup percentage was hit. | 558system.cpu0.dcache.tags.warmup_cycle 346166500 # Cycle when the warmup percentage was hit. |
| 558system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.798460 # Average occupied blocks per requestor 559system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978122 # Average percentage of cache occupancy 560system.cpu0.dcache.tags.occ_percent::total 0.978122 # Average percentage of cache occupancy | 559system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.984031 # Average occupied blocks per requestor 560system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978484 # Average percentage of cache occupancy 561system.cpu0.dcache.tags.occ_percent::total 0.978484 # Average percentage of cache occupancy |
| 561system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 562system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 562system.cpu0.dcache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id 563system.cpu0.dcache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id 564system.cpu0.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id | 563system.cpu0.dcache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id 564system.cpu0.dcache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id 565system.cpu0.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id |
| 565system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 566system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 566system.cpu0.dcache.tags.tag_accesses 63691793 # Number of tag accesses 567system.cpu0.dcache.tags.data_accesses 63691793 # Number of data accesses 568system.cpu0.dcache.ReadReq_hits::cpu0.data 15776398 # number of ReadReq hits 569system.cpu0.dcache.ReadReq_hits::total 15776398 # number of ReadReq hits 570system.cpu0.dcache.WriteReq_hits::cpu0.data 13416114 # number of WriteReq hits 571system.cpu0.dcache.WriteReq_hits::total 13416114 # number of WriteReq hits 572system.cpu0.dcache.SoftPFReq_hits::cpu0.data 321622 # number of SoftPFReq hits 573system.cpu0.dcache.SoftPFReq_hits::total 321622 # number of SoftPFReq hits 574system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365571 # number of LoadLockedReq hits 575system.cpu0.dcache.LoadLockedReq_hits::total 365571 # number of LoadLockedReq hits 576system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361457 # number of StoreCondReq hits 577system.cpu0.dcache.StoreCondReq_hits::total 361457 # number of StoreCondReq hits 578system.cpu0.dcache.demand_hits::cpu0.data 29192512 # number of demand (read+write) hits 579system.cpu0.dcache.demand_hits::total 29192512 # number of demand (read+write) hits 580system.cpu0.dcache.overall_hits::cpu0.data 29514134 # number of overall hits 581system.cpu0.dcache.overall_hits::total 29514134 # number of overall hits 582system.cpu0.dcache.ReadReq_misses::cpu0.data 464236 # number of ReadReq misses 583system.cpu0.dcache.ReadReq_misses::total 464236 # number of ReadReq misses 584system.cpu0.dcache.WriteReq_misses::cpu0.data 577383 # number of WriteReq misses 585system.cpu0.dcache.WriteReq_misses::total 577383 # number of WriteReq misses 586system.cpu0.dcache.SoftPFReq_misses::cpu0.data 136671 # number of SoftPFReq misses 587system.cpu0.dcache.SoftPFReq_misses::total 136671 # number of SoftPFReq misses 588system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21082 # number of LoadLockedReq misses 589system.cpu0.dcache.LoadLockedReq_misses::total 21082 # number of LoadLockedReq misses 590system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20299 # number of StoreCondReq misses 591system.cpu0.dcache.StoreCondReq_misses::total 20299 # number of StoreCondReq misses 592system.cpu0.dcache.demand_misses::cpu0.data 1041619 # number of demand (read+write) misses 593system.cpu0.dcache.demand_misses::total 1041619 # number of demand (read+write) misses 594system.cpu0.dcache.overall_misses::cpu0.data 1178290 # number of overall misses 595system.cpu0.dcache.overall_misses::total 1178290 # number of overall misses 596system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6143546304 # number of ReadReq miss cycles 597system.cpu0.dcache.ReadReq_miss_latency::total 6143546304 # number of ReadReq miss cycles 598system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9155597212 # number of WriteReq miss cycles 599system.cpu0.dcache.WriteReq_miss_latency::total 9155597212 # number of WriteReq miss cycles 600system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 318010226 # number of LoadLockedReq miss cycles 601system.cpu0.dcache.LoadLockedReq_miss_latency::total 318010226 # number of LoadLockedReq miss cycles 602system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 454779772 # number of StoreCondReq miss cycles 603system.cpu0.dcache.StoreCondReq_miss_latency::total 454779772 # number of StoreCondReq miss cycles 604system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 214000 # number of StoreCondFailReq miss cycles 605system.cpu0.dcache.StoreCondFailReq_miss_latency::total 214000 # number of StoreCondFailReq miss cycles 606system.cpu0.dcache.demand_miss_latency::cpu0.data 15299143516 # number of demand (read+write) miss cycles 607system.cpu0.dcache.demand_miss_latency::total 15299143516 # number of demand (read+write) miss cycles 608system.cpu0.dcache.overall_miss_latency::cpu0.data 15299143516 # number of overall miss cycles 609system.cpu0.dcache.overall_miss_latency::total 15299143516 # number of overall miss cycles 610system.cpu0.dcache.ReadReq_accesses::cpu0.data 16240634 # number of ReadReq accesses(hits+misses) 611system.cpu0.dcache.ReadReq_accesses::total 16240634 # number of ReadReq accesses(hits+misses) 612system.cpu0.dcache.WriteReq_accesses::cpu0.data 13993497 # number of WriteReq accesses(hits+misses) 613system.cpu0.dcache.WriteReq_accesses::total 13993497 # number of WriteReq accesses(hits+misses) 614system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 458293 # number of SoftPFReq accesses(hits+misses) 615system.cpu0.dcache.SoftPFReq_accesses::total 458293 # number of SoftPFReq accesses(hits+misses) 616system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386653 # number of LoadLockedReq accesses(hits+misses) 617system.cpu0.dcache.LoadLockedReq_accesses::total 386653 # number of LoadLockedReq accesses(hits+misses) 618system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381756 # number of StoreCondReq accesses(hits+misses) 619system.cpu0.dcache.StoreCondReq_accesses::total 381756 # number of StoreCondReq accesses(hits+misses) 620system.cpu0.dcache.demand_accesses::cpu0.data 30234131 # number of demand (read+write) accesses 621system.cpu0.dcache.demand_accesses::total 30234131 # number of demand (read+write) accesses 622system.cpu0.dcache.overall_accesses::cpu0.data 30692424 # number of overall (read+write) accesses 623system.cpu0.dcache.overall_accesses::total 30692424 # number of overall (read+write) accesses 624system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028585 # miss rate for ReadReq accesses 625system.cpu0.dcache.ReadReq_miss_rate::total 0.028585 # miss rate for ReadReq accesses 626system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041261 # miss rate for WriteReq accesses 627system.cpu0.dcache.WriteReq_miss_rate::total 0.041261 # miss rate for WriteReq accesses 628system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.298218 # miss rate for SoftPFReq accesses 629system.cpu0.dcache.SoftPFReq_miss_rate::total 0.298218 # miss rate for SoftPFReq accesses 630system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054524 # miss rate for LoadLockedReq accesses 631system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054524 # miss rate for LoadLockedReq accesses 632system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053173 # miss rate for StoreCondReq accesses 633system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053173 # miss rate for StoreCondReq accesses 634system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034452 # miss rate for demand accesses 635system.cpu0.dcache.demand_miss_rate::total 0.034452 # miss rate for demand accesses 636system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038390 # miss rate for overall accesses 637system.cpu0.dcache.overall_miss_rate::total 0.038390 # miss rate for overall accesses 638system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13233.670599 # average ReadReq miss latency 639system.cpu0.dcache.ReadReq_avg_miss_latency::total 13233.670599 # average ReadReq miss latency 640system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15857.060585 # average WriteReq miss latency 641system.cpu0.dcache.WriteReq_avg_miss_latency::total 15857.060585 # average WriteReq miss latency 642system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15084.442937 # average LoadLockedReq miss latency 643system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15084.442937 # average LoadLockedReq miss latency 644system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22404.048081 # average StoreCondReq miss latency 645system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22404.048081 # average StoreCondReq miss latency | 567system.cpu0.dcache.tags.tag_accesses 63847334 # Number of tag accesses 568system.cpu0.dcache.tags.data_accesses 63847334 # Number of data accesses 569system.cpu0.dcache.ReadReq_hits::cpu0.data 15827695 # number of ReadReq hits 570system.cpu0.dcache.ReadReq_hits::total 15827695 # number of ReadReq hits 571system.cpu0.dcache.WriteReq_hits::cpu0.data 13439418 # number of WriteReq hits 572system.cpu0.dcache.WriteReq_hits::total 13439418 # number of WriteReq hits 573system.cpu0.dcache.SoftPFReq_hits::cpu0.data 321505 # number of SoftPFReq hits 574system.cpu0.dcache.SoftPFReq_hits::total 321505 # number of SoftPFReq hits 575system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365521 # number of LoadLockedReq hits 576system.cpu0.dcache.LoadLockedReq_hits::total 365521 # number of LoadLockedReq hits 577system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361496 # number of StoreCondReq hits 578system.cpu0.dcache.StoreCondReq_hits::total 361496 # number of StoreCondReq hits 579system.cpu0.dcache.demand_hits::cpu0.data 29267113 # number of demand (read+write) hits 580system.cpu0.dcache.demand_hits::total 29267113 # number of demand (read+write) hits 581system.cpu0.dcache.overall_hits::cpu0.data 29588618 # number of overall hits 582system.cpu0.dcache.overall_hits::total 29588618 # number of overall hits 583system.cpu0.dcache.ReadReq_misses::cpu0.data 465920 # number of ReadReq misses 584system.cpu0.dcache.ReadReq_misses::total 465920 # number of ReadReq misses 585system.cpu0.dcache.WriteReq_misses::cpu0.data 577900 # number of WriteReq misses 586system.cpu0.dcache.WriteReq_misses::total 577900 # number of WriteReq misses 587system.cpu0.dcache.SoftPFReq_misses::cpu0.data 136723 # number of SoftPFReq misses 588system.cpu0.dcache.SoftPFReq_misses::total 136723 # number of SoftPFReq misses 589system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21141 # number of LoadLockedReq misses 590system.cpu0.dcache.LoadLockedReq_misses::total 21141 # number of LoadLockedReq misses 591system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20265 # number of StoreCondReq misses 592system.cpu0.dcache.StoreCondReq_misses::total 20265 # number of StoreCondReq misses 593system.cpu0.dcache.demand_misses::cpu0.data 1043820 # number of demand (read+write) misses 594system.cpu0.dcache.demand_misses::total 1043820 # number of demand (read+write) misses 595system.cpu0.dcache.overall_misses::cpu0.data 1180543 # number of overall misses 596system.cpu0.dcache.overall_misses::total 1180543 # number of overall misses 597system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6144584831 # number of ReadReq miss cycles 598system.cpu0.dcache.ReadReq_miss_latency::total 6144584831 # number of ReadReq miss cycles 599system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9172351028 # number of WriteReq miss cycles 600system.cpu0.dcache.WriteReq_miss_latency::total 9172351028 # number of WriteReq miss cycles 601system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 319190979 # number of LoadLockedReq miss cycles 602system.cpu0.dcache.LoadLockedReq_miss_latency::total 319190979 # number of LoadLockedReq miss cycles 603system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 453656289 # number of StoreCondReq miss cycles 604system.cpu0.dcache.StoreCondReq_miss_latency::total 453656289 # number of StoreCondReq miss cycles 605system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 133500 # number of StoreCondFailReq miss cycles 606system.cpu0.dcache.StoreCondFailReq_miss_latency::total 133500 # number of StoreCondFailReq miss cycles 607system.cpu0.dcache.demand_miss_latency::cpu0.data 15316935859 # number of demand (read+write) miss cycles 608system.cpu0.dcache.demand_miss_latency::total 15316935859 # number of demand (read+write) miss cycles 609system.cpu0.dcache.overall_miss_latency::cpu0.data 15316935859 # number of overall miss cycles 610system.cpu0.dcache.overall_miss_latency::total 15316935859 # number of overall miss cycles 611system.cpu0.dcache.ReadReq_accesses::cpu0.data 16293615 # number of ReadReq accesses(hits+misses) 612system.cpu0.dcache.ReadReq_accesses::total 16293615 # number of ReadReq accesses(hits+misses) 613system.cpu0.dcache.WriteReq_accesses::cpu0.data 14017318 # number of WriteReq accesses(hits+misses) 614system.cpu0.dcache.WriteReq_accesses::total 14017318 # number of WriteReq accesses(hits+misses) 615system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 458228 # number of SoftPFReq accesses(hits+misses) 616system.cpu0.dcache.SoftPFReq_accesses::total 458228 # number of SoftPFReq accesses(hits+misses) 617system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386662 # number of LoadLockedReq accesses(hits+misses) 618system.cpu0.dcache.LoadLockedReq_accesses::total 386662 # number of LoadLockedReq accesses(hits+misses) 619system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381761 # number of StoreCondReq accesses(hits+misses) 620system.cpu0.dcache.StoreCondReq_accesses::total 381761 # number of StoreCondReq accesses(hits+misses) 621system.cpu0.dcache.demand_accesses::cpu0.data 30310933 # number of demand (read+write) accesses 622system.cpu0.dcache.demand_accesses::total 30310933 # number of demand (read+write) accesses 623system.cpu0.dcache.overall_accesses::cpu0.data 30769161 # number of overall (read+write) accesses 624system.cpu0.dcache.overall_accesses::total 30769161 # number of overall (read+write) accesses 625system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028595 # miss rate for ReadReq accesses 626system.cpu0.dcache.ReadReq_miss_rate::total 0.028595 # miss rate for ReadReq accesses 627system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041228 # miss rate for WriteReq accesses 628system.cpu0.dcache.WriteReq_miss_rate::total 0.041228 # miss rate for WriteReq accesses 629system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.298373 # miss rate for SoftPFReq accesses 630system.cpu0.dcache.SoftPFReq_miss_rate::total 0.298373 # miss rate for SoftPFReq accesses 631system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054676 # miss rate for LoadLockedReq accesses 632system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054676 # miss rate for LoadLockedReq accesses 633system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053083 # miss rate for StoreCondReq accesses 634system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053083 # miss rate for StoreCondReq accesses 635system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034437 # miss rate for demand accesses 636system.cpu0.dcache.demand_miss_rate::total 0.034437 # miss rate for demand accesses 637system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038368 # miss rate for overall accesses 638system.cpu0.dcache.overall_miss_rate::total 0.038368 # miss rate for overall accesses 639system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13188.068404 # average ReadReq miss latency 640system.cpu0.dcache.ReadReq_avg_miss_latency::total 13188.068404 # average ReadReq miss latency 641system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15871.865423 # average WriteReq miss latency 642system.cpu0.dcache.WriteReq_avg_miss_latency::total 15871.865423 # average WriteReq miss latency 643system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15098.196821 # average LoadLockedReq miss latency 644system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15098.196821 # average LoadLockedReq miss latency 645system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22386.197335 # average StoreCondReq miss latency 646system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22386.197335 # average StoreCondReq miss latency |
| 646system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 647system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 647system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 648system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 648system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14687.849891 # average overall miss latency 649system.cpu0.dcache.demand_avg_miss_latency::total 14687.849891 # average overall miss latency 650system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12984.191936 # average overall miss latency 651system.cpu0.dcache.overall_avg_miss_latency::total 12984.191936 # average overall miss latency | 649system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14673.924488 # average overall miss latency 650system.cpu0.dcache.demand_avg_miss_latency::total 14673.924488 # average overall miss latency 651system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12974.483656 # average overall miss latency 652system.cpu0.dcache.overall_avg_miss_latency::total 12974.483656 # average overall miss latency |
| 652system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 653system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 654system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 655system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 656system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 657system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 658system.cpu0.dcache.fast_writes 0 # number of fast writes performed 659system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 653system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 654system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 655system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 656system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 657system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 658system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 659system.cpu0.dcache.fast_writes 0 # number of fast writes performed 660system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 660system.cpu0.dcache.writebacks::writebacks 514395 # number of writebacks 661system.cpu0.dcache.writebacks::total 514395 # number of writebacks 662system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 72393 # number of ReadReq MSHR hits 663system.cpu0.dcache.ReadReq_mshr_hits::total 72393 # number of ReadReq MSHR hits 664system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 253509 # number of WriteReq MSHR hits 665system.cpu0.dcache.WriteReq_mshr_hits::total 253509 # number of WriteReq MSHR hits 666system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14653 # number of LoadLockedReq MSHR hits 667system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14653 # number of LoadLockedReq MSHR hits 668system.cpu0.dcache.demand_mshr_hits::cpu0.data 325902 # number of demand (read+write) MSHR hits 669system.cpu0.dcache.demand_mshr_hits::total 325902 # number of demand (read+write) MSHR hits 670system.cpu0.dcache.overall_mshr_hits::cpu0.data 325902 # number of overall MSHR hits 671system.cpu0.dcache.overall_mshr_hits::total 325902 # number of overall MSHR hits 672system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 391843 # number of ReadReq MSHR misses 673system.cpu0.dcache.ReadReq_mshr_misses::total 391843 # number of ReadReq MSHR misses 674system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323874 # number of WriteReq MSHR misses 675system.cpu0.dcache.WriteReq_mshr_misses::total 323874 # number of WriteReq MSHR misses 676system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 103461 # number of SoftPFReq MSHR misses 677system.cpu0.dcache.SoftPFReq_mshr_misses::total 103461 # number of SoftPFReq MSHR misses 678system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6429 # number of LoadLockedReq MSHR misses 679system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6429 # number of LoadLockedReq MSHR misses 680system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20299 # number of StoreCondReq MSHR misses 681system.cpu0.dcache.StoreCondReq_mshr_misses::total 20299 # number of StoreCondReq MSHR misses 682system.cpu0.dcache.demand_mshr_misses::cpu0.data 715717 # number of demand (read+write) MSHR misses 683system.cpu0.dcache.demand_mshr_misses::total 715717 # number of demand (read+write) MSHR misses 684system.cpu0.dcache.overall_mshr_misses::cpu0.data 819178 # number of overall MSHR misses 685system.cpu0.dcache.overall_mshr_misses::total 819178 # number of overall MSHR misses 686system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20386 # number of ReadReq MSHR uncacheable 687system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20386 # number of ReadReq MSHR uncacheable 688system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19085 # number of WriteReq MSHR uncacheable 689system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19085 # number of WriteReq MSHR uncacheable 690system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39471 # number of overall MSHR uncacheable misses 691system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39471 # number of overall MSHR uncacheable misses 692system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4433666662 # number of ReadReq MSHR miss cycles 693system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4433666662 # number of ReadReq MSHR miss cycles 694system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4919386398 # number of WriteReq MSHR miss cycles 695system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4919386398 # number of WriteReq MSHR miss cycles 696system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1621821456 # number of SoftPFReq MSHR miss cycles 697system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1621821456 # number of SoftPFReq MSHR miss cycles 698system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 96313514 # number of LoadLockedReq MSHR miss cycles 699system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96313514 # number of LoadLockedReq MSHR miss cycles 700system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 423613728 # number of StoreCondReq MSHR miss cycles 701system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 423613728 # number of StoreCondReq MSHR miss cycles 702system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 205000 # number of StoreCondFailReq MSHR miss cycles 703system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 205000 # number of StoreCondFailReq MSHR miss cycles 704system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9353053060 # number of demand (read+write) MSHR miss cycles 705system.cpu0.dcache.demand_mshr_miss_latency::total 9353053060 # number of demand (read+write) MSHR miss cycles 706system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10974874516 # number of overall MSHR miss cycles 707system.cpu0.dcache.overall_mshr_miss_latency::total 10974874516 # number of overall MSHR miss cycles 708system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4276413999 # number of ReadReq MSHR uncacheable cycles 709system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4276413999 # number of ReadReq MSHR uncacheable cycles 710system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3259254500 # number of WriteReq MSHR uncacheable cycles 711system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3259254500 # number of WriteReq MSHR uncacheable cycles 712system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7535668499 # number of overall MSHR uncacheable cycles 713system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7535668499 # number of overall MSHR uncacheable cycles 714system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024127 # mshr miss rate for ReadReq accesses 715system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024127 # mshr miss rate for ReadReq accesses 716system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023145 # mshr miss rate for WriteReq accesses 717system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023145 # mshr miss rate for WriteReq accesses 718system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225753 # mshr miss rate for SoftPFReq accesses 719system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225753 # mshr miss rate for SoftPFReq accesses 720system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016627 # mshr miss rate for LoadLockedReq accesses 721system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016627 # mshr miss rate for LoadLockedReq accesses 722system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053173 # mshr miss rate for StoreCondReq accesses 723system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053173 # mshr miss rate for StoreCondReq accesses 724system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023672 # mshr miss rate for demand accesses 725system.cpu0.dcache.demand_mshr_miss_rate::total 0.023672 # mshr miss rate for demand accesses 726system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026690 # mshr miss rate for overall accesses 727system.cpu0.dcache.overall_mshr_miss_rate::total 0.026690 # mshr miss rate for overall accesses 728system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11314.905873 # average ReadReq mshr miss latency 729system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11314.905873 # average ReadReq mshr miss latency 730system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15189.198262 # average WriteReq mshr miss latency 731system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15189.198262 # average WriteReq mshr miss latency 732system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15675.679299 # average SoftPFReq mshr miss latency 733system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15675.679299 # average SoftPFReq mshr miss latency 734system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14981.103438 # average LoadLockedReq mshr miss latency 735system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14981.103438 # average LoadLockedReq mshr miss latency 736system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20868.699345 # average StoreCondReq mshr miss latency 737system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20868.699345 # average StoreCondReq mshr miss latency | 661system.cpu0.dcache.writebacks::writebacks 515635 # number of writebacks 662system.cpu0.dcache.writebacks::total 515635 # number of writebacks 663system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 72452 # number of ReadReq MSHR hits 664system.cpu0.dcache.ReadReq_mshr_hits::total 72452 # number of ReadReq MSHR hits 665system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 253659 # number of WriteReq MSHR hits 666system.cpu0.dcache.WriteReq_mshr_hits::total 253659 # number of WriteReq MSHR hits 667system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14673 # number of LoadLockedReq MSHR hits 668system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14673 # number of LoadLockedReq MSHR hits 669system.cpu0.dcache.demand_mshr_hits::cpu0.data 326111 # number of demand (read+write) MSHR hits 670system.cpu0.dcache.demand_mshr_hits::total 326111 # number of demand (read+write) MSHR hits 671system.cpu0.dcache.overall_mshr_hits::cpu0.data 326111 # number of overall MSHR hits 672system.cpu0.dcache.overall_mshr_hits::total 326111 # number of overall MSHR hits 673system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 393468 # number of ReadReq MSHR misses 674system.cpu0.dcache.ReadReq_mshr_misses::total 393468 # number of ReadReq MSHR misses 675system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324241 # number of WriteReq MSHR misses 676system.cpu0.dcache.WriteReq_mshr_misses::total 324241 # number of WriteReq MSHR misses 677system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 103543 # number of SoftPFReq MSHR misses 678system.cpu0.dcache.SoftPFReq_mshr_misses::total 103543 # number of SoftPFReq MSHR misses 679system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6468 # number of LoadLockedReq MSHR misses 680system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6468 # number of LoadLockedReq MSHR misses 681system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20265 # number of StoreCondReq MSHR misses 682system.cpu0.dcache.StoreCondReq_mshr_misses::total 20265 # number of StoreCondReq MSHR misses 683system.cpu0.dcache.demand_mshr_misses::cpu0.data 717709 # number of demand (read+write) MSHR misses 684system.cpu0.dcache.demand_mshr_misses::total 717709 # number of demand (read+write) MSHR misses 685system.cpu0.dcache.overall_mshr_misses::cpu0.data 821252 # number of overall MSHR misses 686system.cpu0.dcache.overall_mshr_misses::total 821252 # number of overall MSHR misses 687system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20388 # number of ReadReq MSHR uncacheable 688system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20388 # number of ReadReq MSHR uncacheable 689system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19084 # number of WriteReq MSHR uncacheable 690system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19084 # number of WriteReq MSHR uncacheable 691system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39472 # number of overall MSHR uncacheable misses 692system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39472 # number of overall MSHR uncacheable misses 693system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4430984378 # number of ReadReq MSHR miss cycles 694system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4430984378 # number of ReadReq MSHR miss cycles 695system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4926577100 # number of WriteReq MSHR miss cycles 696system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4926577100 # number of WriteReq MSHR miss cycles 697system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1621170703 # number of SoftPFReq MSHR miss cycles 698system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1621170703 # number of SoftPFReq MSHR miss cycles 699system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 96485758 # number of LoadLockedReq MSHR miss cycles 700system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96485758 # number of LoadLockedReq MSHR miss cycles 701system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 422555211 # number of StoreCondReq MSHR miss cycles 702system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 422555211 # number of StoreCondReq MSHR miss cycles 703system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 127500 # number of StoreCondFailReq MSHR miss cycles 704system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 127500 # number of StoreCondFailReq MSHR miss cycles 705system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9357561478 # number of demand (read+write) MSHR miss cycles 706system.cpu0.dcache.demand_mshr_miss_latency::total 9357561478 # number of demand (read+write) MSHR miss cycles 707system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10978732181 # number of overall MSHR miss cycles 708system.cpu0.dcache.overall_mshr_miss_latency::total 10978732181 # number of overall MSHR miss cycles 709system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4278812500 # number of ReadReq MSHR uncacheable cycles 710system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4278812500 # number of ReadReq MSHR uncacheable cycles 711system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3259105000 # number of WriteReq MSHR uncacheable cycles 712system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3259105000 # number of WriteReq MSHR uncacheable cycles 713system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7537917500 # number of overall MSHR uncacheable cycles 714system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7537917500 # number of overall MSHR uncacheable cycles 715system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024149 # mshr miss rate for ReadReq accesses 716system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024149 # mshr miss rate for ReadReq accesses 717system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023131 # mshr miss rate for WriteReq accesses 718system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023131 # mshr miss rate for WriteReq accesses 719system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225964 # mshr miss rate for SoftPFReq accesses 720system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225964 # mshr miss rate for SoftPFReq accesses 721system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016728 # mshr miss rate for LoadLockedReq accesses 722system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016728 # mshr miss rate for LoadLockedReq accesses 723system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053083 # mshr miss rate for StoreCondReq accesses 724system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053083 # mshr miss rate for StoreCondReq accesses 725system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023678 # mshr miss rate for demand accesses 726system.cpu0.dcache.demand_mshr_miss_rate::total 0.023678 # mshr miss rate for demand accesses 727system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026691 # mshr miss rate for overall accesses 728system.cpu0.dcache.overall_mshr_miss_rate::total 0.026691 # mshr miss rate for overall accesses 729system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11261.358936 # average ReadReq mshr miss latency 730system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11261.358936 # average ReadReq mshr miss latency 731system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15194.183031 # average WriteReq mshr miss latency 732system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15194.183031 # average WriteReq mshr miss latency 733system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15656.980221 # average SoftPFReq mshr miss latency 734system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15656.980221 # average SoftPFReq mshr miss latency 735system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14917.402288 # average LoadLockedReq mshr miss latency 736system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14917.402288 # average LoadLockedReq mshr miss latency 737system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20851.478460 # average StoreCondReq mshr miss latency 738system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20851.478460 # average StoreCondReq mshr miss latency |
| 738system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 739system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 739system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 740system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 740system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13068.088448 # average overall mshr miss latency 741system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13068.088448 # average overall mshr miss latency 742system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13397.423412 # average overall mshr miss latency 743system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13397.423412 # average overall mshr miss latency 744system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209772.098450 # average ReadReq mshr uncacheable latency 745system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209772.098450 # average ReadReq mshr uncacheable latency 746system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170775.713911 # average WriteReq mshr uncacheable latency 747system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170775.713911 # average WriteReq mshr uncacheable latency 748system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190916.584302 # average overall mshr uncacheable latency 749system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190916.584302 # average overall mshr uncacheable latency | 741system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13038.099673 # average overall mshr miss latency 742system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13038.099673 # average overall mshr miss latency 743system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13368.286690 # average overall mshr miss latency 744system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13368.286690 # average overall mshr miss latency 745system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209869.163233 # average ReadReq mshr uncacheable latency 746system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209869.163233 # average ReadReq mshr uncacheable latency 747system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170776.828757 # average WriteReq mshr uncacheable latency 748system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170776.828757 # average WriteReq mshr uncacheable latency 749system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190968.724666 # average overall mshr uncacheable latency 750system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190968.724666 # average overall mshr uncacheable latency |
| 750system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 751system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 751system.cpu0.icache.tags.replacements 1966290 # number of replacements 752system.cpu0.icache.tags.tagsinuse 511.784569 # Cycle average of tags in use 753system.cpu0.icache.tags.total_refs 36747505 # Total number of references to valid blocks. 754system.cpu0.icache.tags.sampled_refs 1966802 # Sample count of references to valid blocks. 755system.cpu0.icache.tags.avg_refs 18.683886 # Average number of references to valid blocks. 756system.cpu0.icache.tags.warmup_cycle 6453364250 # Cycle when the warmup percentage was hit. 757system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.784569 # Average occupied blocks per requestor 758system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999579 # Average percentage of cache occupancy 759system.cpu0.icache.tags.occ_percent::total 0.999579 # Average percentage of cache occupancy | 752system.cpu0.icache.tags.replacements 1965366 # number of replacements 753system.cpu0.icache.tags.tagsinuse 511.785087 # Cycle average of tags in use 754system.cpu0.icache.tags.total_refs 36699580 # Total number of references to valid blocks. 755system.cpu0.icache.tags.sampled_refs 1965878 # Sample count of references to valid blocks. 756system.cpu0.icache.tags.avg_refs 18.668290 # Average number of references to valid blocks. 757system.cpu0.icache.tags.warmup_cycle 6403533250 # Cycle when the warmup percentage was hit. 758system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.785087 # Average occupied blocks per requestor 759system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999580 # Average percentage of cache occupancy 760system.cpu0.icache.tags.occ_percent::total 0.999580 # Average percentage of cache occupancy |
| 760system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 761system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 761system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id 762system.cpu0.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id 763system.cpu0.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id | 762system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id 763system.cpu0.icache.tags.age_task_id_blocks_1024::1 228 # Occupied blocks per task id 764system.cpu0.icache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id |
| 764system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 765system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 765system.cpu0.icache.tags.tag_accesses 79395451 # Number of tag accesses 766system.cpu0.icache.tags.data_accesses 79395451 # Number of data accesses 767system.cpu0.icache.ReadReq_hits::cpu0.inst 36747505 # number of ReadReq hits 768system.cpu0.icache.ReadReq_hits::total 36747505 # number of ReadReq hits 769system.cpu0.icache.demand_hits::cpu0.inst 36747505 # number of demand (read+write) hits 770system.cpu0.icache.demand_hits::total 36747505 # number of demand (read+write) hits 771system.cpu0.icache.overall_hits::cpu0.inst 36747505 # number of overall hits 772system.cpu0.icache.overall_hits::total 36747505 # number of overall hits 773system.cpu0.icache.ReadReq_misses::cpu0.inst 1966814 # number of ReadReq misses 774system.cpu0.icache.ReadReq_misses::total 1966814 # number of ReadReq misses 775system.cpu0.icache.demand_misses::cpu0.inst 1966814 # number of demand (read+write) misses 776system.cpu0.icache.demand_misses::total 1966814 # number of demand (read+write) misses 777system.cpu0.icache.overall_misses::cpu0.inst 1966814 # number of overall misses 778system.cpu0.icache.overall_misses::total 1966814 # number of overall misses 779system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18563219293 # number of ReadReq miss cycles 780system.cpu0.icache.ReadReq_miss_latency::total 18563219293 # number of ReadReq miss cycles 781system.cpu0.icache.demand_miss_latency::cpu0.inst 18563219293 # number of demand (read+write) miss cycles 782system.cpu0.icache.demand_miss_latency::total 18563219293 # number of demand (read+write) miss cycles 783system.cpu0.icache.overall_miss_latency::cpu0.inst 18563219293 # number of overall miss cycles 784system.cpu0.icache.overall_miss_latency::total 18563219293 # number of overall miss cycles 785system.cpu0.icache.ReadReq_accesses::cpu0.inst 38714319 # number of ReadReq accesses(hits+misses) 786system.cpu0.icache.ReadReq_accesses::total 38714319 # number of ReadReq accesses(hits+misses) 787system.cpu0.icache.demand_accesses::cpu0.inst 38714319 # number of demand (read+write) accesses 788system.cpu0.icache.demand_accesses::total 38714319 # number of demand (read+write) accesses 789system.cpu0.icache.overall_accesses::cpu0.inst 38714319 # number of overall (read+write) accesses 790system.cpu0.icache.overall_accesses::total 38714319 # number of overall (read+write) accesses 791system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050803 # miss rate for ReadReq accesses 792system.cpu0.icache.ReadReq_miss_rate::total 0.050803 # miss rate for ReadReq accesses 793system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050803 # miss rate for demand accesses 794system.cpu0.icache.demand_miss_rate::total 0.050803 # miss rate for demand accesses 795system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050803 # miss rate for overall accesses 796system.cpu0.icache.overall_miss_rate::total 0.050803 # miss rate for overall accesses 797system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9438.217998 # average ReadReq miss latency 798system.cpu0.icache.ReadReq_avg_miss_latency::total 9438.217998 # average ReadReq miss latency 799system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9438.217998 # average overall miss latency 800system.cpu0.icache.demand_avg_miss_latency::total 9438.217998 # average overall miss latency 801system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9438.217998 # average overall miss latency 802system.cpu0.icache.overall_avg_miss_latency::total 9438.217998 # average overall miss latency | 766system.cpu0.icache.tags.tag_accesses 79296841 # Number of tag accesses 767system.cpu0.icache.tags.data_accesses 79296841 # Number of data accesses 768system.cpu0.icache.ReadReq_hits::cpu0.inst 36699580 # number of ReadReq hits 769system.cpu0.icache.ReadReq_hits::total 36699580 # number of ReadReq hits 770system.cpu0.icache.demand_hits::cpu0.inst 36699580 # number of demand (read+write) hits 771system.cpu0.icache.demand_hits::total 36699580 # number of demand (read+write) hits 772system.cpu0.icache.overall_hits::cpu0.inst 36699580 # number of overall hits 773system.cpu0.icache.overall_hits::total 36699580 # number of overall hits 774system.cpu0.icache.ReadReq_misses::cpu0.inst 1965894 # number of ReadReq misses 775system.cpu0.icache.ReadReq_misses::total 1965894 # number of ReadReq misses 776system.cpu0.icache.demand_misses::cpu0.inst 1965894 # number of demand (read+write) misses 777system.cpu0.icache.demand_misses::total 1965894 # number of demand (read+write) misses 778system.cpu0.icache.overall_misses::cpu0.inst 1965894 # number of overall misses 779system.cpu0.icache.overall_misses::total 1965894 # number of overall misses 780system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18549717200 # number of ReadReq miss cycles 781system.cpu0.icache.ReadReq_miss_latency::total 18549717200 # number of ReadReq miss cycles 782system.cpu0.icache.demand_miss_latency::cpu0.inst 18549717200 # number of demand (read+write) miss cycles 783system.cpu0.icache.demand_miss_latency::total 18549717200 # number of demand (read+write) miss cycles 784system.cpu0.icache.overall_miss_latency::cpu0.inst 18549717200 # number of overall miss cycles 785system.cpu0.icache.overall_miss_latency::total 18549717200 # number of overall miss cycles 786system.cpu0.icache.ReadReq_accesses::cpu0.inst 38665474 # number of ReadReq accesses(hits+misses) 787system.cpu0.icache.ReadReq_accesses::total 38665474 # number of ReadReq accesses(hits+misses) 788system.cpu0.icache.demand_accesses::cpu0.inst 38665474 # number of demand (read+write) accesses 789system.cpu0.icache.demand_accesses::total 38665474 # number of demand (read+write) accesses 790system.cpu0.icache.overall_accesses::cpu0.inst 38665474 # number of overall (read+write) accesses 791system.cpu0.icache.overall_accesses::total 38665474 # number of overall (read+write) accesses 792system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050844 # miss rate for ReadReq accesses 793system.cpu0.icache.ReadReq_miss_rate::total 0.050844 # miss rate for ReadReq accesses 794system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050844 # miss rate for demand accesses 795system.cpu0.icache.demand_miss_rate::total 0.050844 # miss rate for demand accesses 796system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050844 # miss rate for overall accesses 797system.cpu0.icache.overall_miss_rate::total 0.050844 # miss rate for overall accesses 798system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9435.766730 # average ReadReq miss latency 799system.cpu0.icache.ReadReq_avg_miss_latency::total 9435.766730 # average ReadReq miss latency 800system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9435.766730 # average overall miss latency 801system.cpu0.icache.demand_avg_miss_latency::total 9435.766730 # average overall miss latency 802system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9435.766730 # average overall miss latency 803system.cpu0.icache.overall_avg_miss_latency::total 9435.766730 # average overall miss latency |
| 803system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 804system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 805system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 806system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 807system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 808system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 809system.cpu0.icache.fast_writes 0 # number of fast writes performed 810system.cpu0.icache.cache_copies 0 # number of cache copies performed | 804system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 805system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 806system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 807system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 808system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 809system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 810system.cpu0.icache.fast_writes 0 # number of fast writes performed 811system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 811system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1966814 # number of ReadReq MSHR misses 812system.cpu0.icache.ReadReq_mshr_misses::total 1966814 # number of ReadReq MSHR misses 813system.cpu0.icache.demand_mshr_misses::cpu0.inst 1966814 # number of demand (read+write) MSHR misses 814system.cpu0.icache.demand_mshr_misses::total 1966814 # number of demand (read+write) MSHR misses 815system.cpu0.icache.overall_mshr_misses::cpu0.inst 1966814 # number of overall MSHR misses 816system.cpu0.icache.overall_mshr_misses::total 1966814 # number of overall MSHR misses | 812system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1965894 # number of ReadReq MSHR misses 813system.cpu0.icache.ReadReq_mshr_misses::total 1965894 # number of ReadReq MSHR misses 814system.cpu0.icache.demand_mshr_misses::cpu0.inst 1965894 # number of demand (read+write) MSHR misses 815system.cpu0.icache.demand_mshr_misses::total 1965894 # number of demand (read+write) MSHR misses 816system.cpu0.icache.overall_mshr_misses::cpu0.inst 1965894 # number of overall MSHR misses 817system.cpu0.icache.overall_mshr_misses::total 1965894 # number of overall MSHR misses |
| 817system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3367 # number of ReadReq MSHR uncacheable 818system.cpu0.icache.ReadReq_mshr_uncacheable::total 3367 # number of ReadReq MSHR uncacheable 819system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3367 # number of overall MSHR uncacheable misses 820system.cpu0.icache.overall_mshr_uncacheable_misses::total 3367 # number of overall MSHR uncacheable misses | 818system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3367 # number of ReadReq MSHR uncacheable 819system.cpu0.icache.ReadReq_mshr_uncacheable::total 3367 # number of ReadReq MSHR uncacheable 820system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3367 # number of overall MSHR uncacheable misses 821system.cpu0.icache.overall_mshr_uncacheable_misses::total 3367 # number of overall MSHR uncacheable misses |
| 821system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16587142707 # number of ReadReq MSHR miss cycles 822system.cpu0.icache.ReadReq_mshr_miss_latency::total 16587142707 # number of ReadReq MSHR miss cycles 823system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16587142707 # number of demand (read+write) MSHR miss cycles 824system.cpu0.icache.demand_mshr_miss_latency::total 16587142707 # number of demand (read+write) MSHR miss cycles 825system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16587142707 # number of overall MSHR miss cycles 826system.cpu0.icache.overall_mshr_miss_latency::total 16587142707 # number of overall MSHR miss cycles | 822system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16574456804 # number of ReadReq MSHR miss cycles 823system.cpu0.icache.ReadReq_mshr_miss_latency::total 16574456804 # number of ReadReq MSHR miss cycles 824system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16574456804 # number of demand (read+write) MSHR miss cycles 825system.cpu0.icache.demand_mshr_miss_latency::total 16574456804 # number of demand (read+write) MSHR miss cycles 826system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16574456804 # number of overall MSHR miss cycles 827system.cpu0.icache.overall_mshr_miss_latency::total 16574456804 # number of overall MSHR miss cycles |
| 827system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 310652000 # number of ReadReq MSHR uncacheable cycles 828system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 310652000 # number of ReadReq MSHR uncacheable cycles 829system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 310652000 # number of overall MSHR uncacheable cycles 830system.cpu0.icache.overall_mshr_uncacheable_latency::total 310652000 # number of overall MSHR uncacheable cycles | 828system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 310652000 # number of ReadReq MSHR uncacheable cycles 829system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 310652000 # number of ReadReq MSHR uncacheable cycles 830system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 310652000 # number of overall MSHR uncacheable cycles 831system.cpu0.icache.overall_mshr_uncacheable_latency::total 310652000 # number of overall MSHR uncacheable cycles |
| 831system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050803 # mshr miss rate for ReadReq accesses 832system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050803 # mshr miss rate for ReadReq accesses 833system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050803 # mshr miss rate for demand accesses 834system.cpu0.icache.demand_mshr_miss_rate::total 0.050803 # mshr miss rate for demand accesses 835system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050803 # mshr miss rate for overall accesses 836system.cpu0.icache.overall_mshr_miss_rate::total 0.050803 # mshr miss rate for overall accesses 837system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8433.508561 # average ReadReq mshr miss latency 838system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8433.508561 # average ReadReq mshr miss latency 839system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8433.508561 # average overall mshr miss latency 840system.cpu0.icache.demand_avg_mshr_miss_latency::total 8433.508561 # average overall mshr miss latency 841system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8433.508561 # average overall mshr miss latency 842system.cpu0.icache.overall_avg_mshr_miss_latency::total 8433.508561 # average overall mshr miss latency | 832system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for ReadReq accesses 833system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050844 # mshr miss rate for ReadReq accesses 834system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for demand accesses 835system.cpu0.icache.demand_mshr_miss_rate::total 0.050844 # mshr miss rate for demand accesses 836system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for overall accesses 837system.cpu0.icache.overall_mshr_miss_rate::total 0.050844 # mshr miss rate for overall accesses 838system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8431.002284 # average ReadReq mshr miss latency 839system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8431.002284 # average ReadReq mshr miss latency 840system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8431.002284 # average overall mshr miss latency 841system.cpu0.icache.demand_avg_mshr_miss_latency::total 8431.002284 # average overall mshr miss latency 842system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8431.002284 # average overall mshr miss latency 843system.cpu0.icache.overall_avg_mshr_miss_latency::total 8431.002284 # average overall mshr miss latency |
| 843system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264 # average ReadReq mshr uncacheable latency 844system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92263.736264 # average ReadReq mshr uncacheable latency 845system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264 # average overall mshr uncacheable latency 846system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92263.736264 # average overall mshr uncacheable latency 847system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 844system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264 # average ReadReq mshr uncacheable latency 845system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92263.736264 # average ReadReq mshr uncacheable latency 846system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264 # average overall mshr uncacheable latency 847system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92263.736264 # average overall mshr uncacheable latency 848system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 848system.cpu0.l2cache.prefetcher.num_hwpf_issued 1838523 # number of hwpf issued 849system.cpu0.l2cache.prefetcher.pfIdentified 1838641 # number of prefetch candidates identified 850system.cpu0.l2cache.prefetcher.pfBufferHit 103 # number of redundant prefetches already in prefetch queue | 849system.cpu0.l2cache.prefetcher.num_hwpf_issued 1838784 # number of hwpf issued 850system.cpu0.l2cache.prefetcher.pfIdentified 1838936 # number of prefetch candidates identified 851system.cpu0.l2cache.prefetcher.pfBufferHit 132 # number of redundant prefetches already in prefetch queue |
| 851system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 852system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 852system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 853system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 853system.cpu0.l2cache.prefetcher.pfSpanPage 232831 # number of prefetches not generated due to page crossing 854system.cpu0.l2cache.tags.replacements 300437 # number of replacements 855system.cpu0.l2cache.tags.tagsinuse 16148.129146 # Cycle average of tags in use 856system.cpu0.l2cache.tags.total_refs 2913009 # Total number of references to valid blocks. 857system.cpu0.l2cache.tags.sampled_refs 316676 # Sample count of references to valid blocks. 858system.cpu0.l2cache.tags.avg_refs 9.198705 # Average number of references to valid blocks. 859system.cpu0.l2cache.tags.warmup_cycle 2826267479000 # Cycle when the warmup percentage was hit. 860system.cpu0.l2cache.tags.occ_blocks::writebacks 6686.637120 # Average occupied blocks per requestor 861system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 47.827012 # Average occupied blocks per requestor 862system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.093258 # Average occupied blocks per requestor 863system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5824.484196 # Average occupied blocks per requestor 864system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1950.328123 # Average occupied blocks per requestor 865system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1638.759437 # Average occupied blocks per requestor 866system.cpu0.l2cache.tags.occ_percent::writebacks 0.408120 # Average percentage of cache occupancy 867system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002919 # Average percentage of cache occupancy | 854system.cpu0.l2cache.prefetcher.pfSpanPage 233824 # number of prefetches not generated due to page crossing 855system.cpu0.l2cache.tags.replacements 299625 # number of replacements 856system.cpu0.l2cache.tags.tagsinuse 16147.057230 # Cycle average of tags in use 857system.cpu0.l2cache.tags.total_refs 2915503 # Total number of references to valid blocks. 858system.cpu0.l2cache.tags.sampled_refs 315876 # Sample count of references to valid blocks. 859system.cpu0.l2cache.tags.avg_refs 9.229897 # Average number of references to valid blocks. 860system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 861system.cpu0.l2cache.tags.occ_blocks::writebacks 6737.365934 # Average occupied blocks per requestor 862system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.298987 # Average occupied blocks per requestor 863system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.096459 # Average occupied blocks per requestor 864system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5766.699762 # Average occupied blocks per requestor 865system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1949.490017 # Average occupied blocks per requestor 866system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1636.106070 # Average occupied blocks per requestor 867system.cpu0.l2cache.tags.occ_percent::writebacks 0.411216 # Average percentage of cache occupancy 868system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003497 # Average percentage of cache occupancy |
| 868system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy | 869system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy |
| 869system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.355498 # Average percentage of cache occupancy 870system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.119039 # Average percentage of cache occupancy 871system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.100022 # Average percentage of cache occupancy 872system.cpu0.l2cache.tags.occ_percent::total 0.985604 # Average percentage of cache occupancy 873system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1008 # Occupied blocks per task id 874system.cpu0.l2cache.tags.occ_task_id_blocks::1023 17 # Occupied blocks per task id 875system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15214 # Occupied blocks per task id 876system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id 877system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 310 # Occupied blocks per task id 878system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 388 # Occupied blocks per task id 879system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 298 # Occupied blocks per task id 880system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 881system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 882system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id 883system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 884system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id 885system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4157 # Occupied blocks per task id 886system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7950 # Occupied blocks per task id 887system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2796 # Occupied blocks per task id 888system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061523 # Percentage of cache occupancy per task id 889system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.001038 # Percentage of cache occupancy per task id 890system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.928589 # Percentage of cache occupancy per task id 891system.cpu0.l2cache.tags.tag_accesses 55309423 # Number of tag accesses 892system.cpu0.l2cache.tags.data_accesses 55309423 # Number of data accesses 893system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 81547 # number of ReadReq hits 894system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4240 # number of ReadReq hits 895system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1895666 # number of ReadReq hits 896system.cpu0.l2cache.ReadReq_hits::cpu0.data 400950 # number of ReadReq hits 897system.cpu0.l2cache.ReadReq_hits::total 2382403 # number of ReadReq hits 898system.cpu0.l2cache.Writeback_hits::writebacks 514393 # number of Writeback hits 899system.cpu0.l2cache.Writeback_hits::total 514393 # number of Writeback hits 900system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28717 # number of UpgradeReq hits 901system.cpu0.l2cache.UpgradeReq_hits::total 28717 # number of UpgradeReq hits 902system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1850 # number of SCUpgradeReq hits 903system.cpu0.l2cache.SCUpgradeReq_hits::total 1850 # number of SCUpgradeReq hits 904system.cpu0.l2cache.ReadExReq_hits::cpu0.data 223495 # number of ReadExReq hits 905system.cpu0.l2cache.ReadExReq_hits::total 223495 # number of ReadExReq hits 906system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 81547 # number of demand (read+write) hits 907system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4240 # number of demand (read+write) hits 908system.cpu0.l2cache.demand_hits::cpu0.inst 1895666 # number of demand (read+write) hits 909system.cpu0.l2cache.demand_hits::cpu0.data 624445 # number of demand (read+write) hits 910system.cpu0.l2cache.demand_hits::total 2605898 # number of demand (read+write) hits 911system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 81547 # number of overall hits 912system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4240 # number of overall hits 913system.cpu0.l2cache.overall_hits::cpu0.inst 1895666 # number of overall hits 914system.cpu0.l2cache.overall_hits::cpu0.data 624445 # number of overall hits 915system.cpu0.l2cache.overall_hits::total 2605898 # number of overall hits 916system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 820 # number of ReadReq misses 917system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 137 # number of ReadReq misses 918system.cpu0.l2cache.ReadReq_misses::cpu0.inst 71148 # number of ReadReq misses 919system.cpu0.l2cache.ReadReq_misses::cpu0.data 100778 # number of ReadReq misses 920system.cpu0.l2cache.ReadReq_misses::total 172883 # number of ReadReq misses 921system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26770 # number of UpgradeReq misses 922system.cpu0.l2cache.UpgradeReq_misses::total 26770 # number of UpgradeReq misses 923system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18449 # number of SCUpgradeReq misses 924system.cpu0.l2cache.SCUpgradeReq_misses::total 18449 # number of SCUpgradeReq misses 925system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44897 # number of ReadExReq misses 926system.cpu0.l2cache.ReadExReq_misses::total 44897 # number of ReadExReq misses 927system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 820 # number of demand (read+write) misses 928system.cpu0.l2cache.demand_misses::cpu0.itb.walker 137 # number of demand (read+write) misses 929system.cpu0.l2cache.demand_misses::cpu0.inst 71148 # number of demand (read+write) misses 930system.cpu0.l2cache.demand_misses::cpu0.data 145675 # number of demand (read+write) misses 931system.cpu0.l2cache.demand_misses::total 217780 # number of demand (read+write) misses 932system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 820 # number of overall misses 933system.cpu0.l2cache.overall_misses::cpu0.itb.walker 137 # number of overall misses 934system.cpu0.l2cache.overall_misses::cpu0.inst 71148 # number of overall misses 935system.cpu0.l2cache.overall_misses::cpu0.data 145675 # number of overall misses 936system.cpu0.l2cache.overall_misses::total 217780 # number of overall misses 937system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 28707498 # number of ReadReq miss cycles 938system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3099498 # number of ReadReq miss cycles 939system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 3273175214 # number of ReadReq miss cycles 940system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 3026145651 # number of ReadReq miss cycles 941system.cpu0.l2cache.ReadReq_miss_latency::total 6331127861 # number of ReadReq miss cycles 942system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 497876262 # number of UpgradeReq miss cycles 943system.cpu0.l2cache.UpgradeReq_miss_latency::total 497876262 # number of UpgradeReq miss cycles 944system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 373490824 # number of SCUpgradeReq miss cycles 945system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 373490824 # number of SCUpgradeReq miss cycles 946system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 199000 # number of SCUpgradeFailReq miss cycles 947system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 199000 # number of SCUpgradeFailReq miss cycles 948system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2237004716 # number of ReadExReq miss cycles 949system.cpu0.l2cache.ReadExReq_miss_latency::total 2237004716 # number of ReadExReq miss cycles 950system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 28707498 # number of demand (read+write) miss cycles 951system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3099498 # number of demand (read+write) miss cycles 952system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3273175214 # number of demand (read+write) miss cycles 953system.cpu0.l2cache.demand_miss_latency::cpu0.data 5263150367 # number of demand (read+write) miss cycles 954system.cpu0.l2cache.demand_miss_latency::total 8568132577 # number of demand (read+write) miss cycles 955system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 28707498 # number of overall miss cycles 956system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3099498 # number of overall miss cycles 957system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3273175214 # number of overall miss cycles 958system.cpu0.l2cache.overall_miss_latency::cpu0.data 5263150367 # number of overall miss cycles 959system.cpu0.l2cache.overall_miss_latency::total 8568132577 # number of overall miss cycles 960system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 82367 # number of ReadReq accesses(hits+misses) 961system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4377 # number of ReadReq accesses(hits+misses) 962system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1966814 # number of ReadReq accesses(hits+misses) 963system.cpu0.l2cache.ReadReq_accesses::cpu0.data 501728 # number of ReadReq accesses(hits+misses) 964system.cpu0.l2cache.ReadReq_accesses::total 2555286 # number of ReadReq accesses(hits+misses) 965system.cpu0.l2cache.Writeback_accesses::writebacks 514393 # number of Writeback accesses(hits+misses) 966system.cpu0.l2cache.Writeback_accesses::total 514393 # number of Writeback accesses(hits+misses) 967system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55487 # number of UpgradeReq accesses(hits+misses) 968system.cpu0.l2cache.UpgradeReq_accesses::total 55487 # number of UpgradeReq accesses(hits+misses) 969system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20299 # number of SCUpgradeReq accesses(hits+misses) 970system.cpu0.l2cache.SCUpgradeReq_accesses::total 20299 # number of SCUpgradeReq accesses(hits+misses) 971system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 268392 # number of ReadExReq accesses(hits+misses) 972system.cpu0.l2cache.ReadExReq_accesses::total 268392 # number of ReadExReq accesses(hits+misses) 973system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 82367 # number of demand (read+write) accesses 974system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4377 # number of demand (read+write) accesses 975system.cpu0.l2cache.demand_accesses::cpu0.inst 1966814 # number of demand (read+write) accesses 976system.cpu0.l2cache.demand_accesses::cpu0.data 770120 # number of demand (read+write) accesses 977system.cpu0.l2cache.demand_accesses::total 2823678 # number of demand (read+write) accesses 978system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 82367 # number of overall (read+write) accesses 979system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4377 # number of overall (read+write) accesses 980system.cpu0.l2cache.overall_accesses::cpu0.inst 1966814 # number of overall (read+write) accesses 981system.cpu0.l2cache.overall_accesses::cpu0.data 770120 # number of overall (read+write) accesses 982system.cpu0.l2cache.overall_accesses::total 2823678 # number of overall (read+write) accesses 983system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009955 # miss rate for ReadReq accesses 984system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031300 # miss rate for ReadReq accesses 985system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.036174 # miss rate for ReadReq accesses 986system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.200862 # miss rate for ReadReq accesses 987system.cpu0.l2cache.ReadReq_miss_rate::total 0.067657 # miss rate for ReadReq accesses 988system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.482455 # miss rate for UpgradeReq accesses 989system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.482455 # miss rate for UpgradeReq accesses 990system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.908863 # miss rate for SCUpgradeReq accesses 991system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.908863 # miss rate for SCUpgradeReq accesses 992system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.167281 # miss rate for ReadExReq accesses 993system.cpu0.l2cache.ReadExReq_miss_rate::total 0.167281 # miss rate for ReadExReq accesses 994system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009955 # miss rate for demand accesses 995system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.031300 # miss rate for demand accesses 996system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.036174 # miss rate for demand accesses 997system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.189159 # miss rate for demand accesses 998system.cpu0.l2cache.demand_miss_rate::total 0.077126 # miss rate for demand accesses 999system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009955 # miss rate for overall accesses 1000system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.031300 # miss rate for overall accesses 1001system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.036174 # miss rate for overall accesses 1002system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.189159 # miss rate for overall accesses 1003system.cpu0.l2cache.overall_miss_rate::total 0.077126 # miss rate for overall accesses 1004system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35009.143902 # average ReadReq miss latency 1005system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22624.072993 # average ReadReq miss latency 1006system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46005.161269 # average ReadReq miss latency 1007system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 30027.839915 # average ReadReq miss latency 1008system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36620.881527 # average ReadReq miss latency 1009system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18598.291446 # average UpgradeReq miss latency 1010system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18598.291446 # average UpgradeReq miss latency 1011system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20244.502358 # average SCUpgradeReq miss latency 1012system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20244.502358 # average SCUpgradeReq miss latency | 870system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.351971 # Average percentage of cache occupancy 871system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.118987 # Average percentage of cache occupancy 872system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.099860 # Average percentage of cache occupancy 873system.cpu0.l2cache.tags.occ_percent::total 0.985538 # Average percentage of cache occupancy 874system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1040 # Occupied blocks per task id 875system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id 876system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15197 # Occupied blocks per task id 877system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id 878system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 337 # Occupied blocks per task id 879system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 404 # Occupied blocks per task id 880system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 285 # Occupied blocks per task id 881system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 882system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 883system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 884system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 885system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 886system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id 887system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4113 # Occupied blocks per task id 888system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7946 # Occupied blocks per task id 889system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2792 # Occupied blocks per task id 890system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.063477 # Percentage of cache occupancy per task id 891system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id 892system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.927551 # Percentage of cache occupancy per task id 893system.cpu0.l2cache.tags.tag_accesses 55342545 # Number of tag accesses 894system.cpu0.l2cache.tags.data_accesses 55342545 # Number of data accesses 895system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 81587 # number of ReadReq hits 896system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3892 # number of ReadReq hits 897system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1894938 # number of ReadReq hits 898system.cpu0.l2cache.ReadReq_hits::cpu0.data 403004 # number of ReadReq hits 899system.cpu0.l2cache.ReadReq_hits::total 2383421 # number of ReadReq hits 900system.cpu0.l2cache.Writeback_hits::writebacks 515632 # number of Writeback hits 901system.cpu0.l2cache.Writeback_hits::total 515632 # number of Writeback hits 902system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28611 # number of UpgradeReq hits 903system.cpu0.l2cache.UpgradeReq_hits::total 28611 # number of UpgradeReq hits 904system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1830 # number of SCUpgradeReq hits 905system.cpu0.l2cache.SCUpgradeReq_hits::total 1830 # number of SCUpgradeReq hits 906system.cpu0.l2cache.ReadExReq_hits::cpu0.data 223241 # number of ReadExReq hits 907system.cpu0.l2cache.ReadExReq_hits::total 223241 # number of ReadExReq hits 908system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 81587 # number of demand (read+write) hits 909system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3892 # number of demand (read+write) hits 910system.cpu0.l2cache.demand_hits::cpu0.inst 1894938 # number of demand (read+write) hits 911system.cpu0.l2cache.demand_hits::cpu0.data 626245 # number of demand (read+write) hits 912system.cpu0.l2cache.demand_hits::total 2606662 # number of demand (read+write) hits 913system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 81587 # number of overall hits 914system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3892 # number of overall hits 915system.cpu0.l2cache.overall_hits::cpu0.inst 1894938 # number of overall hits 916system.cpu0.l2cache.overall_hits::cpu0.data 626245 # number of overall hits 917system.cpu0.l2cache.overall_hits::total 2606662 # number of overall hits 918system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 835 # number of ReadReq misses 919system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 121 # number of ReadReq misses 920system.cpu0.l2cache.ReadReq_misses::cpu0.inst 70956 # number of ReadReq misses 921system.cpu0.l2cache.ReadReq_misses::cpu0.data 100469 # number of ReadReq misses 922system.cpu0.l2cache.ReadReq_misses::total 172381 # number of ReadReq misses 923system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26947 # number of UpgradeReq misses 924system.cpu0.l2cache.UpgradeReq_misses::total 26947 # number of UpgradeReq misses 925system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18435 # number of SCUpgradeReq misses 926system.cpu0.l2cache.SCUpgradeReq_misses::total 18435 # number of SCUpgradeReq misses 927system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45449 # number of ReadExReq misses 928system.cpu0.l2cache.ReadExReq_misses::total 45449 # number of ReadExReq misses 929system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 835 # number of demand (read+write) misses 930system.cpu0.l2cache.demand_misses::cpu0.itb.walker 121 # number of demand (read+write) misses 931system.cpu0.l2cache.demand_misses::cpu0.inst 70956 # number of demand (read+write) misses 932system.cpu0.l2cache.demand_misses::cpu0.data 145918 # number of demand (read+write) misses 933system.cpu0.l2cache.demand_misses::total 217830 # number of demand (read+write) misses 934system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 835 # number of overall misses 935system.cpu0.l2cache.overall_misses::cpu0.itb.walker 121 # number of overall misses 936system.cpu0.l2cache.overall_misses::cpu0.inst 70956 # number of overall misses 937system.cpu0.l2cache.overall_misses::cpu0.data 145918 # number of overall misses 938system.cpu0.l2cache.overall_misses::total 217830 # number of overall misses 939system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 28533998 # number of ReadReq miss cycles 940system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2724498 # number of ReadReq miss cycles 941system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 3265841724 # number of ReadReq miss cycles 942system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 3007886164 # number of ReadReq miss cycles 943system.cpu0.l2cache.ReadReq_miss_latency::total 6304986384 # number of ReadReq miss cycles 944system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 501041294 # number of UpgradeReq miss cycles 945system.cpu0.l2cache.UpgradeReq_miss_latency::total 501041294 # number of UpgradeReq miss cycles 946system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 372688311 # number of SCUpgradeReq miss cycles 947system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 372688311 # number of SCUpgradeReq miss cycles 948system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 123500 # number of SCUpgradeFailReq miss cycles 949system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 123500 # number of SCUpgradeFailReq miss cycles 950system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2240726575 # number of ReadExReq miss cycles 951system.cpu0.l2cache.ReadExReq_miss_latency::total 2240726575 # number of ReadExReq miss cycles 952system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 28533998 # number of demand (read+write) miss cycles 953system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2724498 # number of demand (read+write) miss cycles 954system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3265841724 # number of demand (read+write) miss cycles 955system.cpu0.l2cache.demand_miss_latency::cpu0.data 5248612739 # number of demand (read+write) miss cycles 956system.cpu0.l2cache.demand_miss_latency::total 8545712959 # number of demand (read+write) miss cycles 957system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 28533998 # number of overall miss cycles 958system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2724498 # number of overall miss cycles 959system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3265841724 # number of overall miss cycles 960system.cpu0.l2cache.overall_miss_latency::cpu0.data 5248612739 # number of overall miss cycles 961system.cpu0.l2cache.overall_miss_latency::total 8545712959 # number of overall miss cycles 962system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 82422 # number of ReadReq accesses(hits+misses) 963system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4013 # number of ReadReq accesses(hits+misses) 964system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1965894 # number of ReadReq accesses(hits+misses) 965system.cpu0.l2cache.ReadReq_accesses::cpu0.data 503473 # number of ReadReq accesses(hits+misses) 966system.cpu0.l2cache.ReadReq_accesses::total 2555802 # number of ReadReq accesses(hits+misses) 967system.cpu0.l2cache.Writeback_accesses::writebacks 515632 # number of Writeback accesses(hits+misses) 968system.cpu0.l2cache.Writeback_accesses::total 515632 # number of Writeback accesses(hits+misses) 969system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55558 # number of UpgradeReq accesses(hits+misses) 970system.cpu0.l2cache.UpgradeReq_accesses::total 55558 # number of UpgradeReq accesses(hits+misses) 971system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20265 # number of SCUpgradeReq accesses(hits+misses) 972system.cpu0.l2cache.SCUpgradeReq_accesses::total 20265 # number of SCUpgradeReq accesses(hits+misses) 973system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 268690 # number of ReadExReq accesses(hits+misses) 974system.cpu0.l2cache.ReadExReq_accesses::total 268690 # number of ReadExReq accesses(hits+misses) 975system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 82422 # number of demand (read+write) accesses 976system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4013 # number of demand (read+write) accesses 977system.cpu0.l2cache.demand_accesses::cpu0.inst 1965894 # number of demand (read+write) accesses 978system.cpu0.l2cache.demand_accesses::cpu0.data 772163 # number of demand (read+write) accesses 979system.cpu0.l2cache.demand_accesses::total 2824492 # number of demand (read+write) accesses 980system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 82422 # number of overall (read+write) accesses 981system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4013 # number of overall (read+write) accesses 982system.cpu0.l2cache.overall_accesses::cpu0.inst 1965894 # number of overall (read+write) accesses 983system.cpu0.l2cache.overall_accesses::cpu0.data 772163 # number of overall (read+write) accesses 984system.cpu0.l2cache.overall_accesses::total 2824492 # number of overall (read+write) accesses 985system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010131 # miss rate for ReadReq accesses 986system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.030152 # miss rate for ReadReq accesses 987system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.036094 # miss rate for ReadReq accesses 988system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.199552 # miss rate for ReadReq accesses 989system.cpu0.l2cache.ReadReq_miss_rate::total 0.067447 # miss rate for ReadReq accesses 990system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.485025 # miss rate for UpgradeReq accesses 991system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.485025 # miss rate for UpgradeReq accesses 992system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.909697 # miss rate for SCUpgradeReq accesses 993system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.909697 # miss rate for SCUpgradeReq accesses 994system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.169150 # miss rate for ReadExReq accesses 995system.cpu0.l2cache.ReadExReq_miss_rate::total 0.169150 # miss rate for ReadExReq accesses 996system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010131 # miss rate for demand accesses 997system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.030152 # miss rate for demand accesses 998system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.036094 # miss rate for demand accesses 999system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.188973 # miss rate for demand accesses 1000system.cpu0.l2cache.demand_miss_rate::total 0.077122 # miss rate for demand accesses 1001system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010131 # miss rate for overall accesses 1002system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.030152 # miss rate for overall accesses 1003system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.036094 # miss rate for overall accesses 1004system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.188973 # miss rate for overall accesses 1005system.cpu0.l2cache.overall_miss_rate::total 0.077122 # miss rate for overall accesses 1006system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34172.452695 # average ReadReq miss latency 1007system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22516.512397 # average ReadReq miss latency 1008system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46026.294098 # average ReadReq miss latency 1009system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29938.450308 # average ReadReq miss latency 1010system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36575.877759 # average ReadReq miss latency 1011system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18593.583479 # average UpgradeReq miss latency 1012system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18593.583479 # average UpgradeReq miss latency 1013system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20216.344508 # average SCUpgradeReq miss latency 1014system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20216.344508 # average SCUpgradeReq miss latency |
| 1013system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency 1014system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency | 1015system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency 1016system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency |
| 1015system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49825.260396 # average ReadExReq miss latency 1016system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49825.260396 # average ReadExReq miss latency 1017system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35009.143902 # average overall miss latency 1018system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22624.072993 # average overall miss latency 1019system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46005.161269 # average overall miss latency 1020system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36129.400151 # average overall miss latency 1021system.cpu0.l2cache.demand_avg_miss_latency::total 39343.064455 # average overall miss latency 1022system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35009.143902 # average overall miss latency 1023system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22624.072993 # average overall miss latency 1024system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46005.161269 # average overall miss latency 1025system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36129.400151 # average overall miss latency 1026system.cpu0.l2cache.overall_avg_miss_latency::total 39343.064455 # average overall miss latency 1027system.cpu0.l2cache.blocked_cycles::no_mshrs 91 # number of cycles access was blocked | 1017system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49301.999494 # average ReadExReq miss latency 1018system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49301.999494 # average ReadExReq miss latency 1019system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34172.452695 # average overall miss latency 1020system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22516.512397 # average overall miss latency 1021system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46026.294098 # average overall miss latency 1022system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35969.604429 # average overall miss latency 1023system.cpu0.l2cache.demand_avg_miss_latency::total 39231.111229 # average overall miss latency 1024system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34172.452695 # average overall miss latency 1025system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22516.512397 # average overall miss latency 1026system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46026.294098 # average overall miss latency 1027system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35969.604429 # average overall miss latency 1028system.cpu0.l2cache.overall_avg_miss_latency::total 39231.111229 # average overall miss latency 1029system.cpu0.l2cache.blocked_cycles::no_mshrs 33 # number of cycles access was blocked |
| 1028system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1030system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1029system.cpu0.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked | 1031system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked |
| 1030system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1032system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1031system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 30.333333 # average number of cycles each access was blocked | 1033system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 33 # average number of cycles each access was blocked |
| 1032system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1033system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1034system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 1034system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1035system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1036system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 1035system.cpu0.l2cache.writebacks::writebacks 200924 # number of writebacks 1036system.cpu0.l2cache.writebacks::total 200924 # number of writebacks 1037system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 68 # number of ReadReq MSHR hits 1038system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 431 # number of ReadReq MSHR hits 1039system.cpu0.l2cache.ReadReq_mshr_hits::total 499 # number of ReadReq MSHR hits 1040system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3081 # number of ReadExReq MSHR hits 1041system.cpu0.l2cache.ReadExReq_mshr_hits::total 3081 # number of ReadExReq MSHR hits 1042system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 68 # number of demand (read+write) MSHR hits 1043system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3512 # number of demand (read+write) MSHR hits 1044system.cpu0.l2cache.demand_mshr_hits::total 3580 # number of demand (read+write) MSHR hits 1045system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 68 # number of overall MSHR hits 1046system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3512 # number of overall MSHR hits 1047system.cpu0.l2cache.overall_mshr_hits::total 3580 # number of overall MSHR hits 1048system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 820 # number of ReadReq MSHR misses 1049system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 137 # number of ReadReq MSHR misses 1050system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 71080 # number of ReadReq MSHR misses 1051system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 100347 # number of ReadReq MSHR misses 1052system.cpu0.l2cache.ReadReq_mshr_misses::total 172384 # number of ReadReq MSHR misses 1053system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 246966 # number of HardPFReq MSHR misses 1054system.cpu0.l2cache.HardPFReq_mshr_misses::total 246966 # number of HardPFReq MSHR misses 1055system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26770 # number of UpgradeReq MSHR misses 1056system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26770 # number of UpgradeReq MSHR misses 1057system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18449 # number of SCUpgradeReq MSHR misses 1058system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18449 # number of SCUpgradeReq MSHR misses 1059system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41816 # number of ReadExReq MSHR misses 1060system.cpu0.l2cache.ReadExReq_mshr_misses::total 41816 # number of ReadExReq MSHR misses 1061system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 820 # number of demand (read+write) MSHR misses 1062system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 137 # number of demand (read+write) MSHR misses 1063system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 71080 # number of demand (read+write) MSHR misses 1064system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142163 # number of demand (read+write) MSHR misses 1065system.cpu0.l2cache.demand_mshr_misses::total 214200 # number of demand (read+write) MSHR misses 1066system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 820 # number of overall MSHR misses 1067system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 137 # number of overall MSHR misses 1068system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 71080 # number of overall MSHR misses 1069system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142163 # number of overall MSHR misses 1070system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 246966 # number of overall MSHR misses 1071system.cpu0.l2cache.overall_mshr_misses::total 461166 # number of overall MSHR misses | 1037system.cpu0.l2cache.writebacks::writebacks 200378 # number of writebacks 1038system.cpu0.l2cache.writebacks::total 200378 # number of writebacks 1039system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 74 # number of ReadReq MSHR hits 1040system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 391 # number of ReadReq MSHR hits 1041system.cpu0.l2cache.ReadReq_mshr_hits::total 465 # number of ReadReq MSHR hits 1042system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3005 # number of ReadExReq MSHR hits 1043system.cpu0.l2cache.ReadExReq_mshr_hits::total 3005 # number of ReadExReq MSHR hits 1044system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 74 # number of demand (read+write) MSHR hits 1045system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3396 # number of demand (read+write) MSHR hits 1046system.cpu0.l2cache.demand_mshr_hits::total 3470 # number of demand (read+write) MSHR hits 1047system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 74 # number of overall MSHR hits 1048system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3396 # number of overall MSHR hits 1049system.cpu0.l2cache.overall_mshr_hits::total 3470 # number of overall MSHR hits 1050system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 835 # number of ReadReq MSHR misses 1051system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 121 # number of ReadReq MSHR misses 1052system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 70882 # number of ReadReq MSHR misses 1053system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 100078 # number of ReadReq MSHR misses 1054system.cpu0.l2cache.ReadReq_mshr_misses::total 171916 # number of ReadReq MSHR misses 1055system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 245909 # number of HardPFReq MSHR misses 1056system.cpu0.l2cache.HardPFReq_mshr_misses::total 245909 # number of HardPFReq MSHR misses 1057system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26947 # number of UpgradeReq MSHR misses 1058system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26947 # number of UpgradeReq MSHR misses 1059system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18435 # number of SCUpgradeReq MSHR misses 1060system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18435 # number of SCUpgradeReq MSHR misses 1061system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42444 # number of ReadExReq MSHR misses 1062system.cpu0.l2cache.ReadExReq_mshr_misses::total 42444 # number of ReadExReq MSHR misses 1063system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 835 # number of demand (read+write) MSHR misses 1064system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 121 # number of demand (read+write) MSHR misses 1065system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 70882 # number of demand (read+write) MSHR misses 1066system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142522 # number of demand (read+write) MSHR misses 1067system.cpu0.l2cache.demand_mshr_misses::total 214360 # number of demand (read+write) MSHR misses 1068system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 835 # number of overall MSHR misses 1069system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 121 # number of overall MSHR misses 1070system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 70882 # number of overall MSHR misses 1071system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142522 # number of overall MSHR misses 1072system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 245909 # number of overall MSHR misses 1073system.cpu0.l2cache.overall_mshr_misses::total 460269 # number of overall MSHR misses |
| 1072system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3367 # number of ReadReq MSHR uncacheable | 1074system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3367 # number of ReadReq MSHR uncacheable |
| 1073system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20386 # number of ReadReq MSHR uncacheable 1074system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23753 # number of ReadReq MSHR uncacheable 1075system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19085 # number of WriteReq MSHR uncacheable 1076system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19085 # number of WriteReq MSHR uncacheable | 1075system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20388 # number of ReadReq MSHR uncacheable 1076system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23755 # number of ReadReq MSHR uncacheable 1077system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19084 # number of WriteReq MSHR uncacheable 1078system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19084 # number of WriteReq MSHR uncacheable |
| 1077system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3367 # number of overall MSHR uncacheable misses | 1079system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3367 # number of overall MSHR uncacheable misses |
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number of demand (read+write) MSHR miss cycles 1098system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1937000 # number of demand (read+write) MSHR miss cycles 1099system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2794111276 # number of demand (read+write) MSHR miss cycles 1100system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3958365842 # number of demand (read+write) MSHR miss cycles 1101system.cpu0.l2cache.demand_mshr_miss_latency::total 6777505118 # number of demand (read+write) MSHR miss cycles 1102system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 23091000 # number of overall MSHR miss cycles 1103system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1937000 # number of overall MSHR miss cycles 1104system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2794111276 # number of overall MSHR miss cycles 1105system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3958365842 # number of overall MSHR miss cycles 1106system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14425244211 # number of overall MSHR miss cycles 1107system.cpu0.l2cache.overall_mshr_miss_latency::total 21202749329 # number of overall MSHR miss cycles |
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| 1107system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4113041750 # number of ReadReq MSHR uncacheable cycles 1108system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4395186250 # number of ReadReq MSHR uncacheable cycles 1109system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3115835500 # number of WriteReq MSHR uncacheable cycles 1110system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3115835500 # number of WriteReq MSHR uncacheable cycles | 1109system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4115441500 # number of ReadReq MSHR uncacheable cycles 1110system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4397586000 # number of ReadReq MSHR uncacheable cycles 1111system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3115690500 # number of WriteReq MSHR uncacheable cycles 1112system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3115690500 # number of WriteReq MSHR uncacheable cycles |
| 1111system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 282144500 # number of overall MSHR uncacheable cycles | 1113system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 282144500 # number of overall MSHR uncacheable cycles |
| 1112system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7228877250 # number of overall MSHR uncacheable cycles 1113system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7511021750 # number of overall MSHR uncacheable cycles 1114system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009955 # mshr miss rate for ReadReq accesses 1115system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031300 # mshr miss rate for ReadReq accesses 1116system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.036140 # mshr miss rate for ReadReq accesses 1117system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.200003 # mshr miss rate for ReadReq accesses 1118system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.067462 # mshr miss rate for ReadReq accesses | 1114system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7231132000 # number of overall MSHR uncacheable cycles 1115system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7513276500 # number of overall MSHR uncacheable cycles 1116system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010131 # mshr miss rate for ReadReq accesses 1117system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.030152 # mshr miss rate for ReadReq accesses 1118system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.036056 # mshr miss rate for ReadReq accesses 1119system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.198775 # mshr miss rate for ReadReq accesses 1120system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.067265 # mshr miss rate for ReadReq accesses |
| 1119system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1120system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1121system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1122system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1121system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.482455 # mshr miss rate for UpgradeReq accesses 1122system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.482455 # mshr miss rate for UpgradeReq accesses 1123system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.908863 # mshr miss rate for SCUpgradeReq accesses 1124system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.908863 # mshr miss rate for SCUpgradeReq accesses 1125system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155802 # mshr miss rate for ReadExReq accesses 1126system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155802 # mshr miss rate for ReadExReq accesses 1127system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009955 # mshr miss rate for demand accesses 1128system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031300 # mshr miss rate for demand accesses 1129system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036140 # mshr miss rate for demand accesses 1130system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.184599 # mshr miss rate for demand accesses 1131system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075859 # mshr miss rate for demand accesses 1132system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009955 # mshr miss rate for overall accesses 1133system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031300 # mshr miss rate for overall accesses 1134system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036140 # mshr miss rate for overall accesses 1135system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.184599 # mshr miss rate for overall accesses | 1123system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.485025 # mshr miss rate for UpgradeReq accesses 1124system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.485025 # mshr miss rate for UpgradeReq accesses 1125system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.909697 # mshr miss rate for SCUpgradeReq accesses 1126system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.909697 # mshr miss rate for SCUpgradeReq accesses 1127system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.157966 # mshr miss rate for ReadExReq accesses 1128system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.157966 # mshr miss rate for ReadExReq accesses 1129system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010131 # mshr miss rate for demand accesses 1130system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.030152 # mshr miss rate for demand accesses 1131system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036056 # mshr miss rate for demand accesses 1132system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.184575 # mshr miss rate for demand accesses 1133system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075893 # mshr miss rate for demand accesses 1134system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010131 # mshr miss rate for overall accesses 1135system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.030152 # mshr miss rate for overall accesses 1136system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036056 # mshr miss rate for overall accesses 1137system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.184575 # mshr miss rate for overall accesses |
| 1136system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1138system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1137system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163321 # mshr miss rate for overall accesses 1138system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28489.024390 # average ReadReq mshr miss latency 1139system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16116.788321 # average ReadReq mshr miss latency 1140system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39399.870371 # average ReadReq mshr miss latency 1141system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23409.502965 # average ReadReq mshr miss latency 1142system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30021.261718 # average ReadReq mshr miss latency 1143system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58911.725424 # average HardPFReq mshr miss latency 1144system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58911.725424 # average HardPFReq mshr miss latency 1145system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20151.626074 # average UpgradeReq mshr miss latency 1146system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20151.626074 # average UpgradeReq mshr miss latency 1147system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14704.905686 # average SCUpgradeReq mshr miss latency 1148system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14704.905686 # average SCUpgradeReq mshr miss latency | 1139system.cpu0.l2cache.overall_mshr_miss_rate::total 0.162956 # mshr miss rate for overall accesses 1140system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27653.892216 # average ReadReq mshr miss latency 1141system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16008.264463 # average ReadReq mshr miss latency 1142system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39419.193533 # average ReadReq mshr miss latency 1143system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23314.226034 # average ReadReq mshr miss latency 1144system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29970.336612 # average ReadReq mshr miss latency 1145system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58660.903875 # average HardPFReq mshr miss latency 1146system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58660.903875 # average HardPFReq mshr miss latency 1147system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20181.948232 # average UpgradeReq mshr miss latency 1148system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20181.948232 # average UpgradeReq mshr miss latency 1149system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14672.081530 # average SCUpgradeReq mshr miss latency 1150system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14672.081530 # average SCUpgradeReq mshr miss latency |
| 1149system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency 1150system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency | 1151system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency 1152system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency |
| 1151system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38572.902454 # average ReadExReq mshr miss latency 1152system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38572.902454 # average ReadExReq mshr miss latency 1153system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28489.024390 # average overall mshr miss latency 1154system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16116.788321 # average overall mshr miss latency 1155system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39399.870371 # average overall mshr miss latency 1156system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27869.683975 # average overall mshr miss latency 1157system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31690.708072 # average overall mshr miss latency 1158system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28489.024390 # average overall mshr miss latency 1159system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16116.788321 # average overall mshr miss latency 1160system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39399.870371 # average overall mshr miss latency 1161system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27869.683975 # average overall mshr miss latency 1162system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58911.725424 # average overall mshr miss latency 1163system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46268.247984 # average overall mshr miss latency | 1153system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38288.679884 # average ReadExReq mshr miss latency 1154system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38288.679884 # average ReadExReq mshr miss latency 1155system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27653.892216 # average overall mshr miss latency 1156system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16008.264463 # average overall mshr miss latency 1157system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39419.193533 # average overall mshr miss latency 1158system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27773.718037 # average overall mshr miss latency 1159system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31617.396520 # average overall mshr miss latency 1160system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27653.892216 # average overall mshr miss latency 1161system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16008.264463 # average overall mshr miss latency 1162system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39419.193533 # average overall mshr miss latency 1163system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27773.718037 # average overall mshr miss latency 1164system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58660.903875 # average overall mshr miss latency 1165system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46065.994731 # average overall mshr miss latency |
| 1164system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average ReadReq mshr uncacheable latency | 1166system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average ReadReq mshr uncacheable latency |
| 1165system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201758.155106 # average ReadReq mshr uncacheable latency 1166system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185037.100577 # average ReadReq mshr uncacheable latency 1167system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163260.964108 # average WriteReq mshr uncacheable latency 1168system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163260.964108 # average WriteReq mshr uncacheable latency | 1167system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201856.067294 # average ReadReq mshr uncacheable latency 1168system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185122.542623 # average ReadReq mshr uncacheable latency 1169system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163261.920981 # average WriteReq mshr uncacheable latency 1170system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163261.920981 # average WriteReq mshr uncacheable latency |
| 1169system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average overall mshr uncacheable latency | 1171system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average overall mshr uncacheable latency |
| 1170system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183144.010793 # average overall mshr uncacheable latency 1171system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 175335.490686 # average overall mshr uncacheable latency | 1172system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183196.493717 # average overall mshr uncacheable latency 1173system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 175384.030906 # average overall mshr uncacheable latency |
| 1172system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1174system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1173system.cpu0.toL2Bus.trans_dist::ReadReq 2715743 # Transaction distribution 1174system.cpu0.toL2Bus.trans_dist::ReadResp 2641226 # Transaction distribution 1175system.cpu0.toL2Bus.trans_dist::WriteReq 31021 # Transaction distribution 1176system.cpu0.toL2Bus.trans_dist::WriteResp 19085 # Transaction distribution 1177system.cpu0.toL2Bus.trans_dist::Writeback 514393 # Transaction distribution 1178system.cpu0.toL2Bus.trans_dist::HardPFReq 305303 # Transaction distribution 1179system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution 1180system.cpu0.toL2Bus.trans_dist::UpgradeReq 89358 # Transaction distribution 1181system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43016 # Transaction distribution 1182system.cpu0.toL2Bus.trans_dist::UpgradeResp 112820 # Transaction distribution 1183system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution 1184system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 16 # Transaction distribution 1185system.cpu0.toL2Bus.trans_dist::ReadExReq 297586 # Transaction distribution 1186system.cpu0.toL2Bus.trans_dist::ReadExResp 284185 # Transaction distribution 1187system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3940361 # Packet count per connected master and slave (bytes) 1188system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2387083 # Packet count per connected master and slave (bytes) 1189system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11736 # Packet count per connected master and slave (bytes) 1190system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 174847 # Packet count per connected master and slave (bytes) 1191system.cpu0.toL2Bus.pkt_count::total 6514027 # Packet count per connected master and slave (bytes) 1192system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126091520 # Cumulative packet size per connected master and slave (bytes) 1193system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86470884 # Cumulative packet size per connected master and slave (bytes) 1194system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17508 # Cumulative packet size per connected master and slave (bytes) 1195system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 329468 # Cumulative packet size per connected master and slave (bytes) 1196system.cpu0.toL2Bus.pkt_size::total 212909380 # Cumulative packet size per connected master and slave (bytes) 1197system.cpu0.toL2Bus.snoops 677925 # Total snoops (count) 1198system.cpu0.toL2Bus.snoop_fanout::samples 4032687 # Request fanout histogram 1199system.cpu0.toL2Bus.snoop_fanout::mean 1.164340 # Request fanout histogram 1200system.cpu0.toL2Bus.snoop_fanout::stdev 0.370584 # Request fanout histogram | 1175system.cpu0.toL2Bus.trans_dist::ReadReq 2719039 # Transaction distribution 1176system.cpu0.toL2Bus.trans_dist::ReadResp 2643816 # Transaction distribution 1177system.cpu0.toL2Bus.trans_dist::WriteReq 31019 # Transaction distribution 1178system.cpu0.toL2Bus.trans_dist::WriteResp 19084 # Transaction distribution 1179system.cpu0.toL2Bus.trans_dist::Writeback 515632 # Transaction distribution 1180system.cpu0.toL2Bus.trans_dist::HardPFReq 304029 # Transaction distribution 1181system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36259 # Transaction distribution 1182system.cpu0.toL2Bus.trans_dist::UpgradeReq 89544 # Transaction distribution 1183system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42988 # Transaction distribution 1184system.cpu0.toL2Bus.trans_dist::UpgradeResp 112734 # Transaction distribution 1185system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution 1186system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution 1187system.cpu0.toL2Bus.trans_dist::ReadExReq 297842 # Transaction distribution 1188system.cpu0.toL2Bus.trans_dist::ReadExResp 284446 # Transaction distribution 1189system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3938521 # Packet count per connected master and slave (bytes) 1190system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2392407 # Packet count per connected master and slave (bytes) 1191system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11394 # Packet count per connected master and slave (bytes) 1192system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 176554 # Packet count per connected master and slave (bytes) 1193system.cpu0.toL2Bus.pkt_count::total 6518876 # Packet count per connected master and slave (bytes) 1194system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126032640 # Cumulative packet size per connected master and slave (bytes) 1195system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86683880 # Cumulative packet size per connected master and slave (bytes) 1196system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 16052 # Cumulative packet size per connected master and slave (bytes) 1197system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 329688 # Cumulative packet size per connected master and slave (bytes) 1198system.cpu0.toL2Bus.pkt_size::total 213062260 # Cumulative packet size per connected master and slave (bytes) 1199system.cpu0.toL2Bus.snoops 679431 # Total snoops (count) 1200system.cpu0.toL2Bus.snoop_fanout::samples 4036359 # Request fanout histogram 1201system.cpu0.toL2Bus.snoop_fanout::mean 1.164506 # Request fanout histogram 1202system.cpu0.toL2Bus.snoop_fanout::stdev 0.370735 # Request fanout histogram |
| 1201system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1202system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1203system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1204system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1203system.cpu0.toL2Bus.snoop_fanout::1 3369954 83.57% 83.57% # Request fanout histogram 1204system.cpu0.toL2Bus.snoop_fanout::2 662733 16.43% 100.00% # Request fanout histogram | 1205system.cpu0.toL2Bus.snoop_fanout::1 3372352 83.55% 83.55% # Request fanout histogram 1206system.cpu0.toL2Bus.snoop_fanout::2 664007 16.45% 100.00% # Request fanout histogram |
| 1205system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1206system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1207system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1207system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1208system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1209system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1208system.cpu0.toL2Bus.snoop_fanout::total 4032687 # Request fanout histogram 1209system.cpu0.toL2Bus.reqLayer0.occupancy 2258839735 # Layer occupancy (ticks) | 1210system.cpu0.toL2Bus.snoop_fanout::total 4036359 # Request fanout histogram 1211system.cpu0.toL2Bus.reqLayer0.occupancy 2262112239 # Layer occupancy (ticks) |
| 1210system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1212system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1211system.cpu0.toL2Bus.snoopLayer0.occupancy 115861999 # Layer occupancy (ticks) | 1213system.cpu0.toL2Bus.snoopLayer0.occupancy 115872000 # Layer occupancy (ticks) |
| 1212system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1214system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1213system.cpu0.toL2Bus.respLayer0.occupancy 2960687293 # Layer occupancy (ticks) | 1215system.cpu0.toL2Bus.respLayer0.occupancy 2959359198 # Layer occupancy (ticks) |
| 1214system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1216system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1215system.cpu0.toL2Bus.respLayer1.occupancy 1231161241 # Layer occupancy (ticks) | 1217system.cpu0.toL2Bus.respLayer1.occupancy 1234268849 # Layer occupancy (ticks) |
| 1216system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1218system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1217system.cpu0.toL2Bus.respLayer2.occupancy 7364989 # Layer occupancy (ticks) | 1219system.cpu0.toL2Bus.respLayer2.occupancy 7386992 # Layer occupancy (ticks) |
| 1218system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1220system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1219system.cpu0.toL2Bus.respLayer3.occupancy 92493743 # Layer occupancy (ticks) | 1221system.cpu0.toL2Bus.respLayer3.occupancy 94142746 # Layer occupancy (ticks) |
| 1220system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1222system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1221system.cpu1.branchPred.lookups 18540788 # Number of BP lookups 1222system.cpu1.branchPred.condPredicted 6039472 # Number of conditional branches predicted 1223system.cpu1.branchPred.condIncorrect 931744 # Number of conditional branches incorrect 1224system.cpu1.branchPred.BTBLookups 9588411 # Number of BTB lookups 1225system.cpu1.branchPred.BTBHits 6940637 # Number of BTB hits | 1223system.cpu1.branchPred.lookups 19410315 # Number of BP lookups 1224system.cpu1.branchPred.condPredicted 6222605 # Number of conditional branches predicted 1225system.cpu1.branchPred.condIncorrect 754773 # Number of conditional branches incorrect 1226system.cpu1.branchPred.BTBLookups 10046576 # Number of BTB lookups 1227system.cpu1.branchPred.BTBHits 7244167 # Number of BTB hits |
| 1226system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1228system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1227system.cpu1.branchPred.BTBHitPct 72.385685 # BTB Hit Percentage 1228system.cpu1.branchPred.usedRAS 8266914 # Number of times the RAS was used to get a target. 1229system.cpu1.branchPred.RASInCorrect 716215 # Number of incorrect RAS predictions. | 1229system.cpu1.branchPred.BTBHitPct 72.105830 # BTB Hit Percentage 1230system.cpu1.branchPred.usedRAS 8699318 # Number of times the RAS was used to get a target. 1231system.cpu1.branchPred.RASInCorrect 540404 # Number of incorrect RAS predictions. |
| 1230system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1231system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1232system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1233system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1234system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1235system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1236system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1237system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1251system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1252system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1253system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1254system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1255system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1256system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1257system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1258system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1232system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1233system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1234system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1235system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1236system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1237system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1238system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1239system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1253system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1254system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1255system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1256system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1257system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1258system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1259system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1260system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1259system.cpu1.dtb.walker.walks 26399 # Table walker walks requested 1260system.cpu1.dtb.walker.walksShort 26399 # Table walker walks initiated with short descriptors 1261system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19296 # Level at which table walker walks with short descriptors terminate 1262system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7103 # Level at which table walker walks with short descriptors terminate 1263system.cpu1.dtb.walker.walkWaitTime::samples 26399 # Table walker wait (enqueue to first request) latency 1264system.cpu1.dtb.walker.walkWaitTime::0 26399 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1265system.cpu1.dtb.walker.walkWaitTime::total 26399 # Table walker wait (enqueue to first request) latency 1266system.cpu1.dtb.walker.walkCompletionTime::samples 2728 # Table walker service (enqueue to completion) latency 1267system.cpu1.dtb.walker.walkCompletionTime::mean 9779.693548 # Table walker service (enqueue to completion) latency 1268system.cpu1.dtb.walker.walkCompletionTime::gmean 8843.591627 # Table walker service (enqueue to completion) latency 1269system.cpu1.dtb.walker.walkCompletionTime::stdev 5628.626467 # Table walker service (enqueue to completion) latency 1270system.cpu1.dtb.walker.walkCompletionTime::0-8191 924 33.87% 33.87% # Table walker service (enqueue to completion) latency 1271system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1671 61.25% 95.12% # Table walker service (enqueue to completion) latency 1272system.cpu1.dtb.walker.walkCompletionTime::16384-24575 66 2.42% 97.54% # Table walker service (enqueue to completion) latency 1273system.cpu1.dtb.walker.walkCompletionTime::24576-32767 58 2.13% 99.67% # Table walker service (enqueue to completion) latency 1274system.cpu1.dtb.walker.walkCompletionTime::32768-40959 1 0.04% 99.71% # Table walker service (enqueue to completion) latency 1275system.cpu1.dtb.walker.walkCompletionTime::40960-49151 5 0.18% 99.89% # Table walker service (enqueue to completion) latency 1276system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.04% 99.93% # Table walker service (enqueue to completion) latency 1277system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 99.96% # Table walker service (enqueue to completion) latency | 1261system.cpu1.dtb.walker.walks 26225 # Table walker walks requested 1262system.cpu1.dtb.walker.walksShort 26225 # Table walker walks initiated with short descriptors 1263system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19144 # Level at which table walker walks with short descriptors terminate 1264system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7081 # Level at which table walker walks with short descriptors terminate 1265system.cpu1.dtb.walker.walkWaitTime::samples 26225 # Table walker wait (enqueue to first request) latency 1266system.cpu1.dtb.walker.walkWaitTime::0 26225 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1267system.cpu1.dtb.walker.walkWaitTime::total 26225 # Table walker wait (enqueue to first request) latency 1268system.cpu1.dtb.walker.walkCompletionTime::samples 2726 # Table walker service (enqueue to completion) latency 1269system.cpu1.dtb.walker.walkCompletionTime::mean 9368.766324 # Table walker service (enqueue to completion) latency 1270system.cpu1.dtb.walker.walkCompletionTime::gmean 8408.351420 # Table walker service (enqueue to completion) latency 1271system.cpu1.dtb.walker.walkCompletionTime::stdev 5475.622761 # Table walker service (enqueue to completion) latency 1272system.cpu1.dtb.walker.walkCompletionTime::0-8191 1046 38.37% 38.37% # Table walker service (enqueue to completion) latency 1273system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1544 56.64% 95.01% # Table walker service (enqueue to completion) latency 1274system.cpu1.dtb.walker.walkCompletionTime::16384-24575 68 2.49% 97.51% # Table walker service (enqueue to completion) latency 1275system.cpu1.dtb.walker.walkCompletionTime::24576-32767 59 2.16% 99.67% # Table walker service (enqueue to completion) latency 1276system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.74% # Table walker service (enqueue to completion) latency 1277system.cpu1.dtb.walker.walkCompletionTime::40960-49151 5 0.18% 99.93% # Table walker service (enqueue to completion) latency 1278system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency |
| 1278system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency | 1279system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency |
| 1279system.cpu1.dtb.walker.walkCompletionTime::total 2728 # Table walker service (enqueue to completion) latency 1280system.cpu1.dtb.walker.walksPending::samples 1622643264 # Table walker pending requests distribution 1281system.cpu1.dtb.walker.walksPending::0 1622643264 100.00% 100.00% # Table walker pending requests distribution 1282system.cpu1.dtb.walker.walksPending::total 1622643264 # Table walker pending requests distribution 1283system.cpu1.dtb.walker.walkPageSizes::4K 2007 73.57% 73.57% # Table walker page sizes translated 1284system.cpu1.dtb.walker.walkPageSizes::1M 721 26.43% 100.00% # Table walker page sizes translated 1285system.cpu1.dtb.walker.walkPageSizes::total 2728 # Table walker page sizes translated 1286system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26399 # Table walker requests started/completed, data/inst | 1280system.cpu1.dtb.walker.walkCompletionTime::total 2726 # Table walker service (enqueue to completion) latency 1281system.cpu1.dtb.walker.walksPending::samples 1584726764 # Table walker pending requests distribution 1282system.cpu1.dtb.walker.walksPending::0 1584726764 100.00% 100.00% # Table walker pending requests distribution 1283system.cpu1.dtb.walker.walksPending::total 1584726764 # Table walker pending requests distribution 1284system.cpu1.dtb.walker.walkPageSizes::4K 2009 73.70% 73.70% # Table walker page sizes translated 1285system.cpu1.dtb.walker.walkPageSizes::1M 717 26.30% 100.00% # Table walker page sizes translated 1286system.cpu1.dtb.walker.walkPageSizes::total 2726 # Table walker page sizes translated 1287system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26225 # Table walker requests started/completed, data/inst |
| 1287system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 1288system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 1288system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26399 # Table walker requests started/completed, data/inst 1289system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2728 # Table walker requests started/completed, data/inst | 1289system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26225 # Table walker requests started/completed, data/inst 1290system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2726 # Table walker requests started/completed, data/inst |
| 1290system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 1291system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 1291system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2728 # Table walker requests started/completed, data/inst 1292system.cpu1.dtb.walker.walkRequestOrigin::total 29127 # Table walker requests started/completed, data/inst | 1292system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2726 # Table walker requests started/completed, data/inst 1293system.cpu1.dtb.walker.walkRequestOrigin::total 28951 # Table walker requests started/completed, data/inst |
| 1293system.cpu1.dtb.inst_hits 0 # ITB inst hits 1294system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1294system.cpu1.dtb.inst_hits 0 # ITB inst hits 1295system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1295system.cpu1.dtb.read_hits 10801915 # DTB read hits 1296system.cpu1.dtb.read_misses 24746 # DTB read misses 1297system.cpu1.dtb.write_hits 6805241 # DTB write hits 1298system.cpu1.dtb.write_misses 1653 # DTB write misses | 1296system.cpu1.dtb.read_hits 11340769 # DTB read hits 1297system.cpu1.dtb.read_misses 24844 # DTB read misses 1298system.cpu1.dtb.write_hits 7074140 # DTB write hits 1299system.cpu1.dtb.write_misses 1381 # DTB write misses |
| 1299system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1300system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1301system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1302system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1303system.cpu1.dtb.flush_entries 2067 # Number of entries that have been flushed from TLB | 1300system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1301system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1302system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1303system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1304system.cpu1.dtb.flush_entries 2067 # Number of entries that have been flushed from TLB |
| 1304system.cpu1.dtb.align_faults 156 # Number of TLB faults due to alignment restrictions 1305system.cpu1.dtb.prefetch_faults 413 # Number of TLB faults due to prefetch | 1305system.cpu1.dtb.align_faults 202 # Number of TLB faults due to alignment restrictions 1306system.cpu1.dtb.prefetch_faults 452 # Number of TLB faults due to prefetch |
| 1306system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1307system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1307system.cpu1.dtb.perms_faults 271 # Number of TLB faults due to permissions restrictions 1308system.cpu1.dtb.read_accesses 10826661 # DTB read accesses 1309system.cpu1.dtb.write_accesses 6806894 # DTB write accesses | 1308system.cpu1.dtb.perms_faults 283 # Number of TLB faults due to permissions restrictions 1309system.cpu1.dtb.read_accesses 11365613 # DTB read accesses 1310system.cpu1.dtb.write_accesses 7075521 # DTB write accesses |
| 1310system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1311system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1311system.cpu1.dtb.hits 17607156 # DTB hits 1312system.cpu1.dtb.misses 26399 # DTB misses 1313system.cpu1.dtb.accesses 17633555 # DTB accesses | 1312system.cpu1.dtb.hits 18414909 # DTB hits 1313system.cpu1.dtb.misses 26225 # DTB misses 1314system.cpu1.dtb.accesses 18441134 # DTB accesses |
| 1314system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1315system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1316system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1317system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1318system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1319system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1320system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1321system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 20 unchanged lines hidden (view full) --- 1342system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1343system.cpu1.itb.walker.walks 2259 # Table walker walks requested 1344system.cpu1.itb.walker.walksShort 2259 # Table walker walks initiated with short descriptors 1345system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate 1346system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2078 # Level at which table walker walks with short descriptors terminate 1347system.cpu1.itb.walker.walkWaitTime::samples 2259 # Table walker wait (enqueue to first request) latency 1348system.cpu1.itb.walker.walkWaitTime::0 2259 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1349system.cpu1.itb.walker.walkWaitTime::total 2259 # Table walker wait (enqueue to first request) latency | 1315system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1316system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1317system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1318system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1319system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1320system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1321system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1322system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 20 unchanged lines hidden (view full) --- 1343system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1344system.cpu1.itb.walker.walks 2259 # Table walker walks requested 1345system.cpu1.itb.walker.walksShort 2259 # Table walker walks initiated with short descriptors 1346system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate 1347system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2078 # Level at which table walker walks with short descriptors terminate 1348system.cpu1.itb.walker.walkWaitTime::samples 2259 # Table walker wait (enqueue to first request) latency 1349system.cpu1.itb.walker.walkWaitTime::0 2259 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1350system.cpu1.itb.walker.walkWaitTime::total 2259 # Table walker wait (enqueue to first request) latency |
| 1350system.cpu1.itb.walker.walkCompletionTime::samples 1119 # Table walker service (enqueue to completion) latency 1351system.cpu1.itb.walker.walkCompletionTime::mean 9888.739946 # Table walker service (enqueue to completion) latency 1352system.cpu1.itb.walker.walkCompletionTime::gmean 9049.592552 # Table walker service (enqueue to completion) latency 1353system.cpu1.itb.walker.walkCompletionTime::stdev 4688.260195 # Table walker service (enqueue to completion) latency 1354system.cpu1.itb.walker.walkCompletionTime::0-4095 127 11.35% 11.35% # Table walker service (enqueue to completion) latency 1355system.cpu1.itb.walker.walkCompletionTime::4096-8191 167 14.92% 26.27% # Table walker service (enqueue to completion) latency 1356system.cpu1.itb.walker.walkCompletionTime::8192-12287 537 47.99% 74.26% # Table walker service (enqueue to completion) latency 1357system.cpu1.itb.walker.walkCompletionTime::12288-16383 253 22.61% 96.87% # Table walker service (enqueue to completion) latency 1358system.cpu1.itb.walker.walkCompletionTime::16384-20479 2 0.18% 97.05% # Table walker service (enqueue to completion) latency 1359system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.27% 97.32% # Table walker service (enqueue to completion) latency 1360system.cpu1.itb.walker.walkCompletionTime::24576-28671 16 1.43% 98.75% # Table walker service (enqueue to completion) latency 1361system.cpu1.itb.walker.walkCompletionTime::28672-32767 11 0.98% 99.73% # Table walker service (enqueue to completion) latency 1362system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 99.91% # Table walker service (enqueue to completion) latency 1363system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency 1364system.cpu1.itb.walker.walkCompletionTime::total 1119 # Table walker service (enqueue to completion) latency 1365system.cpu1.itb.walker.walksPending::samples 1622052264 # Table walker pending requests distribution 1366system.cpu1.itb.walker.walksPending::0 1622052264 100.00% 100.00% # Table walker pending requests distribution 1367system.cpu1.itb.walker.walksPending::total 1622052264 # Table walker pending requests distribution 1368system.cpu1.itb.walker.walkPageSizes::4K 951 84.99% 84.99% # Table walker page sizes translated 1369system.cpu1.itb.walker.walkPageSizes::1M 168 15.01% 100.00% # Table walker page sizes translated 1370system.cpu1.itb.walker.walkPageSizes::total 1119 # Table walker page sizes translated | 1351system.cpu1.itb.walker.walkCompletionTime::samples 1118 # Table walker service (enqueue to completion) latency 1352system.cpu1.itb.walker.walkCompletionTime::mean 9560.375671 # Table walker service (enqueue to completion) latency 1353system.cpu1.itb.walker.walkCompletionTime::gmean 8643.967571 # Table walker service (enqueue to completion) latency 1354system.cpu1.itb.walker.walkCompletionTime::stdev 4716.413998 # Table walker service (enqueue to completion) latency 1355system.cpu1.itb.walker.walkCompletionTime::0-4095 181 16.19% 16.19% # Table walker service (enqueue to completion) latency 1356system.cpu1.itb.walker.walkCompletionTime::4096-8191 171 15.30% 31.48% # Table walker service (enqueue to completion) latency 1357system.cpu1.itb.walker.walkCompletionTime::8192-12287 489 43.74% 75.22% # Table walker service (enqueue to completion) latency 1358system.cpu1.itb.walker.walkCompletionTime::12288-16383 245 21.91% 97.14% # Table walker service (enqueue to completion) latency 1359system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 97.23% # Table walker service (enqueue to completion) latency 1360system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 1.34% 98.57% # Table walker service (enqueue to completion) latency 1361system.cpu1.itb.walker.walkCompletionTime::28672-32767 14 1.25% 99.82% # Table walker service (enqueue to completion) latency 1362system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.91% # Table walker service (enqueue to completion) latency 1363system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 100.00% # Table walker service (enqueue to completion) latency 1364system.cpu1.itb.walker.walkCompletionTime::total 1118 # Table walker service (enqueue to completion) latency 1365system.cpu1.itb.walker.walksPending::samples 1584152264 # Table walker pending requests distribution 1366system.cpu1.itb.walker.walksPending::0 1584152264 100.00% 100.00% # Table walker pending requests distribution 1367system.cpu1.itb.walker.walksPending::total 1584152264 # Table walker pending requests distribution 1368system.cpu1.itb.walker.walkPageSizes::4K 950 84.97% 84.97% # Table walker page sizes translated 1369system.cpu1.itb.walker.walkPageSizes::1M 168 15.03% 100.00% # Table walker page sizes translated 1370system.cpu1.itb.walker.walkPageSizes::total 1118 # Table walker page sizes translated |
| 1371system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1372system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2259 # Table walker requests started/completed, data/inst 1373system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2259 # Table walker requests started/completed, data/inst 1374system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 1371system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1372system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2259 # Table walker requests started/completed, data/inst 1373system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2259 # Table walker requests started/completed, data/inst 1374system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 1375system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1119 # Table walker requests started/completed, data/inst 1376system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1119 # Table walker requests started/completed, data/inst 1377system.cpu1.itb.walker.walkRequestOrigin::total 3378 # Table walker requests started/completed, data/inst 1378system.cpu1.itb.inst_hits 39782626 # ITB inst hits | 1375system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1118 # Table walker requests started/completed, data/inst 1376system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1118 # Table walker requests started/completed, data/inst 1377system.cpu1.itb.walker.walkRequestOrigin::total 3377 # Table walker requests started/completed, data/inst 1378system.cpu1.itb.inst_hits 39752348 # ITB inst hits |
| 1379system.cpu1.itb.inst_misses 2259 # ITB inst misses 1380system.cpu1.itb.read_hits 0 # DTB read hits 1381system.cpu1.itb.read_misses 0 # DTB read misses 1382system.cpu1.itb.write_hits 0 # DTB write hits 1383system.cpu1.itb.write_misses 0 # DTB write misses 1384system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1385system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1386system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1387system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1379system.cpu1.itb.inst_misses 2259 # ITB inst misses 1380system.cpu1.itb.read_hits 0 # DTB read hits 1381system.cpu1.itb.read_misses 0 # DTB read misses 1382system.cpu1.itb.write_hits 0 # DTB write hits 1383system.cpu1.itb.write_misses 0 # DTB write misses 1384system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1385system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1386system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1387system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1388system.cpu1.itb.flush_entries 1157 # Number of entries that have been flushed from TLB | 1388system.cpu1.itb.flush_entries 1156 # Number of entries that have been flushed from TLB |
| 1389system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1390system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1391system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1389system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1390system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1391system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1392system.cpu1.itb.perms_faults 1864 # Number of TLB faults due to permissions restrictions | 1392system.cpu1.itb.perms_faults 1892 # Number of TLB faults due to permissions restrictions |
| 1393system.cpu1.itb.read_accesses 0 # DTB read accesses 1394system.cpu1.itb.write_accesses 0 # DTB write accesses | 1393system.cpu1.itb.read_accesses 0 # DTB read accesses 1394system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1395system.cpu1.itb.inst_accesses 39784885 # ITB inst accesses 1396system.cpu1.itb.hits 39782626 # DTB hits | 1395system.cpu1.itb.inst_accesses 39754607 # ITB inst accesses 1396system.cpu1.itb.hits 39752348 # DTB hits |
| 1397system.cpu1.itb.misses 2259 # DTB misses | 1397system.cpu1.itb.misses 2259 # DTB misses |
| 1398system.cpu1.itb.accesses 39784885 # DTB accesses 1399system.cpu1.numCycles 114626006 # number of cpu cycles simulated | 1398system.cpu1.itb.accesses 39754607 # DTB accesses 1399system.cpu1.numCycles 114648497 # number of cpu cycles simulated |
| 1400system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1401system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1400system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1401system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1402system.cpu1.committedInsts 45881817 # Number of instructions committed 1403system.cpu1.committedOps 56143289 # Number of ops (including micro ops) committed 1404system.cpu1.discardedOps 4843481 # Number of ops (including micro ops) which were discarded before commit 1405system.cpu1.numFetchSuspends 2780 # Number of times Execute suspended instruction fetching 1406system.cpu1.quiesceCycles 5576973220 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1407system.cpu1.cpi 2.498288 # CPI: cycles per instruction 1408system.cpu1.ipc 0.400274 # IPC: instructions per cycle | 1402system.cpu1.committedInsts 48281933 # Number of instructions committed 1403system.cpu1.committedOps 59077199 # Number of ops (including micro ops) committed 1404system.cpu1.discardedOps 5147990 # Number of ops (including micro ops) which were discarded before commit 1405system.cpu1.numFetchSuspends 2790 # Number of times Execute suspended instruction fetching 1406system.cpu1.quiesceCycles 5576811814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1407system.cpu1.cpi 2.374563 # CPI: cycles per instruction 1408system.cpu1.ipc 0.421130 # IPC: instructions per cycle |
| 1409system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1409system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1410system.cpu1.kern.inst.quiesce 2782 # number of quiesce instructions executed 1411system.cpu1.tickCycles 97881179 # Number of cycles that the object actually ticked 1412system.cpu1.idleCycles 16744827 # Total number of cycles that the object has spent stopped 1413system.cpu1.dcache.tags.replacements 194211 # number of replacements 1414system.cpu1.dcache.tags.tagsinuse 472.569028 # Cycle average of tags in use 1415system.cpu1.dcache.tags.total_refs 17169326 # Total number of references to valid blocks. 1416system.cpu1.dcache.tags.sampled_refs 194582 # Sample count of references to valid blocks. 1417system.cpu1.dcache.tags.avg_refs 88.236970 # Average number of references to valid blocks. 1418system.cpu1.dcache.tags.warmup_cycle 90524286500 # Cycle when the warmup percentage was hit. 1419system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.569028 # Average occupied blocks per requestor 1420system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922986 # Average percentage of cache occupancy 1421system.cpu1.dcache.tags.occ_percent::total 0.922986 # Average percentage of cache occupancy 1422system.cpu1.dcache.tags.occ_task_id_blocks::1024 371 # Occupied blocks per task id 1423system.cpu1.dcache.tags.age_task_id_blocks_1024::2 322 # Occupied blocks per task id 1424system.cpu1.dcache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id 1425system.cpu1.dcache.tags.occ_task_id_percent::1024 0.724609 # Percentage of cache occupancy per task id 1426system.cpu1.dcache.tags.tag_accesses 35245180 # Number of tag accesses 1427system.cpu1.dcache.tags.data_accesses 35245180 # Number of data accesses 1428system.cpu1.dcache.ReadReq_hits::cpu1.data 10415746 # number of ReadReq hits 1429system.cpu1.dcache.ReadReq_hits::total 10415746 # number of ReadReq hits 1430system.cpu1.dcache.WriteReq_hits::cpu1.data 6512410 # number of WriteReq hits 1431system.cpu1.dcache.WriteReq_hits::total 6512410 # number of WriteReq hits 1432system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50058 # number of SoftPFReq hits 1433system.cpu1.dcache.SoftPFReq_hits::total 50058 # number of SoftPFReq hits 1434system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80074 # number of LoadLockedReq hits 1435system.cpu1.dcache.LoadLockedReq_hits::total 80074 # number of LoadLockedReq hits 1436system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71526 # number of StoreCondReq hits 1437system.cpu1.dcache.StoreCondReq_hits::total 71526 # number of StoreCondReq hits 1438system.cpu1.dcache.demand_hits::cpu1.data 16928156 # number of demand (read+write) hits 1439system.cpu1.dcache.demand_hits::total 16928156 # number of demand (read+write) hits 1440system.cpu1.dcache.overall_hits::cpu1.data 16978214 # number of overall hits 1441system.cpu1.dcache.overall_hits::total 16978214 # number of overall hits 1442system.cpu1.dcache.ReadReq_misses::cpu1.data 157191 # number of ReadReq misses 1443system.cpu1.dcache.ReadReq_misses::total 157191 # number of ReadReq misses 1444system.cpu1.dcache.WriteReq_misses::cpu1.data 144867 # number of WriteReq misses 1445system.cpu1.dcache.WriteReq_misses::total 144867 # number of WriteReq misses 1446system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30819 # number of SoftPFReq misses 1447system.cpu1.dcache.SoftPFReq_misses::total 30819 # number of SoftPFReq misses 1448system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16921 # number of LoadLockedReq misses 1449system.cpu1.dcache.LoadLockedReq_misses::total 16921 # number of LoadLockedReq misses 1450system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23675 # number of StoreCondReq misses 1451system.cpu1.dcache.StoreCondReq_misses::total 23675 # number of StoreCondReq misses 1452system.cpu1.dcache.demand_misses::cpu1.data 302058 # number of demand (read+write) misses 1453system.cpu1.dcache.demand_misses::total 302058 # number of demand (read+write) misses 1454system.cpu1.dcache.overall_misses::cpu1.data 332877 # number of overall misses 1455system.cpu1.dcache.overall_misses::total 332877 # number of overall misses 1456system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2309301217 # number of ReadReq miss cycles 1457system.cpu1.dcache.ReadReq_miss_latency::total 2309301217 # number of ReadReq miss cycles 1458system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3857781581 # number of WriteReq miss cycles 1459system.cpu1.dcache.WriteReq_miss_latency::total 3857781581 # number of WriteReq miss cycles 1460system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 316145498 # number of LoadLockedReq miss cycles 1461system.cpu1.dcache.LoadLockedReq_miss_latency::total 316145498 # number of LoadLockedReq miss cycles 1462system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557553671 # number of StoreCondReq miss cycles 1463system.cpu1.dcache.StoreCondReq_miss_latency::total 557553671 # number of StoreCondReq miss cycles 1464system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 527500 # number of StoreCondFailReq miss cycles 1465system.cpu1.dcache.StoreCondFailReq_miss_latency::total 527500 # number of StoreCondFailReq miss cycles 1466system.cpu1.dcache.demand_miss_latency::cpu1.data 6167082798 # number of demand (read+write) miss cycles 1467system.cpu1.dcache.demand_miss_latency::total 6167082798 # number of demand (read+write) miss cycles 1468system.cpu1.dcache.overall_miss_latency::cpu1.data 6167082798 # number of overall miss cycles 1469system.cpu1.dcache.overall_miss_latency::total 6167082798 # number of overall miss cycles 1470system.cpu1.dcache.ReadReq_accesses::cpu1.data 10572937 # number of ReadReq accesses(hits+misses) 1471system.cpu1.dcache.ReadReq_accesses::total 10572937 # number of ReadReq accesses(hits+misses) 1472system.cpu1.dcache.WriteReq_accesses::cpu1.data 6657277 # number of WriteReq accesses(hits+misses) 1473system.cpu1.dcache.WriteReq_accesses::total 6657277 # number of WriteReq accesses(hits+misses) 1474system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80877 # number of SoftPFReq accesses(hits+misses) 1475system.cpu1.dcache.SoftPFReq_accesses::total 80877 # number of SoftPFReq accesses(hits+misses) 1476system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96995 # number of LoadLockedReq accesses(hits+misses) 1477system.cpu1.dcache.LoadLockedReq_accesses::total 96995 # number of LoadLockedReq accesses(hits+misses) 1478system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95201 # number of StoreCondReq accesses(hits+misses) 1479system.cpu1.dcache.StoreCondReq_accesses::total 95201 # number of StoreCondReq accesses(hits+misses) 1480system.cpu1.dcache.demand_accesses::cpu1.data 17230214 # number of demand (read+write) accesses 1481system.cpu1.dcache.demand_accesses::total 17230214 # number of demand (read+write) accesses 1482system.cpu1.dcache.overall_accesses::cpu1.data 17311091 # number of overall (read+write) accesses 1483system.cpu1.dcache.overall_accesses::total 17311091 # number of overall (read+write) accesses 1484system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.014867 # miss rate for ReadReq accesses 1485system.cpu1.dcache.ReadReq_miss_rate::total 0.014867 # miss rate for ReadReq accesses 1486system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021761 # miss rate for WriteReq accesses 1487system.cpu1.dcache.WriteReq_miss_rate::total 0.021761 # miss rate for WriteReq accesses 1488system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381060 # miss rate for SoftPFReq accesses 1489system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381060 # miss rate for SoftPFReq accesses 1490system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174452 # miss rate for LoadLockedReq accesses 1491system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174452 # miss rate for LoadLockedReq accesses 1492system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248684 # miss rate for StoreCondReq accesses 1493system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248684 # miss rate for StoreCondReq accesses 1494system.cpu1.dcache.demand_miss_rate::cpu1.data 0.017531 # miss rate for demand accesses 1495system.cpu1.dcache.demand_miss_rate::total 0.017531 # miss rate for demand accesses 1496system.cpu1.dcache.overall_miss_rate::cpu1.data 0.019229 # miss rate for overall accesses 1497system.cpu1.dcache.overall_miss_rate::total 0.019229 # miss rate for overall accesses 1498system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14691.052395 # average ReadReq miss latency 1499system.cpu1.dcache.ReadReq_avg_miss_latency::total 14691.052395 # average ReadReq miss latency 1500system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26629.816183 # average WriteReq miss latency 1501system.cpu1.dcache.WriteReq_avg_miss_latency::total 26629.816183 # average WriteReq miss latency 1502system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18683.617871 # average LoadLockedReq miss latency 1503system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18683.617871 # average LoadLockedReq miss latency 1504system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23550.313453 # average StoreCondReq miss latency 1505system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23550.313453 # average StoreCondReq miss latency | 1410system.cpu1.kern.inst.quiesce 2790 # number of quiesce instructions executed 1411system.cpu1.tickCycles 97744251 # Number of cycles that the object actually ticked 1412system.cpu1.idleCycles 16904246 # Total number of cycles that the object has spent stopped 1413system.cpu1.dcache.tags.replacements 195096 # number of replacements 1414system.cpu1.dcache.tags.tagsinuse 474.102569 # Cycle average of tags in use 1415system.cpu1.dcache.tags.total_refs 17976294 # Total number of references to valid blocks. 1416system.cpu1.dcache.tags.sampled_refs 195460 # Sample count of references to valid blocks. 1417system.cpu1.dcache.tags.avg_refs 91.969170 # Average number of references to valid blocks. 1418system.cpu1.dcache.tags.warmup_cycle 90457158500 # Cycle when the warmup percentage was hit. 1419system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.102569 # Average occupied blocks per requestor 1420system.cpu1.dcache.tags.occ_percent::cpu1.data 0.925982 # Average percentage of cache occupancy 1421system.cpu1.dcache.tags.occ_percent::total 0.925982 # Average percentage of cache occupancy 1422system.cpu1.dcache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id 1423system.cpu1.dcache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id 1424system.cpu1.dcache.tags.age_task_id_blocks_1024::3 50 # Occupied blocks per task id 1425system.cpu1.dcache.tags.occ_task_id_percent::1024 0.710938 # Percentage of cache occupancy per task id 1426system.cpu1.dcache.tags.tag_accesses 36856215 # Number of tag accesses 1427system.cpu1.dcache.tags.data_accesses 36856215 # Number of data accesses 1428system.cpu1.dcache.ReadReq_hits::cpu1.data 10952474 # number of ReadReq hits 1429system.cpu1.dcache.ReadReq_hits::total 10952474 # number of ReadReq hits 1430system.cpu1.dcache.WriteReq_hits::cpu1.data 6779584 # number of WriteReq hits 1431system.cpu1.dcache.WriteReq_hits::total 6779584 # number of WriteReq hits 1432system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50047 # number of SoftPFReq hits 1433system.cpu1.dcache.SoftPFReq_hits::total 50047 # number of SoftPFReq hits 1434system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80034 # number of LoadLockedReq hits 1435system.cpu1.dcache.LoadLockedReq_hits::total 80034 # number of LoadLockedReq hits 1436system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71497 # number of StoreCondReq hits 1437system.cpu1.dcache.StoreCondReq_hits::total 71497 # number of StoreCondReq hits 1438system.cpu1.dcache.demand_hits::cpu1.data 17732058 # number of demand (read+write) hits 1439system.cpu1.dcache.demand_hits::total 17732058 # number of demand (read+write) hits 1440system.cpu1.dcache.overall_hits::cpu1.data 17782105 # number of overall hits 1441system.cpu1.dcache.overall_hits::total 17782105 # number of overall hits 1442system.cpu1.dcache.ReadReq_misses::cpu1.data 158503 # number of ReadReq misses 1443system.cpu1.dcache.ReadReq_misses::total 158503 # number of ReadReq misses 1444system.cpu1.dcache.WriteReq_misses::cpu1.data 144597 # number of WriteReq misses 1445system.cpu1.dcache.WriteReq_misses::total 144597 # number of WriteReq misses 1446system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30804 # number of SoftPFReq misses 1447system.cpu1.dcache.SoftPFReq_misses::total 30804 # number of SoftPFReq misses 1448system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16970 # number of LoadLockedReq misses 1449system.cpu1.dcache.LoadLockedReq_misses::total 16970 # number of LoadLockedReq misses 1450system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23713 # number of StoreCondReq misses 1451system.cpu1.dcache.StoreCondReq_misses::total 23713 # number of StoreCondReq misses 1452system.cpu1.dcache.demand_misses::cpu1.data 303100 # number of demand (read+write) misses 1453system.cpu1.dcache.demand_misses::total 303100 # number of demand (read+write) misses 1454system.cpu1.dcache.overall_misses::cpu1.data 333904 # number of overall misses 1455system.cpu1.dcache.overall_misses::total 333904 # number of overall misses 1456system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2370328398 # number of ReadReq miss cycles 1457system.cpu1.dcache.ReadReq_miss_latency::total 2370328398 # number of ReadReq miss cycles 1458system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3872727461 # number of WriteReq miss cycles 1459system.cpu1.dcache.WriteReq_miss_latency::total 3872727461 # number of WriteReq miss cycles 1460system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 316464239 # number of LoadLockedReq miss cycles 1461system.cpu1.dcache.LoadLockedReq_miss_latency::total 316464239 # number of LoadLockedReq miss cycles 1462system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 558424163 # number of StoreCondReq miss cycles 1463system.cpu1.dcache.StoreCondReq_miss_latency::total 558424163 # number of StoreCondReq miss cycles 1464system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 271500 # number of StoreCondFailReq miss cycles 1465system.cpu1.dcache.StoreCondFailReq_miss_latency::total 271500 # number of StoreCondFailReq miss cycles 1466system.cpu1.dcache.demand_miss_latency::cpu1.data 6243055859 # number of demand (read+write) miss cycles 1467system.cpu1.dcache.demand_miss_latency::total 6243055859 # number of demand (read+write) miss cycles 1468system.cpu1.dcache.overall_miss_latency::cpu1.data 6243055859 # number of overall miss cycles 1469system.cpu1.dcache.overall_miss_latency::total 6243055859 # number of overall miss cycles 1470system.cpu1.dcache.ReadReq_accesses::cpu1.data 11110977 # number of ReadReq accesses(hits+misses) 1471system.cpu1.dcache.ReadReq_accesses::total 11110977 # number of ReadReq accesses(hits+misses) 1472system.cpu1.dcache.WriteReq_accesses::cpu1.data 6924181 # number of WriteReq accesses(hits+misses) 1473system.cpu1.dcache.WriteReq_accesses::total 6924181 # number of WriteReq accesses(hits+misses) 1474system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80851 # number of SoftPFReq accesses(hits+misses) 1475system.cpu1.dcache.SoftPFReq_accesses::total 80851 # number of SoftPFReq accesses(hits+misses) 1476system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97004 # number of LoadLockedReq accesses(hits+misses) 1477system.cpu1.dcache.LoadLockedReq_accesses::total 97004 # number of LoadLockedReq accesses(hits+misses) 1478system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95210 # number of StoreCondReq accesses(hits+misses) 1479system.cpu1.dcache.StoreCondReq_accesses::total 95210 # number of StoreCondReq accesses(hits+misses) 1480system.cpu1.dcache.demand_accesses::cpu1.data 18035158 # number of demand (read+write) accesses 1481system.cpu1.dcache.demand_accesses::total 18035158 # number of demand (read+write) accesses 1482system.cpu1.dcache.overall_accesses::cpu1.data 18116009 # number of overall (read+write) accesses 1483system.cpu1.dcache.overall_accesses::total 18116009 # number of overall (read+write) accesses 1484system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.014265 # miss rate for ReadReq accesses 1485system.cpu1.dcache.ReadReq_miss_rate::total 0.014265 # miss rate for ReadReq accesses 1486system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.020883 # miss rate for WriteReq accesses 1487system.cpu1.dcache.WriteReq_miss_rate::total 0.020883 # miss rate for WriteReq accesses 1488system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380997 # miss rate for SoftPFReq accesses 1489system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380997 # miss rate for SoftPFReq accesses 1490system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174941 # miss rate for LoadLockedReq accesses 1491system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174941 # miss rate for LoadLockedReq accesses 1492system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249060 # miss rate for StoreCondReq accesses 1493system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249060 # miss rate for StoreCondReq accesses 1494system.cpu1.dcache.demand_miss_rate::cpu1.data 0.016806 # miss rate for demand accesses 1495system.cpu1.dcache.demand_miss_rate::total 0.016806 # miss rate for demand accesses 1496system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018431 # miss rate for overall accesses 1497system.cpu1.dcache.overall_miss_rate::total 0.018431 # miss rate for overall accesses 1498system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14954.470250 # average ReadReq miss latency 1499system.cpu1.dcache.ReadReq_avg_miss_latency::total 14954.470250 # average ReadReq miss latency 1500system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26782.903248 # average WriteReq miss latency 1501system.cpu1.dcache.WriteReq_avg_miss_latency::total 26782.903248 # average WriteReq miss latency 1502system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18648.452504 # average LoadLockedReq miss latency 1503system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18648.452504 # average LoadLockedReq miss latency 1504system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23549.283642 # average StoreCondReq miss latency 1505system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23549.283642 # average StoreCondReq miss latency |
| 1506system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1507system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 1506system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1507system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1508system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20416.882844 # average overall miss latency 1509system.cpu1.dcache.demand_avg_miss_latency::total 20416.882844 # average overall miss latency 1510system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18526.611325 # average overall miss latency 1511system.cpu1.dcache.overall_avg_miss_latency::total 18526.611325 # average overall miss latency | 1508system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20597.346945 # average overall miss latency 1509system.cpu1.dcache.demand_avg_miss_latency::total 20597.346945 # average overall miss latency 1510system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18697.158042 # average overall miss latency 1511system.cpu1.dcache.overall_avg_miss_latency::total 18697.158042 # average overall miss latency |
| 1512system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1513system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1514system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1515system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1516system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1517system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1518system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1519system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1512system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1513system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1514system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1515system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1516system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1517system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1518system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1519system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1520system.cpu1.dcache.writebacks::writebacks 117850 # number of writebacks 1521system.cpu1.dcache.writebacks::total 117850 # number of writebacks 1522system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 15942 # number of ReadReq MSHR hits 1523system.cpu1.dcache.ReadReq_mshr_hits::total 15942 # number of ReadReq MSHR hits 1524system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52278 # number of WriteReq MSHR hits 1525system.cpu1.dcache.WriteReq_mshr_hits::total 52278 # number of WriteReq MSHR hits 1526system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12035 # number of LoadLockedReq MSHR hits 1527system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12035 # number of LoadLockedReq MSHR hits 1528system.cpu1.dcache.demand_mshr_hits::cpu1.data 68220 # number of demand (read+write) MSHR hits 1529system.cpu1.dcache.demand_mshr_hits::total 68220 # number of demand (read+write) MSHR hits 1530system.cpu1.dcache.overall_mshr_hits::cpu1.data 68220 # number of overall MSHR hits 1531system.cpu1.dcache.overall_mshr_hits::total 68220 # number of overall MSHR hits 1532system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 141249 # number of ReadReq MSHR misses 1533system.cpu1.dcache.ReadReq_mshr_misses::total 141249 # number of ReadReq MSHR misses 1534system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92589 # number of WriteReq MSHR misses 1535system.cpu1.dcache.WriteReq_mshr_misses::total 92589 # number of WriteReq MSHR misses 1536system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29909 # number of SoftPFReq MSHR misses 1537system.cpu1.dcache.SoftPFReq_mshr_misses::total 29909 # number of SoftPFReq MSHR misses 1538system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4886 # number of LoadLockedReq MSHR misses 1539system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4886 # number of LoadLockedReq MSHR misses 1540system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23675 # number of StoreCondReq MSHR misses 1541system.cpu1.dcache.StoreCondReq_mshr_misses::total 23675 # number of StoreCondReq MSHR misses 1542system.cpu1.dcache.demand_mshr_misses::cpu1.data 233838 # number of demand (read+write) MSHR misses 1543system.cpu1.dcache.demand_mshr_misses::total 233838 # number of demand (read+write) MSHR misses 1544system.cpu1.dcache.overall_mshr_misses::cpu1.data 263747 # number of overall MSHR misses 1545system.cpu1.dcache.overall_mshr_misses::total 263747 # number of overall MSHR misses 1546system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14605 # number of ReadReq MSHR uncacheable 1547system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14605 # number of ReadReq MSHR uncacheable 1548system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11936 # number of WriteReq MSHR uncacheable 1549system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11936 # number of WriteReq MSHR uncacheable 1550system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26541 # number of overall MSHR uncacheable misses 1551system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26541 # number of overall MSHR uncacheable misses 1552system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1867063577 # number of ReadReq MSHR miss cycles 1553system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1867063577 # number of ReadReq MSHR miss cycles 1554system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2294961861 # number of WriteReq MSHR miss cycles 1555system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2294961861 # number of WriteReq MSHR miss cycles 1556system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 485499507 # number of SoftPFReq MSHR miss cycles 1557system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 485499507 # number of SoftPFReq MSHR miss cycles 1558system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 80204246 # number of LoadLockedReq MSHR miss cycles 1559system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 80204246 # number of LoadLockedReq MSHR miss cycles 1560system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 520729829 # number of StoreCondReq MSHR miss cycles 1561system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 520729829 # number of StoreCondReq MSHR miss cycles 1562system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 512500 # number of StoreCondFailReq MSHR miss cycles 1563system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 512500 # number of StoreCondFailReq MSHR miss cycles 1564system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4162025438 # number of demand (read+write) MSHR miss cycles 1565system.cpu1.dcache.demand_mshr_miss_latency::total 4162025438 # number of demand (read+write) MSHR miss cycles 1566system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4647524945 # number of overall MSHR miss cycles 1567system.cpu1.dcache.overall_mshr_miss_latency::total 4647524945 # number of overall MSHR miss cycles 1568system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2322107500 # number of ReadReq MSHR uncacheable cycles 1569system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2322107500 # number of ReadReq MSHR uncacheable cycles 1570system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1843997501 # number of WriteReq MSHR uncacheable cycles 1571system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1843997501 # number of WriteReq MSHR uncacheable cycles 1572system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4166105001 # number of overall MSHR uncacheable cycles 1573system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4166105001 # number of overall MSHR uncacheable cycles 1574system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013359 # mshr miss rate for ReadReq accesses 1575system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013359 # mshr miss rate for ReadReq accesses 1576system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013908 # mshr miss rate for WriteReq accesses 1577system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013908 # mshr miss rate for WriteReq accesses 1578system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369808 # mshr miss rate for SoftPFReq accesses 1579system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369808 # mshr miss rate for SoftPFReq accesses 1580system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050374 # mshr miss rate for LoadLockedReq accesses 1581system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050374 # mshr miss rate for LoadLockedReq accesses 1582system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248684 # mshr miss rate for StoreCondReq accesses 1583system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248684 # mshr miss rate for StoreCondReq accesses 1584system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013571 # mshr miss rate for demand accesses 1585system.cpu1.dcache.demand_mshr_miss_rate::total 0.013571 # mshr miss rate for demand accesses 1586system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015236 # mshr miss rate for overall accesses 1587system.cpu1.dcache.overall_mshr_miss_rate::total 0.015236 # mshr miss rate for overall accesses 1588system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13218.242798 # average ReadReq mshr miss latency 1589system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13218.242798 # average ReadReq mshr miss latency 1590system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24786.549817 # average WriteReq mshr miss latency 1591system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24786.549817 # average WriteReq mshr miss latency 1592system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16232.555652 # average SoftPFReq mshr miss latency 1593system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16232.555652 # average SoftPFReq mshr miss latency 1594system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16415.113795 # average LoadLockedReq mshr miss latency 1595system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16415.113795 # average LoadLockedReq mshr miss latency 1596system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21994.924139 # average StoreCondReq mshr miss latency 1597system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21994.924139 # average StoreCondReq mshr miss latency | 1520system.cpu1.dcache.writebacks::writebacks 119832 # number of writebacks 1521system.cpu1.dcache.writebacks::total 119832 # number of writebacks 1522system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16048 # number of ReadReq MSHR hits 1523system.cpu1.dcache.ReadReq_mshr_hits::total 16048 # number of ReadReq MSHR hits 1524system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52216 # number of WriteReq MSHR hits 1525system.cpu1.dcache.WriteReq_mshr_hits::total 52216 # number of WriteReq MSHR hits 1526system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12045 # number of LoadLockedReq MSHR hits 1527system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12045 # number of LoadLockedReq MSHR hits 1528system.cpu1.dcache.demand_mshr_hits::cpu1.data 68264 # number of demand (read+write) MSHR hits 1529system.cpu1.dcache.demand_mshr_hits::total 68264 # number of demand (read+write) MSHR hits 1530system.cpu1.dcache.overall_mshr_hits::cpu1.data 68264 # number of overall MSHR hits 1531system.cpu1.dcache.overall_mshr_hits::total 68264 # number of overall MSHR hits 1532system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 142455 # number of ReadReq MSHR misses 1533system.cpu1.dcache.ReadReq_mshr_misses::total 142455 # number of ReadReq MSHR misses 1534system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92381 # number of WriteReq MSHR misses 1535system.cpu1.dcache.WriteReq_mshr_misses::total 92381 # number of WriteReq MSHR misses 1536system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29949 # number of SoftPFReq MSHR misses 1537system.cpu1.dcache.SoftPFReq_mshr_misses::total 29949 # number of SoftPFReq MSHR misses 1538system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4925 # number of LoadLockedReq MSHR misses 1539system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4925 # number of LoadLockedReq MSHR misses 1540system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23713 # number of StoreCondReq MSHR misses 1541system.cpu1.dcache.StoreCondReq_mshr_misses::total 23713 # number of StoreCondReq MSHR misses 1542system.cpu1.dcache.demand_mshr_misses::cpu1.data 234836 # number of demand (read+write) MSHR misses 1543system.cpu1.dcache.demand_mshr_misses::total 234836 # number of demand (read+write) MSHR misses 1544system.cpu1.dcache.overall_mshr_misses::cpu1.data 264785 # number of overall MSHR misses 1545system.cpu1.dcache.overall_mshr_misses::total 264785 # number of overall MSHR misses 1546system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14604 # number of ReadReq MSHR uncacheable 1547system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14604 # number of ReadReq MSHR uncacheable 1548system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11935 # number of WriteReq MSHR uncacheable 1549system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11935 # number of WriteReq MSHR uncacheable 1550system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26539 # number of overall MSHR uncacheable misses 1551system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26539 # number of overall MSHR uncacheable misses 1552system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1925101376 # number of ReadReq MSHR miss cycles 1553system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1925101376 # number of ReadReq MSHR miss cycles 1554system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2304194019 # number of WriteReq MSHR miss cycles 1555system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2304194019 # number of WriteReq MSHR miss cycles 1556system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 483540014 # number of SoftPFReq MSHR miss cycles 1557system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 483540014 # number of SoftPFReq MSHR miss cycles 1558system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 80690501 # number of LoadLockedReq MSHR miss cycles 1559system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 80690501 # number of LoadLockedReq MSHR miss cycles 1560system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521529337 # number of StoreCondReq MSHR miss cycles 1561system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521529337 # number of StoreCondReq MSHR miss cycles 1562system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 262500 # number of StoreCondFailReq MSHR miss cycles 1563system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 262500 # number of StoreCondFailReq MSHR miss cycles 1564system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4229295395 # number of demand (read+write) MSHR miss cycles 1565system.cpu1.dcache.demand_mshr_miss_latency::total 4229295395 # number of demand (read+write) MSHR miss cycles 1566system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4712835409 # number of overall MSHR miss cycles 1567system.cpu1.dcache.overall_mshr_miss_latency::total 4712835409 # number of overall MSHR miss cycles 1568system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2321932001 # number of ReadReq MSHR uncacheable cycles 1569system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2321932001 # number of ReadReq MSHR uncacheable cycles 1570system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1843920001 # number of WriteReq MSHR uncacheable cycles 1571system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1843920001 # number of WriteReq MSHR uncacheable cycles 1572system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4165852002 # number of overall MSHR uncacheable cycles 1573system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4165852002 # number of overall MSHR uncacheable cycles 1574system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.012821 # mshr miss rate for ReadReq accesses 1575system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.012821 # mshr miss rate for ReadReq accesses 1576system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013342 # mshr miss rate for WriteReq accesses 1577system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013342 # mshr miss rate for WriteReq accesses 1578system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.370422 # mshr miss rate for SoftPFReq accesses 1579system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.370422 # mshr miss rate for SoftPFReq accesses 1580system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050771 # mshr miss rate for LoadLockedReq accesses 1581system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050771 # mshr miss rate for LoadLockedReq accesses 1582system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249060 # mshr miss rate for StoreCondReq accesses 1583system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249060 # mshr miss rate for StoreCondReq accesses 1584system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013021 # mshr miss rate for demand accesses 1585system.cpu1.dcache.demand_mshr_miss_rate::total 0.013021 # mshr miss rate for demand accesses 1586system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014616 # mshr miss rate for overall accesses 1587system.cpu1.dcache.overall_mshr_miss_rate::total 0.014616 # mshr miss rate for overall accesses 1588system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13513.750841 # average ReadReq mshr miss latency 1589system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13513.750841 # average ReadReq mshr miss latency 1590system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24942.293534 # average WriteReq mshr miss latency 1591system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24942.293534 # average WriteReq mshr miss latency 1592system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16145.447728 # average SoftPFReq mshr miss latency 1593system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16145.447728 # average SoftPFReq mshr miss latency 1594system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16383.858071 # average LoadLockedReq mshr miss latency 1595system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16383.858071 # average LoadLockedReq mshr miss latency 1596system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21993.393371 # average StoreCondReq mshr miss latency 1597system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21993.393371 # average StoreCondReq mshr miss latency |
| 1598system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1599system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1598system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1599system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1600system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17798.755711 # average overall mshr miss latency 1601system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17798.755711 # average overall mshr miss latency 1602system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17621.148089 # average overall mshr miss latency 1603system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17621.148089 # average overall mshr miss latency 1604system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158994.008901 # average ReadReq mshr uncacheable latency 1605system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 158994.008901 # average ReadReq mshr uncacheable latency 1606system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154490.407255 # average WriteReq mshr uncacheable latency 1607system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154490.407255 # average WriteReq mshr uncacheable latency 1608system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 156968.652312 # average overall mshr uncacheable latency 1609system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 156968.652312 # average overall mshr uncacheable latency | 1600system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18009.570062 # average overall mshr miss latency 1601system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18009.570062 # average overall mshr miss latency 1602system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17798.725037 # average overall mshr miss latency 1603system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17798.725037 # average overall mshr miss latency 1604system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158992.878732 # average ReadReq mshr uncacheable latency 1605system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 158992.878732 # average ReadReq mshr uncacheable latency 1606system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154496.858065 # average WriteReq mshr uncacheable latency 1607system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154496.858065 # average WriteReq mshr uncacheable latency 1608system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 156970.948491 # average overall mshr uncacheable latency 1609system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 156970.948491 # average overall mshr uncacheable latency |
| 1610system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1610system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1611system.cpu1.icache.tags.replacements 947892 # number of replacements 1612system.cpu1.icache.tags.tagsinuse 499.324313 # Cycle average of tags in use 1613system.cpu1.icache.tags.total_refs 38832195 # Total number of references to valid blocks. 1614system.cpu1.icache.tags.sampled_refs 948404 # Sample count of references to valid blocks. 1615system.cpu1.icache.tags.avg_refs 40.944782 # Average number of references to valid blocks. 1616system.cpu1.icache.tags.warmup_cycle 72125006000 # Cycle when the warmup percentage was hit. 1617system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.324313 # Average occupied blocks per requestor 1618system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975243 # Average percentage of cache occupancy 1619system.cpu1.icache.tags.occ_percent::total 0.975243 # Average percentage of cache occupancy | 1611system.cpu1.icache.tags.replacements 948604 # number of replacements 1612system.cpu1.icache.tags.tagsinuse 499.330921 # Cycle average of tags in use 1613system.cpu1.icache.tags.total_refs 38801180 # Total number of references to valid blocks. 1614system.cpu1.icache.tags.sampled_refs 949116 # Sample count of references to valid blocks. 1615system.cpu1.icache.tags.avg_refs 40.881389 # Average number of references to valid blocks. 1616system.cpu1.icache.tags.warmup_cycle 72079277000 # Cycle when the warmup percentage was hit. 1617system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.330921 # Average occupied blocks per requestor 1618system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975256 # Average percentage of cache occupancy 1619system.cpu1.icache.tags.occ_percent::total 0.975256 # Average percentage of cache occupancy |
| 1620system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1620system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1621system.cpu1.icache.tags.age_task_id_blocks_1024::2 461 # Occupied blocks per task id 1622system.cpu1.icache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id | 1621system.cpu1.icache.tags.age_task_id_blocks_1024::2 467 # Occupied blocks per task id 1622system.cpu1.icache.tags.age_task_id_blocks_1024::3 45 # Occupied blocks per task id |
| 1623system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1623system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1624system.cpu1.icache.tags.tag_accesses 80509602 # Number of tag accesses 1625system.cpu1.icache.tags.data_accesses 80509602 # Number of data accesses 1626system.cpu1.icache.ReadReq_hits::cpu1.inst 38832195 # number of ReadReq hits 1627system.cpu1.icache.ReadReq_hits::total 38832195 # number of ReadReq hits 1628system.cpu1.icache.demand_hits::cpu1.inst 38832195 # number of demand (read+write) hits 1629system.cpu1.icache.demand_hits::total 38832195 # number of demand (read+write) hits 1630system.cpu1.icache.overall_hits::cpu1.inst 38832195 # number of overall hits 1631system.cpu1.icache.overall_hits::total 38832195 # number of overall hits 1632system.cpu1.icache.ReadReq_misses::cpu1.inst 948404 # number of ReadReq misses 1633system.cpu1.icache.ReadReq_misses::total 948404 # number of ReadReq misses 1634system.cpu1.icache.demand_misses::cpu1.inst 948404 # number of demand (read+write) misses 1635system.cpu1.icache.demand_misses::total 948404 # number of demand (read+write) misses 1636system.cpu1.icache.overall_misses::cpu1.inst 948404 # number of overall misses 1637system.cpu1.icache.overall_misses::total 948404 # number of overall misses 1638system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8190397665 # number of ReadReq miss cycles 1639system.cpu1.icache.ReadReq_miss_latency::total 8190397665 # number of ReadReq miss cycles 1640system.cpu1.icache.demand_miss_latency::cpu1.inst 8190397665 # number of demand (read+write) miss cycles 1641system.cpu1.icache.demand_miss_latency::total 8190397665 # number of demand (read+write) miss cycles 1642system.cpu1.icache.overall_miss_latency::cpu1.inst 8190397665 # number of overall miss cycles 1643system.cpu1.icache.overall_miss_latency::total 8190397665 # number of overall miss cycles 1644system.cpu1.icache.ReadReq_accesses::cpu1.inst 39780599 # number of ReadReq accesses(hits+misses) 1645system.cpu1.icache.ReadReq_accesses::total 39780599 # number of ReadReq accesses(hits+misses) 1646system.cpu1.icache.demand_accesses::cpu1.inst 39780599 # number of demand (read+write) accesses 1647system.cpu1.icache.demand_accesses::total 39780599 # number of demand (read+write) accesses 1648system.cpu1.icache.overall_accesses::cpu1.inst 39780599 # number of overall (read+write) accesses 1649system.cpu1.icache.overall_accesses::total 39780599 # number of overall (read+write) accesses 1650system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023841 # miss rate for ReadReq accesses 1651system.cpu1.icache.ReadReq_miss_rate::total 0.023841 # miss rate for ReadReq accesses 1652system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023841 # miss rate for demand accesses 1653system.cpu1.icache.demand_miss_rate::total 0.023841 # miss rate for demand accesses 1654system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023841 # miss rate for overall accesses 1655system.cpu1.icache.overall_miss_rate::total 0.023841 # miss rate for overall accesses 1656system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8635.979672 # average ReadReq miss latency 1657system.cpu1.icache.ReadReq_avg_miss_latency::total 8635.979672 # average ReadReq miss latency 1658system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8635.979672 # average overall miss latency 1659system.cpu1.icache.demand_avg_miss_latency::total 8635.979672 # average overall miss latency 1660system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8635.979672 # average overall miss latency 1661system.cpu1.icache.overall_avg_miss_latency::total 8635.979672 # average overall miss latency | 1624system.cpu1.icache.tags.tag_accesses 80449708 # Number of tag accesses 1625system.cpu1.icache.tags.data_accesses 80449708 # Number of data accesses 1626system.cpu1.icache.ReadReq_hits::cpu1.inst 38801180 # number of ReadReq hits 1627system.cpu1.icache.ReadReq_hits::total 38801180 # number of ReadReq hits 1628system.cpu1.icache.demand_hits::cpu1.inst 38801180 # number of demand (read+write) hits 1629system.cpu1.icache.demand_hits::total 38801180 # number of demand (read+write) hits 1630system.cpu1.icache.overall_hits::cpu1.inst 38801180 # number of overall hits 1631system.cpu1.icache.overall_hits::total 38801180 # number of overall hits 1632system.cpu1.icache.ReadReq_misses::cpu1.inst 949116 # number of ReadReq misses 1633system.cpu1.icache.ReadReq_misses::total 949116 # number of ReadReq misses 1634system.cpu1.icache.demand_misses::cpu1.inst 949116 # number of demand (read+write) misses 1635system.cpu1.icache.demand_misses::total 949116 # number of demand (read+write) misses 1636system.cpu1.icache.overall_misses::cpu1.inst 949116 # number of overall misses 1637system.cpu1.icache.overall_misses::total 949116 # number of overall misses 1638system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8198295158 # number of ReadReq miss cycles 1639system.cpu1.icache.ReadReq_miss_latency::total 8198295158 # number of ReadReq miss cycles 1640system.cpu1.icache.demand_miss_latency::cpu1.inst 8198295158 # number of demand (read+write) miss cycles 1641system.cpu1.icache.demand_miss_latency::total 8198295158 # number of demand (read+write) miss cycles 1642system.cpu1.icache.overall_miss_latency::cpu1.inst 8198295158 # number of overall miss cycles 1643system.cpu1.icache.overall_miss_latency::total 8198295158 # number of overall miss cycles 1644system.cpu1.icache.ReadReq_accesses::cpu1.inst 39750296 # number of ReadReq accesses(hits+misses) 1645system.cpu1.icache.ReadReq_accesses::total 39750296 # number of ReadReq accesses(hits+misses) 1646system.cpu1.icache.demand_accesses::cpu1.inst 39750296 # number of demand (read+write) accesses 1647system.cpu1.icache.demand_accesses::total 39750296 # number of demand (read+write) accesses 1648system.cpu1.icache.overall_accesses::cpu1.inst 39750296 # number of overall (read+write) accesses 1649system.cpu1.icache.overall_accesses::total 39750296 # number of overall (read+write) accesses 1650system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023877 # miss rate for ReadReq accesses 1651system.cpu1.icache.ReadReq_miss_rate::total 0.023877 # miss rate for ReadReq accesses 1652system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023877 # miss rate for demand accesses 1653system.cpu1.icache.demand_miss_rate::total 0.023877 # miss rate for demand accesses 1654system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023877 # miss rate for overall accesses 1655system.cpu1.icache.overall_miss_rate::total 0.023877 # miss rate for overall accesses 1656system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8637.822098 # average ReadReq miss latency 1657system.cpu1.icache.ReadReq_avg_miss_latency::total 8637.822098 # average ReadReq miss latency 1658system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8637.822098 # average overall miss latency 1659system.cpu1.icache.demand_avg_miss_latency::total 8637.822098 # average overall miss latency 1660system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8637.822098 # average overall miss latency 1661system.cpu1.icache.overall_avg_miss_latency::total 8637.822098 # average overall miss latency |
| 1662system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1663system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1664system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1665system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1666system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1667system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1668system.cpu1.icache.fast_writes 0 # number of fast writes performed 1669system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1662system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1663system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1664system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1665system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1666system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1667system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1668system.cpu1.icache.fast_writes 0 # number of fast writes performed 1669system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1670system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 948404 # number of ReadReq MSHR misses 1671system.cpu1.icache.ReadReq_mshr_misses::total 948404 # number of ReadReq MSHR misses 1672system.cpu1.icache.demand_mshr_misses::cpu1.inst 948404 # number of demand (read+write) MSHR misses 1673system.cpu1.icache.demand_mshr_misses::total 948404 # number of demand (read+write) MSHR misses 1674system.cpu1.icache.overall_mshr_misses::cpu1.inst 948404 # number of overall MSHR misses 1675system.cpu1.icache.overall_mshr_misses::total 948404 # number of overall MSHR misses | 1670system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 949116 # number of ReadReq MSHR misses 1671system.cpu1.icache.ReadReq_mshr_misses::total 949116 # number of ReadReq MSHR misses 1672system.cpu1.icache.demand_mshr_misses::cpu1.inst 949116 # number of demand (read+write) MSHR misses 1673system.cpu1.icache.demand_mshr_misses::total 949116 # number of demand (read+write) MSHR misses 1674system.cpu1.icache.overall_mshr_misses::cpu1.inst 949116 # number of overall MSHR misses 1675system.cpu1.icache.overall_mshr_misses::total 949116 # number of overall MSHR misses |
| 1676system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 1677system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable 1678system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 1679system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses | 1676system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 1677system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable 1678system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 1679system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses |
| 1680system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7240674335 # number of ReadReq MSHR miss cycles 1681system.cpu1.icache.ReadReq_mshr_miss_latency::total 7240674335 # number of ReadReq MSHR miss cycles 1682system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7240674335 # number of demand (read+write) MSHR miss cycles 1683system.cpu1.icache.demand_mshr_miss_latency::total 7240674335 # number of demand (read+write) MSHR miss cycles 1684system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7240674335 # number of overall MSHR miss cycles 1685system.cpu1.icache.overall_mshr_miss_latency::total 7240674335 # number of overall MSHR miss cycles 1686system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10306250 # number of ReadReq MSHR uncacheable cycles 1687system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10306250 # number of ReadReq MSHR uncacheable cycles 1688system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10306250 # number of overall MSHR uncacheable cycles 1689system.cpu1.icache.overall_mshr_uncacheable_latency::total 10306250 # number of overall MSHR uncacheable cycles 1690system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023841 # mshr miss rate for ReadReq accesses 1691system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023841 # mshr miss rate for ReadReq accesses 1692system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023841 # mshr miss rate for demand accesses 1693system.cpu1.icache.demand_mshr_miss_rate::total 0.023841 # mshr miss rate for demand accesses 1694system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023841 # mshr miss rate for overall accesses 1695system.cpu1.icache.overall_mshr_miss_rate::total 0.023841 # mshr miss rate for overall accesses 1696system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7634.588567 # average ReadReq mshr miss latency 1697system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7634.588567 # average ReadReq mshr miss latency 1698system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7634.588567 # average overall mshr miss latency 1699system.cpu1.icache.demand_avg_mshr_miss_latency::total 7634.588567 # average overall mshr miss latency 1700system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7634.588567 # average overall mshr miss latency 1701system.cpu1.icache.overall_avg_mshr_miss_latency::total 7634.588567 # average overall mshr miss latency 1702system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92020.089286 # average ReadReq mshr uncacheable latency 1703system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92020.089286 # average ReadReq mshr uncacheable latency 1704system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92020.089286 # average overall mshr uncacheable latency 1705system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92020.089286 # average overall mshr uncacheable latency | 1680system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7247841842 # number of ReadReq MSHR miss cycles 1681system.cpu1.icache.ReadReq_mshr_miss_latency::total 7247841842 # number of ReadReq MSHR miss cycles 1682system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7247841842 # number of demand (read+write) MSHR miss cycles 1683system.cpu1.icache.demand_mshr_miss_latency::total 7247841842 # number of demand (read+write) MSHR miss cycles 1684system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7247841842 # number of overall MSHR miss cycles 1685system.cpu1.icache.overall_mshr_miss_latency::total 7247841842 # number of overall MSHR miss cycles 1686system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10378250 # number of ReadReq MSHR uncacheable cycles 1687system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10378250 # number of ReadReq MSHR uncacheable cycles 1688system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10378250 # number of overall MSHR uncacheable cycles 1689system.cpu1.icache.overall_mshr_uncacheable_latency::total 10378250 # number of overall MSHR uncacheable cycles 1690system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023877 # mshr miss rate for ReadReq accesses 1691system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023877 # mshr miss rate for ReadReq accesses 1692system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023877 # mshr miss rate for demand accesses 1693system.cpu1.icache.demand_mshr_miss_rate::total 0.023877 # mshr miss rate for demand accesses 1694system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023877 # mshr miss rate for overall accesses 1695system.cpu1.icache.overall_mshr_miss_rate::total 0.023877 # mshr miss rate for overall accesses 1696system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7636.413085 # average ReadReq mshr miss latency 1697system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7636.413085 # average ReadReq mshr miss latency 1698system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7636.413085 # average overall mshr miss latency 1699system.cpu1.icache.demand_avg_mshr_miss_latency::total 7636.413085 # average overall mshr miss latency 1700system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7636.413085 # average overall mshr miss latency 1701system.cpu1.icache.overall_avg_mshr_miss_latency::total 7636.413085 # average overall mshr miss latency 1702system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92662.946429 # average ReadReq mshr uncacheable latency 1703system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92662.946429 # average ReadReq mshr uncacheable latency 1704system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92662.946429 # average overall mshr uncacheable latency 1705system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92662.946429 # average overall mshr uncacheable latency |
| 1706system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1706system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1707system.cpu1.l2cache.prefetcher.num_hwpf_issued 197682 # number of hwpf issued 1708system.cpu1.l2cache.prefetcher.pfIdentified 197698 # number of prefetch candidates identified 1709system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue | 1707system.cpu1.l2cache.prefetcher.num_hwpf_issued 197332 # number of hwpf issued 1708system.cpu1.l2cache.prefetcher.pfIdentified 197391 # number of prefetch candidates identified 1709system.cpu1.l2cache.prefetcher.pfBufferHit 51 # number of redundant prefetches already in prefetch queue |
| 1710system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1711system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 1710system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1711system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 1712system.cpu1.l2cache.prefetcher.pfSpanPage 58310 # number of prefetches not generated due to page crossing 1713system.cpu1.l2cache.tags.replacements 54781 # number of replacements 1714system.cpu1.l2cache.tags.tagsinuse 15316.530997 # Cycle average of tags in use 1715system.cpu1.l2cache.tags.total_refs 1176536 # Total number of references to valid blocks. 1716system.cpu1.l2cache.tags.sampled_refs 69755 # Sample count of references to valid blocks. 1717system.cpu1.l2cache.tags.avg_refs 16.866691 # Average number of references to valid blocks. | 1712system.cpu1.l2cache.prefetcher.pfSpanPage 58593 # number of prefetches not generated due to page crossing 1713system.cpu1.l2cache.tags.replacements 54928 # number of replacements 1714system.cpu1.l2cache.tags.tagsinuse 15357.291554 # Cycle average of tags in use 1715system.cpu1.l2cache.tags.total_refs 1177888 # Total number of references to valid blocks. 1716system.cpu1.l2cache.tags.sampled_refs 69820 # Sample count of references to valid blocks. 1717system.cpu1.l2cache.tags.avg_refs 16.870352 # Average number of references to valid blocks. |
| 1718system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1718system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1719system.cpu1.l2cache.tags.occ_blocks::writebacks 7883.130354 # Average occupied blocks per requestor 1720system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 45.774786 # Average occupied blocks per requestor 1721system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.102173 # Average occupied blocks per requestor 1722system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4372.978904 # Average occupied blocks per requestor 1723system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2161.890501 # Average occupied blocks per requestor 1724system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 852.654278 # Average occupied blocks per requestor 1725system.cpu1.l2cache.tags.occ_percent::writebacks 0.481148 # Average percentage of cache occupancy 1726system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002794 # Average percentage of cache occupancy | 1719system.cpu1.l2cache.tags.occ_blocks::writebacks 7821.827388 # Average occupied blocks per requestor 1720system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 38.231580 # Average occupied blocks per requestor 1721system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.097899 # Average occupied blocks per requestor 1722system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4362.380441 # Average occupied blocks per requestor 1723system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2262.649841 # Average occupied blocks per requestor 1724system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 872.104404 # Average occupied blocks per requestor 1725system.cpu1.l2cache.tags.occ_percent::writebacks 0.477406 # Average percentage of cache occupancy 1726system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002333 # Average percentage of cache occupancy |
| 1727system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy | 1727system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy |
| 1728system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.266905 # Average percentage of cache occupancy 1729system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.131951 # Average percentage of cache occupancy 1730system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.052042 # Average percentage of cache occupancy 1731system.cpu1.l2cache.tags.occ_percent::total 0.934847 # Average percentage of cache occupancy 1732system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1060 # Occupied blocks per task id 1733system.cpu1.l2cache.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id 1734system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13867 # Occupied blocks per task id 1735system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id 1736system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 654 # Occupied blocks per task id 1737system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 402 # Occupied blocks per task id 1738system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id 1739system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id | 1728system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.266259 # Average percentage of cache occupancy 1729system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.138101 # Average percentage of cache occupancy 1730system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.053229 # Average percentage of cache occupancy 1731system.cpu1.l2cache.tags.occ_percent::total 0.937335 # Average percentage of cache occupancy 1732system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1066 # Occupied blocks per task id 1733system.cpu1.l2cache.tags.occ_task_id_blocks::1023 49 # Occupied blocks per task id 1734system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13777 # Occupied blocks per task id 1735system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 657 # Occupied blocks per task id 1736system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 409 # Occupied blocks per task id 1737system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id 1738system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id |
| 1740system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id | 1739system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id |
| 1741system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id 1742system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6188 # Occupied blocks per task id 1743system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7370 # Occupied blocks per task id 1744system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.064697 # Percentage of cache occupancy per task id 1745system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002869 # Percentage of cache occupancy per task id 1746system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.846375 # Percentage of cache occupancy per task id 1747system.cpu1.l2cache.tags.tag_accesses 22471002 # Number of tag accesses 1748system.cpu1.l2cache.tags.data_accesses 22471002 # Number of data accesses 1749system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28799 # number of ReadReq hits 1750system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2667 # number of ReadReq hits 1751system.cpu1.l2cache.ReadReq_hits::cpu1.inst 927404 # number of ReadReq hits 1752system.cpu1.l2cache.ReadReq_hits::cpu1.data 105047 # number of ReadReq hits 1753system.cpu1.l2cache.ReadReq_hits::total 1063917 # number of ReadReq hits 1754system.cpu1.l2cache.Writeback_hits::writebacks 117850 # number of Writeback hits 1755system.cpu1.l2cache.Writeback_hits::total 117850 # number of Writeback hits 1756system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1629 # number of UpgradeReq hits 1757system.cpu1.l2cache.UpgradeReq_hits::total 1629 # number of UpgradeReq hits 1758system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 948 # number of SCUpgradeReq hits 1759system.cpu1.l2cache.SCUpgradeReq_hits::total 948 # number of SCUpgradeReq hits 1760system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27664 # number of ReadExReq hits 1761system.cpu1.l2cache.ReadExReq_hits::total 27664 # number of ReadExReq hits 1762system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28799 # number of demand (read+write) hits 1763system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2667 # number of demand (read+write) hits 1764system.cpu1.l2cache.demand_hits::cpu1.inst 927404 # number of demand (read+write) hits 1765system.cpu1.l2cache.demand_hits::cpu1.data 132711 # number of demand (read+write) hits 1766system.cpu1.l2cache.demand_hits::total 1091581 # number of demand (read+write) hits 1767system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 28799 # number of overall hits 1768system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2667 # number of overall hits 1769system.cpu1.l2cache.overall_hits::cpu1.inst 927404 # number of overall hits 1770system.cpu1.l2cache.overall_hits::cpu1.data 132711 # number of overall hits 1771system.cpu1.l2cache.overall_hits::total 1091581 # number of overall hits 1772system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 641 # number of ReadReq misses 1773system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 224 # number of ReadReq misses 1774system.cpu1.l2cache.ReadReq_misses::cpu1.inst 21000 # number of ReadReq misses 1775system.cpu1.l2cache.ReadReq_misses::cpu1.data 70995 # number of ReadReq misses 1776system.cpu1.l2cache.ReadReq_misses::total 92860 # number of ReadReq misses 1777system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28409 # number of UpgradeReq misses 1778system.cpu1.l2cache.UpgradeReq_misses::total 28409 # number of UpgradeReq misses 1779system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22727 # number of SCUpgradeReq misses 1780system.cpu1.l2cache.SCUpgradeReq_misses::total 22727 # number of SCUpgradeReq misses 1781system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34889 # number of ReadExReq misses 1782system.cpu1.l2cache.ReadExReq_misses::total 34889 # number of ReadExReq misses 1783system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 641 # number of demand (read+write) misses 1784system.cpu1.l2cache.demand_misses::cpu1.itb.walker 224 # number of demand (read+write) misses 1785system.cpu1.l2cache.demand_misses::cpu1.inst 21000 # number of demand (read+write) misses 1786system.cpu1.l2cache.demand_misses::cpu1.data 105884 # number of demand (read+write) misses 1787system.cpu1.l2cache.demand_misses::total 127749 # number of demand (read+write) misses 1788system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 641 # number of overall misses 1789system.cpu1.l2cache.overall_misses::cpu1.itb.walker 224 # number of overall misses 1790system.cpu1.l2cache.overall_misses::cpu1.inst 21000 # number of overall misses 1791system.cpu1.l2cache.overall_misses::cpu1.data 105884 # number of overall misses 1792system.cpu1.l2cache.overall_misses::total 127749 # number of overall misses 1793system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 14838480 # number of ReadReq miss cycles 1794system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4527497 # number of ReadReq miss cycles 1795system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 735996245 # number of ReadReq miss cycles 1796system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1568239223 # number of ReadReq miss cycles 1797system.cpu1.l2cache.ReadReq_miss_latency::total 2323601445 # number of ReadReq miss cycles 1798system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 538393885 # number of UpgradeReq miss cycles 1799system.cpu1.l2cache.UpgradeReq_miss_latency::total 538393885 # number of UpgradeReq miss cycles 1800system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 458698584 # number of SCUpgradeReq miss cycles 1801system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 458698584 # number of SCUpgradeReq miss cycles 1802system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 502500 # number of SCUpgradeFailReq miss cycles 1803system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 502500 # number of SCUpgradeFailReq miss cycles 1804system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1371520229 # number of ReadExReq miss cycles 1805system.cpu1.l2cache.ReadExReq_miss_latency::total 1371520229 # number of ReadExReq miss cycles 1806system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 14838480 # number of demand (read+write) miss cycles 1807system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4527497 # number of demand (read+write) miss cycles 1808system.cpu1.l2cache.demand_miss_latency::cpu1.inst 735996245 # number of demand (read+write) miss cycles 1809system.cpu1.l2cache.demand_miss_latency::cpu1.data 2939759452 # number of demand (read+write) miss cycles 1810system.cpu1.l2cache.demand_miss_latency::total 3695121674 # number of demand (read+write) miss cycles 1811system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 14838480 # number of overall miss cycles 1812system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4527497 # number of overall miss cycles 1813system.cpu1.l2cache.overall_miss_latency::cpu1.inst 735996245 # number of overall miss cycles 1814system.cpu1.l2cache.overall_miss_latency::cpu1.data 2939759452 # number of overall miss cycles 1815system.cpu1.l2cache.overall_miss_latency::total 3695121674 # number of overall miss cycles 1816system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29440 # number of ReadReq accesses(hits+misses) 1817system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2891 # number of ReadReq accesses(hits+misses) 1818system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 948404 # number of ReadReq accesses(hits+misses) 1819system.cpu1.l2cache.ReadReq_accesses::cpu1.data 176042 # number of ReadReq accesses(hits+misses) 1820system.cpu1.l2cache.ReadReq_accesses::total 1156777 # number of ReadReq accesses(hits+misses) 1821system.cpu1.l2cache.Writeback_accesses::writebacks 117850 # number of Writeback accesses(hits+misses) 1822system.cpu1.l2cache.Writeback_accesses::total 117850 # number of Writeback accesses(hits+misses) 1823system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30038 # number of UpgradeReq accesses(hits+misses) 1824system.cpu1.l2cache.UpgradeReq_accesses::total 30038 # number of UpgradeReq accesses(hits+misses) 1825system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23675 # number of SCUpgradeReq accesses(hits+misses) 1826system.cpu1.l2cache.SCUpgradeReq_accesses::total 23675 # number of SCUpgradeReq accesses(hits+misses) 1827system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62553 # number of ReadExReq accesses(hits+misses) 1828system.cpu1.l2cache.ReadExReq_accesses::total 62553 # number of ReadExReq accesses(hits+misses) 1829system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29440 # number of demand (read+write) accesses 1830system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2891 # number of demand (read+write) accesses 1831system.cpu1.l2cache.demand_accesses::cpu1.inst 948404 # number of demand (read+write) accesses 1832system.cpu1.l2cache.demand_accesses::cpu1.data 238595 # number of demand (read+write) accesses 1833system.cpu1.l2cache.demand_accesses::total 1219330 # number of demand (read+write) accesses 1834system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29440 # number of overall (read+write) accesses 1835system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2891 # number of overall (read+write) accesses 1836system.cpu1.l2cache.overall_accesses::cpu1.inst 948404 # number of overall (read+write) accesses 1837system.cpu1.l2cache.overall_accesses::cpu1.data 238595 # number of overall (read+write) accesses 1838system.cpu1.l2cache.overall_accesses::total 1219330 # number of overall (read+write) accesses 1839system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021773 # miss rate for ReadReq accesses 1840system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.077482 # miss rate for ReadReq accesses 1841system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.022142 # miss rate for ReadReq accesses 1842system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.403284 # miss rate for ReadReq accesses 1843system.cpu1.l2cache.ReadReq_miss_rate::total 0.080275 # miss rate for ReadReq accesses 1844system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.945769 # miss rate for UpgradeReq accesses 1845system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.945769 # miss rate for UpgradeReq accesses 1846system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.959958 # miss rate for SCUpgradeReq accesses 1847system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.959958 # miss rate for SCUpgradeReq accesses 1848system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.557751 # miss rate for ReadExReq accesses 1849system.cpu1.l2cache.ReadExReq_miss_rate::total 0.557751 # miss rate for ReadExReq accesses 1850system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021773 # miss rate for demand accesses 1851system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.077482 # miss rate for demand accesses 1852system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.022142 # miss rate for demand accesses 1853system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.443781 # miss rate for demand accesses 1854system.cpu1.l2cache.demand_miss_rate::total 0.104770 # miss rate for demand accesses 1855system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021773 # miss rate for overall accesses 1856system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.077482 # miss rate for overall accesses 1857system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.022142 # miss rate for overall accesses 1858system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.443781 # miss rate for overall accesses 1859system.cpu1.l2cache.overall_miss_rate::total 0.104770 # miss rate for overall accesses 1860system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23148.954758 # average ReadReq miss latency 1861system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20212.040179 # average ReadReq miss latency 1862system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 35047.440238 # average ReadReq miss latency 1863system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22089.431974 # average ReadReq miss latency 1864system.cpu1.l2cache.ReadReq_avg_miss_latency::total 25022.630250 # average ReadReq miss latency 1865system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18951.525397 # average UpgradeReq miss latency 1866system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18951.525397 # average UpgradeReq miss latency 1867system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20182.979892 # average SCUpgradeReq miss latency 1868system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20182.979892 # average SCUpgradeReq miss latency | 1740system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id 1741system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6108 # Occupied blocks per task id 1742system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7366 # Occupied blocks per task id 1743system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.065063 # Percentage of cache occupancy per task id 1744system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002991 # Percentage of cache occupancy per task id 1745system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.840881 # Percentage of cache occupancy per task id 1746system.cpu1.l2cache.tags.tag_accesses 22523169 # Number of tag accesses 1747system.cpu1.l2cache.tags.data_accesses 22523169 # Number of data accesses 1748system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28304 # number of ReadReq hits 1749system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2558 # number of ReadReq hits 1750system.cpu1.l2cache.ReadReq_hits::cpu1.inst 928097 # number of ReadReq hits 1751system.cpu1.l2cache.ReadReq_hits::cpu1.data 105681 # number of ReadReq hits 1752system.cpu1.l2cache.ReadReq_hits::total 1064640 # number of ReadReq hits 1753system.cpu1.l2cache.Writeback_hits::writebacks 119832 # number of Writeback hits 1754system.cpu1.l2cache.Writeback_hits::total 119832 # number of Writeback hits 1755system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1525 # number of UpgradeReq hits 1756system.cpu1.l2cache.UpgradeReq_hits::total 1525 # number of UpgradeReq hits 1757system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 984 # number of SCUpgradeReq hits 1758system.cpu1.l2cache.SCUpgradeReq_hits::total 984 # number of SCUpgradeReq hits 1759system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27488 # number of ReadExReq hits 1760system.cpu1.l2cache.ReadExReq_hits::total 27488 # number of ReadExReq hits 1761system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28304 # number of demand (read+write) hits 1762system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2558 # number of demand (read+write) hits 1763system.cpu1.l2cache.demand_hits::cpu1.inst 928097 # number of demand (read+write) hits 1764system.cpu1.l2cache.demand_hits::cpu1.data 133169 # number of demand (read+write) hits 1765system.cpu1.l2cache.demand_hits::total 1092128 # number of demand (read+write) hits 1766system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 28304 # number of overall hits 1767system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2558 # number of overall hits 1768system.cpu1.l2cache.overall_hits::cpu1.inst 928097 # number of overall hits 1769system.cpu1.l2cache.overall_hits::cpu1.data 133169 # number of overall hits 1770system.cpu1.l2cache.overall_hits::total 1092128 # number of overall hits 1771system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 652 # number of ReadReq misses 1772system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 213 # number of ReadReq misses 1773system.cpu1.l2cache.ReadReq_misses::cpu1.inst 21019 # number of ReadReq misses 1774system.cpu1.l2cache.ReadReq_misses::cpu1.data 71648 # number of ReadReq misses 1775system.cpu1.l2cache.ReadReq_misses::total 93532 # number of ReadReq misses 1776system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28424 # number of UpgradeReq misses 1777system.cpu1.l2cache.UpgradeReq_misses::total 28424 # number of UpgradeReq misses 1778system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22729 # number of SCUpgradeReq misses 1779system.cpu1.l2cache.SCUpgradeReq_misses::total 22729 # number of SCUpgradeReq misses 1780system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34944 # number of ReadExReq misses 1781system.cpu1.l2cache.ReadExReq_misses::total 34944 # number of ReadExReq misses 1782system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 652 # number of demand (read+write) misses 1783system.cpu1.l2cache.demand_misses::cpu1.itb.walker 213 # number of demand (read+write) misses 1784system.cpu1.l2cache.demand_misses::cpu1.inst 21019 # number of demand (read+write) misses 1785system.cpu1.l2cache.demand_misses::cpu1.data 106592 # number of demand (read+write) misses 1786system.cpu1.l2cache.demand_misses::total 128476 # number of demand (read+write) misses 1787system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 652 # number of overall misses 1788system.cpu1.l2cache.overall_misses::cpu1.itb.walker 213 # number of overall misses 1789system.cpu1.l2cache.overall_misses::cpu1.inst 21019 # number of overall misses 1790system.cpu1.l2cache.overall_misses::cpu1.data 106592 # number of overall misses 1791system.cpu1.l2cache.overall_misses::total 128476 # number of overall misses 1792system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 14243728 # number of ReadReq miss cycles 1793system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4276499 # number of ReadReq miss cycles 1794system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 737905240 # number of ReadReq miss cycles 1795system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1619303994 # number of ReadReq miss cycles 1796system.cpu1.l2cache.ReadReq_miss_latency::total 2375729461 # number of ReadReq miss cycles 1797system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 539163396 # number of UpgradeReq miss cycles 1798system.cpu1.l2cache.UpgradeReq_miss_latency::total 539163396 # number of UpgradeReq miss cycles 1799system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 459339096 # number of SCUpgradeReq miss cycles 1800system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 459339096 # number of SCUpgradeReq miss cycles 1801system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 256500 # number of SCUpgradeFailReq miss cycles 1802system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 256500 # number of SCUpgradeFailReq miss cycles 1803system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1382755927 # number of ReadExReq miss cycles 1804system.cpu1.l2cache.ReadExReq_miss_latency::total 1382755927 # number of ReadExReq miss cycles 1805system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 14243728 # number of demand (read+write) miss cycles 1806system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4276499 # number of demand (read+write) miss cycles 1807system.cpu1.l2cache.demand_miss_latency::cpu1.inst 737905240 # number of demand (read+write) miss cycles 1808system.cpu1.l2cache.demand_miss_latency::cpu1.data 3002059921 # number of demand (read+write) miss cycles 1809system.cpu1.l2cache.demand_miss_latency::total 3758485388 # number of demand (read+write) miss cycles 1810system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 14243728 # number of overall miss cycles 1811system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4276499 # number of overall miss cycles 1812system.cpu1.l2cache.overall_miss_latency::cpu1.inst 737905240 # number of overall miss cycles 1813system.cpu1.l2cache.overall_miss_latency::cpu1.data 3002059921 # number of overall miss cycles 1814system.cpu1.l2cache.overall_miss_latency::total 3758485388 # number of overall miss cycles 1815system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 28956 # number of ReadReq accesses(hits+misses) 1816system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2771 # number of ReadReq accesses(hits+misses) 1817system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 949116 # number of ReadReq accesses(hits+misses) 1818system.cpu1.l2cache.ReadReq_accesses::cpu1.data 177329 # number of ReadReq accesses(hits+misses) 1819system.cpu1.l2cache.ReadReq_accesses::total 1158172 # number of ReadReq accesses(hits+misses) 1820system.cpu1.l2cache.Writeback_accesses::writebacks 119832 # number of Writeback accesses(hits+misses) 1821system.cpu1.l2cache.Writeback_accesses::total 119832 # number of Writeback accesses(hits+misses) 1822system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29949 # number of UpgradeReq accesses(hits+misses) 1823system.cpu1.l2cache.UpgradeReq_accesses::total 29949 # number of UpgradeReq accesses(hits+misses) 1824system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23713 # number of SCUpgradeReq accesses(hits+misses) 1825system.cpu1.l2cache.SCUpgradeReq_accesses::total 23713 # number of SCUpgradeReq accesses(hits+misses) 1826system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62432 # number of ReadExReq accesses(hits+misses) 1827system.cpu1.l2cache.ReadExReq_accesses::total 62432 # number of ReadExReq accesses(hits+misses) 1828system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 28956 # number of demand (read+write) accesses 1829system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2771 # number of demand (read+write) accesses 1830system.cpu1.l2cache.demand_accesses::cpu1.inst 949116 # number of demand (read+write) accesses 1831system.cpu1.l2cache.demand_accesses::cpu1.data 239761 # number of demand (read+write) accesses 1832system.cpu1.l2cache.demand_accesses::total 1220604 # number of demand (read+write) accesses 1833system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 28956 # number of overall (read+write) accesses 1834system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2771 # number of overall (read+write) accesses 1835system.cpu1.l2cache.overall_accesses::cpu1.inst 949116 # number of overall (read+write) accesses 1836system.cpu1.l2cache.overall_accesses::cpu1.data 239761 # number of overall (read+write) accesses 1837system.cpu1.l2cache.overall_accesses::total 1220604 # number of overall (read+write) accesses 1838system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022517 # miss rate for ReadReq accesses 1839system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.076868 # miss rate for ReadReq accesses 1840system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.022146 # miss rate for ReadReq accesses 1841system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.404040 # miss rate for ReadReq accesses 1842system.cpu1.l2cache.ReadReq_miss_rate::total 0.080758 # miss rate for ReadReq accesses 1843system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.949080 # miss rate for UpgradeReq accesses 1844system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.949080 # miss rate for UpgradeReq accesses 1845system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.958504 # miss rate for SCUpgradeReq accesses 1846system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.958504 # miss rate for SCUpgradeReq accesses 1847system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.559713 # miss rate for ReadExReq accesses 1848system.cpu1.l2cache.ReadExReq_miss_rate::total 0.559713 # miss rate for ReadExReq accesses 1849system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022517 # miss rate for demand accesses 1850system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.076868 # miss rate for demand accesses 1851system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.022146 # miss rate for demand accesses 1852system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.444576 # miss rate for demand accesses 1853system.cpu1.l2cache.demand_miss_rate::total 0.105256 # miss rate for demand accesses 1854system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022517 # miss rate for overall accesses 1855system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.076868 # miss rate for overall accesses 1856system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.022146 # miss rate for overall accesses 1857system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.444576 # miss rate for overall accesses 1858system.cpu1.l2cache.overall_miss_rate::total 0.105256 # miss rate for overall accesses 1859system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21846.208589 # average ReadReq miss latency 1860system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20077.460094 # average ReadReq miss latency 1861system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 35106.581664 # average ReadReq miss latency 1862system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22600.826178 # average ReadReq miss latency 1863system.cpu1.l2cache.ReadReq_avg_miss_latency::total 25400.178132 # average ReadReq miss latency 1864system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18968.596820 # average UpgradeReq miss latency 1865system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18968.596820 # average UpgradeReq miss latency 1866system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20209.384311 # average SCUpgradeReq miss latency 1867system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20209.384311 # average SCUpgradeReq miss latency |
| 1869system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency 1870system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency | 1868system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency 1869system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency |
| 1871system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39310.964172 # average ReadExReq miss latency 1872system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39310.964172 # average ReadExReq miss latency 1873system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23148.954758 # average overall miss latency 1874system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20212.040179 # average overall miss latency 1875system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35047.440238 # average overall miss latency 1876system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27763.962941 # average overall miss latency 1877system.cpu1.l2cache.demand_avg_miss_latency::total 28924.857917 # average overall miss latency 1878system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23148.954758 # average overall miss latency 1879system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20212.040179 # average overall miss latency 1880system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35047.440238 # average overall miss latency 1881system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27763.962941 # average overall miss latency 1882system.cpu1.l2cache.overall_avg_miss_latency::total 28924.857917 # average overall miss latency 1883system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 1870system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39570.625200 # average ReadExReq miss latency 1871system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39570.625200 # average ReadExReq miss latency 1872system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21846.208589 # average overall miss latency 1873system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20077.460094 # average overall miss latency 1874system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35106.581664 # average overall miss latency 1875system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28164.026578 # average overall miss latency 1876system.cpu1.l2cache.demand_avg_miss_latency::total 29254.377378 # average overall miss latency 1877system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21846.208589 # average overall miss latency 1878system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20077.460094 # average overall miss latency 1879system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35106.581664 # average overall miss latency 1880system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28164.026578 # average overall miss latency 1881system.cpu1.l2cache.overall_avg_miss_latency::total 29254.377378 # average overall miss latency 1882system.cpu1.l2cache.blocked_cycles::no_mshrs 106 # number of cycles access was blocked |
| 1884system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1883system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1885system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked | 1884system.cpu1.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked |
| 1886system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1885system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1887system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 0 # average number of cycles each access was blocked | 1886system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 26.500000 # average number of cycles each access was blocked |
| 1888system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1889system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1890system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 1887system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1888system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1889system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 1891system.cpu1.l2cache.writebacks::writebacks 31909 # number of writebacks 1892system.cpu1.l2cache.writebacks::total 31909 # number of writebacks 1893system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 25 # number of ReadReq MSHR hits 1894system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 89 # number of ReadReq MSHR hits 1895system.cpu1.l2cache.ReadReq_mshr_hits::total 114 # number of ReadReq MSHR hits 1896system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 233 # number of ReadExReq MSHR hits 1897system.cpu1.l2cache.ReadExReq_mshr_hits::total 233 # number of ReadExReq MSHR hits 1898system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 25 # number of demand (read+write) MSHR hits 1899system.cpu1.l2cache.demand_mshr_hits::cpu1.data 322 # number of demand (read+write) MSHR hits 1900system.cpu1.l2cache.demand_mshr_hits::total 347 # number of demand (read+write) MSHR hits 1901system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 25 # number of overall MSHR hits 1902system.cpu1.l2cache.overall_mshr_hits::cpu1.data 322 # number of overall MSHR hits 1903system.cpu1.l2cache.overall_mshr_hits::total 347 # number of overall MSHR hits 1904system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 641 # number of ReadReq MSHR misses 1905system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 224 # number of ReadReq MSHR misses 1906system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 20975 # number of ReadReq MSHR misses 1907system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70906 # number of ReadReq MSHR misses 1908system.cpu1.l2cache.ReadReq_mshr_misses::total 92746 # number of ReadReq MSHR misses 1909system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 23372 # number of HardPFReq MSHR misses 1910system.cpu1.l2cache.HardPFReq_mshr_misses::total 23372 # number of HardPFReq MSHR misses 1911system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28409 # number of UpgradeReq MSHR misses 1912system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28409 # number of UpgradeReq MSHR misses 1913system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22727 # number of SCUpgradeReq MSHR misses 1914system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22727 # number of SCUpgradeReq MSHR misses 1915system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34656 # number of ReadExReq MSHR misses 1916system.cpu1.l2cache.ReadExReq_mshr_misses::total 34656 # number of ReadExReq MSHR misses 1917system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 641 # number of demand (read+write) MSHR misses 1918system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 224 # number of demand (read+write) MSHR misses 1919system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 20975 # number of demand (read+write) MSHR misses 1920system.cpu1.l2cache.demand_mshr_misses::cpu1.data 105562 # number of demand (read+write) MSHR misses 1921system.cpu1.l2cache.demand_mshr_misses::total 127402 # number of demand (read+write) MSHR misses 1922system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 641 # number of overall MSHR misses 1923system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 224 # number of overall MSHR misses 1924system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 20975 # number of overall MSHR misses 1925system.cpu1.l2cache.overall_mshr_misses::cpu1.data 105562 # number of overall MSHR misses 1926system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 23372 # number of overall MSHR misses 1927system.cpu1.l2cache.overall_mshr_misses::total 150774 # number of overall MSHR misses | 1890system.cpu1.l2cache.writebacks::writebacks 32037 # number of writebacks 1891system.cpu1.l2cache.writebacks::total 32037 # number of writebacks 1892system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 22 # number of ReadReq MSHR hits 1893system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 90 # number of ReadReq MSHR hits 1894system.cpu1.l2cache.ReadReq_mshr_hits::total 112 # number of ReadReq MSHR hits 1895system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 230 # number of ReadExReq MSHR hits 1896system.cpu1.l2cache.ReadExReq_mshr_hits::total 230 # number of ReadExReq MSHR hits 1897system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 22 # number of demand (read+write) MSHR hits 1898system.cpu1.l2cache.demand_mshr_hits::cpu1.data 320 # number of demand (read+write) MSHR hits 1899system.cpu1.l2cache.demand_mshr_hits::total 342 # number of demand (read+write) MSHR hits 1900system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 22 # number of overall MSHR hits 1901system.cpu1.l2cache.overall_mshr_hits::cpu1.data 320 # number of overall MSHR hits 1902system.cpu1.l2cache.overall_mshr_hits::total 342 # number of overall MSHR hits 1903system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 652 # number of ReadReq MSHR misses 1904system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 213 # number of ReadReq MSHR misses 1905system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 20997 # number of ReadReq MSHR misses 1906system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 71558 # number of ReadReq MSHR misses 1907system.cpu1.l2cache.ReadReq_mshr_misses::total 93420 # number of ReadReq MSHR misses 1908system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 23227 # number of HardPFReq MSHR misses 1909system.cpu1.l2cache.HardPFReq_mshr_misses::total 23227 # number of HardPFReq MSHR misses 1910system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28424 # number of UpgradeReq MSHR misses 1911system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28424 # number of UpgradeReq MSHR misses 1912system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22729 # number of SCUpgradeReq MSHR misses 1913system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22729 # number of SCUpgradeReq MSHR misses 1914system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34714 # number of ReadExReq MSHR misses 1915system.cpu1.l2cache.ReadExReq_mshr_misses::total 34714 # number of ReadExReq MSHR misses 1916system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 652 # number of demand (read+write) MSHR misses 1917system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 213 # number of demand (read+write) MSHR misses 1918system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 20997 # number of demand (read+write) MSHR misses 1919system.cpu1.l2cache.demand_mshr_misses::cpu1.data 106272 # number of demand (read+write) MSHR misses 1920system.cpu1.l2cache.demand_mshr_misses::total 128134 # number of demand (read+write) MSHR misses 1921system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 652 # number of overall MSHR misses 1922system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 213 # number of overall MSHR misses 1923system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 20997 # number of overall MSHR misses 1924system.cpu1.l2cache.overall_mshr_misses::cpu1.data 106272 # number of overall MSHR misses 1925system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 23227 # number of overall MSHR misses 1926system.cpu1.l2cache.overall_mshr_misses::total 151361 # number of overall MSHR misses |
| 1928system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable | 1927system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable |
| 1929system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14605 # number of ReadReq MSHR uncacheable 1930system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14717 # number of ReadReq MSHR uncacheable 1931system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11936 # number of WriteReq MSHR uncacheable 1932system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11936 # number of WriteReq MSHR uncacheable | 1928system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14604 # number of ReadReq MSHR uncacheable 1929system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14716 # number of ReadReq MSHR uncacheable 1930system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11935 # number of WriteReq MSHR uncacheable 1931system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11935 # number of WriteReq MSHR uncacheable |
| 1933system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses | 1932system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses |
| 1934system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26541 # number of overall MSHR uncacheable misses 1935system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26653 # number of overall MSHR uncacheable misses 1936system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 10662992 # number of ReadReq MSHR miss cycles 1937system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3070499 # number of ReadReq MSHR miss cycles 1938system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 597837255 # number of ReadReq MSHR miss cycles 1939system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1104689269 # number of ReadReq MSHR miss cycles 1940system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1716260015 # number of ReadReq MSHR miss cycles 1941system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 913442152 # number of HardPFReq MSHR miss cycles 1942system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 913442152 # number of HardPFReq MSHR miss cycles 1943system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 453224001 # number of UpgradeReq MSHR miss cycles 1944system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 453224001 # number of UpgradeReq MSHR miss cycles 1945system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 342962233 # number of SCUpgradeReq MSHR miss cycles 1946system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 342962233 # number of SCUpgradeReq MSHR miss cycles 1947system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 437500 # number of SCUpgradeFailReq MSHR miss cycles 1948system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 437500 # number of SCUpgradeFailReq MSHR miss cycles 1949system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1116530031 # number of ReadExReq MSHR miss cycles 1950system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1116530031 # number of ReadExReq MSHR miss cycles 1951system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 10662992 # number of demand (read+write) MSHR miss cycles 1952system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3070499 # number of demand (read+write) MSHR miss cycles 1953system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 597837255 # number of demand (read+write) MSHR miss cycles 1954system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2221219300 # number of demand (read+write) MSHR miss cycles 1955system.cpu1.l2cache.demand_mshr_miss_latency::total 2832790046 # number of demand (read+write) MSHR miss cycles 1956system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 10662992 # number of overall MSHR miss cycles 1957system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3070499 # number of overall MSHR miss cycles 1958system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 597837255 # number of overall MSHR miss cycles 1959system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2221219300 # number of overall MSHR miss cycles 1960system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 913442152 # number of overall MSHR miss cycles 1961system.cpu1.l2cache.overall_mshr_miss_latency::total 3746232198 # number of overall MSHR miss cycles 1962system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9363750 # number of ReadReq MSHR uncacheable cycles 1963system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2205259000 # number of ReadReq MSHR uncacheable cycles 1964system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2214622750 # number of ReadReq MSHR uncacheable cycles 1965system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1754356999 # number of WriteReq MSHR uncacheable cycles 1966system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1754356999 # number of WriteReq MSHR uncacheable cycles 1967system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9363750 # number of overall MSHR uncacheable cycles 1968system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3959615999 # number of overall MSHR uncacheable cycles 1969system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3968979749 # number of overall MSHR uncacheable cycles 1970system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021773 # mshr miss rate for ReadReq accesses 1971system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.077482 # mshr miss rate for ReadReq accesses 1972system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.022116 # mshr miss rate for ReadReq accesses 1973system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.402779 # mshr miss rate for ReadReq accesses 1974system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.080176 # mshr miss rate for ReadReq accesses | 1933system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26539 # number of overall MSHR uncacheable misses 1934system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26651 # number of overall MSHR uncacheable misses 1935system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 9997244 # number of ReadReq MSHR miss cycles 1936system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2891999 # number of ReadReq MSHR miss cycles 1937system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 599685760 # number of ReadReq MSHR miss cycles 1938system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1151439996 # number of ReadReq MSHR miss cycles 1939system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1764014999 # number of ReadReq MSHR miss cycles 1940system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 924666076 # number of HardPFReq MSHR miss cycles 1941system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 924666076 # number of HardPFReq MSHR miss cycles 1942system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 453146005 # number of UpgradeReq MSHR miss cycles 1943system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 453146005 # number of UpgradeReq MSHR miss cycles 1944system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 343401219 # number of SCUpgradeReq MSHR miss cycles 1945system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 343401219 # number of SCUpgradeReq MSHR miss cycles 1946system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 217500 # number of SCUpgradeFailReq MSHR miss cycles 1947system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 217500 # number of SCUpgradeFailReq MSHR miss cycles 1948system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1124328801 # number of ReadExReq MSHR miss cycles 1949system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1124328801 # number of ReadExReq MSHR miss cycles 1950system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 9997244 # number of demand (read+write) MSHR miss cycles 1951system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2891999 # number of demand (read+write) MSHR miss cycles 1952system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 599685760 # number of demand (read+write) MSHR miss cycles 1953system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2275768797 # number of demand (read+write) MSHR miss cycles 1954system.cpu1.l2cache.demand_mshr_miss_latency::total 2888343800 # number of demand (read+write) MSHR miss cycles 1955system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 9997244 # number of overall MSHR miss cycles 1956system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2891999 # number of overall MSHR miss cycles 1957system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 599685760 # number of overall MSHR miss cycles 1958system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2275768797 # number of overall MSHR miss cycles 1959system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 924666076 # number of overall MSHR miss cycles 1960system.cpu1.l2cache.overall_mshr_miss_latency::total 3813009876 # number of overall MSHR miss cycles 1961system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9435750 # number of ReadReq MSHR uncacheable cycles 1962system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2205092749 # number of ReadReq MSHR uncacheable cycles 1963system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2214528499 # number of ReadReq MSHR uncacheable cycles 1964system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1754280499 # number of WriteReq MSHR uncacheable cycles 1965system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1754280499 # number of WriteReq MSHR uncacheable cycles 1966system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9435750 # number of overall MSHR uncacheable cycles 1967system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3959373248 # number of overall MSHR uncacheable cycles 1968system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3968808998 # number of overall MSHR uncacheable cycles 1969system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022517 # mshr miss rate for ReadReq accesses 1970system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.076868 # mshr miss rate for ReadReq accesses 1971system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.022123 # mshr miss rate for ReadReq accesses 1972system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.403532 # mshr miss rate for ReadReq accesses 1973system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.080662 # mshr miss rate for ReadReq accesses |
| 1975system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1976system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1974system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1975system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1977system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.945769 # mshr miss rate for UpgradeReq accesses 1978system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.945769 # mshr miss rate for UpgradeReq accesses 1979system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.959958 # mshr miss rate for SCUpgradeReq accesses 1980system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.959958 # mshr miss rate for SCUpgradeReq accesses 1981system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554026 # mshr miss rate for ReadExReq accesses 1982system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554026 # mshr miss rate for ReadExReq accesses 1983system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021773 # mshr miss rate for demand accesses 1984system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.077482 # mshr miss rate for demand accesses 1985system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.022116 # mshr miss rate for demand accesses 1986system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.442432 # mshr miss rate for demand accesses 1987system.cpu1.l2cache.demand_mshr_miss_rate::total 0.104485 # mshr miss rate for demand accesses 1988system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021773 # mshr miss rate for overall accesses 1989system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.077482 # mshr miss rate for overall accesses 1990system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.022116 # mshr miss rate for overall accesses 1991system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.442432 # mshr miss rate for overall accesses | 1976system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.949080 # mshr miss rate for UpgradeReq accesses 1977system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.949080 # mshr miss rate for UpgradeReq accesses 1978system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.958504 # mshr miss rate for SCUpgradeReq accesses 1979system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.958504 # mshr miss rate for SCUpgradeReq accesses 1980system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.556029 # mshr miss rate for ReadExReq accesses 1981system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.556029 # mshr miss rate for ReadExReq accesses 1982system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022517 # mshr miss rate for demand accesses 1983system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.076868 # mshr miss rate for demand accesses 1984system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.022123 # mshr miss rate for demand accesses 1985system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443241 # mshr miss rate for demand accesses 1986system.cpu1.l2cache.demand_mshr_miss_rate::total 0.104976 # mshr miss rate for demand accesses 1987system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022517 # mshr miss rate for overall accesses 1988system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.076868 # mshr miss rate for overall accesses 1989system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.022123 # mshr miss rate for overall accesses 1990system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443241 # mshr miss rate for overall accesses |
| 1992system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1991system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1993system.cpu1.l2cache.overall_mshr_miss_rate::total 0.123653 # mshr miss rate for overall accesses 1994system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16634.932917 # average ReadReq mshr miss latency 1995system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13707.584821 # average ReadReq mshr miss latency 1996system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28502.372110 # average ReadReq mshr miss latency 1997system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15579.630342 # average ReadReq mshr miss latency 1998system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18504.949162 # average ReadReq mshr miss latency 1999system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39082.755092 # average HardPFReq mshr miss latency 2000system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39082.755092 # average HardPFReq mshr miss latency 2001system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15953.535887 # average UpgradeReq mshr miss latency 2002system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15953.535887 # average UpgradeReq mshr miss latency 2003system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15090.519338 # average SCUpgradeReq mshr miss latency 2004system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15090.519338 # average SCUpgradeReq mshr miss latency | 1992system.cpu1.l2cache.overall_mshr_miss_rate::total 0.124005 # mshr miss rate for overall accesses 1993system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15333.196319 # average ReadReq mshr miss latency 1994system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13577.460094 # average ReadReq mshr miss latency 1995system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28560.544840 # average ReadReq mshr miss latency 1996system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 16091.003046 # average ReadReq mshr miss latency 1997system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18882.626836 # average ReadReq mshr miss latency 1998system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39809.965816 # average HardPFReq mshr miss latency 1999system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39809.965816 # average HardPFReq mshr miss latency 2000system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15942.372819 # average UpgradeReq mshr miss latency 2001system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15942.372819 # average UpgradeReq mshr miss latency 2002system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15108.505390 # average SCUpgradeReq mshr miss latency 2003system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15108.505390 # average SCUpgradeReq mshr miss latency |
| 2005system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency 2006system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency | 2004system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency 2005system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency |
| 2007system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32217.510128 # average ReadExReq mshr miss latency 2008system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32217.510128 # average ReadExReq mshr miss latency 2009system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16634.932917 # average overall mshr miss latency 2010system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13707.584821 # average overall mshr miss latency 2011system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28502.372110 # average overall mshr miss latency 2012system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21041.845550 # average overall mshr miss latency 2013system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22235.051616 # average overall mshr miss latency 2014system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16634.932917 # average overall mshr miss latency 2015system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13707.584821 # average overall mshr miss latency 2016system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28502.372110 # average overall mshr miss latency 2017system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21041.845550 # average overall mshr miss latency 2018system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39082.755092 # average overall mshr miss latency 2019system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24846.672490 # average overall mshr miss latency 2020system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83604.910714 # average ReadReq mshr uncacheable latency 2021system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150993.426909 # average ReadReq mshr uncacheable latency 2022system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 150480.583679 # average ReadReq mshr uncacheable latency 2023system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146980.311578 # average WriteReq mshr uncacheable latency 2024system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 146980.311578 # average WriteReq mshr uncacheable latency 2025system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83604.910714 # average overall mshr uncacheable latency 2026system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 149188.651483 # average overall mshr uncacheable latency 2027system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 148913.058530 # average overall mshr uncacheable latency | 2006system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32388.339027 # average ReadExReq mshr miss latency 2007system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32388.339027 # average ReadExReq mshr miss latency 2008system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15333.196319 # average overall mshr miss latency 2009system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13577.460094 # average overall mshr miss latency 2010system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28560.544840 # average overall mshr miss latency 2011system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21414.566367 # average overall mshr miss latency 2012system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22541.587713 # average overall mshr miss latency 2013system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15333.196319 # average overall mshr miss latency 2014system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13577.460094 # average overall mshr miss latency 2015system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28560.544840 # average overall mshr miss latency 2016system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21414.566367 # average overall mshr miss latency 2017system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39809.965816 # average overall mshr miss latency 2018system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25191.495009 # average overall mshr miss latency 2019system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84247.767857 # average ReadReq mshr uncacheable latency 2020system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150992.382156 # average ReadReq mshr uncacheable latency 2021system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 150484.404662 # average ReadReq mshr uncacheable latency 2022system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146986.216925 # average WriteReq mshr uncacheable latency 2023system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 146986.216925 # average WriteReq mshr uncacheable latency 2024system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84247.767857 # average overall mshr uncacheable latency 2025system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 149190.747504 # average overall mshr uncacheable latency 2026system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 148917.826648 # average overall mshr uncacheable latency |
| 2028system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 2027system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2029system.cpu1.toL2Bus.trans_dist::ReadReq 1570481 # Transaction distribution 2030system.cpu1.toL2Bus.trans_dist::ReadResp 1215284 # Transaction distribution 2031system.cpu1.toL2Bus.trans_dist::WriteReq 31021 # Transaction distribution 2032system.cpu1.toL2Bus.trans_dist::WriteResp 11936 # Transaction distribution 2033system.cpu1.toL2Bus.trans_dist::Writeback 117850 # Transaction distribution 2034system.cpu1.toL2Bus.trans_dist::HardPFReq 29116 # Transaction distribution 2035system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution 2036system.cpu1.toL2Bus.trans_dist::UpgradeReq 76106 # Transaction distribution 2037system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42118 # Transaction distribution 2038system.cpu1.toL2Bus.trans_dist::UpgradeResp 86519 # Transaction distribution 2039system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution 2040system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 16 # Transaction distribution 2041system.cpu1.toL2Bus.trans_dist::ReadExReq 85085 # Transaction distribution 2042system.cpu1.toL2Bus.trans_dist::ReadExResp 67041 # Transaction distribution 2043system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1897032 # Packet count per connected master and slave (bytes) 2044system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 831140 # Packet count per connected master and slave (bytes) 2045system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7228 # Packet count per connected master and slave (bytes) 2046system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62942 # Packet count per connected master and slave (bytes) 2047system.cpu1.toL2Bus.pkt_count::total 2798342 # Packet count per connected master and slave (bytes) 2048system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60705024 # Cumulative packet size per connected master and slave (bytes) 2049system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25653404 # Cumulative packet size per connected master and slave (bytes) 2050system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11564 # Cumulative packet size per connected master and slave (bytes) 2051system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 117760 # Cumulative packet size per connected master and slave (bytes) 2052system.cpu1.toL2Bus.pkt_size::total 86487752 # Cumulative packet size per connected master and slave (bytes) 2053system.cpu1.toL2Bus.snoops 646083 # Total snoops (count) 2054system.cpu1.toL2Bus.snoop_fanout::samples 1988037 # Request fanout histogram 2055system.cpu1.toL2Bus.snoop_fanout::mean 1.303225 # Request fanout histogram 2056system.cpu1.toL2Bus.snoop_fanout::stdev 0.459652 # Request fanout histogram | 2028system.cpu1.toL2Bus.trans_dist::ReadReq 1571398 # Transaction distribution 2029system.cpu1.toL2Bus.trans_dist::ReadResp 1216942 # Transaction distribution 2030system.cpu1.toL2Bus.trans_dist::WriteReq 31019 # Transaction distribution 2031system.cpu1.toL2Bus.trans_dist::WriteResp 11935 # Transaction distribution 2032system.cpu1.toL2Bus.trans_dist::Writeback 119832 # Transaction distribution 2033system.cpu1.toL2Bus.trans_dist::HardPFReq 28997 # Transaction distribution 2034system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36259 # Transaction distribution 2035system.cpu1.toL2Bus.trans_dist::UpgradeReq 76686 # Transaction distribution 2036system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42144 # Transaction distribution 2037system.cpu1.toL2Bus.trans_dist::UpgradeResp 86299 # Transaction distribution 2038system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution 2039system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution 2040system.cpu1.toL2Bus.trans_dist::ReadExReq 85106 # Transaction distribution 2041system.cpu1.toL2Bus.trans_dist::ReadExResp 66899 # Transaction distribution 2042system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1898456 # Packet count per connected master and slave (bytes) 2043system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 835008 # Packet count per connected master and slave (bytes) 2044system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7108 # Packet count per connected master and slave (bytes) 2045system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62262 # Packet count per connected master and slave (bytes) 2046system.cpu1.toL2Bus.pkt_count::total 2802834 # Packet count per connected master and slave (bytes) 2047system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60750592 # Cumulative packet size per connected master and slave (bytes) 2048system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25843924 # Cumulative packet size per connected master and slave (bytes) 2049system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11084 # Cumulative packet size per connected master and slave (bytes) 2050system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 115824 # Cumulative packet size per connected master and slave (bytes) 2051system.cpu1.toL2Bus.pkt_size::total 86721424 # Cumulative packet size per connected master and slave (bytes) 2052system.cpu1.toL2Bus.snoops 645948 # Total snoops (count) 2053system.cpu1.toL2Bus.snoop_fanout::samples 1991449 # Request fanout histogram 2054system.cpu1.toL2Bus.snoop_fanout::mean 1.302505 # Request fanout histogram 2055system.cpu1.toL2Bus.snoop_fanout::stdev 0.459343 # Request fanout histogram |
| 2057system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2058system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 2056system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2057system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 2059system.cpu1.toL2Bus.snoop_fanout::1 1385215 69.68% 69.68% # Request fanout histogram 2060system.cpu1.toL2Bus.snoop_fanout::2 602822 30.32% 100.00% # Request fanout histogram | 2058system.cpu1.toL2Bus.snoop_fanout::1 1389026 69.75% 69.75% # Request fanout histogram 2059system.cpu1.toL2Bus.snoop_fanout::2 602423 30.25% 100.00% # Request fanout histogram |
| 2061system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2062system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2063system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 2060system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2061system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2062system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 2064system.cpu1.toL2Bus.snoop_fanout::total 1988037 # Request fanout histogram 2065system.cpu1.toL2Bus.reqLayer0.occupancy 835355978 # Layer occupancy (ticks) | 2063system.cpu1.toL2Bus.snoop_fanout::total 1991449 # Request fanout histogram 2064system.cpu1.toL2Bus.reqLayer0.occupancy 839147473 # Layer occupancy (ticks) |
| 2066system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 2065system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 2067system.cpu1.toL2Bus.snoopLayer0.occupancy 80571000 # Layer occupancy (ticks) | 2066system.cpu1.toL2Bus.snoopLayer0.occupancy 80233998 # Layer occupancy (ticks) |
| 2068system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2067system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2069system.cpu1.toL2Bus.respLayer0.occupancy 1423456915 # Layer occupancy (ticks) | 2068system.cpu1.toL2Bus.respLayer0.occupancy 1424533908 # Layer occupancy (ticks) |
| 2070system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 2069system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 2071system.cpu1.toL2Bus.respLayer1.occupancy 410007475 # Layer occupancy (ticks) | 2070system.cpu1.toL2Bus.respLayer1.occupancy 411735495 # Layer occupancy (ticks) |
| 2072system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 2071system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 2073system.cpu1.toL2Bus.respLayer2.occupancy 4338499 # Layer occupancy (ticks) | 2072system.cpu1.toL2Bus.respLayer2.occupancy 4337999 # Layer occupancy (ticks) |
| 2074system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 2073system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2075system.cpu1.toL2Bus.respLayer3.occupancy 33513487 # Layer occupancy (ticks) | 2074system.cpu1.toL2Bus.respLayer3.occupancy 33317735 # Layer occupancy (ticks) |
| 2076system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2077system.iobus.trans_dist::ReadReq 31003 # Transaction distribution 2078system.iobus.trans_dist::ReadResp 31003 # Transaction distribution 2079system.iobus.trans_dist::WriteReq 59422 # Transaction distribution 2080system.iobus.trans_dist::WriteResp 23198 # Transaction distribution 2081system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 2082system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) 2083system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) --- 80 unchanged lines hidden (view full) --- 2164system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2165system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2166system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2167system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2168system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2169system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2170system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2171system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 2075system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2076system.iobus.trans_dist::ReadReq 31003 # Transaction distribution 2077system.iobus.trans_dist::ReadResp 31003 # Transaction distribution 2078system.iobus.trans_dist::WriteReq 59422 # Transaction distribution 2079system.iobus.trans_dist::WriteResp 23198 # Transaction distribution 2080system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 2081system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) 2082system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) --- 80 unchanged lines hidden (view full) --- 2163system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2164system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2165system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2166system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2167system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2168system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2169system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2170system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 2172system.iobus.reqLayer27.occupancy 198954212 # Layer occupancy (ticks) | 2171system.iobus.reqLayer27.occupancy 198974708 # Layer occupancy (ticks) |
| 2173system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2174system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2175system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2176system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) 2177system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 2172system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2173system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2174system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2175system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) 2176system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2178system.iobus.respLayer3.occupancy 36786767 # Layer occupancy (ticks) | 2177system.iobus.respLayer3.occupancy 36789763 # Layer occupancy (ticks) |
| 2179system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2180system.iocache.tags.replacements 36433 # number of replacements | 2178system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2179system.iocache.tags.replacements 36433 # number of replacements |
| 2181system.iocache.tags.tagsinuse 14.479130 # Cycle average of tags in use | 2180system.iocache.tags.tagsinuse 14.479314 # Cycle average of tags in use |
| 2182system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2183system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. 2184system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 2181system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2182system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. 2183system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 2185system.iocache.tags.warmup_cycle 270363169000 # Cycle when the warmup percentage was hit. 2186system.iocache.tags.occ_blocks::realview.ide 14.479130 # Average occupied blocks per requestor 2187system.iocache.tags.occ_percent::realview.ide 0.904946 # Average percentage of cache occupancy 2188system.iocache.tags.occ_percent::total 0.904946 # Average percentage of cache occupancy | 2184system.iocache.tags.warmup_cycle 270323444000 # Cycle when the warmup percentage was hit. 2185system.iocache.tags.occ_blocks::realview.ide 14.479314 # Average occupied blocks per requestor 2186system.iocache.tags.occ_percent::realview.ide 0.904957 # Average percentage of cache occupancy 2187system.iocache.tags.occ_percent::total 0.904957 # Average percentage of cache occupancy |
| 2189system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2190system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2191system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2192system.iocache.tags.tag_accesses 328203 # Number of tag accesses 2193system.iocache.tags.data_accesses 328203 # Number of data accesses 2194system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses 2195system.iocache.ReadReq_misses::total 243 # number of ReadReq misses 2196system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 2197system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses 2198system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses 2199system.iocache.demand_misses::total 243 # number of demand (read+write) misses 2200system.iocache.overall_misses::realview.ide 243 # number of overall misses 2201system.iocache.overall_misses::total 243 # number of overall misses | 2188system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2189system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2190system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2191system.iocache.tags.tag_accesses 328203 # Number of tag accesses 2192system.iocache.tags.data_accesses 328203 # Number of data accesses 2193system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses 2194system.iocache.ReadReq_misses::total 243 # number of ReadReq misses 2195system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 2196system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses 2197system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses 2198system.iocache.demand_misses::total 243 # number of demand (read+write) misses 2199system.iocache.overall_misses::realview.ide 243 # number of overall misses 2200system.iocache.overall_misses::total 243 # number of overall misses |
| 2202system.iocache.ReadReq_miss_latency::realview.ide 31382127 # number of ReadReq miss cycles 2203system.iocache.ReadReq_miss_latency::total 31382127 # number of ReadReq miss cycles 2204system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6655722318 # number of WriteInvalidateReq miss cycles 2205system.iocache.WriteInvalidateReq_miss_latency::total 6655722318 # number of WriteInvalidateReq miss cycles 2206system.iocache.demand_miss_latency::realview.ide 31382127 # number of demand (read+write) miss cycles 2207system.iocache.demand_miss_latency::total 31382127 # number of demand (read+write) miss cycles 2208system.iocache.overall_miss_latency::realview.ide 31382127 # number of overall miss cycles 2209system.iocache.overall_miss_latency::total 31382127 # number of overall miss cycles | 2201system.iocache.ReadReq_miss_latency::realview.ide 31377127 # number of ReadReq miss cycles 2202system.iocache.ReadReq_miss_latency::total 31377127 # number of ReadReq miss cycles 2203system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6657460818 # number of WriteInvalidateReq miss cycles 2204system.iocache.WriteInvalidateReq_miss_latency::total 6657460818 # number of WriteInvalidateReq miss cycles 2205system.iocache.demand_miss_latency::realview.ide 31377127 # number of demand (read+write) miss cycles 2206system.iocache.demand_miss_latency::total 31377127 # number of demand (read+write) miss cycles 2207system.iocache.overall_miss_latency::realview.ide 31377127 # number of overall miss cycles 2208system.iocache.overall_miss_latency::total 31377127 # number of overall miss cycles |
| 2210system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) 2211system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) 2212system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 2213system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 2214system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses 2215system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses 2216system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses 2217system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses 2218system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2219system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2220system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2221system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2222system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2223system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2224system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2225system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 2209system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) 2210system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) 2211system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 2212system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 2213system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses 2214system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses 2215system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses 2216system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses 2217system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2218system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2219system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2220system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2221system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2222system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2223system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2224system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 2226system.iocache.ReadReq_avg_miss_latency::realview.ide 129144.555556 # average ReadReq miss latency 2227system.iocache.ReadReq_avg_miss_latency::total 129144.555556 # average ReadReq miss latency 2228system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183737.917348 # average WriteInvalidateReq miss latency 2229system.iocache.WriteInvalidateReq_avg_miss_latency::total 183737.917348 # average WriteInvalidateReq miss latency 2230system.iocache.demand_avg_miss_latency::realview.ide 129144.555556 # average overall miss latency 2231system.iocache.demand_avg_miss_latency::total 129144.555556 # average overall miss latency 2232system.iocache.overall_avg_miss_latency::realview.ide 129144.555556 # average overall miss latency 2233system.iocache.overall_avg_miss_latency::total 129144.555556 # average overall miss latency 2234system.iocache.blocked_cycles::no_mshrs 22459 # number of cycles access was blocked | 2225system.iocache.ReadReq_avg_miss_latency::realview.ide 129123.979424 # average ReadReq miss latency 2226system.iocache.ReadReq_avg_miss_latency::total 129123.979424 # average ReadReq miss latency 2227system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183785.910391 # average WriteInvalidateReq miss latency 2228system.iocache.WriteInvalidateReq_avg_miss_latency::total 183785.910391 # average WriteInvalidateReq miss latency 2229system.iocache.demand_avg_miss_latency::realview.ide 129123.979424 # average overall miss latency 2230system.iocache.demand_avg_miss_latency::total 129123.979424 # average overall miss latency 2231system.iocache.overall_avg_miss_latency::realview.ide 129123.979424 # average overall miss latency 2232system.iocache.overall_avg_miss_latency::total 129123.979424 # average overall miss latency 2233system.iocache.blocked_cycles::no_mshrs 22685 # number of cycles access was blocked |
| 2235system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2234system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2236system.iocache.blocked::no_mshrs 3430 # number of cycles access was blocked | 2235system.iocache.blocked::no_mshrs 3423 # number of cycles access was blocked |
| 2237system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 2236system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 2238system.iocache.avg_blocked_cycles::no_mshrs 6.547813 # average number of cycles each access was blocked | 2237system.iocache.avg_blocked_cycles::no_mshrs 6.627228 # average number of cycles each access was blocked |
| 2239system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2240system.iocache.fast_writes 0 # number of fast writes performed 2241system.iocache.cache_copies 0 # number of cache copies performed 2242system.iocache.writebacks::writebacks 36190 # number of writebacks 2243system.iocache.writebacks::total 36190 # number of writebacks 2244system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses 2245system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses 2246system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 2247system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses 2248system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses 2249system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses 2250system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses 2251system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses | 2238system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2239system.iocache.fast_writes 0 # number of fast writes performed 2240system.iocache.cache_copies 0 # number of cache copies performed 2241system.iocache.writebacks::writebacks 36190 # number of writebacks 2242system.iocache.writebacks::total 36190 # number of writebacks 2243system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses 2244system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses 2245system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 2246system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses 2247system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses 2248system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses 2249system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses 2250system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses |
| 2252system.iocache.ReadReq_mshr_miss_latency::realview.ide 18687627 # number of ReadReq MSHR miss cycles 2253system.iocache.ReadReq_mshr_miss_latency::total 18687627 # number of ReadReq MSHR miss cycles 2254system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4772040352 # number of WriteInvalidateReq MSHR miss cycles 2255system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4772040352 # number of WriteInvalidateReq MSHR miss cycles 2256system.iocache.demand_mshr_miss_latency::realview.ide 18687627 # number of demand (read+write) MSHR miss cycles 2257system.iocache.demand_mshr_miss_latency::total 18687627 # number of demand (read+write) MSHR miss cycles 2258system.iocache.overall_mshr_miss_latency::realview.ide 18687627 # number of overall MSHR miss cycles 2259system.iocache.overall_mshr_miss_latency::total 18687627 # number of overall MSHR miss cycles | 2251system.iocache.ReadReq_mshr_miss_latency::realview.ide 18676627 # number of ReadReq MSHR miss cycles 2252system.iocache.ReadReq_mshr_miss_latency::total 18676627 # number of ReadReq MSHR miss cycles 2253system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4773786844 # number of WriteInvalidateReq MSHR miss cycles 2254system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4773786844 # number of WriteInvalidateReq MSHR miss cycles 2255system.iocache.demand_mshr_miss_latency::realview.ide 18676627 # number of demand (read+write) MSHR miss cycles 2256system.iocache.demand_mshr_miss_latency::total 18676627 # number of demand (read+write) MSHR miss cycles 2257system.iocache.overall_mshr_miss_latency::realview.ide 18676627 # number of overall MSHR miss cycles 2258system.iocache.overall_mshr_miss_latency::total 18676627 # number of overall MSHR miss cycles |
| 2260system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2261system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2262system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2263system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 2264system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2265system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2266system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2267system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 2259system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2260system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2261system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2262system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 2263system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2264system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2265system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2266system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 2268system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76903.814815 # average ReadReq mshr miss latency 2269system.iocache.ReadReq_avg_mshr_miss_latency::total 76903.814815 # average ReadReq mshr miss latency 2270system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131736.979682 # average WriteInvalidateReq mshr miss latency 2271system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131736.979682 # average WriteInvalidateReq mshr miss latency 2272system.iocache.demand_avg_mshr_miss_latency::realview.ide 76903.814815 # average overall mshr miss latency 2273system.iocache.demand_avg_mshr_miss_latency::total 76903.814815 # average overall mshr miss latency 2274system.iocache.overall_avg_mshr_miss_latency::realview.ide 76903.814815 # average overall mshr miss latency 2275system.iocache.overall_avg_mshr_miss_latency::total 76903.814815 # average overall mshr miss latency | 2267system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76858.547325 # average ReadReq mshr miss latency 2268system.iocache.ReadReq_avg_mshr_miss_latency::total 76858.547325 # average ReadReq mshr miss latency 2269system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131785.193352 # average WriteInvalidateReq mshr miss latency 2270system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131785.193352 # average WriteInvalidateReq mshr miss latency 2271system.iocache.demand_avg_mshr_miss_latency::realview.ide 76858.547325 # average overall mshr miss latency 2272system.iocache.demand_avg_mshr_miss_latency::total 76858.547325 # average overall mshr miss latency 2273system.iocache.overall_avg_mshr_miss_latency::realview.ide 76858.547325 # average overall mshr miss latency 2274system.iocache.overall_avg_mshr_miss_latency::total 76858.547325 # average overall mshr miss latency |
| 2276system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 2275system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2277system.l2c.tags.replacements 136145 # number of replacements 2278system.l2c.tags.tagsinuse 64036.316369 # Cycle average of tags in use 2279system.l2c.tags.total_refs 380367 # Total number of references to valid blocks. 2280system.l2c.tags.sampled_refs 200629 # Sample count of references to valid blocks. 2281system.l2c.tags.avg_refs 1.895872 # Average number of references to valid blocks. | 2276system.l2c.tags.replacements 135621 # number of replacements 2277system.l2c.tags.tagsinuse 64040.319526 # Cycle average of tags in use 2278system.l2c.tags.total_refs 379947 # Total number of references to valid blocks. 2279system.l2c.tags.sampled_refs 200130 # Sample count of references to valid blocks. 2280system.l2c.tags.avg_refs 1.898501 # Average number of references to valid blocks. |
| 2282system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2281system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2283system.l2c.tags.occ_blocks::writebacks 12112.427093 # Average occupied blocks per requestor 2284system.l2c.tags.occ_blocks::cpu0.dtb.walker 74.878570 # Average occupied blocks per requestor 2285system.l2c.tags.occ_blocks::cpu0.itb.walker 0.028766 # Average occupied blocks per requestor 2286system.l2c.tags.occ_blocks::cpu0.inst 8551.494132 # Average occupied blocks per requestor 2287system.l2c.tags.occ_blocks::cpu0.data 2840.139732 # Average occupied blocks per requestor 2288system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35681.498153 # Average occupied blocks per requestor 2289system.l2c.tags.occ_blocks::cpu1.dtb.walker 16.446887 # Average occupied blocks per requestor 2290system.l2c.tags.occ_blocks::cpu1.inst 2203.793190 # Average occupied blocks per requestor 2291system.l2c.tags.occ_blocks::cpu1.data 582.329943 # Average occupied blocks per requestor 2292system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1973.279904 # Average occupied blocks per requestor 2293system.l2c.tags.occ_percent::writebacks 0.184821 # Average percentage of cache occupancy 2294system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001143 # Average percentage of cache occupancy | 2282system.l2c.tags.occ_blocks::writebacks 12350.088291 # Average occupied blocks per requestor 2283system.l2c.tags.occ_blocks::cpu0.dtb.walker 68.394364 # Average occupied blocks per requestor 2284system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030949 # Average occupied blocks per requestor 2285system.l2c.tags.occ_blocks::cpu0.inst 8481.237345 # Average occupied blocks per requestor 2286system.l2c.tags.occ_blocks::cpu0.data 2821.026897 # Average occupied blocks per requestor 2287system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35473.229907 # Average occupied blocks per requestor 2288system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.484833 # Average occupied blocks per requestor 2289system.l2c.tags.occ_blocks::cpu1.inst 2216.311582 # Average occupied blocks per requestor 2290system.l2c.tags.occ_blocks::cpu1.data 599.378307 # Average occupied blocks per requestor 2291system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2022.137051 # Average occupied blocks per requestor 2292system.l2c.tags.occ_percent::writebacks 0.188447 # Average percentage of cache occupancy 2293system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001044 # Average percentage of cache occupancy |
| 2295system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy | 2294system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy |
| 2296system.l2c.tags.occ_percent::cpu0.inst 0.130485 # Average percentage of cache occupancy 2297system.l2c.tags.occ_percent::cpu0.data 0.043337 # Average percentage of cache occupancy 2298system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.544456 # Average percentage of cache occupancy 2299system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000251 # Average percentage of cache occupancy 2300system.l2c.tags.occ_percent::cpu1.inst 0.033627 # Average percentage of cache occupancy 2301system.l2c.tags.occ_percent::cpu1.data 0.008886 # Average percentage of cache occupancy 2302system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030110 # Average percentage of cache occupancy 2303system.l2c.tags.occ_percent::total 0.977117 # Average percentage of cache occupancy 2304system.l2c.tags.occ_task_id_blocks::1022 30113 # Occupied blocks per task id 2305system.l2c.tags.occ_task_id_blocks::1023 44 # Occupied blocks per task id 2306system.l2c.tags.occ_task_id_blocks::1024 34327 # Occupied blocks per task id 2307system.l2c.tags.age_task_id_blocks_1022::2 139 # Occupied blocks per task id 2308system.l2c.tags.age_task_id_blocks_1022::3 5558 # Occupied blocks per task id 2309system.l2c.tags.age_task_id_blocks_1022::4 24416 # Occupied blocks per task id | 2295system.l2c.tags.occ_percent::cpu0.inst 0.129413 # Average percentage of cache occupancy 2296system.l2c.tags.occ_percent::cpu0.data 0.043045 # Average percentage of cache occupancy 2297system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.541279 # Average percentage of cache occupancy 2298system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000129 # Average percentage of cache occupancy 2299system.l2c.tags.occ_percent::cpu1.inst 0.033818 # Average percentage of cache occupancy 2300system.l2c.tags.occ_percent::cpu1.data 0.009146 # Average percentage of cache occupancy 2301system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030855 # Average percentage of cache occupancy 2302system.l2c.tags.occ_percent::total 0.977178 # Average percentage of cache occupancy 2303system.l2c.tags.occ_task_id_blocks::1022 29987 # Occupied blocks per task id 2304system.l2c.tags.occ_task_id_blocks::1023 56 # Occupied blocks per task id 2305system.l2c.tags.occ_task_id_blocks::1024 34466 # Occupied blocks per task id 2306system.l2c.tags.age_task_id_blocks_1022::2 143 # Occupied blocks per task id 2307system.l2c.tags.age_task_id_blocks_1022::3 5502 # Occupied blocks per task id 2308system.l2c.tags.age_task_id_blocks_1022::4 24342 # Occupied blocks per task id |
| 2310system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id | 2309system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id |
| 2311system.l2c.tags.age_task_id_blocks_1023::4 43 # Occupied blocks per task id 2312system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 2313system.l2c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 2314system.l2c.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id 2315system.l2c.tags.age_task_id_blocks_1024::3 3300 # Occupied blocks per task id 2316system.l2c.tags.age_task_id_blocks_1024::4 30690 # Occupied blocks per task id 2317system.l2c.tags.occ_task_id_percent::1022 0.459488 # Percentage of cache occupancy per task id 2318system.l2c.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id 2319system.l2c.tags.occ_task_id_percent::1024 0.523788 # Percentage of cache occupancy per task id 2320system.l2c.tags.tag_accesses 5288124 # Number of tag accesses 2321system.l2c.tags.data_accesses 5288124 # Number of data accesses 2322system.l2c.ReadReq_hits::cpu0.dtb.walker 404 # number of ReadReq hits 2323system.l2c.ReadReq_hits::cpu0.itb.walker 85 # number of ReadReq hits 2324system.l2c.ReadReq_hits::cpu0.inst 48346 # number of ReadReq hits 2325system.l2c.ReadReq_hits::cpu0.data 49709 # number of ReadReq hits 2326system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 47536 # number of ReadReq hits 2327system.l2c.ReadReq_hits::cpu1.dtb.walker 123 # number of ReadReq hits 2328system.l2c.ReadReq_hits::cpu1.itb.walker 32 # number of ReadReq hits 2329system.l2c.ReadReq_hits::cpu1.inst 17643 # number of ReadReq hits 2330system.l2c.ReadReq_hits::cpu1.data 9297 # number of ReadReq hits 2331system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 5444 # number of ReadReq hits 2332system.l2c.ReadReq_hits::total 178619 # number of ReadReq hits 2333system.l2c.Writeback_hits::writebacks 232833 # number of Writeback hits 2334system.l2c.Writeback_hits::total 232833 # number of Writeback hits 2335system.l2c.UpgradeReq_hits::cpu0.data 2833 # number of UpgradeReq hits 2336system.l2c.UpgradeReq_hits::cpu1.data 761 # number of UpgradeReq hits 2337system.l2c.UpgradeReq_hits::total 3594 # number of UpgradeReq hits 2338system.l2c.SCUpgradeReq_hits::cpu0.data 161 # number of SCUpgradeReq hits 2339system.l2c.SCUpgradeReq_hits::cpu1.data 166 # number of SCUpgradeReq hits 2340system.l2c.SCUpgradeReq_hits::total 327 # number of SCUpgradeReq hits 2341system.l2c.ReadExReq_hits::cpu0.data 4206 # number of ReadExReq hits 2342system.l2c.ReadExReq_hits::cpu1.data 1689 # number of ReadExReq hits 2343system.l2c.ReadExReq_hits::total 5895 # number of ReadExReq hits 2344system.l2c.demand_hits::cpu0.dtb.walker 404 # number of demand (read+write) hits 2345system.l2c.demand_hits::cpu0.itb.walker 85 # number of demand (read+write) hits 2346system.l2c.demand_hits::cpu0.inst 48346 # number of demand (read+write) hits 2347system.l2c.demand_hits::cpu0.data 53915 # number of demand (read+write) hits 2348system.l2c.demand_hits::cpu0.l2cache.prefetcher 47536 # number of demand (read+write) hits 2349system.l2c.demand_hits::cpu1.dtb.walker 123 # number of demand (read+write) hits 2350system.l2c.demand_hits::cpu1.itb.walker 32 # number of demand (read+write) hits 2351system.l2c.demand_hits::cpu1.inst 17643 # number of demand (read+write) hits 2352system.l2c.demand_hits::cpu1.data 10986 # number of demand (read+write) hits 2353system.l2c.demand_hits::cpu1.l2cache.prefetcher 5444 # number of demand (read+write) hits 2354system.l2c.demand_hits::total 184514 # number of demand (read+write) hits 2355system.l2c.overall_hits::cpu0.dtb.walker 404 # number of overall hits 2356system.l2c.overall_hits::cpu0.itb.walker 85 # number of overall hits 2357system.l2c.overall_hits::cpu0.inst 48346 # number of overall hits 2358system.l2c.overall_hits::cpu0.data 53915 # number of overall hits 2359system.l2c.overall_hits::cpu0.l2cache.prefetcher 47536 # number of overall hits 2360system.l2c.overall_hits::cpu1.dtb.walker 123 # number of overall hits 2361system.l2c.overall_hits::cpu1.itb.walker 32 # number of overall hits 2362system.l2c.overall_hits::cpu1.inst 17643 # number of overall hits 2363system.l2c.overall_hits::cpu1.data 10986 # number of overall hits 2364system.l2c.overall_hits::cpu1.l2cache.prefetcher 5444 # number of overall hits 2365system.l2c.overall_hits::total 184514 # number of overall hits 2366system.l2c.ReadReq_misses::cpu0.dtb.walker 138 # number of ReadReq misses | 2310system.l2c.tags.age_task_id_blocks_1023::4 55 # Occupied blocks per task id 2311system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 2312system.l2c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id 2313system.l2c.tags.age_task_id_blocks_1024::2 307 # Occupied blocks per task id 2314system.l2c.tags.age_task_id_blocks_1024::3 3362 # Occupied blocks per task id 2315system.l2c.tags.age_task_id_blocks_1024::4 30784 # Occupied blocks per task id 2316system.l2c.tags.occ_task_id_percent::1022 0.457565 # Percentage of cache occupancy per task id 2317system.l2c.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id 2318system.l2c.tags.occ_task_id_percent::1024 0.525909 # Percentage of cache occupancy per task id 2319system.l2c.tags.tag_accesses 5285534 # Number of tag accesses 2320system.l2c.tags.data_accesses 5285534 # Number of data accesses 2321system.l2c.ReadReq_hits::cpu0.dtb.walker 409 # number of ReadReq hits 2322system.l2c.ReadReq_hits::cpu0.itb.walker 68 # number of ReadReq hits 2323system.l2c.ReadReq_hits::cpu0.inst 48212 # number of ReadReq hits 2324system.l2c.ReadReq_hits::cpu0.data 49449 # number of ReadReq hits 2325system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 47699 # number of ReadReq hits 2326system.l2c.ReadReq_hits::cpu1.dtb.walker 127 # number of ReadReq hits 2327system.l2c.ReadReq_hits::cpu1.itb.walker 23 # number of ReadReq hits 2328system.l2c.ReadReq_hits::cpu1.inst 17668 # number of ReadReq hits 2329system.l2c.ReadReq_hits::cpu1.data 9341 # number of ReadReq hits 2330system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 5522 # number of ReadReq hits 2331system.l2c.ReadReq_hits::total 178518 # number of ReadReq hits 2332system.l2c.Writeback_hits::writebacks 232415 # number of Writeback hits 2333system.l2c.Writeback_hits::total 232415 # number of Writeback hits 2334system.l2c.UpgradeReq_hits::cpu0.data 3312 # number of UpgradeReq hits 2335system.l2c.UpgradeReq_hits::cpu1.data 786 # number of UpgradeReq hits 2336system.l2c.UpgradeReq_hits::total 4098 # number of UpgradeReq hits 2337system.l2c.SCUpgradeReq_hits::cpu0.data 163 # number of SCUpgradeReq hits 2338system.l2c.SCUpgradeReq_hits::cpu1.data 161 # number of SCUpgradeReq hits 2339system.l2c.SCUpgradeReq_hits::total 324 # number of SCUpgradeReq hits 2340system.l2c.ReadExReq_hits::cpu0.data 4321 # number of ReadExReq hits 2341system.l2c.ReadExReq_hits::cpu1.data 1657 # number of ReadExReq hits 2342system.l2c.ReadExReq_hits::total 5978 # number of ReadExReq hits 2343system.l2c.demand_hits::cpu0.dtb.walker 409 # number of demand (read+write) hits 2344system.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits 2345system.l2c.demand_hits::cpu0.inst 48212 # number of demand (read+write) hits 2346system.l2c.demand_hits::cpu0.data 53770 # number of demand (read+write) hits 2347system.l2c.demand_hits::cpu0.l2cache.prefetcher 47699 # number of demand (read+write) hits 2348system.l2c.demand_hits::cpu1.dtb.walker 127 # number of demand (read+write) hits 2349system.l2c.demand_hits::cpu1.itb.walker 23 # number of demand (read+write) hits 2350system.l2c.demand_hits::cpu1.inst 17668 # number of demand (read+write) hits 2351system.l2c.demand_hits::cpu1.data 10998 # number of demand (read+write) hits 2352system.l2c.demand_hits::cpu1.l2cache.prefetcher 5522 # number of demand (read+write) hits 2353system.l2c.demand_hits::total 184496 # number of demand (read+write) hits 2354system.l2c.overall_hits::cpu0.dtb.walker 409 # number of overall hits 2355system.l2c.overall_hits::cpu0.itb.walker 68 # number of overall hits 2356system.l2c.overall_hits::cpu0.inst 48212 # number of overall hits 2357system.l2c.overall_hits::cpu0.data 53770 # number of overall hits 2358system.l2c.overall_hits::cpu0.l2cache.prefetcher 47699 # number of overall hits 2359system.l2c.overall_hits::cpu1.dtb.walker 127 # number of overall hits 2360system.l2c.overall_hits::cpu1.itb.walker 23 # number of overall hits 2361system.l2c.overall_hits::cpu1.inst 17668 # number of overall hits 2362system.l2c.overall_hits::cpu1.data 10998 # number of overall hits 2363system.l2c.overall_hits::cpu1.l2cache.prefetcher 5522 # number of overall hits 2364system.l2c.overall_hits::total 184496 # number of overall hits 2365system.l2c.ReadReq_misses::cpu0.dtb.walker 131 # number of ReadReq misses |
| 2367system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses | 2366system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses |
| 2368system.l2c.ReadReq_misses::cpu0.inst 22734 # number of ReadReq misses 2369system.l2c.ReadReq_misses::cpu0.data 9861 # number of ReadReq misses 2370system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 133208 # number of ReadReq misses 2371system.l2c.ReadReq_misses::cpu1.dtb.walker 22 # number of ReadReq misses 2372system.l2c.ReadReq_misses::cpu1.inst 3332 # number of ReadReq misses 2373system.l2c.ReadReq_misses::cpu1.data 1132 # number of ReadReq misses 2374system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 6262 # number of ReadReq misses 2375system.l2c.ReadReq_misses::total 176690 # number of ReadReq misses 2376system.l2c.UpgradeReq_misses::cpu0.data 9235 # number of UpgradeReq misses 2377system.l2c.UpgradeReq_misses::cpu1.data 2955 # number of UpgradeReq misses 2378system.l2c.UpgradeReq_misses::total 12190 # number of UpgradeReq misses 2379system.l2c.SCUpgradeReq_misses::cpu0.data 697 # number of SCUpgradeReq misses 2380system.l2c.SCUpgradeReq_misses::cpu1.data 1269 # number of SCUpgradeReq misses 2381system.l2c.SCUpgradeReq_misses::total 1966 # number of SCUpgradeReq misses 2382system.l2c.ReadExReq_misses::cpu0.data 11244 # number of ReadExReq misses 2383system.l2c.ReadExReq_misses::cpu1.data 8331 # number of ReadExReq misses 2384system.l2c.ReadExReq_misses::total 19575 # number of ReadExReq misses 2385system.l2c.demand_misses::cpu0.dtb.walker 138 # number of demand (read+write) misses | 2367system.l2c.ReadReq_misses::cpu0.inst 22670 # number of ReadReq misses 2368system.l2c.ReadReq_misses::cpu0.data 9764 # number of ReadReq misses 2369system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 132484 # number of ReadReq misses 2370system.l2c.ReadReq_misses::cpu1.dtb.walker 12 # number of ReadReq misses 2371system.l2c.ReadReq_misses::cpu1.inst 3329 # number of ReadReq misses 2372system.l2c.ReadReq_misses::cpu1.data 1605 # number of ReadReq misses 2373system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 6236 # number of ReadReq misses 2374system.l2c.ReadReq_misses::total 176232 # number of ReadReq misses 2375system.l2c.UpgradeReq_misses::cpu0.data 9270 # number of UpgradeReq misses 2376system.l2c.UpgradeReq_misses::cpu1.data 2936 # number of UpgradeReq misses 2377system.l2c.UpgradeReq_misses::total 12206 # number of UpgradeReq misses 2378system.l2c.SCUpgradeReq_misses::cpu0.data 679 # number of SCUpgradeReq misses 2379system.l2c.SCUpgradeReq_misses::cpu1.data 1284 # number of SCUpgradeReq misses 2380system.l2c.SCUpgradeReq_misses::total 1963 # number of SCUpgradeReq misses 2381system.l2c.ReadExReq_misses::cpu0.data 11261 # number of ReadExReq misses 2382system.l2c.ReadExReq_misses::cpu1.data 8349 # number of ReadExReq misses 2383system.l2c.ReadExReq_misses::total 19610 # number of ReadExReq misses 2384system.l2c.demand_misses::cpu0.dtb.walker 131 # number of demand (read+write) misses |
| 2386system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses | 2385system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses |
| 2387system.l2c.demand_misses::cpu0.inst 22734 # number of demand (read+write) misses 2388system.l2c.demand_misses::cpu0.data 21105 # number of demand (read+write) misses 2389system.l2c.demand_misses::cpu0.l2cache.prefetcher 133208 # number of demand (read+write) misses 2390system.l2c.demand_misses::cpu1.dtb.walker 22 # number of demand (read+write) misses 2391system.l2c.demand_misses::cpu1.inst 3332 # number of demand (read+write) misses 2392system.l2c.demand_misses::cpu1.data 9463 # number of demand (read+write) misses 2393system.l2c.demand_misses::cpu1.l2cache.prefetcher 6262 # number of demand (read+write) misses 2394system.l2c.demand_misses::total 196265 # number of demand (read+write) misses 2395system.l2c.overall_misses::cpu0.dtb.walker 138 # number of overall misses | 2386system.l2c.demand_misses::cpu0.inst 22670 # number of demand (read+write) misses 2387system.l2c.demand_misses::cpu0.data 21025 # number of demand (read+write) misses 2388system.l2c.demand_misses::cpu0.l2cache.prefetcher 132484 # number of demand (read+write) misses 2389system.l2c.demand_misses::cpu1.dtb.walker 12 # number of demand (read+write) misses 2390system.l2c.demand_misses::cpu1.inst 3329 # number of demand (read+write) misses 2391system.l2c.demand_misses::cpu1.data 9954 # number of demand (read+write) misses 2392system.l2c.demand_misses::cpu1.l2cache.prefetcher 6236 # number of demand (read+write) misses 2393system.l2c.demand_misses::total 195842 # number of demand (read+write) misses 2394system.l2c.overall_misses::cpu0.dtb.walker 131 # number of overall misses |
| 2396system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses | 2395system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses |
| 2397system.l2c.overall_misses::cpu0.inst 22734 # number of overall misses 2398system.l2c.overall_misses::cpu0.data 21105 # number of overall misses 2399system.l2c.overall_misses::cpu0.l2cache.prefetcher 133208 # number of overall misses 2400system.l2c.overall_misses::cpu1.dtb.walker 22 # number of overall misses 2401system.l2c.overall_misses::cpu1.inst 3332 # number of overall misses 2402system.l2c.overall_misses::cpu1.data 9463 # number of overall misses 2403system.l2c.overall_misses::cpu1.l2cache.prefetcher 6262 # number of overall misses 2404system.l2c.overall_misses::total 196265 # number of overall misses 2405system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 11906500 # number of ReadReq miss cycles | 2396system.l2c.overall_misses::cpu0.inst 22670 # number of overall misses 2397system.l2c.overall_misses::cpu0.data 21025 # number of overall misses 2398system.l2c.overall_misses::cpu0.l2cache.prefetcher 132484 # number of overall misses 2399system.l2c.overall_misses::cpu1.dtb.walker 12 # number of overall misses 2400system.l2c.overall_misses::cpu1.inst 3329 # number of overall misses 2401system.l2c.overall_misses::cpu1.data 9954 # number of overall misses 2402system.l2c.overall_misses::cpu1.l2cache.prefetcher 6236 # number of overall misses 2403system.l2c.overall_misses::total 195842 # number of overall misses 2404system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 11375500 # number of ReadReq miss cycles |
| 2406system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82500 # number of ReadReq miss cycles | 2405system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82500 # number of ReadReq miss cycles |
| 2407system.l2c.ReadReq_miss_latency::cpu0.inst 1830615779 # number of ReadReq miss cycles 2408system.l2c.ReadReq_miss_latency::cpu0.data 872554898 # number of ReadReq miss cycles 2409system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 13804634964 # number of ReadReq miss cycles 2410system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1919000 # number of ReadReq miss cycles 2411system.l2c.ReadReq_miss_latency::cpu1.inst 276050505 # number of ReadReq miss cycles 2412system.l2c.ReadReq_miss_latency::cpu1.data 100986272 # number of ReadReq miss cycles 2413system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 812337192 # number of ReadReq miss cycles 2414system.l2c.ReadReq_miss_latency::total 17711087610 # number of ReadReq miss cycles 2415system.l2c.UpgradeReq_miss_latency::cpu0.data 10802199 # number of UpgradeReq miss cycles 2416system.l2c.UpgradeReq_miss_latency::cpu1.data 3228400 # number of UpgradeReq miss cycles 2417system.l2c.UpgradeReq_miss_latency::total 14030599 # number of UpgradeReq miss cycles 2418system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1283464 # number of SCUpgradeReq miss cycles 2419system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1219962 # number of SCUpgradeReq miss cycles 2420system.l2c.SCUpgradeReq_miss_latency::total 2503426 # number of SCUpgradeReq miss cycles 2421system.l2c.ReadExReq_miss_latency::cpu0.data 1032599700 # number of ReadExReq miss cycles 2422system.l2c.ReadExReq_miss_latency::cpu1.data 678696974 # number of ReadExReq miss cycles 2423system.l2c.ReadExReq_miss_latency::total 1711296674 # number of ReadExReq miss cycles 2424system.l2c.demand_miss_latency::cpu0.dtb.walker 11906500 # number of demand (read+write) miss cycles | 2406system.l2c.ReadReq_miss_latency::cpu0.inst 1826895022 # number of ReadReq miss cycles 2407system.l2c.ReadReq_miss_latency::cpu0.data 860956862 # number of ReadReq miss cycles 2408system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 13678177756 # number of ReadReq miss cycles 2409system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1020250 # number of ReadReq miss cycles 2410system.l2c.ReadReq_miss_latency::cpu1.inst 277468755 # number of ReadReq miss cycles 2411system.l2c.ReadReq_miss_latency::cpu1.data 142082250 # number of ReadReq miss cycles 2412system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 821626642 # number of ReadReq miss cycles 2413system.l2c.ReadReq_miss_latency::total 17619685537 # number of ReadReq miss cycles 2414system.l2c.UpgradeReq_miss_latency::cpu0.data 12058658 # number of UpgradeReq miss cycles 2415system.l2c.UpgradeReq_miss_latency::cpu1.data 2910410 # number of UpgradeReq miss cycles 2416system.l2c.UpgradeReq_miss_latency::total 14969068 # number of UpgradeReq miss cycles 2417system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1225966 # number of SCUpgradeReq miss cycles 2418system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1472453 # number of SCUpgradeReq miss cycles 2419system.l2c.SCUpgradeReq_miss_latency::total 2698419 # number of SCUpgradeReq miss cycles 2420system.l2c.ReadExReq_miss_latency::cpu0.data 1034866909 # number of ReadExReq miss cycles 2421system.l2c.ReadExReq_miss_latency::cpu1.data 686149232 # number of ReadExReq miss cycles 2422system.l2c.ReadExReq_miss_latency::total 1721016141 # number of ReadExReq miss cycles 2423system.l2c.demand_miss_latency::cpu0.dtb.walker 11375500 # number of demand (read+write) miss cycles |
| 2425system.l2c.demand_miss_latency::cpu0.itb.walker 82500 # number of demand (read+write) miss cycles | 2424system.l2c.demand_miss_latency::cpu0.itb.walker 82500 # number of demand (read+write) miss cycles |
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| 2435system.l2c.overall_miss_latency::cpu0.itb.walker 82500 # number of overall miss cycles | 2434system.l2c.overall_miss_latency::cpu0.itb.walker 82500 # number of overall miss cycles |
| 2436system.l2c.overall_miss_latency::cpu0.inst 1830615779 # number of overall miss cycles 2437system.l2c.overall_miss_latency::cpu0.data 1905154598 # number of overall miss cycles 2438system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13804634964 # number of overall miss cycles 2439system.l2c.overall_miss_latency::cpu1.dtb.walker 1919000 # number of overall miss cycles 2440system.l2c.overall_miss_latency::cpu1.inst 276050505 # number of overall miss cycles 2441system.l2c.overall_miss_latency::cpu1.data 779683246 # number of overall miss cycles 2442system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 812337192 # number of overall miss cycles 2443system.l2c.overall_miss_latency::total 19422384284 # number of overall miss cycles 2444system.l2c.ReadReq_accesses::cpu0.dtb.walker 542 # number of ReadReq accesses(hits+misses) 2445system.l2c.ReadReq_accesses::cpu0.itb.walker 86 # number of ReadReq accesses(hits+misses) 2446system.l2c.ReadReq_accesses::cpu0.inst 71080 # number of ReadReq accesses(hits+misses) 2447system.l2c.ReadReq_accesses::cpu0.data 59570 # number of ReadReq accesses(hits+misses) 2448system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 180744 # number of ReadReq accesses(hits+misses) 2449system.l2c.ReadReq_accesses::cpu1.dtb.walker 145 # number of ReadReq accesses(hits+misses) 2450system.l2c.ReadReq_accesses::cpu1.itb.walker 32 # number of ReadReq accesses(hits+misses) 2451system.l2c.ReadReq_accesses::cpu1.inst 20975 # number of ReadReq accesses(hits+misses) 2452system.l2c.ReadReq_accesses::cpu1.data 10429 # number of ReadReq accesses(hits+misses) 2453system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 11706 # number of ReadReq accesses(hits+misses) 2454system.l2c.ReadReq_accesses::total 355309 # number of ReadReq accesses(hits+misses) 2455system.l2c.Writeback_accesses::writebacks 232833 # number of Writeback accesses(hits+misses) 2456system.l2c.Writeback_accesses::total 232833 # number of Writeback accesses(hits+misses) 2457system.l2c.UpgradeReq_accesses::cpu0.data 12068 # number of UpgradeReq accesses(hits+misses) 2458system.l2c.UpgradeReq_accesses::cpu1.data 3716 # number of UpgradeReq accesses(hits+misses) 2459system.l2c.UpgradeReq_accesses::total 15784 # number of UpgradeReq accesses(hits+misses) 2460system.l2c.SCUpgradeReq_accesses::cpu0.data 858 # number of SCUpgradeReq accesses(hits+misses) 2461system.l2c.SCUpgradeReq_accesses::cpu1.data 1435 # number of SCUpgradeReq accesses(hits+misses) 2462system.l2c.SCUpgradeReq_accesses::total 2293 # number of SCUpgradeReq accesses(hits+misses) 2463system.l2c.ReadExReq_accesses::cpu0.data 15450 # number of ReadExReq accesses(hits+misses) 2464system.l2c.ReadExReq_accesses::cpu1.data 10020 # number of ReadExReq accesses(hits+misses) 2465system.l2c.ReadExReq_accesses::total 25470 # number of ReadExReq accesses(hits+misses) 2466system.l2c.demand_accesses::cpu0.dtb.walker 542 # number of demand (read+write) accesses 2467system.l2c.demand_accesses::cpu0.itb.walker 86 # number of demand (read+write) accesses 2468system.l2c.demand_accesses::cpu0.inst 71080 # number of demand (read+write) accesses 2469system.l2c.demand_accesses::cpu0.data 75020 # number of demand (read+write) accesses 2470system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180744 # number of demand (read+write) accesses 2471system.l2c.demand_accesses::cpu1.dtb.walker 145 # number of demand (read+write) accesses 2472system.l2c.demand_accesses::cpu1.itb.walker 32 # number of demand (read+write) accesses 2473system.l2c.demand_accesses::cpu1.inst 20975 # number of demand (read+write) accesses 2474system.l2c.demand_accesses::cpu1.data 20449 # number of demand (read+write) accesses 2475system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11706 # number of demand (read+write) accesses 2476system.l2c.demand_accesses::total 380779 # number of demand (read+write) accesses 2477system.l2c.overall_accesses::cpu0.dtb.walker 542 # number of overall (read+write) accesses 2478system.l2c.overall_accesses::cpu0.itb.walker 86 # number of overall (read+write) accesses 2479system.l2c.overall_accesses::cpu0.inst 71080 # number of overall (read+write) accesses 2480system.l2c.overall_accesses::cpu0.data 75020 # number of overall (read+write) accesses 2481system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180744 # number of overall (read+write) accesses 2482system.l2c.overall_accesses::cpu1.dtb.walker 145 # number of overall (read+write) accesses 2483system.l2c.overall_accesses::cpu1.itb.walker 32 # number of overall (read+write) accesses 2484system.l2c.overall_accesses::cpu1.inst 20975 # number of overall (read+write) accesses 2485system.l2c.overall_accesses::cpu1.data 20449 # number of overall (read+write) accesses 2486system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11706 # number of overall (read+write) accesses 2487system.l2c.overall_accesses::total 380779 # number of overall (read+write) accesses 2488system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.254613 # miss rate for ReadReq accesses 2489system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.011628 # miss rate for ReadReq accesses 2490system.l2c.ReadReq_miss_rate::cpu0.inst 0.319837 # miss rate for ReadReq accesses 2491system.l2c.ReadReq_miss_rate::cpu0.data 0.165536 # miss rate for ReadReq accesses 2492system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.736998 # miss rate for ReadReq accesses 2493system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.151724 # miss rate for ReadReq accesses 2494system.l2c.ReadReq_miss_rate::cpu1.inst 0.158856 # miss rate for ReadReq accesses 2495system.l2c.ReadReq_miss_rate::cpu1.data 0.108543 # miss rate for ReadReq accesses 2496system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.534939 # miss rate for ReadReq accesses 2497system.l2c.ReadReq_miss_rate::total 0.497285 # miss rate for ReadReq accesses 2498system.l2c.UpgradeReq_miss_rate::cpu0.data 0.765247 # miss rate for UpgradeReq accesses 2499system.l2c.UpgradeReq_miss_rate::cpu1.data 0.795210 # miss rate for UpgradeReq accesses 2500system.l2c.UpgradeReq_miss_rate::total 0.772301 # miss rate for UpgradeReq accesses 2501system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.812354 # miss rate for SCUpgradeReq accesses 2502system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.884321 # miss rate for SCUpgradeReq accesses 2503system.l2c.SCUpgradeReq_miss_rate::total 0.857392 # miss rate for SCUpgradeReq accesses 2504system.l2c.ReadExReq_miss_rate::cpu0.data 0.727767 # miss rate for ReadExReq accesses 2505system.l2c.ReadExReq_miss_rate::cpu1.data 0.831437 # miss rate for ReadExReq accesses 2506system.l2c.ReadExReq_miss_rate::total 0.768551 # miss rate for ReadExReq accesses 2507system.l2c.demand_miss_rate::cpu0.dtb.walker 0.254613 # miss rate for demand accesses 2508system.l2c.demand_miss_rate::cpu0.itb.walker 0.011628 # miss rate for demand accesses 2509system.l2c.demand_miss_rate::cpu0.inst 0.319837 # miss rate for demand accesses 2510system.l2c.demand_miss_rate::cpu0.data 0.281325 # miss rate for demand accesses 2511system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.736998 # miss rate for demand accesses 2512system.l2c.demand_miss_rate::cpu1.dtb.walker 0.151724 # miss rate for demand accesses 2513system.l2c.demand_miss_rate::cpu1.inst 0.158856 # miss rate for demand accesses 2514system.l2c.demand_miss_rate::cpu1.data 0.462761 # miss rate for demand accesses 2515system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.534939 # miss rate for demand accesses 2516system.l2c.demand_miss_rate::total 0.515430 # miss rate for demand accesses 2517system.l2c.overall_miss_rate::cpu0.dtb.walker 0.254613 # miss rate for overall accesses 2518system.l2c.overall_miss_rate::cpu0.itb.walker 0.011628 # miss rate for overall accesses 2519system.l2c.overall_miss_rate::cpu0.inst 0.319837 # miss rate for overall accesses 2520system.l2c.overall_miss_rate::cpu0.data 0.281325 # miss rate for overall accesses 2521system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.736998 # miss rate for overall accesses 2522system.l2c.overall_miss_rate::cpu1.dtb.walker 0.151724 # miss rate for overall accesses 2523system.l2c.overall_miss_rate::cpu1.inst 0.158856 # miss rate for overall accesses 2524system.l2c.overall_miss_rate::cpu1.data 0.462761 # miss rate for overall accesses 2525system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.534939 # miss rate for overall accesses 2526system.l2c.overall_miss_rate::total 0.515430 # miss rate for overall accesses 2527system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 86278.985507 # average ReadReq miss latency | 2435system.l2c.overall_miss_latency::cpu0.inst 1826895022 # number of overall miss cycles 2436system.l2c.overall_miss_latency::cpu0.data 1895823771 # number of overall miss cycles 2437system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13678177756 # number of overall miss cycles 2438system.l2c.overall_miss_latency::cpu1.dtb.walker 1020250 # number of overall miss cycles 2439system.l2c.overall_miss_latency::cpu1.inst 277468755 # number of overall miss cycles 2440system.l2c.overall_miss_latency::cpu1.data 828231482 # number of overall miss cycles 2441system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 821626642 # number of overall miss cycles 2442system.l2c.overall_miss_latency::total 19340701678 # number of overall miss cycles 2443system.l2c.ReadReq_accesses::cpu0.dtb.walker 540 # number of ReadReq accesses(hits+misses) 2444system.l2c.ReadReq_accesses::cpu0.itb.walker 69 # number of ReadReq accesses(hits+misses) 2445system.l2c.ReadReq_accesses::cpu0.inst 70882 # number of ReadReq accesses(hits+misses) 2446system.l2c.ReadReq_accesses::cpu0.data 59213 # number of ReadReq accesses(hits+misses) 2447system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 180183 # number of ReadReq accesses(hits+misses) 2448system.l2c.ReadReq_accesses::cpu1.dtb.walker 139 # number of ReadReq accesses(hits+misses) 2449system.l2c.ReadReq_accesses::cpu1.itb.walker 23 # number of ReadReq accesses(hits+misses) 2450system.l2c.ReadReq_accesses::cpu1.inst 20997 # number of ReadReq accesses(hits+misses) 2451system.l2c.ReadReq_accesses::cpu1.data 10946 # number of ReadReq accesses(hits+misses) 2452system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 11758 # number of ReadReq accesses(hits+misses) 2453system.l2c.ReadReq_accesses::total 354750 # number of ReadReq accesses(hits+misses) 2454system.l2c.Writeback_accesses::writebacks 232415 # number of Writeback accesses(hits+misses) 2455system.l2c.Writeback_accesses::total 232415 # number of Writeback accesses(hits+misses) 2456system.l2c.UpgradeReq_accesses::cpu0.data 12582 # number of UpgradeReq accesses(hits+misses) 2457system.l2c.UpgradeReq_accesses::cpu1.data 3722 # number of UpgradeReq accesses(hits+misses) 2458system.l2c.UpgradeReq_accesses::total 16304 # number of UpgradeReq accesses(hits+misses) 2459system.l2c.SCUpgradeReq_accesses::cpu0.data 842 # number of SCUpgradeReq accesses(hits+misses) 2460system.l2c.SCUpgradeReq_accesses::cpu1.data 1445 # number of SCUpgradeReq accesses(hits+misses) 2461system.l2c.SCUpgradeReq_accesses::total 2287 # number of SCUpgradeReq accesses(hits+misses) 2462system.l2c.ReadExReq_accesses::cpu0.data 15582 # number of ReadExReq accesses(hits+misses) 2463system.l2c.ReadExReq_accesses::cpu1.data 10006 # number of ReadExReq accesses(hits+misses) 2464system.l2c.ReadExReq_accesses::total 25588 # number of ReadExReq accesses(hits+misses) 2465system.l2c.demand_accesses::cpu0.dtb.walker 540 # number of demand (read+write) accesses 2466system.l2c.demand_accesses::cpu0.itb.walker 69 # number of demand (read+write) accesses 2467system.l2c.demand_accesses::cpu0.inst 70882 # number of demand (read+write) accesses 2468system.l2c.demand_accesses::cpu0.data 74795 # number of demand (read+write) accesses 2469system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180183 # number of demand (read+write) accesses 2470system.l2c.demand_accesses::cpu1.dtb.walker 139 # number of demand (read+write) accesses 2471system.l2c.demand_accesses::cpu1.itb.walker 23 # number of demand (read+write) accesses 2472system.l2c.demand_accesses::cpu1.inst 20997 # number of demand (read+write) accesses 2473system.l2c.demand_accesses::cpu1.data 20952 # number of demand (read+write) accesses 2474system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11758 # number of demand (read+write) accesses 2475system.l2c.demand_accesses::total 380338 # number of demand (read+write) accesses 2476system.l2c.overall_accesses::cpu0.dtb.walker 540 # number of overall (read+write) accesses 2477system.l2c.overall_accesses::cpu0.itb.walker 69 # number of overall (read+write) accesses 2478system.l2c.overall_accesses::cpu0.inst 70882 # number of overall (read+write) accesses 2479system.l2c.overall_accesses::cpu0.data 74795 # number of overall (read+write) accesses 2480system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180183 # number of overall (read+write) accesses 2481system.l2c.overall_accesses::cpu1.dtb.walker 139 # number of overall (read+write) accesses 2482system.l2c.overall_accesses::cpu1.itb.walker 23 # number of overall (read+write) accesses 2483system.l2c.overall_accesses::cpu1.inst 20997 # number of overall (read+write) accesses 2484system.l2c.overall_accesses::cpu1.data 20952 # number of overall (read+write) accesses 2485system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11758 # number of overall (read+write) accesses 2486system.l2c.overall_accesses::total 380338 # number of overall (read+write) accesses 2487system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.242593 # miss rate for ReadReq accesses 2488system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.014493 # miss rate for ReadReq accesses 2489system.l2c.ReadReq_miss_rate::cpu0.inst 0.319827 # miss rate for ReadReq accesses 2490system.l2c.ReadReq_miss_rate::cpu0.data 0.164896 # miss rate for ReadReq accesses 2491system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.735275 # miss rate for ReadReq accesses 2492system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.086331 # miss rate for ReadReq accesses 2493system.l2c.ReadReq_miss_rate::cpu1.inst 0.158546 # miss rate for ReadReq accesses 2494system.l2c.ReadReq_miss_rate::cpu1.data 0.146629 # miss rate for ReadReq accesses 2495system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.530362 # miss rate for ReadReq accesses 2496system.l2c.ReadReq_miss_rate::total 0.496778 # miss rate for ReadReq accesses 2497system.l2c.UpgradeReq_miss_rate::cpu0.data 0.736767 # miss rate for UpgradeReq accesses 2498system.l2c.UpgradeReq_miss_rate::cpu1.data 0.788823 # miss rate for UpgradeReq accesses 2499system.l2c.UpgradeReq_miss_rate::total 0.748651 # miss rate for UpgradeReq accesses 2500system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.806413 # miss rate for SCUpgradeReq accesses 2501system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.888581 # miss rate for SCUpgradeReq accesses 2502system.l2c.SCUpgradeReq_miss_rate::total 0.858330 # miss rate for SCUpgradeReq accesses 2503system.l2c.ReadExReq_miss_rate::cpu0.data 0.722693 # miss rate for ReadExReq accesses 2504system.l2c.ReadExReq_miss_rate::cpu1.data 0.834399 # miss rate for ReadExReq accesses 2505system.l2c.ReadExReq_miss_rate::total 0.766375 # miss rate for ReadExReq accesses 2506system.l2c.demand_miss_rate::cpu0.dtb.walker 0.242593 # miss rate for demand accesses 2507system.l2c.demand_miss_rate::cpu0.itb.walker 0.014493 # miss rate for demand accesses 2508system.l2c.demand_miss_rate::cpu0.inst 0.319827 # miss rate for demand accesses 2509system.l2c.demand_miss_rate::cpu0.data 0.281102 # miss rate for demand accesses 2510system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.735275 # miss rate for demand accesses 2511system.l2c.demand_miss_rate::cpu1.dtb.walker 0.086331 # miss rate for demand accesses 2512system.l2c.demand_miss_rate::cpu1.inst 0.158546 # miss rate for demand accesses 2513system.l2c.demand_miss_rate::cpu1.data 0.475086 # miss rate for demand accesses 2514system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.530362 # miss rate for demand accesses 2515system.l2c.demand_miss_rate::total 0.514916 # miss rate for demand accesses 2516system.l2c.overall_miss_rate::cpu0.dtb.walker 0.242593 # miss rate for overall accesses 2517system.l2c.overall_miss_rate::cpu0.itb.walker 0.014493 # miss rate for overall accesses 2518system.l2c.overall_miss_rate::cpu0.inst 0.319827 # miss rate for overall accesses 2519system.l2c.overall_miss_rate::cpu0.data 0.281102 # miss rate for overall accesses 2520system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.735275 # miss rate for overall accesses 2521system.l2c.overall_miss_rate::cpu1.dtb.walker 0.086331 # miss rate for overall accesses 2522system.l2c.overall_miss_rate::cpu1.inst 0.158546 # miss rate for overall accesses 2523system.l2c.overall_miss_rate::cpu1.data 0.475086 # miss rate for overall accesses 2524system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.530362 # miss rate for overall accesses 2525system.l2c.overall_miss_rate::total 0.514916 # miss rate for overall accesses 2526system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 86835.877863 # average ReadReq miss latency |
| 2528system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82500 # average ReadReq miss latency | 2527system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82500 # average ReadReq miss latency |
| 2529system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80523.259391 # average ReadReq miss latency 2530system.l2c.ReadReq_avg_miss_latency::cpu0.data 88485.437380 # average ReadReq miss latency 2531system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 103632.176476 # average ReadReq miss latency 2532system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87227.272727 # average ReadReq miss latency 2533system.l2c.ReadReq_avg_miss_latency::cpu1.inst 82848.290816 # average ReadReq miss latency 2534system.l2c.ReadReq_avg_miss_latency::cpu1.data 89210.487633 # average ReadReq miss latency 2535system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 129724.878952 # average ReadReq miss latency 2536system.l2c.ReadReq_avg_miss_latency::total 100238.200294 # average ReadReq miss latency 2537system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1169.702112 # average UpgradeReq miss latency 2538system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1092.521151 # average UpgradeReq miss latency 2539system.l2c.UpgradeReq_avg_miss_latency::total 1150.992535 # average UpgradeReq miss latency 2540system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1841.411765 # average SCUpgradeReq miss latency 2541system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 961.356974 # average SCUpgradeReq miss latency 2542system.l2c.SCUpgradeReq_avg_miss_latency::total 1273.360122 # average SCUpgradeReq miss latency 2543system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91835.618997 # average ReadExReq miss latency 2544system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81466.447485 # average ReadExReq miss latency 2545system.l2c.ReadExReq_avg_miss_latency::total 87422.563167 # average ReadExReq miss latency 2546system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86278.985507 # average overall miss latency | 2528system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80586.458844 # average ReadReq miss latency 2529system.l2c.ReadReq_avg_miss_latency::cpu0.data 88176.655264 # average ReadReq miss latency 2530system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 103243.997434 # average ReadReq miss latency 2531system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 85020.833333 # average ReadReq miss latency 2532system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83348.980174 # average ReadReq miss latency 2533system.l2c.ReadReq_avg_miss_latency::cpu1.data 88524.766355 # average ReadReq miss latency 2534system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 131755.394804 # average ReadReq miss latency 2535system.l2c.ReadReq_avg_miss_latency::total 99980.057748 # average ReadReq miss latency 2536system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1300.826106 # average UpgradeReq miss latency 2537system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 991.284060 # average UpgradeReq miss latency 2538system.l2c.UpgradeReq_avg_miss_latency::total 1226.369654 # average UpgradeReq miss latency 2539system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1805.546392 # average SCUpgradeReq miss latency 2540system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1146.770249 # average SCUpgradeReq miss latency 2541system.l2c.SCUpgradeReq_avg_miss_latency::total 1374.640346 # average SCUpgradeReq miss latency 2542system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91898.313560 # average ReadExReq miss latency 2543system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82183.403042 # average ReadExReq miss latency 2544system.l2c.ReadExReq_avg_miss_latency::total 87762.169352 # average ReadExReq miss latency 2545system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86835.877863 # average overall miss latency |
| 2547system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency | 2546system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency |
| 2548system.l2c.demand_avg_miss_latency::cpu0.inst 80523.259391 # average overall miss latency 2549system.l2c.demand_avg_miss_latency::cpu0.data 90270.296044 # average overall miss latency 2550system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 103632.176476 # average overall miss latency 2551system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87227.272727 # average overall miss latency 2552system.l2c.demand_avg_miss_latency::cpu1.inst 82848.290816 # average overall miss latency 2553system.l2c.demand_avg_miss_latency::cpu1.data 82392.818979 # average overall miss latency 2554system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 129724.878952 # average overall miss latency 2555system.l2c.demand_avg_miss_latency::total 98959.999409 # average overall miss latency 2556system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86278.985507 # average overall miss latency | 2547system.l2c.demand_avg_miss_latency::cpu0.inst 80586.458844 # average overall miss latency 2548system.l2c.demand_avg_miss_latency::cpu0.data 90169.977218 # average overall miss latency 2549system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 103243.997434 # average overall miss latency 2550system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85020.833333 # average overall miss latency 2551system.l2c.demand_avg_miss_latency::cpu1.inst 83348.980174 # average overall miss latency 2552system.l2c.demand_avg_miss_latency::cpu1.data 83205.895318 # average overall miss latency 2553system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 131755.394804 # average overall miss latency 2554system.l2c.demand_avg_miss_latency::total 98756.659338 # average overall miss latency 2555system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86835.877863 # average overall miss latency |
| 2557system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency | 2556system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency |
| 2558system.l2c.overall_avg_miss_latency::cpu0.inst 80523.259391 # average overall miss latency 2559system.l2c.overall_avg_miss_latency::cpu0.data 90270.296044 # average overall miss latency 2560system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 103632.176476 # average overall miss latency 2561system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87227.272727 # average overall miss latency 2562system.l2c.overall_avg_miss_latency::cpu1.inst 82848.290816 # average overall miss latency 2563system.l2c.overall_avg_miss_latency::cpu1.data 82392.818979 # average overall miss latency 2564system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 129724.878952 # average overall miss latency 2565system.l2c.overall_avg_miss_latency::total 98959.999409 # average overall miss latency | 2557system.l2c.overall_avg_miss_latency::cpu0.inst 80586.458844 # average overall miss latency 2558system.l2c.overall_avg_miss_latency::cpu0.data 90169.977218 # average overall miss latency 2559system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 103243.997434 # average overall miss latency 2560system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85020.833333 # average overall miss latency 2561system.l2c.overall_avg_miss_latency::cpu1.inst 83348.980174 # average overall miss latency 2562system.l2c.overall_avg_miss_latency::cpu1.data 83205.895318 # average overall miss latency 2563system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 131755.394804 # average overall miss latency 2564system.l2c.overall_avg_miss_latency::total 98756.659338 # average overall miss latency |
| 2566system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2567system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2568system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2569system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2570system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2571system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2572system.l2c.fast_writes 0 # number of fast writes performed 2573system.l2c.cache_copies 0 # number of cache copies performed | 2565system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2566system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2567system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2568system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2569system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2570system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2571system.l2c.fast_writes 0 # number of fast writes performed 2572system.l2c.cache_copies 0 # number of cache copies performed |
| 2574system.l2c.writebacks::writebacks 102156 # number of writebacks 2575system.l2c.writebacks::total 102156 # number of writebacks 2576system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 2577system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 2578system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 2579system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 2580system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 2581system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 2582system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 138 # number of ReadReq MSHR misses | 2573system.l2c.writebacks::writebacks 101997 # number of writebacks 2574system.l2c.writebacks::total 101997 # number of writebacks 2575system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits 2576system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 2577system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits 2578system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits 2579system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits 2580system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits 2581system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 131 # number of ReadReq MSHR misses |
| 2583system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses | 2582system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses |
| 2584system.l2c.ReadReq_mshr_misses::cpu0.inst 22733 # number of ReadReq MSHR misses 2585system.l2c.ReadReq_mshr_misses::cpu0.data 9861 # number of ReadReq MSHR misses 2586system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 133208 # number of ReadReq MSHR misses 2587system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 22 # number of ReadReq MSHR misses 2588system.l2c.ReadReq_mshr_misses::cpu1.inst 3332 # number of ReadReq MSHR misses 2589system.l2c.ReadReq_mshr_misses::cpu1.data 1132 # number of ReadReq MSHR misses 2590system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 6262 # number of ReadReq MSHR misses 2591system.l2c.ReadReq_mshr_misses::total 176689 # number of ReadReq MSHR misses 2592system.l2c.UpgradeReq_mshr_misses::cpu0.data 9235 # number of UpgradeReq MSHR misses 2593system.l2c.UpgradeReq_mshr_misses::cpu1.data 2955 # number of UpgradeReq MSHR misses 2594system.l2c.UpgradeReq_mshr_misses::total 12190 # number of UpgradeReq MSHR misses 2595system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 697 # number of SCUpgradeReq MSHR misses 2596system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1269 # number of SCUpgradeReq MSHR misses 2597system.l2c.SCUpgradeReq_mshr_misses::total 1966 # number of SCUpgradeReq MSHR misses 2598system.l2c.ReadExReq_mshr_misses::cpu0.data 11244 # number of ReadExReq MSHR misses 2599system.l2c.ReadExReq_mshr_misses::cpu1.data 8331 # number of ReadExReq MSHR misses 2600system.l2c.ReadExReq_mshr_misses::total 19575 # number of ReadExReq MSHR misses 2601system.l2c.demand_mshr_misses::cpu0.dtb.walker 138 # number of demand (read+write) MSHR misses | 2583system.l2c.ReadReq_mshr_misses::cpu0.inst 22668 # number of ReadReq MSHR misses 2584system.l2c.ReadReq_mshr_misses::cpu0.data 9764 # number of ReadReq MSHR misses 2585system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 132484 # number of ReadReq MSHR misses 2586system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 12 # number of ReadReq MSHR misses 2587system.l2c.ReadReq_mshr_misses::cpu1.inst 3329 # number of ReadReq MSHR misses 2588system.l2c.ReadReq_mshr_misses::cpu1.data 1605 # number of ReadReq MSHR misses 2589system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 6236 # number of ReadReq MSHR misses 2590system.l2c.ReadReq_mshr_misses::total 176230 # number of ReadReq MSHR misses 2591system.l2c.UpgradeReq_mshr_misses::cpu0.data 9270 # number of UpgradeReq MSHR misses 2592system.l2c.UpgradeReq_mshr_misses::cpu1.data 2936 # number of UpgradeReq MSHR misses 2593system.l2c.UpgradeReq_mshr_misses::total 12206 # number of UpgradeReq MSHR misses 2594system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 679 # number of SCUpgradeReq MSHR misses 2595system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1284 # number of SCUpgradeReq MSHR misses 2596system.l2c.SCUpgradeReq_mshr_misses::total 1963 # number of SCUpgradeReq MSHR misses 2597system.l2c.ReadExReq_mshr_misses::cpu0.data 11261 # number of ReadExReq MSHR misses 2598system.l2c.ReadExReq_mshr_misses::cpu1.data 8349 # number of ReadExReq MSHR misses 2599system.l2c.ReadExReq_mshr_misses::total 19610 # number of ReadExReq MSHR misses 2600system.l2c.demand_mshr_misses::cpu0.dtb.walker 131 # number of demand (read+write) MSHR misses |
| 2602system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses | 2601system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses |
| 2603system.l2c.demand_mshr_misses::cpu0.inst 22733 # number of demand (read+write) MSHR misses 2604system.l2c.demand_mshr_misses::cpu0.data 21105 # number of demand (read+write) MSHR misses 2605system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133208 # number of demand (read+write) MSHR misses 2606system.l2c.demand_mshr_misses::cpu1.dtb.walker 22 # number of demand (read+write) MSHR misses 2607system.l2c.demand_mshr_misses::cpu1.inst 3332 # number of demand (read+write) MSHR misses 2608system.l2c.demand_mshr_misses::cpu1.data 9463 # number of demand (read+write) MSHR misses 2609system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6262 # number of demand (read+write) MSHR misses 2610system.l2c.demand_mshr_misses::total 196264 # number of demand (read+write) MSHR misses 2611system.l2c.overall_mshr_misses::cpu0.dtb.walker 138 # number of overall MSHR misses | 2602system.l2c.demand_mshr_misses::cpu0.inst 22668 # number of demand (read+write) MSHR misses 2603system.l2c.demand_mshr_misses::cpu0.data 21025 # number of demand (read+write) MSHR misses 2604system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 132484 # number of demand (read+write) MSHR misses 2605system.l2c.demand_mshr_misses::cpu1.dtb.walker 12 # number of demand (read+write) MSHR misses 2606system.l2c.demand_mshr_misses::cpu1.inst 3329 # number of demand (read+write) MSHR misses 2607system.l2c.demand_mshr_misses::cpu1.data 9954 # number of demand (read+write) MSHR misses 2608system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6236 # number of demand (read+write) MSHR misses 2609system.l2c.demand_mshr_misses::total 195840 # number of demand (read+write) MSHR misses 2610system.l2c.overall_mshr_misses::cpu0.dtb.walker 131 # number of overall MSHR misses |
| 2612system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses | 2611system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses |
| 2613system.l2c.overall_mshr_misses::cpu0.inst 22733 # number of overall MSHR misses 2614system.l2c.overall_mshr_misses::cpu0.data 21105 # number of overall MSHR misses 2615system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133208 # number of overall MSHR misses 2616system.l2c.overall_mshr_misses::cpu1.dtb.walker 22 # number of overall MSHR misses 2617system.l2c.overall_mshr_misses::cpu1.inst 3332 # number of overall MSHR misses 2618system.l2c.overall_mshr_misses::cpu1.data 9463 # number of overall MSHR misses 2619system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6262 # number of overall MSHR misses 2620system.l2c.overall_mshr_misses::total 196264 # number of overall MSHR misses | 2612system.l2c.overall_mshr_misses::cpu0.inst 22668 # number of overall MSHR misses 2613system.l2c.overall_mshr_misses::cpu0.data 21025 # number of overall MSHR misses 2614system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 132484 # number of overall MSHR misses 2615system.l2c.overall_mshr_misses::cpu1.dtb.walker 12 # number of overall MSHR misses 2616system.l2c.overall_mshr_misses::cpu1.inst 3329 # number of overall MSHR misses 2617system.l2c.overall_mshr_misses::cpu1.data 9954 # number of overall MSHR misses 2618system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6236 # number of overall MSHR misses 2619system.l2c.overall_mshr_misses::total 195840 # number of overall MSHR misses |
| 2621system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3367 # number of ReadReq MSHR uncacheable | 2620system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3367 # number of ReadReq MSHR uncacheable |
| 2622system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20386 # number of ReadReq MSHR uncacheable | 2621system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20388 # number of ReadReq MSHR uncacheable |
| 2623system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 2624system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14601 # number of ReadReq MSHR uncacheable | 2622system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 2623system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14601 # number of ReadReq MSHR uncacheable |
| 2625system.l2c.ReadReq_mshr_uncacheable::total 38466 # number of ReadReq MSHR uncacheable 2626system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19085 # number of WriteReq MSHR uncacheable 2627system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11936 # number of WriteReq MSHR uncacheable 2628system.l2c.WriteReq_mshr_uncacheable::total 31021 # number of WriteReq MSHR uncacheable | 2624system.l2c.ReadReq_mshr_uncacheable::total 38468 # number of ReadReq MSHR uncacheable 2625system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19084 # number of WriteReq MSHR uncacheable 2626system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11935 # number of WriteReq MSHR uncacheable 2627system.l2c.WriteReq_mshr_uncacheable::total 31019 # number of WriteReq MSHR uncacheable |
| 2629system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3367 # number of overall MSHR uncacheable misses | 2628system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3367 # number of overall MSHR uncacheable misses |
| 2630system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39471 # number of overall MSHR uncacheable misses | 2629system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39472 # number of overall MSHR uncacheable misses |
| 2631system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses | 2630system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses |
| 2632system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26537 # number of overall MSHR uncacheable misses | 2631system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26536 # number of overall MSHR uncacheable misses |
| 2633system.l2c.overall_mshr_uncacheable_misses::total 69487 # number of overall MSHR uncacheable misses | 2632system.l2c.overall_mshr_uncacheable_misses::total 69487 # number of overall MSHR uncacheable misses |
| 2634system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10173000 # number of ReadReq MSHR miss cycles | 2633system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 9728000 # number of ReadReq MSHR miss cycles |
| 2635system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 70000 # number of ReadReq MSHR miss cycles | 2634system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 70000 # number of ReadReq MSHR miss cycles |
| 2636system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1545823471 # number of ReadReq MSHR miss cycles 2637system.l2c.ReadReq_mshr_miss_latency::cpu0.data 749260602 # number of ReadReq MSHR miss cycles 2638system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12163111570 # number of ReadReq MSHR miss cycles 2639system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1642500 # number of ReadReq MSHR miss cycles 2640system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 234290995 # number of ReadReq MSHR miss cycles 2641system.l2c.ReadReq_mshr_miss_latency::cpu1.data 86797728 # number of ReadReq MSHR miss cycles 2642system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 735598364 # number of ReadReq MSHR miss cycles 2643system.l2c.ReadReq_mshr_miss_latency::total 15526768230 # number of ReadReq MSHR miss cycles 2644system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 164742191 # number of UpgradeReq MSHR miss cycles 2645system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 52500445 # number of UpgradeReq MSHR miss cycles 2646system.l2c.UpgradeReq_mshr_miss_latency::total 217242636 # number of UpgradeReq MSHR miss cycles 2647system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12465195 # number of SCUpgradeReq MSHR miss cycles 2648system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22538766 # number of SCUpgradeReq MSHR miss cycles 2649system.l2c.SCUpgradeReq_mshr_miss_latency::total 35003961 # number of SCUpgradeReq MSHR miss cycles 2650system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 893597800 # number of ReadExReq MSHR miss cycles 2651system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 574508526 # number of ReadExReq MSHR miss cycles 2652system.l2c.ReadExReq_mshr_miss_latency::total 1468106326 # number of ReadExReq MSHR miss cycles 2653system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10173000 # number of demand (read+write) MSHR miss cycles | 2635system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1542775978 # number of ReadReq MSHR miss cycles 2636system.l2c.ReadReq_mshr_miss_latency::cpu0.data 738824138 # number of ReadReq MSHR miss cycles 2637system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12045165114 # number of ReadReq MSHR miss cycles 2638system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 870250 # number of ReadReq MSHR miss cycles 2639system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 235730745 # number of ReadReq MSHR miss cycles 2640system.l2c.ReadReq_mshr_miss_latency::cpu1.data 121970250 # number of ReadReq MSHR miss cycles 2641system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 745216962 # number of ReadReq MSHR miss cycles 2642system.l2c.ReadReq_mshr_miss_latency::total 15440351437 # number of ReadReq MSHR miss cycles 2643system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 165428726 # number of UpgradeReq MSHR miss cycles 2644system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 52162926 # number of UpgradeReq MSHR miss cycles 2645system.l2c.UpgradeReq_mshr_miss_latency::total 217591652 # number of UpgradeReq MSHR miss cycles 2646system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12163677 # number of SCUpgradeReq MSHR miss cycles 2647system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22807281 # number of SCUpgradeReq MSHR miss cycles 2648system.l2c.SCUpgradeReq_mshr_miss_latency::total 34970958 # number of SCUpgradeReq MSHR miss cycles 2649system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 895596591 # number of ReadExReq MSHR miss cycles 2650system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 581734768 # number of ReadExReq MSHR miss cycles 2651system.l2c.ReadExReq_mshr_miss_latency::total 1477331359 # number of ReadExReq MSHR miss cycles 2652system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 9728000 # number of demand (read+write) MSHR miss cycles |
| 2654system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 70000 # number of demand (read+write) MSHR miss cycles | 2653system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 70000 # number of demand (read+write) MSHR miss cycles |
| 2655system.l2c.demand_mshr_miss_latency::cpu0.inst 1545823471 # number of demand (read+write) MSHR miss cycles 2656system.l2c.demand_mshr_miss_latency::cpu0.data 1642858402 # number of demand (read+write) MSHR miss cycles 2657system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12163111570 # number of demand (read+write) MSHR miss cycles 2658system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1642500 # number of demand (read+write) MSHR miss cycles 2659system.l2c.demand_mshr_miss_latency::cpu1.inst 234290995 # number of demand (read+write) MSHR miss cycles 2660system.l2c.demand_mshr_miss_latency::cpu1.data 661306254 # number of demand (read+write) MSHR miss cycles 2661system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 735598364 # number of demand (read+write) MSHR miss cycles 2662system.l2c.demand_mshr_miss_latency::total 16994874556 # number of demand (read+write) MSHR miss cycles 2663system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10173000 # number of overall MSHR miss cycles | 2654system.l2c.demand_mshr_miss_latency::cpu0.inst 1542775978 # number of demand (read+write) MSHR miss cycles 2655system.l2c.demand_mshr_miss_latency::cpu0.data 1634420729 # number of demand (read+write) MSHR miss cycles 2656system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12045165114 # number of demand (read+write) MSHR miss cycles 2657system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 870250 # number of demand (read+write) MSHR miss cycles 2658system.l2c.demand_mshr_miss_latency::cpu1.inst 235730745 # number of demand (read+write) MSHR miss cycles 2659system.l2c.demand_mshr_miss_latency::cpu1.data 703705018 # number of demand (read+write) MSHR miss cycles 2660system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 745216962 # number of demand (read+write) MSHR miss cycles 2661system.l2c.demand_mshr_miss_latency::total 16917682796 # number of demand (read+write) MSHR miss cycles 2662system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 9728000 # number of overall MSHR miss cycles |
| 2664system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 70000 # number of overall MSHR miss cycles | 2663system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 70000 # number of overall MSHR miss cycles |
| 2665system.l2c.overall_mshr_miss_latency::cpu0.inst 1545823471 # number of overall MSHR miss cycles 2666system.l2c.overall_mshr_miss_latency::cpu0.data 1642858402 # number of overall MSHR miss cycles 2667system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12163111570 # number of overall MSHR miss cycles 2668system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1642500 # number of overall MSHR miss cycles 2669system.l2c.overall_mshr_miss_latency::cpu1.inst 234290995 # number of overall MSHR miss cycles 2670system.l2c.overall_mshr_miss_latency::cpu1.data 661306254 # number of overall MSHR miss cycles 2671system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 735598364 # number of overall MSHR miss cycles 2672system.l2c.overall_mshr_miss_latency::total 16994874556 # number of overall MSHR miss cycles | 2664system.l2c.overall_mshr_miss_latency::cpu0.inst 1542775978 # number of overall MSHR miss cycles 2665system.l2c.overall_mshr_miss_latency::cpu0.data 1634420729 # number of overall MSHR miss cycles 2666system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12045165114 # number of overall MSHR miss cycles 2667system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 870250 # number of overall MSHR miss cycles 2668system.l2c.overall_mshr_miss_latency::cpu1.inst 235730745 # number of overall MSHR miss cycles 2669system.l2c.overall_mshr_miss_latency::cpu1.data 703705018 # number of overall MSHR miss cycles 2670system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 745216962 # number of overall MSHR miss cycles 2671system.l2c.overall_mshr_miss_latency::total 16917682796 # number of overall MSHR miss cycles |
| 2673system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 204708000 # number of ReadReq MSHR uncacheable cycles | 2672system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 204708000 # number of ReadReq MSHR uncacheable cycles |
| 2674system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3714675750 # number of ReadReq MSHR uncacheable cycles 2675system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6791250 # number of ReadReq MSHR uncacheable cycles 2676system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919935500 # number of ReadReq MSHR uncacheable cycles 2677system.l2c.ReadReq_mshr_uncacheable_latency::total 5846110500 # number of ReadReq MSHR uncacheable cycles 2678system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2762262500 # number of WriteReq MSHR uncacheable cycles 2679system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1533068501 # number of WriteReq MSHR uncacheable cycles 2680system.l2c.WriteReq_mshr_uncacheable_latency::total 4295331001 # number of WriteReq MSHR uncacheable cycles | 2673system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3717048000 # number of ReadReq MSHR uncacheable cycles 2674system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6862750 # number of ReadReq MSHR uncacheable cycles 2675system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919952251 # number of ReadReq MSHR uncacheable cycles 2676system.l2c.ReadReq_mshr_uncacheable_latency::total 5848571001 # number of ReadReq MSHR uncacheable cycles 2677system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2762074500 # number of WriteReq MSHR uncacheable cycles 2678system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1533074001 # number of WriteReq MSHR uncacheable cycles 2679system.l2c.WriteReq_mshr_uncacheable_latency::total 4295148501 # number of WriteReq MSHR uncacheable cycles |
| 2681system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 204708000 # number of overall MSHR uncacheable cycles | 2680system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 204708000 # number of overall MSHR uncacheable cycles |
| 2682system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6476938250 # number of overall MSHR uncacheable cycles 2683system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6791250 # number of overall MSHR uncacheable cycles 2684system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3453004001 # number of overall MSHR uncacheable cycles 2685system.l2c.overall_mshr_uncacheable_latency::total 10141441501 # number of overall MSHR uncacheable cycles 2686system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.254613 # mshr miss rate for ReadReq accesses 2687system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.011628 # mshr miss rate for ReadReq accesses 2688system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.319823 # mshr miss rate for ReadReq accesses 2689system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.165536 # mshr miss rate for ReadReq accesses 2690system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736998 # mshr miss rate for ReadReq accesses 2691system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.151724 # mshr miss rate for ReadReq accesses 2692system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.158856 # mshr miss rate for ReadReq accesses 2693system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.108543 # mshr miss rate for ReadReq accesses 2694system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.534939 # mshr miss rate for ReadReq accesses 2695system.l2c.ReadReq_mshr_miss_rate::total 0.497283 # mshr miss rate for ReadReq accesses 2696system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.765247 # mshr miss rate for UpgradeReq accesses 2697system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.795210 # mshr miss rate for UpgradeReq accesses 2698system.l2c.UpgradeReq_mshr_miss_rate::total 0.772301 # mshr miss rate for UpgradeReq accesses 2699system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.812354 # mshr miss rate for SCUpgradeReq accesses 2700system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.884321 # mshr miss rate for SCUpgradeReq accesses 2701system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.857392 # mshr miss rate for SCUpgradeReq accesses 2702system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.727767 # mshr miss rate for ReadExReq accesses 2703system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.831437 # mshr miss rate for ReadExReq accesses 2704system.l2c.ReadExReq_mshr_miss_rate::total 0.768551 # mshr miss rate for ReadExReq accesses 2705system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.254613 # mshr miss rate for demand accesses 2706system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011628 # mshr miss rate for demand accesses 2707system.l2c.demand_mshr_miss_rate::cpu0.inst 0.319823 # mshr miss rate for demand accesses 2708system.l2c.demand_mshr_miss_rate::cpu0.data 0.281325 # mshr miss rate for demand accesses 2709system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736998 # mshr miss rate for demand accesses 2710system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.151724 # mshr miss rate for demand accesses 2711system.l2c.demand_mshr_miss_rate::cpu1.inst 0.158856 # mshr miss rate for demand accesses 2712system.l2c.demand_mshr_miss_rate::cpu1.data 0.462761 # mshr miss rate for demand accesses 2713system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.534939 # mshr miss rate for demand accesses 2714system.l2c.demand_mshr_miss_rate::total 0.515428 # mshr miss rate for demand accesses 2715system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.254613 # mshr miss rate for overall accesses 2716system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011628 # mshr miss rate for overall accesses 2717system.l2c.overall_mshr_miss_rate::cpu0.inst 0.319823 # mshr miss rate for overall accesses 2718system.l2c.overall_mshr_miss_rate::cpu0.data 0.281325 # mshr miss rate for overall accesses 2719system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736998 # mshr miss rate for overall accesses 2720system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.151724 # mshr miss rate for overall accesses 2721system.l2c.overall_mshr_miss_rate::cpu1.inst 0.158856 # mshr miss rate for overall accesses 2722system.l2c.overall_mshr_miss_rate::cpu1.data 0.462761 # mshr miss rate for overall accesses 2723system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.534939 # mshr miss rate for overall accesses 2724system.l2c.overall_mshr_miss_rate::total 0.515428 # mshr miss rate for overall accesses 2725system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73717.391304 # average ReadReq mshr miss latency | 2681system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6479122500 # number of overall MSHR uncacheable cycles 2682system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6862750 # number of overall MSHR uncacheable cycles 2683system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3453026252 # number of overall MSHR uncacheable cycles 2684system.l2c.overall_mshr_uncacheable_latency::total 10143719502 # number of overall MSHR uncacheable cycles 2685system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.242593 # mshr miss rate for ReadReq accesses 2686system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.014493 # mshr miss rate for ReadReq accesses 2687system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.319799 # mshr miss rate for ReadReq accesses 2688system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.164896 # mshr miss rate for ReadReq accesses 2689system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735275 # mshr miss rate for ReadReq accesses 2690system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.086331 # mshr miss rate for ReadReq accesses 2691system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.158546 # mshr miss rate for ReadReq accesses 2692system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.146629 # mshr miss rate for ReadReq accesses 2693system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530362 # mshr miss rate for ReadReq accesses 2694system.l2c.ReadReq_mshr_miss_rate::total 0.496772 # mshr miss rate for ReadReq accesses 2695system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.736767 # mshr miss rate for UpgradeReq accesses 2696system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.788823 # mshr miss rate for UpgradeReq accesses 2697system.l2c.UpgradeReq_mshr_miss_rate::total 0.748651 # mshr miss rate for UpgradeReq accesses 2698system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.806413 # mshr miss rate for SCUpgradeReq accesses 2699system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.888581 # mshr miss rate for SCUpgradeReq accesses 2700system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.858330 # mshr miss rate for SCUpgradeReq accesses 2701system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.722693 # mshr miss rate for ReadExReq accesses 2702system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.834399 # mshr miss rate for ReadExReq accesses 2703system.l2c.ReadExReq_mshr_miss_rate::total 0.766375 # mshr miss rate for ReadExReq accesses 2704system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.242593 # mshr miss rate for demand accesses 2705system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.014493 # mshr miss rate for demand accesses 2706system.l2c.demand_mshr_miss_rate::cpu0.inst 0.319799 # mshr miss rate for demand accesses 2707system.l2c.demand_mshr_miss_rate::cpu0.data 0.281102 # mshr miss rate for demand accesses 2708system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735275 # mshr miss rate for demand accesses 2709system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.086331 # mshr miss rate for demand accesses 2710system.l2c.demand_mshr_miss_rate::cpu1.inst 0.158546 # mshr miss rate for demand accesses 2711system.l2c.demand_mshr_miss_rate::cpu1.data 0.475086 # mshr miss rate for demand accesses 2712system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530362 # mshr miss rate for demand accesses 2713system.l2c.demand_mshr_miss_rate::total 0.514910 # mshr miss rate for demand accesses 2714system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.242593 # mshr miss rate for overall accesses 2715system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.014493 # mshr miss rate for overall accesses 2716system.l2c.overall_mshr_miss_rate::cpu0.inst 0.319799 # mshr miss rate for overall accesses 2717system.l2c.overall_mshr_miss_rate::cpu0.data 0.281102 # mshr miss rate for overall accesses 2718system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735275 # mshr miss rate for overall accesses 2719system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.086331 # mshr miss rate for overall accesses 2720system.l2c.overall_mshr_miss_rate::cpu1.inst 0.158546 # mshr miss rate for overall accesses 2721system.l2c.overall_mshr_miss_rate::cpu1.data 0.475086 # mshr miss rate for overall accesses 2722system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530362 # mshr miss rate for overall accesses 2723system.l2c.overall_mshr_miss_rate::total 0.514910 # mshr miss rate for overall accesses 2724system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 74259.541985 # average ReadReq mshr miss latency |
| 2726system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency | 2725system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency |
| 2727system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67999.096952 # average ReadReq mshr miss latency 2728system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75982.212960 # average ReadReq mshr miss latency 2729system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91309.167392 # average ReadReq mshr miss latency 2730system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74659.090909 # average ReadReq mshr miss latency 2731system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70315.424670 # average ReadReq mshr miss latency 2732system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76676.438163 # average ReadReq mshr miss latency 2733system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117470.195465 # average ReadReq mshr miss latency 2734system.l2c.ReadReq_avg_mshr_miss_latency::total 87876.258454 # average ReadReq mshr miss latency 2735system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17838.894532 # average UpgradeReq mshr miss latency 2736system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17766.648054 # average UpgradeReq mshr miss latency 2737system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17821.381132 # average UpgradeReq mshr miss latency 2738system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17884.067432 # average SCUpgradeReq mshr miss latency 2739system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17761.044917 # average SCUpgradeReq mshr miss latency 2740system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17804.659715 # average SCUpgradeReq mshr miss latency 2741system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79473.301316 # average ReadExReq mshr miss latency 2742system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68960.332013 # average ReadExReq mshr miss latency 2743system.l2c.ReadExReq_avg_mshr_miss_latency::total 74999.046028 # average ReadExReq mshr miss latency 2744system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73717.391304 # average overall mshr miss latency | 2726system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68059.642580 # average ReadReq mshr miss latency 2727system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75668.182917 # average ReadReq mshr miss latency 2728system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90917.885284 # average ReadReq mshr miss latency 2729system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72520.833333 # average ReadReq mshr miss latency 2730system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70811.278162 # average ReadReq mshr miss latency 2731system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75993.925234 # average ReadReq mshr miss latency 2732system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119502.399294 # average ReadReq mshr miss latency 2733system.l2c.ReadReq_avg_mshr_miss_latency::total 87614.772950 # average ReadReq mshr miss latency 2734system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17845.601510 # average UpgradeReq mshr miss latency 2735system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17766.664169 # average UpgradeReq mshr miss latency 2736system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17826.614124 # average UpgradeReq mshr miss latency 2737system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17914.104566 # average SCUpgradeReq mshr miss latency 2738system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17762.679907 # average SCUpgradeReq mshr miss latency 2739system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17815.057565 # average SCUpgradeReq mshr miss latency 2740system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79530.822396 # average ReadExReq mshr miss latency 2741system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69677.179063 # average ReadExReq mshr miss latency 2742system.l2c.ReadExReq_avg_mshr_miss_latency::total 75335.612392 # average ReadExReq mshr miss latency 2743system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 74259.541985 # average overall mshr miss latency |
| 2745system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency | 2744system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency |
| 2746system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67999.096952 # average overall mshr miss latency 2747system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77842.141767 # average overall mshr miss latency 2748system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91309.167392 # average overall mshr miss latency 2749system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74659.090909 # average overall mshr miss latency 2750system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70315.424670 # average overall mshr miss latency 2751system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69883.361936 # average overall mshr miss latency 2752system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117470.195465 # average overall mshr miss latency 2753system.l2c.demand_avg_mshr_miss_latency::total 86591.909652 # average overall mshr miss latency 2754system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73717.391304 # average overall mshr miss latency | 2745system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68059.642580 # average overall mshr miss latency 2746system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77737.014459 # average overall mshr miss latency 2747system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90917.885284 # average overall mshr miss latency 2748system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72520.833333 # average overall mshr miss latency 2749system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70811.278162 # average overall mshr miss latency 2750system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70695.702029 # average overall mshr miss latency 2751system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119502.399294 # average overall mshr miss latency 2752system.l2c.demand_avg_mshr_miss_latency::total 86385.226695 # average overall mshr miss latency 2753system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74259.541985 # average overall mshr miss latency |
| 2755system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency | 2754system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency |
| 2756system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67999.096952 # average overall mshr miss latency 2757system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77842.141767 # average overall mshr miss latency 2758system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91309.167392 # average overall mshr miss latency 2759system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74659.090909 # average overall mshr miss latency 2760system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70315.424670 # average overall mshr miss latency 2761system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69883.361936 # average overall mshr miss latency 2762system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117470.195465 # average overall mshr miss latency 2763system.l2c.overall_avg_mshr_miss_latency::total 86591.909652 # average overall mshr miss latency | 2755system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68059.642580 # average overall mshr miss latency 2756system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77737.014459 # average overall mshr miss latency 2757system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90917.885284 # average overall mshr miss latency 2758system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72520.833333 # average overall mshr miss latency 2759system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70811.278162 # average overall mshr miss latency 2760system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70695.702029 # average overall mshr miss latency 2761system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119502.399294 # average overall mshr miss latency 2762system.l2c.overall_avg_mshr_miss_latency::total 86385.226695 # average overall mshr miss latency |
| 2764system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average ReadReq mshr uncacheable latency | 2763system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average ReadReq mshr uncacheable latency |
| 2765system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182216.999411 # average ReadReq mshr uncacheable latency 2766system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60636.160714 # average ReadReq mshr uncacheable latency 2767system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131493.425108 # average ReadReq mshr uncacheable latency 2768system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 151981.243176 # average ReadReq mshr uncacheable latency 2769system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144734.739324 # average WriteReq mshr uncacheable latency 2770system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 128440.725620 # average WriteReq mshr uncacheable latency 2771system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138465.265498 # average WriteReq mshr uncacheable latency | 2764system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182315.479694 # average ReadReq mshr uncacheable latency 2765system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61274.553571 # average ReadReq mshr uncacheable latency 2766system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131494.572358 # average ReadReq mshr uncacheable latency 2767system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 152037.303759 # average ReadReq mshr uncacheable latency 2768system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144732.472228 # average WriteReq mshr uncacheable latency 2769system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 128451.948136 # average WriteReq mshr uncacheable latency 2770system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138468.309778 # average WriteReq mshr uncacheable latency |
| 2772system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average overall mshr uncacheable latency | 2771system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average overall mshr uncacheable latency |
| 2773system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164093.594031 # average overall mshr uncacheable latency 2774system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60636.160714 # average overall mshr uncacheable latency 2775system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 130120.360289 # average overall mshr uncacheable latency 2776system.l2c.overall_avg_mshr_uncacheable_latency::total 145947.321096 # average overall mshr uncacheable latency | 2772system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164144.773510 # average overall mshr uncacheable latency 2773system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61274.553571 # average overall mshr uncacheable latency 2774system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 130126.102352 # average overall mshr uncacheable latency 2775system.l2c.overall_avg_mshr_uncacheable_latency::total 145980.104221 # average overall mshr uncacheable latency |
| 2777system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 2776system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2778system.membus.trans_dist::ReadReq 215398 # Transaction distribution 2779system.membus.trans_dist::ReadResp 215398 # Transaction distribution 2780system.membus.trans_dist::WriteReq 31021 # Transaction distribution 2781system.membus.trans_dist::WriteResp 31021 # Transaction distribution 2782system.membus.trans_dist::Writeback 138346 # Transaction distribution | 2777system.membus.trans_dist::ReadReq 214941 # Transaction distribution 2778system.membus.trans_dist::ReadResp 214941 # Transaction distribution 2779system.membus.trans_dist::WriteReq 31019 # Transaction distribution 2780system.membus.trans_dist::WriteResp 31019 # Transaction distribution 2781system.membus.trans_dist::Writeback 138187 # Transaction distribution |
| 2783system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2784system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution | 2782system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2783system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 2785system.membus.trans_dist::UpgradeReq 76455 # Transaction distribution 2786system.membus.trans_dist::SCUpgradeReq 40833 # Transaction distribution 2787system.membus.trans_dist::UpgradeResp 14266 # Transaction distribution 2788system.membus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution 2789system.membus.trans_dist::ReadExReq 39995 # Transaction distribution 2790system.membus.trans_dist::ReadExResp 19465 # Transaction distribution | 2784system.membus.trans_dist::UpgradeReq 76766 # Transaction distribution 2785system.membus.trans_dist::SCUpgradeReq 40830 # Transaction distribution 2786system.membus.trans_dist::UpgradeResp 14310 # Transaction distribution 2787system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution 2788system.membus.trans_dist::ReadExReq 39945 # Transaction distribution 2789system.membus.trans_dist::ReadExResp 19469 # Transaction distribution |
| 2791system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) 2792system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) | 2790system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) 2791system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) |
| 2793system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14158 # Packet count per connected master and slave (bytes) 2794system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 663047 # Packet count per connected master and slave (bytes) 2795system.membus.pkt_count_system.l2c.mem_side::total 785159 # Packet count per connected master and slave (bytes) | 2792system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14152 # Packet count per connected master and slave (bytes) 2793system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 662279 # Packet count per connected master and slave (bytes) 2794system.membus.pkt_count_system.l2c.mem_side::total 784385 # Packet count per connected master and slave (bytes) |
| 2796system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108896 # Packet count per connected master and slave (bytes) 2797system.membus.pkt_count_system.iocache.mem_side::total 108896 # Packet count per connected master and slave (bytes) | 2795system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108896 # Packet count per connected master and slave (bytes) 2796system.membus.pkt_count_system.iocache.mem_side::total 108896 # Packet count per connected master and slave (bytes) |
| 2798system.membus.pkt_count::total 894055 # Packet count per connected master and slave (bytes) | 2797system.membus.pkt_count::total 893281 # Packet count per connected master and slave (bytes) |
| 2799system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) 2800system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) | 2798system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) 2799system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) |
| 2801system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28316 # Cumulative packet size per connected master and slave (bytes) 2802system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19310684 # Cumulative packet size per connected master and slave (bytes) 2803system.membus.pkt_size_system.l2c.mem_side::total 19503012 # Cumulative packet size per connected master and slave (bytes) | 2800system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28304 # Cumulative packet size per connected master and slave (bytes) 2801system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19271336 # Cumulative packet size per connected master and slave (bytes) 2802system.membus.pkt_size_system.l2c.mem_side::total 19463652 # Cumulative packet size per connected master and slave (bytes) |
| 2804system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 2805system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) | 2803system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 2804system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) |
| 2806system.membus.pkt_size::total 24138468 # Cumulative packet size per connected master and slave (bytes) 2807system.membus.snoops 124155 # Total snoops (count) 2808system.membus.snoop_fanout::samples 578323 # Request fanout histogram | 2805system.membus.pkt_size::total 24099108 # Cumulative packet size per connected master and slave (bytes) 2806system.membus.snoops 124366 # Total snoops (count) 2807system.membus.snoop_fanout::samples 577962 # Request fanout histogram |
| 2809system.membus.snoop_fanout::mean 1 # Request fanout histogram 2810system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2811system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2812system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 2808system.membus.snoop_fanout::mean 1 # Request fanout histogram 2809system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2810system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2811system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 2813system.membus.snoop_fanout::1 578323 100.00% 100.00% # Request fanout histogram | 2812system.membus.snoop_fanout::1 577962 100.00% 100.00% # Request fanout histogram |
| 2814system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2815system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2816system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2817system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 2813system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2814system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2815system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2816system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 2818system.membus.snoop_fanout::total 578323 # Request fanout histogram 2819system.membus.reqLayer0.occupancy 88747000 # Layer occupancy (ticks) | 2817system.membus.snoop_fanout::total 577962 # Request fanout histogram 2818system.membus.reqLayer0.occupancy 91190000 # Layer occupancy (ticks) |
| 2820system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2821system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) 2822system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 2819system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2820system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) 2821system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 2823system.membus.reqLayer2.occupancy 12490999 # Layer occupancy (ticks) | 2822system.membus.reqLayer2.occupancy 12300498 # Layer occupancy (ticks) |
| 2824system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 2823system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 2825system.membus.reqLayer5.occupancy 1169123868 # Layer occupancy (ticks) | 2824system.membus.reqLayer5.occupancy 1168075116 # Layer occupancy (ticks) |
| 2826system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 2825system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 2827system.membus.respLayer2.occupancy 1173969642 # Layer occupancy (ticks) | 2826system.membus.respLayer2.occupancy 1171902830 # Layer occupancy (ticks) |
| 2828system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 2827system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2829system.membus.respLayer3.occupancy 37485233 # Layer occupancy (ticks) | 2828system.membus.respLayer3.occupancy 37484237 # Layer occupancy (ticks) |
| 2830system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2831system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2832system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2833system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2834system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2835system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2836system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2837system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 2854system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2855system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2856system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2857system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2858system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2859system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2860system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2861system.realview.ethernet.droppedPackets 0 # number of packets dropped | 2829system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2830system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2831system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2832system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2833system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2834system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2835system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2836system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 2853system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2854system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2855system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2856system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2857system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2858system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2859system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2860system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 2862system.toL2Bus.trans_dist::ReadReq 516846 # Transaction distribution 2863system.toL2Bus.trans_dist::ReadResp 516831 # Transaction distribution 2864system.toL2Bus.trans_dist::WriteReq 31021 # Transaction distribution 2865system.toL2Bus.trans_dist::WriteResp 31021 # Transaction distribution 2866system.toL2Bus.trans_dist::Writeback 232833 # Transaction distribution 2867system.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution 2868system.toL2Bus.trans_dist::UpgradeReq 79939 # Transaction distribution 2869system.toL2Bus.trans_dist::SCUpgradeReq 41160 # Transaction distribution 2870system.toL2Bus.trans_dist::UpgradeResp 121099 # Transaction distribution 2871system.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution 2872system.toL2Bus.trans_dist::UpgradeFailResp 16 # Transaction distribution 2873system.toL2Bus.trans_dist::ReadExReq 51726 # Transaction distribution 2874system.toL2Bus.trans_dist::ReadExResp 51726 # Transaction distribution 2875system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1083746 # Packet count per connected master and slave (bytes) 2876system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 338123 # Packet count per connected master and slave (bytes) 2877system.toL2Bus.pkt_count::total 1421869 # Packet count per connected master and slave (bytes) 2878system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34155096 # Cumulative packet size per connected master and slave (bytes) 2879system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5564428 # Cumulative packet size per connected master and slave (bytes) 2880system.toL2Bus.pkt_size::total 39719524 # Cumulative packet size per connected master and slave (bytes) 2881system.toL2Bus.snoops 288847 # Total snoops (count) 2882system.toL2Bus.snoop_fanout::samples 989795 # Request fanout histogram 2883system.toL2Bus.snoop_fanout::mean 1.036873 # Request fanout histogram 2884system.toL2Bus.snoop_fanout::stdev 0.188451 # Request fanout histogram | 2861system.toL2Bus.trans_dist::ReadReq 516760 # Transaction distribution 2862system.toL2Bus.trans_dist::ReadResp 516745 # Transaction distribution 2863system.toL2Bus.trans_dist::WriteReq 31019 # Transaction distribution 2864system.toL2Bus.trans_dist::WriteResp 31019 # Transaction distribution 2865system.toL2Bus.trans_dist::Writeback 232415 # Transaction distribution 2866system.toL2Bus.trans_dist::WriteInvalidateReq 36259 # Transaction distribution 2867system.toL2Bus.trans_dist::UpgradeReq 80723 # Transaction distribution 2868system.toL2Bus.trans_dist::SCUpgradeReq 41154 # Transaction distribution 2869system.toL2Bus.trans_dist::UpgradeResp 121877 # Transaction distribution 2870system.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution 2871system.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution 2872system.toL2Bus.trans_dist::ReadExReq 51826 # Transaction distribution 2873system.toL2Bus.trans_dist::ReadExResp 51826 # Transaction distribution 2874system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1082609 # Packet count per connected master and slave (bytes) 2875system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 339699 # Packet count per connected master and slave (bytes) 2876system.toL2Bus.pkt_count::total 1422308 # Packet count per connected master and slave (bytes) 2877system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34055964 # Cumulative packet size per connected master and slave (bytes) 2878system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5608584 # Cumulative packet size per connected master and slave (bytes) 2879system.toL2Bus.pkt_size::total 39664548 # Cumulative packet size per connected master and slave (bytes) 2880system.toL2Bus.snoops 289563 # Total snoops (count) 2881system.toL2Bus.snoop_fanout::samples 990166 # Request fanout histogram 2882system.toL2Bus.snoop_fanout::mean 1.036865 # Request fanout histogram 2883system.toL2Bus.snoop_fanout::stdev 0.188429 # Request fanout histogram |
| 2885system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2886system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 2884system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2885system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 2887system.toL2Bus.snoop_fanout::1 953298 96.31% 96.31% # Request fanout histogram 2888system.toL2Bus.snoop_fanout::2 36497 3.69% 100.00% # Request fanout histogram | 2886system.toL2Bus.snoop_fanout::1 953664 96.31% 96.31% # Request fanout histogram 2887system.toL2Bus.snoop_fanout::2 36502 3.69% 100.00% # Request fanout histogram |
| 2889system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2890system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2891system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 2888system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2889system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2890system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 2892system.toL2Bus.snoop_fanout::total 989795 # Request fanout histogram 2893system.toL2Bus.reqLayer0.occupancy 786931704 # Layer occupancy (ticks) | 2891system.toL2Bus.snoop_fanout::total 990166 # Request fanout histogram 2892system.toL2Bus.reqLayer0.occupancy 786658690 # Layer occupancy (ticks) |
| 2894system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2895system.toL2Bus.snoopLayer0.occupancy 342000 # Layer occupancy (ticks) 2896system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2893system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2894system.toL2Bus.snoopLayer0.occupancy 342000 # Layer occupancy (ticks) 2895system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2897system.toL2Bus.respLayer0.occupancy 682239026 # Layer occupancy (ticks) | 2896system.toL2Bus.respLayer0.occupancy 681591350 # Layer occupancy (ticks) |
| 2898system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 2897system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2899system.toL2Bus.respLayer1.occupancy 258695257 # Layer occupancy (ticks) | 2898system.toL2Bus.respLayer1.occupancy 259907159 # Layer occupancy (ticks) |
| 2900system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2901 2902---------- End Simulation Statistics ---------- | 2899system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2900 2901---------- End Simulation Statistics ---------- |