| stats.txt (10753:48a72150f82c) | stats.txt (10827:7f5467f2f8b8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.846097 # Number of seconds simulated 4sim_ticks 2846097440000 # Number of ticks simulated 5final_tick 2846097440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.846145 # Number of seconds simulated 4sim_ticks 2846145040000 # Number of ticks simulated 5final_tick 2846145040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 101530 # Simulator instruction rate (inst/s) 8host_op_rate 122947 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2278332577 # Simulator tick rate (ticks/s) 10host_mem_usage 584920 # Number of bytes of host memory used 11host_seconds 1249.20 # Real time elapsed on the host 12sim_insts 126830911 # Number of instructions simulated 13sim_ops 153585651 # Number of ops (including micro ops) simulated | 7host_inst_rate 162017 # Simulator instruction rate (inst/s) 8host_op_rate 196203 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3671761280 # Simulator tick rate (ticks/s) 10host_mem_usage 648900 # Number of bytes of host memory used 11host_seconds 775.14 # Real time elapsed on the host 12sim_insts 125586921 # Number of instructions simulated 13sim_ops 152085297 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu0.dtb.walker 9344 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1671232 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1335292 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8458880 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 217280 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 606496 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 432576 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu0.dtb.walker 8320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1497984 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1248876 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8305216 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 2560 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 388800 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 684240 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 582144 # Number of bytes read from this memory |
| 25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 26system.physmem.bytes_read::total 12733532 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 1671232 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 217280 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 1888512 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 8840256 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory | 27system.physmem.bytes_read::total 12719228 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 1497984 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 388800 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 1886784 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 8861888 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory |
| 32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory | 33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory |
| 33system.physmem.bytes_written::total 8858000 # Number of bytes written to this memory 34system.physmem.num_reads::cpu0.dtb.walker 146 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 26113 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 21389 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.l2cache.prefetcher 132170 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.inst 3395 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.data 9500 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.l2cache.prefetcher 6759 # Number of read requests responded to by this memory | 34system.physmem.bytes_written::total 8879452 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 130 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 23406 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 20035 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 129769 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 40 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 6075 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 10711 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 9096 # Number of read requests responded to by this memory |
| 43system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 45system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 44system.physmem.num_reads::total 199510 # Number of read requests responded to by this memory 45system.physmem.num_writes::writebacks 138129 # Number of write requests responded to by this memory 46system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory | 46system.physmem.num_reads::total 199279 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 138467 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory |
| 47system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory | 49system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory |
| 48system.physmem.num_writes::total 142565 # Number of write requests responded to by this memory 49system.physmem.bw_read::cpu0.dtb.walker 3283 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.inst 587201 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.data 469166 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.l2cache.prefetcher 2972098 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.dtb.walker 472 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.inst 76343 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.data 213097 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.l2cache.prefetcher 151989 # Total read bandwidth from this memory (bytes/s) | 50system.physmem.num_writes::total 142858 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 2923 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 526320 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 438796 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 2918058 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 899 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 136606 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 240409 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 204538 # Total read bandwidth from this memory (bytes/s) |
| 58system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) | 61system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) |
| 59system.physmem.bw_read::total 4474032 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::cpu0.inst 587201 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu1.inst 76343 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::total 663544 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_write::writebacks 3106097 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_write::cpu0.data 6220 # Write bandwidth from this memory (bytes/s) | 62system.physmem.bw_read::total 4468932 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 526320 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 136606 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 662926 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 3113646 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 6157 # Write bandwidth from this memory (bytes/s) |
| 65system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) | 68system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) |
| 66system.physmem.bw_write::total 3112332 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_total::writebacks 3106097 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.dtb.walker 3283 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.inst 587201 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.data 475386 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.l2cache.prefetcher 2972098 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.dtb.walker 472 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.inst 76343 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.data 213111 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.l2cache.prefetcher 151989 # Total bandwidth to/from this memory (bytes/s) | 69system.physmem.bw_write::total 3119817 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 3113646 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 2923 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 526320 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 444953 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 2918058 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 899 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 136606 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 240423 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 204538 # Total bandwidth to/from this memory (bytes/s) |
| 77system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) | 81system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) |
| 78system.physmem.bw_total::total 7586364 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.readReqs 199510 # Number of read requests accepted 80system.physmem.writeReqs 178789 # Number of write requests accepted 81system.physmem.readBursts 199510 # Number of DRAM read bursts, including those serviced by the write queue 82system.physmem.writeBursts 178789 # Number of DRAM write bursts, including those merged in the write queue 83system.physmem.bytesReadDRAM 12761024 # Total number of bytes read from DRAM 84system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue 85system.physmem.bytesWritten 9911424 # Total number of bytes written to DRAM 86system.physmem.bytesReadSys 12733532 # Total read bytes from the system interface side 87system.physmem.bytesWrittenSys 11176336 # Total written bytes from the system interface side 88system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue 89system.physmem.mergedWrBursts 23895 # Number of DRAM write bursts merged with an existing one 90system.physmem.neitherReadNorWriteReqs 14191 # Number of requests that are neither read nor write 91system.physmem.perBankRdBursts::0 12377 # Per bank write bursts 92system.physmem.perBankRdBursts::1 12507 # Per bank write bursts 93system.physmem.perBankRdBursts::2 12921 # Per bank write bursts 94system.physmem.perBankRdBursts::3 12944 # Per bank write bursts 95system.physmem.perBankRdBursts::4 15059 # Per bank write bursts 96system.physmem.perBankRdBursts::5 12345 # Per bank write bursts 97system.physmem.perBankRdBursts::6 13163 # Per bank write bursts 98system.physmem.perBankRdBursts::7 13279 # Per bank write bursts 99system.physmem.perBankRdBursts::8 12255 # Per bank write bursts 100system.physmem.perBankRdBursts::9 12304 # Per bank write bursts 101system.physmem.perBankRdBursts::10 12058 # Per bank write bursts 102system.physmem.perBankRdBursts::11 11233 # Per bank write bursts 103system.physmem.perBankRdBursts::12 11543 # Per bank write bursts 104system.physmem.perBankRdBursts::13 12301 # Per bank write bursts 105system.physmem.perBankRdBursts::14 11677 # Per bank write bursts 106system.physmem.perBankRdBursts::15 11425 # Per bank write bursts 107system.physmem.perBankWrBursts::0 9896 # Per bank write bursts 108system.physmem.perBankWrBursts::1 10159 # Per bank write bursts 109system.physmem.perBankWrBursts::2 10174 # Per bank write bursts 110system.physmem.perBankWrBursts::3 9995 # Per bank write bursts 111system.physmem.perBankWrBursts::4 9156 # Per bank write bursts 112system.physmem.perBankWrBursts::5 9568 # Per bank write bursts 113system.physmem.perBankWrBursts::6 10283 # Per bank write bursts 114system.physmem.perBankWrBursts::7 10373 # Per bank write bursts 115system.physmem.perBankWrBursts::8 9590 # Per bank write bursts 116system.physmem.perBankWrBursts::9 9571 # Per bank write bursts 117system.physmem.perBankWrBursts::10 9719 # Per bank write bursts 118system.physmem.perBankWrBursts::11 9542 # Per bank write bursts 119system.physmem.perBankWrBursts::12 9254 # Per bank write bursts 120system.physmem.perBankWrBursts::13 9350 # Per bank write bursts 121system.physmem.perBankWrBursts::14 9412 # Per bank write bursts 122system.physmem.perBankWrBursts::15 8824 # Per bank write bursts | 82system.physmem.bw_total::total 7588749 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 199279 # Number of read requests accepted 84system.physmem.writeReqs 179082 # Number of write requests accepted 85system.physmem.readBursts 199279 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 179082 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 12747712 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue 89system.physmem.bytesWritten 9932032 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 12719228 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 11197788 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 23866 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 14978 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 12467 # Per bank write bursts 96system.physmem.perBankRdBursts::1 12549 # Per bank write bursts 97system.physmem.perBankRdBursts::2 12590 # Per bank write bursts 98system.physmem.perBankRdBursts::3 12626 # Per bank write bursts 99system.physmem.perBankRdBursts::4 14976 # Per bank write bursts 100system.physmem.perBankRdBursts::5 12125 # Per bank write bursts 101system.physmem.perBankRdBursts::6 13379 # Per bank write bursts 102system.physmem.perBankRdBursts::7 13505 # Per bank write bursts 103system.physmem.perBankRdBursts::8 12274 # Per bank write bursts 104system.physmem.perBankRdBursts::9 12440 # Per bank write bursts 105system.physmem.perBankRdBursts::10 11813 # Per bank write bursts 106system.physmem.perBankRdBursts::11 11246 # Per bank write bursts 107system.physmem.perBankRdBursts::12 11354 # Per bank write bursts 108system.physmem.perBankRdBursts::13 11924 # Per bank write bursts 109system.physmem.perBankRdBursts::14 11833 # Per bank write bursts 110system.physmem.perBankRdBursts::15 12082 # Per bank write bursts 111system.physmem.perBankWrBursts::0 9603 # Per bank write bursts 112system.physmem.perBankWrBursts::1 9871 # Per bank write bursts 113system.physmem.perBankWrBursts::2 10084 # Per bank write bursts 114system.physmem.perBankWrBursts::3 9904 # Per bank write bursts 115system.physmem.perBankWrBursts::4 9385 # Per bank write bursts 116system.physmem.perBankWrBursts::5 9666 # Per bank write bursts 117system.physmem.perBankWrBursts::6 10609 # Per bank write bursts 118system.physmem.perBankWrBursts::7 10482 # Per bank write bursts 119system.physmem.perBankWrBursts::8 9764 # Per bank write bursts 120system.physmem.perBankWrBursts::9 9386 # Per bank write bursts 121system.physmem.perBankWrBursts::10 9428 # Per bank write bursts 122system.physmem.perBankWrBursts::11 9248 # Per bank write bursts 123system.physmem.perBankWrBursts::12 9294 # Per bank write bursts 124system.physmem.perBankWrBursts::13 9689 # Per bank write bursts 125system.physmem.perBankWrBursts::14 9592 # Per bank write bursts 126system.physmem.perBankWrBursts::15 9183 # Per bank write bursts |
| 123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 124system.physmem.numWrRetry 38 # Number of times write queue was full causing retry 125system.physmem.totGap 2846096933500 # Total gap between requests | 128system.physmem.numWrRetry 107 # Number of times write queue was full causing retry 129system.physmem.totGap 2846144533500 # Total gap between requests |
| 126system.physmem.readPktSize::0 0 # Read request sizes (log2) 127system.physmem.readPktSize::1 0 # Read request sizes (log2) | 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) |
| 128system.physmem.readPktSize::2 559 # Read request sizes (log2) | 132system.physmem.readPktSize::2 551 # Read request sizes (log2) |
| 129system.physmem.readPktSize::3 28 # Read request sizes (log2) 130system.physmem.readPktSize::4 0 # Read request sizes (log2) 131system.physmem.readPktSize::5 0 # Read request sizes (log2) | 133system.physmem.readPktSize::3 28 # Read request sizes (log2) 134system.physmem.readPktSize::4 0 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 132system.physmem.readPktSize::6 198923 # Read request sizes (log2) | 136system.physmem.readPktSize::6 198700 # Read request sizes (log2) |
| 133system.physmem.writePktSize::0 0 # Write request sizes (log2) 134system.physmem.writePktSize::1 0 # Write request sizes (log2) | 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) |
| 135system.physmem.writePktSize::2 4436 # Write request sizes (log2) | 139system.physmem.writePktSize::2 4391 # Write request sizes (log2) |
| 136system.physmem.writePktSize::3 0 # Write request sizes (log2) 137system.physmem.writePktSize::4 0 # Write request sizes (log2) 138system.physmem.writePktSize::5 0 # Write request sizes (log2) | 140system.physmem.writePktSize::3 0 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 139system.physmem.writePktSize::6 174353 # Write request sizes (log2) 140system.physmem.rdQLenPdf::0 98295 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 47940 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 13231 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 9850 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 7837 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 6409 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 5336 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 4702 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 4182 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 765 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 268 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 250 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::12 168 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::13 153 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see | 143system.physmem.writePktSize::6 174691 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 98289 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 47643 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 13113 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 9874 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 7835 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 6424 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 5388 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 4763 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 4219 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 766 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 286 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 254 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 167 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 149 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see |
| 158system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see --- 13 unchanged lines hidden (view full) --- 179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 162system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see --- 13 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 187system.physmem.wrQLenPdf::15 2215 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::16 2534 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::17 3771 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::18 4787 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::19 5445 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::20 6062 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::21 6493 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::22 7082 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::23 8354 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::24 7379 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::25 7734 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::26 9231 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::27 8142 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::28 8296 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::29 10951 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::30 8932 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::31 8227 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::32 7988 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::33 1408 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::34 1340 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::35 1453 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::36 2379 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::37 2537 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::38 1912 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::39 1868 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::40 2527 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::41 1779 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::42 1855 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::43 1708 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::44 1845 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::45 1734 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::46 1253 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::47 1386 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::48 999 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::49 773 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::50 467 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::51 316 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::52 221 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::53 206 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::54 195 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::55 211 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::56 157 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::57 142 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::59 115 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::60 100 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::61 145 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see 236system.physmem.bytesPerActivate::samples 90716 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::mean 249.927069 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::gmean 140.222601 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::stdev 310.362875 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::0-127 47359 52.21% 52.21% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::128-255 17889 19.72% 71.93% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::256-383 6289 6.93% 78.86% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::384-511 3581 3.95% 82.81% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::512-639 2839 3.13% 85.94% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::640-767 1568 1.73% 87.66% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::768-895 985 1.09% 88.75% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::896-1023 1019 1.12% 89.87% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::1024-1151 9187 10.13% 100.00% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::total 90716 # Bytes accessed per row activation 250system.physmem.rdPerTurnAround::samples 6524 # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::mean 30.562538 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::stdev 556.578248 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::0-2047 6523 99.98% 99.98% # Reads before turning the bus around for writes | 191system.physmem.wrQLenPdf::15 2161 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 2432 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 3791 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 4634 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 5553 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 6050 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 6450 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 7017 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 8315 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 7470 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 7525 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 9574 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 8177 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 8060 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 10880 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 8816 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 8421 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 7952 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 1407 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 1294 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 1605 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 2476 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 2505 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 1864 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 1962 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 2412 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 1768 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 2040 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 1751 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 1743 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 1419 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 1360 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 1471 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 1077 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 718 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 381 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 295 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 270 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 290 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 127 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 186 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 191 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 150 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 132 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 193 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 95 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 127 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 78 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 536 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 91273 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 248.481807 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 139.408554 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 309.811796 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 47817 52.39% 52.39% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 18099 19.83% 72.22% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 6231 6.83% 79.05% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 3556 3.90% 82.94% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 2836 3.11% 86.05% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 1554 1.70% 87.75% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 946 1.04% 88.79% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 1020 1.12% 89.91% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 9214 10.09% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 91273 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 6574 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 30.298296 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 554.918828 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-2047 6572 99.97% 99.97% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes |
| 254system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes | 259system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 255system.physmem.rdPerTurnAround::total 6524 # Reads before turning the bus around for writes 256system.physmem.wrPerTurnAround::samples 6524 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::mean 23.737891 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::gmean 18.670801 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::stdev 40.283485 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::16-31 6175 94.65% 94.65% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::32-47 90 1.38% 96.03% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::48-63 23 0.35% 96.38% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::64-79 12 0.18% 96.57% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::80-95 26 0.40% 96.97% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::96-111 32 0.49% 97.46% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::112-127 26 0.40% 97.85% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::128-143 10 0.15% 98.01% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::144-159 20 0.31% 98.31% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::160-175 5 0.08% 98.39% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::176-191 20 0.31% 98.70% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::192-207 23 0.35% 99.05% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::208-223 7 0.11% 99.16% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::224-239 7 0.11% 99.26% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::240-255 1 0.02% 99.28% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::256-271 3 0.05% 99.33% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::272-287 2 0.03% 99.36% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::288-303 5 0.08% 99.43% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::304-319 4 0.06% 99.49% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::336-351 4 0.06% 99.56% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::352-367 14 0.21% 99.77% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::384-399 2 0.03% 99.80% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::400-415 1 0.02% 99.82% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::464-479 1 0.02% 99.83% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::496-511 2 0.03% 99.86% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::512-527 2 0.03% 99.89% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::528-543 3 0.05% 99.94% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::576-591 1 0.02% 99.95% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::720-735 1 0.02% 99.98% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::total 6524 # Writes before turning the bus around for reads 292system.physmem.totQLat 5679096455 # Total ticks spent queuing 293system.physmem.totMemAccLat 9417677705 # Total ticks spent from burst creation until serviced by the DRAM 294system.physmem.totBusLat 996955000 # Total ticks spent in databus transfers 295system.physmem.avgQLat 28482.21 # Average queueing delay per DRAM burst | 260system.physmem.rdPerTurnAround::total 6574 # Reads before turning the bus around for writes 261system.physmem.wrPerTurnAround::samples 6574 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::mean 23.606328 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::gmean 18.587470 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::stdev 41.316435 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::16-31 6233 94.81% 94.81% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::32-47 88 1.34% 96.15% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::48-63 20 0.30% 96.46% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::64-79 23 0.35% 96.81% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::80-95 27 0.41% 97.22% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::96-111 26 0.40% 97.61% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::112-127 23 0.35% 97.96% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::128-143 19 0.29% 98.25% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::144-159 11 0.17% 98.42% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::160-175 6 0.09% 98.51% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::176-191 17 0.26% 98.77% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::192-207 19 0.29% 99.06% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::208-223 5 0.08% 99.13% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::224-239 3 0.05% 99.18% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::240-255 2 0.03% 99.21% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::256-271 1 0.02% 99.22% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::272-287 2 0.03% 99.25% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::288-303 3 0.05% 99.30% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::304-319 5 0.08% 99.38% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::320-335 6 0.09% 99.47% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::336-351 6 0.09% 99.56% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::352-367 9 0.14% 99.70% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::368-383 2 0.03% 99.73% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::384-399 3 0.05% 99.77% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::400-415 2 0.03% 99.80% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::416-431 1 0.02% 99.82% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::496-511 3 0.05% 99.86% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::528-543 2 0.03% 99.89% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::544-559 1 0.02% 99.91% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::560-575 1 0.02% 99.92% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::640-655 1 0.02% 99.94% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::672-687 1 0.02% 99.95% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::688-703 2 0.03% 99.98% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::total 6574 # Writes before turning the bus around for reads 300system.physmem.totQLat 5766362365 # Total ticks spent queuing 301system.physmem.totMemAccLat 9501043615 # Total ticks spent from burst creation until serviced by the DRAM 302system.physmem.totBusLat 995915000 # Total ticks spent in databus transfers 303system.physmem.avgQLat 28950.07 # Average queueing delay per DRAM burst |
| 296system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 304system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 297system.physmem.avgMemAccLat 47232.21 # Average memory access latency per DRAM burst | 305system.physmem.avgMemAccLat 47700.07 # Average memory access latency per DRAM burst |
| 298system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s | 306system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s |
| 299system.physmem.avgWrBW 3.48 # Average achieved write bandwidth in MiByte/s | 307system.physmem.avgWrBW 3.49 # Average achieved write bandwidth in MiByte/s |
| 300system.physmem.avgRdBWSys 4.47 # Average system read bandwidth in MiByte/s 301system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s 302system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 303system.physmem.busUtil 0.06 # Data bus utilization in percentage | 308system.physmem.avgRdBWSys 4.47 # Average system read bandwidth in MiByte/s 309system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s 310system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 311system.physmem.busUtil 0.06 # Data bus utilization in percentage |
| 304system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads | 312system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads |
| 305system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 313system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| 306system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing 307system.physmem.avgWrQLen 24.18 # Average write queue length when enqueuing 308system.physmem.readRowHits 166067 # Number of row buffer hits during reads 309system.physmem.writeRowHits 97473 # Number of row buffer hits during writes 310system.physmem.readRowHitRate 83.29 # Row buffer hit rate for reads 311system.physmem.writeRowHitRate 62.93 # Row buffer hit rate for writes 312system.physmem.avgGap 7523405.91 # Average gap between requests 313system.physmem.pageHitRate 74.39 # Row buffer hit rate, read and write combined 314system.physmem_0.actEnergy 359115120 # Energy for activate commands per rank (pJ) 315system.physmem_0.preEnergy 195945750 # Energy for precharge commands per rank (pJ) 316system.physmem_0.readEnergy 815841000 # Energy for read commands per rank (pJ) | 314system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing 315system.physmem.avgWrQLen 25.19 # Average write queue length when enqueuing 316system.physmem.readRowHits 165729 # Number of row buffer hits during reads 317system.physmem.writeRowHits 97368 # Number of row buffer hits during writes 318system.physmem.readRowHitRate 83.20 # Row buffer hit rate for reads 319system.physmem.writeRowHitRate 62.73 # Row buffer hit rate for writes 320system.physmem.avgGap 7522298.90 # Average gap between requests 321system.physmem.pageHitRate 74.24 # Row buffer hit rate, read and write combined 322system.physmem_0.actEnergy 359432640 # Energy for activate commands per rank (pJ) 323system.physmem_0.preEnergy 196119000 # Energy for precharge commands per rank (pJ) 324system.physmem_0.readEnergy 812892600 # Energy for read commands per rank (pJ) |
| 317system.physmem_0.writeEnergy 515833920 # Energy for write commands per rank (pJ) | 325system.physmem_0.writeEnergy 515833920 # Energy for write commands per rank (pJ) |
| 318system.physmem_0.refreshEnergy 185892919680 # Energy for refresh commands per rank (pJ) 319system.physmem_0.actBackEnergy 83249453610 # Energy for active background per rank (pJ) 320system.physmem_0.preBackEnergy 1634629745250 # Energy for precharge background per rank (pJ) 321system.physmem_0.totalEnergy 1905658854330 # Total energy per rank (pJ) 322system.physmem_0.averagePower 669.570214 # Core power per rank (mW) 323system.physmem_0.memoryStateTime::IDLE 2719227401175 # Time in different power states 324system.physmem_0.memoryStateTime::REF 95037280000 # Time in different power states | 326system.physmem_0.refreshEnergy 185895971040 # Energy for refresh commands per rank (pJ) 327system.physmem_0.actBackEnergy 83250586485 # Energy for active background per rank (pJ) 328system.physmem_0.preBackEnergy 1634656782000 # Energy for precharge background per rank (pJ) 329system.physmem_0.totalEnergy 1905687617685 # Total energy per rank (pJ) 330system.physmem_0.averagePower 669.569329 # Core power per rank (mW) 331system.physmem_0.memoryStateTime::IDLE 2719272584266 # Time in different power states 332system.physmem_0.memoryStateTime::REF 95038840000 # Time in different power states |
| 325system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 333system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 326system.physmem_0.memoryStateTime::ACT 31827968825 # Time in different power states | 334system.physmem_0.memoryStateTime::ACT 31827943234 # Time in different power states |
| 327system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 335system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 328system.physmem_1.actEnergy 326697840 # Energy for activate commands per rank (pJ) 329system.physmem_1.preEnergy 178257750 # Energy for precharge commands per rank (pJ) 330system.physmem_1.readEnergy 739401000 # Energy for read commands per rank (pJ) 331system.physmem_1.writeEnergy 487697760 # Energy for write commands per rank (pJ) 332system.physmem_1.refreshEnergy 185892919680 # Energy for refresh commands per rank (pJ) 333system.physmem_1.actBackEnergy 82096607520 # Energy for active background per rank (pJ) 334system.physmem_1.preBackEnergy 1635641013750 # Energy for precharge background per rank (pJ) 335system.physmem_1.totalEnergy 1905362595300 # Total energy per rank (pJ) 336system.physmem_1.averagePower 669.466120 # Core power per rank (mW) 337system.physmem_1.memoryStateTime::IDLE 2720918284391 # Time in different power states 338system.physmem_1.memoryStateTime::REF 95037280000 # Time in different power states | 336system.physmem_1.actEnergy 330591240 # Energy for activate commands per rank (pJ) 337system.physmem_1.preEnergy 180382125 # Energy for precharge commands per rank (pJ) 338system.physmem_1.readEnergy 740727000 # Energy for read commands per rank (pJ) 339system.physmem_1.writeEnergy 489784320 # Energy for write commands per rank (pJ) 340system.physmem_1.refreshEnergy 185895971040 # Energy for refresh commands per rank (pJ) 341system.physmem_1.actBackEnergy 82231883055 # Energy for active background per rank (pJ) 342system.physmem_1.preBackEnergy 1635550381500 # Energy for precharge background per rank (pJ) 343system.physmem_1.totalEnergy 1905419720280 # Total energy per rank (pJ) 344system.physmem_1.averagePower 669.475203 # Core power per rank (mW) 345system.physmem_1.memoryStateTime::IDLE 2720770086744 # Time in different power states 346system.physmem_1.memoryStateTime::REF 95038840000 # Time in different power states |
| 339system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 347system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 340system.physmem_1.memoryStateTime::ACT 30141762609 # Time in different power states | 348system.physmem_1.memoryStateTime::ACT 30336000256 # Time in different power states |
| 341system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 342system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory 343system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory 344system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory 345system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory 346system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory 347system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory 348system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory --- 9 unchanged lines hidden (view full) --- 358system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) 359system.realview.nvmem.bw_total::total 427 # Total bandwidth to/from this memory (bytes/s) 360system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 361system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 362system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 363system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 364system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 365system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 349system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 350system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory 351system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory 352system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory 353system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory 354system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory 355system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory 356system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory --- 9 unchanged lines hidden (view full) --- 366system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) 367system.realview.nvmem.bw_total::total 427 # Total bandwidth to/from this memory (bytes/s) 368system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 369system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 370system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 371system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 372system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 373system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 366system.cpu0.branchPred.lookups 20630955 # Number of BP lookups 367system.cpu0.branchPred.condPredicted 13593557 # Number of conditional branches predicted 368system.cpu0.branchPred.condIncorrect 1040069 # Number of conditional branches incorrect 369system.cpu0.branchPred.BTBLookups 13124579 # Number of BTB lookups 370system.cpu0.branchPred.BTBHits 9315197 # Number of BTB hits | 374system.cpu0.branchPred.lookups 33812647 # Number of BP lookups 375system.cpu0.branchPred.condPredicted 16331756 # Number of conditional branches predicted 376system.cpu0.branchPred.condIncorrect 1585484 # Number of conditional branches incorrect 377system.cpu0.branchPred.BTBLookups 19439562 # Number of BTB lookups 378system.cpu0.branchPred.BTBHits 14041669 # Number of BTB hits |
| 371system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 379system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 372system.cpu0.branchPred.BTBHitPct 70.975206 # BTB Hit Percentage 373system.cpu0.branchPred.usedRAS 3367508 # Number of times the RAS was used to get a target. 374system.cpu0.branchPred.RASInCorrect 204886 # Number of incorrect RAS predictions. | 380system.cpu0.branchPred.BTBHitPct 72.232435 # BTB Hit Percentage 381system.cpu0.branchPred.usedRAS 10663467 # Number of times the RAS was used to get a target. 382system.cpu0.branchPred.RASInCorrect 792082 # Number of incorrect RAS predictions. |
| 375system.cpu_clk_domain.clock 500 # Clock period in ticks 376system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 377system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 378system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 379system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 380system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 381system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 382system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 397system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 398system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 399system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 400system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 401system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 402system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 403system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 404system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 383system.cpu_clk_domain.clock 500 # Clock period in ticks 384system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 405system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 406system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 407system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 408system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 409system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 410system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 411system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 412system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 405system.cpu0.dtb.walker.walks 69457 # Table walker walks requested 406system.cpu0.dtb.walker.walksShort 69457 # Table walker walks initiated with short descriptors 407system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46535 # Level at which table walker walks with short descriptors terminate 408system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22922 # Level at which table walker walks with short descriptors terminate 409system.cpu0.dtb.walker.walkWaitTime::samples 69457 # Table walker wait (enqueue to first request) latency 410system.cpu0.dtb.walker.walkWaitTime::0 69457 100.00% 100.00% # Table walker wait (enqueue to first request) latency 411system.cpu0.dtb.walker.walkWaitTime::total 69457 # Table walker wait (enqueue to first request) latency 412system.cpu0.dtb.walker.walkCompletionTime::samples 6849 # Table walker service (enqueue to completion) latency 413system.cpu0.dtb.walker.walkCompletionTime::mean 9469.922616 # Table walker service (enqueue to completion) latency 414system.cpu0.dtb.walker.walkCompletionTime::gmean 8283.824538 # Table walker service (enqueue to completion) latency 415system.cpu0.dtb.walker.walkCompletionTime::stdev 6457.338241 # Table walker service (enqueue to completion) latency 416system.cpu0.dtb.walker.walkCompletionTime::0-16383 6642 96.98% 96.98% # Table walker service (enqueue to completion) latency 417system.cpu0.dtb.walker.walkCompletionTime::16384-32767 191 2.79% 99.77% # Table walker service (enqueue to completion) latency 418system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.85% # Table walker service (enqueue to completion) latency 419system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.10% 99.96% # Table walker service (enqueue to completion) latency 420system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.97% # Table walker service (enqueue to completion) latency 421system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 422system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 423system.cpu0.dtb.walker.walkCompletionTime::total 6849 # Table walker service (enqueue to completion) latency | 413system.cpu0.dtb.walker.walks 65253 # Table walker walks requested 414system.cpu0.dtb.walker.walksShort 65253 # Table walker walks initiated with short descriptors 415system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 42795 # Level at which table walker walks with short descriptors terminate 416system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22458 # Level at which table walker walks with short descriptors terminate 417system.cpu0.dtb.walker.walkWaitTime::samples 65253 # Table walker wait (enqueue to first request) latency 418system.cpu0.dtb.walker.walkWaitTime::0 65253 100.00% 100.00% # Table walker wait (enqueue to first request) latency 419system.cpu0.dtb.walker.walkWaitTime::total 65253 # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkCompletionTime::samples 6648 # Table walker service (enqueue to completion) latency 421system.cpu0.dtb.walker.walkCompletionTime::mean 9627.369284 # Table walker service (enqueue to completion) latency 422system.cpu0.dtb.walker.walkCompletionTime::gmean 8488.785540 # Table walker service (enqueue to completion) latency 423system.cpu0.dtb.walker.walkCompletionTime::stdev 6159.752779 # Table walker service (enqueue to completion) latency 424system.cpu0.dtb.walker.walkCompletionTime::0-16383 6446 96.96% 96.96% # Table walker service (enqueue to completion) latency 425system.cpu0.dtb.walker.walkCompletionTime::16384-32767 188 2.83% 99.79% # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::32768-49151 4 0.06% 99.85% # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.11% 99.95% # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.98% # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::total 6648 # Table walker service (enqueue to completion) latency |
| 424system.cpu0.dtb.walker.walksPending::samples 328505000 # Table walker pending requests distribution 425system.cpu0.dtb.walker.walksPending::0 328505000 100.00% 100.00% # Table walker pending requests distribution 426system.cpu0.dtb.walker.walksPending::total 328505000 # Table walker pending requests distribution | 431system.cpu0.dtb.walker.walksPending::samples 328505000 # Table walker pending requests distribution 432system.cpu0.dtb.walker.walksPending::0 328505000 100.00% 100.00% # Table walker pending requests distribution 433system.cpu0.dtb.walker.walksPending::total 328505000 # Table walker pending requests distribution |
| 427system.cpu0.dtb.walker.walkPageSizes::4K 5259 76.78% 76.78% # Table walker page sizes translated 428system.cpu0.dtb.walker.walkPageSizes::1M 1590 23.22% 100.00% # Table walker page sizes translated 429system.cpu0.dtb.walker.walkPageSizes::total 6849 # Table walker page sizes translated 430system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 69457 # Table walker requests started/completed, data/inst | 434system.cpu0.dtb.walker.walkPageSizes::4K 5136 77.26% 77.26% # Table walker page sizes translated 435system.cpu0.dtb.walker.walkPageSizes::1M 1512 22.74% 100.00% # Table walker page sizes translated 436system.cpu0.dtb.walker.walkPageSizes::total 6648 # Table walker page sizes translated 437system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65253 # Table walker requests started/completed, data/inst |
| 431system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 438system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 432system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 69457 # Table walker requests started/completed, data/inst 433system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6849 # Table walker requests started/completed, data/inst | 439system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65253 # Table walker requests started/completed, data/inst 440system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6648 # Table walker requests started/completed, data/inst |
| 434system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 441system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 435system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6849 # Table walker requests started/completed, data/inst 436system.cpu0.dtb.walker.walkRequestOrigin::total 76306 # Table walker requests started/completed, data/inst | 442system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6648 # Table walker requests started/completed, data/inst 443system.cpu0.dtb.walker.walkRequestOrigin::total 71901 # Table walker requests started/completed, data/inst |
| 437system.cpu0.dtb.inst_hits 0 # ITB inst hits 438system.cpu0.dtb.inst_misses 0 # ITB inst misses | 444system.cpu0.dtb.inst_hits 0 # ITB inst hits 445system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 439system.cpu0.dtb.read_hits 17312533 # DTB read hits 440system.cpu0.dtb.read_misses 63301 # DTB read misses 441system.cpu0.dtb.write_hits 14536158 # DTB write hits 442system.cpu0.dtb.write_misses 6156 # DTB write misses | 446system.cpu0.dtb.read_hits 22995822 # DTB read hits 447system.cpu0.dtb.read_misses 59685 # DTB read misses 448system.cpu0.dtb.write_hits 17147924 # DTB write hits 449system.cpu0.dtb.write_misses 5568 # DTB write misses |
| 443system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 444system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 445system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 446system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 450system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 451system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 452system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 453system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 447system.cpu0.dtb.flush_entries 3522 # Number of entries that have been flushed from TLB 448system.cpu0.dtb.align_faults 1254 # Number of TLB faults due to alignment restrictions 449system.cpu0.dtb.prefetch_faults 1942 # Number of TLB faults due to prefetch | 454system.cpu0.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB 455system.cpu0.dtb.align_faults 1156 # Number of TLB faults due to alignment restrictions 456system.cpu0.dtb.prefetch_faults 1615 # Number of TLB faults due to prefetch |
| 450system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 457system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 451system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions 452system.cpu0.dtb.read_accesses 17375834 # DTB read accesses 453system.cpu0.dtb.write_accesses 14542314 # DTB write accesses | 458system.cpu0.dtb.perms_faults 564 # Number of TLB faults due to permissions restrictions 459system.cpu0.dtb.read_accesses 23055507 # DTB read accesses 460system.cpu0.dtb.write_accesses 17153492 # DTB write accesses |
| 454system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 461system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 455system.cpu0.dtb.hits 31848691 # DTB hits 456system.cpu0.dtb.misses 69457 # DTB misses 457system.cpu0.dtb.accesses 31918148 # DTB accesses | 462system.cpu0.dtb.hits 40143746 # DTB hits 463system.cpu0.dtb.misses 65253 # DTB misses 464system.cpu0.dtb.accesses 40208999 # DTB accesses |
| 458system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 459system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 460system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 461system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 462system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 463system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 464system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 465system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 479system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 480system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 481system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 482system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 483system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 484system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 485system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 486system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 465system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 466system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 467system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 468system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 469system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 470system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 471system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 472system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 486system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 487system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 488system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 489system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 490system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 491system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 492system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 493system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 487system.cpu0.itb.walker.walks 3833 # Table walker walks requested 488system.cpu0.itb.walker.walksShort 3833 # Table walker walks initiated with short descriptors 489system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate 490system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3526 # Level at which table walker walks with short descriptors terminate 491system.cpu0.itb.walker.walkWaitTime::samples 3833 # Table walker wait (enqueue to first request) latency 492system.cpu0.itb.walker.walkWaitTime::0 3833 100.00% 100.00% # Table walker wait (enqueue to first request) latency 493system.cpu0.itb.walker.walkWaitTime::total 3833 # Table walker wait (enqueue to first request) latency 494system.cpu0.itb.walker.walkCompletionTime::samples 2419 # Table walker service (enqueue to completion) latency 495system.cpu0.itb.walker.walkCompletionTime::mean 9485.117817 # Table walker service (enqueue to completion) latency 496system.cpu0.itb.walker.walkCompletionTime::gmean 8378.584027 # Table walker service (enqueue to completion) latency 497system.cpu0.itb.walker.walkCompletionTime::stdev 4911.792845 # Table walker service (enqueue to completion) latency 498system.cpu0.itb.walker.walkCompletionTime::0-8191 918 37.95% 37.95% # Table walker service (enqueue to completion) latency 499system.cpu0.itb.walker.walkCompletionTime::8192-16383 1466 60.60% 98.55% # Table walker service (enqueue to completion) latency 500system.cpu0.itb.walker.walkCompletionTime::16384-24575 5 0.21% 98.76% # Table walker service (enqueue to completion) latency 501system.cpu0.itb.walker.walkCompletionTime::24576-32767 29 1.20% 99.96% # Table walker service (enqueue to completion) latency | 494system.cpu0.itb.walker.walks 3866 # Table walker walks requested 495system.cpu0.itb.walker.walksShort 3866 # Table walker walks initiated with short descriptors 496system.cpu0.itb.walker.walksShortTerminationLevel::Level1 306 # Level at which table walker walks with short descriptors terminate 497system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3560 # Level at which table walker walks with short descriptors terminate 498system.cpu0.itb.walker.walkWaitTime::samples 3866 # Table walker wait (enqueue to first request) latency 499system.cpu0.itb.walker.walkWaitTime::0 3866 100.00% 100.00% # Table walker wait (enqueue to first request) latency 500system.cpu0.itb.walker.walkWaitTime::total 3866 # Table walker wait (enqueue to first request) latency 501system.cpu0.itb.walker.walkCompletionTime::samples 2421 # Table walker service (enqueue to completion) latency 502system.cpu0.itb.walker.walkCompletionTime::mean 9944.030566 # Table walker service (enqueue to completion) latency 503system.cpu0.itb.walker.walkCompletionTime::gmean 8839.286720 # Table walker service (enqueue to completion) latency 504system.cpu0.itb.walker.walkCompletionTime::stdev 5045.849413 # Table walker service (enqueue to completion) latency 505system.cpu0.itb.walker.walkCompletionTime::0-8191 802 33.13% 33.13% # Table walker service (enqueue to completion) latency 506system.cpu0.itb.walker.walkCompletionTime::8192-16383 1572 64.93% 98.06% # Table walker service (enqueue to completion) latency 507system.cpu0.itb.walker.walkCompletionTime::16384-24575 10 0.41% 98.47% # Table walker service (enqueue to completion) latency 508system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 99.92% # Table walker service (enqueue to completion) latency 509system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency |
| 502system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency | 510system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency |
| 503system.cpu0.itb.walker.walkCompletionTime::total 2419 # Table walker service (enqueue to completion) latency | 511system.cpu0.itb.walker.walkCompletionTime::total 2421 # Table walker service (enqueue to completion) latency |
| 504system.cpu0.itb.walker.walksPending::samples 328041000 # Table walker pending requests distribution 505system.cpu0.itb.walker.walksPending::0 328041000 100.00% 100.00% # Table walker pending requests distribution 506system.cpu0.itb.walker.walksPending::total 328041000 # Table walker pending requests distribution | 512system.cpu0.itb.walker.walksPending::samples 328041000 # Table walker pending requests distribution 513system.cpu0.itb.walker.walksPending::0 328041000 100.00% 100.00% # Table walker pending requests distribution 514system.cpu0.itb.walker.walksPending::total 328041000 # Table walker pending requests distribution |
| 507system.cpu0.itb.walker.walkPageSizes::4K 2119 87.60% 87.60% # Table walker page sizes translated 508system.cpu0.itb.walker.walkPageSizes::1M 300 12.40% 100.00% # Table walker page sizes translated 509system.cpu0.itb.walker.walkPageSizes::total 2419 # Table walker page sizes translated | 515system.cpu0.itb.walker.walkPageSizes::4K 2122 87.65% 87.65% # Table walker page sizes translated 516system.cpu0.itb.walker.walkPageSizes::1M 299 12.35% 100.00% # Table walker page sizes translated 517system.cpu0.itb.walker.walkPageSizes::total 2421 # Table walker page sizes translated |
| 510system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 518system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 511system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3833 # Table walker requests started/completed, data/inst 512system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3833 # Table walker requests started/completed, data/inst | 519system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3866 # Table walker requests started/completed, data/inst 520system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3866 # Table walker requests started/completed, data/inst |
| 513system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 521system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 514system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2419 # Table walker requests started/completed, data/inst 515system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2419 # Table walker requests started/completed, data/inst 516system.cpu0.itb.walker.walkRequestOrigin::total 6252 # Table walker requests started/completed, data/inst 517system.cpu0.itb.inst_hits 38694088 # ITB inst hits 518system.cpu0.itb.inst_misses 3833 # ITB inst misses | 522system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2421 # Table walker requests started/completed, data/inst 523system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2421 # Table walker requests started/completed, data/inst 524system.cpu0.itb.walker.walkRequestOrigin::total 6287 # Table walker requests started/completed, data/inst 525system.cpu0.itb.inst_hits 68390761 # ITB inst hits 526system.cpu0.itb.inst_misses 3866 # ITB inst misses |
| 519system.cpu0.itb.read_hits 0 # DTB read hits 520system.cpu0.itb.read_misses 0 # DTB read misses 521system.cpu0.itb.write_hits 0 # DTB write hits 522system.cpu0.itb.write_misses 0 # DTB write misses 523system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 524system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 525system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 526system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 527system.cpu0.itb.read_hits 0 # DTB read hits 528system.cpu0.itb.read_misses 0 # DTB read misses 529system.cpu0.itb.write_hits 0 # DTB write hits 530system.cpu0.itb.write_misses 0 # DTB write misses 531system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 532system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 533system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 534system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 527system.cpu0.itb.flush_entries 2222 # Number of entries that have been flushed from TLB | 535system.cpu0.itb.flush_entries 2224 # Number of entries that have been flushed from TLB |
| 528system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 529system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 530system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 536system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 537system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 538system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 531system.cpu0.itb.perms_faults 7309 # Number of TLB faults due to permissions restrictions | 539system.cpu0.itb.perms_faults 7604 # Number of TLB faults due to permissions restrictions |
| 532system.cpu0.itb.read_accesses 0 # DTB read accesses 533system.cpu0.itb.write_accesses 0 # DTB write accesses | 540system.cpu0.itb.read_accesses 0 # DTB read accesses 541system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 534system.cpu0.itb.inst_accesses 38697921 # ITB inst accesses 535system.cpu0.itb.hits 38694088 # DTB hits 536system.cpu0.itb.misses 3833 # DTB misses 537system.cpu0.itb.accesses 38697921 # DTB accesses 538system.cpu0.numCycles 164664294 # number of cpu cycles simulated | 542system.cpu0.itb.inst_accesses 68394627 # ITB inst accesses 543system.cpu0.itb.hits 68390761 # DTB hits 544system.cpu0.itb.misses 3866 # DTB misses 545system.cpu0.itb.accesses 68394627 # DTB accesses 546system.cpu0.numCycles 225488562 # number of cpu cycles simulated |
| 539system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 540system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 547system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 548system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 541system.cpu0.committedInsts 79545676 # Number of instructions committed 542system.cpu0.committedOps 95726645 # Number of ops (including micro ops) committed 543system.cpu0.discardedOps 5037895 # Number of ops (including micro ops) which were discarded before commit 544system.cpu0.numFetchSuspends 1845 # Number of times Execute suspended instruction fetching 545system.cpu0.quiesceCycles 5527555817 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 546system.cpu0.cpi 2.070060 # CPI: cycles per instruction 547system.cpu0.ipc 0.483078 # IPC: instructions per cycle | 549system.cpu0.committedInsts 104715622 # Number of instructions committed 550system.cpu0.committedOps 126599996 # Number of ops (including micro ops) committed 551system.cpu0.discardedOps 8092675 # Number of ops (including micro ops) which were discarded before commit 552system.cpu0.numFetchSuspends 2098 # Number of times Execute suspended instruction fetching 553system.cpu0.quiesceCycles 5466839701 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 554system.cpu0.cpi 2.153342 # CPI: cycles per instruction 555system.cpu0.ipc 0.464394 # IPC: instructions per cycle |
| 548system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 556system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 549system.cpu0.kern.inst.quiesce 1847 # number of quiesce instructions executed 550system.cpu0.tickCycles 127989646 # Number of cycles that the object actually ticked 551system.cpu0.idleCycles 36674648 # Total number of cycles that the object has spent stopped 552system.cpu0.dcache.tags.replacements 713904 # number of replacements 553system.cpu0.dcache.tags.tagsinuse 500.482804 # Cycle average of tags in use 554system.cpu0.dcache.tags.total_refs 30358451 # Total number of references to valid blocks. 555system.cpu0.dcache.tags.sampled_refs 714416 # Sample count of references to valid blocks. 556system.cpu0.dcache.tags.avg_refs 42.494080 # Average number of references to valid blocks. 557system.cpu0.dcache.tags.warmup_cycle 348749500 # Cycle when the warmup percentage was hit. 558system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.482804 # Average occupied blocks per requestor 559system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977505 # Average percentage of cache occupancy 560system.cpu0.dcache.tags.occ_percent::total 0.977505 # Average percentage of cache occupancy | 557system.cpu0.kern.inst.quiesce 2103 # number of quiesce instructions executed 558system.cpu0.tickCycles 187544415 # Number of cycles that the object actually ticked 559system.cpu0.idleCycles 37944147 # Total number of cycles that the object has spent stopped 560system.cpu0.dcache.tags.replacements 678004 # number of replacements 561system.cpu0.dcache.tags.tagsinuse 485.290770 # Cycle average of tags in use 562system.cpu0.dcache.tags.total_refs 38699274 # Total number of references to valid blocks. 563system.cpu0.dcache.tags.sampled_refs 678516 # Sample count of references to valid blocks. 564system.cpu0.dcache.tags.avg_refs 57.035168 # Average number of references to valid blocks. 565system.cpu0.dcache.tags.warmup_cycle 346166500 # Cycle when the warmup percentage was hit. 566system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.290770 # Average occupied blocks per requestor 567system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947834 # Average percentage of cache occupancy 568system.cpu0.dcache.tags.occ_percent::total 0.947834 # Average percentage of cache occupancy |
| 561system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 569system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 562system.cpu0.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id 563system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 564system.cpu0.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id | 570system.cpu0.dcache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id 571system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id 572system.cpu0.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id |
| 565system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 573system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 566system.cpu0.dcache.tags.tag_accesses 63703980 # Number of tag accesses 567system.cpu0.dcache.tags.data_accesses 63703980 # Number of data accesses 568system.cpu0.dcache.ReadReq_hits::cpu0.data 15781686 # number of ReadReq hits 569system.cpu0.dcache.ReadReq_hits::total 15781686 # number of ReadReq hits 570system.cpu0.dcache.WriteReq_hits::cpu0.data 13418199 # number of WriteReq hits 571system.cpu0.dcache.WriteReq_hits::total 13418199 # number of WriteReq hits 572system.cpu0.dcache.SoftPFReq_hits::cpu0.data 321521 # number of SoftPFReq hits 573system.cpu0.dcache.SoftPFReq_hits::total 321521 # number of SoftPFReq hits 574system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365596 # number of LoadLockedReq hits 575system.cpu0.dcache.LoadLockedReq_hits::total 365596 # number of LoadLockedReq hits 576system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361488 # number of StoreCondReq hits 577system.cpu0.dcache.StoreCondReq_hits::total 361488 # number of StoreCondReq hits 578system.cpu0.dcache.demand_hits::cpu0.data 29199885 # number of demand (read+write) hits 579system.cpu0.dcache.demand_hits::total 29199885 # number of demand (read+write) hits 580system.cpu0.dcache.overall_hits::cpu0.data 29521406 # number of overall hits 581system.cpu0.dcache.overall_hits::total 29521406 # number of overall hits 582system.cpu0.dcache.ReadReq_misses::cpu0.data 463568 # number of ReadReq misses 583system.cpu0.dcache.ReadReq_misses::total 463568 # number of ReadReq misses 584system.cpu0.dcache.WriteReq_misses::cpu0.data 577310 # number of WriteReq misses 585system.cpu0.dcache.WriteReq_misses::total 577310 # number of WriteReq misses 586system.cpu0.dcache.SoftPFReq_misses::cpu0.data 136519 # number of SoftPFReq misses 587system.cpu0.dcache.SoftPFReq_misses::total 136519 # number of SoftPFReq misses 588system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21073 # number of LoadLockedReq misses 589system.cpu0.dcache.LoadLockedReq_misses::total 21073 # number of LoadLockedReq misses 590system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20283 # number of StoreCondReq misses 591system.cpu0.dcache.StoreCondReq_misses::total 20283 # number of StoreCondReq misses 592system.cpu0.dcache.demand_misses::cpu0.data 1040878 # number of demand (read+write) misses 593system.cpu0.dcache.demand_misses::total 1040878 # number of demand (read+write) misses 594system.cpu0.dcache.overall_misses::cpu0.data 1177397 # number of overall misses 595system.cpu0.dcache.overall_misses::total 1177397 # number of overall misses 596system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6134841542 # number of ReadReq miss cycles 597system.cpu0.dcache.ReadReq_miss_latency::total 6134841542 # number of ReadReq miss cycles 598system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9140419725 # number of WriteReq miss cycles 599system.cpu0.dcache.WriteReq_miss_latency::total 9140419725 # number of WriteReq miss cycles 600system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 317623227 # number of LoadLockedReq miss cycles 601system.cpu0.dcache.LoadLockedReq_miss_latency::total 317623227 # number of LoadLockedReq miss cycles 602system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 453858268 # number of StoreCondReq miss cycles 603system.cpu0.dcache.StoreCondReq_miss_latency::total 453858268 # number of StoreCondReq miss cycles 604system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 454500 # number of StoreCondFailReq miss cycles 605system.cpu0.dcache.StoreCondFailReq_miss_latency::total 454500 # number of StoreCondFailReq miss cycles 606system.cpu0.dcache.demand_miss_latency::cpu0.data 15275261267 # number of demand (read+write) miss cycles 607system.cpu0.dcache.demand_miss_latency::total 15275261267 # number of demand (read+write) miss cycles 608system.cpu0.dcache.overall_miss_latency::cpu0.data 15275261267 # number of overall miss cycles 609system.cpu0.dcache.overall_miss_latency::total 15275261267 # number of overall miss cycles 610system.cpu0.dcache.ReadReq_accesses::cpu0.data 16245254 # number of ReadReq accesses(hits+misses) 611system.cpu0.dcache.ReadReq_accesses::total 16245254 # number of ReadReq accesses(hits+misses) 612system.cpu0.dcache.WriteReq_accesses::cpu0.data 13995509 # number of WriteReq accesses(hits+misses) 613system.cpu0.dcache.WriteReq_accesses::total 13995509 # number of WriteReq accesses(hits+misses) 614system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 458040 # number of SoftPFReq accesses(hits+misses) 615system.cpu0.dcache.SoftPFReq_accesses::total 458040 # number of SoftPFReq accesses(hits+misses) 616system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386669 # number of LoadLockedReq accesses(hits+misses) 617system.cpu0.dcache.LoadLockedReq_accesses::total 386669 # number of LoadLockedReq accesses(hits+misses) 618system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381771 # number of StoreCondReq accesses(hits+misses) 619system.cpu0.dcache.StoreCondReq_accesses::total 381771 # number of StoreCondReq accesses(hits+misses) 620system.cpu0.dcache.demand_accesses::cpu0.data 30240763 # number of demand (read+write) accesses 621system.cpu0.dcache.demand_accesses::total 30240763 # number of demand (read+write) accesses 622system.cpu0.dcache.overall_accesses::cpu0.data 30698803 # number of overall (read+write) accesses 623system.cpu0.dcache.overall_accesses::total 30698803 # number of overall (read+write) accesses 624system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028536 # miss rate for ReadReq accesses 625system.cpu0.dcache.ReadReq_miss_rate::total 0.028536 # miss rate for ReadReq accesses 626system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041250 # miss rate for WriteReq accesses 627system.cpu0.dcache.WriteReq_miss_rate::total 0.041250 # miss rate for WriteReq accesses 628system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.298050 # miss rate for SoftPFReq accesses 629system.cpu0.dcache.SoftPFReq_miss_rate::total 0.298050 # miss rate for SoftPFReq accesses 630system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054499 # miss rate for LoadLockedReq accesses 631system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054499 # miss rate for LoadLockedReq accesses 632system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053129 # miss rate for StoreCondReq accesses 633system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053129 # miss rate for StoreCondReq accesses 634system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034420 # miss rate for demand accesses 635system.cpu0.dcache.demand_miss_rate::total 0.034420 # miss rate for demand accesses 636system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038353 # miss rate for overall accesses 637system.cpu0.dcache.overall_miss_rate::total 0.038353 # miss rate for overall accesses 638system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13233.962530 # average ReadReq miss latency 639system.cpu0.dcache.ReadReq_avg_miss_latency::total 13233.962530 # average ReadReq miss latency 640system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15832.775675 # average WriteReq miss latency 641system.cpu0.dcache.WriteReq_avg_miss_latency::total 15832.775675 # average WriteReq miss latency 642system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15072.520619 # average LoadLockedReq miss latency 643system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15072.520619 # average LoadLockedReq miss latency 644system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22376.288912 # average StoreCondReq miss latency 645system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22376.288912 # average StoreCondReq miss latency | 574system.cpu0.dcache.tags.tag_accesses 80249956 # Number of tag accesses 575system.cpu0.dcache.tags.data_accesses 80249956 # Number of data accesses 576system.cpu0.dcache.ReadReq_hits::cpu0.data 21509384 # number of ReadReq hits 577system.cpu0.dcache.ReadReq_hits::total 21509384 # number of ReadReq hits 578system.cpu0.dcache.WriteReq_hits::cpu0.data 16060534 # number of WriteReq hits 579system.cpu0.dcache.WriteReq_hits::total 16060534 # number of WriteReq hits 580system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307394 # number of SoftPFReq hits 581system.cpu0.dcache.SoftPFReq_hits::total 307394 # number of SoftPFReq hits 582system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 357644 # number of LoadLockedReq hits 583system.cpu0.dcache.LoadLockedReq_hits::total 357644 # number of LoadLockedReq hits 584system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352742 # number of StoreCondReq hits 585system.cpu0.dcache.StoreCondReq_hits::total 352742 # number of StoreCondReq hits 586system.cpu0.dcache.demand_hits::cpu0.data 37569918 # number of demand (read+write) hits 587system.cpu0.dcache.demand_hits::total 37569918 # number of demand (read+write) hits 588system.cpu0.dcache.overall_hits::cpu0.data 37877312 # number of overall hits 589system.cpu0.dcache.overall_hits::total 37877312 # number of overall hits 590system.cpu0.dcache.ReadReq_misses::cpu0.data 441440 # number of ReadReq misses 591system.cpu0.dcache.ReadReq_misses::total 441440 # number of ReadReq misses 592system.cpu0.dcache.WriteReq_misses::cpu0.data 555221 # number of WriteReq misses 593system.cpu0.dcache.WriteReq_misses::total 555221 # number of WriteReq misses 594system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131923 # number of SoftPFReq misses 595system.cpu0.dcache.SoftPFReq_misses::total 131923 # number of SoftPFReq misses 596system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20844 # number of LoadLockedReq misses 597system.cpu0.dcache.LoadLockedReq_misses::total 20844 # number of LoadLockedReq misses 598system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21317 # number of StoreCondReq misses 599system.cpu0.dcache.StoreCondReq_misses::total 21317 # number of StoreCondReq misses 600system.cpu0.dcache.demand_misses::cpu0.data 996661 # number of demand (read+write) misses 601system.cpu0.dcache.demand_misses::total 996661 # number of demand (read+write) misses 602system.cpu0.dcache.overall_misses::cpu0.data 1128584 # number of overall misses 603system.cpu0.dcache.overall_misses::total 1128584 # number of overall misses 604system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5848521453 # number of ReadReq miss cycles 605system.cpu0.dcache.ReadReq_miss_latency::total 5848521453 # number of ReadReq miss cycles 606system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8885926805 # number of WriteReq miss cycles 607system.cpu0.dcache.WriteReq_miss_latency::total 8885926805 # number of WriteReq miss cycles 608system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 320729731 # number of LoadLockedReq miss cycles 609system.cpu0.dcache.LoadLockedReq_miss_latency::total 320729731 # number of LoadLockedReq miss cycles 610system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 481626159 # number of StoreCondReq miss cycles 611system.cpu0.dcache.StoreCondReq_miss_latency::total 481626159 # number of StoreCondReq miss cycles 612system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 602000 # number of StoreCondFailReq miss cycles 613system.cpu0.dcache.StoreCondFailReq_miss_latency::total 602000 # number of StoreCondFailReq miss cycles 614system.cpu0.dcache.demand_miss_latency::cpu0.data 14734448258 # number of demand (read+write) miss cycles 615system.cpu0.dcache.demand_miss_latency::total 14734448258 # number of demand (read+write) miss cycles 616system.cpu0.dcache.overall_miss_latency::cpu0.data 14734448258 # number of overall miss cycles 617system.cpu0.dcache.overall_miss_latency::total 14734448258 # number of overall miss cycles 618system.cpu0.dcache.ReadReq_accesses::cpu0.data 21950824 # number of ReadReq accesses(hits+misses) 619system.cpu0.dcache.ReadReq_accesses::total 21950824 # number of ReadReq accesses(hits+misses) 620system.cpu0.dcache.WriteReq_accesses::cpu0.data 16615755 # number of WriteReq accesses(hits+misses) 621system.cpu0.dcache.WriteReq_accesses::total 16615755 # number of WriteReq accesses(hits+misses) 622system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 439317 # number of SoftPFReq accesses(hits+misses) 623system.cpu0.dcache.SoftPFReq_accesses::total 439317 # number of SoftPFReq accesses(hits+misses) 624system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378488 # number of LoadLockedReq accesses(hits+misses) 625system.cpu0.dcache.LoadLockedReq_accesses::total 378488 # number of LoadLockedReq accesses(hits+misses) 626system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 374059 # number of StoreCondReq accesses(hits+misses) 627system.cpu0.dcache.StoreCondReq_accesses::total 374059 # number of StoreCondReq accesses(hits+misses) 628system.cpu0.dcache.demand_accesses::cpu0.data 38566579 # number of demand (read+write) accesses 629system.cpu0.dcache.demand_accesses::total 38566579 # number of demand (read+write) accesses 630system.cpu0.dcache.overall_accesses::cpu0.data 39005896 # number of overall (read+write) accesses 631system.cpu0.dcache.overall_accesses::total 39005896 # number of overall (read+write) accesses 632system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.020110 # miss rate for ReadReq accesses 633system.cpu0.dcache.ReadReq_miss_rate::total 0.020110 # miss rate for ReadReq accesses 634system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033415 # miss rate for WriteReq accesses 635system.cpu0.dcache.WriteReq_miss_rate::total 0.033415 # miss rate for WriteReq accesses 636system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300291 # miss rate for SoftPFReq accesses 637system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300291 # miss rate for SoftPFReq accesses 638system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055072 # miss rate for LoadLockedReq accesses 639system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055072 # miss rate for LoadLockedReq accesses 640system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056988 # miss rate for StoreCondReq accesses 641system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056988 # miss rate for StoreCondReq accesses 642system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025843 # miss rate for demand accesses 643system.cpu0.dcache.demand_miss_rate::total 0.025843 # miss rate for demand accesses 644system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028934 # miss rate for overall accesses 645system.cpu0.dcache.overall_miss_rate::total 0.028934 # miss rate for overall accesses 646system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13248.734716 # average ReadReq miss latency 647system.cpu0.dcache.ReadReq_avg_miss_latency::total 13248.734716 # average ReadReq miss latency 648system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16004.306042 # average WriteReq miss latency 649system.cpu0.dcache.WriteReq_avg_miss_latency::total 16004.306042 # average WriteReq miss latency 650system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15387.148868 # average LoadLockedReq miss latency 651system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15387.148868 # average LoadLockedReq miss latency 652system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22593.524370 # average StoreCondReq miss latency 653system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22593.524370 # average StoreCondReq miss latency |
| 646system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 647system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 654system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 655system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 648system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14675.361826 # average overall miss latency 649system.cpu0.dcache.demand_avg_miss_latency::total 14675.361826 # average overall miss latency 650system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12973.755893 # average overall miss latency 651system.cpu0.dcache.overall_avg_miss_latency::total 12973.755893 # average overall miss latency | 656system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14783.811404 # average overall miss latency 657system.cpu0.dcache.demand_avg_miss_latency::total 14783.811404 # average overall miss latency 658system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13055.694798 # average overall miss latency 659system.cpu0.dcache.overall_avg_miss_latency::total 13055.694798 # average overall miss latency |
| 652system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 653system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 654system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 655system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 656system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 657system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 658system.cpu0.dcache.fast_writes 0 # number of fast writes performed 659system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 660system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 661system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 662system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 663system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 664system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 665system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 666system.cpu0.dcache.fast_writes 0 # number of fast writes performed 667system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 660system.cpu0.dcache.writebacks::writebacks 513522 # number of writebacks 661system.cpu0.dcache.writebacks::total 513522 # number of writebacks 662system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 72271 # number of ReadReq MSHR hits 663system.cpu0.dcache.ReadReq_mshr_hits::total 72271 # number of ReadReq MSHR hits 664system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 253439 # number of WriteReq MSHR hits 665system.cpu0.dcache.WriteReq_mshr_hits::total 253439 # number of WriteReq MSHR hits 666system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14656 # number of LoadLockedReq MSHR hits 667system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14656 # number of LoadLockedReq MSHR hits 668system.cpu0.dcache.demand_mshr_hits::cpu0.data 325710 # number of demand (read+write) MSHR hits 669system.cpu0.dcache.demand_mshr_hits::total 325710 # number of demand (read+write) MSHR hits 670system.cpu0.dcache.overall_mshr_hits::cpu0.data 325710 # number of overall MSHR hits 671system.cpu0.dcache.overall_mshr_hits::total 325710 # number of overall MSHR hits 672system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 391297 # number of ReadReq MSHR misses 673system.cpu0.dcache.ReadReq_mshr_misses::total 391297 # number of ReadReq MSHR misses 674system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323871 # number of WriteReq MSHR misses 675system.cpu0.dcache.WriteReq_mshr_misses::total 323871 # number of WriteReq MSHR misses 676system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 103394 # number of SoftPFReq MSHR misses 677system.cpu0.dcache.SoftPFReq_mshr_misses::total 103394 # number of SoftPFReq MSHR misses 678system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6417 # number of LoadLockedReq MSHR misses 679system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6417 # number of LoadLockedReq MSHR misses 680system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20283 # number of StoreCondReq MSHR misses 681system.cpu0.dcache.StoreCondReq_mshr_misses::total 20283 # number of StoreCondReq MSHR misses 682system.cpu0.dcache.demand_mshr_misses::cpu0.data 715168 # number of demand (read+write) MSHR misses 683system.cpu0.dcache.demand_mshr_misses::total 715168 # number of demand (read+write) MSHR misses 684system.cpu0.dcache.overall_mshr_misses::cpu0.data 818562 # number of overall MSHR misses 685system.cpu0.dcache.overall_mshr_misses::total 818562 # number of overall MSHR misses 686system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4428376943 # number of ReadReq MSHR miss cycles 687system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4428376943 # number of ReadReq MSHR miss cycles 688system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4906976685 # number of WriteReq MSHR miss cycles 689system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4906976685 # number of WriteReq MSHR miss cycles 690system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1616801678 # number of SoftPFReq MSHR miss cycles 691system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1616801678 # number of SoftPFReq MSHR miss cycles 692system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 95832009 # number of LoadLockedReq MSHR miss cycles 693system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95832009 # number of LoadLockedReq MSHR miss cycles 694system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 422721232 # number of StoreCondReq MSHR miss cycles 695system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 422721232 # number of StoreCondReq MSHR miss cycles 696system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 436500 # number of StoreCondFailReq MSHR miss cycles 697system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 436500 # number of StoreCondFailReq MSHR miss cycles 698system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9335353628 # number of demand (read+write) MSHR miss cycles 699system.cpu0.dcache.demand_mshr_miss_latency::total 9335353628 # number of demand (read+write) MSHR miss cycles 700system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10952155306 # number of overall MSHR miss cycles 701system.cpu0.dcache.overall_mshr_miss_latency::total 10952155306 # number of overall MSHR miss cycles 702system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4276481750 # number of ReadReq MSHR uncacheable cycles 703system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4276481750 # number of ReadReq MSHR uncacheable cycles 704system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3261665000 # number of WriteReq MSHR uncacheable cycles 705system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3261665000 # number of WriteReq MSHR uncacheable cycles 706system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7538146750 # number of overall MSHR uncacheable cycles 707system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7538146750 # number of overall MSHR uncacheable cycles 708system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024087 # mshr miss rate for ReadReq accesses 709system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024087 # mshr miss rate for ReadReq accesses 710system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023141 # mshr miss rate for WriteReq accesses 711system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023141 # mshr miss rate for WriteReq accesses 712system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225731 # mshr miss rate for SoftPFReq accesses 713system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225731 # mshr miss rate for SoftPFReq accesses 714system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016596 # mshr miss rate for LoadLockedReq accesses 715system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016596 # mshr miss rate for LoadLockedReq accesses 716system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053129 # mshr miss rate for StoreCondReq accesses 717system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053129 # mshr miss rate for StoreCondReq accesses 718system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023649 # mshr miss rate for demand accesses 719system.cpu0.dcache.demand_mshr_miss_rate::total 0.023649 # mshr miss rate for demand accesses 720system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026664 # mshr miss rate for overall accesses 721system.cpu0.dcache.overall_mshr_miss_rate::total 0.026664 # mshr miss rate for overall accesses 722system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11317.175810 # average ReadReq mshr miss latency 723system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11317.175810 # average ReadReq mshr miss latency 724system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15151.022120 # average WriteReq mshr miss latency 725system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15151.022120 # average WriteReq mshr miss latency 726system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15637.287251 # average SoftPFReq mshr miss latency 727system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15637.287251 # average SoftPFReq mshr miss latency 728system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14934.082749 # average LoadLockedReq mshr miss latency 729system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14934.082749 # average LoadLockedReq mshr miss latency 730system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20841.159197 # average StoreCondReq mshr miss latency 731system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20841.159197 # average StoreCondReq mshr miss latency | 668system.cpu0.dcache.writebacks::writebacks 490183 # number of writebacks 669system.cpu0.dcache.writebacks::total 490183 # number of writebacks 670system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 69583 # number of ReadReq MSHR hits 671system.cpu0.dcache.ReadReq_mshr_hits::total 69583 # number of ReadReq MSHR hits 672system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 243174 # number of WriteReq MSHR hits 673system.cpu0.dcache.WriteReq_mshr_hits::total 243174 # number of WriteReq MSHR hits 674system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14803 # number of LoadLockedReq MSHR hits 675system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14803 # number of LoadLockedReq MSHR hits 676system.cpu0.dcache.demand_mshr_hits::cpu0.data 312757 # number of demand (read+write) MSHR hits 677system.cpu0.dcache.demand_mshr_hits::total 312757 # number of demand (read+write) MSHR hits 678system.cpu0.dcache.overall_mshr_hits::cpu0.data 312757 # number of overall MSHR hits 679system.cpu0.dcache.overall_mshr_hits::total 312757 # number of overall MSHR hits 680system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 371857 # number of ReadReq MSHR misses 681system.cpu0.dcache.ReadReq_mshr_misses::total 371857 # number of ReadReq MSHR misses 682system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312047 # number of WriteReq MSHR misses 683system.cpu0.dcache.WriteReq_mshr_misses::total 312047 # number of WriteReq MSHR misses 684system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99536 # number of SoftPFReq MSHR misses 685system.cpu0.dcache.SoftPFReq_mshr_misses::total 99536 # number of SoftPFReq MSHR misses 686system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6041 # number of LoadLockedReq MSHR misses 687system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6041 # number of LoadLockedReq MSHR misses 688system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21317 # number of StoreCondReq MSHR misses 689system.cpu0.dcache.StoreCondReq_mshr_misses::total 21317 # number of StoreCondReq MSHR misses 690system.cpu0.dcache.demand_mshr_misses::cpu0.data 683904 # number of demand (read+write) MSHR misses 691system.cpu0.dcache.demand_mshr_misses::total 683904 # number of demand (read+write) MSHR misses 692system.cpu0.dcache.overall_mshr_misses::cpu0.data 783440 # number of overall MSHR misses 693system.cpu0.dcache.overall_mshr_misses::total 783440 # number of overall MSHR misses 694system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29433 # number of ReadReq MSHR uncacheable 695system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29433 # number of ReadReq MSHR uncacheable 696system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26165 # number of WriteReq MSHR uncacheable 697system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26165 # number of WriteReq MSHR uncacheable 698system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 55598 # number of overall MSHR uncacheable misses 699system.cpu0.dcache.overall_mshr_uncacheable_misses::total 55598 # number of overall MSHR uncacheable misses 700system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4208861714 # number of ReadReq MSHR miss cycles 701system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4208861714 # number of ReadReq MSHR miss cycles 702system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4793451106 # number of WriteReq MSHR miss cycles 703system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4793451106 # number of WriteReq MSHR miss cycles 704system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1567109691 # number of SoftPFReq MSHR miss cycles 705system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1567109691 # number of SoftPFReq MSHR miss cycles 706system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 90045006 # number of LoadLockedReq MSHR miss cycles 707system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90045006 # number of LoadLockedReq MSHR miss cycles 708system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 448833841 # number of StoreCondReq MSHR miss cycles 709system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 448833841 # number of StoreCondReq MSHR miss cycles 710system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 579500 # number of StoreCondFailReq MSHR miss cycles 711system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 579500 # number of StoreCondFailReq MSHR miss cycles 712system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9002312820 # number of demand (read+write) MSHR miss cycles 713system.cpu0.dcache.demand_mshr_miss_latency::total 9002312820 # number of demand (read+write) MSHR miss cycles 714system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10569422511 # number of overall MSHR miss cycles 715system.cpu0.dcache.overall_mshr_miss_latency::total 10569422511 # number of overall MSHR miss cycles 716system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5627001499 # number of ReadReq MSHR uncacheable cycles 717system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5627001499 # number of ReadReq MSHR uncacheable cycles 718system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4261635500 # number of WriteReq MSHR uncacheable cycles 719system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4261635500 # number of WriteReq MSHR uncacheable cycles 720system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9888636999 # number of overall MSHR uncacheable cycles 721system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9888636999 # number of overall MSHR uncacheable cycles 722system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016940 # mshr miss rate for ReadReq accesses 723system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016940 # mshr miss rate for ReadReq accesses 724system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018780 # mshr miss rate for WriteReq accesses 725system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018780 # mshr miss rate for WriteReq accesses 726system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226570 # mshr miss rate for SoftPFReq accesses 727system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226570 # mshr miss rate for SoftPFReq accesses 728system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.015961 # mshr miss rate for LoadLockedReq accesses 729system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.015961 # mshr miss rate for LoadLockedReq accesses 730system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056988 # mshr miss rate for StoreCondReq accesses 731system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056988 # mshr miss rate for StoreCondReq accesses 732system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017733 # mshr miss rate for demand accesses 733system.cpu0.dcache.demand_mshr_miss_rate::total 0.017733 # mshr miss rate for demand accesses 734system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020085 # mshr miss rate for overall accesses 735system.cpu0.dcache.overall_mshr_miss_rate::total 0.020085 # mshr miss rate for overall accesses 736system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11318.495319 # average ReadReq mshr miss latency 737system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11318.495319 # average ReadReq mshr miss latency 738system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15361.311296 # average WriteReq mshr miss latency 739system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15361.311296 # average WriteReq mshr miss latency 740system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15744.149765 # average SoftPFReq mshr miss latency 741system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15744.149765 # average SoftPFReq mshr miss latency 742system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14905.645754 # average LoadLockedReq mshr miss latency 743system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14905.645754 # average LoadLockedReq mshr miss latency 744system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21055.206689 # average StoreCondReq mshr miss latency 745system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21055.206689 # average StoreCondReq mshr miss latency |
| 732system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 733system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 746system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 747system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 734system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13053.371555 # average overall mshr miss latency 735system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13053.371555 # average overall mshr miss latency 736system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13379.750472 # average overall mshr miss latency 737system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13379.750472 # average overall mshr miss latency 738system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 739system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 740system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 741system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 742system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 743system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 748system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13163.123509 # average overall mshr miss latency 749system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13163.123509 # average overall mshr miss latency 750system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13491.042723 # average overall mshr miss latency 751system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13491.042723 # average overall mshr miss latency 752system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191180.018992 # average ReadReq mshr uncacheable latency 753system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191180.018992 # average ReadReq mshr uncacheable latency 754system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162875.425186 # average WriteReq mshr uncacheable latency 755system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162875.425186 # average WriteReq mshr uncacheable latency 756system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177859.581262 # average overall mshr uncacheable latency 757system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177859.581262 # average overall mshr uncacheable latency |
| 744system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 758system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 745system.cpu0.icache.tags.replacements 1969157 # number of replacements 746system.cpu0.icache.tags.tagsinuse 511.783924 # Cycle average of tags in use 747system.cpu0.icache.tags.total_refs 36716761 # Total number of references to valid blocks. 748system.cpu0.icache.tags.sampled_refs 1969669 # Sample count of references to valid blocks. 749system.cpu0.icache.tags.avg_refs 18.641082 # Average number of references to valid blocks. 750system.cpu0.icache.tags.warmup_cycle 6455779250 # Cycle when the warmup percentage was hit. 751system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.783924 # Average occupied blocks per requestor 752system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999578 # Average percentage of cache occupancy 753system.cpu0.icache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy | 759system.cpu0.icache.tags.replacements 1884730 # number of replacements 760system.cpu0.icache.tags.tagsinuse 511.784347 # Cycle average of tags in use 761system.cpu0.icache.tags.total_refs 66497574 # Total number of references to valid blocks. 762system.cpu0.icache.tags.sampled_refs 1885242 # Sample count of references to valid blocks. 763system.cpu0.icache.tags.avg_refs 35.272699 # Average number of references to valid blocks. 764system.cpu0.icache.tags.warmup_cycle 6453364250 # Cycle when the warmup percentage was hit. 765system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.784347 # Average occupied blocks per requestor 766system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999579 # Average percentage of cache occupancy 767system.cpu0.icache.tags.occ_percent::total 0.999579 # Average percentage of cache occupancy |
| 754system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 768system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 755system.cpu0.icache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id 756system.cpu0.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id 757system.cpu0.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id | 769system.cpu0.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id 770system.cpu0.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id 771system.cpu0.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id |
| 758system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 772system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 759system.cpu0.icache.tags.tag_accesses 79342579 # Number of tag accesses 760system.cpu0.icache.tags.data_accesses 79342579 # Number of data accesses 761system.cpu0.icache.ReadReq_hits::cpu0.inst 36716761 # number of ReadReq hits 762system.cpu0.icache.ReadReq_hits::total 36716761 # number of ReadReq hits 763system.cpu0.icache.demand_hits::cpu0.inst 36716761 # number of demand (read+write) hits 764system.cpu0.icache.demand_hits::total 36716761 # number of demand (read+write) hits 765system.cpu0.icache.overall_hits::cpu0.inst 36716761 # number of overall hits 766system.cpu0.icache.overall_hits::total 36716761 # number of overall hits 767system.cpu0.icache.ReadReq_misses::cpu0.inst 1969686 # number of ReadReq misses 768system.cpu0.icache.ReadReq_misses::total 1969686 # number of ReadReq misses 769system.cpu0.icache.demand_misses::cpu0.inst 1969686 # number of demand (read+write) misses 770system.cpu0.icache.demand_misses::total 1969686 # number of demand (read+write) misses 771system.cpu0.icache.overall_misses::cpu0.inst 1969686 # number of overall misses 772system.cpu0.icache.overall_misses::total 1969686 # number of overall misses 773system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18594001543 # number of ReadReq miss cycles 774system.cpu0.icache.ReadReq_miss_latency::total 18594001543 # number of ReadReq miss cycles 775system.cpu0.icache.demand_miss_latency::cpu0.inst 18594001543 # number of demand (read+write) miss cycles 776system.cpu0.icache.demand_miss_latency::total 18594001543 # number of demand (read+write) miss cycles 777system.cpu0.icache.overall_miss_latency::cpu0.inst 18594001543 # number of overall miss cycles 778system.cpu0.icache.overall_miss_latency::total 18594001543 # number of overall miss cycles 779system.cpu0.icache.ReadReq_accesses::cpu0.inst 38686447 # number of ReadReq accesses(hits+misses) 780system.cpu0.icache.ReadReq_accesses::total 38686447 # number of ReadReq accesses(hits+misses) 781system.cpu0.icache.demand_accesses::cpu0.inst 38686447 # number of demand (read+write) accesses 782system.cpu0.icache.demand_accesses::total 38686447 # number of demand (read+write) accesses 783system.cpu0.icache.overall_accesses::cpu0.inst 38686447 # number of overall (read+write) accesses 784system.cpu0.icache.overall_accesses::total 38686447 # number of overall (read+write) accesses 785system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050914 # miss rate for ReadReq accesses 786system.cpu0.icache.ReadReq_miss_rate::total 0.050914 # miss rate for ReadReq accesses 787system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050914 # miss rate for demand accesses 788system.cpu0.icache.demand_miss_rate::total 0.050914 # miss rate for demand accesses 789system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050914 # miss rate for overall accesses 790system.cpu0.icache.overall_miss_rate::total 0.050914 # miss rate for overall accesses 791system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9440.084127 # average ReadReq miss latency 792system.cpu0.icache.ReadReq_avg_miss_latency::total 9440.084127 # average ReadReq miss latency 793system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9440.084127 # average overall miss latency 794system.cpu0.icache.demand_avg_miss_latency::total 9440.084127 # average overall miss latency 795system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9440.084127 # average overall miss latency 796system.cpu0.icache.overall_avg_miss_latency::total 9440.084127 # average overall miss latency | 773system.cpu0.icache.tags.tag_accesses 138650918 # Number of tag accesses 774system.cpu0.icache.tags.data_accesses 138650918 # Number of data accesses 775system.cpu0.icache.ReadReq_hits::cpu0.inst 66497574 # number of ReadReq hits 776system.cpu0.icache.ReadReq_hits::total 66497574 # number of ReadReq hits 777system.cpu0.icache.demand_hits::cpu0.inst 66497574 # number of demand (read+write) hits 778system.cpu0.icache.demand_hits::total 66497574 # number of demand (read+write) hits 779system.cpu0.icache.overall_hits::cpu0.inst 66497574 # number of overall hits 780system.cpu0.icache.overall_hits::total 66497574 # number of overall hits 781system.cpu0.icache.ReadReq_misses::cpu0.inst 1885257 # number of ReadReq misses 782system.cpu0.icache.ReadReq_misses::total 1885257 # number of ReadReq misses 783system.cpu0.icache.demand_misses::cpu0.inst 1885257 # number of demand (read+write) misses 784system.cpu0.icache.demand_misses::total 1885257 # number of demand (read+write) misses 785system.cpu0.icache.overall_misses::cpu0.inst 1885257 # number of overall misses 786system.cpu0.icache.overall_misses::total 1885257 # number of overall misses 787system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17590953808 # number of ReadReq miss cycles 788system.cpu0.icache.ReadReq_miss_latency::total 17590953808 # number of ReadReq miss cycles 789system.cpu0.icache.demand_miss_latency::cpu0.inst 17590953808 # number of demand (read+write) miss cycles 790system.cpu0.icache.demand_miss_latency::total 17590953808 # number of demand (read+write) miss cycles 791system.cpu0.icache.overall_miss_latency::cpu0.inst 17590953808 # number of overall miss cycles 792system.cpu0.icache.overall_miss_latency::total 17590953808 # number of overall miss cycles 793system.cpu0.icache.ReadReq_accesses::cpu0.inst 68382831 # number of ReadReq accesses(hits+misses) 794system.cpu0.icache.ReadReq_accesses::total 68382831 # number of ReadReq accesses(hits+misses) 795system.cpu0.icache.demand_accesses::cpu0.inst 68382831 # number of demand (read+write) accesses 796system.cpu0.icache.demand_accesses::total 68382831 # number of demand (read+write) accesses 797system.cpu0.icache.overall_accesses::cpu0.inst 68382831 # number of overall (read+write) accesses 798system.cpu0.icache.overall_accesses::total 68382831 # number of overall (read+write) accesses 799system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.027569 # miss rate for ReadReq accesses 800system.cpu0.icache.ReadReq_miss_rate::total 0.027569 # miss rate for ReadReq accesses 801system.cpu0.icache.demand_miss_rate::cpu0.inst 0.027569 # miss rate for demand accesses 802system.cpu0.icache.demand_miss_rate::total 0.027569 # miss rate for demand accesses 803system.cpu0.icache.overall_miss_rate::cpu0.inst 0.027569 # miss rate for overall accesses 804system.cpu0.icache.overall_miss_rate::total 0.027569 # miss rate for overall accesses 805system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9330.798829 # average ReadReq miss latency 806system.cpu0.icache.ReadReq_avg_miss_latency::total 9330.798829 # average ReadReq miss latency 807system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9330.798829 # average overall miss latency 808system.cpu0.icache.demand_avg_miss_latency::total 9330.798829 # average overall miss latency 809system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9330.798829 # average overall miss latency 810system.cpu0.icache.overall_avg_miss_latency::total 9330.798829 # average overall miss latency |
| 797system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 798system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 799system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 800system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 801system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 802system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 803system.cpu0.icache.fast_writes 0 # number of fast writes performed 804system.cpu0.icache.cache_copies 0 # number of cache copies performed | 811system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 812system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 813system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 814system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 815system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 816system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 817system.cpu0.icache.fast_writes 0 # number of fast writes performed 818system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 805system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1969686 # number of ReadReq MSHR misses 806system.cpu0.icache.ReadReq_mshr_misses::total 1969686 # number of ReadReq MSHR misses 807system.cpu0.icache.demand_mshr_misses::cpu0.inst 1969686 # number of demand (read+write) MSHR misses 808system.cpu0.icache.demand_mshr_misses::total 1969686 # number of demand (read+write) MSHR misses 809system.cpu0.icache.overall_mshr_misses::cpu0.inst 1969686 # number of overall MSHR misses 810system.cpu0.icache.overall_mshr_misses::total 1969686 # number of overall MSHR misses 811system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16614994457 # number of ReadReq MSHR miss cycles 812system.cpu0.icache.ReadReq_mshr_miss_latency::total 16614994457 # number of ReadReq MSHR miss cycles 813system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16614994457 # number of demand (read+write) MSHR miss cycles 814system.cpu0.icache.demand_mshr_miss_latency::total 16614994457 # number of demand (read+write) MSHR miss cycles 815system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16614994457 # number of overall MSHR miss cycles 816system.cpu0.icache.overall_mshr_miss_latency::total 16614994457 # number of overall MSHR miss cycles 817system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 312159000 # number of ReadReq MSHR uncacheable cycles 818system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 312159000 # number of ReadReq MSHR uncacheable cycles 819system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 312159000 # number of overall MSHR uncacheable cycles 820system.cpu0.icache.overall_mshr_uncacheable_latency::total 312159000 # number of overall MSHR uncacheable cycles 821system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050914 # mshr miss rate for ReadReq accesses 822system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050914 # mshr miss rate for ReadReq accesses 823system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050914 # mshr miss rate for demand accesses 824system.cpu0.icache.demand_mshr_miss_rate::total 0.050914 # mshr miss rate for demand accesses 825system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050914 # mshr miss rate for overall accesses 826system.cpu0.icache.overall_mshr_miss_rate::total 0.050914 # mshr miss rate for overall accesses 827system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8435.351857 # average ReadReq mshr miss latency 828system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8435.351857 # average ReadReq mshr miss latency 829system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8435.351857 # average overall mshr miss latency 830system.cpu0.icache.demand_avg_mshr_miss_latency::total 8435.351857 # average overall mshr miss latency 831system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8435.351857 # average overall mshr miss latency 832system.cpu0.icache.overall_avg_mshr_miss_latency::total 8435.351857 # average overall mshr miss latency 833system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 834system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 835system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 836system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 819system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1885257 # number of ReadReq MSHR misses 820system.cpu0.icache.ReadReq_mshr_misses::total 1885257 # number of ReadReq MSHR misses 821system.cpu0.icache.demand_mshr_misses::cpu0.inst 1885257 # number of demand (read+write) MSHR misses 822system.cpu0.icache.demand_mshr_misses::total 1885257 # number of demand (read+write) MSHR misses 823system.cpu0.icache.overall_mshr_misses::cpu0.inst 1885257 # number of overall MSHR misses 824system.cpu0.icache.overall_mshr_misses::total 1885257 # number of overall MSHR misses 825system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3367 # number of ReadReq MSHR uncacheable 826system.cpu0.icache.ReadReq_mshr_uncacheable::total 3367 # number of ReadReq MSHR uncacheable 827system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3367 # number of overall MSHR uncacheable misses 828system.cpu0.icache.overall_mshr_uncacheable_misses::total 3367 # number of overall MSHR uncacheable misses 829system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 15697482196 # number of ReadReq MSHR miss cycles 830system.cpu0.icache.ReadReq_mshr_miss_latency::total 15697482196 # number of ReadReq MSHR miss cycles 831system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 15697482196 # number of demand (read+write) MSHR miss cycles 832system.cpu0.icache.demand_mshr_miss_latency::total 15697482196 # number of demand (read+write) MSHR miss cycles 833system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 15697482196 # number of overall MSHR miss cycles 834system.cpu0.icache.overall_mshr_miss_latency::total 15697482196 # number of overall MSHR miss cycles 835system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 310652000 # number of ReadReq MSHR uncacheable cycles 836system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 310652000 # number of ReadReq MSHR uncacheable cycles 837system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 310652000 # number of overall MSHR uncacheable cycles 838system.cpu0.icache.overall_mshr_uncacheable_latency::total 310652000 # number of overall MSHR uncacheable cycles 839system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027569 # mshr miss rate for ReadReq accesses 840system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027569 # mshr miss rate for ReadReq accesses 841system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027569 # mshr miss rate for demand accesses 842system.cpu0.icache.demand_mshr_miss_rate::total 0.027569 # mshr miss rate for demand accesses 843system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027569 # mshr miss rate for overall accesses 844system.cpu0.icache.overall_mshr_miss_rate::total 0.027569 # mshr miss rate for overall accesses 845system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8326.441539 # average ReadReq mshr miss latency 846system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8326.441539 # average ReadReq mshr miss latency 847system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8326.441539 # average overall mshr miss latency 848system.cpu0.icache.demand_avg_mshr_miss_latency::total 8326.441539 # average overall mshr miss latency 849system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8326.441539 # average overall mshr miss latency 850system.cpu0.icache.overall_avg_mshr_miss_latency::total 8326.441539 # average overall mshr miss latency 851system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264 # average ReadReq mshr uncacheable latency 852system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92263.736264 # average ReadReq mshr uncacheable latency 853system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92263.736264 # average overall mshr uncacheable latency 854system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92263.736264 # average overall mshr uncacheable latency |
| 837system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 855system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 838system.cpu0.l2cache.prefetcher.num_hwpf_issued 1838342 # number of hwpf issued 839system.cpu0.l2cache.prefetcher.pfIdentified 1838481 # number of prefetch candidates identified 840system.cpu0.l2cache.prefetcher.pfBufferHit 119 # number of redundant prefetches already in prefetch queue | 856system.cpu0.l2cache.prefetcher.num_hwpf_issued 1754468 # number of hwpf issued 857system.cpu0.l2cache.prefetcher.pfIdentified 1754508 # number of prefetch candidates identified 858system.cpu0.l2cache.prefetcher.pfBufferHit 35 # number of redundant prefetches already in prefetch queue |
| 841system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 842system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 859system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 860system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 843system.cpu0.l2cache.prefetcher.pfSpanPage 233119 # number of prefetches not generated due to page crossing 844system.cpu0.l2cache.tags.replacements 300411 # number of replacements 845system.cpu0.l2cache.tags.tagsinuse 16152.844833 # Cycle average of tags in use 846system.cpu0.l2cache.tags.total_refs 2914098 # Total number of references to valid blocks. 847system.cpu0.l2cache.tags.sampled_refs 316661 # Sample count of references to valid blocks. 848system.cpu0.l2cache.tags.avg_refs 9.202579 # Average number of references to valid blocks. 849system.cpu0.l2cache.tags.warmup_cycle 2826281697500 # Cycle when the warmup percentage was hit. 850system.cpu0.l2cache.tags.occ_blocks::writebacks 6746.773874 # Average occupied blocks per requestor 851system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 56.784036 # Average occupied blocks per requestor 852system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.060323 # Average occupied blocks per requestor 853system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5767.067703 # Average occupied blocks per requestor 854system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1954.184068 # Average occupied blocks per requestor 855system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1627.974828 # Average occupied blocks per requestor 856system.cpu0.l2cache.tags.occ_percent::writebacks 0.411790 # Average percentage of cache occupancy 857system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003466 # Average percentage of cache occupancy 858system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy 859system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.351994 # Average percentage of cache occupancy 860system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.119274 # Average percentage of cache occupancy 861system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.099364 # Average percentage of cache occupancy 862system.cpu0.l2cache.tags.occ_percent::total 0.985891 # Average percentage of cache occupancy 863system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1019 # Occupied blocks per task id 864system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 865system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15218 # Occupied blocks per task id 866system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id 867system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 323 # Occupied blocks per task id 868system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 417 # Occupied blocks per task id 869system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 268 # Occupied blocks per task id 870system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 871system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 872system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 873system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id 874system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4291 # Occupied blocks per task id 875system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7836 # Occupied blocks per task id 876system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2805 # Occupied blocks per task id 877system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062195 # Percentage of cache occupancy per task id 878system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id 879system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.928833 # Percentage of cache occupancy per task id 880system.cpu0.l2cache.tags.tag_accesses 55319704 # Number of tag accesses 881system.cpu0.l2cache.tags.data_accesses 55319704 # Number of data accesses 882system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 80908 # number of ReadReq hits 883system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4161 # number of ReadReq hits 884system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1898400 # number of ReadReq hits 885system.cpu0.l2cache.ReadReq_hits::cpu0.data 400606 # number of ReadReq hits 886system.cpu0.l2cache.ReadReq_hits::total 2384075 # number of ReadReq hits 887system.cpu0.l2cache.Writeback_hits::writebacks 513519 # number of Writeback hits 888system.cpu0.l2cache.Writeback_hits::total 513519 # number of Writeback hits 889system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28702 # number of UpgradeReq hits 890system.cpu0.l2cache.UpgradeReq_hits::total 28702 # number of UpgradeReq hits 891system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1838 # number of SCUpgradeReq hits 892system.cpu0.l2cache.SCUpgradeReq_hits::total 1838 # number of SCUpgradeReq hits 893system.cpu0.l2cache.ReadExReq_hits::cpu0.data 223052 # number of ReadExReq hits 894system.cpu0.l2cache.ReadExReq_hits::total 223052 # number of ReadExReq hits 895system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 80908 # number of demand (read+write) hits 896system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4161 # number of demand (read+write) hits 897system.cpu0.l2cache.demand_hits::cpu0.inst 1898400 # number of demand (read+write) hits 898system.cpu0.l2cache.demand_hits::cpu0.data 623658 # number of demand (read+write) hits 899system.cpu0.l2cache.demand_hits::total 2607127 # number of demand (read+write) hits 900system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 80908 # number of overall hits 901system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4161 # number of overall hits 902system.cpu0.l2cache.overall_hits::cpu0.inst 1898400 # number of overall hits 903system.cpu0.l2cache.overall_hits::cpu0.data 623658 # number of overall hits 904system.cpu0.l2cache.overall_hits::total 2607127 # number of overall hits 905system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 892 # number of ReadReq misses 906system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 113 # number of ReadReq misses 907system.cpu0.l2cache.ReadReq_misses::cpu0.inst 71286 # number of ReadReq misses 908system.cpu0.l2cache.ReadReq_misses::cpu0.data 100496 # number of ReadReq misses 909system.cpu0.l2cache.ReadReq_misses::total 172787 # number of ReadReq misses 910system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26801 # number of UpgradeReq misses 911system.cpu0.l2cache.UpgradeReq_misses::total 26801 # number of UpgradeReq misses 912system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18444 # number of SCUpgradeReq misses 913system.cpu0.l2cache.SCUpgradeReq_misses::total 18444 # number of SCUpgradeReq misses | 861system.cpu0.l2cache.prefetcher.pfSpanPage 221228 # number of prefetches not generated due to page crossing 862system.cpu0.l2cache.tags.replacements 285273 # number of replacements 863system.cpu0.l2cache.tags.tagsinuse 16083.611278 # Cycle average of tags in use 864system.cpu0.l2cache.tags.total_refs 2784455 # Total number of references to valid blocks. 865system.cpu0.l2cache.tags.sampled_refs 301530 # Sample count of references to valid blocks. 866system.cpu0.l2cache.tags.avg_refs 9.234421 # Average number of references to valid blocks. 867system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 868system.cpu0.l2cache.tags.occ_blocks::writebacks 8638.017947 # Average occupied blocks per requestor 869system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 60.519313 # Average occupied blocks per requestor 870system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.077213 # Average occupied blocks per requestor 871system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4655.233239 # Average occupied blocks per requestor 872system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1567.458030 # Average occupied blocks per requestor 873system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1162.305536 # Average occupied blocks per requestor 874system.cpu0.l2cache.tags.occ_percent::writebacks 0.527223 # Average percentage of cache occupancy 875system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003694 # Average percentage of cache occupancy 876system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy 877system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.284133 # Average percentage of cache occupancy 878system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.095670 # Average percentage of cache occupancy 879system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.070942 # Average percentage of cache occupancy 880system.cpu0.l2cache.tags.occ_percent::total 0.981666 # Average percentage of cache occupancy 881system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1030 # Occupied blocks per task id 882system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id 883system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15217 # Occupied blocks per task id 884system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id 885system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 322 # Occupied blocks per task id 886system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 428 # Occupied blocks per task id 887system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 273 # Occupied blocks per task id 888system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 889system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 890system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 891system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 892system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id 893system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id 894system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4109 # Occupied blocks per task id 895system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7718 # Occupied blocks per task id 896system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3035 # Occupied blocks per task id 897system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062866 # Percentage of cache occupancy per task id 898system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id 899system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.928772 # Percentage of cache occupancy per task id 900system.cpu0.l2cache.tags.tag_accesses 52971740 # Number of tag accesses 901system.cpu0.l2cache.tags.data_accesses 52971740 # Number of data accesses 902system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77753 # number of ReadReq hits 903system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4353 # number of ReadReq hits 904system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1821437 # number of ReadReq hits 905system.cpu0.l2cache.ReadReq_hits::cpu0.data 376273 # number of ReadReq hits 906system.cpu0.l2cache.ReadReq_hits::total 2279816 # number of ReadReq hits 907system.cpu0.l2cache.Writeback_hits::writebacks 490181 # number of Writeback hits 908system.cpu0.l2cache.Writeback_hits::total 490181 # number of Writeback hits 909system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28296 # number of UpgradeReq hits 910system.cpu0.l2cache.UpgradeReq_hits::total 28296 # number of UpgradeReq hits 911system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1798 # number of SCUpgradeReq hits 912system.cpu0.l2cache.SCUpgradeReq_hits::total 1798 # number of SCUpgradeReq hits 913system.cpu0.l2cache.ReadExReq_hits::cpu0.data 212312 # number of ReadExReq hits 914system.cpu0.l2cache.ReadExReq_hits::total 212312 # number of ReadExReq hits 915system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77753 # number of demand (read+write) hits 916system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4353 # number of demand (read+write) hits 917system.cpu0.l2cache.demand_hits::cpu0.inst 1821437 # number of demand (read+write) hits 918system.cpu0.l2cache.demand_hits::cpu0.data 588585 # number of demand (read+write) hits 919system.cpu0.l2cache.demand_hits::total 2492128 # number of demand (read+write) hits 920system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77753 # number of overall hits 921system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4353 # number of overall hits 922system.cpu0.l2cache.overall_hits::cpu0.inst 1821437 # number of overall hits 923system.cpu0.l2cache.overall_hits::cpu0.data 588585 # number of overall hits 924system.cpu0.l2cache.overall_hits::total 2492128 # number of overall hits 925system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 788 # number of ReadReq misses 926system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 123 # number of ReadReq misses 927system.cpu0.l2cache.ReadReq_misses::cpu0.inst 63820 # number of ReadReq misses 928system.cpu0.l2cache.ReadReq_misses::cpu0.data 101159 # number of ReadReq misses 929system.cpu0.l2cache.ReadReq_misses::total 165890 # number of ReadReq misses 930system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 28131 # number of UpgradeReq misses 931system.cpu0.l2cache.UpgradeReq_misses::total 28131 # number of UpgradeReq misses 932system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19518 # number of SCUpgradeReq misses 933system.cpu0.l2cache.SCUpgradeReq_misses::total 19518 # number of SCUpgradeReq misses |
| 914system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses 915system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses | 934system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses 935system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses |
| 916system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45324 # number of ReadExReq misses 917system.cpu0.l2cache.ReadExReq_misses::total 45324 # number of ReadExReq misses 918system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 892 # number of demand (read+write) misses 919system.cpu0.l2cache.demand_misses::cpu0.itb.walker 113 # number of demand (read+write) misses 920system.cpu0.l2cache.demand_misses::cpu0.inst 71286 # number of demand (read+write) misses 921system.cpu0.l2cache.demand_misses::cpu0.data 145820 # number of demand (read+write) misses 922system.cpu0.l2cache.demand_misses::total 218111 # number of demand (read+write) misses 923system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 892 # number of overall misses 924system.cpu0.l2cache.overall_misses::cpu0.itb.walker 113 # number of overall misses 925system.cpu0.l2cache.overall_misses::cpu0.inst 71286 # number of overall misses 926system.cpu0.l2cache.overall_misses::cpu0.data 145820 # number of overall misses 927system.cpu0.l2cache.overall_misses::total 218111 # number of overall misses 928system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 31644248 # number of ReadReq miss cycles 929system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2618496 # number of ReadReq miss cycles 930system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 3281889931 # number of ReadReq miss cycles 931system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 3018329920 # number of ReadReq miss cycles 932system.cpu0.l2cache.ReadReq_miss_latency::total 6334482595 # number of ReadReq miss cycles 933system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 498950782 # number of UpgradeReq miss cycles 934system.cpu0.l2cache.UpgradeReq_miss_latency::total 498950782 # number of UpgradeReq miss cycles 935system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 372929796 # number of SCUpgradeReq miss cycles 936system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 372929796 # number of SCUpgradeReq miss cycles 937system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 423999 # number of SCUpgradeFailReq miss cycles 938system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 423999 # number of SCUpgradeFailReq miss cycles 939system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2226350926 # number of ReadExReq miss cycles 940system.cpu0.l2cache.ReadExReq_miss_latency::total 2226350926 # number of ReadExReq miss cycles 941system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 31644248 # number of demand (read+write) miss cycles 942system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2618496 # number of demand (read+write) miss cycles 943system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3281889931 # number of demand (read+write) miss cycles 944system.cpu0.l2cache.demand_miss_latency::cpu0.data 5244680846 # number of demand (read+write) miss cycles 945system.cpu0.l2cache.demand_miss_latency::total 8560833521 # number of demand (read+write) miss cycles 946system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 31644248 # number of overall miss cycles 947system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2618496 # number of overall miss cycles 948system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3281889931 # number of overall miss cycles 949system.cpu0.l2cache.overall_miss_latency::cpu0.data 5244680846 # number of overall miss cycles 950system.cpu0.l2cache.overall_miss_latency::total 8560833521 # number of overall miss cycles 951system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 81800 # number of ReadReq accesses(hits+misses) 952system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4274 # number of ReadReq accesses(hits+misses) 953system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1969686 # number of ReadReq accesses(hits+misses) 954system.cpu0.l2cache.ReadReq_accesses::cpu0.data 501102 # number of ReadReq accesses(hits+misses) 955system.cpu0.l2cache.ReadReq_accesses::total 2556862 # number of ReadReq accesses(hits+misses) 956system.cpu0.l2cache.Writeback_accesses::writebacks 513519 # number of Writeback accesses(hits+misses) 957system.cpu0.l2cache.Writeback_accesses::total 513519 # number of Writeback accesses(hits+misses) 958system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55503 # number of UpgradeReq accesses(hits+misses) 959system.cpu0.l2cache.UpgradeReq_accesses::total 55503 # number of UpgradeReq accesses(hits+misses) 960system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20282 # number of SCUpgradeReq accesses(hits+misses) 961system.cpu0.l2cache.SCUpgradeReq_accesses::total 20282 # number of SCUpgradeReq accesses(hits+misses) | 936system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43311 # number of ReadExReq misses 937system.cpu0.l2cache.ReadExReq_misses::total 43311 # number of ReadExReq misses 938system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 788 # number of demand (read+write) misses 939system.cpu0.l2cache.demand_misses::cpu0.itb.walker 123 # number of demand (read+write) misses 940system.cpu0.l2cache.demand_misses::cpu0.inst 63820 # number of demand (read+write) misses 941system.cpu0.l2cache.demand_misses::cpu0.data 144470 # number of demand (read+write) misses 942system.cpu0.l2cache.demand_misses::total 209201 # number of demand (read+write) misses 943system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 788 # number of overall misses 944system.cpu0.l2cache.overall_misses::cpu0.itb.walker 123 # number of overall misses 945system.cpu0.l2cache.overall_misses::cpu0.inst 63820 # number of overall misses 946system.cpu0.l2cache.overall_misses::cpu0.data 144470 # number of overall misses 947system.cpu0.l2cache.overall_misses::total 209201 # number of overall misses 948system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 27073496 # number of ReadReq miss cycles 949system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2775500 # number of ReadReq miss cycles 950system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2907382734 # number of ReadReq miss cycles 951system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2926155686 # number of ReadReq miss cycles 952system.cpu0.l2cache.ReadReq_miss_latency::total 5863387416 # number of ReadReq miss cycles 953system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 516960426 # number of UpgradeReq miss cycles 954system.cpu0.l2cache.UpgradeReq_miss_latency::total 516960426 # number of UpgradeReq miss cycles 955system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 396286408 # number of SCUpgradeReq miss cycles 956system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 396286408 # number of SCUpgradeReq miss cycles 957system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 563999 # number of SCUpgradeFailReq miss cycles 958system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 563999 # number of SCUpgradeFailReq miss cycles 959system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2178252172 # number of ReadExReq miss cycles 960system.cpu0.l2cache.ReadExReq_miss_latency::total 2178252172 # number of ReadExReq miss cycles 961system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 27073496 # number of demand (read+write) miss cycles 962system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2775500 # number of demand (read+write) miss cycles 963system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2907382734 # number of demand (read+write) miss cycles 964system.cpu0.l2cache.demand_miss_latency::cpu0.data 5104407858 # number of demand (read+write) miss cycles 965system.cpu0.l2cache.demand_miss_latency::total 8041639588 # number of demand (read+write) miss cycles 966system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 27073496 # number of overall miss cycles 967system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2775500 # number of overall miss cycles 968system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2907382734 # number of overall miss cycles 969system.cpu0.l2cache.overall_miss_latency::cpu0.data 5104407858 # number of overall miss cycles 970system.cpu0.l2cache.overall_miss_latency::total 8041639588 # number of overall miss cycles 971system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78541 # number of ReadReq accesses(hits+misses) 972system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4476 # number of ReadReq accesses(hits+misses) 973system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1885257 # number of ReadReq accesses(hits+misses) 974system.cpu0.l2cache.ReadReq_accesses::cpu0.data 477432 # number of ReadReq accesses(hits+misses) 975system.cpu0.l2cache.ReadReq_accesses::total 2445706 # number of ReadReq accesses(hits+misses) 976system.cpu0.l2cache.Writeback_accesses::writebacks 490181 # number of Writeback accesses(hits+misses) 977system.cpu0.l2cache.Writeback_accesses::total 490181 # number of Writeback accesses(hits+misses) 978system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56427 # number of UpgradeReq accesses(hits+misses) 979system.cpu0.l2cache.UpgradeReq_accesses::total 56427 # number of UpgradeReq accesses(hits+misses) 980system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21316 # number of SCUpgradeReq accesses(hits+misses) 981system.cpu0.l2cache.SCUpgradeReq_accesses::total 21316 # number of SCUpgradeReq accesses(hits+misses) |
| 962system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 963system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) | 982system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 983system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) |
| 964system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 268376 # number of ReadExReq accesses(hits+misses) 965system.cpu0.l2cache.ReadExReq_accesses::total 268376 # number of ReadExReq accesses(hits+misses) 966system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 81800 # number of demand (read+write) accesses 967system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4274 # number of demand (read+write) accesses 968system.cpu0.l2cache.demand_accesses::cpu0.inst 1969686 # number of demand (read+write) accesses 969system.cpu0.l2cache.demand_accesses::cpu0.data 769478 # number of demand (read+write) accesses 970system.cpu0.l2cache.demand_accesses::total 2825238 # number of demand (read+write) accesses 971system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 81800 # number of overall (read+write) accesses 972system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4274 # number of overall (read+write) accesses 973system.cpu0.l2cache.overall_accesses::cpu0.inst 1969686 # number of overall (read+write) accesses 974system.cpu0.l2cache.overall_accesses::cpu0.data 769478 # number of overall (read+write) accesses 975system.cpu0.l2cache.overall_accesses::total 2825238 # number of overall (read+write) accesses 976system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010905 # miss rate for ReadReq accesses 977system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.026439 # miss rate for ReadReq accesses 978system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.036192 # miss rate for ReadReq accesses 979system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.200550 # miss rate for ReadReq accesses 980system.cpu0.l2cache.ReadReq_miss_rate::total 0.067578 # miss rate for ReadReq accesses 981system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.482875 # miss rate for UpgradeReq accesses 982system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.482875 # miss rate for UpgradeReq accesses 983system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.909378 # miss rate for SCUpgradeReq accesses 984system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.909378 # miss rate for SCUpgradeReq accesses | 984system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 255623 # number of ReadExReq accesses(hits+misses) 985system.cpu0.l2cache.ReadExReq_accesses::total 255623 # number of ReadExReq accesses(hits+misses) 986system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78541 # number of demand (read+write) accesses 987system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4476 # number of demand (read+write) accesses 988system.cpu0.l2cache.demand_accesses::cpu0.inst 1885257 # number of demand (read+write) accesses 989system.cpu0.l2cache.demand_accesses::cpu0.data 733055 # number of demand (read+write) accesses 990system.cpu0.l2cache.demand_accesses::total 2701329 # number of demand (read+write) accesses 991system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78541 # number of overall (read+write) accesses 992system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4476 # number of overall (read+write) accesses 993system.cpu0.l2cache.overall_accesses::cpu0.inst 1885257 # number of overall (read+write) accesses 994system.cpu0.l2cache.overall_accesses::cpu0.data 733055 # number of overall (read+write) accesses 995system.cpu0.l2cache.overall_accesses::total 2701329 # number of overall (read+write) accesses 996system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010033 # miss rate for ReadReq accesses 997system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.027480 # miss rate for ReadReq accesses 998system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.033852 # miss rate for ReadReq accesses 999system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.211881 # miss rate for ReadReq accesses 1000system.cpu0.l2cache.ReadReq_miss_rate::total 0.067829 # miss rate for ReadReq accesses 1001system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.498538 # miss rate for UpgradeReq accesses 1002system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.498538 # miss rate for UpgradeReq accesses 1003system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.915650 # miss rate for SCUpgradeReq accesses 1004system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.915650 # miss rate for SCUpgradeReq accesses |
| 985system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 986system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 1005system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1006system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 987system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.168882 # miss rate for ReadExReq accesses 988system.cpu0.l2cache.ReadExReq_miss_rate::total 0.168882 # miss rate for ReadExReq accesses 989system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010905 # miss rate for demand accesses 990system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.026439 # miss rate for demand accesses 991system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.036192 # miss rate for demand accesses 992system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.189505 # miss rate for demand accesses 993system.cpu0.l2cache.demand_miss_rate::total 0.077201 # miss rate for demand accesses 994system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010905 # miss rate for overall accesses 995system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.026439 # miss rate for overall accesses 996system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.036192 # miss rate for overall accesses 997system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.189505 # miss rate for overall accesses 998system.cpu0.l2cache.overall_miss_rate::total 0.077201 # miss rate for overall accesses 999system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35475.614350 # average ReadReq miss latency 1000system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23172.530973 # average ReadReq miss latency 1001system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46038.351584 # average ReadReq miss latency 1002system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 30034.328929 # average ReadReq miss latency 1003system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36660.643422 # average ReadReq miss latency 1004system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18616.871833 # average UpgradeReq miss latency 1005system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18616.871833 # average UpgradeReq miss latency 1006system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20219.572544 # average SCUpgradeReq miss latency 1007system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20219.572544 # average SCUpgradeReq miss latency 1008system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 423999 # average SCUpgradeFailReq miss latency 1009system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 423999 # average SCUpgradeFailReq miss latency 1010system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49120.795296 # average ReadExReq miss latency 1011system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49120.795296 # average ReadExReq miss latency 1012system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35475.614350 # average overall miss latency 1013system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23172.530973 # average overall miss latency 1014system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46038.351584 # average overall miss latency 1015system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35966.814196 # average overall miss latency 1016system.cpu0.l2cache.demand_avg_miss_latency::total 39249.893499 # average overall miss latency 1017system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35475.614350 # average overall miss latency 1018system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23172.530973 # average overall miss latency 1019system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46038.351584 # average overall miss latency 1020system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35966.814196 # average overall miss latency 1021system.cpu0.l2cache.overall_avg_miss_latency::total 39249.893499 # average overall miss latency 1022system.cpu0.l2cache.blocked_cycles::no_mshrs 13 # number of cycles access was blocked | 1007system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.169433 # miss rate for ReadExReq accesses 1008system.cpu0.l2cache.ReadExReq_miss_rate::total 0.169433 # miss rate for ReadExReq accesses 1009system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010033 # miss rate for demand accesses 1010system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.027480 # miss rate for demand accesses 1011system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.033852 # miss rate for demand accesses 1012system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.197079 # miss rate for demand accesses 1013system.cpu0.l2cache.demand_miss_rate::total 0.077444 # miss rate for demand accesses 1014system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010033 # miss rate for overall accesses 1015system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.027480 # miss rate for overall accesses 1016system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.033852 # miss rate for overall accesses 1017system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.197079 # miss rate for overall accesses 1018system.cpu0.l2cache.overall_miss_rate::total 0.077444 # miss rate for overall accesses 1019system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34357.228426 # average ReadReq miss latency 1020system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22565.040650 # average ReadReq miss latency 1021system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 45555.981416 # average ReadReq miss latency 1022system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 28926.301031 # average ReadReq miss latency 1023system.cpu0.l2cache.ReadReq_avg_miss_latency::total 35345.032347 # average ReadReq miss latency 1024system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18376.894742 # average UpgradeReq miss latency 1025system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18376.894742 # average UpgradeReq miss latency 1026system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20303.638078 # average SCUpgradeReq miss latency 1027system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20303.638078 # average SCUpgradeReq miss latency 1028system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 563999 # average SCUpgradeFailReq miss latency 1029system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 563999 # average SCUpgradeFailReq miss latency 1030system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50293.278197 # average ReadExReq miss latency 1031system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50293.278197 # average ReadExReq miss latency 1032system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34357.228426 # average overall miss latency 1033system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22565.040650 # average overall miss latency 1034system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 45555.981416 # average overall miss latency 1035system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35331.957209 # average overall miss latency 1036system.cpu0.l2cache.demand_avg_miss_latency::total 38439.776043 # average overall miss latency 1037system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34357.228426 # average overall miss latency 1038system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22565.040650 # average overall miss latency 1039system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 45555.981416 # average overall miss latency 1040system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35331.957209 # average overall miss latency 1041system.cpu0.l2cache.overall_avg_miss_latency::total 38439.776043 # average overall miss latency 1042system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 1023system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1043system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1024system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked | 1044system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 1025system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1045system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1026system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked | 1046system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 1027system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1028system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1029system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 1047system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1048system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1049system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 1030system.cpu0.l2cache.writebacks::writebacks 200740 # number of writebacks 1031system.cpu0.l2cache.writebacks::total 200740 # number of writebacks 1032system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 77 # number of ReadReq MSHR hits 1033system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 418 # number of ReadReq MSHR hits 1034system.cpu0.l2cache.ReadReq_mshr_hits::total 495 # number of ReadReq MSHR hits 1035system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3009 # number of ReadExReq MSHR hits 1036system.cpu0.l2cache.ReadExReq_mshr_hits::total 3009 # number of ReadExReq MSHR hits 1037system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 77 # number of demand (read+write) MSHR hits 1038system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3427 # number of demand (read+write) MSHR hits 1039system.cpu0.l2cache.demand_mshr_hits::total 3504 # number of demand (read+write) MSHR hits 1040system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 77 # number of overall MSHR hits 1041system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3427 # number of overall MSHR hits 1042system.cpu0.l2cache.overall_mshr_hits::total 3504 # number of overall MSHR hits 1043system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 892 # number of ReadReq MSHR misses 1044system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 113 # number of ReadReq MSHR misses 1045system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 71209 # number of ReadReq MSHR misses 1046system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 100078 # number of ReadReq MSHR misses 1047system.cpu0.l2cache.ReadReq_mshr_misses::total 172292 # number of ReadReq MSHR misses 1048system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 246246 # number of HardPFReq MSHR misses 1049system.cpu0.l2cache.HardPFReq_mshr_misses::total 246246 # number of HardPFReq MSHR misses 1050system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26801 # number of UpgradeReq MSHR misses 1051system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26801 # number of UpgradeReq MSHR misses 1052system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18444 # number of SCUpgradeReq MSHR misses 1053system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18444 # number of SCUpgradeReq MSHR misses | 1050system.cpu0.l2cache.writebacks::writebacks 196267 # number of writebacks 1051system.cpu0.l2cache.writebacks::total 196267 # number of writebacks 1052system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 50 # number of ReadReq MSHR hits 1053system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 373 # number of ReadReq MSHR hits 1054system.cpu0.l2cache.ReadReq_mshr_hits::total 423 # number of ReadReq MSHR hits 1055system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 2918 # number of ReadExReq MSHR hits 1056system.cpu0.l2cache.ReadExReq_mshr_hits::total 2918 # number of ReadExReq MSHR hits 1057system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 50 # number of demand (read+write) MSHR hits 1058system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3291 # number of demand (read+write) MSHR hits 1059system.cpu0.l2cache.demand_mshr_hits::total 3341 # number of demand (read+write) MSHR hits 1060system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 50 # number of overall MSHR hits 1061system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3291 # number of overall MSHR hits 1062system.cpu0.l2cache.overall_mshr_hits::total 3341 # number of overall MSHR hits 1063system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 788 # number of ReadReq MSHR misses 1064system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 123 # number of ReadReq MSHR misses 1065system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 63770 # number of ReadReq MSHR misses 1066system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 100786 # number of ReadReq MSHR misses 1067system.cpu0.l2cache.ReadReq_mshr_misses::total 165467 # number of ReadReq MSHR misses 1068system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 233242 # number of HardPFReq MSHR misses 1069system.cpu0.l2cache.HardPFReq_mshr_misses::total 233242 # number of HardPFReq MSHR misses 1070system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 28131 # number of UpgradeReq MSHR misses 1071system.cpu0.l2cache.UpgradeReq_mshr_misses::total 28131 # number of UpgradeReq MSHR misses 1072system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19518 # number of SCUpgradeReq MSHR misses 1073system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19518 # number of SCUpgradeReq MSHR misses |
| 1054system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses 1055system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses | 1074system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses 1075system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses |
| 1056system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42315 # number of ReadExReq MSHR misses 1057system.cpu0.l2cache.ReadExReq_mshr_misses::total 42315 # number of ReadExReq MSHR misses 1058system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 892 # number of demand (read+write) MSHR misses 1059system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 113 # number of demand (read+write) MSHR misses 1060system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 71209 # number of demand (read+write) MSHR misses 1061system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142393 # number of demand (read+write) MSHR misses 1062system.cpu0.l2cache.demand_mshr_misses::total 214607 # number of demand (read+write) MSHR misses 1063system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 892 # number of overall MSHR misses 1064system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 113 # number of overall MSHR misses 1065system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 71209 # number of overall MSHR misses 1066system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142393 # number of overall MSHR misses 1067system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 246246 # number of overall MSHR misses 1068system.cpu0.l2cache.overall_mshr_misses::total 460853 # number of overall MSHR misses 1069system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 25830750 # number of ReadReq MSHR miss cycles 1070system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1882000 # number of ReadReq MSHR miss cycles 1071system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2808366569 # number of ReadReq MSHR miss cycles 1072system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2341826150 # number of ReadReq MSHR miss cycles 1073system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 5177905469 # number of ReadReq MSHR miss cycles 1074system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14395344158 # number of HardPFReq MSHR miss cycles 1075system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 14395344158 # number of HardPFReq MSHR miss cycles 1076system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 540640009 # number of UpgradeReq MSHR miss cycles 1077system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 540640009 # number of UpgradeReq MSHR miss cycles 1078system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 270568831 # number of SCUpgradeReq MSHR miss cycles 1079system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 270568831 # number of SCUpgradeReq MSHR miss cycles 1080system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 345999 # number of SCUpgradeFailReq MSHR miss cycles 1081system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 345999 # number of SCUpgradeFailReq MSHR miss cycles 1082system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1615514460 # number of ReadExReq MSHR miss cycles 1083system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1615514460 # number of ReadExReq MSHR miss cycles 1084system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 25830750 # number of demand (read+write) MSHR miss cycles 1085system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1882000 # number of demand (read+write) MSHR miss cycles 1086system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2808366569 # number of demand (read+write) MSHR miss cycles 1087system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3957340610 # number of demand (read+write) MSHR miss cycles 1088system.cpu0.l2cache.demand_mshr_miss_latency::total 6793419929 # number of demand (read+write) MSHR miss cycles 1089system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 25830750 # number of overall MSHR miss cycles 1090system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1882000 # number of overall MSHR miss cycles 1091system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2808366569 # number of overall MSHR miss cycles 1092system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3957340610 # number of overall MSHR miss cycles 1093system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14395344158 # number of overall MSHR miss cycles 1094system.cpu0.l2cache.overall_mshr_miss_latency::total 21188764087 # number of overall MSHR miss cycles 1095system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 283536500 # number of ReadReq MSHR uncacheable cycles 1096system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4113067750 # number of ReadReq MSHR uncacheable cycles 1097system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4396604250 # number of ReadReq MSHR uncacheable cycles 1098system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3117904500 # number of WriteReq MSHR uncacheable cycles 1099system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3117904500 # number of WriteReq MSHR uncacheable cycles 1100system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 283536500 # number of overall MSHR uncacheable cycles 1101system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7230972250 # number of overall MSHR uncacheable cycles 1102system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7514508750 # number of overall MSHR uncacheable cycles 1103system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010905 # mshr miss rate for ReadReq accesses 1104system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.026439 # mshr miss rate for ReadReq accesses 1105system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.036152 # mshr miss rate for ReadReq accesses 1106system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.199716 # mshr miss rate for ReadReq accesses 1107system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.067384 # mshr miss rate for ReadReq accesses | 1076system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40393 # number of ReadExReq MSHR misses 1077system.cpu0.l2cache.ReadExReq_mshr_misses::total 40393 # number of ReadExReq MSHR misses 1078system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 788 # number of demand (read+write) MSHR misses 1079system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 123 # number of demand (read+write) MSHR misses 1080system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 63770 # number of demand (read+write) MSHR misses 1081system.cpu0.l2cache.demand_mshr_misses::cpu0.data 141179 # number of demand (read+write) MSHR misses 1082system.cpu0.l2cache.demand_mshr_misses::total 205860 # number of demand (read+write) MSHR misses 1083system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 788 # number of overall MSHR misses 1084system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 123 # number of overall MSHR misses 1085system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 63770 # number of overall MSHR misses 1086system.cpu0.l2cache.overall_mshr_misses::cpu0.data 141179 # number of overall MSHR misses 1087system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 233242 # number of overall MSHR misses 1088system.cpu0.l2cache.overall_mshr_misses::total 439102 # number of overall MSHR misses 1089system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3367 # number of ReadReq MSHR uncacheable 1090system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29433 # number of ReadReq MSHR uncacheable 1091system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 32800 # number of ReadReq MSHR uncacheable 1092system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 26165 # number of WriteReq MSHR uncacheable 1093system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 26165 # number of WriteReq MSHR uncacheable 1094system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3367 # number of overall MSHR uncacheable misses 1095system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 55598 # number of overall MSHR uncacheable misses 1096system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 58965 # number of overall MSHR uncacheable misses 1097system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 21938500 # number of ReadReq MSHR miss cycles 1098system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1976000 # number of ReadReq MSHR miss cycles 1099system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2484151766 # number of ReadReq MSHR miss cycles 1100system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2249231613 # number of ReadReq MSHR miss cycles 1101system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4757297879 # number of ReadReq MSHR miss cycles 1102system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14218858632 # number of HardPFReq MSHR miss cycles 1103system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 14218858632 # number of HardPFReq MSHR miss cycles 1104system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 550871371 # number of UpgradeReq MSHR miss cycles 1105system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 550871371 # number of UpgradeReq MSHR miss cycles 1106system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 288938194 # number of SCUpgradeReq MSHR miss cycles 1107system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 288938194 # number of SCUpgradeReq MSHR miss cycles 1108system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 466499 # number of SCUpgradeFailReq MSHR miss cycles 1109system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 466499 # number of SCUpgradeFailReq MSHR miss cycles 1110system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1582913137 # number of ReadExReq MSHR miss cycles 1111system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1582913137 # number of ReadExReq MSHR miss cycles 1112system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 21938500 # number of demand (read+write) MSHR miss cycles 1113system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1976000 # number of demand (read+write) MSHR miss cycles 1114system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2484151766 # number of demand (read+write) MSHR miss cycles 1115system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3832144750 # number of demand (read+write) MSHR miss cycles 1116system.cpu0.l2cache.demand_mshr_miss_latency::total 6340211016 # number of demand (read+write) MSHR miss cycles 1117system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 21938500 # number of overall MSHR miss cycles 1118system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1976000 # number of overall MSHR miss cycles 1119system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2484151766 # number of overall MSHR miss cycles 1120system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3832144750 # number of overall MSHR miss cycles 1121system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14218858632 # number of overall MSHR miss cycles 1122system.cpu0.l2cache.overall_mshr_miss_latency::total 20559069648 # number of overall MSHR miss cycles 1123system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 282144500 # number of ReadReq MSHR uncacheable cycles 1124system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5391279750 # number of ReadReq MSHR uncacheable cycles 1125system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5673424250 # number of ReadReq MSHR uncacheable cycles 1126system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4065113000 # number of WriteReq MSHR uncacheable cycles 1127system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4065113000 # number of WriteReq MSHR uncacheable cycles 1128system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 282144500 # number of overall MSHR uncacheable cycles 1129system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9456392750 # number of overall MSHR uncacheable cycles 1130system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9738537250 # number of overall MSHR uncacheable cycles 1131system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010033 # mshr miss rate for ReadReq accesses 1132system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.027480 # mshr miss rate for ReadReq accesses 1133system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.033826 # mshr miss rate for ReadReq accesses 1134system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.211100 # mshr miss rate for ReadReq accesses 1135system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.067656 # mshr miss rate for ReadReq accesses |
| 1108system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1109system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1136system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1137system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1110system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.482875 # mshr miss rate for UpgradeReq accesses 1111system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.482875 # mshr miss rate for UpgradeReq accesses 1112system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.909378 # mshr miss rate for SCUpgradeReq accesses 1113system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.909378 # mshr miss rate for SCUpgradeReq accesses | 1138system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.498538 # mshr miss rate for UpgradeReq accesses 1139system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.498538 # mshr miss rate for UpgradeReq accesses 1140system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.915650 # mshr miss rate for SCUpgradeReq accesses 1141system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.915650 # mshr miss rate for SCUpgradeReq accesses |
| 1114system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1115system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 1142system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1143system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 1116system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.157671 # mshr miss rate for ReadExReq accesses 1117system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.157671 # mshr miss rate for ReadExReq accesses 1118system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010905 # mshr miss rate for demand accesses 1119system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.026439 # mshr miss rate for demand accesses 1120system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036152 # mshr miss rate for demand accesses 1121system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.185051 # mshr miss rate for demand accesses 1122system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075961 # mshr miss rate for demand accesses 1123system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010905 # mshr miss rate for overall accesses 1124system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.026439 # mshr miss rate for overall accesses 1125system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036152 # mshr miss rate for overall accesses 1126system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.185051 # mshr miss rate for overall accesses | 1144system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158018 # mshr miss rate for ReadExReq accesses 1145system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158018 # mshr miss rate for ReadExReq accesses 1146system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010033 # mshr miss rate for demand accesses 1147system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.027480 # mshr miss rate for demand accesses 1148system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.033826 # mshr miss rate for demand accesses 1149system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.192590 # mshr miss rate for demand accesses 1150system.cpu0.l2cache.demand_mshr_miss_rate::total 0.076207 # mshr miss rate for demand accesses 1151system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010033 # mshr miss rate for overall accesses 1152system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.027480 # mshr miss rate for overall accesses 1153system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.033826 # mshr miss rate for overall accesses 1154system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192590 # mshr miss rate for overall accesses |
| 1127system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1155system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1128system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163120 # mshr miss rate for overall accesses 1129system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average ReadReq mshr miss latency 1130system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average ReadReq mshr miss latency 1131system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average ReadReq mshr miss latency 1132system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23400.009493 # average ReadReq mshr miss latency 1133system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30053.081217 # average ReadReq mshr miss latency 1134system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58459.199979 # average HardPFReq mshr miss latency 1135system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58459.199979 # average HardPFReq mshr miss latency 1136system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20172.381963 # average UpgradeReq mshr miss latency 1137system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20172.381963 # average UpgradeReq mshr miss latency 1138system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14669.747940 # average SCUpgradeReq mshr miss latency 1139system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14669.747940 # average SCUpgradeReq mshr miss latency 1140system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 345999 # average SCUpgradeFailReq mshr miss latency 1141system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 345999 # average SCUpgradeFailReq mshr miss latency 1142system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38178.292804 # average ReadExReq mshr miss latency 1143system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38178.292804 # average ReadExReq mshr miss latency 1144system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average overall mshr miss latency 1145system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average overall mshr miss latency 1146system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average overall mshr miss latency 1147system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27791.679436 # average overall mshr miss latency 1148system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31655.164692 # average overall mshr miss latency 1149system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average overall mshr miss latency 1150system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average overall mshr miss latency 1151system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average overall mshr miss latency 1152system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27791.679436 # average overall mshr miss latency 1153system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58459.199979 # average overall mshr miss latency 1154system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45977.272768 # average overall mshr miss latency 1155system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1156system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1157system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1158system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1159system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1160system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1161system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1162system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1156system.cpu0.l2cache.overall_mshr_miss_rate::total 0.162550 # mshr miss rate for overall accesses 1157system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27840.736041 # average ReadReq mshr miss latency 1158system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650 # average ReadReq mshr miss latency 1159system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 38954.865391 # average ReadReq mshr miss latency 1160system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22316.905255 # average ReadReq mshr miss latency 1161system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28750.735065 # average ReadReq mshr miss latency 1162system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60961.827767 # average HardPFReq mshr miss latency 1163system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60961.827767 # average HardPFReq mshr miss latency 1164system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19582.360065 # average UpgradeReq mshr miss latency 1165system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19582.360065 # average UpgradeReq mshr miss latency 1166system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14803.678348 # average SCUpgradeReq mshr miss latency 1167system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14803.678348 # average SCUpgradeReq mshr miss latency 1168system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 466499 # average SCUpgradeFailReq mshr miss latency 1169system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 466499 # average SCUpgradeFailReq mshr miss latency 1170system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39187.808209 # average ReadExReq mshr miss latency 1171system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39187.808209 # average ReadExReq mshr miss latency 1172system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27840.736041 # average overall mshr miss latency 1173system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650 # average overall mshr miss latency 1174system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38954.865391 # average overall mshr miss latency 1175system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27143.872318 # average overall mshr miss latency 1176system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30798.654503 # average overall mshr miss latency 1177system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27840.736041 # average overall mshr miss latency 1178system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650 # average overall mshr miss latency 1179system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38954.865391 # average overall mshr miss latency 1180system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27143.872318 # average overall mshr miss latency 1181system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60961.827767 # average overall mshr miss latency 1182system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46820.715114 # average overall mshr miss latency 1183system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average ReadReq mshr uncacheable latency 1184system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183171.261849 # average ReadReq mshr uncacheable latency 1185system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172970.251524 # average ReadReq mshr uncacheable latency 1186system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155364.532773 # average WriteReq mshr uncacheable latency 1187system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155364.532773 # average WriteReq mshr uncacheable latency 1188system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average overall mshr uncacheable latency 1189system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 170085.124465 # average overall mshr uncacheable latency 1190system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 165157.928432 # average overall mshr uncacheable latency |
| 1163system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1191system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1164system.cpu0.toL2Bus.trans_dist::ReadReq 2703667 # Transaction distribution 1165system.cpu0.toL2Bus.trans_dist::ReadResp 2643606 # Transaction distribution 1166system.cpu0.toL2Bus.trans_dist::WriteReq 19130 # Transaction distribution 1167system.cpu0.toL2Bus.trans_dist::WriteResp 19130 # Transaction distribution 1168system.cpu0.toL2Bus.trans_dist::Writeback 513519 # Transaction distribution 1169system.cpu0.toL2Bus.trans_dist::HardPFReq 304285 # Transaction distribution 1170system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution 1171system.cpu0.toL2Bus.trans_dist::UpgradeReq 88848 # Transaction distribution 1172system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42983 # Transaction distribution 1173system.cpu0.toL2Bus.trans_dist::UpgradeResp 113085 # Transaction distribution 1174system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution 1175system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution 1176system.cpu0.toL2Bus.trans_dist::ReadExReq 297594 # Transaction distribution 1177system.cpu0.toL2Bus.trans_dist::ReadExResp 284124 # Transaction distribution 1178system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3946133 # Packet count per connected master and slave (bytes) 1179system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2385460 # Packet count per connected master and slave (bytes) 1180system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11633 # Packet count per connected master and slave (bytes) 1181system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 174179 # Packet count per connected master and slave (bytes) 1182system.cpu0.toL2Bus.pkt_count::total 6517405 # Packet count per connected master and slave (bytes) 1183system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126276224 # Cumulative packet size per connected master and slave (bytes) 1184system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86385120 # Cumulative packet size per connected master and slave (bytes) 1185system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17096 # Cumulative packet size per connected master and slave (bytes) 1186system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 327200 # Cumulative packet size per connected master and slave (bytes) 1187system.cpu0.toL2Bus.pkt_size::total 213005640 # Cumulative packet size per connected master and slave (bytes) 1188system.cpu0.toL2Bus.snoops 651207 # Total snoops (count) 1189system.cpu0.toL2Bus.snoop_fanout::samples 3963380 # Request fanout histogram 1190system.cpu0.toL2Bus.snoop_fanout::mean 3.135029 # Request fanout histogram 1191system.cpu0.toL2Bus.snoop_fanout::stdev 0.341755 # Request fanout histogram | 1192system.cpu0.toL2Bus.trans_dist::ReadReq 2622296 # Transaction distribution 1193system.cpu0.toL2Bus.trans_dist::ReadResp 2539595 # Transaction distribution 1194system.cpu0.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution 1195system.cpu0.toL2Bus.trans_dist::WriteResp 26165 # Transaction distribution 1196system.cpu0.toL2Bus.trans_dist::Writeback 490181 # Transaction distribution 1197system.cpu0.toL2Bus.trans_dist::HardPFReq 288086 # Transaction distribution 1198system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution 1199system.cpu0.toL2Bus.trans_dist::UpgradeReq 93335 # Transaction distribution 1200system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43761 # Transaction distribution 1201system.cpu0.toL2Bus.trans_dist::UpgradeResp 114801 # Transaction distribution 1202system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution 1203system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution 1204system.cpu0.toL2Bus.trans_dist::ReadExReq 284088 # Transaction distribution 1205system.cpu0.toL2Bus.trans_dist::ReadExResp 269989 # Transaction distribution 1206system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3777247 # Packet count per connected master and slave (bytes) 1207system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2323391 # Packet count per connected master and slave (bytes) 1208system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11902 # Packet count per connected master and slave (bytes) 1209system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 166252 # Packet count per connected master and slave (bytes) 1210system.cpu0.toL2Bus.pkt_count::total 6278792 # Packet count per connected master and slave (bytes) 1211system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 120871872 # Cumulative packet size per connected master and slave (bytes) 1212system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82524675 # Cumulative packet size per connected master and slave (bytes) 1213system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17904 # Cumulative packet size per connected master and slave (bytes) 1214system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314164 # Cumulative packet size per connected master and slave (bytes) 1215system.cpu0.toL2Bus.pkt_size::total 203728615 # Cumulative packet size per connected master and slave (bytes) 1216system.cpu0.toL2Bus.snoops 661406 # Total snoops (count) 1217system.cpu0.toL2Bus.snoop_fanout::samples 3889209 # Request fanout histogram 1218system.cpu0.toL2Bus.snoop_fanout::mean 1.165588 # Request fanout histogram 1219system.cpu0.toL2Bus.snoop_fanout::stdev 0.371711 # Request fanout histogram |
| 1192system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1193system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1220system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1221system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1194system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1195system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1196system.cpu0.toL2Bus.snoop_fanout::3 3428208 86.50% 86.50% # Request fanout histogram 1197system.cpu0.toL2Bus.snoop_fanout::4 535172 13.50% 100.00% # Request fanout histogram | 1222system.cpu0.toL2Bus.snoop_fanout::1 3245202 83.44% 83.44% # Request fanout histogram 1223system.cpu0.toL2Bus.snoop_fanout::2 644007 16.56% 100.00% # Request fanout histogram |
| 1198system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1224system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1199system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1200system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1201system.cpu0.toL2Bus.snoop_fanout::total 3963380 # Request fanout histogram 1202system.cpu0.toL2Bus.reqLayer0.occupancy 2258643996 # Layer occupancy (ticks) | 1225system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1226system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1227system.cpu0.toL2Bus.snoop_fanout::total 3889209 # Request fanout histogram 1228system.cpu0.toL2Bus.reqLayer0.occupancy 2173439238 # Layer occupancy (ticks) |
| 1203system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1229system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1204system.cpu0.toL2Bus.snoopLayer0.occupancy 116241999 # Layer occupancy (ticks) | 1230system.cpu0.toL2Bus.snoopLayer0.occupancy 113551498 # Layer occupancy (ticks) |
| 1205system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1231system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1206system.cpu0.toL2Bus.respLayer0.occupancy 2965047043 # Layer occupancy (ticks) | 1232system.cpu0.toL2Bus.respLayer0.occupancy 2837827806 # Layer occupancy (ticks) |
| 1207system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1233system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1208system.cpu0.toL2Bus.respLayer1.occupancy 1230256203 # Layer occupancy (ticks) | 1234system.cpu0.toL2Bus.respLayer1.occupancy 1188833142 # Layer occupancy (ticks) |
| 1209system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1235system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1210system.cpu0.toL2Bus.respLayer2.occupancy 7364491 # Layer occupancy (ticks) | 1236system.cpu0.toL2Bus.respLayer2.occupancy 7429994 # Layer occupancy (ticks) |
| 1211system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1237system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1212system.cpu0.toL2Bus.respLayer3.occupancy 92392742 # Layer occupancy (ticks) | 1238system.cpu0.toL2Bus.respLayer3.occupancy 87720745 # Layer occupancy (ticks) |
| 1213system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1239system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1214system.cpu1.branchPred.lookups 18842889 # Number of BP lookups 1215system.cpu1.branchPred.condPredicted 6205402 # Number of conditional branches predicted 1216system.cpu1.branchPred.condIncorrect 629106 # Number of conditional branches incorrect 1217system.cpu1.branchPred.BTBLookups 9920552 # Number of BTB lookups 1218system.cpu1.branchPred.BTBHits 7177439 # Number of BTB hits | 1240system.cpu1.branchPred.lookups 5430284 # Number of BP lookups 1241system.cpu1.branchPred.condPredicted 3355584 # Number of conditional branches predicted 1242system.cpu1.branchPred.condIncorrect 331008 # Number of conditional branches incorrect 1243system.cpu1.branchPred.BTBLookups 3397877 # Number of BTB lookups 1244system.cpu1.branchPred.BTBHits 2268406 # Number of BTB hits |
| 1219system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1245system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1220system.cpu1.branchPred.BTBHitPct 72.349190 # BTB Hit Percentage 1221system.cpu1.branchPred.usedRAS 8245946 # Number of times the RAS was used to get a target. 1222system.cpu1.branchPred.RASInCorrect 413041 # Number of incorrect RAS predictions. | 1246system.cpu1.branchPred.BTBHitPct 66.759509 # BTB Hit Percentage 1247system.cpu1.branchPred.usedRAS 972543 # Number of times the RAS was used to get a target. 1248system.cpu1.branchPred.RASInCorrect 68492 # Number of incorrect RAS predictions. |
| 1223system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1224system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1225system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1226system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1227system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1228system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1229system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1230system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1244system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1245system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1246system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1247system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1248system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1249system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1250system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1251system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1249system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1250system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1251system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1252system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1253system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1254system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1255system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1256system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1270system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1271system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1272system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1273system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1274system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1275system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1276system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1277system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1252system.cpu1.dtb.walker.walks 26188 # Table walker walks requested 1253system.cpu1.dtb.walker.walksShort 26188 # Table walker walks initiated with short descriptors 1254system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19132 # Level at which table walker walks with short descriptors terminate 1255system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7056 # Level at which table walker walks with short descriptors terminate 1256system.cpu1.dtb.walker.walkWaitTime::samples 26188 # Table walker wait (enqueue to first request) latency 1257system.cpu1.dtb.walker.walkWaitTime::0 26188 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1258system.cpu1.dtb.walker.walkWaitTime::total 26188 # Table walker wait (enqueue to first request) latency 1259system.cpu1.dtb.walker.walkCompletionTime::samples 2719 # Table walker service (enqueue to completion) latency 1260system.cpu1.dtb.walker.walkCompletionTime::mean 9780.159618 # Table walker service (enqueue to completion) latency 1261system.cpu1.dtb.walker.walkCompletionTime::gmean 8826.212048 # Table walker service (enqueue to completion) latency 1262system.cpu1.dtb.walker.walkCompletionTime::stdev 5631.617808 # Table walker service (enqueue to completion) latency 1263system.cpu1.dtb.walker.walkCompletionTime::0-8191 919 33.80% 33.80% # Table walker service (enqueue to completion) latency 1264system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1662 61.13% 94.92% # Table walker service (enqueue to completion) latency 1265system.cpu1.dtb.walker.walkCompletionTime::16384-24575 68 2.50% 97.43% # Table walker service (enqueue to completion) latency 1266system.cpu1.dtb.walker.walkCompletionTime::24576-32767 62 2.28% 99.71% # Table walker service (enqueue to completion) latency 1267system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.78% # Table walker service (enqueue to completion) latency 1268system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.11% 99.89% # Table walker service (enqueue to completion) latency 1269system.cpu1.dtb.walker.walkCompletionTime::90112-98303 2 0.07% 99.96% # Table walker service (enqueue to completion) latency 1270system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 1271system.cpu1.dtb.walker.walkCompletionTime::total 2719 # Table walker service (enqueue to completion) latency 1272system.cpu1.dtb.walker.walksPending::samples 1631340764 # Table walker pending requests distribution 1273system.cpu1.dtb.walker.walksPending::0 1631340764 100.00% 100.00% # Table walker pending requests distribution 1274system.cpu1.dtb.walker.walksPending::total 1631340764 # Table walker pending requests distribution 1275system.cpu1.dtb.walker.walkPageSizes::4K 2011 73.96% 73.96% # Table walker page sizes translated 1276system.cpu1.dtb.walker.walkPageSizes::1M 708 26.04% 100.00% # Table walker page sizes translated 1277system.cpu1.dtb.walker.walkPageSizes::total 2719 # Table walker page sizes translated 1278system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26188 # Table walker requests started/completed, data/inst | 1278system.cpu1.dtb.walker.walks 30040 # Table walker walks requested 1279system.cpu1.dtb.walker.walksShort 30040 # Table walker walks initiated with short descriptors 1280system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 22353 # Level at which table walker walks with short descriptors terminate 1281system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7687 # Level at which table walker walks with short descriptors terminate 1282system.cpu1.dtb.walker.walkWaitTime::samples 30040 # Table walker wait (enqueue to first request) latency 1283system.cpu1.dtb.walker.walkWaitTime::0 30040 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1284system.cpu1.dtb.walker.walkWaitTime::total 30040 # Table walker wait (enqueue to first request) latency 1285system.cpu1.dtb.walker.walkCompletionTime::samples 2702 # Table walker service (enqueue to completion) latency 1286system.cpu1.dtb.walker.walkCompletionTime::mean 9799.871947 # Table walker service (enqueue to completion) latency 1287system.cpu1.dtb.walker.walkCompletionTime::gmean 8761.915074 # Table walker service (enqueue to completion) latency 1288system.cpu1.dtb.walker.walkCompletionTime::stdev 6575.386381 # Table walker service (enqueue to completion) latency 1289system.cpu1.dtb.walker.walkCompletionTime::0-8191 913 33.79% 33.79% # Table walker service (enqueue to completion) latency 1290system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1652 61.14% 94.93% # Table walker service (enqueue to completion) latency 1291system.cpu1.dtb.walker.walkCompletionTime::16384-24575 67 2.48% 97.41% # Table walker service (enqueue to completion) latency 1292system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.07% 99.48% # Table walker service (enqueue to completion) latency 1293system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.56% # Table walker service (enqueue to completion) latency 1294system.cpu1.dtb.walker.walkCompletionTime::40960-49151 5 0.19% 99.74% # Table walker service (enqueue to completion) latency 1295system.cpu1.dtb.walker.walkCompletionTime::90112-98303 6 0.22% 99.96% # Table walker service (enqueue to completion) latency 1296system.cpu1.dtb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 1297system.cpu1.dtb.walker.walkCompletionTime::total 2702 # Table walker service (enqueue to completion) latency 1298system.cpu1.dtb.walker.walksPending::samples 1622459264 # Table walker pending requests distribution 1299system.cpu1.dtb.walker.walksPending::0 1622459264 100.00% 100.00% # Table walker pending requests distribution 1300system.cpu1.dtb.walker.walksPending::total 1622459264 # Table walker pending requests distribution 1301system.cpu1.dtb.walker.walkPageSizes::4K 2019 74.72% 74.72% # Table walker page sizes translated 1302system.cpu1.dtb.walker.walkPageSizes::1M 683 25.28% 100.00% # Table walker page sizes translated 1303system.cpu1.dtb.walker.walkPageSizes::total 2702 # Table walker page sizes translated 1304system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30040 # Table walker requests started/completed, data/inst |
| 1279system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 1305system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 1280system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26188 # Table walker requests started/completed, data/inst 1281system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2719 # Table walker requests started/completed, data/inst | 1306system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30040 # Table walker requests started/completed, data/inst 1307system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2702 # Table walker requests started/completed, data/inst |
| 1282system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 1308system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 1283system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2719 # Table walker requests started/completed, data/inst 1284system.cpu1.dtb.walker.walkRequestOrigin::total 28907 # Table walker requests started/completed, data/inst | 1309system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2702 # Table walker requests started/completed, data/inst 1310system.cpu1.dtb.walker.walkRequestOrigin::total 32742 # Table walker requests started/completed, data/inst |
| 1285system.cpu1.dtb.inst_hits 0 # ITB inst hits 1286system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1311system.cpu1.dtb.inst_hits 0 # ITB inst hits 1312system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1287system.cpu1.dtb.read_hits 11112548 # DTB read hits 1288system.cpu1.dtb.read_misses 24192 # DTB read misses 1289system.cpu1.dtb.write_hits 6961122 # DTB write hits 1290system.cpu1.dtb.write_misses 1996 # DTB write misses | 1313system.cpu1.dtb.read_hits 5155380 # DTB read hits 1314system.cpu1.dtb.read_misses 27847 # DTB read misses 1315system.cpu1.dtb.write_hits 4232538 # DTB write hits 1316system.cpu1.dtb.write_misses 2193 # DTB write misses |
| 1291system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1292system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1293system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1294system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1317system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1318system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1319system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1320system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1295system.cpu1.dtb.flush_entries 2061 # Number of entries that have been flushed from TLB 1296system.cpu1.dtb.align_faults 148 # Number of TLB faults due to alignment restrictions 1297system.cpu1.dtb.prefetch_faults 422 # Number of TLB faults due to prefetch | 1321system.cpu1.dtb.flush_entries 2049 # Number of entries that have been flushed from TLB 1322system.cpu1.dtb.align_faults 312 # Number of TLB faults due to alignment restrictions 1323system.cpu1.dtb.prefetch_faults 511 # Number of TLB faults due to prefetch |
| 1298system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1324system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1299system.cpu1.dtb.perms_faults 278 # Number of TLB faults due to permissions restrictions 1300system.cpu1.dtb.read_accesses 11136740 # DTB read accesses 1301system.cpu1.dtb.write_accesses 6963118 # DTB write accesses | 1325system.cpu1.dtb.perms_faults 285 # Number of TLB faults due to permissions restrictions 1326system.cpu1.dtb.read_accesses 5183227 # DTB read accesses 1327system.cpu1.dtb.write_accesses 4234731 # DTB write accesses |
| 1302system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1328system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1303system.cpu1.dtb.hits 18073670 # DTB hits 1304system.cpu1.dtb.misses 26188 # DTB misses 1305system.cpu1.dtb.accesses 18099858 # DTB accesses | 1329system.cpu1.dtb.hits 9387918 # DTB hits 1330system.cpu1.dtb.misses 30040 # DTB misses 1331system.cpu1.dtb.accesses 9417958 # DTB accesses |
| 1306system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1307system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1308system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1309system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1310system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1311system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1312system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1313system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1327system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1328system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1329system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1330system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1331system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1332system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1333system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1334system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1332system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1333system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1334system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1335system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1336system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1337system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1338system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1339system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1353system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1354system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1355system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1356system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1357system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1358system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1359system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1360system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1335system.cpu1.itb.walker.walks 2252 # Table walker walks requested 1336system.cpu1.itb.walker.walksShort 2252 # Table walker walks initiated with short descriptors 1337system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate 1338system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2071 # Level at which table walker walks with short descriptors terminate 1339system.cpu1.itb.walker.walkWaitTime::samples 2252 # Table walker wait (enqueue to first request) latency 1340system.cpu1.itb.walker.walkWaitTime::0 2252 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1341system.cpu1.itb.walker.walkWaitTime::total 2252 # Table walker wait (enqueue to first request) latency 1342system.cpu1.itb.walker.walkCompletionTime::samples 1119 # Table walker service (enqueue to completion) latency 1343system.cpu1.itb.walker.walkCompletionTime::mean 9763.181412 # Table walker service (enqueue to completion) latency 1344system.cpu1.itb.walker.walkCompletionTime::gmean 8935.720507 # Table walker service (enqueue to completion) latency 1345system.cpu1.itb.walker.walkCompletionTime::stdev 4528.605471 # Table walker service (enqueue to completion) latency 1346system.cpu1.itb.walker.walkCompletionTime::0-4095 139 12.42% 12.42% # Table walker service (enqueue to completion) latency 1347system.cpu1.itb.walker.walkCompletionTime::4096-8191 170 15.19% 27.61% # Table walker service (enqueue to completion) latency 1348system.cpu1.itb.walker.walkCompletionTime::8192-12287 525 46.92% 74.53% # Table walker service (enqueue to completion) latency 1349system.cpu1.itb.walker.walkCompletionTime::12288-16383 253 22.61% 97.14% # Table walker service (enqueue to completion) latency 1350system.cpu1.itb.walker.walkCompletionTime::16384-20479 2 0.18% 97.32% # Table walker service (enqueue to completion) latency 1351system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 1.88% 99.20% # Table walker service (enqueue to completion) latency 1352system.cpu1.itb.walker.walkCompletionTime::28672-32767 7 0.63% 99.82% # Table walker service (enqueue to completion) latency 1353system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 100.00% # Table walker service (enqueue to completion) latency 1354system.cpu1.itb.walker.walkCompletionTime::total 1119 # Table walker service (enqueue to completion) latency 1355system.cpu1.itb.walker.walksPending::samples 1630766264 # Table walker pending requests distribution 1356system.cpu1.itb.walker.walksPending::0 1630766264 100.00% 100.00% # Table walker pending requests distribution 1357system.cpu1.itb.walker.walksPending::total 1630766264 # Table walker pending requests distribution 1358system.cpu1.itb.walker.walkPageSizes::4K 951 84.99% 84.99% # Table walker page sizes translated 1359system.cpu1.itb.walker.walkPageSizes::1M 168 15.01% 100.00% # Table walker page sizes translated 1360system.cpu1.itb.walker.walkPageSizes::total 1119 # Table walker page sizes translated | 1361system.cpu1.itb.walker.walks 2268 # Table walker walks requested 1362system.cpu1.itb.walker.walksShort 2268 # Table walker walks initiated with short descriptors 1363system.cpu1.itb.walker.walksShortTerminationLevel::Level1 178 # Level at which table walker walks with short descriptors terminate 1364system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2090 # Level at which table walker walks with short descriptors terminate 1365system.cpu1.itb.walker.walkWaitTime::samples 2268 # Table walker wait (enqueue to first request) latency 1366system.cpu1.itb.walker.walkWaitTime::0 2268 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1367system.cpu1.itb.walker.walkWaitTime::total 2268 # Table walker wait (enqueue to first request) latency 1368system.cpu1.itb.walker.walkCompletionTime::samples 1115 # Table walker service (enqueue to completion) latency 1369system.cpu1.itb.walker.walkCompletionTime::mean 9869.507623 # Table walker service (enqueue to completion) latency 1370system.cpu1.itb.walker.walkCompletionTime::gmean 8954.185655 # Table walker service (enqueue to completion) latency 1371system.cpu1.itb.walker.walkCompletionTime::stdev 5421.941384 # Table walker service (enqueue to completion) latency 1372system.cpu1.itb.walker.walkCompletionTime::0-8191 302 27.09% 27.09% # Table walker service (enqueue to completion) latency 1373system.cpu1.itb.walker.walkCompletionTime::8192-16383 778 69.78% 96.86% # Table walker service (enqueue to completion) latency 1374system.cpu1.itb.walker.walkCompletionTime::16384-24575 3 0.27% 97.13% # Table walker service (enqueue to completion) latency 1375system.cpu1.itb.walker.walkCompletionTime::24576-32767 27 2.42% 99.55% # Table walker service (enqueue to completion) latency 1376system.cpu1.itb.walker.walkCompletionTime::32768-40959 1 0.09% 99.64% # Table walker service (enqueue to completion) latency 1377system.cpu1.itb.walker.walkCompletionTime::40960-49151 3 0.27% 99.91% # Table walker service (enqueue to completion) latency 1378system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.09% 100.00% # Table walker service (enqueue to completion) latency 1379system.cpu1.itb.walker.walkCompletionTime::total 1115 # Table walker service (enqueue to completion) latency 1380system.cpu1.itb.walker.walksPending::samples 1621868264 # Table walker pending requests distribution 1381system.cpu1.itb.walker.walksPending::0 1621868264 100.00% 100.00% # Table walker pending requests distribution 1382system.cpu1.itb.walker.walksPending::total 1621868264 # Table walker pending requests distribution 1383system.cpu1.itb.walker.walkPageSizes::4K 950 85.20% 85.20% # Table walker page sizes translated 1384system.cpu1.itb.walker.walkPageSizes::1M 165 14.80% 100.00% # Table walker page sizes translated 1385system.cpu1.itb.walker.walkPageSizes::total 1115 # Table walker page sizes translated |
| 1361system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 1386system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 1362system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2252 # Table walker requests started/completed, data/inst 1363system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2252 # Table walker requests started/completed, data/inst | 1387system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2268 # Table walker requests started/completed, data/inst 1388system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2268 # Table walker requests started/completed, data/inst |
| 1364system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 1389system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 1365system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1119 # Table walker requests started/completed, data/inst 1366system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1119 # Table walker requests started/completed, data/inst 1367system.cpu1.itb.walker.walkRequestOrigin::total 3371 # Table walker requests started/completed, data/inst 1368system.cpu1.itb.inst_hits 39781680 # ITB inst hits 1369system.cpu1.itb.inst_misses 2252 # ITB inst misses | 1390system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1115 # Table walker requests started/completed, data/inst 1391system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1115 # Table walker requests started/completed, data/inst 1392system.cpu1.itb.walker.walkRequestOrigin::total 3383 # Table walker requests started/completed, data/inst 1393system.cpu1.itb.inst_hits 10199097 # ITB inst hits 1394system.cpu1.itb.inst_misses 2268 # ITB inst misses |
| 1370system.cpu1.itb.read_hits 0 # DTB read hits 1371system.cpu1.itb.read_misses 0 # DTB read misses 1372system.cpu1.itb.write_hits 0 # DTB write hits 1373system.cpu1.itb.write_misses 0 # DTB write misses 1374system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1375system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1376system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1377system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1395system.cpu1.itb.read_hits 0 # DTB read hits 1396system.cpu1.itb.read_misses 0 # DTB read misses 1397system.cpu1.itb.write_hits 0 # DTB write hits 1398system.cpu1.itb.write_misses 0 # DTB write misses 1399system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1400system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1401system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1402system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1378system.cpu1.itb.flush_entries 1157 # Number of entries that have been flushed from TLB | 1403system.cpu1.itb.flush_entries 1153 # Number of entries that have been flushed from TLB |
| 1379system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1380system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1381system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1404system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1405system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1406system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1382system.cpu1.itb.perms_faults 1899 # Number of TLB faults due to permissions restrictions | 1407system.cpu1.itb.perms_faults 1907 # Number of TLB faults due to permissions restrictions |
| 1383system.cpu1.itb.read_accesses 0 # DTB read accesses 1384system.cpu1.itb.write_accesses 0 # DTB write accesses | 1408system.cpu1.itb.read_accesses 0 # DTB read accesses 1409system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1385system.cpu1.itb.inst_accesses 39783932 # ITB inst accesses 1386system.cpu1.itb.hits 39781680 # DTB hits 1387system.cpu1.itb.misses 2252 # DTB misses 1388system.cpu1.itb.accesses 39783932 # DTB accesses 1389system.cpu1.numCycles 114623988 # number of cpu cycles simulated | 1410system.cpu1.itb.inst_accesses 10201365 # ITB inst accesses 1411system.cpu1.itb.hits 10199097 # DTB hits 1412system.cpu1.itb.misses 2268 # DTB misses 1413system.cpu1.itb.accesses 10201365 # DTB accesses 1414system.cpu1.numCycles 54377537 # number of cpu cycles simulated |
| 1390system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1391system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1415system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1416system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1392system.cpu1.committedInsts 47285235 # Number of instructions committed 1393system.cpu1.committedOps 57859006 # Number of ops (including micro ops) committed 1394system.cpu1.discardedOps 5005620 # Number of ops (including micro ops) which were discarded before commit 1395system.cpu1.numFetchSuspends 2776 # Number of times Execute suspended instruction fetching 1396system.cpu1.quiesceCycles 5576963738 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1397system.cpu1.cpi 2.424097 # CPI: cycles per instruction 1398system.cpu1.ipc 0.412525 # IPC: instructions per cycle | 1417system.cpu1.committedInsts 20871299 # Number of instructions committed 1418system.cpu1.committedOps 25485301 # Number of ops (including micro ops) committed 1419system.cpu1.discardedOps 1815368 # Number of ops (including micro ops) which were discarded before commit 1420system.cpu1.numFetchSuspends 2715 # Number of times Execute suspended instruction fetching 1421system.cpu1.quiesceCycles 5637293692 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1422system.cpu1.cpi 2.605374 # CPI: cycles per instruction 1423system.cpu1.ipc 0.383822 # IPC: instructions per cycle |
| 1399system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1424system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1400system.cpu1.kern.inst.quiesce 2776 # number of quiesce instructions executed 1401system.cpu1.tickCycles 97884766 # Number of cycles that the object actually ticked 1402system.cpu1.idleCycles 16739222 # Total number of cycles that the object has spent stopped 1403system.cpu1.dcache.tags.replacements 194739 # number of replacements 1404system.cpu1.dcache.tags.tagsinuse 472.948438 # Cycle average of tags in use 1405system.cpu1.dcache.tags.total_refs 17633406 # Total number of references to valid blocks. 1406system.cpu1.dcache.tags.sampled_refs 195100 # Sample count of references to valid blocks. 1407system.cpu1.dcache.tags.avg_refs 90.381374 # Average number of references to valid blocks. 1408system.cpu1.dcache.tags.warmup_cycle 90504077500 # Cycle when the warmup percentage was hit. 1409system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.948438 # Average occupied blocks per requestor 1410system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923727 # Average percentage of cache occupancy 1411system.cpu1.dcache.tags.occ_percent::total 0.923727 # Average percentage of cache occupancy 1412system.cpu1.dcache.tags.occ_task_id_blocks::1024 361 # Occupied blocks per task id 1413system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id 1414system.cpu1.dcache.tags.age_task_id_blocks_1024::3 55 # Occupied blocks per task id 1415system.cpu1.dcache.tags.occ_task_id_percent::1024 0.705078 # Percentage of cache occupancy per task id 1416system.cpu1.dcache.tags.tag_accesses 36178407 # Number of tag accesses 1417system.cpu1.dcache.tags.data_accesses 36178407 # Number of data accesses 1418system.cpu1.dcache.ReadReq_hits::cpu1.data 10725883 # number of ReadReq hits 1419system.cpu1.dcache.ReadReq_hits::total 10725883 # number of ReadReq hits 1420system.cpu1.dcache.WriteReq_hits::cpu1.data 6668052 # number of WriteReq hits 1421system.cpu1.dcache.WriteReq_hits::total 6668052 # number of WriteReq hits 1422system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49984 # number of SoftPFReq hits 1423system.cpu1.dcache.SoftPFReq_hits::total 49984 # number of SoftPFReq hits 1424system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80051 # number of LoadLockedReq hits 1425system.cpu1.dcache.LoadLockedReq_hits::total 80051 # number of LoadLockedReq hits 1426system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71499 # number of StoreCondReq hits 1427system.cpu1.dcache.StoreCondReq_hits::total 71499 # number of StoreCondReq hits 1428system.cpu1.dcache.demand_hits::cpu1.data 17393935 # number of demand (read+write) hits 1429system.cpu1.dcache.demand_hits::total 17393935 # number of demand (read+write) hits 1430system.cpu1.dcache.overall_hits::cpu1.data 17443919 # number of overall hits 1431system.cpu1.dcache.overall_hits::total 17443919 # number of overall hits 1432system.cpu1.dcache.ReadReq_misses::cpu1.data 157968 # number of ReadReq misses 1433system.cpu1.dcache.ReadReq_misses::total 157968 # number of ReadReq misses 1434system.cpu1.dcache.WriteReq_misses::cpu1.data 144726 # number of WriteReq misses 1435system.cpu1.dcache.WriteReq_misses::total 144726 # number of WriteReq misses 1436system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30816 # number of SoftPFReq misses 1437system.cpu1.dcache.SoftPFReq_misses::total 30816 # number of SoftPFReq misses 1438system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16919 # number of LoadLockedReq misses 1439system.cpu1.dcache.LoadLockedReq_misses::total 16919 # number of LoadLockedReq misses 1440system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23678 # number of StoreCondReq misses 1441system.cpu1.dcache.StoreCondReq_misses::total 23678 # number of StoreCondReq misses 1442system.cpu1.dcache.demand_misses::cpu1.data 302694 # number of demand (read+write) misses 1443system.cpu1.dcache.demand_misses::total 302694 # number of demand (read+write) misses 1444system.cpu1.dcache.overall_misses::cpu1.data 333510 # number of overall misses 1445system.cpu1.dcache.overall_misses::total 333510 # number of overall misses 1446system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2315952429 # number of ReadReq miss cycles 1447system.cpu1.dcache.ReadReq_miss_latency::total 2315952429 # number of ReadReq miss cycles 1448system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3861386324 # number of WriteReq miss cycles 1449system.cpu1.dcache.WriteReq_miss_latency::total 3861386324 # number of WriteReq miss cycles 1450system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 316030492 # number of LoadLockedReq miss cycles 1451system.cpu1.dcache.LoadLockedReq_miss_latency::total 316030492 # number of LoadLockedReq miss cycles 1452system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557062155 # number of StoreCondReq miss cycles 1453system.cpu1.dcache.StoreCondReq_miss_latency::total 557062155 # number of StoreCondReq miss cycles 1454system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 124000 # number of StoreCondFailReq miss cycles 1455system.cpu1.dcache.StoreCondFailReq_miss_latency::total 124000 # number of StoreCondFailReq miss cycles 1456system.cpu1.dcache.demand_miss_latency::cpu1.data 6177338753 # number of demand (read+write) miss cycles 1457system.cpu1.dcache.demand_miss_latency::total 6177338753 # number of demand (read+write) miss cycles 1458system.cpu1.dcache.overall_miss_latency::cpu1.data 6177338753 # number of overall miss cycles 1459system.cpu1.dcache.overall_miss_latency::total 6177338753 # number of overall miss cycles 1460system.cpu1.dcache.ReadReq_accesses::cpu1.data 10883851 # number of ReadReq accesses(hits+misses) 1461system.cpu1.dcache.ReadReq_accesses::total 10883851 # number of ReadReq accesses(hits+misses) 1462system.cpu1.dcache.WriteReq_accesses::cpu1.data 6812778 # number of WriteReq accesses(hits+misses) 1463system.cpu1.dcache.WriteReq_accesses::total 6812778 # number of WriteReq accesses(hits+misses) 1464system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80800 # number of SoftPFReq accesses(hits+misses) 1465system.cpu1.dcache.SoftPFReq_accesses::total 80800 # number of SoftPFReq accesses(hits+misses) 1466system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96970 # number of LoadLockedReq accesses(hits+misses) 1467system.cpu1.dcache.LoadLockedReq_accesses::total 96970 # number of LoadLockedReq accesses(hits+misses) 1468system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95177 # number of StoreCondReq accesses(hits+misses) 1469system.cpu1.dcache.StoreCondReq_accesses::total 95177 # number of StoreCondReq accesses(hits+misses) 1470system.cpu1.dcache.demand_accesses::cpu1.data 17696629 # number of demand (read+write) accesses 1471system.cpu1.dcache.demand_accesses::total 17696629 # number of demand (read+write) accesses 1472system.cpu1.dcache.overall_accesses::cpu1.data 17777429 # number of overall (read+write) accesses 1473system.cpu1.dcache.overall_accesses::total 17777429 # number of overall (read+write) accesses 1474system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.014514 # miss rate for ReadReq accesses 1475system.cpu1.dcache.ReadReq_miss_rate::total 0.014514 # miss rate for ReadReq accesses 1476system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021243 # miss rate for WriteReq accesses 1477system.cpu1.dcache.WriteReq_miss_rate::total 0.021243 # miss rate for WriteReq accesses 1478system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381386 # miss rate for SoftPFReq accesses 1479system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381386 # miss rate for SoftPFReq accesses 1480system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174477 # miss rate for LoadLockedReq accesses 1481system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174477 # miss rate for LoadLockedReq accesses 1482system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248779 # miss rate for StoreCondReq accesses 1483system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248779 # miss rate for StoreCondReq accesses 1484system.cpu1.dcache.demand_miss_rate::cpu1.data 0.017105 # miss rate for demand accesses 1485system.cpu1.dcache.demand_miss_rate::total 0.017105 # miss rate for demand accesses 1486system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018760 # miss rate for overall accesses 1487system.cpu1.dcache.overall_miss_rate::total 0.018760 # miss rate for overall accesses 1488system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14660.896061 # average ReadReq miss latency 1489system.cpu1.dcache.ReadReq_avg_miss_latency::total 14660.896061 # average ReadReq miss latency 1490system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26680.667772 # average WriteReq miss latency 1491system.cpu1.dcache.WriteReq_avg_miss_latency::total 26680.667772 # average WriteReq miss latency 1492system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18679.029021 # average LoadLockedReq miss latency 1493system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18679.029021 # average LoadLockedReq miss latency 1494system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23526.571290 # average StoreCondReq miss latency 1495system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23526.571290 # average StoreCondReq miss latency | 1425system.cpu1.kern.inst.quiesce 2716 # number of quiesce instructions executed 1426system.cpu1.tickCycles 38719894 # Number of cycles that the object actually ticked 1427system.cpu1.idleCycles 15657643 # Total number of cycles that the object has spent stopped 1428system.cpu1.dcache.tags.replacements 231595 # number of replacements 1429system.cpu1.dcache.tags.tagsinuse 482.666397 # Cycle average of tags in use 1430system.cpu1.dcache.tags.total_refs 8898721 # Total number of references to valid blocks. 1431system.cpu1.dcache.tags.sampled_refs 231963 # Sample count of references to valid blocks. 1432system.cpu1.dcache.tags.avg_refs 38.362674 # Average number of references to valid blocks. 1433system.cpu1.dcache.tags.warmup_cycle 90493998000 # Cycle when the warmup percentage was hit. 1434system.cpu1.dcache.tags.occ_blocks::cpu1.data 482.666397 # Average occupied blocks per requestor 1435system.cpu1.dcache.tags.occ_percent::cpu1.data 0.942708 # Average percentage of cache occupancy 1436system.cpu1.dcache.tags.occ_percent::total 0.942708 # Average percentage of cache occupancy 1437system.cpu1.dcache.tags.occ_task_id_blocks::1024 368 # Occupied blocks per task id 1438system.cpu1.dcache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id 1439system.cpu1.dcache.tags.age_task_id_blocks_1024::3 53 # Occupied blocks per task id 1440system.cpu1.dcache.tags.occ_task_id_percent::1024 0.718750 # Percentage of cache occupancy per task id 1441system.cpu1.dcache.tags.tag_accesses 18845353 # Number of tag accesses 1442system.cpu1.dcache.tags.data_accesses 18845353 # Number of data accesses 1443system.cpu1.dcache.ReadReq_hits::cpu1.data 4715534 # number of ReadReq hits 1444system.cpu1.dcache.ReadReq_hits::total 4715534 # number of ReadReq hits 1445system.cpu1.dcache.WriteReq_hits::cpu1.data 3905905 # number of WriteReq hits 1446system.cpu1.dcache.WriteReq_hits::total 3905905 # number of WriteReq hits 1447system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65439 # number of SoftPFReq hits 1448system.cpu1.dcache.SoftPFReq_hits::total 65439 # number of SoftPFReq hits 1449system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88128 # number of LoadLockedReq hits 1450system.cpu1.dcache.LoadLockedReq_hits::total 88128 # number of LoadLockedReq hits 1451system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80091 # number of StoreCondReq hits 1452system.cpu1.dcache.StoreCondReq_hits::total 80091 # number of StoreCondReq hits 1453system.cpu1.dcache.demand_hits::cpu1.data 8621439 # number of demand (read+write) hits 1454system.cpu1.dcache.demand_hits::total 8621439 # number of demand (read+write) hits 1455system.cpu1.dcache.overall_hits::cpu1.data 8686878 # number of overall hits 1456system.cpu1.dcache.overall_hits::total 8686878 # number of overall hits 1457system.cpu1.dcache.ReadReq_misses::cpu1.data 182965 # number of ReadReq misses 1458system.cpu1.dcache.ReadReq_misses::total 182965 # number of ReadReq misses 1459system.cpu1.dcache.WriteReq_misses::cpu1.data 168408 # number of WriteReq misses 1460system.cpu1.dcache.WriteReq_misses::total 168408 # number of WriteReq misses 1461system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35586 # number of SoftPFReq misses 1462system.cpu1.dcache.SoftPFReq_misses::total 35586 # number of SoftPFReq misses 1463system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17713 # number of LoadLockedReq misses 1464system.cpu1.dcache.LoadLockedReq_misses::total 17713 # number of LoadLockedReq misses 1465system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23494 # number of StoreCondReq misses 1466system.cpu1.dcache.StoreCondReq_misses::total 23494 # number of StoreCondReq misses 1467system.cpu1.dcache.demand_misses::cpu1.data 351373 # number of demand (read+write) misses 1468system.cpu1.dcache.demand_misses::total 351373 # number of demand (read+write) misses 1469system.cpu1.dcache.overall_misses::cpu1.data 386959 # number of overall misses 1470system.cpu1.dcache.overall_misses::total 386959 # number of overall misses 1471system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2670008756 # number of ReadReq miss cycles 1472system.cpu1.dcache.ReadReq_miss_latency::total 2670008756 # number of ReadReq miss cycles 1473system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4196907972 # number of WriteReq miss cycles 1474system.cpu1.dcache.WriteReq_miss_latency::total 4196907972 # number of WriteReq miss cycles 1475system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325609985 # number of LoadLockedReq miss cycles 1476system.cpu1.dcache.LoadLockedReq_miss_latency::total 325609985 # number of LoadLockedReq miss cycles 1477system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 550485715 # number of StoreCondReq miss cycles 1478system.cpu1.dcache.StoreCondReq_miss_latency::total 550485715 # number of StoreCondReq miss cycles 1479system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 359500 # number of StoreCondFailReq miss cycles 1480system.cpu1.dcache.StoreCondFailReq_miss_latency::total 359500 # number of StoreCondFailReq miss cycles 1481system.cpu1.dcache.demand_miss_latency::cpu1.data 6866916728 # number of demand (read+write) miss cycles 1482system.cpu1.dcache.demand_miss_latency::total 6866916728 # number of demand (read+write) miss cycles 1483system.cpu1.dcache.overall_miss_latency::cpu1.data 6866916728 # number of overall miss cycles 1484system.cpu1.dcache.overall_miss_latency::total 6866916728 # number of overall miss cycles 1485system.cpu1.dcache.ReadReq_accesses::cpu1.data 4898499 # number of ReadReq accesses(hits+misses) 1486system.cpu1.dcache.ReadReq_accesses::total 4898499 # number of ReadReq accesses(hits+misses) 1487system.cpu1.dcache.WriteReq_accesses::cpu1.data 4074313 # number of WriteReq accesses(hits+misses) 1488system.cpu1.dcache.WriteReq_accesses::total 4074313 # number of WriteReq accesses(hits+misses) 1489system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 101025 # number of SoftPFReq accesses(hits+misses) 1490system.cpu1.dcache.SoftPFReq_accesses::total 101025 # number of SoftPFReq accesses(hits+misses) 1491system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105841 # number of LoadLockedReq accesses(hits+misses) 1492system.cpu1.dcache.LoadLockedReq_accesses::total 105841 # number of LoadLockedReq accesses(hits+misses) 1493system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 103585 # number of StoreCondReq accesses(hits+misses) 1494system.cpu1.dcache.StoreCondReq_accesses::total 103585 # number of StoreCondReq accesses(hits+misses) 1495system.cpu1.dcache.demand_accesses::cpu1.data 8972812 # number of demand (read+write) accesses 1496system.cpu1.dcache.demand_accesses::total 8972812 # number of demand (read+write) accesses 1497system.cpu1.dcache.overall_accesses::cpu1.data 9073837 # number of overall (read+write) accesses 1498system.cpu1.dcache.overall_accesses::total 9073837 # number of overall (read+write) accesses 1499system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037351 # miss rate for ReadReq accesses 1500system.cpu1.dcache.ReadReq_miss_rate::total 0.037351 # miss rate for ReadReq accesses 1501system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.041334 # miss rate for WriteReq accesses 1502system.cpu1.dcache.WriteReq_miss_rate::total 0.041334 # miss rate for WriteReq accesses 1503system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.352249 # miss rate for SoftPFReq accesses 1504system.cpu1.dcache.SoftPFReq_miss_rate::total 0.352249 # miss rate for SoftPFReq accesses 1505system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.167355 # miss rate for LoadLockedReq accesses 1506system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.167355 # miss rate for LoadLockedReq accesses 1507system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.226809 # miss rate for StoreCondReq accesses 1508system.cpu1.dcache.StoreCondReq_miss_rate::total 0.226809 # miss rate for StoreCondReq accesses 1509system.cpu1.dcache.demand_miss_rate::cpu1.data 0.039160 # miss rate for demand accesses 1510system.cpu1.dcache.demand_miss_rate::total 0.039160 # miss rate for demand accesses 1511system.cpu1.dcache.overall_miss_rate::cpu1.data 0.042646 # miss rate for overall accesses 1512system.cpu1.dcache.overall_miss_rate::total 0.042646 # miss rate for overall accesses 1513system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14593.002793 # average ReadReq miss latency 1514system.cpu1.dcache.ReadReq_avg_miss_latency::total 14593.002793 # average ReadReq miss latency 1515system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24921.072467 # average WriteReq miss latency 1516system.cpu1.dcache.WriteReq_avg_miss_latency::total 24921.072467 # average WriteReq miss latency 1517system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18382.543047 # average LoadLockedReq miss latency 1518system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18382.543047 # average LoadLockedReq miss latency 1519system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23430.906402 # average StoreCondReq miss latency 1520system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23430.906402 # average StoreCondReq miss latency |
| 1496system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1497system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 1521system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1522system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1498system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20407.866535 # average overall miss latency 1499system.cpu1.dcache.demand_avg_miss_latency::total 20407.866535 # average overall miss latency 1500system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18522.199493 # average overall miss latency 1501system.cpu1.dcache.overall_avg_miss_latency::total 18522.199493 # average overall miss latency | 1523system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19543.097301 # average overall miss latency 1524system.cpu1.dcache.demand_avg_miss_latency::total 19543.097301 # average overall miss latency 1525system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17745.850925 # average overall miss latency 1526system.cpu1.dcache.overall_avg_miss_latency::total 17745.850925 # average overall miss latency |
| 1502system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1503system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1504system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1505system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1506system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1507system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1508system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1509system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1527system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1528system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1529system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1530system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1531system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1532system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1533system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1534system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1510system.cpu1.dcache.writebacks::writebacks 119475 # number of writebacks 1511system.cpu1.dcache.writebacks::total 119475 # number of writebacks 1512system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16075 # number of ReadReq MSHR hits 1513system.cpu1.dcache.ReadReq_mshr_hits::total 16075 # number of ReadReq MSHR hits 1514system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52265 # number of WriteReq MSHR hits 1515system.cpu1.dcache.WriteReq_mshr_hits::total 52265 # number of WriteReq MSHR hits 1516system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12035 # number of LoadLockedReq MSHR hits 1517system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12035 # number of LoadLockedReq MSHR hits 1518system.cpu1.dcache.demand_mshr_hits::cpu1.data 68340 # number of demand (read+write) MSHR hits 1519system.cpu1.dcache.demand_mshr_hits::total 68340 # number of demand (read+write) MSHR hits 1520system.cpu1.dcache.overall_mshr_hits::cpu1.data 68340 # number of overall MSHR hits 1521system.cpu1.dcache.overall_mshr_hits::total 68340 # number of overall MSHR hits 1522system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 141893 # number of ReadReq MSHR misses 1523system.cpu1.dcache.ReadReq_mshr_misses::total 141893 # number of ReadReq MSHR misses 1524system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92461 # number of WriteReq MSHR misses 1525system.cpu1.dcache.WriteReq_mshr_misses::total 92461 # number of WriteReq MSHR misses 1526system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29935 # number of SoftPFReq MSHR misses 1527system.cpu1.dcache.SoftPFReq_mshr_misses::total 29935 # number of SoftPFReq MSHR misses 1528system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4884 # number of LoadLockedReq MSHR misses 1529system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4884 # number of LoadLockedReq MSHR misses 1530system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23678 # number of StoreCondReq MSHR misses 1531system.cpu1.dcache.StoreCondReq_mshr_misses::total 23678 # number of StoreCondReq MSHR misses 1532system.cpu1.dcache.demand_mshr_misses::cpu1.data 234354 # number of demand (read+write) MSHR misses 1533system.cpu1.dcache.demand_mshr_misses::total 234354 # number of demand (read+write) MSHR misses 1534system.cpu1.dcache.overall_mshr_misses::cpu1.data 264289 # number of overall MSHR misses 1535system.cpu1.dcache.overall_mshr_misses::total 264289 # number of overall MSHR misses 1536system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1871458583 # number of ReadReq MSHR miss cycles 1537system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1871458583 # number of ReadReq MSHR miss cycles 1538system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2300176813 # number of WriteReq MSHR miss cycles 1539system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2300176813 # number of WriteReq MSHR miss cycles 1540system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 487265761 # number of SoftPFReq MSHR miss cycles 1541system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 487265761 # number of SoftPFReq MSHR miss cycles 1542system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79878753 # number of LoadLockedReq MSHR miss cycles 1543system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 79878753 # number of LoadLockedReq MSHR miss cycles 1544system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 520207345 # number of StoreCondReq MSHR miss cycles 1545system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 520207345 # number of StoreCondReq MSHR miss cycles 1546system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 119500 # number of StoreCondFailReq MSHR miss cycles 1547system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 119500 # number of StoreCondFailReq MSHR miss cycles 1548system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4171635396 # number of demand (read+write) MSHR miss cycles 1549system.cpu1.dcache.demand_mshr_miss_latency::total 4171635396 # number of demand (read+write) MSHR miss cycles 1550system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4658901157 # number of overall MSHR miss cycles 1551system.cpu1.dcache.overall_mshr_miss_latency::total 4658901157 # number of overall MSHR miss cycles 1552system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2322015751 # number of ReadReq MSHR uncacheable cycles 1553system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2322015751 # number of ReadReq MSHR uncacheable cycles 1554system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1843986000 # number of WriteReq MSHR uncacheable cycles 1555system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1843986000 # number of WriteReq MSHR uncacheable cycles 1556system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4166001751 # number of overall MSHR uncacheable cycles 1557system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4166001751 # number of overall MSHR uncacheable cycles 1558system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013037 # mshr miss rate for ReadReq accesses 1559system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013037 # mshr miss rate for ReadReq accesses 1560system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013572 # mshr miss rate for WriteReq accesses 1561system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013572 # mshr miss rate for WriteReq accesses 1562system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.370483 # mshr miss rate for SoftPFReq accesses 1563system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.370483 # mshr miss rate for SoftPFReq accesses 1564system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050366 # mshr miss rate for LoadLockedReq accesses 1565system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050366 # mshr miss rate for LoadLockedReq accesses 1566system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248779 # mshr miss rate for StoreCondReq accesses 1567system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248779 # mshr miss rate for StoreCondReq accesses 1568system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013243 # mshr miss rate for demand accesses 1569system.cpu1.dcache.demand_mshr_miss_rate::total 0.013243 # mshr miss rate for demand accesses 1570system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014867 # mshr miss rate for overall accesses 1571system.cpu1.dcache.overall_mshr_miss_rate::total 0.014867 # mshr miss rate for overall accesses 1572system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13189.224155 # average ReadReq mshr miss latency 1573system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13189.224155 # average ReadReq mshr miss latency 1574system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24877.265150 # average WriteReq mshr miss latency 1575system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24877.265150 # average WriteReq mshr miss latency 1576system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16277.459863 # average SoftPFReq mshr miss latency 1577system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16277.459863 # average SoftPFReq mshr miss latency 1578system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16355.191032 # average LoadLockedReq mshr miss latency 1579system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16355.191032 # average LoadLockedReq mshr miss latency 1580system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21970.071163 # average StoreCondReq mshr miss latency 1581system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21970.071163 # average StoreCondReq mshr miss latency | 1535system.cpu1.dcache.writebacks::writebacks 138038 # number of writebacks 1536system.cpu1.dcache.writebacks::total 138038 # number of writebacks 1537system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18091 # number of ReadReq MSHR hits 1538system.cpu1.dcache.ReadReq_mshr_hits::total 18091 # number of ReadReq MSHR hits 1539system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62532 # number of WriteReq MSHR hits 1540system.cpu1.dcache.WriteReq_mshr_hits::total 62532 # number of WriteReq MSHR hits 1541system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12272 # number of LoadLockedReq MSHR hits 1542system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12272 # number of LoadLockedReq MSHR hits 1543system.cpu1.dcache.demand_mshr_hits::cpu1.data 80623 # number of demand (read+write) MSHR hits 1544system.cpu1.dcache.demand_mshr_hits::total 80623 # number of demand (read+write) MSHR hits 1545system.cpu1.dcache.overall_mshr_hits::cpu1.data 80623 # number of overall MSHR hits 1546system.cpu1.dcache.overall_mshr_hits::total 80623 # number of overall MSHR hits 1547system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164874 # number of ReadReq MSHR misses 1548system.cpu1.dcache.ReadReq_mshr_misses::total 164874 # number of ReadReq MSHR misses 1549system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105876 # number of WriteReq MSHR misses 1550system.cpu1.dcache.WriteReq_mshr_misses::total 105876 # number of WriteReq MSHR misses 1551system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 34136 # number of SoftPFReq MSHR misses 1552system.cpu1.dcache.SoftPFReq_mshr_misses::total 34136 # number of SoftPFReq MSHR misses 1553system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5441 # number of LoadLockedReq MSHR misses 1554system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5441 # number of LoadLockedReq MSHR misses 1555system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23494 # number of StoreCondReq MSHR misses 1556system.cpu1.dcache.StoreCondReq_mshr_misses::total 23494 # number of StoreCondReq MSHR misses 1557system.cpu1.dcache.demand_mshr_misses::cpu1.data 270750 # number of demand (read+write) MSHR misses 1558system.cpu1.dcache.demand_mshr_misses::total 270750 # number of demand (read+write) MSHR misses 1559system.cpu1.dcache.overall_mshr_misses::cpu1.data 304886 # number of overall MSHR misses 1560system.cpu1.dcache.overall_mshr_misses::total 304886 # number of overall MSHR misses 1561system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5716 # number of ReadReq MSHR uncacheable 1562system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5716 # number of ReadReq MSHR uncacheable 1563system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5010 # number of WriteReq MSHR uncacheable 1564system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5010 # number of WriteReq MSHR uncacheable 1565system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10726 # number of overall MSHR uncacheable misses 1566system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10726 # number of overall MSHR uncacheable misses 1567system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2161886054 # number of ReadReq MSHR miss cycles 1568system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2161886054 # number of ReadReq MSHR miss cycles 1569system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2482626291 # number of WriteReq MSHR miss cycles 1570system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2482626291 # number of WriteReq MSHR miss cycles 1571system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 533136002 # number of SoftPFReq MSHR miss cycles 1572system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 533136002 # number of SoftPFReq MSHR miss cycles 1573system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89692006 # number of LoadLockedReq MSHR miss cycles 1574system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89692006 # number of LoadLockedReq MSHR miss cycles 1575system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 513974285 # number of StoreCondReq MSHR miss cycles 1576system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 513974285 # number of StoreCondReq MSHR miss cycles 1577system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 347500 # number of StoreCondFailReq MSHR miss cycles 1578system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 347500 # number of StoreCondFailReq MSHR miss cycles 1579system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4644512345 # number of demand (read+write) MSHR miss cycles 1580system.cpu1.dcache.demand_mshr_miss_latency::total 4644512345 # number of demand (read+write) MSHR miss cycles 1581system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5177648347 # number of overall MSHR miss cycles 1582system.cpu1.dcache.overall_mshr_miss_latency::total 5177648347 # number of overall MSHR miss cycles 1583system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 978236749 # number of ReadReq MSHR uncacheable cycles 1584system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 978236749 # number of ReadReq MSHR uncacheable cycles 1585system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 848797501 # number of WriteReq MSHR uncacheable cycles 1586system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 848797501 # number of WriteReq MSHR uncacheable cycles 1587system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1827034250 # number of overall MSHR uncacheable cycles 1588system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1827034250 # number of overall MSHR uncacheable cycles 1589system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033658 # mshr miss rate for ReadReq accesses 1590system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033658 # mshr miss rate for ReadReq accesses 1591system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025986 # mshr miss rate for WriteReq accesses 1592system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025986 # mshr miss rate for WriteReq accesses 1593system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.337897 # mshr miss rate for SoftPFReq accesses 1594system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.337897 # mshr miss rate for SoftPFReq accesses 1595system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051407 # mshr miss rate for LoadLockedReq accesses 1596system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051407 # mshr miss rate for LoadLockedReq accesses 1597system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.226809 # mshr miss rate for StoreCondReq accesses 1598system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.226809 # mshr miss rate for StoreCondReq accesses 1599system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030174 # mshr miss rate for demand accesses 1600system.cpu1.dcache.demand_mshr_miss_rate::total 0.030174 # mshr miss rate for demand accesses 1601system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033601 # mshr miss rate for overall accesses 1602system.cpu1.dcache.overall_mshr_miss_rate::total 0.033601 # mshr miss rate for overall accesses 1603system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13112.352791 # average ReadReq mshr miss latency 1604system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13112.352791 # average ReadReq mshr miss latency 1605system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23448.432988 # average WriteReq mshr miss latency 1606system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23448.432988 # average WriteReq mshr miss latency 1607system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15617.998652 # average SoftPFReq mshr miss latency 1608system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15617.998652 # average SoftPFReq mshr miss latency 1609system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16484.470869 # average LoadLockedReq mshr miss latency 1610system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16484.470869 # average LoadLockedReq mshr miss latency 1611system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21876.831744 # average StoreCondReq mshr miss latency 1612system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21876.831744 # average StoreCondReq mshr miss latency |
| 1582system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1583system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1613system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1614system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1584system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17800.572621 # average overall mshr miss latency 1585system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17800.572621 # average overall mshr miss latency 1586system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17628.055488 # average overall mshr miss latency 1587system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17628.055488 # average overall mshr miss latency 1588system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1589system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1590system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1591system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1592system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1593system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1615system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17154.246888 # average overall mshr miss latency 1616system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17154.246888 # average overall mshr miss latency 1617system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16982.243681 # average overall mshr miss latency 1618system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16982.243681 # average overall mshr miss latency 1619system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171140.089048 # average ReadReq mshr uncacheable latency 1620system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171140.089048 # average ReadReq mshr uncacheable latency 1621system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169420.658882 # average WriteReq mshr uncacheable latency 1622system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169420.658882 # average WriteReq mshr uncacheable latency 1623system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170336.961589 # average overall mshr uncacheable latency 1624system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170336.961589 # average overall mshr uncacheable latency |
| 1594system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1625system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1595system.cpu1.icache.tags.replacements 947666 # number of replacements 1596system.cpu1.icache.tags.tagsinuse 499.322678 # Cycle average of tags in use 1597system.cpu1.icache.tags.total_refs 38831450 # Total number of references to valid blocks. 1598system.cpu1.icache.tags.sampled_refs 948178 # Sample count of references to valid blocks. 1599system.cpu1.icache.tags.avg_refs 40.953756 # Average number of references to valid blocks. 1600system.cpu1.icache.tags.warmup_cycle 72138919500 # Cycle when the warmup percentage was hit. 1601system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.322678 # Average occupied blocks per requestor 1602system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975240 # Average percentage of cache occupancy 1603system.cpu1.icache.tags.occ_percent::total 0.975240 # Average percentage of cache occupancy | 1626system.cpu1.icache.tags.replacements 1038832 # number of replacements 1627system.cpu1.icache.tags.tagsinuse 499.324542 # Cycle average of tags in use 1628system.cpu1.icache.tags.total_refs 9157675 # Total number of references to valid blocks. 1629system.cpu1.icache.tags.sampled_refs 1039344 # Sample count of references to valid blocks. 1630system.cpu1.icache.tags.avg_refs 8.811014 # Average number of references to valid blocks. 1631system.cpu1.icache.tags.warmup_cycle 72123856500 # Cycle when the warmup percentage was hit. 1632system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.324542 # Average occupied blocks per requestor 1633system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975243 # Average percentage of cache occupancy 1634system.cpu1.icache.tags.occ_percent::total 0.975243 # Average percentage of cache occupancy |
| 1604system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1635system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1605system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id 1606system.cpu1.icache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id | 1636system.cpu1.icache.tags.age_task_id_blocks_1024::2 459 # Occupied blocks per task id 1637system.cpu1.icache.tags.age_task_id_blocks_1024::3 53 # Occupied blocks per task id |
| 1607system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1638system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1608system.cpu1.icache.tags.tag_accesses 80507434 # Number of tag accesses 1609system.cpu1.icache.tags.data_accesses 80507434 # Number of data accesses 1610system.cpu1.icache.ReadReq_hits::cpu1.inst 38831450 # number of ReadReq hits 1611system.cpu1.icache.ReadReq_hits::total 38831450 # number of ReadReq hits 1612system.cpu1.icache.demand_hits::cpu1.inst 38831450 # number of demand (read+write) hits 1613system.cpu1.icache.demand_hits::total 38831450 # number of demand (read+write) hits 1614system.cpu1.icache.overall_hits::cpu1.inst 38831450 # number of overall hits 1615system.cpu1.icache.overall_hits::total 38831450 # number of overall hits 1616system.cpu1.icache.ReadReq_misses::cpu1.inst 948178 # number of ReadReq misses 1617system.cpu1.icache.ReadReq_misses::total 948178 # number of ReadReq misses 1618system.cpu1.icache.demand_misses::cpu1.inst 948178 # number of demand (read+write) misses 1619system.cpu1.icache.demand_misses::total 948178 # number of demand (read+write) misses 1620system.cpu1.icache.overall_misses::cpu1.inst 948178 # number of overall misses 1621system.cpu1.icache.overall_misses::total 948178 # number of overall misses 1622system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8186316171 # number of ReadReq miss cycles 1623system.cpu1.icache.ReadReq_miss_latency::total 8186316171 # number of ReadReq miss cycles 1624system.cpu1.icache.demand_miss_latency::cpu1.inst 8186316171 # number of demand (read+write) miss cycles 1625system.cpu1.icache.demand_miss_latency::total 8186316171 # number of demand (read+write) miss cycles 1626system.cpu1.icache.overall_miss_latency::cpu1.inst 8186316171 # number of overall miss cycles 1627system.cpu1.icache.overall_miss_latency::total 8186316171 # number of overall miss cycles 1628system.cpu1.icache.ReadReq_accesses::cpu1.inst 39779628 # number of ReadReq accesses(hits+misses) 1629system.cpu1.icache.ReadReq_accesses::total 39779628 # number of ReadReq accesses(hits+misses) 1630system.cpu1.icache.demand_accesses::cpu1.inst 39779628 # number of demand (read+write) accesses 1631system.cpu1.icache.demand_accesses::total 39779628 # number of demand (read+write) accesses 1632system.cpu1.icache.overall_accesses::cpu1.inst 39779628 # number of overall (read+write) accesses 1633system.cpu1.icache.overall_accesses::total 39779628 # number of overall (read+write) accesses 1634system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023836 # miss rate for ReadReq accesses 1635system.cpu1.icache.ReadReq_miss_rate::total 0.023836 # miss rate for ReadReq accesses 1636system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023836 # miss rate for demand accesses 1637system.cpu1.icache.demand_miss_rate::total 0.023836 # miss rate for demand accesses 1638system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023836 # miss rate for overall accesses 1639system.cpu1.icache.overall_miss_rate::total 0.023836 # miss rate for overall accesses 1640system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8633.733509 # average ReadReq miss latency 1641system.cpu1.icache.ReadReq_avg_miss_latency::total 8633.733509 # average ReadReq miss latency 1642system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8633.733509 # average overall miss latency 1643system.cpu1.icache.demand_avg_miss_latency::total 8633.733509 # average overall miss latency 1644system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8633.733509 # average overall miss latency 1645system.cpu1.icache.overall_avg_miss_latency::total 8633.733509 # average overall miss latency | 1639system.cpu1.icache.tags.tag_accesses 21433382 # Number of tag accesses 1640system.cpu1.icache.tags.data_accesses 21433382 # Number of data accesses 1641system.cpu1.icache.ReadReq_hits::cpu1.inst 9157675 # number of ReadReq hits 1642system.cpu1.icache.ReadReq_hits::total 9157675 # number of ReadReq hits 1643system.cpu1.icache.demand_hits::cpu1.inst 9157675 # number of demand (read+write) hits 1644system.cpu1.icache.demand_hits::total 9157675 # number of demand (read+write) hits 1645system.cpu1.icache.overall_hits::cpu1.inst 9157675 # number of overall hits 1646system.cpu1.icache.overall_hits::total 9157675 # number of overall hits 1647system.cpu1.icache.ReadReq_misses::cpu1.inst 1039344 # number of ReadReq misses 1648system.cpu1.icache.ReadReq_misses::total 1039344 # number of ReadReq misses 1649system.cpu1.icache.demand_misses::cpu1.inst 1039344 # number of demand (read+write) misses 1650system.cpu1.icache.demand_misses::total 1039344 # number of demand (read+write) misses 1651system.cpu1.icache.overall_misses::cpu1.inst 1039344 # number of overall misses 1652system.cpu1.icache.overall_misses::total 1039344 # number of overall misses 1653system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9221968883 # number of ReadReq miss cycles 1654system.cpu1.icache.ReadReq_miss_latency::total 9221968883 # number of ReadReq miss cycles 1655system.cpu1.icache.demand_miss_latency::cpu1.inst 9221968883 # number of demand (read+write) miss cycles 1656system.cpu1.icache.demand_miss_latency::total 9221968883 # number of demand (read+write) miss cycles 1657system.cpu1.icache.overall_miss_latency::cpu1.inst 9221968883 # number of overall miss cycles 1658system.cpu1.icache.overall_miss_latency::total 9221968883 # number of overall miss cycles 1659system.cpu1.icache.ReadReq_accesses::cpu1.inst 10197019 # number of ReadReq accesses(hits+misses) 1660system.cpu1.icache.ReadReq_accesses::total 10197019 # number of ReadReq accesses(hits+misses) 1661system.cpu1.icache.demand_accesses::cpu1.inst 10197019 # number of demand (read+write) accesses 1662system.cpu1.icache.demand_accesses::total 10197019 # number of demand (read+write) accesses 1663system.cpu1.icache.overall_accesses::cpu1.inst 10197019 # number of overall (read+write) accesses 1664system.cpu1.icache.overall_accesses::total 10197019 # number of overall (read+write) accesses 1665system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.101926 # miss rate for ReadReq accesses 1666system.cpu1.icache.ReadReq_miss_rate::total 0.101926 # miss rate for ReadReq accesses 1667system.cpu1.icache.demand_miss_rate::cpu1.inst 0.101926 # miss rate for demand accesses 1668system.cpu1.icache.demand_miss_rate::total 0.101926 # miss rate for demand accesses 1669system.cpu1.icache.overall_miss_rate::cpu1.inst 0.101926 # miss rate for overall accesses 1670system.cpu1.icache.overall_miss_rate::total 0.101926 # miss rate for overall accesses 1671system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8872.874508 # average ReadReq miss latency 1672system.cpu1.icache.ReadReq_avg_miss_latency::total 8872.874508 # average ReadReq miss latency 1673system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8872.874508 # average overall miss latency 1674system.cpu1.icache.demand_avg_miss_latency::total 8872.874508 # average overall miss latency 1675system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8872.874508 # average overall miss latency 1676system.cpu1.icache.overall_avg_miss_latency::total 8872.874508 # average overall miss latency |
| 1646system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1647system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1648system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1649system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1650system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1651system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1652system.cpu1.icache.fast_writes 0 # number of fast writes performed 1653system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1677system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1678system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1679system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1680system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1681system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1682system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1683system.cpu1.icache.fast_writes 0 # number of fast writes performed 1684system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1654system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 948178 # number of ReadReq MSHR misses 1655system.cpu1.icache.ReadReq_mshr_misses::total 948178 # number of ReadReq MSHR misses 1656system.cpu1.icache.demand_mshr_misses::cpu1.inst 948178 # number of demand (read+write) MSHR misses 1657system.cpu1.icache.demand_mshr_misses::total 948178 # number of demand (read+write) MSHR misses 1658system.cpu1.icache.overall_mshr_misses::cpu1.inst 948178 # number of overall MSHR misses 1659system.cpu1.icache.overall_mshr_misses::total 948178 # number of overall MSHR misses 1660system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7236829829 # number of ReadReq MSHR miss cycles 1661system.cpu1.icache.ReadReq_mshr_miss_latency::total 7236829829 # number of ReadReq MSHR miss cycles 1662system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7236829829 # number of demand (read+write) MSHR miss cycles 1663system.cpu1.icache.demand_mshr_miss_latency::total 7236829829 # number of demand (read+write) MSHR miss cycles 1664system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7236829829 # number of overall MSHR miss cycles 1665system.cpu1.icache.overall_mshr_miss_latency::total 7236829829 # number of overall MSHR miss cycles 1666system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10429000 # number of ReadReq MSHR uncacheable cycles 1667system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10429000 # number of ReadReq MSHR uncacheable cycles 1668system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10429000 # number of overall MSHR uncacheable cycles 1669system.cpu1.icache.overall_mshr_uncacheable_latency::total 10429000 # number of overall MSHR uncacheable cycles 1670system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023836 # mshr miss rate for ReadReq accesses 1671system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023836 # mshr miss rate for ReadReq accesses 1672system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023836 # mshr miss rate for demand accesses 1673system.cpu1.icache.demand_mshr_miss_rate::total 0.023836 # mshr miss rate for demand accesses 1674system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023836 # mshr miss rate for overall accesses 1675system.cpu1.icache.overall_mshr_miss_rate::total 0.023836 # mshr miss rate for overall accesses 1676system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7632.353660 # average ReadReq mshr miss latency 1677system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7632.353660 # average ReadReq mshr miss latency 1678system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7632.353660 # average overall mshr miss latency 1679system.cpu1.icache.demand_avg_mshr_miss_latency::total 7632.353660 # average overall mshr miss latency 1680system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7632.353660 # average overall mshr miss latency 1681system.cpu1.icache.overall_avg_mshr_miss_latency::total 7632.353660 # average overall mshr miss latency 1682system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1683system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1684system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1685system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1685system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 1039344 # number of ReadReq MSHR misses 1686system.cpu1.icache.ReadReq_mshr_misses::total 1039344 # number of ReadReq MSHR misses 1687system.cpu1.icache.demand_mshr_misses::cpu1.inst 1039344 # number of demand (read+write) MSHR misses 1688system.cpu1.icache.demand_mshr_misses::total 1039344 # number of demand (read+write) MSHR misses 1689system.cpu1.icache.overall_mshr_misses::cpu1.inst 1039344 # number of overall MSHR misses 1690system.cpu1.icache.overall_mshr_misses::total 1039344 # number of overall MSHR misses 1691system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 1692system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable 1693system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 1694system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses 1695system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8180244117 # number of ReadReq MSHR miss cycles 1696system.cpu1.icache.ReadReq_mshr_miss_latency::total 8180244117 # number of ReadReq MSHR miss cycles 1697system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8180244117 # number of demand (read+write) MSHR miss cycles 1698system.cpu1.icache.demand_mshr_miss_latency::total 8180244117 # number of demand (read+write) MSHR miss cycles 1699system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8180244117 # number of overall MSHR miss cycles 1700system.cpu1.icache.overall_mshr_miss_latency::total 8180244117 # number of overall MSHR miss cycles 1701system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10330000 # number of ReadReq MSHR uncacheable cycles 1702system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10330000 # number of ReadReq MSHR uncacheable cycles 1703system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10330000 # number of overall MSHR uncacheable cycles 1704system.cpu1.icache.overall_mshr_uncacheable_latency::total 10330000 # number of overall MSHR uncacheable cycles 1705system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.101926 # mshr miss rate for ReadReq accesses 1706system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.101926 # mshr miss rate for ReadReq accesses 1707system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.101926 # mshr miss rate for demand accesses 1708system.cpu1.icache.demand_mshr_miss_rate::total 0.101926 # mshr miss rate for demand accesses 1709system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.101926 # mshr miss rate for overall accesses 1710system.cpu1.icache.overall_mshr_miss_rate::total 0.101926 # mshr miss rate for overall accesses 1711system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7870.583865 # average ReadReq mshr miss latency 1712system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7870.583865 # average ReadReq mshr miss latency 1713system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7870.583865 # average overall mshr miss latency 1714system.cpu1.icache.demand_avg_mshr_miss_latency::total 7870.583865 # average overall mshr miss latency 1715system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7870.583865 # average overall mshr miss latency 1716system.cpu1.icache.overall_avg_mshr_miss_latency::total 7870.583865 # average overall mshr miss latency 1717system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92232.142857 # average ReadReq mshr uncacheable latency 1718system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92232.142857 # average ReadReq mshr uncacheable latency 1719system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92232.142857 # average overall mshr uncacheable latency 1720system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92232.142857 # average overall mshr uncacheable latency |
| 1686system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1721system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1687system.cpu1.l2cache.prefetcher.num_hwpf_issued 198185 # number of hwpf issued 1688system.cpu1.l2cache.prefetcher.pfIdentified 198250 # number of prefetch candidates identified 1689system.cpu1.l2cache.prefetcher.pfBufferHit 56 # number of redundant prefetches already in prefetch queue | 1722system.cpu1.l2cache.prefetcher.num_hwpf_issued 272919 # number of hwpf issued 1723system.cpu1.l2cache.prefetcher.pfIdentified 272954 # number of prefetch candidates identified 1724system.cpu1.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue |
| 1690system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1691system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 1725system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1726system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 1692system.cpu1.l2cache.prefetcher.pfSpanPage 58438 # number of prefetches not generated due to page crossing 1693system.cpu1.l2cache.tags.replacements 54866 # number of replacements 1694system.cpu1.l2cache.tags.tagsinuse 15346.205956 # Cycle average of tags in use 1695system.cpu1.l2cache.tags.total_refs 1177923 # Total number of references to valid blocks. 1696system.cpu1.l2cache.tags.sampled_refs 69767 # Sample count of references to valid blocks. 1697system.cpu1.l2cache.tags.avg_refs 16.883670 # Average number of references to valid blocks. | 1727system.cpu1.l2cache.prefetcher.pfSpanPage 68790 # number of prefetches not generated due to page crossing 1728system.cpu1.l2cache.tags.replacements 69865 # number of replacements 1729system.cpu1.l2cache.tags.tagsinuse 15664.735857 # Cycle average of tags in use 1730system.cpu1.l2cache.tags.total_refs 1313161 # Total number of references to valid blocks. 1731system.cpu1.l2cache.tags.sampled_refs 84814 # Sample count of references to valid blocks. 1732system.cpu1.l2cache.tags.avg_refs 15.482833 # Average number of references to valid blocks. |
| 1698system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1733system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1699system.cpu1.l2cache.tags.occ_blocks::writebacks 7899.614060 # Average occupied blocks per requestor 1700system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 43.616627 # Average occupied blocks per requestor 1701system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.093163 # Average occupied blocks per requestor 1702system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4379.239024 # Average occupied blocks per requestor 1703system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2180.842140 # Average occupied blocks per requestor 1704system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 842.800943 # Average occupied blocks per requestor 1705system.cpu1.l2cache.tags.occ_percent::writebacks 0.482154 # Average percentage of cache occupancy 1706system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002662 # Average percentage of cache occupancy 1707system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy 1708system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.267288 # Average percentage of cache occupancy 1709system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.133108 # Average percentage of cache occupancy 1710system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051440 # Average percentage of cache occupancy 1711system.cpu1.l2cache.tags.occ_percent::total 0.936658 # Average percentage of cache occupancy 1712system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1047 # Occupied blocks per task id 1713system.cpu1.l2cache.tags.occ_task_id_blocks::1023 51 # Occupied blocks per task id 1714system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13803 # Occupied blocks per task id 1715system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id 1716system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 662 # Occupied blocks per task id 1717system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 384 # Occupied blocks per task id 1718system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id 1719system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id 1720system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id 1721system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id 1722system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6041 # Occupied blocks per task id 1723system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7452 # Occupied blocks per task id 1724system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.063904 # Percentage of cache occupancy per task id 1725system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id 1726system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.842468 # Percentage of cache occupancy per task id 1727system.cpu1.l2cache.tags.tag_accesses 22495354 # Number of tag accesses 1728system.cpu1.l2cache.tags.data_accesses 22495354 # Number of data accesses 1729system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28402 # number of ReadReq hits 1730system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2611 # number of ReadReq hits 1731system.cpu1.l2cache.ReadReq_hits::cpu1.inst 927201 # number of ReadReq hits 1732system.cpu1.l2cache.ReadReq_hits::cpu1.data 105616 # number of ReadReq hits 1733system.cpu1.l2cache.ReadReq_hits::total 1063830 # number of ReadReq hits 1734system.cpu1.l2cache.Writeback_hits::writebacks 119475 # number of Writeback hits 1735system.cpu1.l2cache.Writeback_hits::total 119475 # number of Writeback hits 1736system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1556 # number of UpgradeReq hits 1737system.cpu1.l2cache.UpgradeReq_hits::total 1556 # number of UpgradeReq hits 1738system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 974 # number of SCUpgradeReq hits 1739system.cpu1.l2cache.SCUpgradeReq_hits::total 974 # number of SCUpgradeReq hits 1740system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28114 # number of ReadExReq hits 1741system.cpu1.l2cache.ReadExReq_hits::total 28114 # number of ReadExReq hits 1742system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28402 # number of demand (read+write) hits 1743system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2611 # number of demand (read+write) hits 1744system.cpu1.l2cache.demand_hits::cpu1.inst 927201 # number of demand (read+write) hits 1745system.cpu1.l2cache.demand_hits::cpu1.data 133730 # number of demand (read+write) hits 1746system.cpu1.l2cache.demand_hits::total 1091944 # number of demand (read+write) hits 1747system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 28402 # number of overall hits 1748system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2611 # number of overall hits 1749system.cpu1.l2cache.overall_hits::cpu1.inst 927201 # number of overall hits 1750system.cpu1.l2cache.overall_hits::cpu1.data 133730 # number of overall hits 1751system.cpu1.l2cache.overall_hits::total 1091944 # number of overall hits 1752system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 655 # number of ReadReq misses 1753system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 221 # number of ReadReq misses 1754system.cpu1.l2cache.ReadReq_misses::cpu1.inst 20977 # number of ReadReq misses 1755system.cpu1.l2cache.ReadReq_misses::cpu1.data 71094 # number of ReadReq misses 1756system.cpu1.l2cache.ReadReq_misses::total 92947 # number of ReadReq misses 1757system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28365 # number of UpgradeReq misses 1758system.cpu1.l2cache.UpgradeReq_misses::total 28365 # number of UpgradeReq misses 1759system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22703 # number of SCUpgradeReq misses 1760system.cpu1.l2cache.SCUpgradeReq_misses::total 22703 # number of SCUpgradeReq misses 1761system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses 1762system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 1763system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34428 # number of ReadExReq misses 1764system.cpu1.l2cache.ReadExReq_misses::total 34428 # number of ReadExReq misses 1765system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 655 # number of demand (read+write) misses 1766system.cpu1.l2cache.demand_misses::cpu1.itb.walker 221 # number of demand (read+write) misses 1767system.cpu1.l2cache.demand_misses::cpu1.inst 20977 # number of demand (read+write) misses 1768system.cpu1.l2cache.demand_misses::cpu1.data 105522 # number of demand (read+write) misses 1769system.cpu1.l2cache.demand_misses::total 127375 # number of demand (read+write) misses 1770system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 655 # number of overall misses 1771system.cpu1.l2cache.overall_misses::cpu1.itb.walker 221 # number of overall misses 1772system.cpu1.l2cache.overall_misses::cpu1.inst 20977 # number of overall misses 1773system.cpu1.l2cache.overall_misses::cpu1.data 105522 # number of overall misses 1774system.cpu1.l2cache.overall_misses::total 127375 # number of overall misses 1775system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 15088235 # number of ReadReq miss cycles 1776system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4439998 # number of ReadReq miss cycles 1777system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 733507240 # number of ReadReq miss cycles 1778system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1569643994 # number of ReadReq miss cycles 1779system.cpu1.l2cache.ReadReq_miss_latency::total 2322679467 # number of ReadReq miss cycles 1780system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536973358 # number of UpgradeReq miss cycles 1781system.cpu1.l2cache.UpgradeReq_miss_latency::total 536973358 # number of UpgradeReq miss cycles 1782system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 458518574 # number of SCUpgradeReq miss cycles 1783system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 458518574 # number of SCUpgradeReq miss cycles 1784system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 116500 # number of SCUpgradeFailReq miss cycles 1785system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 116500 # number of SCUpgradeFailReq miss cycles 1786system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1375727201 # number of ReadExReq miss cycles 1787system.cpu1.l2cache.ReadExReq_miss_latency::total 1375727201 # number of ReadExReq miss cycles 1788system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 15088235 # number of demand (read+write) miss cycles 1789system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4439998 # number of demand (read+write) miss cycles 1790system.cpu1.l2cache.demand_miss_latency::cpu1.inst 733507240 # number of demand (read+write) miss cycles 1791system.cpu1.l2cache.demand_miss_latency::cpu1.data 2945371195 # number of demand (read+write) miss cycles 1792system.cpu1.l2cache.demand_miss_latency::total 3698406668 # number of demand (read+write) miss cycles 1793system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 15088235 # number of overall miss cycles 1794system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4439998 # number of overall miss cycles 1795system.cpu1.l2cache.overall_miss_latency::cpu1.inst 733507240 # number of overall miss cycles 1796system.cpu1.l2cache.overall_miss_latency::cpu1.data 2945371195 # number of overall miss cycles 1797system.cpu1.l2cache.overall_miss_latency::total 3698406668 # number of overall miss cycles 1798system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29057 # number of ReadReq accesses(hits+misses) 1799system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2832 # number of ReadReq accesses(hits+misses) 1800system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 948178 # number of ReadReq accesses(hits+misses) 1801system.cpu1.l2cache.ReadReq_accesses::cpu1.data 176710 # number of ReadReq accesses(hits+misses) 1802system.cpu1.l2cache.ReadReq_accesses::total 1156777 # number of ReadReq accesses(hits+misses) 1803system.cpu1.l2cache.Writeback_accesses::writebacks 119475 # number of Writeback accesses(hits+misses) 1804system.cpu1.l2cache.Writeback_accesses::total 119475 # number of Writeback accesses(hits+misses) 1805system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29921 # number of UpgradeReq accesses(hits+misses) 1806system.cpu1.l2cache.UpgradeReq_accesses::total 29921 # number of UpgradeReq accesses(hits+misses) 1807system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23677 # number of SCUpgradeReq accesses(hits+misses) 1808system.cpu1.l2cache.SCUpgradeReq_accesses::total 23677 # number of SCUpgradeReq accesses(hits+misses) 1809system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 1810system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 1811system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62542 # number of ReadExReq accesses(hits+misses) 1812system.cpu1.l2cache.ReadExReq_accesses::total 62542 # number of ReadExReq accesses(hits+misses) 1813system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29057 # number of demand (read+write) accesses 1814system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2832 # number of demand (read+write) accesses 1815system.cpu1.l2cache.demand_accesses::cpu1.inst 948178 # number of demand (read+write) accesses 1816system.cpu1.l2cache.demand_accesses::cpu1.data 239252 # number of demand (read+write) accesses 1817system.cpu1.l2cache.demand_accesses::total 1219319 # number of demand (read+write) accesses 1818system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29057 # number of overall (read+write) accesses 1819system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2832 # number of overall (read+write) accesses 1820system.cpu1.l2cache.overall_accesses::cpu1.inst 948178 # number of overall (read+write) accesses 1821system.cpu1.l2cache.overall_accesses::cpu1.data 239252 # number of overall (read+write) accesses 1822system.cpu1.l2cache.overall_accesses::total 1219319 # number of overall (read+write) accesses 1823system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022542 # miss rate for ReadReq accesses 1824system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.078037 # miss rate for ReadReq accesses 1825system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.022123 # miss rate for ReadReq accesses 1826system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.402320 # miss rate for ReadReq accesses 1827system.cpu1.l2cache.ReadReq_miss_rate::total 0.080350 # miss rate for ReadReq accesses 1828system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.947996 # miss rate for UpgradeReq accesses 1829system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.947996 # miss rate for UpgradeReq accesses 1830system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.958863 # miss rate for SCUpgradeReq accesses 1831system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.958863 # miss rate for SCUpgradeReq accesses 1832system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 1833system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1834system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.550478 # miss rate for ReadExReq accesses 1835system.cpu1.l2cache.ReadExReq_miss_rate::total 0.550478 # miss rate for ReadExReq accesses 1836system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022542 # miss rate for demand accesses 1837system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.078037 # miss rate for demand accesses 1838system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.022123 # miss rate for demand accesses 1839system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.441050 # miss rate for demand accesses 1840system.cpu1.l2cache.demand_miss_rate::total 0.104464 # miss rate for demand accesses 1841system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022542 # miss rate for overall accesses 1842system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.078037 # miss rate for overall accesses 1843system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.022123 # miss rate for overall accesses 1844system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.441050 # miss rate for overall accesses 1845system.cpu1.l2cache.overall_miss_rate::total 0.104464 # miss rate for overall accesses 1846system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23035.473282 # average ReadReq miss latency 1847system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20090.488688 # average ReadReq miss latency 1848system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34967.213615 # average ReadReq miss latency 1849system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22078.431288 # average ReadReq miss latency 1850system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24989.289240 # average ReadReq miss latency 1851system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18930.842870 # average UpgradeReq miss latency 1852system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18930.842870 # average UpgradeReq miss latency 1853system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20196.386997 # average SCUpgradeReq miss latency 1854system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20196.386997 # average SCUpgradeReq miss latency 1855system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 116500 # average SCUpgradeFailReq miss latency 1856system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 116500 # average SCUpgradeFailReq miss latency 1857system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39959.544586 # average ReadExReq miss latency 1858system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39959.544586 # average ReadExReq miss latency 1859system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23035.473282 # average overall miss latency 1860system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20090.488688 # average overall miss latency 1861system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34967.213615 # average overall miss latency 1862system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27912.389786 # average overall miss latency 1863system.cpu1.l2cache.demand_avg_miss_latency::total 29035.577374 # average overall miss latency 1864system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23035.473282 # average overall miss latency 1865system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20090.488688 # average overall miss latency 1866system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34967.213615 # average overall miss latency 1867system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27912.389786 # average overall miss latency 1868system.cpu1.l2cache.overall_avg_miss_latency::total 29035.577374 # average overall miss latency 1869system.cpu1.l2cache.blocked_cycles::no_mshrs 66 # number of cycles access was blocked | 1734system.cpu1.l2cache.tags.occ_blocks::writebacks 6115.525293 # Average occupied blocks per requestor 1735system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 60.132908 # Average occupied blocks per requestor 1736system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.972099 # Average occupied blocks per requestor 1737system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5626.461246 # Average occupied blocks per requestor 1738system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2273.619533 # Average occupied blocks per requestor 1739system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1588.024777 # Average occupied blocks per requestor 1740system.cpu1.l2cache.tags.occ_percent::writebacks 0.373262 # Average percentage of cache occupancy 1741system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003670 # Average percentage of cache occupancy 1742system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000059 # Average percentage of cache occupancy 1743system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.343412 # Average percentage of cache occupancy 1744system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.138771 # Average percentage of cache occupancy 1745system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.096925 # Average percentage of cache occupancy 1746system.cpu1.l2cache.tags.occ_percent::total 0.956100 # Average percentage of cache occupancy 1747system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1163 # Occupied blocks per task id 1748system.cpu1.l2cache.tags.occ_task_id_blocks::1023 63 # Occupied blocks per task id 1749system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13723 # Occupied blocks per task id 1750system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id 1751system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 666 # Occupied blocks per task id 1752system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 493 # Occupied blocks per task id 1753system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id 1754system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id 1755system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id 1756system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id 1757system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6148 # Occupied blocks per task id 1758system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7266 # Occupied blocks per task id 1759system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.070984 # Percentage of cache occupancy per task id 1760system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id 1761system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.837585 # Percentage of cache occupancy per task id 1762system.cpu1.l2cache.tags.tag_accesses 25009138 # Number of tag accesses 1763system.cpu1.l2cache.tags.data_accesses 25009138 # Number of data accesses 1764system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 33079 # number of ReadReq hits 1765system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2665 # number of ReadReq hits 1766system.cpu1.l2cache.ReadReq_hits::cpu1.inst 1011889 # number of ReadReq hits 1767system.cpu1.l2cache.ReadReq_hits::cpu1.data 130945 # number of ReadReq hits 1768system.cpu1.l2cache.ReadReq_hits::total 1178578 # number of ReadReq hits 1769system.cpu1.l2cache.Writeback_hits::writebacks 138038 # number of Writeback hits 1770system.cpu1.l2cache.Writeback_hits::total 138038 # number of Writeback hits 1771system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1986 # number of UpgradeReq hits 1772system.cpu1.l2cache.UpgradeReq_hits::total 1986 # number of UpgradeReq hits 1773system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1041 # number of SCUpgradeReq hits 1774system.cpu1.l2cache.SCUpgradeReq_hits::total 1041 # number of SCUpgradeReq hits 1775system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38169 # number of ReadExReq hits 1776system.cpu1.l2cache.ReadExReq_hits::total 38169 # number of ReadExReq hits 1777system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 33079 # number of demand (read+write) hits 1778system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2665 # number of demand (read+write) hits 1779system.cpu1.l2cache.demand_hits::cpu1.inst 1011889 # number of demand (read+write) hits 1780system.cpu1.l2cache.demand_hits::cpu1.data 169114 # number of demand (read+write) hits 1781system.cpu1.l2cache.demand_hits::total 1216747 # number of demand (read+write) hits 1782system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 33079 # number of overall hits 1783system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2665 # number of overall hits 1784system.cpu1.l2cache.overall_hits::cpu1.inst 1011889 # number of overall hits 1785system.cpu1.l2cache.overall_hits::cpu1.data 169114 # number of overall hits 1786system.cpu1.l2cache.overall_hits::total 1216747 # number of overall hits 1787system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 706 # number of ReadReq misses 1788system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 219 # number of ReadReq misses 1789system.cpu1.l2cache.ReadReq_misses::cpu1.inst 27455 # number of ReadReq misses 1790system.cpu1.l2cache.ReadReq_misses::cpu1.data 73504 # number of ReadReq misses 1791system.cpu1.l2cache.ReadReq_misses::total 101884 # number of ReadReq misses 1792system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29526 # number of UpgradeReq misses 1793system.cpu1.l2cache.UpgradeReq_misses::total 29526 # number of UpgradeReq misses 1794system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22453 # number of SCUpgradeReq misses 1795system.cpu1.l2cache.SCUpgradeReq_misses::total 22453 # number of SCUpgradeReq misses 1796system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36197 # number of ReadExReq misses 1797system.cpu1.l2cache.ReadExReq_misses::total 36197 # number of ReadExReq misses 1798system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 706 # number of demand (read+write) misses 1799system.cpu1.l2cache.demand_misses::cpu1.itb.walker 219 # number of demand (read+write) misses 1800system.cpu1.l2cache.demand_misses::cpu1.inst 27455 # number of demand (read+write) misses 1801system.cpu1.l2cache.demand_misses::cpu1.data 109701 # number of demand (read+write) misses 1802system.cpu1.l2cache.demand_misses::total 138081 # number of demand (read+write) misses 1803system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 706 # number of overall misses 1804system.cpu1.l2cache.overall_misses::cpu1.itb.walker 219 # number of overall misses 1805system.cpu1.l2cache.overall_misses::cpu1.inst 27455 # number of overall misses 1806system.cpu1.l2cache.overall_misses::cpu1.data 109701 # number of overall misses 1807system.cpu1.l2cache.overall_misses::total 138081 # number of overall misses 1808system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 17675980 # number of ReadReq miss cycles 1809system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4473998 # number of ReadReq miss cycles 1810system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1080327485 # number of ReadReq miss cycles 1811system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1722703491 # number of ReadReq miss cycles 1812system.cpu1.l2cache.ReadReq_miss_latency::total 2825180954 # number of ReadReq miss cycles 1813system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 558586766 # number of UpgradeReq miss cycles 1814system.cpu1.l2cache.UpgradeReq_miss_latency::total 558586766 # number of UpgradeReq miss cycles 1815system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449048470 # number of SCUpgradeReq miss cycles 1816system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449048470 # number of SCUpgradeReq miss cycles 1817system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 339500 # number of SCUpgradeFailReq miss cycles 1818system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 339500 # number of SCUpgradeFailReq miss cycles 1819system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1429113805 # number of ReadExReq miss cycles 1820system.cpu1.l2cache.ReadExReq_miss_latency::total 1429113805 # number of ReadExReq miss cycles 1821system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 17675980 # number of demand (read+write) miss cycles 1822system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4473998 # number of demand (read+write) miss cycles 1823system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1080327485 # number of demand (read+write) miss cycles 1824system.cpu1.l2cache.demand_miss_latency::cpu1.data 3151817296 # number of demand (read+write) miss cycles 1825system.cpu1.l2cache.demand_miss_latency::total 4254294759 # number of demand (read+write) miss cycles 1826system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 17675980 # number of overall miss cycles 1827system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4473998 # number of overall miss cycles 1828system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1080327485 # number of overall miss cycles 1829system.cpu1.l2cache.overall_miss_latency::cpu1.data 3151817296 # number of overall miss cycles 1830system.cpu1.l2cache.overall_miss_latency::total 4254294759 # number of overall miss cycles 1831system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 33785 # number of ReadReq accesses(hits+misses) 1832system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2884 # number of ReadReq accesses(hits+misses) 1833system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 1039344 # number of ReadReq accesses(hits+misses) 1834system.cpu1.l2cache.ReadReq_accesses::cpu1.data 204449 # number of ReadReq accesses(hits+misses) 1835system.cpu1.l2cache.ReadReq_accesses::total 1280462 # number of ReadReq accesses(hits+misses) 1836system.cpu1.l2cache.Writeback_accesses::writebacks 138038 # number of Writeback accesses(hits+misses) 1837system.cpu1.l2cache.Writeback_accesses::total 138038 # number of Writeback accesses(hits+misses) 1838system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31512 # number of UpgradeReq accesses(hits+misses) 1839system.cpu1.l2cache.UpgradeReq_accesses::total 31512 # number of UpgradeReq accesses(hits+misses) 1840system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23494 # number of SCUpgradeReq accesses(hits+misses) 1841system.cpu1.l2cache.SCUpgradeReq_accesses::total 23494 # number of SCUpgradeReq accesses(hits+misses) 1842system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 74366 # number of ReadExReq accesses(hits+misses) 1843system.cpu1.l2cache.ReadExReq_accesses::total 74366 # number of ReadExReq accesses(hits+misses) 1844system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 33785 # number of demand (read+write) accesses 1845system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2884 # number of demand (read+write) accesses 1846system.cpu1.l2cache.demand_accesses::cpu1.inst 1039344 # number of demand (read+write) accesses 1847system.cpu1.l2cache.demand_accesses::cpu1.data 278815 # number of demand (read+write) accesses 1848system.cpu1.l2cache.demand_accesses::total 1354828 # number of demand (read+write) accesses 1849system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 33785 # number of overall (read+write) accesses 1850system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2884 # number of overall (read+write) accesses 1851system.cpu1.l2cache.overall_accesses::cpu1.inst 1039344 # number of overall (read+write) accesses 1852system.cpu1.l2cache.overall_accesses::cpu1.data 278815 # number of overall (read+write) accesses 1853system.cpu1.l2cache.overall_accesses::total 1354828 # number of overall (read+write) accesses 1854system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020897 # miss rate for ReadReq accesses 1855system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.075936 # miss rate for ReadReq accesses 1856system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026416 # miss rate for ReadReq accesses 1857system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.359522 # miss rate for ReadReq accesses 1858system.cpu1.l2cache.ReadReq_miss_rate::total 0.079568 # miss rate for ReadReq accesses 1859system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.936976 # miss rate for UpgradeReq accesses 1860system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.936976 # miss rate for UpgradeReq accesses 1861system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.955691 # miss rate for SCUpgradeReq accesses 1862system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.955691 # miss rate for SCUpgradeReq accesses 1863system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.486741 # miss rate for ReadExReq accesses 1864system.cpu1.l2cache.ReadExReq_miss_rate::total 0.486741 # miss rate for ReadExReq accesses 1865system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020897 # miss rate for demand accesses 1866system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.075936 # miss rate for demand accesses 1867system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026416 # miss rate for demand accesses 1868system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.393454 # miss rate for demand accesses 1869system.cpu1.l2cache.demand_miss_rate::total 0.101918 # miss rate for demand accesses 1870system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020897 # miss rate for overall accesses 1871system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.075936 # miss rate for overall accesses 1872system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026416 # miss rate for overall accesses 1873system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.393454 # miss rate for overall accesses 1874system.cpu1.l2cache.overall_miss_rate::total 0.101918 # miss rate for overall accesses 1875system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25036.798867 # average ReadReq miss latency 1876system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20429.214612 # average ReadReq miss latency 1877system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 39349.025132 # average ReadReq miss latency 1878system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 23436.867259 # average ReadReq miss latency 1879system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27729.387872 # average ReadReq miss latency 1880system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18918.470704 # average UpgradeReq miss latency 1881system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18918.470704 # average UpgradeReq miss latency 1882system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19999.486483 # average SCUpgradeReq miss latency 1883system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19999.486483 # average SCUpgradeReq miss latency 1884system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency 1885system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 1886system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39481.553858 # average ReadExReq miss latency 1887system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39481.553858 # average ReadExReq miss latency 1888system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25036.798867 # average overall miss latency 1889system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20429.214612 # average overall miss latency 1890system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39349.025132 # average overall miss latency 1891system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28730.980538 # average overall miss latency 1892system.cpu1.l2cache.demand_avg_miss_latency::total 30810.138679 # average overall miss latency 1893system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25036.798867 # average overall miss latency 1894system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20429.214612 # average overall miss latency 1895system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39349.025132 # average overall miss latency 1896system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28730.980538 # average overall miss latency 1897system.cpu1.l2cache.overall_avg_miss_latency::total 30810.138679 # average overall miss latency 1898system.cpu1.l2cache.blocked_cycles::no_mshrs 82 # number of cycles access was blocked |
| 1870system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1899system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1871system.cpu1.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked | 1900system.cpu1.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked |
| 1872system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1901system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1873system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 33 # average number of cycles each access was blocked | 1902system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 20.500000 # average number of cycles each access was blocked |
| 1874system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1875system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1876system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 1903system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1904system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1905system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 1877system.cpu1.l2cache.writebacks::writebacks 32095 # number of writebacks 1878system.cpu1.l2cache.writebacks::total 32095 # number of writebacks 1879system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 29 # number of ReadReq MSHR hits 1880system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 84 # number of ReadReq MSHR hits 1881system.cpu1.l2cache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits 1882system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 230 # number of ReadExReq MSHR hits 1883system.cpu1.l2cache.ReadExReq_mshr_hits::total 230 # number of ReadExReq MSHR hits 1884system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 29 # number of demand (read+write) MSHR hits 1885system.cpu1.l2cache.demand_mshr_hits::cpu1.data 314 # number of demand (read+write) MSHR hits 1886system.cpu1.l2cache.demand_mshr_hits::total 343 # number of demand (read+write) MSHR hits 1887system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 29 # number of overall MSHR hits 1888system.cpu1.l2cache.overall_mshr_hits::cpu1.data 314 # number of overall MSHR hits 1889system.cpu1.l2cache.overall_mshr_hits::total 343 # number of overall MSHR hits 1890system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 655 # number of ReadReq MSHR misses 1891system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 221 # number of ReadReq MSHR misses 1892system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 20948 # number of ReadReq MSHR misses 1893system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 71010 # number of ReadReq MSHR misses 1894system.cpu1.l2cache.ReadReq_mshr_misses::total 92834 # number of ReadReq MSHR misses 1895system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 23894 # number of HardPFReq MSHR misses 1896system.cpu1.l2cache.HardPFReq_mshr_misses::total 23894 # number of HardPFReq MSHR misses 1897system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28365 # number of UpgradeReq MSHR misses 1898system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28365 # number of UpgradeReq MSHR misses 1899system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22703 # number of SCUpgradeReq MSHR misses 1900system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22703 # number of SCUpgradeReq MSHR misses 1901system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses 1902system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 1903system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34198 # number of ReadExReq MSHR misses 1904system.cpu1.l2cache.ReadExReq_mshr_misses::total 34198 # number of ReadExReq MSHR misses 1905system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 655 # number of demand (read+write) MSHR misses 1906system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 221 # number of demand (read+write) MSHR misses 1907system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 20948 # number of demand (read+write) MSHR misses 1908system.cpu1.l2cache.demand_mshr_misses::cpu1.data 105208 # number of demand (read+write) MSHR misses 1909system.cpu1.l2cache.demand_mshr_misses::total 127032 # number of demand (read+write) MSHR misses 1910system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 655 # number of overall MSHR misses 1911system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 221 # number of overall MSHR misses 1912system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 20948 # number of overall MSHR misses 1913system.cpu1.l2cache.overall_mshr_misses::cpu1.data 105208 # number of overall MSHR misses 1914system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 23894 # number of overall MSHR misses 1915system.cpu1.l2cache.overall_mshr_misses::total 150926 # number of overall MSHR misses 1916system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 10825243 # number of ReadReq MSHR miss cycles 1917system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3002500 # number of ReadReq MSHR miss cycles 1918system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 595509510 # number of ReadReq MSHR miss cycles 1919system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1105908750 # number of ReadReq MSHR miss cycles 1920system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1715246003 # number of ReadReq MSHR miss cycles 1921system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1009576164 # number of HardPFReq MSHR miss cycles 1922system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1009576164 # number of HardPFReq MSHR miss cycles 1923system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 452138519 # number of UpgradeReq MSHR miss cycles 1924system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 452138519 # number of UpgradeReq MSHR miss cycles 1925system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 342402748 # number of SCUpgradeReq MSHR miss cycles 1926system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 342402748 # number of SCUpgradeReq MSHR miss cycles 1927system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 97000 # number of SCUpgradeFailReq MSHR miss cycles 1928system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 97000 # number of SCUpgradeFailReq MSHR miss cycles 1929system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1121062806 # number of ReadExReq MSHR miss cycles 1930system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1121062806 # number of ReadExReq MSHR miss cycles 1931system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 10825243 # number of demand (read+write) MSHR miss cycles 1932system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3002500 # number of demand (read+write) MSHR miss cycles 1933system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 595509510 # number of demand (read+write) MSHR miss cycles 1934system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2226971556 # number of demand (read+write) MSHR miss cycles 1935system.cpu1.l2cache.demand_mshr_miss_latency::total 2836308809 # number of demand (read+write) MSHR miss cycles 1936system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 10825243 # number of overall MSHR miss cycles 1937system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3002500 # number of overall MSHR miss cycles 1938system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 595509510 # number of overall MSHR miss cycles 1939system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2226971556 # number of overall MSHR miss cycles 1940system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1009576164 # number of overall MSHR miss cycles 1941system.cpu1.l2cache.overall_mshr_miss_latency::total 3845884973 # number of overall MSHR miss cycles 1942system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9469000 # number of ReadReq MSHR uncacheable cycles 1943system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2205184749 # number of ReadReq MSHR uncacheable cycles 1944system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2214653749 # number of ReadReq MSHR uncacheable cycles 1945system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1754353500 # number of WriteReq MSHR uncacheable cycles 1946system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1754353500 # number of WriteReq MSHR uncacheable cycles 1947system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9469000 # number of overall MSHR uncacheable cycles 1948system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3959538249 # number of overall MSHR uncacheable cycles 1949system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3969007249 # number of overall MSHR uncacheable cycles 1950system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022542 # mshr miss rate for ReadReq accesses 1951system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.078037 # mshr miss rate for ReadReq accesses 1952system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.022093 # mshr miss rate for ReadReq accesses 1953system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.401845 # mshr miss rate for ReadReq accesses 1954system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.080252 # mshr miss rate for ReadReq accesses | 1906system.cpu1.l2cache.writebacks::writebacks 37239 # number of writebacks 1907system.cpu1.l2cache.writebacks::total 37239 # number of writebacks 1908system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 26 # number of ReadReq MSHR hits 1909system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 127 # number of ReadReq MSHR hits 1910system.cpu1.l2cache.ReadReq_mshr_hits::total 153 # number of ReadReq MSHR hits 1911system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 350 # number of ReadExReq MSHR hits 1912system.cpu1.l2cache.ReadExReq_mshr_hits::total 350 # number of ReadExReq MSHR hits 1913system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 26 # number of demand (read+write) MSHR hits 1914system.cpu1.l2cache.demand_mshr_hits::cpu1.data 477 # number of demand (read+write) MSHR hits 1915system.cpu1.l2cache.demand_mshr_hits::total 503 # number of demand (read+write) MSHR hits 1916system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 26 # number of overall MSHR hits 1917system.cpu1.l2cache.overall_mshr_hits::cpu1.data 477 # number of overall MSHR hits 1918system.cpu1.l2cache.overall_mshr_hits::total 503 # number of overall MSHR hits 1919system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 706 # number of ReadReq MSHR misses 1920system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 219 # number of ReadReq MSHR misses 1921system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 27429 # number of ReadReq MSHR misses 1922system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 73377 # number of ReadReq MSHR misses 1923system.cpu1.l2cache.ReadReq_mshr_misses::total 101731 # number of ReadReq MSHR misses 1924system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 35271 # number of HardPFReq MSHR misses 1925system.cpu1.l2cache.HardPFReq_mshr_misses::total 35271 # number of HardPFReq MSHR misses 1926system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29526 # number of UpgradeReq MSHR misses 1927system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29526 # number of UpgradeReq MSHR misses 1928system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22453 # number of SCUpgradeReq MSHR misses 1929system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22453 # number of SCUpgradeReq MSHR misses 1930system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35847 # number of ReadExReq MSHR misses 1931system.cpu1.l2cache.ReadExReq_mshr_misses::total 35847 # number of ReadExReq MSHR misses 1932system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 706 # number of demand (read+write) MSHR misses 1933system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 219 # number of demand (read+write) MSHR misses 1934system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 27429 # number of demand (read+write) MSHR misses 1935system.cpu1.l2cache.demand_mshr_misses::cpu1.data 109224 # number of demand (read+write) MSHR misses 1936system.cpu1.l2cache.demand_mshr_misses::total 137578 # number of demand (read+write) MSHR misses 1937system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 706 # number of overall MSHR misses 1938system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 219 # number of overall MSHR misses 1939system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 27429 # number of overall MSHR misses 1940system.cpu1.l2cache.overall_mshr_misses::cpu1.data 109224 # number of overall MSHR misses 1941system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 35271 # number of overall MSHR misses 1942system.cpu1.l2cache.overall_mshr_misses::total 172849 # number of overall MSHR misses 1943system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 1944system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5716 # number of ReadReq MSHR uncacheable 1945system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5828 # number of ReadReq MSHR uncacheable 1946system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5010 # number of WriteReq MSHR uncacheable 1947system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5010 # number of WriteReq MSHR uncacheable 1948system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 1949system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10726 # number of overall MSHR uncacheable misses 1950system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10838 # number of overall MSHR uncacheable misses 1951system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 13073996 # number of ReadReq MSHR miss cycles 1952system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3049500 # number of ReadReq MSHR miss cycles 1953system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 898741765 # number of ReadReq MSHR miss cycles 1954system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1240067767 # number of ReadReq MSHR miss cycles 1955system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 2154933028 # number of ReadReq MSHR miss cycles 1956system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1274079828 # number of HardPFReq MSHR miss cycles 1957system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1274079828 # number of HardPFReq MSHR miss cycles 1958system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 492031029 # number of UpgradeReq MSHR miss cycles 1959system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 492031029 # number of UpgradeReq MSHR miss cycles 1960system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 337561796 # number of SCUpgradeReq MSHR miss cycles 1961system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 337561796 # number of SCUpgradeReq MSHR miss cycles 1962system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 287500 # number of SCUpgradeFailReq MSHR miss cycles 1963system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 287500 # number of SCUpgradeFailReq MSHR miss cycles 1964system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1155906813 # number of ReadExReq MSHR miss cycles 1965system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1155906813 # number of ReadExReq MSHR miss cycles 1966system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 13073996 # number of demand (read+write) MSHR miss cycles 1967system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3049500 # number of demand (read+write) MSHR miss cycles 1968system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 898741765 # number of demand (read+write) MSHR miss cycles 1969system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2395974580 # number of demand (read+write) MSHR miss cycles 1970system.cpu1.l2cache.demand_mshr_miss_latency::total 3310839841 # number of demand (read+write) MSHR miss cycles 1971system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 13073996 # number of overall MSHR miss cycles 1972system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3049500 # number of overall MSHR miss cycles 1973system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 898741765 # number of overall MSHR miss cycles 1974system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2395974580 # number of overall MSHR miss cycles 1975system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1274079828 # number of overall MSHR miss cycles 1976system.cpu1.l2cache.overall_mshr_miss_latency::total 4584919669 # number of overall MSHR miss cycles 1977system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9388000 # number of ReadReq MSHR uncacheable cycles 1978system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 932474750 # number of ReadReq MSHR uncacheable cycles 1979system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 941862750 # number of ReadReq MSHR uncacheable cycles 1980system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 811133499 # number of WriteReq MSHR uncacheable cycles 1981system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 811133499 # number of WriteReq MSHR uncacheable cycles 1982system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9388000 # number of overall MSHR uncacheable cycles 1983system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1743608249 # number of overall MSHR uncacheable cycles 1984system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1752996249 # number of overall MSHR uncacheable cycles 1985system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020897 # mshr miss rate for ReadReq accesses 1986system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.075936 # mshr miss rate for ReadReq accesses 1987system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.026391 # mshr miss rate for ReadReq accesses 1988system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.358901 # mshr miss rate for ReadReq accesses 1989system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.079449 # mshr miss rate for ReadReq accesses |
| 1955system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1956system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1990system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1991system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1957system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.947996 # mshr miss rate for UpgradeReq accesses 1958system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.947996 # mshr miss rate for UpgradeReq accesses 1959system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.958863 # mshr miss rate for SCUpgradeReq accesses 1960system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.958863 # mshr miss rate for SCUpgradeReq accesses 1961system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1962system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1963system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.546801 # mshr miss rate for ReadExReq accesses 1964system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.546801 # mshr miss rate for ReadExReq accesses 1965system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022542 # mshr miss rate for demand accesses 1966system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.078037 # mshr miss rate for demand accesses 1967system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.022093 # mshr miss rate for demand accesses 1968system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.439737 # mshr miss rate for demand accesses 1969system.cpu1.l2cache.demand_mshr_miss_rate::total 0.104183 # mshr miss rate for demand accesses 1970system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022542 # mshr miss rate for overall accesses 1971system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.078037 # mshr miss rate for overall accesses 1972system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.022093 # mshr miss rate for overall accesses 1973system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.439737 # mshr miss rate for overall accesses | 1992system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.936976 # mshr miss rate for UpgradeReq accesses 1993system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.936976 # mshr miss rate for UpgradeReq accesses 1994system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.955691 # mshr miss rate for SCUpgradeReq accesses 1995system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.955691 # mshr miss rate for SCUpgradeReq accesses 1996system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.482035 # mshr miss rate for ReadExReq accesses 1997system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.482035 # mshr miss rate for ReadExReq accesses 1998system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020897 # mshr miss rate for demand accesses 1999system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.075936 # mshr miss rate for demand accesses 2000system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026391 # mshr miss rate for demand accesses 2001system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.391744 # mshr miss rate for demand accesses 2002system.cpu1.l2cache.demand_mshr_miss_rate::total 0.101546 # mshr miss rate for demand accesses 2003system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020897 # mshr miss rate for overall accesses 2004system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.075936 # mshr miss rate for overall accesses 2005system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026391 # mshr miss rate for overall accesses 2006system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.391744 # mshr miss rate for overall accesses |
| 1974system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 2007system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1975system.cpu1.l2cache.overall_mshr_miss_rate::total 0.123779 # mshr miss rate for overall accesses 1976system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average ReadReq mshr miss latency 1977system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average ReadReq mshr miss latency 1978system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average ReadReq mshr miss latency 1979system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15573.986058 # average ReadReq mshr miss latency 1980system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18476.484941 # average ReadReq mshr miss latency 1981system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42252.287771 # average HardPFReq mshr miss latency 1982system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 42252.287771 # average HardPFReq mshr miss latency 1983system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15940.014772 # average UpgradeReq mshr miss latency 1984system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15940.014772 # average UpgradeReq mshr miss latency 1985system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15081.828305 # average SCUpgradeReq mshr miss latency 1986system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15081.828305 # average SCUpgradeReq mshr miss latency 1987system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 97000 # average SCUpgradeFailReq mshr miss latency 1988system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 97000 # average SCUpgradeFailReq mshr miss latency 1989system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32781.531259 # average ReadExReq mshr miss latency 1990system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32781.531259 # average ReadExReq mshr miss latency 1991system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average overall mshr miss latency 1992system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average overall mshr miss latency 1993system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average overall mshr miss latency 1994system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21167.321458 # average overall mshr miss latency 1995system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22327.514398 # average overall mshr miss latency 1996system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average overall mshr miss latency 1997system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average overall mshr miss latency 1998system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average overall mshr miss latency 1999system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21167.321458 # average overall mshr miss latency 2000system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42252.287771 # average overall mshr miss latency 2001system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25481.924738 # average overall mshr miss latency 2002system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2003system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2004system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2005system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2006system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2007system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2008system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2009system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 2008system.cpu1.l2cache.overall_mshr_miss_rate::total 0.127580 # mshr miss rate for overall accesses 2009system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932 # average ReadReq mshr miss latency 2010system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534 # average ReadReq mshr miss latency 2011system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 32766.114878 # average ReadReq mshr miss latency 2012system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 16899.951851 # average ReadReq mshr miss latency 2013system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21182.658462 # average ReadReq mshr miss latency 2014system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36122.588756 # average HardPFReq mshr miss latency 2015system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36122.588756 # average HardPFReq mshr miss latency 2016system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16664.330725 # average UpgradeReq mshr miss latency 2017system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16664.330725 # average UpgradeReq mshr miss latency 2018system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15034.151160 # average SCUpgradeReq mshr miss latency 2019system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15034.151160 # average SCUpgradeReq mshr miss latency 2020system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency 2021system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 2022system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32245.566240 # average ReadExReq mshr miss latency 2023system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32245.566240 # average ReadExReq mshr miss latency 2024system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932 # average overall mshr miss latency 2025system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534 # average overall mshr miss latency 2026system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32766.114878 # average overall mshr miss latency 2027system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21936.337984 # average overall mshr miss latency 2028system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24065.183685 # average overall mshr miss latency 2029system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932 # average overall mshr miss latency 2030system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534 # average overall mshr miss latency 2031system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32766.114878 # average overall mshr miss latency 2032system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21936.337984 # average overall mshr miss latency 2033system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36122.588756 # average overall mshr miss latency 2034system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26525.578216 # average overall mshr miss latency 2035system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83821.428571 # average ReadReq mshr uncacheable latency 2036system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163134.141008 # average ReadReq mshr uncacheable latency 2037system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161609.943377 # average ReadReq mshr uncacheable latency 2038system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161902.894012 # average WriteReq mshr uncacheable latency 2039system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161902.894012 # average WriteReq mshr uncacheable latency 2040system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83821.428571 # average overall mshr uncacheable latency 2041system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162559.038691 # average overall mshr uncacheable latency 2042system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161745.363443 # average overall mshr uncacheable latency |
| 2010system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 2043system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2011system.cpu1.toL2Bus.trans_dist::ReadReq 1546268 # Transaction distribution 2012system.cpu1.toL2Bus.trans_dist::ReadResp 1215347 # Transaction distribution 2013system.cpu1.toL2Bus.trans_dist::WriteReq 11936 # Transaction distribution 2014system.cpu1.toL2Bus.trans_dist::WriteResp 11936 # Transaction distribution 2015system.cpu1.toL2Bus.trans_dist::Writeback 119475 # Transaction distribution 2016system.cpu1.toL2Bus.trans_dist::HardPFReq 29668 # Transaction distribution 2017system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution 2018system.cpu1.toL2Bus.trans_dist::UpgradeReq 76508 # Transaction distribution 2019system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42110 # Transaction distribution 2020system.cpu1.toL2Bus.trans_dist::UpgradeResp 86467 # Transaction distribution 2021system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution 2022system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution 2023system.cpu1.toL2Bus.trans_dist::ReadExReq 85086 # Transaction distribution 2024system.cpu1.toL2Bus.trans_dist::ReadExResp 67037 # Transaction distribution 2025system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1896584 # Packet count per connected master and slave (bytes) 2026system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 833808 # Packet count per connected master and slave (bytes) 2027system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7155 # Packet count per connected master and slave (bytes) 2028system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62301 # Packet count per connected master and slave (bytes) 2029system.cpu1.toL2Bus.pkt_count::total 2799848 # Packet count per connected master and slave (bytes) 2030system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60690688 # Cumulative packet size per connected master and slave (bytes) 2031system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25792980 # Cumulative packet size per connected master and slave (bytes) 2032system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11328 # Cumulative packet size per connected master and slave (bytes) 2033system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 116228 # Cumulative packet size per connected master and slave (bytes) 2034system.cpu1.toL2Bus.pkt_size::total 86611224 # Cumulative packet size per connected master and slave (bytes) 2035system.cpu1.toL2Bus.snoops 603822 # Total snoops (count) 2036system.cpu1.toL2Bus.snoop_fanout::samples 1920664 # Request fanout histogram 2037system.cpu1.toL2Bus.snoop_fanout::mean 3.272089 # Request fanout histogram 2038system.cpu1.toL2Bus.snoop_fanout::stdev 0.445035 # Request fanout histogram | 2044system.cpu1.toL2Bus.trans_dist::ReadReq 1679463 # Transaction distribution 2045system.cpu1.toL2Bus.trans_dist::ReadResp 1332654 # Transaction distribution 2046system.cpu1.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution 2047system.cpu1.toL2Bus.trans_dist::WriteResp 5010 # Transaction distribution 2048system.cpu1.toL2Bus.trans_dist::Writeback 138038 # Transaction distribution 2049system.cpu1.toL2Bus.trans_dist::HardPFReq 44141 # Transaction distribution 2050system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution 2051system.cpu1.toL2Bus.trans_dist::UpgradeReq 76606 # Transaction distribution 2052system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42998 # Transaction distribution 2053system.cpu1.toL2Bus.trans_dist::UpgradeResp 89660 # Transaction distribution 2054system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution 2055system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution 2056system.cpu1.toL2Bus.trans_dist::ReadExReq 97798 # Transaction distribution 2057system.cpu1.toL2Bus.trans_dist::ReadExResp 80302 # Transaction distribution 2058system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2078912 # Packet count per connected master and slave (bytes) 2059system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 908693 # Packet count per connected master and slave (bytes) 2060system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7242 # Packet count per connected master and slave (bytes) 2061system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 71512 # Packet count per connected master and slave (bytes) 2062system.cpu1.toL2Bus.pkt_count::total 3066359 # Packet count per connected master and slave (bytes) 2063system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66525184 # Cumulative packet size per connected master and slave (bytes) 2064system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29710243 # Cumulative packet size per connected master and slave (bytes) 2065system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11536 # Cumulative packet size per connected master and slave (bytes) 2066system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 135140 # Cumulative packet size per connected master and slave (bytes) 2067system.cpu1.toL2Bus.pkt_size::total 96382103 # Cumulative packet size per connected master and slave (bytes) 2068system.cpu1.toL2Bus.snoops 669363 # Total snoops (count) 2069system.cpu1.toL2Bus.snoop_fanout::samples 2146516 # Request fanout histogram 2070system.cpu1.toL2Bus.snoop_fanout::mean 1.290923 # Request fanout histogram 2071system.cpu1.toL2Bus.snoop_fanout::stdev 0.454188 # Request fanout histogram |
| 2039system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2040system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 2072system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2073system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 2041system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2042system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2043system.cpu1.toL2Bus.snoop_fanout::3 1398073 72.79% 72.79% # Request fanout histogram 2044system.cpu1.toL2Bus.snoop_fanout::4 522591 27.21% 100.00% # Request fanout histogram | 2074system.cpu1.toL2Bus.snoop_fanout::1 1522045 70.91% 70.91% # Request fanout histogram 2075system.cpu1.toL2Bus.snoop_fanout::2 624471 29.09% 100.00% # Request fanout histogram |
| 2045system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 2076system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 2046system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 2047system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 2048system.cpu1.toL2Bus.snoop_fanout::total 1920664 # Request fanout histogram 2049system.cpu1.toL2Bus.reqLayer0.occupancy 837814982 # Layer occupancy (ticks) | 2077system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2078system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2079system.cpu1.toL2Bus.snoop_fanout::total 2146516 # Request fanout histogram 2080system.cpu1.toL2Bus.reqLayer0.occupancy 922622470 # Layer occupancy (ticks) |
| 2050system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 2081system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 2051system.cpu1.toL2Bus.snoopLayer0.occupancy 80458500 # Layer occupancy (ticks) | 2082system.cpu1.toL2Bus.snoopLayer0.occupancy 87676498 # Layer occupancy (ticks) |
| 2052system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2083system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2053system.cpu1.toL2Bus.respLayer0.occupancy 1423116171 # Layer occupancy (ticks) | 2084system.cpu1.toL2Bus.respLayer0.occupancy 1560397383 # Layer occupancy (ticks) |
| 2054system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 2085system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 2055system.cpu1.toL2Bus.respLayer1.occupancy 410915491 # Layer occupancy (ticks) | 2086system.cpu1.toL2Bus.respLayer1.occupancy 459276108 # Layer occupancy (ticks) |
| 2056system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 2087system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 2057system.cpu1.toL2Bus.respLayer2.occupancy 4323500 # Layer occupancy (ticks) | 2088system.cpu1.toL2Bus.respLayer2.occupancy 4359499 # Layer occupancy (ticks) |
| 2058system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 2089system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2059system.cpu1.toL2Bus.respLayer3.occupancy 33252737 # Layer occupancy (ticks) | 2090system.cpu1.toL2Bus.respLayer3.occupancy 37739490 # Layer occupancy (ticks) |
| 2060system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2091system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2061system.iobus.trans_dist::ReadReq 31003 # Transaction distribution 2062system.iobus.trans_dist::ReadResp 31003 # Transaction distribution | 2092system.iobus.trans_dist::ReadReq 30987 # Transaction distribution 2093system.iobus.trans_dist::ReadResp 30987 # Transaction distribution |
| 2063system.iobus.trans_dist::WriteReq 59422 # Transaction distribution 2064system.iobus.trans_dist::WriteResp 23198 # Transaction distribution 2065system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 2066system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) 2067system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2068system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2069system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2070system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) | 2094system.iobus.trans_dist::WriteReq 59422 # Transaction distribution 2095system.iobus.trans_dist::WriteResp 23198 # Transaction distribution 2096system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 2097system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) 2098system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2099system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2100system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2101system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) |
| 2071system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) | 2102system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) |
| 2072system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2073system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2074system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2075system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2076system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2077system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2078system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2079system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2080system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2081system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2082system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2083system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2084system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2085system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2086system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 2103system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2104system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2105system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2106system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2107system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2108system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2109system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2110system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2111system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2112system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2113system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2114system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2115system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2116system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2117system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 2087system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) 2088system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) 2089system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) 2090system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes) | 2118system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) 2119system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72906 # Packet count per connected master and slave (bytes) 2120system.iobus.pkt_count_system.realview.ide.dma::total 72906 # Packet count per connected master and slave (bytes) 2121system.iobus.pkt_count::total 180818 # Packet count per connected master and slave (bytes) |
| 2091system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) 2092system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2093system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2094system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2095system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) | 2122system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) 2123system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2124system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2125system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2126system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) |
| 2096system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) | 2127system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) |
| 2097system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2098system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2099system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2100system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2101system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2102system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2103system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2104system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2105system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2106system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2107system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2108system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 2109system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2110system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 2111system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | 2128system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2129system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2130system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2131system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2132system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2133system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2134system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2135system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2136system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2137system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2138system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2139system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 2140system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2141system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 2142system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 2112system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) 2113system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) 2114system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) 2115system.iobus.pkt_size::total 2483972 # Cumulative packet size per connected master and slave (bytes) | 2143system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) 2144system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321064 # Cumulative packet size per connected master and slave (bytes) 2145system.iobus.pkt_size_system.realview.ide.dma::total 2321064 # Cumulative packet size per connected master and slave (bytes) 2146system.iobus.pkt_size::total 2483858 # Cumulative packet size per connected master and slave (bytes) |
| 2116system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) 2117system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2118system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 2119system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2120system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 2121system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2122system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 2123system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2124system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 2125system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) | 2147system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) 2148system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2149system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 2150system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2151system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 2152system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2153system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 2154system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2155system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 2156system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) |
| 2126system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) | 2157system.iobus.reqLayer7.occupancy 504000 # Layer occupancy (ticks) |
| 2127system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2128system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 2129system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2130system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2131system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2132system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2133system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2134system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) --- 13 unchanged lines hidden (view full) --- 2148system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2149system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2150system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2151system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2152system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2153system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2154system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2155system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 2158system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2159system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 2160system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2161system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2162system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2163system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2164system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2165system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) --- 13 unchanged lines hidden (view full) --- 2179system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2180system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2181system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2182system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2183system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2184system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2185system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2186system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 2156system.iobus.reqLayer27.occupancy 198973953 # Layer occupancy (ticks) | 2187system.iobus.reqLayer27.occupancy 198858516 # Layer occupancy (ticks) |
| 2157system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2158system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2159system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 2188system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2189system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2190system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 2160system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) | 2191system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks) |
| 2161system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 2192system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2162system.iobus.respLayer3.occupancy 36786758 # Layer occupancy (ticks) | 2193system.iobus.respLayer3.occupancy 36733518 # Layer occupancy (ticks) |
| 2163system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 2194system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2164system.iocache.tags.replacements 36449 # number of replacements 2165system.iocache.tags.tagsinuse 14.479940 # Cycle average of tags in use | 2195system.iocache.tags.replacements 36403 # number of replacements 2196system.iocache.tags.tagsinuse 1.010559 # Cycle average of tags in use |
| 2166system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 2197system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 2167system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. | 2198system.iocache.tags.sampled_refs 36419 # Sample count of references to valid blocks. |
| 2168system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 2199system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 2169system.iocache.tags.warmup_cycle 270378265000 # Cycle when the warmup percentage was hit. 2170system.iocache.tags.occ_blocks::realview.ide 14.479940 # Average occupied blocks per requestor 2171system.iocache.tags.occ_percent::realview.ide 0.904996 # Average percentage of cache occupancy 2172system.iocache.tags.occ_percent::total 0.904996 # Average percentage of cache occupancy | 2200system.iocache.tags.warmup_cycle 270375766000 # Cycle when the warmup percentage was hit. 2201system.iocache.tags.occ_blocks::realview.ide 1.010559 # Average occupied blocks per requestor 2202system.iocache.tags.occ_percent::realview.ide 0.063160 # Average percentage of cache occupancy 2203system.iocache.tags.occ_percent::total 0.063160 # Average percentage of cache occupancy |
| 2173system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2174system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2175system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 2204system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2205system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2206system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 2176system.iocache.tags.tag_accesses 328203 # Number of tag accesses 2177system.iocache.tags.data_accesses 328203 # Number of data accesses 2178system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses 2179system.iocache.ReadReq_misses::total 243 # number of ReadReq misses | 2207system.iocache.tags.tag_accesses 328077 # Number of tag accesses 2208system.iocache.tags.data_accesses 328077 # Number of data accesses 2209system.iocache.ReadReq_misses::realview.ide 229 # number of ReadReq misses 2210system.iocache.ReadReq_misses::total 229 # number of ReadReq misses |
| 2180system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 2181system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses | 2211system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 2212system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses |
| 2182system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses 2183system.iocache.demand_misses::total 243 # number of demand (read+write) misses 2184system.iocache.overall_misses::realview.ide 243 # number of overall misses 2185system.iocache.overall_misses::total 243 # number of overall misses 2186system.iocache.ReadReq_miss_latency::realview.ide 31380127 # number of ReadReq miss cycles 2187system.iocache.ReadReq_miss_latency::total 31380127 # number of ReadReq miss cycles 2188system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6638963068 # number of WriteInvalidateReq miss cycles 2189system.iocache.WriteInvalidateReq_miss_latency::total 6638963068 # number of WriteInvalidateReq miss cycles 2190system.iocache.demand_miss_latency::realview.ide 31380127 # number of demand (read+write) miss cycles 2191system.iocache.demand_miss_latency::total 31380127 # number of demand (read+write) miss cycles 2192system.iocache.overall_miss_latency::realview.ide 31380127 # number of overall miss cycles 2193system.iocache.overall_miss_latency::total 31380127 # number of overall miss cycles 2194system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) 2195system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) | 2213system.iocache.demand_misses::realview.ide 229 # number of demand (read+write) misses 2214system.iocache.demand_misses::total 229 # number of demand (read+write) misses 2215system.iocache.overall_misses::realview.ide 229 # number of overall misses 2216system.iocache.overall_misses::total 229 # number of overall misses 2217system.iocache.ReadReq_miss_latency::realview.ide 29476377 # number of ReadReq miss cycles 2218system.iocache.ReadReq_miss_latency::total 29476377 # number of ReadReq miss cycles 2219system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6677842621 # number of WriteInvalidateReq miss cycles 2220system.iocache.WriteInvalidateReq_miss_latency::total 6677842621 # number of WriteInvalidateReq miss cycles 2221system.iocache.demand_miss_latency::realview.ide 29476377 # number of demand (read+write) miss cycles 2222system.iocache.demand_miss_latency::total 29476377 # number of demand (read+write) miss cycles 2223system.iocache.overall_miss_latency::realview.ide 29476377 # number of overall miss cycles 2224system.iocache.overall_miss_latency::total 29476377 # number of overall miss cycles 2225system.iocache.ReadReq_accesses::realview.ide 229 # number of ReadReq accesses(hits+misses) 2226system.iocache.ReadReq_accesses::total 229 # number of ReadReq accesses(hits+misses) |
| 2196system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 2197system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) | 2227system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 2228system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) |
| 2198system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses 2199system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses 2200system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses 2201system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses | 2229system.iocache.demand_accesses::realview.ide 229 # number of demand (read+write) accesses 2230system.iocache.demand_accesses::total 229 # number of demand (read+write) accesses 2231system.iocache.overall_accesses::realview.ide 229 # number of overall (read+write) accesses 2232system.iocache.overall_accesses::total 229 # number of overall (read+write) accesses |
| 2202system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2203system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2204system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2205system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2206system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2207system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2208system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2209system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 2233system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2234system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2235system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2236system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2237system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2238system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2239system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2240system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 2210system.iocache.ReadReq_avg_miss_latency::realview.ide 129136.325103 # average ReadReq miss latency 2211system.iocache.ReadReq_avg_miss_latency::total 129136.325103 # average ReadReq miss latency 2212system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183275.261374 # average WriteInvalidateReq miss latency 2213system.iocache.WriteInvalidateReq_avg_miss_latency::total 183275.261374 # average WriteInvalidateReq miss latency 2214system.iocache.demand_avg_miss_latency::realview.ide 129136.325103 # average overall miss latency 2215system.iocache.demand_avg_miss_latency::total 129136.325103 # average overall miss latency 2216system.iocache.overall_avg_miss_latency::realview.ide 129136.325103 # average overall miss latency 2217system.iocache.overall_avg_miss_latency::total 129136.325103 # average overall miss latency 2218system.iocache.blocked_cycles::no_mshrs 22458 # number of cycles access was blocked | 2241system.iocache.ReadReq_avg_miss_latency::realview.ide 128717.803493 # average ReadReq miss latency 2242system.iocache.ReadReq_avg_miss_latency::total 128717.803493 # average ReadReq miss latency 2243system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 184348.570589 # average WriteInvalidateReq miss latency 2244system.iocache.WriteInvalidateReq_avg_miss_latency::total 184348.570589 # average WriteInvalidateReq miss latency 2245system.iocache.demand_avg_miss_latency::realview.ide 128717.803493 # average overall miss latency 2246system.iocache.demand_avg_miss_latency::total 128717.803493 # average overall miss latency 2247system.iocache.overall_avg_miss_latency::realview.ide 128717.803493 # average overall miss latency 2248system.iocache.overall_avg_miss_latency::total 128717.803493 # average overall miss latency 2249system.iocache.blocked_cycles::no_mshrs 23020 # number of cycles access was blocked |
| 2219system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2250system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2220system.iocache.blocked::no_mshrs 3415 # number of cycles access was blocked | 2251system.iocache.blocked::no_mshrs 3484 # number of cycles access was blocked |
| 2221system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 2252system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 2222system.iocache.avg_blocked_cycles::no_mshrs 6.576281 # average number of cycles each access was blocked | 2253system.iocache.avg_blocked_cycles::no_mshrs 6.607348 # average number of cycles each access was blocked |
| 2223system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2224system.iocache.fast_writes 0 # number of fast writes performed 2225system.iocache.cache_copies 0 # number of cache copies performed | 2254system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2255system.iocache.fast_writes 0 # number of fast writes performed 2256system.iocache.cache_copies 0 # number of cache copies performed |
| 2226system.iocache.writebacks::writebacks 36206 # number of writebacks 2227system.iocache.writebacks::total 36206 # number of writebacks 2228system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses 2229system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses | 2257system.iocache.writebacks::writebacks 36174 # number of writebacks 2258system.iocache.writebacks::total 36174 # number of writebacks 2259system.iocache.ReadReq_mshr_misses::realview.ide 229 # number of ReadReq MSHR misses 2260system.iocache.ReadReq_mshr_misses::total 229 # number of ReadReq MSHR misses |
| 2230system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 2231system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses | 2261system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 2262system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses |
| 2232system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses 2233system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses 2234system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses 2235system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses 2236system.iocache.ReadReq_mshr_miss_latency::realview.ide 18685627 # number of ReadReq MSHR miss cycles 2237system.iocache.ReadReq_mshr_miss_latency::total 18685627 # number of ReadReq MSHR miss cycles 2238system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4755299084 # number of WriteInvalidateReq MSHR miss cycles 2239system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4755299084 # number of WriteInvalidateReq MSHR miss cycles 2240system.iocache.demand_mshr_miss_latency::realview.ide 18685627 # number of demand (read+write) MSHR miss cycles 2241system.iocache.demand_mshr_miss_latency::total 18685627 # number of demand (read+write) MSHR miss cycles 2242system.iocache.overall_mshr_miss_latency::realview.ide 18685627 # number of overall MSHR miss cycles 2243system.iocache.overall_mshr_miss_latency::total 18685627 # number of overall MSHR miss cycles | 2263system.iocache.demand_mshr_misses::realview.ide 229 # number of demand (read+write) MSHR misses 2264system.iocache.demand_mshr_misses::total 229 # number of demand (read+write) MSHR misses 2265system.iocache.overall_mshr_misses::realview.ide 229 # number of overall MSHR misses 2266system.iocache.overall_mshr_misses::total 229 # number of overall MSHR misses 2267system.iocache.ReadReq_mshr_miss_latency::realview.ide 17561377 # number of ReadReq MSHR miss cycles 2268system.iocache.ReadReq_mshr_miss_latency::total 17561377 # number of ReadReq MSHR miss cycles 2269system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4794158657 # number of WriteInvalidateReq MSHR miss cycles 2270system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4794158657 # number of WriteInvalidateReq MSHR miss cycles 2271system.iocache.demand_mshr_miss_latency::realview.ide 17561377 # number of demand (read+write) MSHR miss cycles 2272system.iocache.demand_mshr_miss_latency::total 17561377 # number of demand (read+write) MSHR miss cycles 2273system.iocache.overall_mshr_miss_latency::realview.ide 17561377 # number of overall MSHR miss cycles 2274system.iocache.overall_mshr_miss_latency::total 17561377 # number of overall MSHR miss cycles |
| 2244system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2245system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2246system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2247system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 2248system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2249system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2250system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2251system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 2275system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2276system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2277system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2278system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 2279system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2280system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2281system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2282system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 2252system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76895.584362 # average ReadReq mshr miss latency 2253system.iocache.ReadReq_avg_mshr_miss_latency::total 76895.584362 # average ReadReq mshr miss latency 2254system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131274.820119 # average WriteInvalidateReq mshr miss latency 2255system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131274.820119 # average WriteInvalidateReq mshr miss latency 2256system.iocache.demand_avg_mshr_miss_latency::realview.ide 76895.584362 # average overall mshr miss latency 2257system.iocache.demand_avg_mshr_miss_latency::total 76895.584362 # average overall mshr miss latency 2258system.iocache.overall_avg_mshr_miss_latency::realview.ide 76895.584362 # average overall mshr miss latency 2259system.iocache.overall_avg_mshr_miss_latency::total 76895.584362 # average overall mshr miss latency | 2283system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76687.235808 # average ReadReq mshr miss latency 2284system.iocache.ReadReq_avg_mshr_miss_latency::total 76687.235808 # average ReadReq mshr miss latency 2285system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 132347.577766 # average WriteInvalidateReq mshr miss latency 2286system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 132347.577766 # average WriteInvalidateReq mshr miss latency 2287system.iocache.demand_avg_mshr_miss_latency::realview.ide 76687.235808 # average overall mshr miss latency 2288system.iocache.demand_avg_mshr_miss_latency::total 76687.235808 # average overall mshr miss latency 2289system.iocache.overall_avg_mshr_miss_latency::realview.ide 76687.235808 # average overall mshr miss latency 2290system.iocache.overall_avg_mshr_miss_latency::total 76687.235808 # average overall mshr miss latency |
| 2260system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 2291system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2261system.l2c.tags.replacements 135638 # number of replacements 2262system.l2c.tags.tagsinuse 64035.864385 # Cycle average of tags in use 2263system.l2c.tags.total_refs 380564 # Total number of references to valid blocks. 2264system.l2c.tags.sampled_refs 200114 # Sample count of references to valid blocks. 2265system.l2c.tags.avg_refs 1.901736 # Average number of references to valid blocks. | 2292system.l2c.tags.replacements 136197 # number of replacements 2293system.l2c.tags.tagsinuse 64163.282922 # Cycle average of tags in use 2294system.l2c.tags.total_refs 379817 # Total number of references to valid blocks. 2295system.l2c.tags.sampled_refs 200471 # Sample count of references to valid blocks. 2296system.l2c.tags.avg_refs 1.894623 # Average number of references to valid blocks. |
| 2266system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2297system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2267system.l2c.tags.occ_blocks::writebacks 12087.017372 # Average occupied blocks per requestor 2268system.l2c.tags.occ_blocks::cpu0.dtb.walker 77.160254 # Average occupied blocks per requestor 2269system.l2c.tags.occ_blocks::cpu0.itb.walker 0.033685 # Average occupied blocks per requestor 2270system.l2c.tags.occ_blocks::cpu0.inst 8509.496822 # Average occupied blocks per requestor 2271system.l2c.tags.occ_blocks::cpu0.data 2877.165248 # Average occupied blocks per requestor 2272system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35676.414678 # Average occupied blocks per requestor 2273system.l2c.tags.occ_blocks::cpu1.dtb.walker 13.500349 # Average occupied blocks per requestor 2274system.l2c.tags.occ_blocks::cpu1.inst 2186.391247 # Average occupied blocks per requestor 2275system.l2c.tags.occ_blocks::cpu1.data 567.991773 # Average occupied blocks per requestor 2276system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2040.692959 # Average occupied blocks per requestor 2277system.l2c.tags.occ_percent::writebacks 0.184433 # Average percentage of cache occupancy 2278system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001177 # Average percentage of cache occupancy 2279system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 2280system.l2c.tags.occ_percent::cpu0.inst 0.129845 # Average percentage of cache occupancy 2281system.l2c.tags.occ_percent::cpu0.data 0.043902 # Average percentage of cache occupancy 2282system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.544379 # Average percentage of cache occupancy 2283system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000206 # Average percentage of cache occupancy 2284system.l2c.tags.occ_percent::cpu1.inst 0.033362 # Average percentage of cache occupancy 2285system.l2c.tags.occ_percent::cpu1.data 0.008667 # Average percentage of cache occupancy 2286system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.031139 # Average percentage of cache occupancy 2287system.l2c.tags.occ_percent::total 0.977110 # Average percentage of cache occupancy 2288system.l2c.tags.occ_task_id_blocks::1022 30037 # Occupied blocks per task id 2289system.l2c.tags.occ_task_id_blocks::1023 48 # Occupied blocks per task id 2290system.l2c.tags.occ_task_id_blocks::1024 34391 # Occupied blocks per task id 2291system.l2c.tags.age_task_id_blocks_1022::2 135 # Occupied blocks per task id 2292system.l2c.tags.age_task_id_blocks_1022::3 4776 # Occupied blocks per task id 2293system.l2c.tags.age_task_id_blocks_1022::4 25126 # Occupied blocks per task id 2294system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 2295system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id 2296system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 2297system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id | 2298system.l2c.tags.occ_blocks::writebacks 12850.317421 # Average occupied blocks per requestor 2299system.l2c.tags.occ_blocks::cpu0.dtb.walker 69.201711 # Average occupied blocks per requestor 2300system.l2c.tags.occ_blocks::cpu0.itb.walker 0.031095 # Average occupied blocks per requestor 2301system.l2c.tags.occ_blocks::cpu0.inst 6628.601764 # Average occupied blocks per requestor 2302system.l2c.tags.occ_blocks::cpu0.data 1957.826461 # Average occupied blocks per requestor 2303system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32727.538139 # Average occupied blocks per requestor 2304system.l2c.tags.occ_blocks::cpu1.dtb.walker 28.180445 # Average occupied blocks per requestor 2305system.l2c.tags.occ_blocks::cpu1.itb.walker 0.851989 # Average occupied blocks per requestor 2306system.l2c.tags.occ_blocks::cpu1.inst 4115.294958 # Average occupied blocks per requestor 2307system.l2c.tags.occ_blocks::cpu1.data 1518.513926 # Average occupied blocks per requestor 2308system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4266.925013 # Average occupied blocks per requestor 2309system.l2c.tags.occ_percent::writebacks 0.196080 # Average percentage of cache occupancy 2310system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001056 # Average percentage of cache occupancy 2311system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 2312system.l2c.tags.occ_percent::cpu0.inst 0.101144 # Average percentage of cache occupancy 2313system.l2c.tags.occ_percent::cpu0.data 0.029874 # Average percentage of cache occupancy 2314system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.499383 # Average percentage of cache occupancy 2315system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000430 # Average percentage of cache occupancy 2316system.l2c.tags.occ_percent::cpu1.itb.walker 0.000013 # Average percentage of cache occupancy 2317system.l2c.tags.occ_percent::cpu1.inst 0.062794 # Average percentage of cache occupancy 2318system.l2c.tags.occ_percent::cpu1.data 0.023171 # Average percentage of cache occupancy 2319system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.065108 # Average percentage of cache occupancy 2320system.l2c.tags.occ_percent::total 0.979054 # Average percentage of cache occupancy 2321system.l2c.tags.occ_task_id_blocks::1022 30066 # Occupied blocks per task id 2322system.l2c.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id 2323system.l2c.tags.occ_task_id_blocks::1024 34130 # Occupied blocks per task id 2324system.l2c.tags.age_task_id_blocks_1022::2 141 # Occupied blocks per task id 2325system.l2c.tags.age_task_id_blocks_1022::3 5589 # Occupied blocks per task id 2326system.l2c.tags.age_task_id_blocks_1022::4 24336 # Occupied blocks per task id 2327system.l2c.tags.age_task_id_blocks_1023::4 78 # Occupied blocks per task id 2328system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 2329system.l2c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id |
| 2298system.l2c.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id | 2330system.l2c.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id |
| 2299system.l2c.tags.age_task_id_blocks_1024::3 3317 # Occupied blocks per task id 2300system.l2c.tags.age_task_id_blocks_1024::4 30762 # Occupied blocks per task id 2301system.l2c.tags.occ_task_id_percent::1022 0.458328 # Percentage of cache occupancy per task id 2302system.l2c.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id 2303system.l2c.tags.occ_task_id_percent::1024 0.524765 # Percentage of cache occupancy per task id 2304system.l2c.tags.tag_accesses 5287806 # Number of tag accesses 2305system.l2c.tags.data_accesses 5287806 # Number of data accesses 2306system.l2c.ReadReq_hits::cpu0.dtb.walker 444 # number of ReadReq hits 2307system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits 2308system.l2c.ReadReq_hits::cpu0.inst 48461 # number of ReadReq hits 2309system.l2c.ReadReq_hits::cpu0.data 49558 # number of ReadReq hits 2310system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 47653 # number of ReadReq hits 2311system.l2c.ReadReq_hits::cpu1.dtb.walker 127 # number of ReadReq hits 2312system.l2c.ReadReq_hits::cpu1.itb.walker 25 # number of ReadReq hits 2313system.l2c.ReadReq_hits::cpu1.inst 17654 # number of ReadReq hits 2314system.l2c.ReadReq_hits::cpu1.data 9320 # number of ReadReq hits 2315system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 5533 # number of ReadReq hits 2316system.l2c.ReadReq_hits::total 178838 # number of ReadReq hits 2317system.l2c.Writeback_hits::writebacks 232835 # number of Writeback hits 2318system.l2c.Writeback_hits::total 232835 # number of Writeback hits 2319system.l2c.UpgradeReq_hits::cpu0.data 3130 # number of UpgradeReq hits 2320system.l2c.UpgradeReq_hits::cpu1.data 650 # number of UpgradeReq hits 2321system.l2c.UpgradeReq_hits::total 3780 # number of UpgradeReq hits 2322system.l2c.SCUpgradeReq_hits::cpu0.data 173 # number of SCUpgradeReq hits 2323system.l2c.SCUpgradeReq_hits::cpu1.data 165 # number of SCUpgradeReq hits | 2331system.l2c.tags.age_task_id_blocks_1024::3 3041 # Occupied blocks per task id 2332system.l2c.tags.age_task_id_blocks_1024::4 30776 # Occupied blocks per task id 2333system.l2c.tags.occ_task_id_percent::1022 0.458771 # Percentage of cache occupancy per task id 2334system.l2c.tags.occ_task_id_percent::1023 0.001190 # Percentage of cache occupancy per task id 2335system.l2c.tags.occ_task_id_percent::1024 0.520782 # Percentage of cache occupancy per task id 2336system.l2c.tags.tag_accesses 5295828 # Number of tag accesses 2337system.l2c.tags.data_accesses 5295828 # Number of data accesses 2338system.l2c.ReadReq_hits::cpu0.dtb.walker 375 # number of ReadReq hits 2339system.l2c.ReadReq_hits::cpu0.itb.walker 73 # number of ReadReq hits 2340system.l2c.ReadReq_hits::cpu0.inst 43717 # number of ReadReq hits 2341system.l2c.ReadReq_hits::cpu0.data 47365 # number of ReadReq hits 2342system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 45781 # number of ReadReq hits 2343system.l2c.ReadReq_hits::cpu1.dtb.walker 167 # number of ReadReq hits 2344system.l2c.ReadReq_hits::cpu1.itb.walker 27 # number of ReadReq hits 2345system.l2c.ReadReq_hits::cpu1.inst 21454 # number of ReadReq hits 2346system.l2c.ReadReq_hits::cpu1.data 10985 # number of ReadReq hits 2347system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 8059 # number of ReadReq hits 2348system.l2c.ReadReq_hits::total 178003 # number of ReadReq hits 2349system.l2c.Writeback_hits::writebacks 233506 # number of Writeback hits 2350system.l2c.Writeback_hits::total 233506 # number of Writeback hits 2351system.l2c.UpgradeReq_hits::cpu0.data 2927 # number of UpgradeReq hits 2352system.l2c.UpgradeReq_hits::cpu1.data 947 # number of UpgradeReq hits 2353system.l2c.UpgradeReq_hits::total 3874 # number of UpgradeReq hits 2354system.l2c.SCUpgradeReq_hits::cpu0.data 249 # number of SCUpgradeReq hits 2355system.l2c.SCUpgradeReq_hits::cpu1.data 89 # number of SCUpgradeReq hits |
| 2324system.l2c.SCUpgradeReq_hits::total 338 # number of SCUpgradeReq hits | 2356system.l2c.SCUpgradeReq_hits::total 338 # number of SCUpgradeReq hits |
| 2325system.l2c.ReadExReq_hits::cpu0.data 4192 # number of ReadExReq hits 2326system.l2c.ReadExReq_hits::cpu1.data 1733 # number of ReadExReq hits 2327system.l2c.ReadExReq_hits::total 5925 # number of ReadExReq hits 2328system.l2c.demand_hits::cpu0.dtb.walker 444 # number of demand (read+write) hits 2329system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits 2330system.l2c.demand_hits::cpu0.inst 48461 # number of demand (read+write) hits 2331system.l2c.demand_hits::cpu0.data 53750 # number of demand (read+write) hits 2332system.l2c.demand_hits::cpu0.l2cache.prefetcher 47653 # number of demand (read+write) hits 2333system.l2c.demand_hits::cpu1.dtb.walker 127 # number of demand (read+write) hits 2334system.l2c.demand_hits::cpu1.itb.walker 25 # number of demand (read+write) hits 2335system.l2c.demand_hits::cpu1.inst 17654 # number of demand (read+write) hits 2336system.l2c.demand_hits::cpu1.data 11053 # number of demand (read+write) hits 2337system.l2c.demand_hits::cpu1.l2cache.prefetcher 5533 # number of demand (read+write) hits 2338system.l2c.demand_hits::total 184763 # number of demand (read+write) hits 2339system.l2c.overall_hits::cpu0.dtb.walker 444 # number of overall hits 2340system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits 2341system.l2c.overall_hits::cpu0.inst 48461 # number of overall hits 2342system.l2c.overall_hits::cpu0.data 53750 # number of overall hits 2343system.l2c.overall_hits::cpu0.l2cache.prefetcher 47653 # number of overall hits 2344system.l2c.overall_hits::cpu1.dtb.walker 127 # number of overall hits 2345system.l2c.overall_hits::cpu1.itb.walker 25 # number of overall hits 2346system.l2c.overall_hits::cpu1.inst 17654 # number of overall hits 2347system.l2c.overall_hits::cpu1.data 11053 # number of overall hits 2348system.l2c.overall_hits::cpu1.l2cache.prefetcher 5533 # number of overall hits 2349system.l2c.overall_hits::total 184763 # number of overall hits 2350system.l2c.ReadReq_misses::cpu0.dtb.walker 146 # number of ReadReq misses 2351system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 2352system.l2c.ReadReq_misses::cpu0.inst 22747 # number of ReadReq misses 2353system.l2c.ReadReq_misses::cpu0.data 9845 # number of ReadReq misses 2354system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 132327 # number of ReadReq misses 2355system.l2c.ReadReq_misses::cpu1.dtb.walker 21 # number of ReadReq misses 2356system.l2c.ReadReq_misses::cpu1.inst 3294 # number of ReadReq misses 2357system.l2c.ReadReq_misses::cpu1.data 1096 # number of ReadReq misses 2358system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 6759 # number of ReadReq misses 2359system.l2c.ReadReq_misses::total 176237 # number of ReadReq misses 2360system.l2c.UpgradeReq_misses::cpu0.data 9250 # number of UpgradeReq misses 2361system.l2c.UpgradeReq_misses::cpu1.data 2916 # number of UpgradeReq misses 2362system.l2c.UpgradeReq_misses::total 12166 # number of UpgradeReq misses 2363system.l2c.SCUpgradeReq_misses::cpu0.data 671 # number of SCUpgradeReq misses 2364system.l2c.SCUpgradeReq_misses::cpu1.data 1253 # number of SCUpgradeReq misses 2365system.l2c.SCUpgradeReq_misses::total 1924 # number of SCUpgradeReq misses 2366system.l2c.ReadExReq_misses::cpu0.data 11244 # number of ReadExReq misses 2367system.l2c.ReadExReq_misses::cpu1.data 8399 # number of ReadExReq misses 2368system.l2c.ReadExReq_misses::total 19643 # number of ReadExReq misses 2369system.l2c.demand_misses::cpu0.dtb.walker 146 # number of demand (read+write) misses 2370system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 2371system.l2c.demand_misses::cpu0.inst 22747 # number of demand (read+write) misses 2372system.l2c.demand_misses::cpu0.data 21089 # number of demand (read+write) misses 2373system.l2c.demand_misses::cpu0.l2cache.prefetcher 132327 # number of demand (read+write) misses 2374system.l2c.demand_misses::cpu1.dtb.walker 21 # number of demand (read+write) misses 2375system.l2c.demand_misses::cpu1.inst 3294 # number of demand (read+write) misses 2376system.l2c.demand_misses::cpu1.data 9495 # number of demand (read+write) misses 2377system.l2c.demand_misses::cpu1.l2cache.prefetcher 6759 # number of demand (read+write) misses 2378system.l2c.demand_misses::total 195880 # number of demand (read+write) misses 2379system.l2c.overall_misses::cpu0.dtb.walker 146 # number of overall misses 2380system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 2381system.l2c.overall_misses::cpu0.inst 22747 # number of overall misses 2382system.l2c.overall_misses::cpu0.data 21089 # number of overall misses 2383system.l2c.overall_misses::cpu0.l2cache.prefetcher 132327 # number of overall misses 2384system.l2c.overall_misses::cpu1.dtb.walker 21 # number of overall misses 2385system.l2c.overall_misses::cpu1.inst 3294 # number of overall misses 2386system.l2c.overall_misses::cpu1.data 9495 # number of overall misses 2387system.l2c.overall_misses::cpu1.l2cache.prefetcher 6759 # number of overall misses 2388system.l2c.overall_misses::total 195880 # number of overall misses 2389system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 13322250 # number of ReadReq miss cycles 2390system.l2c.ReadReq_miss_latency::cpu0.itb.walker 165000 # number of ReadReq miss cycles 2391system.l2c.ReadReq_miss_latency::cpu0.inst 1836389560 # number of ReadReq miss cycles 2392system.l2c.ReadReq_miss_latency::cpu0.data 869862901 # number of ReadReq miss cycles 2393system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 13647658866 # number of ReadReq miss cycles 2394system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1878250 # number of ReadReq miss cycles 2395system.l2c.ReadReq_miss_latency::cpu1.inst 273761254 # number of ReadReq miss cycles 2396system.l2c.ReadReq_miss_latency::cpu1.data 100369500 # number of ReadReq miss cycles 2397system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 908948741 # number of ReadReq miss cycles 2398system.l2c.ReadReq_miss_latency::total 17652356322 # number of ReadReq miss cycles 2399system.l2c.UpgradeReq_miss_latency::cpu0.data 7104776 # number of UpgradeReq miss cycles 2400system.l2c.UpgradeReq_miss_latency::cpu1.data 3030406 # number of UpgradeReq miss cycles 2401system.l2c.UpgradeReq_miss_latency::total 10135182 # number of UpgradeReq miss cycles 2402system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1032472 # number of SCUpgradeReq miss cycles 2403system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1498952 # number of SCUpgradeReq miss cycles 2404system.l2c.SCUpgradeReq_miss_latency::total 2531424 # number of SCUpgradeReq miss cycles 2405system.l2c.ReadExReq_miss_latency::cpu0.data 1028146684 # number of ReadExReq miss cycles 2406system.l2c.ReadExReq_miss_latency::cpu1.data 690374730 # number of ReadExReq miss cycles 2407system.l2c.ReadExReq_miss_latency::total 1718521414 # number of ReadExReq miss cycles 2408system.l2c.demand_miss_latency::cpu0.dtb.walker 13322250 # number of demand (read+write) miss cycles 2409system.l2c.demand_miss_latency::cpu0.itb.walker 165000 # number of demand (read+write) miss cycles 2410system.l2c.demand_miss_latency::cpu0.inst 1836389560 # number of demand (read+write) miss cycles 2411system.l2c.demand_miss_latency::cpu0.data 1898009585 # number of demand (read+write) miss cycles 2412system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13647658866 # number of demand (read+write) miss cycles 2413system.l2c.demand_miss_latency::cpu1.dtb.walker 1878250 # number of demand (read+write) miss cycles 2414system.l2c.demand_miss_latency::cpu1.inst 273761254 # number of demand (read+write) miss cycles 2415system.l2c.demand_miss_latency::cpu1.data 790744230 # number of demand (read+write) miss cycles 2416system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 908948741 # number of demand (read+write) miss cycles 2417system.l2c.demand_miss_latency::total 19370877736 # number of demand (read+write) miss cycles 2418system.l2c.overall_miss_latency::cpu0.dtb.walker 13322250 # number of overall miss cycles 2419system.l2c.overall_miss_latency::cpu0.itb.walker 165000 # number of overall miss cycles 2420system.l2c.overall_miss_latency::cpu0.inst 1836389560 # number of overall miss cycles 2421system.l2c.overall_miss_latency::cpu0.data 1898009585 # number of overall miss cycles 2422system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13647658866 # number of overall miss cycles 2423system.l2c.overall_miss_latency::cpu1.dtb.walker 1878250 # number of overall miss cycles 2424system.l2c.overall_miss_latency::cpu1.inst 273761254 # number of overall miss cycles 2425system.l2c.overall_miss_latency::cpu1.data 790744230 # number of overall miss cycles 2426system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 908948741 # number of overall miss cycles 2427system.l2c.overall_miss_latency::total 19370877736 # number of overall miss cycles 2428system.l2c.ReadReq_accesses::cpu0.dtb.walker 590 # number of ReadReq accesses(hits+misses) 2429system.l2c.ReadReq_accesses::cpu0.itb.walker 65 # number of ReadReq accesses(hits+misses) 2430system.l2c.ReadReq_accesses::cpu0.inst 71208 # number of ReadReq accesses(hits+misses) 2431system.l2c.ReadReq_accesses::cpu0.data 59403 # number of ReadReq accesses(hits+misses) 2432system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 179980 # number of ReadReq accesses(hits+misses) 2433system.l2c.ReadReq_accesses::cpu1.dtb.walker 148 # number of ReadReq accesses(hits+misses) 2434system.l2c.ReadReq_accesses::cpu1.itb.walker 25 # number of ReadReq accesses(hits+misses) 2435system.l2c.ReadReq_accesses::cpu1.inst 20948 # number of ReadReq accesses(hits+misses) 2436system.l2c.ReadReq_accesses::cpu1.data 10416 # number of ReadReq accesses(hits+misses) 2437system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 12292 # number of ReadReq accesses(hits+misses) 2438system.l2c.ReadReq_accesses::total 355075 # number of ReadReq accesses(hits+misses) 2439system.l2c.Writeback_accesses::writebacks 232835 # number of Writeback accesses(hits+misses) 2440system.l2c.Writeback_accesses::total 232835 # number of Writeback accesses(hits+misses) 2441system.l2c.UpgradeReq_accesses::cpu0.data 12380 # number of UpgradeReq accesses(hits+misses) 2442system.l2c.UpgradeReq_accesses::cpu1.data 3566 # number of UpgradeReq accesses(hits+misses) 2443system.l2c.UpgradeReq_accesses::total 15946 # number of UpgradeReq accesses(hits+misses) 2444system.l2c.SCUpgradeReq_accesses::cpu0.data 844 # number of SCUpgradeReq accesses(hits+misses) 2445system.l2c.SCUpgradeReq_accesses::cpu1.data 1418 # number of SCUpgradeReq accesses(hits+misses) 2446system.l2c.SCUpgradeReq_accesses::total 2262 # number of SCUpgradeReq accesses(hits+misses) 2447system.l2c.ReadExReq_accesses::cpu0.data 15436 # number of ReadExReq accesses(hits+misses) 2448system.l2c.ReadExReq_accesses::cpu1.data 10132 # number of ReadExReq accesses(hits+misses) 2449system.l2c.ReadExReq_accesses::total 25568 # number of ReadExReq accesses(hits+misses) 2450system.l2c.demand_accesses::cpu0.dtb.walker 590 # number of demand (read+write) accesses 2451system.l2c.demand_accesses::cpu0.itb.walker 65 # number of demand (read+write) accesses 2452system.l2c.demand_accesses::cpu0.inst 71208 # number of demand (read+write) accesses 2453system.l2c.demand_accesses::cpu0.data 74839 # number of demand (read+write) accesses 2454system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179980 # number of demand (read+write) accesses 2455system.l2c.demand_accesses::cpu1.dtb.walker 148 # number of demand (read+write) accesses 2456system.l2c.demand_accesses::cpu1.itb.walker 25 # number of demand (read+write) accesses 2457system.l2c.demand_accesses::cpu1.inst 20948 # number of demand (read+write) accesses 2458system.l2c.demand_accesses::cpu1.data 20548 # number of demand (read+write) accesses 2459system.l2c.demand_accesses::cpu1.l2cache.prefetcher 12292 # number of demand (read+write) accesses 2460system.l2c.demand_accesses::total 380643 # number of demand (read+write) accesses 2461system.l2c.overall_accesses::cpu0.dtb.walker 590 # number of overall (read+write) accesses 2462system.l2c.overall_accesses::cpu0.itb.walker 65 # number of overall (read+write) accesses 2463system.l2c.overall_accesses::cpu0.inst 71208 # number of overall (read+write) accesses 2464system.l2c.overall_accesses::cpu0.data 74839 # number of overall (read+write) accesses 2465system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179980 # number of overall (read+write) accesses 2466system.l2c.overall_accesses::cpu1.dtb.walker 148 # number of overall (read+write) accesses 2467system.l2c.overall_accesses::cpu1.itb.walker 25 # number of overall (read+write) accesses 2468system.l2c.overall_accesses::cpu1.inst 20948 # number of overall (read+write) accesses 2469system.l2c.overall_accesses::cpu1.data 20548 # number of overall (read+write) accesses 2470system.l2c.overall_accesses::cpu1.l2cache.prefetcher 12292 # number of overall (read+write) accesses 2471system.l2c.overall_accesses::total 380643 # number of overall (read+write) accesses 2472system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.247458 # miss rate for ReadReq accesses 2473system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.030769 # miss rate for ReadReq accesses 2474system.l2c.ReadReq_miss_rate::cpu0.inst 0.319444 # miss rate for ReadReq accesses 2475system.l2c.ReadReq_miss_rate::cpu0.data 0.165732 # miss rate for ReadReq accesses 2476system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.735232 # miss rate for ReadReq accesses 2477system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.141892 # miss rate for ReadReq accesses 2478system.l2c.ReadReq_miss_rate::cpu1.inst 0.157247 # miss rate for ReadReq accesses 2479system.l2c.ReadReq_miss_rate::cpu1.data 0.105223 # miss rate for ReadReq accesses 2480system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.549870 # miss rate for ReadReq accesses 2481system.l2c.ReadReq_miss_rate::total 0.496337 # miss rate for ReadReq accesses 2482system.l2c.UpgradeReq_miss_rate::cpu0.data 0.747173 # miss rate for UpgradeReq accesses 2483system.l2c.UpgradeReq_miss_rate::cpu1.data 0.817723 # miss rate for UpgradeReq accesses 2484system.l2c.UpgradeReq_miss_rate::total 0.762950 # miss rate for UpgradeReq accesses 2485system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.795024 # miss rate for SCUpgradeReq accesses 2486system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.883639 # miss rate for SCUpgradeReq accesses 2487system.l2c.SCUpgradeReq_miss_rate::total 0.850575 # miss rate for SCUpgradeReq accesses 2488system.l2c.ReadExReq_miss_rate::cpu0.data 0.728427 # miss rate for ReadExReq accesses 2489system.l2c.ReadExReq_miss_rate::cpu1.data 0.828958 # miss rate for ReadExReq accesses 2490system.l2c.ReadExReq_miss_rate::total 0.768265 # miss rate for ReadExReq accesses 2491system.l2c.demand_miss_rate::cpu0.dtb.walker 0.247458 # miss rate for demand accesses 2492system.l2c.demand_miss_rate::cpu0.itb.walker 0.030769 # miss rate for demand accesses 2493system.l2c.demand_miss_rate::cpu0.inst 0.319444 # miss rate for demand accesses 2494system.l2c.demand_miss_rate::cpu0.data 0.281792 # miss rate for demand accesses 2495system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.735232 # miss rate for demand accesses 2496system.l2c.demand_miss_rate::cpu1.dtb.walker 0.141892 # miss rate for demand accesses 2497system.l2c.demand_miss_rate::cpu1.inst 0.157247 # miss rate for demand accesses 2498system.l2c.demand_miss_rate::cpu1.data 0.462089 # miss rate for demand accesses 2499system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.549870 # miss rate for demand accesses 2500system.l2c.demand_miss_rate::total 0.514603 # miss rate for demand accesses 2501system.l2c.overall_miss_rate::cpu0.dtb.walker 0.247458 # miss rate for overall accesses 2502system.l2c.overall_miss_rate::cpu0.itb.walker 0.030769 # miss rate for overall accesses 2503system.l2c.overall_miss_rate::cpu0.inst 0.319444 # miss rate for overall accesses 2504system.l2c.overall_miss_rate::cpu0.data 0.281792 # miss rate for overall accesses 2505system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.735232 # miss rate for overall accesses 2506system.l2c.overall_miss_rate::cpu1.dtb.walker 0.141892 # miss rate for overall accesses 2507system.l2c.overall_miss_rate::cpu1.inst 0.157247 # miss rate for overall accesses 2508system.l2c.overall_miss_rate::cpu1.data 0.462089 # miss rate for overall accesses 2509system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.549870 # miss rate for overall accesses 2510system.l2c.overall_miss_rate::total 0.514603 # miss rate for overall accesses 2511system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 91248.287671 # average ReadReq miss latency | 2357system.l2c.ReadExReq_hits::cpu0.data 4056 # number of ReadExReq hits 2358system.l2c.ReadExReq_hits::cpu1.data 2216 # number of ReadExReq hits 2359system.l2c.ReadExReq_hits::total 6272 # number of ReadExReq hits 2360system.l2c.demand_hits::cpu0.dtb.walker 375 # number of demand (read+write) hits 2361system.l2c.demand_hits::cpu0.itb.walker 73 # number of demand (read+write) hits 2362system.l2c.demand_hits::cpu0.inst 43717 # number of demand (read+write) hits 2363system.l2c.demand_hits::cpu0.data 51421 # number of demand (read+write) hits 2364system.l2c.demand_hits::cpu0.l2cache.prefetcher 45781 # number of demand (read+write) hits 2365system.l2c.demand_hits::cpu1.dtb.walker 167 # number of demand (read+write) hits 2366system.l2c.demand_hits::cpu1.itb.walker 27 # number of demand (read+write) hits 2367system.l2c.demand_hits::cpu1.inst 21454 # number of demand (read+write) hits 2368system.l2c.demand_hits::cpu1.data 13201 # number of demand (read+write) hits 2369system.l2c.demand_hits::cpu1.l2cache.prefetcher 8059 # number of demand (read+write) hits 2370system.l2c.demand_hits::total 184275 # number of demand (read+write) hits 2371system.l2c.overall_hits::cpu0.dtb.walker 375 # number of overall hits 2372system.l2c.overall_hits::cpu0.itb.walker 73 # number of overall hits 2373system.l2c.overall_hits::cpu0.inst 43717 # number of overall hits 2374system.l2c.overall_hits::cpu0.data 51421 # number of overall hits 2375system.l2c.overall_hits::cpu0.l2cache.prefetcher 45781 # number of overall hits 2376system.l2c.overall_hits::cpu1.dtb.walker 167 # number of overall hits 2377system.l2c.overall_hits::cpu1.itb.walker 27 # number of overall hits 2378system.l2c.overall_hits::cpu1.inst 21454 # number of overall hits 2379system.l2c.overall_hits::cpu1.data 13201 # number of overall hits 2380system.l2c.overall_hits::cpu1.l2cache.prefetcher 8059 # number of overall hits 2381system.l2c.overall_hits::total 184275 # number of overall hits 2382system.l2c.ReadReq_misses::cpu0.dtb.walker 130 # number of ReadReq misses 2383system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses 2384system.l2c.ReadReq_misses::cpu0.inst 20052 # number of ReadReq misses 2385system.l2c.ReadReq_misses::cpu0.data 8676 # number of ReadReq misses 2386system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 129939 # number of ReadReq misses 2387system.l2c.ReadReq_misses::cpu1.dtb.walker 40 # number of ReadReq misses 2388system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 2389system.l2c.ReadReq_misses::cpu1.inst 5975 # number of ReadReq misses 2390system.l2c.ReadReq_misses::cpu1.data 2283 # number of ReadReq misses 2391system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 9112 # number of ReadReq misses 2392system.l2c.ReadReq_misses::total 176209 # number of ReadReq misses 2393system.l2c.UpgradeReq_misses::cpu0.data 8724 # number of UpgradeReq misses 2394system.l2c.UpgradeReq_misses::cpu1.data 4132 # number of UpgradeReq misses 2395system.l2c.UpgradeReq_misses::total 12856 # number of UpgradeReq misses 2396system.l2c.SCUpgradeReq_misses::cpu0.data 807 # number of SCUpgradeReq misses 2397system.l2c.SCUpgradeReq_misses::cpu1.data 1210 # number of SCUpgradeReq misses 2398system.l2c.SCUpgradeReq_misses::total 2017 # number of SCUpgradeReq misses 2399system.l2c.ReadExReq_misses::cpu0.data 11072 # number of ReadExReq misses 2400system.l2c.ReadExReq_misses::cpu1.data 8457 # number of ReadExReq misses 2401system.l2c.ReadExReq_misses::total 19529 # number of ReadExReq misses 2402system.l2c.demand_misses::cpu0.dtb.walker 130 # number of demand (read+write) misses 2403system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses 2404system.l2c.demand_misses::cpu0.inst 20052 # number of demand (read+write) misses 2405system.l2c.demand_misses::cpu0.data 19748 # number of demand (read+write) misses 2406system.l2c.demand_misses::cpu0.l2cache.prefetcher 129939 # number of demand (read+write) misses 2407system.l2c.demand_misses::cpu1.dtb.walker 40 # number of demand (read+write) misses 2408system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 2409system.l2c.demand_misses::cpu1.inst 5975 # number of demand (read+write) misses 2410system.l2c.demand_misses::cpu1.data 10740 # number of demand (read+write) misses 2411system.l2c.demand_misses::cpu1.l2cache.prefetcher 9112 # number of demand (read+write) misses 2412system.l2c.demand_misses::total 195738 # number of demand (read+write) misses 2413system.l2c.overall_misses::cpu0.dtb.walker 130 # number of overall misses 2414system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses 2415system.l2c.overall_misses::cpu0.inst 20052 # number of overall misses 2416system.l2c.overall_misses::cpu0.data 19748 # number of overall misses 2417system.l2c.overall_misses::cpu0.l2cache.prefetcher 129939 # number of overall misses 2418system.l2c.overall_misses::cpu1.dtb.walker 40 # number of overall misses 2419system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 2420system.l2c.overall_misses::cpu1.inst 5975 # number of overall misses 2421system.l2c.overall_misses::cpu1.data 10740 # number of overall misses 2422system.l2c.overall_misses::cpu1.l2cache.prefetcher 9112 # number of overall misses 2423system.l2c.overall_misses::total 195738 # number of overall misses 2424system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 10973000 # number of ReadReq miss cycles 2425system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82500 # number of ReadReq miss cycles 2426system.l2c.ReadReq_miss_latency::cpu0.inst 1610371008 # number of ReadReq miss cycles 2427system.l2c.ReadReq_miss_latency::cpu0.data 763651868 # number of ReadReq miss cycles 2428system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 13522119331 # number of ReadReq miss cycles 2429system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 3426000 # number of ReadReq miss cycles 2430system.l2c.ReadReq_miss_latency::cpu1.itb.walker 83000 # number of ReadReq miss cycles 2431system.l2c.ReadReq_miss_latency::cpu1.inst 494933758 # number of ReadReq miss cycles 2432system.l2c.ReadReq_miss_latency::cpu1.data 205725771 # number of ReadReq miss cycles 2433system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 1117904049 # number of ReadReq miss cycles 2434system.l2c.ReadReq_miss_latency::total 17729270285 # number of ReadReq miss cycles 2435system.l2c.UpgradeReq_miss_latency::cpu0.data 8986748 # number of UpgradeReq miss cycles 2436system.l2c.UpgradeReq_miss_latency::cpu1.data 6209345 # number of UpgradeReq miss cycles 2437system.l2c.UpgradeReq_miss_latency::total 15196093 # number of UpgradeReq miss cycles 2438system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1132469 # number of SCUpgradeReq miss cycles 2439system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1093465 # number of SCUpgradeReq miss cycles 2440system.l2c.SCUpgradeReq_miss_latency::total 2225934 # number of SCUpgradeReq miss cycles 2441system.l2c.ReadExReq_miss_latency::cpu0.data 1027113188 # number of ReadExReq miss cycles 2442system.l2c.ReadExReq_miss_latency::cpu1.data 693883201 # number of ReadExReq miss cycles 2443system.l2c.ReadExReq_miss_latency::total 1720996389 # number of ReadExReq miss cycles 2444system.l2c.demand_miss_latency::cpu0.dtb.walker 10973000 # number of demand (read+write) miss cycles 2445system.l2c.demand_miss_latency::cpu0.itb.walker 82500 # number of demand (read+write) miss cycles 2446system.l2c.demand_miss_latency::cpu0.inst 1610371008 # number of demand (read+write) miss cycles 2447system.l2c.demand_miss_latency::cpu0.data 1790765056 # number of demand (read+write) miss cycles 2448system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13522119331 # number of demand (read+write) miss cycles 2449system.l2c.demand_miss_latency::cpu1.dtb.walker 3426000 # number of demand (read+write) miss cycles 2450system.l2c.demand_miss_latency::cpu1.itb.walker 83000 # number of demand (read+write) miss cycles 2451system.l2c.demand_miss_latency::cpu1.inst 494933758 # number of demand (read+write) miss cycles 2452system.l2c.demand_miss_latency::cpu1.data 899608972 # number of demand (read+write) miss cycles 2453system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1117904049 # number of demand (read+write) miss cycles 2454system.l2c.demand_miss_latency::total 19450266674 # number of demand (read+write) miss cycles 2455system.l2c.overall_miss_latency::cpu0.dtb.walker 10973000 # number of overall miss cycles 2456system.l2c.overall_miss_latency::cpu0.itb.walker 82500 # number of overall miss cycles 2457system.l2c.overall_miss_latency::cpu0.inst 1610371008 # number of overall miss cycles 2458system.l2c.overall_miss_latency::cpu0.data 1790765056 # number of overall miss cycles 2459system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13522119331 # number of overall miss cycles 2460system.l2c.overall_miss_latency::cpu1.dtb.walker 3426000 # number of overall miss cycles 2461system.l2c.overall_miss_latency::cpu1.itb.walker 83000 # number of overall miss cycles 2462system.l2c.overall_miss_latency::cpu1.inst 494933758 # number of overall miss cycles 2463system.l2c.overall_miss_latency::cpu1.data 899608972 # number of overall miss cycles 2464system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1117904049 # number of overall miss cycles 2465system.l2c.overall_miss_latency::total 19450266674 # number of overall miss cycles 2466system.l2c.ReadReq_accesses::cpu0.dtb.walker 505 # number of ReadReq accesses(hits+misses) 2467system.l2c.ReadReq_accesses::cpu0.itb.walker 74 # number of ReadReq accesses(hits+misses) 2468system.l2c.ReadReq_accesses::cpu0.inst 63769 # number of ReadReq accesses(hits+misses) 2469system.l2c.ReadReq_accesses::cpu0.data 56041 # number of ReadReq accesses(hits+misses) 2470system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 175720 # number of ReadReq accesses(hits+misses) 2471system.l2c.ReadReq_accesses::cpu1.dtb.walker 207 # number of ReadReq accesses(hits+misses) 2472system.l2c.ReadReq_accesses::cpu1.itb.walker 28 # number of ReadReq accesses(hits+misses) 2473system.l2c.ReadReq_accesses::cpu1.inst 27429 # number of ReadReq accesses(hits+misses) 2474system.l2c.ReadReq_accesses::cpu1.data 13268 # number of ReadReq accesses(hits+misses) 2475system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 17171 # number of ReadReq accesses(hits+misses) 2476system.l2c.ReadReq_accesses::total 354212 # number of ReadReq accesses(hits+misses) 2477system.l2c.Writeback_accesses::writebacks 233506 # number of Writeback accesses(hits+misses) 2478system.l2c.Writeback_accesses::total 233506 # number of Writeback accesses(hits+misses) 2479system.l2c.UpgradeReq_accesses::cpu0.data 11651 # number of UpgradeReq accesses(hits+misses) 2480system.l2c.UpgradeReq_accesses::cpu1.data 5079 # number of UpgradeReq accesses(hits+misses) 2481system.l2c.UpgradeReq_accesses::total 16730 # number of UpgradeReq accesses(hits+misses) 2482system.l2c.SCUpgradeReq_accesses::cpu0.data 1056 # number of SCUpgradeReq accesses(hits+misses) 2483system.l2c.SCUpgradeReq_accesses::cpu1.data 1299 # number of SCUpgradeReq accesses(hits+misses) 2484system.l2c.SCUpgradeReq_accesses::total 2355 # number of SCUpgradeReq accesses(hits+misses) 2485system.l2c.ReadExReq_accesses::cpu0.data 15128 # number of ReadExReq accesses(hits+misses) 2486system.l2c.ReadExReq_accesses::cpu1.data 10673 # number of ReadExReq accesses(hits+misses) 2487system.l2c.ReadExReq_accesses::total 25801 # number of ReadExReq accesses(hits+misses) 2488system.l2c.demand_accesses::cpu0.dtb.walker 505 # number of demand (read+write) accesses 2489system.l2c.demand_accesses::cpu0.itb.walker 74 # number of demand (read+write) accesses 2490system.l2c.demand_accesses::cpu0.inst 63769 # number of demand (read+write) accesses 2491system.l2c.demand_accesses::cpu0.data 71169 # number of demand (read+write) accesses 2492system.l2c.demand_accesses::cpu0.l2cache.prefetcher 175720 # number of demand (read+write) accesses 2493system.l2c.demand_accesses::cpu1.dtb.walker 207 # number of demand (read+write) accesses 2494system.l2c.demand_accesses::cpu1.itb.walker 28 # number of demand (read+write) accesses 2495system.l2c.demand_accesses::cpu1.inst 27429 # number of demand (read+write) accesses 2496system.l2c.demand_accesses::cpu1.data 23941 # number of demand (read+write) accesses 2497system.l2c.demand_accesses::cpu1.l2cache.prefetcher 17171 # number of demand (read+write) accesses 2498system.l2c.demand_accesses::total 380013 # number of demand (read+write) accesses 2499system.l2c.overall_accesses::cpu0.dtb.walker 505 # number of overall (read+write) accesses 2500system.l2c.overall_accesses::cpu0.itb.walker 74 # number of overall (read+write) accesses 2501system.l2c.overall_accesses::cpu0.inst 63769 # number of overall (read+write) accesses 2502system.l2c.overall_accesses::cpu0.data 71169 # number of overall (read+write) accesses 2503system.l2c.overall_accesses::cpu0.l2cache.prefetcher 175720 # number of overall (read+write) accesses 2504system.l2c.overall_accesses::cpu1.dtb.walker 207 # number of overall (read+write) accesses 2505system.l2c.overall_accesses::cpu1.itb.walker 28 # number of overall (read+write) accesses 2506system.l2c.overall_accesses::cpu1.inst 27429 # number of overall (read+write) accesses 2507system.l2c.overall_accesses::cpu1.data 23941 # number of overall (read+write) accesses 2508system.l2c.overall_accesses::cpu1.l2cache.prefetcher 17171 # number of overall (read+write) accesses 2509system.l2c.overall_accesses::total 380013 # number of overall (read+write) accesses 2510system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.257426 # miss rate for ReadReq accesses 2511system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.013514 # miss rate for ReadReq accesses 2512system.l2c.ReadReq_miss_rate::cpu0.inst 0.314447 # miss rate for ReadReq accesses 2513system.l2c.ReadReq_miss_rate::cpu0.data 0.154815 # miss rate for ReadReq accesses 2514system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.739466 # miss rate for ReadReq accesses 2515system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.193237 # miss rate for ReadReq accesses 2516system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.035714 # miss rate for ReadReq accesses 2517system.l2c.ReadReq_miss_rate::cpu1.inst 0.217835 # miss rate for ReadReq accesses 2518system.l2c.ReadReq_miss_rate::cpu1.data 0.172068 # miss rate for ReadReq accesses 2519system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.530662 # miss rate for ReadReq accesses 2520system.l2c.ReadReq_miss_rate::total 0.497468 # miss rate for ReadReq accesses 2521system.l2c.UpgradeReq_miss_rate::cpu0.data 0.748777 # miss rate for UpgradeReq accesses 2522system.l2c.UpgradeReq_miss_rate::cpu1.data 0.813546 # miss rate for UpgradeReq accesses 2523system.l2c.UpgradeReq_miss_rate::total 0.768440 # miss rate for UpgradeReq accesses 2524system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.764205 # miss rate for SCUpgradeReq accesses 2525system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.931486 # miss rate for SCUpgradeReq accesses 2526system.l2c.SCUpgradeReq_miss_rate::total 0.856476 # miss rate for SCUpgradeReq accesses 2527system.l2c.ReadExReq_miss_rate::cpu0.data 0.731888 # miss rate for ReadExReq accesses 2528system.l2c.ReadExReq_miss_rate::cpu1.data 0.792373 # miss rate for ReadExReq accesses 2529system.l2c.ReadExReq_miss_rate::total 0.756909 # miss rate for ReadExReq accesses 2530system.l2c.demand_miss_rate::cpu0.dtb.walker 0.257426 # miss rate for demand accesses 2531system.l2c.demand_miss_rate::cpu0.itb.walker 0.013514 # miss rate for demand accesses 2532system.l2c.demand_miss_rate::cpu0.inst 0.314447 # miss rate for demand accesses 2533system.l2c.demand_miss_rate::cpu0.data 0.277480 # miss rate for demand accesses 2534system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.739466 # miss rate for demand accesses 2535system.l2c.demand_miss_rate::cpu1.dtb.walker 0.193237 # miss rate for demand accesses 2536system.l2c.demand_miss_rate::cpu1.itb.walker 0.035714 # miss rate for demand accesses 2537system.l2c.demand_miss_rate::cpu1.inst 0.217835 # miss rate for demand accesses 2538system.l2c.demand_miss_rate::cpu1.data 0.448603 # miss rate for demand accesses 2539system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.530662 # miss rate for demand accesses 2540system.l2c.demand_miss_rate::total 0.515082 # miss rate for demand accesses 2541system.l2c.overall_miss_rate::cpu0.dtb.walker 0.257426 # miss rate for overall accesses 2542system.l2c.overall_miss_rate::cpu0.itb.walker 0.013514 # miss rate for overall accesses 2543system.l2c.overall_miss_rate::cpu0.inst 0.314447 # miss rate for overall accesses 2544system.l2c.overall_miss_rate::cpu0.data 0.277480 # miss rate for overall accesses 2545system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.739466 # miss rate for overall accesses 2546system.l2c.overall_miss_rate::cpu1.dtb.walker 0.193237 # miss rate for overall accesses 2547system.l2c.overall_miss_rate::cpu1.itb.walker 0.035714 # miss rate for overall accesses 2548system.l2c.overall_miss_rate::cpu1.inst 0.217835 # miss rate for overall accesses 2549system.l2c.overall_miss_rate::cpu1.data 0.448603 # miss rate for overall accesses 2550system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.530662 # miss rate for overall accesses 2551system.l2c.overall_miss_rate::total 0.515082 # miss rate for overall accesses 2552system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 84407.692308 # average ReadReq miss latency |
| 2512system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82500 # average ReadReq miss latency | 2553system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82500 # average ReadReq miss latency |
| 2513system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80731.066075 # average ReadReq miss latency 2514system.l2c.ReadReq_avg_miss_latency::cpu0.data 88355.805079 # average ReadReq miss latency 2515system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 103135.859394 # average ReadReq miss latency 2516system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89440.476190 # average ReadReq miss latency 2517system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83109.063145 # average ReadReq miss latency 2518system.l2c.ReadReq_avg_miss_latency::cpu1.data 91578.010949 # average ReadReq miss latency 2519system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 134479.766386 # average ReadReq miss latency 2520system.l2c.ReadReq_avg_miss_latency::total 100162.601054 # average ReadReq miss latency 2521system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 768.083892 # average UpgradeReq miss latency 2522system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1039.233882 # average UpgradeReq miss latency 2523system.l2c.UpgradeReq_avg_miss_latency::total 833.074305 # average UpgradeReq miss latency 2524system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1538.706408 # average SCUpgradeReq miss latency 2525system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1196.290503 # average SCUpgradeReq miss latency 2526system.l2c.SCUpgradeReq_avg_miss_latency::total 1315.708940 # average SCUpgradeReq miss latency 2527system.l2c.ReadExReq_avg_miss_latency::cpu0.data 91439.584134 # average ReadExReq miss latency 2528system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82197.253244 # average ReadExReq miss latency 2529system.l2c.ReadExReq_avg_miss_latency::total 87487.726620 # average ReadExReq miss latency 2530system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 91248.287671 # average overall miss latency | 2554system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80309.745063 # average ReadReq miss latency 2555system.l2c.ReadReq_avg_miss_latency::cpu0.data 88018.887506 # average ReadReq miss latency 2556system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 104065.133109 # average ReadReq miss latency 2557system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 85650 # average ReadReq miss latency 2558system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 83000 # average ReadReq miss latency 2559system.l2c.ReadReq_avg_miss_latency::cpu1.inst 82834.101757 # average ReadReq miss latency 2560system.l2c.ReadReq_avg_miss_latency::cpu1.data 90112.032852 # average ReadReq miss latency 2561system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 122684.816615 # average ReadReq miss latency 2562system.l2c.ReadReq_avg_miss_latency::total 100615.009931 # average ReadReq miss latency 2563system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1030.117836 # average UpgradeReq miss latency 2564system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1502.745644 # average UpgradeReq miss latency 2565system.l2c.UpgradeReq_avg_miss_latency::total 1182.023413 # average UpgradeReq miss latency 2566system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1403.307311 # average SCUpgradeReq miss latency 2567system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 903.690083 # average SCUpgradeReq miss latency 2568system.l2c.SCUpgradeReq_avg_miss_latency::total 1103.586515 # average SCUpgradeReq miss latency 2569system.l2c.ReadExReq_avg_miss_latency::cpu0.data 92766.725795 # average ReadExReq miss latency 2570system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82048.386071 # average ReadExReq miss latency 2571system.l2c.ReadExReq_avg_miss_latency::total 88125.167136 # average ReadExReq miss latency 2572system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 84407.692308 # average overall miss latency |
| 2531system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency | 2573system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency |
| 2532system.l2c.demand_avg_miss_latency::cpu0.inst 80731.066075 # average overall miss latency 2533system.l2c.demand_avg_miss_latency::cpu0.data 89999.980321 # average overall miss latency 2534system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 103135.859394 # average overall miss latency 2535system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89440.476190 # average overall miss latency 2536system.l2c.demand_avg_miss_latency::cpu1.inst 83109.063145 # average overall miss latency 2537system.l2c.demand_avg_miss_latency::cpu1.data 83280.066351 # average overall miss latency 2538system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134479.766386 # average overall miss latency 2539system.l2c.demand_avg_miss_latency::total 98891.554707 # average overall miss latency 2540system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 91248.287671 # average overall miss latency | 2574system.l2c.demand_avg_miss_latency::cpu0.inst 80309.745063 # average overall miss latency 2575system.l2c.demand_avg_miss_latency::cpu0.data 90680.831274 # average overall miss latency 2576system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 104065.133109 # average overall miss latency 2577system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85650 # average overall miss latency 2578system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83000 # average overall miss latency 2579system.l2c.demand_avg_miss_latency::cpu1.inst 82834.101757 # average overall miss latency 2580system.l2c.demand_avg_miss_latency::cpu1.data 83762.474115 # average overall miss latency 2581system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 122684.816615 # average overall miss latency 2582system.l2c.demand_avg_miss_latency::total 99368.884294 # average overall miss latency 2583system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 84407.692308 # average overall miss latency |
| 2541system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency | 2584system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency |
| 2542system.l2c.overall_avg_miss_latency::cpu0.inst 80731.066075 # average overall miss latency 2543system.l2c.overall_avg_miss_latency::cpu0.data 89999.980321 # average overall miss latency 2544system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 103135.859394 # average overall miss latency 2545system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89440.476190 # average overall miss latency 2546system.l2c.overall_avg_miss_latency::cpu1.inst 83109.063145 # average overall miss latency 2547system.l2c.overall_avg_miss_latency::cpu1.data 83280.066351 # average overall miss latency 2548system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134479.766386 # average overall miss latency 2549system.l2c.overall_avg_miss_latency::total 98891.554707 # average overall miss latency 2550system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 2585system.l2c.overall_avg_miss_latency::cpu0.inst 80309.745063 # average overall miss latency 2586system.l2c.overall_avg_miss_latency::cpu0.data 90680.831274 # average overall miss latency 2587system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 104065.133109 # average overall miss latency 2588system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85650 # average overall miss latency 2589system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83000 # average overall miss latency 2590system.l2c.overall_avg_miss_latency::cpu1.inst 82834.101757 # average overall miss latency 2591system.l2c.overall_avg_miss_latency::cpu1.data 83762.474115 # average overall miss latency 2592system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 122684.816615 # average overall miss latency 2593system.l2c.overall_avg_miss_latency::total 99368.884294 # average overall miss latency 2594system.l2c.blocked_cycles::no_mshrs 17 # number of cycles access was blocked |
| 2551system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2595system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2552system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked | 2596system.l2c.blocked::no_mshrs 1 # number of cycles access was blocked |
| 2553system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 2597system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 2554system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 2598system.l2c.avg_blocked_cycles::no_mshrs 17 # average number of cycles each access was blocked |
| 2555system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2556system.l2c.fast_writes 0 # number of fast writes performed 2557system.l2c.cache_copies 0 # number of cache copies performed | 2599system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2600system.l2c.fast_writes 0 # number of fast writes performed 2601system.l2c.cache_copies 0 # number of cache copies performed |
| 2558system.l2c.writebacks::writebacks 101923 # number of writebacks 2559system.l2c.writebacks::total 101923 # number of writebacks 2560system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits 2561system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits 2562system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits 2563system.l2c.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits 2564system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits 2565system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits 2566system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits 2567system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits 2568system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits 2569system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits 2570system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits 2571system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits 2572system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 146 # number of ReadReq MSHR misses 2573system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses 2574system.l2c.ReadReq_mshr_misses::cpu0.inst 22742 # number of ReadReq MSHR misses 2575system.l2c.ReadReq_mshr_misses::cpu0.data 9845 # number of ReadReq MSHR misses 2576system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 132327 # number of ReadReq MSHR misses 2577system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 21 # number of ReadReq MSHR misses 2578system.l2c.ReadReq_mshr_misses::cpu1.inst 3293 # number of ReadReq MSHR misses 2579system.l2c.ReadReq_mshr_misses::cpu1.data 1095 # number of ReadReq MSHR misses 2580system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 6759 # number of ReadReq MSHR misses 2581system.l2c.ReadReq_mshr_misses::total 176230 # number of ReadReq MSHR misses 2582system.l2c.UpgradeReq_mshr_misses::cpu0.data 9250 # number of UpgradeReq MSHR misses 2583system.l2c.UpgradeReq_mshr_misses::cpu1.data 2916 # number of UpgradeReq MSHR misses 2584system.l2c.UpgradeReq_mshr_misses::total 12166 # number of UpgradeReq MSHR misses 2585system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 671 # number of SCUpgradeReq MSHR misses 2586system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1253 # number of SCUpgradeReq MSHR misses 2587system.l2c.SCUpgradeReq_mshr_misses::total 1924 # number of SCUpgradeReq MSHR misses 2588system.l2c.ReadExReq_mshr_misses::cpu0.data 11244 # number of ReadExReq MSHR misses 2589system.l2c.ReadExReq_mshr_misses::cpu1.data 8399 # number of ReadExReq MSHR misses 2590system.l2c.ReadExReq_mshr_misses::total 19643 # number of ReadExReq MSHR misses 2591system.l2c.demand_mshr_misses::cpu0.dtb.walker 146 # number of demand (read+write) MSHR misses 2592system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 2593system.l2c.demand_mshr_misses::cpu0.inst 22742 # number of demand (read+write) MSHR misses 2594system.l2c.demand_mshr_misses::cpu0.data 21089 # number of demand (read+write) MSHR misses 2595system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 132327 # number of demand (read+write) MSHR misses 2596system.l2c.demand_mshr_misses::cpu1.dtb.walker 21 # number of demand (read+write) MSHR misses 2597system.l2c.demand_mshr_misses::cpu1.inst 3293 # number of demand (read+write) MSHR misses 2598system.l2c.demand_mshr_misses::cpu1.data 9494 # number of demand (read+write) MSHR misses 2599system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6759 # number of demand (read+write) MSHR misses 2600system.l2c.demand_mshr_misses::total 195873 # number of demand (read+write) MSHR misses 2601system.l2c.overall_mshr_misses::cpu0.dtb.walker 146 # number of overall MSHR misses 2602system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 2603system.l2c.overall_mshr_misses::cpu0.inst 22742 # number of overall MSHR misses 2604system.l2c.overall_mshr_misses::cpu0.data 21089 # number of overall MSHR misses 2605system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 132327 # number of overall MSHR misses 2606system.l2c.overall_mshr_misses::cpu1.dtb.walker 21 # number of overall MSHR misses 2607system.l2c.overall_mshr_misses::cpu1.inst 3293 # number of overall MSHR misses 2608system.l2c.overall_mshr_misses::cpu1.data 9494 # number of overall MSHR misses 2609system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6759 # number of overall MSHR misses 2610system.l2c.overall_mshr_misses::total 195873 # number of overall MSHR misses 2611system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 11489750 # number of ReadReq MSHR miss cycles 2612system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 140000 # number of ReadReq MSHR miss cycles 2613system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1551174190 # number of ReadReq MSHR miss cycles 2614system.l2c.ReadReq_mshr_miss_latency::cpu0.data 746786599 # number of ReadReq MSHR miss cycles 2615system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12016886672 # number of ReadReq MSHR miss cycles 2616system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1614750 # number of ReadReq MSHR miss cycles 2617system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 232356996 # number of ReadReq MSHR miss cycles 2618system.l2c.ReadReq_mshr_miss_latency::cpu1.data 86604500 # number of ReadReq MSHR miss cycles 2619system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 826146057 # number of ReadReq MSHR miss cycles 2620system.l2c.ReadReq_mshr_miss_latency::total 15473199514 # number of ReadReq MSHR miss cycles 2621system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 164200724 # number of UpgradeReq MSHR miss cycles 2622system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 51784907 # number of UpgradeReq MSHR miss cycles 2623system.l2c.UpgradeReq_mshr_miss_latency::total 215985631 # number of UpgradeReq MSHR miss cycles 2624system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12008669 # number of SCUpgradeReq MSHR miss cycles 2625system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22268252 # number of SCUpgradeReq MSHR miss cycles 2626system.l2c.SCUpgradeReq_mshr_miss_latency::total 34276921 # number of SCUpgradeReq MSHR miss cycles 2627system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 889143316 # number of ReadExReq MSHR miss cycles 2628system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 585339270 # number of ReadExReq MSHR miss cycles 2629system.l2c.ReadExReq_mshr_miss_latency::total 1474482586 # number of ReadExReq MSHR miss cycles 2630system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 11489750 # number of demand (read+write) MSHR miss cycles 2631system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 140000 # number of demand (read+write) MSHR miss cycles 2632system.l2c.demand_mshr_miss_latency::cpu0.inst 1551174190 # number of demand (read+write) MSHR miss cycles 2633system.l2c.demand_mshr_miss_latency::cpu0.data 1635929915 # number of demand (read+write) MSHR miss cycles 2634system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12016886672 # number of demand (read+write) MSHR miss cycles 2635system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1614750 # number of demand (read+write) MSHR miss cycles 2636system.l2c.demand_mshr_miss_latency::cpu1.inst 232356996 # number of demand (read+write) MSHR miss cycles 2637system.l2c.demand_mshr_miss_latency::cpu1.data 671943770 # number of demand (read+write) MSHR miss cycles 2638system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 826146057 # number of demand (read+write) MSHR miss cycles 2639system.l2c.demand_mshr_miss_latency::total 16947682100 # number of demand (read+write) MSHR miss cycles 2640system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 11489750 # number of overall MSHR miss cycles 2641system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 140000 # number of overall MSHR miss cycles 2642system.l2c.overall_mshr_miss_latency::cpu0.inst 1551174190 # number of overall MSHR miss cycles 2643system.l2c.overall_mshr_miss_latency::cpu0.data 1635929915 # number of overall MSHR miss cycles 2644system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12016886672 # number of overall MSHR miss cycles 2645system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1614750 # number of overall MSHR miss cycles 2646system.l2c.overall_mshr_miss_latency::cpu1.inst 232356996 # number of overall MSHR miss cycles 2647system.l2c.overall_mshr_miss_latency::cpu1.data 671943770 # number of overall MSHR miss cycles 2648system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 826146057 # number of overall MSHR miss cycles 2649system.l2c.overall_mshr_miss_latency::total 16947682100 # number of overall MSHR miss cycles 2650system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 205778000 # number of ReadReq MSHR uncacheable cycles 2651system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3714619750 # number of ReadReq MSHR uncacheable cycles 2652system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6850000 # number of ReadReq MSHR uncacheable cycles 2653system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919856251 # number of ReadReq MSHR uncacheable cycles 2654system.l2c.ReadReq_mshr_uncacheable_latency::total 5847104001 # number of ReadReq MSHR uncacheable cycles 2655system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2763444000 # number of WriteReq MSHR uncacheable cycles 2656system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1533087000 # number of WriteReq MSHR uncacheable cycles 2657system.l2c.WriteReq_mshr_uncacheable_latency::total 4296531000 # number of WriteReq MSHR uncacheable cycles 2658system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 205778000 # number of overall MSHR uncacheable cycles 2659system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6478063750 # number of overall MSHR uncacheable cycles 2660system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6850000 # number of overall MSHR uncacheable cycles 2661system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3452943251 # number of overall MSHR uncacheable cycles 2662system.l2c.overall_mshr_uncacheable_latency::total 10143635001 # number of overall MSHR uncacheable cycles 2663system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.247458 # mshr miss rate for ReadReq accesses 2664system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for ReadReq accesses 2665system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.319374 # mshr miss rate for ReadReq accesses 2666system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.165732 # mshr miss rate for ReadReq accesses 2667system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735232 # mshr miss rate for ReadReq accesses 2668system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.141892 # mshr miss rate for ReadReq accesses 2669system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.157199 # mshr miss rate for ReadReq accesses 2670system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.105127 # mshr miss rate for ReadReq accesses 2671system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.549870 # mshr miss rate for ReadReq accesses 2672system.l2c.ReadReq_mshr_miss_rate::total 0.496318 # mshr miss rate for ReadReq accesses 2673system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.747173 # mshr miss rate for UpgradeReq accesses 2674system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.817723 # mshr miss rate for UpgradeReq accesses 2675system.l2c.UpgradeReq_mshr_miss_rate::total 0.762950 # mshr miss rate for UpgradeReq accesses 2676system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.795024 # mshr miss rate for SCUpgradeReq accesses 2677system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.883639 # mshr miss rate for SCUpgradeReq accesses 2678system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.850575 # mshr miss rate for SCUpgradeReq accesses 2679system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.728427 # mshr miss rate for ReadExReq accesses 2680system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.828958 # mshr miss rate for ReadExReq accesses 2681system.l2c.ReadExReq_mshr_miss_rate::total 0.768265 # mshr miss rate for ReadExReq accesses 2682system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.247458 # mshr miss rate for demand accesses 2683system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for demand accesses 2684system.l2c.demand_mshr_miss_rate::cpu0.inst 0.319374 # mshr miss rate for demand accesses 2685system.l2c.demand_mshr_miss_rate::cpu0.data 0.281792 # mshr miss rate for demand accesses 2686system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735232 # mshr miss rate for demand accesses 2687system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.141892 # mshr miss rate for demand accesses 2688system.l2c.demand_mshr_miss_rate::cpu1.inst 0.157199 # mshr miss rate for demand accesses 2689system.l2c.demand_mshr_miss_rate::cpu1.data 0.462040 # mshr miss rate for demand accesses 2690system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.549870 # mshr miss rate for demand accesses 2691system.l2c.demand_mshr_miss_rate::total 0.514585 # mshr miss rate for demand accesses 2692system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.247458 # mshr miss rate for overall accesses 2693system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for overall accesses 2694system.l2c.overall_mshr_miss_rate::cpu0.inst 0.319374 # mshr miss rate for overall accesses 2695system.l2c.overall_mshr_miss_rate::cpu0.data 0.281792 # mshr miss rate for overall accesses 2696system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735232 # mshr miss rate for overall accesses 2697system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.141892 # mshr miss rate for overall accesses 2698system.l2c.overall_mshr_miss_rate::cpu1.inst 0.157199 # mshr miss rate for overall accesses 2699system.l2c.overall_mshr_miss_rate::cpu1.data 0.462040 # mshr miss rate for overall accesses 2700system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.549870 # mshr miss rate for overall accesses 2701system.l2c.overall_mshr_miss_rate::total 0.514585 # mshr miss rate for overall accesses 2702system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 78696.917808 # average ReadReq mshr miss latency | 2602system.l2c.writebacks::writebacks 102293 # number of writebacks 2603system.l2c.writebacks::total 102293 # number of writebacks 2604system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits 2605system.l2c.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 2606system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits 2607system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits 2608system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits 2609system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits 2610system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 130 # number of ReadReq MSHR misses 2611system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses 2612system.l2c.ReadReq_mshr_misses::cpu0.inst 20049 # number of ReadReq MSHR misses 2613system.l2c.ReadReq_mshr_misses::cpu0.data 8676 # number of ReadReq MSHR misses 2614system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 129939 # number of ReadReq MSHR misses 2615system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 40 # number of ReadReq MSHR misses 2616system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses 2617system.l2c.ReadReq_mshr_misses::cpu1.inst 5975 # number of ReadReq MSHR misses 2618system.l2c.ReadReq_mshr_misses::cpu1.data 2283 # number of ReadReq MSHR misses 2619system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 9112 # number of ReadReq MSHR misses 2620system.l2c.ReadReq_mshr_misses::total 176206 # number of ReadReq MSHR misses 2621system.l2c.UpgradeReq_mshr_misses::cpu0.data 8724 # number of UpgradeReq MSHR misses 2622system.l2c.UpgradeReq_mshr_misses::cpu1.data 4132 # number of UpgradeReq MSHR misses 2623system.l2c.UpgradeReq_mshr_misses::total 12856 # number of UpgradeReq MSHR misses 2624system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 807 # number of SCUpgradeReq MSHR misses 2625system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1210 # number of SCUpgradeReq MSHR misses 2626system.l2c.SCUpgradeReq_mshr_misses::total 2017 # number of SCUpgradeReq MSHR misses 2627system.l2c.ReadExReq_mshr_misses::cpu0.data 11072 # number of ReadExReq MSHR misses 2628system.l2c.ReadExReq_mshr_misses::cpu1.data 8457 # number of ReadExReq MSHR misses 2629system.l2c.ReadExReq_mshr_misses::total 19529 # number of ReadExReq MSHR misses 2630system.l2c.demand_mshr_misses::cpu0.dtb.walker 130 # number of demand (read+write) MSHR misses 2631system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses 2632system.l2c.demand_mshr_misses::cpu0.inst 20049 # number of demand (read+write) MSHR misses 2633system.l2c.demand_mshr_misses::cpu0.data 19748 # number of demand (read+write) MSHR misses 2634system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 129939 # number of demand (read+write) MSHR misses 2635system.l2c.demand_mshr_misses::cpu1.dtb.walker 40 # number of demand (read+write) MSHR misses 2636system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses 2637system.l2c.demand_mshr_misses::cpu1.inst 5975 # number of demand (read+write) MSHR misses 2638system.l2c.demand_mshr_misses::cpu1.data 10740 # number of demand (read+write) MSHR misses 2639system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 9112 # number of demand (read+write) MSHR misses 2640system.l2c.demand_mshr_misses::total 195735 # number of demand (read+write) MSHR misses 2641system.l2c.overall_mshr_misses::cpu0.dtb.walker 130 # number of overall MSHR misses 2642system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses 2643system.l2c.overall_mshr_misses::cpu0.inst 20049 # number of overall MSHR misses 2644system.l2c.overall_mshr_misses::cpu0.data 19748 # number of overall MSHR misses 2645system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 129939 # number of overall MSHR misses 2646system.l2c.overall_mshr_misses::cpu1.dtb.walker 40 # number of overall MSHR misses 2647system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 2648system.l2c.overall_mshr_misses::cpu1.inst 5975 # number of overall MSHR misses 2649system.l2c.overall_mshr_misses::cpu1.data 10740 # number of overall MSHR misses 2650system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 9112 # number of overall MSHR misses 2651system.l2c.overall_mshr_misses::total 195735 # number of overall MSHR misses 2652system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3367 # number of ReadReq MSHR uncacheable 2653system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29433 # number of ReadReq MSHR uncacheable 2654system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable 2655system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5712 # number of ReadReq MSHR uncacheable 2656system.l2c.ReadReq_mshr_uncacheable::total 38624 # number of ReadReq MSHR uncacheable 2657system.l2c.WriteReq_mshr_uncacheable::cpu0.data 26165 # number of WriteReq MSHR uncacheable 2658system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5010 # number of WriteReq MSHR uncacheable 2659system.l2c.WriteReq_mshr_uncacheable::total 31175 # number of WriteReq MSHR uncacheable 2660system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3367 # number of overall MSHR uncacheable misses 2661system.l2c.overall_mshr_uncacheable_misses::cpu0.data 55598 # number of overall MSHR uncacheable misses 2662system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses 2663system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10722 # number of overall MSHR uncacheable misses 2664system.l2c.overall_mshr_uncacheable_misses::total 69799 # number of overall MSHR uncacheable misses 2665system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 9340000 # number of ReadReq MSHR miss cycles 2666system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 70000 # number of ReadReq MSHR miss cycles 2667system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1359057992 # number of ReadReq MSHR miss cycles 2668system.l2c.ReadReq_mshr_miss_latency::cpu0.data 655200132 # number of ReadReq MSHR miss cycles 2669system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11920664281 # number of ReadReq MSHR miss cycles 2670system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 2921500 # number of ReadReq MSHR miss cycles 2671system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 70500 # number of ReadReq MSHR miss cycles 2672system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 420043242 # number of ReadReq MSHR miss cycles 2673system.l2c.ReadReq_mshr_miss_latency::cpu1.data 177097729 # number of ReadReq MSHR miss cycles 2674system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1006174503 # number of ReadReq MSHR miss cycles 2675system.l2c.ReadReq_mshr_miss_latency::total 15550639879 # number of ReadReq MSHR miss cycles 2676system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 155599187 # number of UpgradeReq MSHR miss cycles 2677system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 74220106 # number of UpgradeReq MSHR miss cycles 2678system.l2c.UpgradeReq_mshr_miss_latency::total 229819293 # number of UpgradeReq MSHR miss cycles 2679system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 14429805 # number of SCUpgradeReq MSHR miss cycles 2680system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 21503704 # number of SCUpgradeReq MSHR miss cycles 2681system.l2c.SCUpgradeReq_mshr_miss_latency::total 35933509 # number of SCUpgradeReq MSHR miss cycles 2682system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 890221812 # number of ReadExReq MSHR miss cycles 2683system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 588134799 # number of ReadExReq MSHR miss cycles 2684system.l2c.ReadExReq_mshr_miss_latency::total 1478356611 # number of ReadExReq MSHR miss cycles 2685system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 9340000 # number of demand (read+write) MSHR miss cycles 2686system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 70000 # number of demand (read+write) MSHR miss cycles 2687system.l2c.demand_mshr_miss_latency::cpu0.inst 1359057992 # number of demand (read+write) MSHR miss cycles 2688system.l2c.demand_mshr_miss_latency::cpu0.data 1545421944 # number of demand (read+write) MSHR miss cycles 2689system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11920664281 # number of demand (read+write) MSHR miss cycles 2690system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 2921500 # number of demand (read+write) MSHR miss cycles 2691system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 70500 # number of demand (read+write) MSHR miss cycles 2692system.l2c.demand_mshr_miss_latency::cpu1.inst 420043242 # number of demand (read+write) MSHR miss cycles 2693system.l2c.demand_mshr_miss_latency::cpu1.data 765232528 # number of demand (read+write) MSHR miss cycles 2694system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1006174503 # number of demand (read+write) MSHR miss cycles 2695system.l2c.demand_mshr_miss_latency::total 17028996490 # number of demand (read+write) MSHR miss cycles 2696system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 9340000 # number of overall MSHR miss cycles 2697system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 70000 # number of overall MSHR miss cycles 2698system.l2c.overall_mshr_miss_latency::cpu0.inst 1359057992 # number of overall MSHR miss cycles 2699system.l2c.overall_mshr_miss_latency::cpu0.data 1545421944 # number of overall MSHR miss cycles 2700system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11920664281 # number of overall MSHR miss cycles 2701system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2921500 # number of overall MSHR miss cycles 2702system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 70500 # number of overall MSHR miss cycles 2703system.l2c.overall_mshr_miss_latency::cpu1.inst 420043242 # number of overall MSHR miss cycles 2704system.l2c.overall_mshr_miss_latency::cpu1.data 765232528 # number of overall MSHR miss cycles 2705system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1006174503 # number of overall MSHR miss cycles 2706system.l2c.overall_mshr_miss_latency::total 17028996490 # number of overall MSHR miss cycles 2707system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 204708000 # number of ReadReq MSHR uncacheable cycles 2708system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4816468250 # number of ReadReq MSHR uncacheable cycles 2709system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6816000 # number of ReadReq MSHR uncacheable cycles 2710system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 820420250 # number of ReadReq MSHR uncacheable cycles 2711system.l2c.ReadReq_mshr_uncacheable_latency::total 5848412500 # number of ReadReq MSHR uncacheable cycles 2712system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3580583500 # number of WriteReq MSHR uncacheable cycles 2713system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 717922501 # number of WriteReq MSHR uncacheable cycles 2714system.l2c.WriteReq_mshr_uncacheable_latency::total 4298506001 # number of WriteReq MSHR uncacheable cycles 2715system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 204708000 # number of overall MSHR uncacheable cycles 2716system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8397051750 # number of overall MSHR uncacheable cycles 2717system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6816000 # number of overall MSHR uncacheable cycles 2718system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1538342751 # number of overall MSHR uncacheable cycles 2719system.l2c.overall_mshr_uncacheable_latency::total 10146918501 # number of overall MSHR uncacheable cycles 2720system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.257426 # mshr miss rate for ReadReq accesses 2721system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013514 # mshr miss rate for ReadReq accesses 2722system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.314400 # mshr miss rate for ReadReq accesses 2723system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.154815 # mshr miss rate for ReadReq accesses 2724system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739466 # mshr miss rate for ReadReq accesses 2725system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.193237 # mshr miss rate for ReadReq accesses 2726system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035714 # mshr miss rate for ReadReq accesses 2727system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.217835 # mshr miss rate for ReadReq accesses 2728system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.172068 # mshr miss rate for ReadReq accesses 2729system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530662 # mshr miss rate for ReadReq accesses 2730system.l2c.ReadReq_mshr_miss_rate::total 0.497459 # mshr miss rate for ReadReq accesses 2731system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.748777 # mshr miss rate for UpgradeReq accesses 2732system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.813546 # mshr miss rate for UpgradeReq accesses 2733system.l2c.UpgradeReq_mshr_miss_rate::total 0.768440 # mshr miss rate for UpgradeReq accesses 2734system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.764205 # mshr miss rate for SCUpgradeReq accesses 2735system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.931486 # mshr miss rate for SCUpgradeReq accesses 2736system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.856476 # mshr miss rate for SCUpgradeReq accesses 2737system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.731888 # mshr miss rate for ReadExReq accesses 2738system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.792373 # mshr miss rate for ReadExReq accesses 2739system.l2c.ReadExReq_mshr_miss_rate::total 0.756909 # mshr miss rate for ReadExReq accesses 2740system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.257426 # mshr miss rate for demand accesses 2741system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.013514 # mshr miss rate for demand accesses 2742system.l2c.demand_mshr_miss_rate::cpu0.inst 0.314400 # mshr miss rate for demand accesses 2743system.l2c.demand_mshr_miss_rate::cpu0.data 0.277480 # mshr miss rate for demand accesses 2744system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739466 # mshr miss rate for demand accesses 2745system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.193237 # mshr miss rate for demand accesses 2746system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.035714 # mshr miss rate for demand accesses 2747system.l2c.demand_mshr_miss_rate::cpu1.inst 0.217835 # mshr miss rate for demand accesses 2748system.l2c.demand_mshr_miss_rate::cpu1.data 0.448603 # mshr miss rate for demand accesses 2749system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530662 # mshr miss rate for demand accesses 2750system.l2c.demand_mshr_miss_rate::total 0.515074 # mshr miss rate for demand accesses 2751system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.257426 # mshr miss rate for overall accesses 2752system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.013514 # mshr miss rate for overall accesses 2753system.l2c.overall_mshr_miss_rate::cpu0.inst 0.314400 # mshr miss rate for overall accesses 2754system.l2c.overall_mshr_miss_rate::cpu0.data 0.277480 # mshr miss rate for overall accesses 2755system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739466 # mshr miss rate for overall accesses 2756system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.193237 # mshr miss rate for overall accesses 2757system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.035714 # mshr miss rate for overall accesses 2758system.l2c.overall_mshr_miss_rate::cpu1.inst 0.217835 # mshr miss rate for overall accesses 2759system.l2c.overall_mshr_miss_rate::cpu1.data 0.448603 # mshr miss rate for overall accesses 2760system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530662 # mshr miss rate for overall accesses 2761system.l2c.overall_mshr_miss_rate::total 0.515074 # mshr miss rate for overall accesses 2762system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71846.153846 # average ReadReq mshr miss latency |
| 2703system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency | 2763system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency |
| 2704system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68207.465922 # average ReadReq mshr miss latency 2705system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75854.403149 # average ReadReq mshr miss latency 2706system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90812.054018 # average ReadReq mshr miss latency 2707system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76892.857143 # average ReadReq mshr miss latency 2708system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70560.885515 # average ReadReq mshr miss latency 2709system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 79090.867580 # average ReadReq mshr miss latency 2710system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122229.036396 # average ReadReq mshr miss latency 2711system.l2c.ReadReq_avg_mshr_miss_latency::total 87801.166169 # average ReadReq mshr miss latency 2712system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17751.429622 # average UpgradeReq mshr miss latency 2713system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17758.884431 # average UpgradeReq mshr miss latency 2714system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17753.216423 # average UpgradeReq mshr miss latency 2715system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17896.675112 # average SCUpgradeReq mshr miss latency 2716system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17771.948923 # average SCUpgradeReq mshr miss latency 2717system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17815.447505 # average SCUpgradeReq mshr miss latency 2718system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79077.135895 # average ReadExReq mshr miss latency 2719system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69691.543041 # average ReadExReq mshr miss latency 2720system.l2c.ReadExReq_avg_mshr_miss_latency::total 75064.022094 # average ReadExReq mshr miss latency 2721system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78696.917808 # average overall mshr miss latency | 2764system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67786.821886 # average ReadReq mshr miss latency 2765system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75518.687414 # average ReadReq mshr miss latency 2766system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91740.464995 # average ReadReq mshr miss latency 2767system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73037.500000 # average ReadReq mshr miss latency 2768system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average ReadReq mshr miss latency 2769system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70300.124184 # average ReadReq mshr miss latency 2770system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77572.373631 # average ReadReq mshr miss latency 2771system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110423.013938 # average ReadReq mshr miss latency 2772system.l2c.ReadReq_avg_mshr_miss_latency::total 88252.612732 # average ReadReq mshr miss latency 2773system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17835.761921 # average UpgradeReq mshr miss latency 2774system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17962.271539 # average UpgradeReq mshr miss latency 2775system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17876.422915 # average UpgradeReq mshr miss latency 2776system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17880.799257 # average SCUpgradeReq mshr miss latency 2777system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17771.656198 # average SCUpgradeReq mshr miss latency 2778system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17815.324244 # average SCUpgradeReq mshr miss latency 2779system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80402.981575 # average ReadExReq mshr miss latency 2780system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69544.140830 # average ReadExReq mshr miss latency 2781system.l2c.ReadExReq_avg_mshr_miss_latency::total 75700.579190 # average ReadExReq mshr miss latency 2782system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71846.153846 # average overall mshr miss latency |
| 2722system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency | 2783system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency |
| 2723system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68207.465922 # average overall mshr miss latency 2724system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77572.664185 # average overall mshr miss latency 2725system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90812.054018 # average overall mshr miss latency 2726system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76892.857143 # average overall mshr miss latency 2727system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70560.885515 # average overall mshr miss latency 2728system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70775.623552 # average overall mshr miss latency 2729system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122229.036396 # average overall mshr miss latency 2730system.l2c.demand_avg_mshr_miss_latency::total 86523.829726 # average overall mshr miss latency 2731system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78696.917808 # average overall mshr miss latency | 2784system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67786.821886 # average overall mshr miss latency 2785system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78257.137128 # average overall mshr miss latency 2786system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91740.464995 # average overall mshr miss latency 2787system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73037.500000 # average overall mshr miss latency 2788system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average overall mshr miss latency 2789system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70300.124184 # average overall mshr miss latency 2790system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71250.700931 # average overall mshr miss latency 2791system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110423.013938 # average overall mshr miss latency 2792system.l2c.demand_avg_mshr_miss_latency::total 87000.263060 # average overall mshr miss latency 2793system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71846.153846 # average overall mshr miss latency |
| 2732system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency | 2794system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency |
| 2733system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68207.465922 # average overall mshr miss latency 2734system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77572.664185 # average overall mshr miss latency 2735system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90812.054018 # average overall mshr miss latency 2736system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76892.857143 # average overall mshr miss latency 2737system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70560.885515 # average overall mshr miss latency 2738system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70775.623552 # average overall mshr miss latency 2739system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122229.036396 # average overall mshr miss latency 2740system.l2c.overall_avg_mshr_miss_latency::total 86523.829726 # average overall mshr miss latency 2741system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 2742system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 2743system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2744system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2745system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2746system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 2747system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2748system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2749system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 2750system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 2751system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2752system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2753system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 2795system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67786.821886 # average overall mshr miss latency 2796system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78257.137128 # average overall mshr miss latency 2797system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91740.464995 # average overall mshr miss latency 2798system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73037.500000 # average overall mshr miss latency 2799system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average overall mshr miss latency 2800system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70300.124184 # average overall mshr miss latency 2801system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71250.700931 # average overall mshr miss latency 2802system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110423.013938 # average overall mshr miss latency 2803system.l2c.overall_avg_mshr_miss_latency::total 87000.263060 # average overall mshr miss latency 2804system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average ReadReq mshr uncacheable latency 2805system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 163641.771141 # average ReadReq mshr uncacheable latency 2806system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60857.142857 # average ReadReq mshr uncacheable latency 2807system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143630.996148 # average ReadReq mshr uncacheable latency 2808system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 151419.130592 # average ReadReq mshr uncacheable latency 2809system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 136846.302312 # average WriteReq mshr uncacheable latency 2810system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143297.904391 # average WriteReq mshr uncacheable latency 2811system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 137883.111500 # average WriteReq mshr uncacheable latency 2812system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average overall mshr uncacheable latency 2813system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151031.543401 # average overall mshr uncacheable latency 2814system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60857.142857 # average overall mshr uncacheable latency 2815system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 143475.354505 # average overall mshr uncacheable latency 2816system.l2c.overall_avg_mshr_uncacheable_latency::total 145373.407943 # average overall mshr uncacheable latency |
| 2754system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 2817system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2755system.membus.trans_dist::ReadReq 214962 # Transaction distribution 2756system.membus.trans_dist::ReadResp 214962 # Transaction distribution 2757system.membus.trans_dist::WriteReq 31066 # Transaction distribution 2758system.membus.trans_dist::WriteResp 31066 # Transaction distribution 2759system.membus.trans_dist::Writeback 138129 # Transaction distribution | 2818system.membus.trans_dist::ReadReq 215059 # Transaction distribution 2819system.membus.trans_dist::ReadResp 215059 # Transaction distribution 2820system.membus.trans_dist::WriteReq 31175 # Transaction distribution 2821system.membus.trans_dist::WriteResp 31175 # Transaction distribution 2822system.membus.trans_dist::Writeback 138467 # Transaction distribution |
| 2760system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2761system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution | 2823system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2824system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 2762system.membus.trans_dist::UpgradeReq 76255 # Transaction distribution 2763system.membus.trans_dist::SCUpgradeReq 40796 # Transaction distribution 2764system.membus.trans_dist::UpgradeResp 14193 # Transaction distribution 2765system.membus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution 2766system.membus.trans_dist::ReadExReq 40018 # Transaction distribution 2767system.membus.trans_dist::ReadExResp 19540 # Transaction distribution 2768system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) | 2825system.membus.trans_dist::UpgradeReq 78265 # Transaction distribution 2826system.membus.trans_dist::SCUpgradeReq 41611 # Transaction distribution 2827system.membus.trans_dist::UpgradeResp 15010 # Transaction distribution 2828system.membus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution 2829system.membus.trans_dist::ReadExReq 39963 # Transaction distribution 2830system.membus.trans_dist::ReadExResp 19392 # Transaction distribution 2831system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) |
| 2769system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) | 2832system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) |
| 2770system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14158 # Packet count per connected master and slave (bytes) 2771system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661851 # Packet count per connected master and slave (bytes) 2772system.membus.pkt_count_system.l2c.mem_side::total 783963 # Packet count per connected master and slave (bytes) 2773system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108912 # Packet count per connected master and slave (bytes) 2774system.membus.pkt_count_system.iocache.mem_side::total 108912 # Packet count per connected master and slave (bytes) 2775system.membus.pkt_count::total 892875 # Packet count per connected master and slave (bytes) 2776system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) | 2833system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14788 # Packet count per connected master and slave (bytes) 2834system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 665413 # Packet count per connected master and slave (bytes) 2835system.membus.pkt_count_system.l2c.mem_side::total 788151 # Packet count per connected master and slave (bytes) 2836system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108866 # Packet count per connected master and slave (bytes) 2837system.membus.pkt_count_system.iocache.mem_side::total 108866 # Packet count per connected master and slave (bytes) 2838system.membus.pkt_count::total 897017 # Packet count per connected master and slave (bytes) 2839system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) |
| 2777system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) | 2840system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) |
| 2778system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28316 # Cumulative packet size per connected master and slave (bytes) 2779system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19273388 # Cumulative packet size per connected master and slave (bytes) 2780system.membus.pkt_size_system.l2c.mem_side::total 19465716 # Cumulative packet size per connected master and slave (bytes) 2781system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) 2782system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) 2783system.membus.pkt_size::total 24102196 # Cumulative packet size per connected master and slave (bytes) 2784system.membus.snoops 123912 # Total snoops (count) 2785system.membus.snoop_fanout::samples 507941 # Request fanout histogram | 2841system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29576 # Cumulative packet size per connected master and slave (bytes) 2842system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19282584 # Cumulative packet size per connected master and slave (bytes) 2843system.membus.pkt_size_system.l2c.mem_side::total 19476170 # Cumulative packet size per connected master and slave (bytes) 2844system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4634432 # Cumulative packet size per connected master and slave (bytes) 2845system.membus.pkt_size_system.iocache.mem_side::total 4634432 # Cumulative packet size per connected master and slave (bytes) 2846system.membus.pkt_size::total 24110602 # Cumulative packet size per connected master and slave (bytes) 2847system.membus.snoops 126068 # Total snoops (count) 2848system.membus.snoop_fanout::samples 580884 # Request fanout histogram |
| 2786system.membus.snoop_fanout::mean 1 # Request fanout histogram 2787system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2788system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2789system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 2849system.membus.snoop_fanout::mean 1 # Request fanout histogram 2850system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2851system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2852system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 2790system.membus.snoop_fanout::1 507941 100.00% 100.00% # Request fanout histogram | 2853system.membus.snoop_fanout::1 580884 100.00% 100.00% # Request fanout histogram |
| 2791system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2792system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2793system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2794system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 2854system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2855system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2856system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2857system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 2795system.membus.snoop_fanout::total 507941 # Request fanout histogram 2796system.membus.reqLayer0.occupancy 88612000 # Layer occupancy (ticks) | 2858system.membus.snoop_fanout::total 580884 # Request fanout histogram 2859system.membus.reqLayer0.occupancy 88642500 # Layer occupancy (ticks) |
| 2797system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2798system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) 2799system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 2860system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2861system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) 2862system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 2800system.membus.reqLayer2.occupancy 12528499 # Layer occupancy (ticks) | 2863system.membus.reqLayer2.occupancy 13073499 # Layer occupancy (ticks) |
| 2801system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 2864system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 2802system.membus.reqLayer5.occupancy 1167691410 # Layer occupancy (ticks) | 2865system.membus.reqLayer5.occupancy 1170162100 # Layer occupancy (ticks) |
| 2803system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 2866system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 2804system.membus.respLayer2.occupancy 1172073016 # Layer occupancy (ticks) | 2867system.membus.respLayer2.occupancy 1173257543 # Layer occupancy (ticks) |
| 2805system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 2868system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2806system.membus.respLayer3.occupancy 37476242 # Layer occupancy (ticks) | 2869system.membus.respLayer3.occupancy 37390482 # Layer occupancy (ticks) |
| 2807system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2808system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2809system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2810system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2811system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2812system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2813system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2814system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 2831system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2832system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2833system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2834system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2835system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2836system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2837system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2838system.realview.ethernet.droppedPackets 0 # number of packets dropped | 2870system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2871system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2872system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2873system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2874system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2875system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2876system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2877system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 2894system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2895system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2896system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2897system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2898system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2899system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2900system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2901system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 2839system.toL2Bus.trans_dist::ReadReq 516720 # Transaction distribution 2840system.toL2Bus.trans_dist::ReadResp 516705 # Transaction distribution 2841system.toL2Bus.trans_dist::WriteReq 31066 # Transaction distribution 2842system.toL2Bus.trans_dist::WriteResp 31066 # Transaction distribution 2843system.toL2Bus.trans_dist::Writeback 232835 # Transaction distribution 2844system.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution 2845system.toL2Bus.trans_dist::UpgradeReq 79932 # Transaction distribution 2846system.toL2Bus.trans_dist::SCUpgradeReq 41134 # Transaction distribution 2847system.toL2Bus.trans_dist::UpgradeResp 121066 # Transaction distribution 2848system.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution 2849system.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution 2850system.toL2Bus.trans_dist::ReadExReq 51762 # Transaction distribution 2851system.toL2Bus.trans_dist::ReadExResp 51762 # Transaction distribution 2852system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1083099 # Packet count per connected master and slave (bytes) 2853system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 338756 # Packet count per connected master and slave (bytes) 2854system.toL2Bus.pkt_count::total 1421855 # Packet count per connected master and slave (bytes) 2855system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34093856 # Cumulative packet size per connected master and slave (bytes) 2856system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5618324 # Cumulative packet size per connected master and slave (bytes) 2857system.toL2Bus.pkt_size::total 39712180 # Cumulative packet size per connected master and slave (bytes) 2858system.toL2Bus.snoops 288702 # Total snoops (count) 2859system.toL2Bus.snoop_fanout::samples 920160 # Request fanout histogram 2860system.toL2Bus.snoop_fanout::mean 1.039660 # Request fanout histogram 2861system.toL2Bus.snoop_fanout::stdev 0.195160 # Request fanout histogram | 2902system.toL2Bus.trans_dist::ReadReq 519203 # Transaction distribution 2903system.toL2Bus.trans_dist::ReadResp 519188 # Transaction distribution 2904system.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution 2905system.toL2Bus.trans_dist::WriteResp 31175 # Transaction distribution 2906system.toL2Bus.trans_dist::Writeback 233506 # Transaction distribution 2907system.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution 2908system.toL2Bus.trans_dist::UpgradeReq 82002 # Transaction distribution 2909system.toL2Bus.trans_dist::SCUpgradeReq 41949 # Transaction distribution 2910system.toL2Bus.trans_dist::UpgradeResp 123951 # Transaction distribution 2911system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution 2912system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution 2913system.toL2Bus.trans_dist::ReadExReq 51897 # Transaction distribution 2914system.toL2Bus.trans_dist::ReadExResp 51897 # Transaction distribution 2915system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1081118 # Packet count per connected master and slave (bytes) 2916system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 347519 # Packet count per connected master and slave (bytes) 2917system.toL2Bus.pkt_count::total 1428637 # Packet count per connected master and slave (bytes) 2918system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32891255 # Cumulative packet size per connected master and slave (bytes) 2919system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6822675 # Cumulative packet size per connected master and slave (bytes) 2920system.toL2Bus.pkt_size::total 39713930 # Cumulative packet size per connected master and slave (bytes) 2921system.toL2Bus.snoops 293844 # Total snoops (count) 2922system.toL2Bus.snoop_fanout::samples 996034 # Request fanout histogram 2923system.toL2Bus.snoop_fanout::mean 1.036652 # Request fanout histogram 2924system.toL2Bus.snoop_fanout::stdev 0.187907 # Request fanout histogram |
| 2862system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2863system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 2925system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2926system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 2864system.toL2Bus.snoop_fanout::1 883666 96.03% 96.03% # Request fanout histogram 2865system.toL2Bus.snoop_fanout::2 36494 3.97% 100.00% # Request fanout histogram | 2927system.toL2Bus.snoop_fanout::1 959527 96.33% 96.33% # Request fanout histogram 2928system.toL2Bus.snoop_fanout::2 36507 3.67% 100.00% # Request fanout histogram |
| 2866system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2867system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2868system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 2929system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2930system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2931system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 2869system.toL2Bus.snoop_fanout::total 920160 # Request fanout histogram 2870system.toL2Bus.reqLayer0.occupancy 787000770 # Layer occupancy (ticks) | 2932system.toL2Bus.snoop_fanout::total 996034 # Request fanout histogram 2933system.toL2Bus.reqLayer0.occupancy 791138952 # Layer occupancy (ticks) |
| 2871system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 2934system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 2872system.toL2Bus.snoopLayer0.occupancy 342000 # Layer occupancy (ticks) | 2935system.toL2Bus.snoopLayer0.occupancy 321000 # Layer occupancy (ticks) |
| 2873system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2936system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2874system.toL2Bus.respLayer0.occupancy 681574777 # Layer occupancy (ticks) | 2937system.toL2Bus.respLayer0.occupancy 673122022 # Layer occupancy (ticks) |
| 2875system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 2938system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2876system.toL2Bus.respLayer1.occupancy 259216519 # Layer occupancy (ticks) | 2939system.toL2Bus.respLayer1.occupancy 273051412 # Layer occupancy (ticks) |
| 2877system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2878 2879---------- End Simulation Statistics ---------- | 2940system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2941 2942---------- End Simulation Statistics ---------- |