| stats.txt (10636:9ac724889705) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.845843 # Number of seconds simulated 4sim_ticks 2845842660500 # Number of ticks simulated 5final_tick 2845842660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.846001 # Number of seconds simulated 4sim_ticks 2846001096000 # Number of ticks simulated 5final_tick 2846001096000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 92448 # Simulator instruction rate (inst/s) 8host_op_rate 111941 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2101025547 # Simulator tick rate (ticks/s) 10host_mem_usage 635156 # Number of bytes of host memory used 11host_seconds 1354.50 # Real time elapsed on the host 12sim_insts 125221621 # Number of instructions simulated 13sim_ops 151624712 # Number of ops (including micro ops) simulated | 7host_inst_rate 163513 # Simulator instruction rate (inst/s) 8host_op_rate 197998 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3697981305 # Simulator tick rate (ticks/s) 10host_mem_usage 648920 # Number of bytes of host memory used 11host_seconds 769.61 # Real time elapsed on the host 12sim_insts 125841424 # Number of instructions simulated 13sim_ops 152380857 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu0.dtb.walker 10368 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu0.dtb.walker 9664 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu0.inst 1722304 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1285116 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8732480 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 153024 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 621216 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 399936 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu0.inst 1676864 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1253436 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8602112 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 217536 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 601248 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 396864 # Number of bytes read from this memory |
| 25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 26system.physmem.bytes_read::total 12926236 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 1722304 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 153024 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 1875328 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 8977344 # Number of bytes written to this memory | 26system.physmem.bytes_read::total 12760092 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 1676864 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 217536 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 1894400 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 8825856 # Number of bytes written to this memory |
| 31system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory | 31system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory |
| 33system.physmem.bytes_written::total 8995088 # Number of bytes written to this memory 34system.physmem.num_reads::cpu0.dtb.walker 162 # Number of read requests responded to by this memory | 33system.physmem.bytes_written::total 8843600 # Number of bytes written to this memory 34system.physmem.num_reads::cpu0.dtb.walker 151 # Number of read requests responded to by this memory |
| 35system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory | 35system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory |
| 36system.physmem.num_reads::cpu0.inst 26911 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 20605 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.l2cache.prefetcher 136445 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.inst 2391 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.data 9730 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.l2cache.prefetcher 6249 # Number of read requests responded to by this memory | 36system.physmem.num_reads::cpu0.inst 26201 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 20110 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.l2cache.prefetcher 134408 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.inst 3399 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.data 9418 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.l2cache.prefetcher 6201 # Number of read requests responded to by this memory |
| 43system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 43system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 44system.physmem.num_reads::total 202521 # Number of read requests responded to by this memory 45system.physmem.num_writes::writebacks 140271 # Number of write requests responded to by this memory | 44system.physmem.num_reads::total 199925 # Number of read requests responded to by this memory 45system.physmem.num_writes::writebacks 137904 # Number of write requests responded to by this memory |
| 46system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 47system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory | 46system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 47system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory |
| 48system.physmem.num_writes::total 144707 # Number of write requests responded to by this memory 49system.physmem.bw_read::cpu0.dtb.walker 3643 # Total read bandwidth from this memory (bytes/s) | 48system.physmem.num_writes::total 142340 # Number of write requests responded to by this memory 49system.physmem.bw_read::cpu0.dtb.walker 3396 # Total read bandwidth from this memory (bytes/s) |
| 50system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) | 50system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) |
| 51system.physmem.bw_read::cpu0.inst 605200 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.data 451577 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.l2cache.prefetcher 3068504 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.dtb.walker 270 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.inst 53771 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.data 218289 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.l2cache.prefetcher 140533 # Total read bandwidth from this memory (bytes/s) | 51system.physmem.bw_read::cpu0.inst 589200 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.data 440420 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.l2cache.prefetcher 3022526 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.dtb.walker 472 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.inst 76436 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.data 211261 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.l2cache.prefetcher 139446 # Total read bandwidth from this memory (bytes/s) |
| 58system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) | 58system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) |
| 59system.physmem.bw_read::total 4542147 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::cpu0.inst 605200 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu1.inst 53771 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::total 658971 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_write::writebacks 3154547 # Write bandwidth from this memory (bytes/s) | 59system.physmem.bw_read::total 4483516 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::cpu0.inst 589200 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu1.inst 76436 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::total 665636 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_write::writebacks 3101143 # Write bandwidth from this memory (bytes/s) |
| 64system.physmem.bw_write::cpu0.data 6221 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) | 64system.physmem.bw_write::cpu0.data 6221 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) |
| 66system.physmem.bw_write::total 3160782 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_total::writebacks 3154547 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.dtb.walker 3643 # Total bandwidth to/from this memory (bytes/s) | 66system.physmem.bw_write::total 3107378 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_total::writebacks 3101143 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.dtb.walker 3396 # Total bandwidth to/from this memory (bytes/s) |
| 69system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) | 69system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) |
| 70system.physmem.bw_total::cpu0.inst 605200 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.data 457798 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.l2cache.prefetcher 3068504 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.dtb.walker 270 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.inst 53771 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.data 218303 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.l2cache.prefetcher 140533 # Total bandwidth to/from this memory (bytes/s) | 70system.physmem.bw_total::cpu0.inst 589200 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.data 446641 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.l2cache.prefetcher 3022526 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.dtb.walker 472 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.inst 76436 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.data 211275 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.l2cache.prefetcher 139446 # Total bandwidth to/from this memory (bytes/s) |
| 77system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) | 77system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) |
| 78system.physmem.bw_total::total 7702929 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.readReqs 202521 # Number of read requests accepted 80system.physmem.writeReqs 180931 # Number of write requests accepted 81system.physmem.readBursts 202521 # Number of DRAM read bursts, including those serviced by the write queue 82system.physmem.writeBursts 180931 # Number of DRAM write bursts, including those merged in the write queue 83system.physmem.bytesReadDRAM 12951936 # Total number of bytes read from DRAM 84system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue 85system.physmem.bytesWritten 11206784 # Total number of bytes written to DRAM 86system.physmem.bytesReadSys 12926236 # Total read bytes from the system interface side 87system.physmem.bytesWrittenSys 11313424 # Total written bytes from the system interface side 88system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue 89system.physmem.mergedWrBursts 5797 # Number of DRAM write bursts merged with an existing one 90system.physmem.neitherReadNorWriteReqs 13571 # Number of requests that are neither read nor write 91system.physmem.perBankRdBursts::0 12806 # Per bank write bursts 92system.physmem.perBankRdBursts::1 12696 # Per bank write bursts 93system.physmem.perBankRdBursts::2 13455 # Per bank write bursts 94system.physmem.perBankRdBursts::3 13223 # Per bank write bursts 95system.physmem.perBankRdBursts::4 15141 # Per bank write bursts 96system.physmem.perBankRdBursts::5 12251 # Per bank write bursts 97system.physmem.perBankRdBursts::6 12720 # Per bank write bursts 98system.physmem.perBankRdBursts::7 12666 # Per bank write bursts 99system.physmem.perBankRdBursts::8 12396 # Per bank write bursts 100system.physmem.perBankRdBursts::9 12410 # Per bank write bursts 101system.physmem.perBankRdBursts::10 12030 # Per bank write bursts 102system.physmem.perBankRdBursts::11 11077 # Per bank write bursts 103system.physmem.perBankRdBursts::12 12224 # Per bank write bursts 104system.physmem.perBankRdBursts::13 12978 # Per bank write bursts 105system.physmem.perBankRdBursts::14 12239 # Per bank write bursts 106system.physmem.perBankRdBursts::15 12062 # Per bank write bursts 107system.physmem.perBankWrBursts::0 11243 # Per bank write bursts 108system.physmem.perBankWrBursts::1 11520 # Per bank write bursts 109system.physmem.perBankWrBursts::2 11868 # Per bank write bursts 110system.physmem.perBankWrBursts::3 11342 # Per bank write bursts 111system.physmem.perBankWrBursts::4 10753 # Per bank write bursts 112system.physmem.perBankWrBursts::5 10659 # Per bank write bursts 113system.physmem.perBankWrBursts::6 11197 # Per bank write bursts 114system.physmem.perBankWrBursts::7 10854 # Per bank write bursts 115system.physmem.perBankWrBursts::8 10720 # Per bank write bursts 116system.physmem.perBankWrBursts::9 10780 # Per bank write bursts 117system.physmem.perBankWrBursts::10 10917 # Per bank write bursts 118system.physmem.perBankWrBursts::11 10553 # Per bank write bursts 119system.physmem.perBankWrBursts::12 10892 # Per bank write bursts 120system.physmem.perBankWrBursts::13 10850 # Per bank write bursts 121system.physmem.perBankWrBursts::14 10512 # Per bank write bursts 122system.physmem.perBankWrBursts::15 10446 # Per bank write bursts | 78system.physmem.bw_total::total 7590894 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.readReqs 199925 # Number of read requests accepted 80system.physmem.writeReqs 178564 # Number of write requests accepted 81system.physmem.readBursts 199925 # Number of DRAM read bursts, including those serviced by the write queue 82system.physmem.writeBursts 178564 # Number of DRAM write bursts, including those merged in the write queue 83system.physmem.bytesReadDRAM 12787648 # Total number of bytes read from DRAM 84system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue 85system.physmem.bytesWritten 9914112 # Total number of bytes written to DRAM 86system.physmem.bytesReadSys 12760092 # Total read bytes from the system interface side 87system.physmem.bytesWrittenSys 11161936 # Total written bytes from the system interface side 88system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue 89system.physmem.mergedWrBursts 23627 # Number of DRAM write bursts merged with an existing one 90system.physmem.neitherReadNorWriteReqs 14395 # Number of requests that are neither read nor write 91system.physmem.perBankRdBursts::0 11804 # Per bank write bursts 92system.physmem.perBankRdBursts::1 12403 # Per bank write bursts 93system.physmem.perBankRdBursts::2 13173 # Per bank write bursts 94system.physmem.perBankRdBursts::3 12915 # Per bank write bursts 95system.physmem.perBankRdBursts::4 15440 # Per bank write bursts 96system.physmem.perBankRdBursts::5 12419 # Per bank write bursts 97system.physmem.perBankRdBursts::6 12541 # Per bank write bursts 98system.physmem.perBankRdBursts::7 12439 # Per bank write bursts 99system.physmem.perBankRdBursts::8 12804 # Per bank write bursts 100system.physmem.perBankRdBursts::9 13107 # Per bank write bursts 101system.physmem.perBankRdBursts::10 11847 # Per bank write bursts 102system.physmem.perBankRdBursts::11 11130 # Per bank write bursts 103system.physmem.perBankRdBursts::12 12155 # Per bank write bursts 104system.physmem.perBankRdBursts::13 12699 # Per bank write bursts 105system.physmem.perBankRdBursts::14 11526 # Per bank write bursts 106system.physmem.perBankRdBursts::15 11405 # Per bank write bursts 107system.physmem.perBankWrBursts::0 9464 # Per bank write bursts 108system.physmem.perBankWrBursts::1 9978 # Per bank write bursts 109system.physmem.perBankWrBursts::2 10476 # Per bank write bursts 110system.physmem.perBankWrBursts::3 10111 # Per bank write bursts 111system.physmem.perBankWrBursts::4 9384 # Per bank write bursts 112system.physmem.perBankWrBursts::5 9602 # Per bank write bursts 113system.physmem.perBankWrBursts::6 9874 # Per bank write bursts 114system.physmem.perBankWrBursts::7 9552 # Per bank write bursts 115system.physmem.perBankWrBursts::8 9896 # Per bank write bursts 116system.physmem.perBankWrBursts::9 10357 # Per bank write bursts 117system.physmem.perBankWrBursts::10 9473 # Per bank write bursts 118system.physmem.perBankWrBursts::11 9143 # Per bank write bursts 119system.physmem.perBankWrBursts::12 9886 # Per bank write bursts 120system.physmem.perBankWrBursts::13 9717 # Per bank write bursts 121system.physmem.perBankWrBursts::14 9232 # Per bank write bursts 122system.physmem.perBankWrBursts::15 8763 # Per bank write bursts |
| 123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 124system.physmem.numWrRetry 2 # Number of times write queue was full causing retry 125system.physmem.totGap 2845842079500 # Total gap between requests | 124system.physmem.numWrRetry 62 # Number of times write queue was full causing retry 125system.physmem.totGap 2846000520000 # Total gap between requests |
| 126system.physmem.readPktSize::0 0 # Read request sizes (log2) 127system.physmem.readPktSize::1 0 # Read request sizes (log2) 128system.physmem.readPktSize::2 559 # Read request sizes (log2) 129system.physmem.readPktSize::3 28 # Read request sizes (log2) 130system.physmem.readPktSize::4 0 # Read request sizes (log2) 131system.physmem.readPktSize::5 0 # Read request sizes (log2) | 126system.physmem.readPktSize::0 0 # Read request sizes (log2) 127system.physmem.readPktSize::1 0 # Read request sizes (log2) 128system.physmem.readPktSize::2 559 # Read request sizes (log2) 129system.physmem.readPktSize::3 28 # Read request sizes (log2) 130system.physmem.readPktSize::4 0 # Read request sizes (log2) 131system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 132system.physmem.readPktSize::6 201934 # Read request sizes (log2) | 132system.physmem.readPktSize::6 199338 # Read request sizes (log2) |
| 133system.physmem.writePktSize::0 0 # Write request sizes (log2) 134system.physmem.writePktSize::1 0 # Write request sizes (log2) 135system.physmem.writePktSize::2 4436 # Write request sizes (log2) 136system.physmem.writePktSize::3 0 # Write request sizes (log2) 137system.physmem.writePktSize::4 0 # Write request sizes (log2) 138system.physmem.writePktSize::5 0 # Write request sizes (log2) | 133system.physmem.writePktSize::0 0 # Write request sizes (log2) 134system.physmem.writePktSize::1 0 # Write request sizes (log2) 135system.physmem.writePktSize::2 4436 # Write request sizes (log2) 136system.physmem.writePktSize::3 0 # Write request sizes (log2) 137system.physmem.writePktSize::4 0 # Write request sizes (log2) 138system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 139system.physmem.writePktSize::6 176495 # Write request sizes (log2) 140system.physmem.rdQLenPdf::0 98520 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 50579 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 12267 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 9843 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 8294 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 6337 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 5553 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 4965 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 4352 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 735 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 300 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 250 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::12 218 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::13 156 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see | 139system.physmem.writePktSize::6 174128 # Write request sizes (log2) 140system.physmem.rdQLenPdf::0 99213 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 47252 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 13156 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 10017 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 7935 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 6072 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 5376 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 4784 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 4217 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 818 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 297 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 297 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::12 198 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::13 168 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see |
| 156system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 156system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 187system.physmem.wrQLenPdf::15 2878 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::16 4586 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::17 6172 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::18 7768 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::19 8767 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::20 10076 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::21 10729 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::22 11682 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::23 11838 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::24 12804 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::25 12238 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::26 12014 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::27 11495 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::28 11369 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::29 9447 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::30 9041 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::31 8809 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::32 8307 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::33 693 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::34 570 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::35 469 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::36 381 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::37 332 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::38 285 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::39 233 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::40 218 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::41 204 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::42 186 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::43 200 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::44 181 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::45 147 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::46 135 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::49 128 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::50 115 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::59 8 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::60 5 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see 236system.physmem.bytesPerActivate::samples 94139 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::mean 256.627498 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::gmean 142.457232 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::stdev 317.924062 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::0-127 48795 51.83% 51.83% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::128-255 18347 19.49% 71.32% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::256-383 6488 6.89% 78.21% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::384-511 3770 4.00% 82.22% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::512-639 2738 2.91% 85.13% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::640-767 1619 1.72% 86.85% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::768-895 964 1.02% 87.87% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::896-1023 1076 1.14% 89.01% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::1024-1151 10342 10.99% 100.00% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::total 94139 # Bytes accessed per row activation 250system.physmem.rdPerTurnAround::samples 7479 # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::mean 27.058430 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::stdev 520.327968 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::0-2047 7478 99.99% 99.99% # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::total 7479 # Reads before turning the bus around for writes 256system.physmem.wrPerTurnAround::samples 7479 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::mean 23.413023 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::gmean 19.870843 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::stdev 21.578889 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::16-23 6390 85.44% 85.44% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::24-31 248 3.32% 88.76% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::32-39 198 2.65% 91.40% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::40-47 77 1.03% 92.43% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::48-55 144 1.93% 94.36% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::56-63 30 0.40% 94.76% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::64-71 35 0.47% 95.23% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::72-79 33 0.44% 95.67% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::80-87 72 0.96% 96.63% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::88-95 21 0.28% 96.91% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::96-103 96 1.28% 98.19% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::104-111 18 0.24% 98.44% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::112-119 22 0.29% 98.73% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::120-127 12 0.16% 98.89% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::128-135 35 0.47% 99.36% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::136-143 4 0.05% 99.41% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::144-151 12 0.16% 99.57% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::152-159 4 0.05% 99.63% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::160-167 8 0.11% 99.73% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::168-175 2 0.03% 99.76% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::176-183 4 0.05% 99.81% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::184-191 3 0.04% 99.85% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::200-207 2 0.03% 99.88% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::208-215 2 0.03% 99.91% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::216-223 2 0.03% 99.93% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::224-231 1 0.01% 99.95% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::232-239 1 0.01% 99.96% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::248-255 2 0.03% 99.99% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::264-271 1 0.01% 100.00% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::total 7479 # Writes before turning the bus around for reads 290system.physmem.totQLat 5783977250 # Total ticks spent queuing 291system.physmem.totMemAccLat 9578489750 # Total ticks spent from burst creation until serviced by the DRAM 292system.physmem.totBusLat 1011870000 # Total ticks spent in databus transfers 293system.physmem.avgQLat 28580.63 # Average queueing delay per DRAM burst | 187system.physmem.wrQLenPdf::15 2204 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::16 2419 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::17 3811 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::18 4849 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::19 5527 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::20 6119 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::21 6557 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::22 6912 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::23 8140 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::24 7330 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::25 7722 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::26 9551 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::27 8386 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::28 8378 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::29 10984 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::30 8774 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::31 8231 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::32 7780 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::33 1483 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::34 1356 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::35 1653 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::36 2286 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::37 2184 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::38 1751 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::39 1846 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::40 2527 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::41 1977 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::42 1892 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::43 1780 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::44 1818 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::45 1302 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::46 1433 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::47 1245 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::48 955 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::49 771 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::50 424 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::51 397 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::52 331 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::53 276 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::54 208 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::55 201 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::56 216 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::58 175 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::59 145 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::60 111 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::61 133 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::62 75 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::63 117 # What write queue length does an incoming req see 236system.physmem.bytesPerActivate::samples 90945 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::mean 249.620056 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::gmean 140.134877 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::stdev 309.994619 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::0-127 47499 52.23% 52.23% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::128-255 17879 19.66% 71.89% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::256-383 6335 6.97% 78.85% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::384-511 3699 4.07% 82.92% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::512-639 2819 3.10% 86.02% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::640-767 1518 1.67% 87.69% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::768-895 969 1.07% 88.75% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::896-1023 1044 1.15% 89.90% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::1024-1151 9183 10.10% 100.00% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::total 90945 # Bytes accessed per row activation 250system.physmem.rdPerTurnAround::samples 6522 # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::mean 30.635388 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::stdev 556.912572 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::0-2047 6520 99.97% 99.97% # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::total 6522 # Reads before turning the bus around for writes 257system.physmem.wrPerTurnAround::samples 6522 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::mean 23.751610 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::gmean 18.656400 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::stdev 41.548658 # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::16-31 6178 94.73% 94.73% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::32-47 86 1.32% 96.04% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::48-63 19 0.29% 96.34% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::64-79 12 0.18% 96.52% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::80-95 33 0.51% 97.03% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::96-111 33 0.51% 97.53% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::112-127 29 0.44% 97.98% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::128-143 13 0.20% 98.18% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::144-159 13 0.20% 98.37% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::160-175 4 0.06% 98.44% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::176-191 22 0.34% 98.77% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::192-207 18 0.28% 99.05% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::208-223 8 0.12% 99.17% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::224-239 6 0.09% 99.26% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::256-271 3 0.05% 99.31% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::288-303 3 0.05% 99.36% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::304-319 5 0.08% 99.43% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::320-335 5 0.08% 99.51% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::336-351 7 0.11% 99.62% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::352-367 9 0.14% 99.75% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::368-383 1 0.02% 99.77% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::384-399 1 0.02% 99.79% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::432-447 1 0.02% 99.80% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::496-511 2 0.03% 99.83% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::512-527 2 0.03% 99.86% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::528-543 2 0.03% 99.89% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::544-559 2 0.03% 99.92% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::576-591 1 0.02% 99.94% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::640-655 1 0.02% 99.95% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::688-703 1 0.02% 99.97% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::896-911 1 0.02% 99.98% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::total 6522 # Writes before turning the bus around for reads 294system.physmem.totQLat 5658505376 # Total ticks spent queuing 295system.physmem.totMemAccLat 9404886626 # Total ticks spent from burst creation until serviced by the DRAM 296system.physmem.totBusLat 999035000 # Total ticks spent in databus transfers 297system.physmem.avgQLat 28319.86 # Average queueing delay per DRAM burst |
| 294system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 298system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 295system.physmem.avgMemAccLat 47330.63 # Average memory access latency per DRAM burst 296system.physmem.avgRdBW 4.55 # Average DRAM read bandwidth in MiByte/s 297system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MiByte/s 298system.physmem.avgRdBWSys 4.54 # Average system read bandwidth in MiByte/s 299system.physmem.avgWrBWSys 3.98 # Average system write bandwidth in MiByte/s | 299system.physmem.avgMemAccLat 47069.86 # Average memory access latency per DRAM burst 300system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s 301system.physmem.avgWrBW 3.48 # Average achieved write bandwidth in MiByte/s 302system.physmem.avgRdBWSys 4.48 # Average system read bandwidth in MiByte/s 303system.physmem.avgWrBWSys 3.92 # Average system write bandwidth in MiByte/s |
| 300system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 304system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 301system.physmem.busUtil 0.07 # Data bus utilization in percentage | 305system.physmem.busUtil 0.06 # Data bus utilization in percentage |
| 302system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 303system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 306system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 307system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| 304system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing 305system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing 306system.physmem.readRowHits 168404 # Number of row buffer hits during reads 307system.physmem.writeRowHits 114936 # Number of row buffer hits during writes 308system.physmem.readRowHitRate 83.21 # Row buffer hit rate for reads 309system.physmem.writeRowHitRate 65.63 # Row buffer hit rate for writes 310system.physmem.avgGap 7421638.38 # Average gap between requests 311system.physmem.pageHitRate 75.06 # Row buffer hit rate, read and write combined 312system.physmem_0.actEnergy 372813840 # Energy for activate commands per rank (pJ) 313system.physmem_0.preEnergy 203420250 # Energy for precharge commands per rank (pJ) 314system.physmem_0.readEnergy 818672400 # Energy for read commands per rank (pJ) 315system.physmem_0.writeEnergy 579545280 # Energy for write commands per rank (pJ) 316system.physmem_0.refreshEnergy 185876137200 # Energy for refresh commands per rank (pJ) 317system.physmem_0.actBackEnergy 83421293220 # Energy for active background per rank (pJ) 318system.physmem_0.preBackEnergy 1634324841000 # Energy for precharge background per rank (pJ) 319system.physmem_0.totalEnergy 1905596723190 # Total energy per rank (pJ) 320system.physmem_0.averagePower 669.608836 # Core power per rank (mW) 321system.physmem_0.memoryStateTime::IDLE 2718714861000 # Time in different power states 322system.physmem_0.memoryStateTime::REF 95028700000 # Time in different power states | 308system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing 309system.physmem.avgWrQLen 23.33 # Average write queue length when enqueuing 310system.physmem.readRowHits 166469 # Number of row buffer hits during reads 311system.physmem.writeRowHits 97300 # Number of row buffer hits during writes 312system.physmem.readRowHitRate 83.31 # Row buffer hit rate for reads 313system.physmem.writeRowHitRate 62.80 # Row buffer hit rate for writes 314system.physmem.avgGap 7519374.46 # Average gap between requests 315system.physmem.pageHitRate 74.35 # Row buffer hit rate, read and write combined 316system.physmem_0.actEnergy 351842400 # Energy for activate commands per rank (pJ) 317system.physmem_0.preEnergy 191977500 # Energy for precharge commands per rank (pJ) 318system.physmem_0.readEnergy 804437400 # Energy for read commands per rank (pJ) 319system.physmem_0.writeEnergy 508297680 # Energy for write commands per rank (pJ) 320system.physmem_0.refreshEnergy 185886816960 # Energy for refresh commands per rank (pJ) 321system.physmem_0.actBackEnergy 83070715860 # Energy for active background per rank (pJ) 322system.physmem_0.preBackEnergy 1634730471750 # Energy for precharge background per rank (pJ) 323system.physmem_0.totalEnergy 1905544559550 # Total energy per rank (pJ) 324system.physmem_0.averagePower 669.552036 # Core power per rank (mW) 325system.physmem_0.memoryStateTime::IDLE 2719396100671 # Time in different power states 326system.physmem_0.memoryStateTime::REF 95034160000 # Time in different power states |
| 323system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 327system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 324system.physmem_0.memoryStateTime::ACT 32092142750 # Time in different power states | 328system.physmem_0.memoryStateTime::ACT 31570722329 # Time in different power states |
| 325system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 329system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 326system.physmem_1.actEnergy 338877000 # Energy for activate commands per rank (pJ) 327system.physmem_1.preEnergy 184903125 # Energy for precharge commands per rank (pJ) 328system.physmem_1.readEnergy 759837000 # Energy for read commands per rank (pJ) 329system.physmem_1.writeEnergy 555141600 # Energy for write commands per rank (pJ) 330system.physmem_1.refreshEnergy 185876137200 # Energy for refresh commands per rank (pJ) 331system.physmem_1.actBackEnergy 82372109895 # Energy for active background per rank (pJ) 332system.physmem_1.preBackEnergy 1635245177250 # Energy for precharge background per rank (pJ) 333system.physmem_1.totalEnergy 1905332183070 # Total energy per rank (pJ) 334system.physmem_1.averagePower 669.515879 # Core power per rank (mW) 335system.physmem_1.memoryStateTime::IDLE 2720254769500 # Time in different power states 336system.physmem_1.memoryStateTime::REF 95028700000 # Time in different power states | 330system.physmem_1.actEnergy 335701800 # Energy for activate commands per rank (pJ) 331system.physmem_1.preEnergy 183170625 # Energy for precharge commands per rank (pJ) 332system.physmem_1.readEnergy 754049400 # Energy for read commands per rank (pJ) 333system.physmem_1.writeEnergy 495506160 # Energy for write commands per rank (pJ) 334system.physmem_1.refreshEnergy 185886816960 # Energy for refresh commands per rank (pJ) 335system.physmem_1.actBackEnergy 82302536835 # Energy for active background per rank (pJ) 336system.physmem_1.preBackEnergy 1635404313000 # Energy for precharge background per rank (pJ) 337system.physmem_1.totalEnergy 1905362094780 # Total energy per rank (pJ) 338system.physmem_1.averagePower 669.487923 # Core power per rank (mW) 339system.physmem_1.memoryStateTime::IDLE 2720522847414 # Time in different power states 340system.physmem_1.memoryStateTime::REF 95034160000 # Time in different power states |
| 337system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 341system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 338system.physmem_1.memoryStateTime::ACT 30559102000 # Time in different power states | 342system.physmem_1.memoryStateTime::ACT 30442207586 # Time in different power states |
| 339system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 340system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory 341system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory 342system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory 343system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory 344system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory 345system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory 346system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory --- 9 unchanged lines hidden (view full) --- 356system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) 357system.realview.nvmem.bw_total::total 427 # Total bandwidth to/from this memory (bytes/s) 358system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 359system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 360system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 361system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 362system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 363system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 343system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 344system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory 345system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory 346system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory 347system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory 348system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory 349system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory 350system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory --- 9 unchanged lines hidden (view full) --- 360system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) 361system.realview.nvmem.bw_total::total 427 # Total bandwidth to/from this memory (bytes/s) 362system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 363system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 364system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 365system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 366system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 367system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 364system.cpu0.branchPred.lookups 35059389 # Number of BP lookups 365system.cpu0.branchPred.condPredicted 17250705 # Number of conditional branches predicted 366system.cpu0.branchPred.condIncorrect 1579435 # Number of conditional branches incorrect 367system.cpu0.branchPred.BTBLookups 20094508 # Number of BTB lookups 368system.cpu0.branchPred.BTBHits 14609065 # Number of BTB hits | 368system.cpu0.branchPred.lookups 20635824 # Number of BP lookups 369system.cpu0.branchPred.condPredicted 13602989 # Number of conditional branches predicted 370system.cpu0.branchPred.condIncorrect 1045571 # Number of conditional branches incorrect 371system.cpu0.branchPred.BTBLookups 13187813 # Number of BTB lookups 372system.cpu0.branchPred.BTBHits 9323038 # Number of BTB hits |
| 369system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 373system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 370system.cpu0.branchPred.BTBHitPct 72.701780 # BTB Hit Percentage 371system.cpu0.branchPred.usedRAS 10810171 # Number of times the RAS was used to get a target. 372system.cpu0.branchPred.RASInCorrect 733013 # Number of incorrect RAS predictions. | 374system.cpu0.branchPred.BTBHitPct 70.694345 # BTB Hit Percentage 375system.cpu0.branchPred.usedRAS 3366354 # Number of times the RAS was used to get a target. 376system.cpu0.branchPred.RASInCorrect 208367 # Number of incorrect RAS predictions. |
| 373system.cpu_clk_domain.clock 500 # Clock period in ticks 374system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 375system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 376system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 377system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 378system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 379system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 380system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 395system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 396system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 397system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 398system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 399system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 400system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 401system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 402system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 377system.cpu_clk_domain.clock 500 # Clock period in ticks 378system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 379system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 380system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 381system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 382system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 383system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 384system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 399system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 400system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 401system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 402system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 403system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 404system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 405system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 406system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 403system.cpu0.dtb.walker.walks 67889 # Table walker walks requested 404system.cpu0.dtb.walker.walksShort 67889 # Table walker walks initiated with short descriptors 405system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44852 # Level at which table walker walks with short descriptors terminate 406system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23037 # Level at which table walker walks with short descriptors terminate 407system.cpu0.dtb.walker.walkWaitTime::samples 67889 # Table walker wait (enqueue to first request) latency 408system.cpu0.dtb.walker.walkWaitTime::0 67889 100.00% 100.00% # Table walker wait (enqueue to first request) latency 409system.cpu0.dtb.walker.walkWaitTime::total 67889 # Table walker wait (enqueue to first request) latency 410system.cpu0.dtb.walker.walkCompletionTime::samples 6673 # Table walker service (enqueue to completion) latency 411system.cpu0.dtb.walker.walkCompletionTime::mean 8598.195564 # Table walker service (enqueue to completion) latency 412system.cpu0.dtb.walker.walkCompletionTime::gmean 7320.525431 # Table walker service (enqueue to completion) latency 413system.cpu0.dtb.walker.walkCompletionTime::stdev 6106.619536 # Table walker service (enqueue to completion) latency 414system.cpu0.dtb.walker.walkCompletionTime::0-16383 6491 97.27% 97.27% # Table walker service (enqueue to completion) latency 415system.cpu0.dtb.walker.walkCompletionTime::16384-32767 168 2.52% 99.79% # Table walker service (enqueue to completion) latency 416system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.88% # Table walker service (enqueue to completion) latency 417system.cpu0.dtb.walker.walkCompletionTime::81920-98303 6 0.09% 99.97% # Table walker service (enqueue to completion) latency 418system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 419system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 420system.cpu0.dtb.walker.walkCompletionTime::total 6673 # Table walker service (enqueue to completion) latency 421system.cpu0.dtb.walker.walksPending::samples 287368000 # Table walker pending requests distribution 422system.cpu0.dtb.walker.walksPending::0 287368000 100.00% 100.00% # Table walker pending requests distribution 423system.cpu0.dtb.walker.walksPending::total 287368000 # Table walker pending requests distribution 424system.cpu0.dtb.walker.walkPageSizes::4K 5164 77.39% 77.39% # Table walker page sizes translated 425system.cpu0.dtb.walker.walkPageSizes::1M 1509 22.61% 100.00% # Table walker page sizes translated 426system.cpu0.dtb.walker.walkPageSizes::total 6673 # Table walker page sizes translated 427system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67889 # Table walker requests started/completed, data/inst | 407system.cpu0.dtb.walker.walks 68383 # Table walker walks requested 408system.cpu0.dtb.walker.walksShort 68383 # Table walker walks initiated with short descriptors 409system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 45560 # Level at which table walker walks with short descriptors terminate 410system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22823 # Level at which table walker walks with short descriptors terminate 411system.cpu0.dtb.walker.walkWaitTime::samples 68383 # Table walker wait (enqueue to first request) latency 412system.cpu0.dtb.walker.walkWaitTime::0 68383 100.00% 100.00% # Table walker wait (enqueue to first request) latency 413system.cpu0.dtb.walker.walkWaitTime::total 68383 # Table walker wait (enqueue to first request) latency 414system.cpu0.dtb.walker.walkCompletionTime::samples 6747 # Table walker service (enqueue to completion) latency 415system.cpu0.dtb.walker.walkCompletionTime::mean 9430.747147 # Table walker service (enqueue to completion) latency 416system.cpu0.dtb.walker.walkCompletionTime::gmean 8234.841596 # Table walker service (enqueue to completion) latency 417system.cpu0.dtb.walker.walkCompletionTime::stdev 6251.099816 # Table walker service (enqueue to completion) latency 418system.cpu0.dtb.walker.walkCompletionTime::0-16383 6572 97.41% 97.41% # Table walker service (enqueue to completion) latency 419system.cpu0.dtb.walker.walkCompletionTime::16384-32767 158 2.34% 99.75% # Table walker service (enqueue to completion) latency 420system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.84% # Table walker service (enqueue to completion) latency 421system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.10% 99.94% # Table walker service (enqueue to completion) latency 422system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.97% # Table walker service (enqueue to completion) latency 423system.cpu0.dtb.walker.walkCompletionTime::114688-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 424system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 425system.cpu0.dtb.walker.walkCompletionTime::total 6747 # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walksPending::samples 328505000 # Table walker pending requests distribution 427system.cpu0.dtb.walker.walksPending::0 328505000 100.00% 100.00% # Table walker pending requests distribution 428system.cpu0.dtb.walker.walksPending::total 328505000 # Table walker pending requests distribution 429system.cpu0.dtb.walker.walkPageSizes::4K 5180 76.77% 76.77% # Table walker page sizes translated 430system.cpu0.dtb.walker.walkPageSizes::1M 1567 23.23% 100.00% # Table walker page sizes translated 431system.cpu0.dtb.walker.walkPageSizes::total 6747 # Table walker page sizes translated 432system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 68383 # Table walker requests started/completed, data/inst |
| 428system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 433system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 429system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67889 # Table walker requests started/completed, data/inst 430system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6673 # Table walker requests started/completed, data/inst | 434system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 68383 # Table walker requests started/completed, data/inst 435system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6747 # Table walker requests started/completed, data/inst |
| 431system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 436system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 432system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6673 # Table walker requests started/completed, data/inst 433system.cpu0.dtb.walker.walkRequestOrigin::total 74562 # Table walker requests started/completed, data/inst | 437system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6747 # Table walker requests started/completed, data/inst 438system.cpu0.dtb.walker.walkRequestOrigin::total 75130 # Table walker requests started/completed, data/inst |
| 434system.cpu0.dtb.inst_hits 0 # ITB inst hits 435system.cpu0.dtb.inst_misses 0 # ITB inst misses | 439system.cpu0.dtb.inst_hits 0 # ITB inst hits 440system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 436system.cpu0.dtb.read_hits 23969568 # DTB read hits 437system.cpu0.dtb.read_misses 61820 # DTB read misses 438system.cpu0.dtb.write_hits 17946825 # DTB write hits 439system.cpu0.dtb.write_misses 6069 # DTB write misses | 441system.cpu0.dtb.read_hits 17310932 # DTB read hits 442system.cpu0.dtb.read_misses 62315 # DTB read misses 443system.cpu0.dtb.write_hits 14537397 # DTB write hits 444system.cpu0.dtb.write_misses 6068 # DTB write misses |
| 440system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 441system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 442system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 443system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 445system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 446system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 447system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 448system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 444system.cpu0.dtb.flush_entries 3496 # Number of entries that have been flushed from TLB 445system.cpu0.dtb.align_faults 1251 # Number of TLB faults due to alignment restrictions 446system.cpu0.dtb.prefetch_faults 2004 # Number of TLB faults due to prefetch | 449system.cpu0.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB 450system.cpu0.dtb.align_faults 1366 # Number of TLB faults due to alignment restrictions 451system.cpu0.dtb.prefetch_faults 1946 # Number of TLB faults due to prefetch |
| 447system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 452system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 448system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions 449system.cpu0.dtb.read_accesses 24031388 # DTB read accesses 450system.cpu0.dtb.write_accesses 17952894 # DTB write accesses | 453system.cpu0.dtb.perms_faults 545 # Number of TLB faults due to permissions restrictions 454system.cpu0.dtb.read_accesses 17373247 # DTB read accesses 455system.cpu0.dtb.write_accesses 14543465 # DTB write accesses |
| 451system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 456system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 452system.cpu0.dtb.hits 41916393 # DTB hits 453system.cpu0.dtb.misses 67889 # DTB misses 454system.cpu0.dtb.accesses 41984282 # DTB accesses | 457system.cpu0.dtb.hits 31848329 # DTB hits 458system.cpu0.dtb.misses 68383 # DTB misses 459system.cpu0.dtb.accesses 31916712 # DTB accesses |
| 455system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 456system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 457system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 458system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 459system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 460system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 461system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 462system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 476system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 477system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 478system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 479system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 480system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 481system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 482system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 483system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 460system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 461system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 462system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 463system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 464system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 465system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 466system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 467system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 481system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 482system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 483system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 484system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 485system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 486system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 487system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 488system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 484system.cpu0.itb.walker.walks 3825 # Table walker walks requested 485system.cpu0.itb.walker.walksShort 3825 # Table walker walks initiated with short descriptors 486system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate 487system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3518 # Level at which table walker walks with short descriptors terminate 488system.cpu0.itb.walker.walkWaitTime::samples 3825 # Table walker wait (enqueue to first request) latency 489system.cpu0.itb.walker.walkWaitTime::0 3825 100.00% 100.00% # Table walker wait (enqueue to first request) latency 490system.cpu0.itb.walker.walkWaitTime::total 3825 # Table walker wait (enqueue to first request) latency 491system.cpu0.itb.walker.walkCompletionTime::samples 2419 # Table walker service (enqueue to completion) latency 492system.cpu0.itb.walker.walkCompletionTime::mean 8874.535345 # Table walker service (enqueue to completion) latency 493system.cpu0.itb.walker.walkCompletionTime::gmean 7628.532351 # Table walker service (enqueue to completion) latency 494system.cpu0.itb.walker.walkCompletionTime::stdev 4888.994435 # Table walker service (enqueue to completion) latency 495system.cpu0.itb.walker.walkCompletionTime::0-8191 1491 61.64% 61.64% # Table walker service (enqueue to completion) latency 496system.cpu0.itb.walker.walkCompletionTime::8192-16383 888 36.71% 98.35% # Table walker service (enqueue to completion) latency 497system.cpu0.itb.walker.walkCompletionTime::16384-24575 4 0.17% 98.51% # Table walker service (enqueue to completion) latency 498system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 99.96% # Table walker service (enqueue to completion) latency 499system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 500system.cpu0.itb.walker.walkCompletionTime::total 2419 # Table walker service (enqueue to completion) latency 501system.cpu0.itb.walker.walksPending::samples 286941000 # Table walker pending requests distribution 502system.cpu0.itb.walker.walksPending::0 286941000 100.00% 100.00% # Table walker pending requests distribution 503system.cpu0.itb.walker.walksPending::total 286941000 # Table walker pending requests distribution 504system.cpu0.itb.walker.walkPageSizes::4K 2119 87.60% 87.60% # Table walker page sizes translated 505system.cpu0.itb.walker.walkPageSizes::1M 300 12.40% 100.00% # Table walker page sizes translated 506system.cpu0.itb.walker.walkPageSizes::total 2419 # Table walker page sizes translated | 489system.cpu0.itb.walker.walks 3838 # Table walker walks requested 490system.cpu0.itb.walker.walksShort 3838 # Table walker walks initiated with short descriptors 491system.cpu0.itb.walker.walksShortTerminationLevel::Level1 306 # Level at which table walker walks with short descriptors terminate 492system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3532 # Level at which table walker walks with short descriptors terminate 493system.cpu0.itb.walker.walkWaitTime::samples 3838 # Table walker wait (enqueue to first request) latency 494system.cpu0.itb.walker.walkWaitTime::0 3838 100.00% 100.00% # Table walker wait (enqueue to first request) latency 495system.cpu0.itb.walker.walkWaitTime::total 3838 # Table walker wait (enqueue to first request) latency 496system.cpu0.itb.walker.walkCompletionTime::samples 2413 # Table walker service (enqueue to completion) latency 497system.cpu0.itb.walker.walkCompletionTime::mean 9817.861169 # Table walker service (enqueue to completion) latency 498system.cpu0.itb.walker.walkCompletionTime::gmean 8667.312532 # Table walker service (enqueue to completion) latency 499system.cpu0.itb.walker.walkCompletionTime::stdev 5173.169908 # Table walker service (enqueue to completion) latency 500system.cpu0.itb.walker.walkCompletionTime::0-8191 854 35.39% 35.39% # Table walker service (enqueue to completion) latency 501system.cpu0.itb.walker.walkCompletionTime::8192-16383 1509 62.54% 97.93% # Table walker service (enqueue to completion) latency 502system.cpu0.itb.walker.walkCompletionTime::16384-24575 3 0.12% 98.05% # Table walker service (enqueue to completion) latency 503system.cpu0.itb.walker.walkCompletionTime::24576-32767 46 1.91% 99.96% # Table walker service (enqueue to completion) latency 504system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 505system.cpu0.itb.walker.walkCompletionTime::total 2413 # Table walker service (enqueue to completion) latency 506system.cpu0.itb.walker.walksPending::samples 328041000 # Table walker pending requests distribution 507system.cpu0.itb.walker.walksPending::0 328041000 100.00% 100.00% # Table walker pending requests distribution 508system.cpu0.itb.walker.walksPending::total 328041000 # Table walker pending requests distribution 509system.cpu0.itb.walker.walkPageSizes::4K 2114 87.61% 87.61% # Table walker page sizes translated 510system.cpu0.itb.walker.walkPageSizes::1M 299 12.39% 100.00% # Table walker page sizes translated 511system.cpu0.itb.walker.walkPageSizes::total 2413 # Table walker page sizes translated |
| 507system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 512system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 508system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3825 # Table walker requests started/completed, data/inst 509system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3825 # Table walker requests started/completed, data/inst | 513system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3838 # Table walker requests started/completed, data/inst 514system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3838 # Table walker requests started/completed, data/inst |
| 510system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 515system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 511system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2419 # Table walker requests started/completed, data/inst 512system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2419 # Table walker requests started/completed, data/inst 513system.cpu0.itb.walker.walkRequestOrigin::total 6244 # Table walker requests started/completed, data/inst 514system.cpu0.itb.inst_hits 70462798 # ITB inst hits 515system.cpu0.itb.inst_misses 3825 # ITB inst misses | 516system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2413 # Table walker requests started/completed, data/inst 517system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2413 # Table walker requests started/completed, data/inst 518system.cpu0.itb.walker.walkRequestOrigin::total 6251 # Table walker requests started/completed, data/inst 519system.cpu0.itb.inst_hits 38726658 # ITB inst hits 520system.cpu0.itb.inst_misses 3838 # ITB inst misses |
| 516system.cpu0.itb.read_hits 0 # DTB read hits 517system.cpu0.itb.read_misses 0 # DTB read misses 518system.cpu0.itb.write_hits 0 # DTB write hits 519system.cpu0.itb.write_misses 0 # DTB write misses 520system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 521system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 522system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 523system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 521system.cpu0.itb.read_hits 0 # DTB read hits 522system.cpu0.itb.read_misses 0 # DTB read misses 523system.cpu0.itb.write_hits 0 # DTB write hits 524system.cpu0.itb.write_misses 0 # DTB write misses 525system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 526system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 527system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 528system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 524system.cpu0.itb.flush_entries 2222 # Number of entries that have been flushed from TLB | 529system.cpu0.itb.flush_entries 2219 # Number of entries that have been flushed from TLB |
| 525system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 526system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 527system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 530system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 531system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 532system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 528system.cpu0.itb.perms_faults 7291 # Number of TLB faults due to permissions restrictions | 533system.cpu0.itb.perms_faults 7377 # Number of TLB faults due to permissions restrictions |
| 529system.cpu0.itb.read_accesses 0 # DTB read accesses 530system.cpu0.itb.write_accesses 0 # DTB write accesses | 534system.cpu0.itb.read_accesses 0 # DTB read accesses 535system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 531system.cpu0.itb.inst_accesses 70466623 # ITB inst accesses 532system.cpu0.itb.hits 70462798 # DTB hits 533system.cpu0.itb.misses 3825 # DTB misses 534system.cpu0.itb.accesses 70466623 # DTB accesses 535system.cpu0.numCycles 234985394 # number of cpu cycles simulated | 536system.cpu0.itb.inst_accesses 38730496 # ITB inst accesses 537system.cpu0.itb.hits 38726658 # DTB hits 538system.cpu0.itb.misses 3838 # DTB misses 539system.cpu0.itb.accesses 38730496 # DTB accesses 540system.cpu0.numCycles 164623207 # number of cpu cycles simulated |
| 536system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 537system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 541system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 542system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 538system.cpu0.committedInsts 109265327 # Number of instructions committed 539system.cpu0.committedOps 132114239 # Number of ops (including micro ops) committed 540system.cpu0.discardedOps 8364757 # Number of ops (including micro ops) which were discarded before commit 541system.cpu0.numFetchSuspends 1821 # Number of times Execute suspended instruction fetching 542system.cpu0.quiesceCycles 5456715361 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 543system.cpu0.cpi 2.150594 # CPI: cycles per instruction 544system.cpu0.ipc 0.464988 # IPC: instructions per cycle | 543system.cpu0.committedInsts 79533802 # Number of instructions committed 544system.cpu0.committedOps 95718607 # Number of ops (including micro ops) committed 545system.cpu0.discardedOps 5045973 # Number of ops (including micro ops) which were discarded before commit 546system.cpu0.numFetchSuspends 1856 # Number of times Execute suspended instruction fetching 547system.cpu0.quiesceCycles 5527394503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 548system.cpu0.cpi 2.069852 # CPI: cycles per instruction 549system.cpu0.ipc 0.483126 # IPC: instructions per cycle |
| 545system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 550system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 546system.cpu0.kern.inst.quiesce 1824 # number of quiesce instructions executed 547system.cpu0.tickCycles 195318282 # Number of cycles that the object actually ticked 548system.cpu0.idleCycles 39667112 # Total number of cycles that the object has spent stopped 549system.cpu0.dcache.tags.replacements 718541 # number of replacements 550system.cpu0.dcache.tags.tagsinuse 494.305697 # Cycle average of tags in use 551system.cpu0.dcache.tags.total_refs 40476936 # Total number of references to valid blocks. 552system.cpu0.dcache.tags.sampled_refs 719053 # Sample count of references to valid blocks. 553system.cpu0.dcache.tags.avg_refs 56.292006 # Average number of references to valid blocks. 554system.cpu0.dcache.tags.warmup_cycle 306903000 # Cycle when the warmup percentage was hit. 555system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.305697 # Average occupied blocks per requestor 556system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965441 # Average percentage of cache occupancy 557system.cpu0.dcache.tags.occ_percent::total 0.965441 # Average percentage of cache occupancy | 551system.cpu0.kern.inst.quiesce 1858 # number of quiesce instructions executed 552system.cpu0.tickCycles 128554371 # Number of cycles that the object actually ticked 553system.cpu0.idleCycles 36068836 # Total number of cycles that the object has spent stopped 554system.cpu0.dcache.tags.replacements 714653 # number of replacements 555system.cpu0.dcache.tags.tagsinuse 500.517650 # Cycle average of tags in use 556system.cpu0.dcache.tags.total_refs 30439123 # Total number of references to valid blocks. 557system.cpu0.dcache.tags.sampled_refs 715165 # Sample count of references to valid blocks. 558system.cpu0.dcache.tags.avg_refs 42.562378 # Average number of references to valid blocks. 559system.cpu0.dcache.tags.warmup_cycle 348749500 # Cycle when the warmup percentage was hit. 560system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.517650 # Average occupied blocks per requestor 561system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977574 # Average percentage of cache occupancy 562system.cpu0.dcache.tags.occ_percent::total 0.977574 # Average percentage of cache occupancy |
| 558system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 563system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 559system.cpu0.dcache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id 560system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id 561system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id | 564system.cpu0.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 565system.cpu0.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id 566system.cpu0.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id |
| 562system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 567system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 563system.cpu0.dcache.tags.tag_accesses 83802985 # Number of tag accesses 564system.cpu0.dcache.tags.data_accesses 83802985 # Number of data accesses 565system.cpu0.dcache.ReadReq_hits::cpu0.data 22808347 # number of ReadReq hits 566system.cpu0.dcache.ReadReq_hits::total 22808347 # number of ReadReq hits 567system.cpu0.dcache.WriteReq_hits::cpu0.data 16863099 # number of WriteReq hits 568system.cpu0.dcache.WriteReq_hits::total 16863099 # number of WriteReq hits 569system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 381264 # number of LoadLockedReq hits 570system.cpu0.dcache.LoadLockedReq_hits::total 381264 # number of LoadLockedReq hits 571system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362825 # number of StoreCondReq hits 572system.cpu0.dcache.StoreCondReq_hits::total 362825 # number of StoreCondReq hits 573system.cpu0.dcache.demand_hits::cpu0.data 39671446 # number of demand (read+write) hits 574system.cpu0.dcache.demand_hits::total 39671446 # number of demand (read+write) hits 575system.cpu0.dcache.overall_hits::cpu0.data 39671446 # number of overall hits 576system.cpu0.dcache.overall_hits::total 39671446 # number of overall hits 577system.cpu0.dcache.ReadReq_misses::cpu0.data 540080 # number of ReadReq misses 578system.cpu0.dcache.ReadReq_misses::total 540080 # number of ReadReq misses 579system.cpu0.dcache.WriteReq_misses::cpu0.data 532227 # number of WriteReq misses 580system.cpu0.dcache.WriteReq_misses::total 532227 # number of WriteReq misses 581system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6489 # number of LoadLockedReq misses 582system.cpu0.dcache.LoadLockedReq_misses::total 6489 # number of LoadLockedReq misses 583system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19898 # number of StoreCondReq misses 584system.cpu0.dcache.StoreCondReq_misses::total 19898 # number of StoreCondReq misses 585system.cpu0.dcache.demand_misses::cpu0.data 1072307 # number of demand (read+write) misses 586system.cpu0.dcache.demand_misses::total 1072307 # number of demand (read+write) misses 587system.cpu0.dcache.overall_misses::cpu0.data 1072307 # number of overall misses 588system.cpu0.dcache.overall_misses::total 1072307 # number of overall misses 589system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6648434719 # number of ReadReq miss cycles 590system.cpu0.dcache.ReadReq_miss_latency::total 6648434719 # number of ReadReq miss cycles 591system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8319872197 # number of WriteReq miss cycles 592system.cpu0.dcache.WriteReq_miss_latency::total 8319872197 # number of WriteReq miss cycles 593system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104923750 # number of LoadLockedReq miss cycles 594system.cpu0.dcache.LoadLockedReq_miss_latency::total 104923750 # number of LoadLockedReq miss cycles 595system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 438142885 # number of StoreCondReq miss cycles 596system.cpu0.dcache.StoreCondReq_miss_latency::total 438142885 # number of StoreCondReq miss cycles 597system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 309000 # number of StoreCondFailReq miss cycles 598system.cpu0.dcache.StoreCondFailReq_miss_latency::total 309000 # number of StoreCondFailReq miss cycles 599system.cpu0.dcache.demand_miss_latency::cpu0.data 14968306916 # number of demand (read+write) miss cycles 600system.cpu0.dcache.demand_miss_latency::total 14968306916 # number of demand (read+write) miss cycles 601system.cpu0.dcache.overall_miss_latency::cpu0.data 14968306916 # number of overall miss cycles 602system.cpu0.dcache.overall_miss_latency::total 14968306916 # number of overall miss cycles 603system.cpu0.dcache.ReadReq_accesses::cpu0.data 23348427 # number of ReadReq accesses(hits+misses) 604system.cpu0.dcache.ReadReq_accesses::total 23348427 # number of ReadReq accesses(hits+misses) 605system.cpu0.dcache.WriteReq_accesses::cpu0.data 17395326 # number of WriteReq accesses(hits+misses) 606system.cpu0.dcache.WriteReq_accesses::total 17395326 # number of WriteReq accesses(hits+misses) 607system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387753 # number of LoadLockedReq accesses(hits+misses) 608system.cpu0.dcache.LoadLockedReq_accesses::total 387753 # number of LoadLockedReq accesses(hits+misses) 609system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382723 # number of StoreCondReq accesses(hits+misses) 610system.cpu0.dcache.StoreCondReq_accesses::total 382723 # number of StoreCondReq accesses(hits+misses) 611system.cpu0.dcache.demand_accesses::cpu0.data 40743753 # number of demand (read+write) accesses 612system.cpu0.dcache.demand_accesses::total 40743753 # number of demand (read+write) accesses 613system.cpu0.dcache.overall_accesses::cpu0.data 40743753 # number of overall (read+write) accesses 614system.cpu0.dcache.overall_accesses::total 40743753 # number of overall (read+write) accesses 615system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023131 # miss rate for ReadReq accesses 616system.cpu0.dcache.ReadReq_miss_rate::total 0.023131 # miss rate for ReadReq accesses 617system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030596 # miss rate for WriteReq accesses 618system.cpu0.dcache.WriteReq_miss_rate::total 0.030596 # miss rate for WriteReq accesses 619system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016735 # miss rate for LoadLockedReq accesses 620system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016735 # miss rate for LoadLockedReq accesses 621system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051991 # miss rate for StoreCondReq accesses 622system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051991 # miss rate for StoreCondReq accesses 623system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026318 # miss rate for demand accesses 624system.cpu0.dcache.demand_miss_rate::total 0.026318 # miss rate for demand accesses 625system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026318 # miss rate for overall accesses 626system.cpu0.dcache.overall_miss_rate::total 0.026318 # miss rate for overall accesses 627system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12310.092429 # average ReadReq miss latency 628system.cpu0.dcache.ReadReq_avg_miss_latency::total 12310.092429 # average ReadReq miss latency 629system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15632.187388 # average WriteReq miss latency 630system.cpu0.dcache.WriteReq_avg_miss_latency::total 15632.187388 # average WriteReq miss latency 631system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16169.479119 # average LoadLockedReq miss latency 632system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16169.479119 # average LoadLockedReq miss latency 633system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22019.443411 # average StoreCondReq miss latency 634system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22019.443411 # average StoreCondReq miss latency | 568system.cpu0.dcache.tags.tag_accesses 63710880 # Number of tag accesses 569system.cpu0.dcache.tags.data_accesses 63710880 # Number of data accesses 570system.cpu0.dcache.ReadReq_hits::cpu0.data 16167111 # number of ReadReq hits 571system.cpu0.dcache.ReadReq_hits::total 16167111 # number of ReadReq hits 572system.cpu0.dcache.WriteReq_hits::cpu0.data 13468154 # number of WriteReq hits 573system.cpu0.dcache.WriteReq_hits::total 13468154 # number of WriteReq hits 574system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 380067 # number of LoadLockedReq hits 575system.cpu0.dcache.LoadLockedReq_hits::total 380067 # number of LoadLockedReq hits 576system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361342 # number of StoreCondReq hits 577system.cpu0.dcache.StoreCondReq_hits::total 361342 # number of StoreCondReq hits 578system.cpu0.dcache.demand_hits::cpu0.data 29635265 # number of demand (read+write) hits 579system.cpu0.dcache.demand_hits::total 29635265 # number of demand (read+write) hits 580system.cpu0.dcache.overall_hits::cpu0.data 29635265 # number of overall hits 581system.cpu0.dcache.overall_hits::total 29635265 # number of overall hits 582system.cpu0.dcache.ReadReq_misses::cpu0.data 537159 # number of ReadReq misses 583system.cpu0.dcache.ReadReq_misses::total 537159 # number of ReadReq misses 584system.cpu0.dcache.WriteReq_misses::cpu0.data 529716 # number of WriteReq misses 585system.cpu0.dcache.WriteReq_misses::total 529716 # number of WriteReq misses 586system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6447 # number of LoadLockedReq misses 587system.cpu0.dcache.LoadLockedReq_misses::total 6447 # number of LoadLockedReq misses 588system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20264 # number of StoreCondReq misses 589system.cpu0.dcache.StoreCondReq_misses::total 20264 # number of StoreCondReq misses 590system.cpu0.dcache.demand_misses::cpu0.data 1066875 # number of demand (read+write) misses 591system.cpu0.dcache.demand_misses::total 1066875 # number of demand (read+write) misses 592system.cpu0.dcache.overall_misses::cpu0.data 1066875 # number of overall misses 593system.cpu0.dcache.overall_misses::total 1066875 # number of overall misses 594system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6690812322 # number of ReadReq miss cycles 595system.cpu0.dcache.ReadReq_miss_latency::total 6690812322 # number of ReadReq miss cycles 596system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8678584493 # number of WriteReq miss cycles 597system.cpu0.dcache.WriteReq_miss_latency::total 8678584493 # number of WriteReq miss cycles 598system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104630740 # number of LoadLockedReq miss cycles 599system.cpu0.dcache.LoadLockedReq_miss_latency::total 104630740 # number of LoadLockedReq miss cycles 600system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 454305285 # number of StoreCondReq miss cycles 601system.cpu0.dcache.StoreCondReq_miss_latency::total 454305285 # number of StoreCondReq miss cycles 602system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 153000 # number of StoreCondFailReq miss cycles 603system.cpu0.dcache.StoreCondFailReq_miss_latency::total 153000 # number of StoreCondFailReq miss cycles 604system.cpu0.dcache.demand_miss_latency::cpu0.data 15369396815 # number of demand (read+write) miss cycles 605system.cpu0.dcache.demand_miss_latency::total 15369396815 # number of demand (read+write) miss cycles 606system.cpu0.dcache.overall_miss_latency::cpu0.data 15369396815 # number of overall miss cycles 607system.cpu0.dcache.overall_miss_latency::total 15369396815 # number of overall miss cycles 608system.cpu0.dcache.ReadReq_accesses::cpu0.data 16704270 # number of ReadReq accesses(hits+misses) 609system.cpu0.dcache.ReadReq_accesses::total 16704270 # number of ReadReq accesses(hits+misses) 610system.cpu0.dcache.WriteReq_accesses::cpu0.data 13997870 # number of WriteReq accesses(hits+misses) 611system.cpu0.dcache.WriteReq_accesses::total 13997870 # number of WriteReq accesses(hits+misses) 612system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386514 # number of LoadLockedReq accesses(hits+misses) 613system.cpu0.dcache.LoadLockedReq_accesses::total 386514 # number of LoadLockedReq accesses(hits+misses) 614system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381606 # number of StoreCondReq accesses(hits+misses) 615system.cpu0.dcache.StoreCondReq_accesses::total 381606 # number of StoreCondReq accesses(hits+misses) 616system.cpu0.dcache.demand_accesses::cpu0.data 30702140 # number of demand (read+write) accesses 617system.cpu0.dcache.demand_accesses::total 30702140 # number of demand (read+write) accesses 618system.cpu0.dcache.overall_accesses::cpu0.data 30702140 # number of overall (read+write) accesses 619system.cpu0.dcache.overall_accesses::total 30702140 # number of overall (read+write) accesses 620system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032157 # miss rate for ReadReq accesses 621system.cpu0.dcache.ReadReq_miss_rate::total 0.032157 # miss rate for ReadReq accesses 622system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.037843 # miss rate for WriteReq accesses 623system.cpu0.dcache.WriteReq_miss_rate::total 0.037843 # miss rate for WriteReq accesses 624system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016680 # miss rate for LoadLockedReq accesses 625system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016680 # miss rate for LoadLockedReq accesses 626system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053102 # miss rate for StoreCondReq accesses 627system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053102 # miss rate for StoreCondReq accesses 628system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034749 # miss rate for demand accesses 629system.cpu0.dcache.demand_miss_rate::total 0.034749 # miss rate for demand accesses 630system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034749 # miss rate for overall accesses 631system.cpu0.dcache.overall_miss_rate::total 0.034749 # miss rate for overall accesses 632system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12455.925195 # average ReadReq miss latency 633system.cpu0.dcache.ReadReq_avg_miss_latency::total 12455.925195 # average ReadReq miss latency 634system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16383.466788 # average WriteReq miss latency 635system.cpu0.dcache.WriteReq_avg_miss_latency::total 16383.466788 # average WriteReq miss latency 636system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16229.368699 # average LoadLockedReq miss latency 637system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16229.368699 # average LoadLockedReq miss latency 638system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22419.329106 # average StoreCondReq miss latency 639system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22419.329106 # average StoreCondReq miss latency |
| 635system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 636system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 640system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 641system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 637system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13958.975290 # average overall miss latency 638system.cpu0.dcache.demand_avg_miss_latency::total 13958.975290 # average overall miss latency 639system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13958.975290 # average overall miss latency 640system.cpu0.dcache.overall_avg_miss_latency::total 13958.975290 # average overall miss latency | 642system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14405.995843 # average overall miss latency 643system.cpu0.dcache.demand_avg_miss_latency::total 14405.995843 # average overall miss latency 644system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14405.995843 # average overall miss latency 645system.cpu0.dcache.overall_avg_miss_latency::total 14405.995843 # average overall miss latency |
| 641system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 642system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 643system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 644system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 645system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 646system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 647system.cpu0.dcache.fast_writes 0 # number of fast writes performed 648system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 646system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 647system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 648system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 649system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 650system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 651system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 652system.cpu0.dcache.fast_writes 0 # number of fast writes performed 653system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 649system.cpu0.dcache.writebacks::writebacks 523102 # number of writebacks 650system.cpu0.dcache.writebacks::total 523102 # number of writebacks 651system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 42658 # number of ReadReq MSHR hits 652system.cpu0.dcache.ReadReq_mshr_hits::total 42658 # number of ReadReq MSHR hits 653system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 230433 # number of WriteReq MSHR hits 654system.cpu0.dcache.WriteReq_mshr_hits::total 230433 # number of WriteReq MSHR hits 655system.cpu0.dcache.demand_mshr_hits::cpu0.data 273091 # number of demand (read+write) MSHR hits 656system.cpu0.dcache.demand_mshr_hits::total 273091 # number of demand (read+write) MSHR hits 657system.cpu0.dcache.overall_mshr_hits::cpu0.data 273091 # number of overall MSHR hits 658system.cpu0.dcache.overall_mshr_hits::total 273091 # number of overall MSHR hits 659system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 497422 # number of ReadReq MSHR misses 660system.cpu0.dcache.ReadReq_mshr_misses::total 497422 # number of ReadReq MSHR misses 661system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 301794 # number of WriteReq MSHR misses 662system.cpu0.dcache.WriteReq_mshr_misses::total 301794 # number of WriteReq MSHR misses 663system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6489 # number of LoadLockedReq MSHR misses 664system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6489 # number of LoadLockedReq MSHR misses 665system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19898 # number of StoreCondReq MSHR misses 666system.cpu0.dcache.StoreCondReq_mshr_misses::total 19898 # number of StoreCondReq MSHR misses 667system.cpu0.dcache.demand_mshr_misses::cpu0.data 799216 # number of demand (read+write) MSHR misses 668system.cpu0.dcache.demand_mshr_misses::total 799216 # number of demand (read+write) MSHR misses 669system.cpu0.dcache.overall_mshr_misses::cpu0.data 799216 # number of overall MSHR misses 670system.cpu0.dcache.overall_mshr_misses::total 799216 # number of overall MSHR misses 671system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5149793898 # number of ReadReq MSHR miss cycles 672system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5149793898 # number of ReadReq MSHR miss cycles 673system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4423706193 # number of WriteReq MSHR miss cycles 674system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4423706193 # number of WriteReq MSHR miss cycles 675system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 91926250 # number of LoadLockedReq MSHR miss cycles 676system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 91926250 # number of LoadLockedReq MSHR miss cycles 677system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 397751115 # number of StoreCondReq MSHR miss cycles 678system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 397751115 # number of StoreCondReq MSHR miss cycles 679system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 291000 # number of StoreCondFailReq MSHR miss cycles 680system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 291000 # number of StoreCondFailReq MSHR miss cycles 681system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9573500091 # number of demand (read+write) MSHR miss cycles 682system.cpu0.dcache.demand_mshr_miss_latency::total 9573500091 # number of demand (read+write) MSHR miss cycles 683system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9573500091 # number of overall MSHR miss cycles 684system.cpu0.dcache.overall_mshr_miss_latency::total 9573500091 # number of overall MSHR miss cycles 685system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6190990749 # number of ReadReq MSHR uncacheable cycles 686system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6190990749 # number of ReadReq MSHR uncacheable cycles 687system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4804555500 # number of WriteReq MSHR uncacheable cycles 688system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4804555500 # number of WriteReq MSHR uncacheable cycles 689system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10995546249 # number of overall MSHR uncacheable cycles 690system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10995546249 # number of overall MSHR uncacheable cycles 691system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.021304 # mshr miss rate for ReadReq accesses 692system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021304 # mshr miss rate for ReadReq accesses 693system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017349 # mshr miss rate for WriteReq accesses 694system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017349 # mshr miss rate for WriteReq accesses 695system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016735 # mshr miss rate for LoadLockedReq accesses 696system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016735 # mshr miss rate for LoadLockedReq accesses 697system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051991 # mshr miss rate for StoreCondReq accesses 698system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051991 # mshr miss rate for StoreCondReq accesses 699system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.019616 # mshr miss rate for demand accesses 700system.cpu0.dcache.demand_mshr_miss_rate::total 0.019616 # mshr miss rate for demand accesses 701system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019616 # mshr miss rate for overall accesses 702system.cpu0.dcache.overall_mshr_miss_rate::total 0.019616 # mshr miss rate for overall accesses 703system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10352.967697 # average ReadReq mshr miss latency 704system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10352.967697 # average ReadReq mshr miss latency 705system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14658.032277 # average WriteReq mshr miss latency 706system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14658.032277 # average WriteReq mshr miss latency 707system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14166.474033 # average LoadLockedReq mshr miss latency 708system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14166.474033 # average LoadLockedReq mshr miss latency 709system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19989.502211 # average StoreCondReq mshr miss latency 710system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19989.502211 # average StoreCondReq mshr miss latency | 654system.cpu0.dcache.writebacks::writebacks 516062 # number of writebacks 655system.cpu0.dcache.writebacks::total 516062 # number of writebacks 656system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 42087 # number of ReadReq MSHR hits 657system.cpu0.dcache.ReadReq_mshr_hits::total 42087 # number of ReadReq MSHR hits 658system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 229086 # number of WriteReq MSHR hits 659system.cpu0.dcache.WriteReq_mshr_hits::total 229086 # number of WriteReq MSHR hits 660system.cpu0.dcache.demand_mshr_hits::cpu0.data 271173 # number of demand (read+write) MSHR hits 661system.cpu0.dcache.demand_mshr_hits::total 271173 # number of demand (read+write) MSHR hits 662system.cpu0.dcache.overall_mshr_hits::cpu0.data 271173 # number of overall MSHR hits 663system.cpu0.dcache.overall_mshr_hits::total 271173 # number of overall MSHR hits 664system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 495072 # number of ReadReq MSHR misses 665system.cpu0.dcache.ReadReq_mshr_misses::total 495072 # number of ReadReq MSHR misses 666system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 300630 # number of WriteReq MSHR misses 667system.cpu0.dcache.WriteReq_mshr_misses::total 300630 # number of WriteReq MSHR misses 668system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6447 # number of LoadLockedReq MSHR misses 669system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6447 # number of LoadLockedReq MSHR misses 670system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20264 # number of StoreCondReq MSHR misses 671system.cpu0.dcache.StoreCondReq_mshr_misses::total 20264 # number of StoreCondReq MSHR misses 672system.cpu0.dcache.demand_mshr_misses::cpu0.data 795702 # number of demand (read+write) MSHR misses 673system.cpu0.dcache.demand_mshr_misses::total 795702 # number of demand (read+write) MSHR misses 674system.cpu0.dcache.overall_mshr_misses::cpu0.data 795702 # number of overall MSHR misses 675system.cpu0.dcache.overall_mshr_misses::total 795702 # number of overall MSHR misses 676system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5420342985 # number of ReadReq MSHR miss cycles 677system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5420342985 # number of ReadReq MSHR miss cycles 678system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4742244244 # number of WriteReq MSHR miss cycles 679system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4742244244 # number of WriteReq MSHR miss cycles 680system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94933760 # number of LoadLockedReq MSHR miss cycles 681system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94933760 # number of LoadLockedReq MSHR miss cycles 682system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 423201715 # number of StoreCondReq MSHR miss cycles 683system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 423201715 # number of StoreCondReq MSHR miss cycles 684system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 147000 # number of StoreCondFailReq MSHR miss cycles 685system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 147000 # number of StoreCondFailReq MSHR miss cycles 686system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10162587229 # number of demand (read+write) MSHR miss cycles 687system.cpu0.dcache.demand_mshr_miss_latency::total 10162587229 # number of demand (read+write) MSHR miss cycles 688system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10162587229 # number of overall MSHR miss cycles 689system.cpu0.dcache.overall_mshr_miss_latency::total 10162587229 # number of overall MSHR miss cycles 690system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4276747000 # number of ReadReq MSHR uncacheable cycles 691system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4276747000 # number of ReadReq MSHR uncacheable cycles 692system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3261903001 # number of WriteReq MSHR uncacheable cycles 693system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3261903001 # number of WriteReq MSHR uncacheable cycles 694system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7538650001 # number of overall MSHR uncacheable cycles 695system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7538650001 # number of overall MSHR uncacheable cycles 696system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029637 # mshr miss rate for ReadReq accesses 697system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029637 # mshr miss rate for ReadReq accesses 698system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.021477 # mshr miss rate for WriteReq accesses 699system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021477 # mshr miss rate for WriteReq accesses 700system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016680 # mshr miss rate for LoadLockedReq accesses 701system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016680 # mshr miss rate for LoadLockedReq accesses 702system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053102 # mshr miss rate for StoreCondReq accesses 703system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053102 # mshr miss rate for StoreCondReq accesses 704system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025917 # mshr miss rate for demand accesses 705system.cpu0.dcache.demand_mshr_miss_rate::total 0.025917 # mshr miss rate for demand accesses 706system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025917 # mshr miss rate for overall accesses 707system.cpu0.dcache.overall_mshr_miss_rate::total 0.025917 # mshr miss rate for overall accesses 708system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10948.595326 # average ReadReq mshr miss latency 709system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10948.595326 # average ReadReq mshr miss latency 710system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15774.354669 # average WriteReq mshr miss latency 711system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15774.354669 # average WriteReq mshr miss latency 712system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14725.261362 # average LoadLockedReq mshr miss latency 713system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14725.261362 # average LoadLockedReq mshr miss latency 714system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20884.411518 # average StoreCondReq mshr miss latency 715system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20884.411518 # average StoreCondReq mshr miss latency |
| 711system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 712system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 716system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 717system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 713system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11978.614156 # average overall mshr miss latency 714system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11978.614156 # average overall mshr miss latency 715system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11978.614156 # average overall mshr miss latency 716system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11978.614156 # average overall mshr miss latency | 718system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12771.850805 # average overall mshr miss latency 719system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12771.850805 # average overall mshr miss latency 720system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12771.850805 # average overall mshr miss latency 721system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12771.850805 # average overall mshr miss latency |
| 717system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 718system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 719system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 720system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 721system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 722system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 723system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 722system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 723system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 724system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 725system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 726system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 727system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 728system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 724system.cpu0.icache.tags.replacements 1982441 # number of replacements 725system.cpu0.icache.tags.tagsinuse 511.792915 # Cycle average of tags in use 726system.cpu0.icache.tags.total_refs 68472197 # Total number of references to valid blocks. 727system.cpu0.icache.tags.sampled_refs 1982953 # Sample count of references to valid blocks. 728system.cpu0.icache.tags.avg_refs 34.530419 # Average number of references to valid blocks. 729system.cpu0.icache.tags.warmup_cycle 6378447750 # Cycle when the warmup percentage was hit. 730system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.792915 # Average occupied blocks per requestor 731system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999596 # Average percentage of cache occupancy 732system.cpu0.icache.tags.occ_percent::total 0.999596 # Average percentage of cache occupancy | 729system.cpu0.icache.tags.replacements 1970130 # number of replacements 730system.cpu0.icache.tags.tagsinuse 511.783768 # Cycle average of tags in use 731system.cpu0.icache.tags.total_refs 36748265 # Total number of references to valid blocks. 732system.cpu0.icache.tags.sampled_refs 1970642 # Sample count of references to valid blocks. 733system.cpu0.icache.tags.avg_refs 18.647865 # Average number of references to valid blocks. 734system.cpu0.icache.tags.warmup_cycle 6452193250 # Cycle when the warmup percentage was hit. 735system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.783768 # Average occupied blocks per requestor 736system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999578 # Average percentage of cache occupancy 737system.cpu0.icache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy |
| 733system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 738system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 734system.cpu0.icache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id 735system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id 736system.cpu0.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id | 739system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id 740system.cpu0.icache.tags.age_task_id_blocks_1024::1 230 # Occupied blocks per task id 741system.cpu0.icache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id |
| 737system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 742system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 738system.cpu0.icache.tags.tag_accesses 142893294 # Number of tag accesses 739system.cpu0.icache.tags.data_accesses 142893294 # Number of data accesses 740system.cpu0.icache.ReadReq_hits::cpu0.inst 68472197 # number of ReadReq hits 741system.cpu0.icache.ReadReq_hits::total 68472197 # number of ReadReq hits 742system.cpu0.icache.demand_hits::cpu0.inst 68472197 # number of demand (read+write) hits 743system.cpu0.icache.demand_hits::total 68472197 # number of demand (read+write) hits 744system.cpu0.icache.overall_hits::cpu0.inst 68472197 # number of overall hits 745system.cpu0.icache.overall_hits::total 68472197 # number of overall hits 746system.cpu0.icache.ReadReq_misses::cpu0.inst 1982967 # number of ReadReq misses 747system.cpu0.icache.ReadReq_misses::total 1982967 # number of ReadReq misses 748system.cpu0.icache.demand_misses::cpu0.inst 1982967 # number of demand (read+write) misses 749system.cpu0.icache.demand_misses::total 1982967 # number of demand (read+write) misses 750system.cpu0.icache.overall_misses::cpu0.inst 1982967 # number of overall misses 751system.cpu0.icache.overall_misses::total 1982967 # number of overall misses 752system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18641895952 # number of ReadReq miss cycles 753system.cpu0.icache.ReadReq_miss_latency::total 18641895952 # number of ReadReq miss cycles 754system.cpu0.icache.demand_miss_latency::cpu0.inst 18641895952 # number of demand (read+write) miss cycles 755system.cpu0.icache.demand_miss_latency::total 18641895952 # number of demand (read+write) miss cycles 756system.cpu0.icache.overall_miss_latency::cpu0.inst 18641895952 # number of overall miss cycles 757system.cpu0.icache.overall_miss_latency::total 18641895952 # number of overall miss cycles 758system.cpu0.icache.ReadReq_accesses::cpu0.inst 70455164 # number of ReadReq accesses(hits+misses) 759system.cpu0.icache.ReadReq_accesses::total 70455164 # number of ReadReq accesses(hits+misses) 760system.cpu0.icache.demand_accesses::cpu0.inst 70455164 # number of demand (read+write) accesses 761system.cpu0.icache.demand_accesses::total 70455164 # number of demand (read+write) accesses 762system.cpu0.icache.overall_accesses::cpu0.inst 70455164 # number of overall (read+write) accesses 763system.cpu0.icache.overall_accesses::total 70455164 # number of overall (read+write) accesses 764system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028145 # miss rate for ReadReq accesses 765system.cpu0.icache.ReadReq_miss_rate::total 0.028145 # miss rate for ReadReq accesses 766system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028145 # miss rate for demand accesses 767system.cpu0.icache.demand_miss_rate::total 0.028145 # miss rate for demand accesses 768system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028145 # miss rate for overall accesses 769system.cpu0.icache.overall_miss_rate::total 0.028145 # miss rate for overall accesses 770system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9401.011692 # average ReadReq miss latency 771system.cpu0.icache.ReadReq_avg_miss_latency::total 9401.011692 # average ReadReq miss latency 772system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9401.011692 # average overall miss latency 773system.cpu0.icache.demand_avg_miss_latency::total 9401.011692 # average overall miss latency 774system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9401.011692 # average overall miss latency 775system.cpu0.icache.overall_avg_miss_latency::total 9401.011692 # average overall miss latency | 743system.cpu0.icache.tags.tag_accesses 79408512 # Number of tag accesses 744system.cpu0.icache.tags.data_accesses 79408512 # Number of data accesses 745system.cpu0.icache.ReadReq_hits::cpu0.inst 36748265 # number of ReadReq hits 746system.cpu0.icache.ReadReq_hits::total 36748265 # number of ReadReq hits 747system.cpu0.icache.demand_hits::cpu0.inst 36748265 # number of demand (read+write) hits 748system.cpu0.icache.demand_hits::total 36748265 # number of demand (read+write) hits 749system.cpu0.icache.overall_hits::cpu0.inst 36748265 # number of overall hits 750system.cpu0.icache.overall_hits::total 36748265 # number of overall hits 751system.cpu0.icache.ReadReq_misses::cpu0.inst 1970661 # number of ReadReq misses 752system.cpu0.icache.ReadReq_misses::total 1970661 # number of ReadReq misses 753system.cpu0.icache.demand_misses::cpu0.inst 1970661 # number of demand (read+write) misses 754system.cpu0.icache.demand_misses::total 1970661 # number of demand (read+write) misses 755system.cpu0.icache.overall_misses::cpu0.inst 1970661 # number of overall misses 756system.cpu0.icache.overall_misses::total 1970661 # number of overall misses 757system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18596838762 # number of ReadReq miss cycles 758system.cpu0.icache.ReadReq_miss_latency::total 18596838762 # number of ReadReq miss cycles 759system.cpu0.icache.demand_miss_latency::cpu0.inst 18596838762 # number of demand (read+write) miss cycles 760system.cpu0.icache.demand_miss_latency::total 18596838762 # number of demand (read+write) miss cycles 761system.cpu0.icache.overall_miss_latency::cpu0.inst 18596838762 # number of overall miss cycles 762system.cpu0.icache.overall_miss_latency::total 18596838762 # number of overall miss cycles 763system.cpu0.icache.ReadReq_accesses::cpu0.inst 38718926 # number of ReadReq accesses(hits+misses) 764system.cpu0.icache.ReadReq_accesses::total 38718926 # number of ReadReq accesses(hits+misses) 765system.cpu0.icache.demand_accesses::cpu0.inst 38718926 # number of demand (read+write) accesses 766system.cpu0.icache.demand_accesses::total 38718926 # number of demand (read+write) accesses 767system.cpu0.icache.overall_accesses::cpu0.inst 38718926 # number of overall (read+write) accesses 768system.cpu0.icache.overall_accesses::total 38718926 # number of overall (read+write) accesses 769system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050897 # miss rate for ReadReq accesses 770system.cpu0.icache.ReadReq_miss_rate::total 0.050897 # miss rate for ReadReq accesses 771system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050897 # miss rate for demand accesses 772system.cpu0.icache.demand_miss_rate::total 0.050897 # miss rate for demand accesses 773system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050897 # miss rate for overall accesses 774system.cpu0.icache.overall_miss_rate::total 0.050897 # miss rate for overall accesses 775system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9436.853300 # average ReadReq miss latency 776system.cpu0.icache.ReadReq_avg_miss_latency::total 9436.853300 # average ReadReq miss latency 777system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9436.853300 # average overall miss latency 778system.cpu0.icache.demand_avg_miss_latency::total 9436.853300 # average overall miss latency 779system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9436.853300 # average overall miss latency 780system.cpu0.icache.overall_avg_miss_latency::total 9436.853300 # average overall miss latency |
| 776system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 777system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 778system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 779system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 780system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 781system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 782system.cpu0.icache.fast_writes 0 # number of fast writes performed 783system.cpu0.icache.cache_copies 0 # number of cache copies performed | 781system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 782system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 783system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 784system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 785system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 786system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 787system.cpu0.icache.fast_writes 0 # number of fast writes performed 788system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 784system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1982967 # number of ReadReq MSHR misses 785system.cpu0.icache.ReadReq_mshr_misses::total 1982967 # number of ReadReq MSHR misses 786system.cpu0.icache.demand_mshr_misses::cpu0.inst 1982967 # number of demand (read+write) MSHR misses 787system.cpu0.icache.demand_mshr_misses::total 1982967 # number of demand (read+write) MSHR misses 788system.cpu0.icache.overall_mshr_misses::cpu0.inst 1982967 # number of overall MSHR misses 789system.cpu0.icache.overall_mshr_misses::total 1982967 # number of overall MSHR misses 790system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 15657207046 # number of ReadReq MSHR miss cycles 791system.cpu0.icache.ReadReq_mshr_miss_latency::total 15657207046 # number of ReadReq MSHR miss cycles 792system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 15657207046 # number of demand (read+write) MSHR miss cycles 793system.cpu0.icache.demand_mshr_miss_latency::total 15657207046 # number of demand (read+write) MSHR miss cycles 794system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 15657207046 # number of overall MSHR miss cycles 795system.cpu0.icache.overall_mshr_miss_latency::total 15657207046 # number of overall MSHR miss cycles 796system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 278031000 # number of ReadReq MSHR uncacheable cycles 797system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 278031000 # number of ReadReq MSHR uncacheable cycles 798system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 278031000 # number of overall MSHR uncacheable cycles 799system.cpu0.icache.overall_mshr_uncacheable_latency::total 278031000 # number of overall MSHR uncacheable cycles 800system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028145 # mshr miss rate for ReadReq accesses 801system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028145 # mshr miss rate for ReadReq accesses 802system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028145 # mshr miss rate for demand accesses 803system.cpu0.icache.demand_mshr_miss_rate::total 0.028145 # mshr miss rate for demand accesses 804system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028145 # mshr miss rate for overall accesses 805system.cpu0.icache.overall_mshr_miss_rate::total 0.028145 # mshr miss rate for overall accesses 806system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7895.848517 # average ReadReq mshr miss latency 807system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7895.848517 # average ReadReq mshr miss latency 808system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7895.848517 # average overall mshr miss latency 809system.cpu0.icache.demand_avg_mshr_miss_latency::total 7895.848517 # average overall mshr miss latency 810system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7895.848517 # average overall mshr miss latency 811system.cpu0.icache.overall_avg_mshr_miss_latency::total 7895.848517 # average overall mshr miss latency | 789system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1970661 # number of ReadReq MSHR misses 790system.cpu0.icache.ReadReq_mshr_misses::total 1970661 # number of ReadReq MSHR misses 791system.cpu0.icache.demand_mshr_misses::cpu0.inst 1970661 # number of demand (read+write) MSHR misses 792system.cpu0.icache.demand_mshr_misses::total 1970661 # number of demand (read+write) MSHR misses 793system.cpu0.icache.overall_mshr_misses::cpu0.inst 1970661 # number of overall MSHR misses 794system.cpu0.icache.overall_mshr_misses::total 1970661 # number of overall MSHR misses 795system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16616813240 # number of ReadReq MSHR miss cycles 796system.cpu0.icache.ReadReq_mshr_miss_latency::total 16616813240 # number of ReadReq MSHR miss cycles 797system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16616813240 # number of demand (read+write) MSHR miss cycles 798system.cpu0.icache.demand_mshr_miss_latency::total 16616813240 # number of demand (read+write) MSHR miss cycles 799system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16616813240 # number of overall MSHR miss cycles 800system.cpu0.icache.overall_mshr_miss_latency::total 16616813240 # number of overall MSHR miss cycles 801system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 312357250 # number of ReadReq MSHR uncacheable cycles 802system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 312357250 # number of ReadReq MSHR uncacheable cycles 803system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 312357250 # number of overall MSHR uncacheable cycles 804system.cpu0.icache.overall_mshr_uncacheable_latency::total 312357250 # number of overall MSHR uncacheable cycles 805system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050897 # mshr miss rate for ReadReq accesses 806system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050897 # mshr miss rate for ReadReq accesses 807system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050897 # mshr miss rate for demand accesses 808system.cpu0.icache.demand_mshr_miss_rate::total 0.050897 # mshr miss rate for demand accesses 809system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050897 # mshr miss rate for overall accesses 810system.cpu0.icache.overall_mshr_miss_rate::total 0.050897 # mshr miss rate for overall accesses 811system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8432.101330 # average ReadReq mshr miss latency 812system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8432.101330 # average ReadReq mshr miss latency 813system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8432.101330 # average overall mshr miss latency 814system.cpu0.icache.demand_avg_mshr_miss_latency::total 8432.101330 # average overall mshr miss latency 815system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8432.101330 # average overall mshr miss latency 816system.cpu0.icache.overall_avg_mshr_miss_latency::total 8432.101330 # average overall mshr miss latency |
| 812system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 813system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 814system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 815system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 816system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 817system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 818system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 819system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 820system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 821system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 817system.cpu0.l2cache.prefetcher.num_hwpf_issued 2292717 # number of hwpf issued 818system.cpu0.l2cache.prefetcher.pfIdentified 2293221 # number of prefetch candidates identified 819system.cpu0.l2cache.prefetcher.pfBufferHit 436 # number of redundant prefetches already in prefetch queue | 822system.cpu0.l2cache.prefetcher.num_hwpf_issued 2299938 # number of hwpf issued 823system.cpu0.l2cache.prefetcher.pfIdentified 2300657 # number of prefetch candidates identified 824system.cpu0.l2cache.prefetcher.pfBufferHit 626 # number of redundant prefetches already in prefetch queue |
| 820system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 821system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 825system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 826system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 822system.cpu0.l2cache.prefetcher.pfSpanPage 284211 # number of prefetches not generated due to page crossing 823system.cpu0.l2cache.tags.replacements 303376 # number of replacements 824system.cpu0.l2cache.tags.tagsinuse 16141.726832 # Cycle average of tags in use 825system.cpu0.l2cache.tags.total_refs 2969035 # Total number of references to valid blocks. 826system.cpu0.l2cache.tags.sampled_refs 319611 # Sample count of references to valid blocks. 827system.cpu0.l2cache.tags.avg_refs 9.289527 # Average number of references to valid blocks. 828system.cpu0.l2cache.tags.warmup_cycle 2825848630000 # Cycle when the warmup percentage was hit. 829system.cpu0.l2cache.tags.occ_blocks::writebacks 6310.295058 # Average occupied blocks per requestor 830system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.412646 # Average occupied blocks per requestor 831system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.063392 # Average occupied blocks per requestor 832system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5929.101601 # Average occupied blocks per requestor 833system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1862.423160 # Average occupied blocks per requestor 834system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1981.430976 # Average occupied blocks per requestor 835system.cpu0.l2cache.tags.occ_percent::writebacks 0.385150 # Average percentage of cache occupancy 836system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003565 # Average percentage of cache occupancy 837system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy 838system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.361884 # Average percentage of cache occupancy 839system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.113673 # Average percentage of cache occupancy 840system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.120937 # Average percentage of cache occupancy 841system.cpu0.l2cache.tags.occ_percent::total 0.985213 # Average percentage of cache occupancy 842system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1941 # Occupied blocks per task id 843system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id 844system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14280 # Occupied blocks per task id 845system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id 846system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 509 # Occupied blocks per task id 847system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 923 # Occupied blocks per task id 848system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 497 # Occupied blocks per task id | 827system.cpu0.l2cache.prefetcher.pfSpanPage 288151 # number of prefetches not generated due to page crossing 828system.cpu0.l2cache.tags.replacements 300423 # number of replacements 829system.cpu0.l2cache.tags.tagsinuse 16135.818285 # Cycle average of tags in use 830system.cpu0.l2cache.tags.total_refs 2948802 # Total number of references to valid blocks. 831system.cpu0.l2cache.tags.sampled_refs 316647 # Sample count of references to valid blocks. 832system.cpu0.l2cache.tags.avg_refs 9.312585 # Average number of references to valid blocks. 833system.cpu0.l2cache.tags.warmup_cycle 2825975663500 # Cycle when the warmup percentage was hit. 834system.cpu0.l2cache.tags.occ_blocks::writebacks 6474.830142 # Average occupied blocks per requestor 835system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 56.840728 # Average occupied blocks per requestor 836system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.090495 # Average occupied blocks per requestor 837system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5820.472159 # Average occupied blocks per requestor 838system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1850.674004 # Average occupied blocks per requestor 839system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1932.910757 # Average occupied blocks per requestor 840system.cpu0.l2cache.tags.occ_percent::writebacks 0.395192 # Average percentage of cache occupancy 841system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003469 # Average percentage of cache occupancy 842system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy 843system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.355253 # Average percentage of cache occupancy 844system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.112956 # Average percentage of cache occupancy 845system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.117976 # Average percentage of cache occupancy 846system.cpu0.l2cache.tags.occ_percent::total 0.984852 # Average percentage of cache occupancy 847system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1935 # Occupied blocks per task id 848system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 849system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14276 # Occupied blocks per task id 850system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 851system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 526 # Occupied blocks per task id 852system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 949 # Occupied blocks per task id 853system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 452 # Occupied blocks per task id 854system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id |
| 849system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 850system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id | 855system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 856system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id |
| 851system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 852system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id 853system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id 854system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4022 # Occupied blocks per task id 855system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7455 # Occupied blocks per task id 856system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2494 # Occupied blocks per task id 857system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.118469 # Percentage of cache occupancy per task id 858system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id 859system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.871582 # Percentage of cache occupancy per task id 860system.cpu0.l2cache.tags.tag_accesses 55347065 # Number of tag accesses 861system.cpu0.l2cache.tags.data_accesses 55347065 # Number of data accesses 862system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 80493 # number of ReadReq hits 863system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4332 # number of ReadReq hits 864system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1910084 # number of ReadReq hits 865system.cpu0.l2cache.ReadReq_hits::cpu0.data 434260 # number of ReadReq hits 866system.cpu0.l2cache.ReadReq_hits::total 2429169 # number of ReadReq hits 867system.cpu0.l2cache.Writeback_hits::writebacks 523100 # number of Writeback hits 868system.cpu0.l2cache.Writeback_hits::total 523100 # number of Writeback hits 869system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 4781 # number of UpgradeReq hits 870system.cpu0.l2cache.UpgradeReq_hits::total 4781 # number of UpgradeReq hits 871system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1890 # number of SCUpgradeReq hits 872system.cpu0.l2cache.SCUpgradeReq_hits::total 1890 # number of SCUpgradeReq hits 873system.cpu0.l2cache.ReadExReq_hits::cpu0.data 226532 # number of ReadExReq hits 874system.cpu0.l2cache.ReadExReq_hits::total 226532 # number of ReadExReq hits 875system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 80493 # number of demand (read+write) hits 876system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4332 # number of demand (read+write) hits 877system.cpu0.l2cache.demand_hits::cpu0.inst 1910084 # number of demand (read+write) hits 878system.cpu0.l2cache.demand_hits::cpu0.data 660792 # number of demand (read+write) hits 879system.cpu0.l2cache.demand_hits::total 2655701 # number of demand (read+write) hits 880system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 80493 # number of overall hits 881system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4332 # number of overall hits 882system.cpu0.l2cache.overall_hits::cpu0.inst 1910084 # number of overall hits 883system.cpu0.l2cache.overall_hits::cpu0.data 660792 # number of overall hits 884system.cpu0.l2cache.overall_hits::total 2655701 # number of overall hits 885system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 854 # number of ReadReq misses 886system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 113 # number of ReadReq misses 887system.cpu0.l2cache.ReadReq_misses::cpu0.inst 72883 # number of ReadReq misses 888system.cpu0.l2cache.ReadReq_misses::cpu0.data 69644 # number of ReadReq misses 889system.cpu0.l2cache.ReadReq_misses::total 143494 # number of ReadReq misses 890system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26406 # number of UpgradeReq misses 891system.cpu0.l2cache.UpgradeReq_misses::total 26406 # number of UpgradeReq misses 892system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18006 # number of SCUpgradeReq misses 893system.cpu0.l2cache.SCUpgradeReq_misses::total 18006 # number of SCUpgradeReq misses 894system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses 895system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 896system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44082 # number of ReadExReq misses 897system.cpu0.l2cache.ReadExReq_misses::total 44082 # number of ReadExReq misses 898system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 854 # number of demand (read+write) misses 899system.cpu0.l2cache.demand_misses::cpu0.itb.walker 113 # number of demand (read+write) misses 900system.cpu0.l2cache.demand_misses::cpu0.inst 72883 # number of demand (read+write) misses 901system.cpu0.l2cache.demand_misses::cpu0.data 113726 # number of demand (read+write) misses 902system.cpu0.l2cache.demand_misses::total 187576 # number of demand (read+write) misses 903system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 854 # number of overall misses 904system.cpu0.l2cache.overall_misses::cpu0.itb.walker 113 # number of overall misses 905system.cpu0.l2cache.overall_misses::cpu0.inst 72883 # number of overall misses 906system.cpu0.l2cache.overall_misses::cpu0.data 113726 # number of overall misses 907system.cpu0.l2cache.overall_misses::total 187576 # number of overall misses 908system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 30085500 # number of ReadReq miss cycles 909system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2495499 # number of ReadReq miss cycles 910system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 3197828979 # number of ReadReq miss cycles 911system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2112725700 # number of ReadReq miss cycles 912system.cpu0.l2cache.ReadReq_miss_latency::total 5343135678 # number of ReadReq miss cycles 913system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 462181513 # number of UpgradeReq miss cycles 914system.cpu0.l2cache.UpgradeReq_miss_latency::total 462181513 # number of UpgradeReq miss cycles 915system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 354964789 # number of SCUpgradeReq miss cycles 916system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 354964789 # number of SCUpgradeReq miss cycles 917system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 282000 # number of SCUpgradeFailReq miss cycles 918system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 282000 # number of SCUpgradeFailReq miss cycles 919system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2099231484 # number of ReadExReq miss cycles 920system.cpu0.l2cache.ReadExReq_miss_latency::total 2099231484 # number of ReadExReq miss cycles 921system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 30085500 # number of demand (read+write) miss cycles 922system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2495499 # number of demand (read+write) miss cycles 923system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3197828979 # number of demand (read+write) miss cycles 924system.cpu0.l2cache.demand_miss_latency::cpu0.data 4211957184 # number of demand (read+write) miss cycles 925system.cpu0.l2cache.demand_miss_latency::total 7442367162 # number of demand (read+write) miss cycles 926system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 30085500 # number of overall miss cycles 927system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2495499 # number of overall miss cycles 928system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3197828979 # number of overall miss cycles 929system.cpu0.l2cache.overall_miss_latency::cpu0.data 4211957184 # number of overall miss cycles 930system.cpu0.l2cache.overall_miss_latency::total 7442367162 # number of overall miss cycles 931system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 81347 # number of ReadReq accesses(hits+misses) 932system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4445 # number of ReadReq accesses(hits+misses) 933system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1982967 # number of ReadReq accesses(hits+misses) 934system.cpu0.l2cache.ReadReq_accesses::cpu0.data 503904 # number of ReadReq accesses(hits+misses) 935system.cpu0.l2cache.ReadReq_accesses::total 2572663 # number of ReadReq accesses(hits+misses) 936system.cpu0.l2cache.Writeback_accesses::writebacks 523100 # number of Writeback accesses(hits+misses) 937system.cpu0.l2cache.Writeback_accesses::total 523100 # number of Writeback accesses(hits+misses) 938system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 31187 # number of UpgradeReq accesses(hits+misses) 939system.cpu0.l2cache.UpgradeReq_accesses::total 31187 # number of UpgradeReq accesses(hits+misses) 940system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19896 # number of SCUpgradeReq accesses(hits+misses) 941system.cpu0.l2cache.SCUpgradeReq_accesses::total 19896 # number of SCUpgradeReq accesses(hits+misses) 942system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 943system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 944system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270614 # number of ReadExReq accesses(hits+misses) 945system.cpu0.l2cache.ReadExReq_accesses::total 270614 # number of ReadExReq accesses(hits+misses) 946system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 81347 # number of demand (read+write) accesses 947system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4445 # number of demand (read+write) accesses 948system.cpu0.l2cache.demand_accesses::cpu0.inst 1982967 # number of demand (read+write) accesses 949system.cpu0.l2cache.demand_accesses::cpu0.data 774518 # number of demand (read+write) accesses 950system.cpu0.l2cache.demand_accesses::total 2843277 # number of demand (read+write) accesses 951system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 81347 # number of overall (read+write) accesses 952system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4445 # number of overall (read+write) accesses 953system.cpu0.l2cache.overall_accesses::cpu0.inst 1982967 # number of overall (read+write) accesses 954system.cpu0.l2cache.overall_accesses::cpu0.data 774518 # number of overall (read+write) accesses 955system.cpu0.l2cache.overall_accesses::total 2843277 # number of overall (read+write) accesses 956system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010498 # miss rate for ReadReq accesses 957system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025422 # miss rate for ReadReq accesses 958system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.036755 # miss rate for ReadReq accesses 959system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.138209 # miss rate for ReadReq accesses 960system.cpu0.l2cache.ReadReq_miss_rate::total 0.055776 # miss rate for ReadReq accesses 961system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.846699 # miss rate for UpgradeReq accesses 962system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.846699 # miss rate for UpgradeReq accesses 963system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.905006 # miss rate for SCUpgradeReq accesses 964system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.905006 # miss rate for SCUpgradeReq accesses | 857system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 858system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 859system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id 860system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3958 # Occupied blocks per task id 861system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7592 # Occupied blocks per task id 862system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2420 # Occupied blocks per task id 863system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.118103 # Percentage of cache occupancy per task id 864system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id 865system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.871338 # Percentage of cache occupancy per task id 866system.cpu0.l2cache.tags.tag_accesses 54983870 # Number of tag accesses 867system.cpu0.l2cache.tags.data_accesses 54983870 # Number of data accesses 868system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 80556 # number of ReadReq hits 869system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4286 # number of ReadReq hits 870system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1899770 # number of ReadReq hits 871system.cpu0.l2cache.ReadReq_hits::cpu0.data 431338 # number of ReadReq hits 872system.cpu0.l2cache.ReadReq_hits::total 2415950 # number of ReadReq hits 873system.cpu0.l2cache.Writeback_hits::writebacks 516061 # number of Writeback hits 874system.cpu0.l2cache.Writeback_hits::total 516061 # number of Writeback hits 875system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 4718 # number of UpgradeReq hits 876system.cpu0.l2cache.UpgradeReq_hits::total 4718 # number of UpgradeReq hits 877system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1821 # number of SCUpgradeReq hits 878system.cpu0.l2cache.SCUpgradeReq_hits::total 1821 # number of SCUpgradeReq hits 879system.cpu0.l2cache.ReadExReq_hits::cpu0.data 223877 # number of ReadExReq hits 880system.cpu0.l2cache.ReadExReq_hits::total 223877 # number of ReadExReq hits 881system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 80556 # number of demand (read+write) hits 882system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4286 # number of demand (read+write) hits 883system.cpu0.l2cache.demand_hits::cpu0.inst 1899770 # number of demand (read+write) hits 884system.cpu0.l2cache.demand_hits::cpu0.data 655215 # number of demand (read+write) hits 885system.cpu0.l2cache.demand_hits::total 2639827 # number of demand (read+write) hits 886system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 80556 # number of overall hits 887system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4286 # number of overall hits 888system.cpu0.l2cache.overall_hits::cpu0.inst 1899770 # number of overall hits 889system.cpu0.l2cache.overall_hits::cpu0.data 655215 # number of overall hits 890system.cpu0.l2cache.overall_hits::total 2639827 # number of overall hits 891system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 849 # number of ReadReq misses 892system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 121 # number of ReadReq misses 893system.cpu0.l2cache.ReadReq_misses::cpu0.inst 70891 # number of ReadReq misses 894system.cpu0.l2cache.ReadReq_misses::cpu0.data 70175 # number of ReadReq misses 895system.cpu0.l2cache.ReadReq_misses::total 142036 # number of ReadReq misses 896system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27075 # number of UpgradeReq misses 897system.cpu0.l2cache.UpgradeReq_misses::total 27075 # number of UpgradeReq misses 898system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18442 # number of SCUpgradeReq misses 899system.cpu0.l2cache.SCUpgradeReq_misses::total 18442 # number of SCUpgradeReq misses 900system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses 901system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 902system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44966 # number of ReadExReq misses 903system.cpu0.l2cache.ReadExReq_misses::total 44966 # number of ReadExReq misses 904system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 849 # number of demand (read+write) misses 905system.cpu0.l2cache.demand_misses::cpu0.itb.walker 121 # number of demand (read+write) misses 906system.cpu0.l2cache.demand_misses::cpu0.inst 70891 # number of demand (read+write) misses 907system.cpu0.l2cache.demand_misses::cpu0.data 115141 # number of demand (read+write) misses 908system.cpu0.l2cache.demand_misses::total 187002 # number of demand (read+write) misses 909system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 849 # number of overall misses 910system.cpu0.l2cache.overall_misses::cpu0.itb.walker 121 # number of overall misses 911system.cpu0.l2cache.overall_misses::cpu0.inst 70891 # number of overall misses 912system.cpu0.l2cache.overall_misses::cpu0.data 115141 # number of overall misses 913system.cpu0.l2cache.overall_misses::total 187002 # number of overall misses 914system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 30876250 # number of ReadReq miss cycles 915system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2731998 # number of ReadReq miss cycles 916system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 3274401699 # number of ReadReq miss cycles 917system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2190541082 # number of ReadReq miss cycles 918system.cpu0.l2cache.ReadReq_miss_latency::total 5498551029 # number of ReadReq miss cycles 919system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 500181256 # number of UpgradeReq miss cycles 920system.cpu0.l2cache.UpgradeReq_miss_latency::total 500181256 # number of UpgradeReq miss cycles 921system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 372946806 # number of SCUpgradeReq miss cycles 922system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 372946806 # number of SCUpgradeReq miss cycles 923system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 142499 # number of SCUpgradeFailReq miss cycles 924system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 142499 # number of SCUpgradeFailReq miss cycles 925system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2230359389 # number of ReadExReq miss cycles 926system.cpu0.l2cache.ReadExReq_miss_latency::total 2230359389 # number of ReadExReq miss cycles 927system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 30876250 # number of demand (read+write) miss cycles 928system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2731998 # number of demand (read+write) miss cycles 929system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3274401699 # number of demand (read+write) miss cycles 930system.cpu0.l2cache.demand_miss_latency::cpu0.data 4420900471 # number of demand (read+write) miss cycles 931system.cpu0.l2cache.demand_miss_latency::total 7728910418 # number of demand (read+write) miss cycles 932system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 30876250 # number of overall miss cycles 933system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2731998 # number of overall miss cycles 934system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3274401699 # number of overall miss cycles 935system.cpu0.l2cache.overall_miss_latency::cpu0.data 4420900471 # number of overall miss cycles 936system.cpu0.l2cache.overall_miss_latency::total 7728910418 # number of overall miss cycles 937system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 81405 # number of ReadReq accesses(hits+misses) 938system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4407 # number of ReadReq accesses(hits+misses) 939system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1970661 # number of ReadReq accesses(hits+misses) 940system.cpu0.l2cache.ReadReq_accesses::cpu0.data 501513 # number of ReadReq accesses(hits+misses) 941system.cpu0.l2cache.ReadReq_accesses::total 2557986 # number of ReadReq accesses(hits+misses) 942system.cpu0.l2cache.Writeback_accesses::writebacks 516061 # number of Writeback accesses(hits+misses) 943system.cpu0.l2cache.Writeback_accesses::total 516061 # number of Writeback accesses(hits+misses) 944system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 31793 # number of UpgradeReq accesses(hits+misses) 945system.cpu0.l2cache.UpgradeReq_accesses::total 31793 # number of UpgradeReq accesses(hits+misses) 946system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20263 # number of SCUpgradeReq accesses(hits+misses) 947system.cpu0.l2cache.SCUpgradeReq_accesses::total 20263 # number of SCUpgradeReq accesses(hits+misses) 948system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 949system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 950system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 268843 # number of ReadExReq accesses(hits+misses) 951system.cpu0.l2cache.ReadExReq_accesses::total 268843 # number of ReadExReq accesses(hits+misses) 952system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 81405 # number of demand (read+write) accesses 953system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4407 # number of demand (read+write) accesses 954system.cpu0.l2cache.demand_accesses::cpu0.inst 1970661 # number of demand (read+write) accesses 955system.cpu0.l2cache.demand_accesses::cpu0.data 770356 # number of demand (read+write) accesses 956system.cpu0.l2cache.demand_accesses::total 2826829 # number of demand (read+write) accesses 957system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 81405 # number of overall (read+write) accesses 958system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4407 # number of overall (read+write) accesses 959system.cpu0.l2cache.overall_accesses::cpu0.inst 1970661 # number of overall (read+write) accesses 960system.cpu0.l2cache.overall_accesses::cpu0.data 770356 # number of overall (read+write) accesses 961system.cpu0.l2cache.overall_accesses::total 2826829 # number of overall (read+write) accesses 962system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010429 # miss rate for ReadReq accesses 963system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.027456 # miss rate for ReadReq accesses 964system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.035973 # miss rate for ReadReq accesses 965system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.139927 # miss rate for ReadReq accesses 966system.cpu0.l2cache.ReadReq_miss_rate::total 0.055526 # miss rate for ReadReq accesses 967system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.851603 # miss rate for UpgradeReq accesses 968system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.851603 # miss rate for UpgradeReq accesses 969system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.910132 # miss rate for SCUpgradeReq accesses 970system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.910132 # miss rate for SCUpgradeReq accesses |
| 965system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 966system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 971system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 972system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 967system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.162896 # miss rate for ReadExReq accesses 968system.cpu0.l2cache.ReadExReq_miss_rate::total 0.162896 # miss rate for ReadExReq accesses 969system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010498 # miss rate for demand accesses 970system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025422 # miss rate for demand accesses 971system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.036755 # miss rate for demand accesses 972system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.146835 # miss rate for demand accesses 973system.cpu0.l2cache.demand_miss_rate::total 0.065972 # miss rate for demand accesses 974system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010498 # miss rate for overall accesses 975system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025422 # miss rate for overall accesses 976system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.036755 # miss rate for overall accesses 977system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.146835 # miss rate for overall accesses 978system.cpu0.l2cache.overall_miss_rate::total 0.065972 # miss rate for overall accesses 979system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35228.922717 # average ReadReq miss latency 980system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22084.061947 # average ReadReq miss latency 981system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 43876.198551 # average ReadReq miss latency 982system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 30336.076331 # average ReadReq miss latency 983system.cpu0.l2cache.ReadReq_avg_miss_latency::total 37235.951873 # average ReadReq miss latency 984system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17502.897561 # average UpgradeReq miss latency 985system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17502.897561 # average UpgradeReq miss latency 986system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19713.694824 # average SCUpgradeReq miss latency 987system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19713.694824 # average SCUpgradeReq miss latency 988system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 141000 # average SCUpgradeFailReq miss latency 989system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 141000 # average SCUpgradeFailReq miss latency 990system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47621.058119 # average ReadExReq miss latency 991system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47621.058119 # average ReadExReq miss latency 992system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35228.922717 # average overall miss latency 993system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22084.061947 # average overall miss latency 994system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 43876.198551 # average overall miss latency 995system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37036.009215 # average overall miss latency 996system.cpu0.l2cache.demand_avg_miss_latency::total 39676.542639 # average overall miss latency 997system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35228.922717 # average overall miss latency 998system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22084.061947 # average overall miss latency 999system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 43876.198551 # average overall miss latency 1000system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37036.009215 # average overall miss latency 1001system.cpu0.l2cache.overall_avg_miss_latency::total 39676.542639 # average overall miss latency | 973system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.167257 # miss rate for ReadExReq accesses 974system.cpu0.l2cache.ReadExReq_miss_rate::total 0.167257 # miss rate for ReadExReq accesses 975system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010429 # miss rate for demand accesses 976system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.027456 # miss rate for demand accesses 977system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.035973 # miss rate for demand accesses 978system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.149465 # miss rate for demand accesses 979system.cpu0.l2cache.demand_miss_rate::total 0.066153 # miss rate for demand accesses 980system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010429 # miss rate for overall accesses 981system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.027456 # miss rate for overall accesses 982system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.035973 # miss rate for overall accesses 983system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.149465 # miss rate for overall accesses 984system.cpu0.l2cache.overall_miss_rate::total 0.066153 # miss rate for overall accesses 985system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36367.785630 # average ReadReq miss latency 986system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22578.495868 # average ReadReq miss latency 987system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46189.244037 # average ReadReq miss latency 988system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 31215.405515 # average ReadReq miss latency 989system.cpu0.l2cache.ReadReq_avg_miss_latency::total 38712.375940 # average ReadReq miss latency 990system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18473.915272 # average UpgradeReq miss latency 991system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18473.915272 # average UpgradeReq miss latency 992system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20222.687669 # average SCUpgradeReq miss latency 993system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20222.687669 # average SCUpgradeReq miss latency 994system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 142499 # average SCUpgradeFailReq miss latency 995system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 142499 # average SCUpgradeFailReq miss latency 996system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49601.018303 # average ReadExReq miss latency 997system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49601.018303 # average ReadExReq miss latency 998system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36367.785630 # average overall miss latency 999system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22578.495868 # average overall miss latency 1000system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46189.244037 # average overall miss latency 1001system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38395.536525 # average overall miss latency 1002system.cpu0.l2cache.demand_avg_miss_latency::total 41330.629715 # average overall miss latency 1003system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36367.785630 # average overall miss latency 1004system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22578.495868 # average overall miss latency 1005system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46189.244037 # average overall miss latency 1006system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38395.536525 # average overall miss latency 1007system.cpu0.l2cache.overall_avg_miss_latency::total 41330.629715 # average overall miss latency |
| 1002system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1003system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1004system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1005system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1006system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1007system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1008system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1009system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 1008system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1009system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1010system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1011system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1012system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1013system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1014system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1015system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 1010system.cpu0.l2cache.writebacks::writebacks 201133 # number of writebacks 1011system.cpu0.l2cache.writebacks::total 201133 # number of writebacks 1012system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits 1013system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 65 # number of ReadReq MSHR hits 1014system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 446 # number of ReadReq MSHR hits 1015system.cpu0.l2cache.ReadReq_mshr_hits::total 512 # number of ReadReq MSHR hits 1016system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3265 # number of ReadExReq MSHR hits 1017system.cpu0.l2cache.ReadExReq_mshr_hits::total 3265 # number of ReadExReq MSHR hits 1018system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits 1019system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 65 # number of demand (read+write) MSHR hits 1020system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3711 # number of demand (read+write) MSHR hits 1021system.cpu0.l2cache.demand_mshr_hits::total 3777 # number of demand (read+write) MSHR hits 1022system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits 1023system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 65 # number of overall MSHR hits 1024system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3711 # number of overall MSHR hits 1025system.cpu0.l2cache.overall_mshr_hits::total 3777 # number of overall MSHR hits 1026system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 854 # number of ReadReq MSHR misses 1027system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 112 # number of ReadReq MSHR misses 1028system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 72818 # number of ReadReq MSHR misses 1029system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 69198 # number of ReadReq MSHR misses 1030system.cpu0.l2cache.ReadReq_mshr_misses::total 142982 # number of ReadReq MSHR misses 1031system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 280772 # number of HardPFReq MSHR misses 1032system.cpu0.l2cache.HardPFReq_mshr_misses::total 280772 # number of HardPFReq MSHR misses 1033system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26406 # number of UpgradeReq MSHR misses 1034system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26406 # number of UpgradeReq MSHR misses 1035system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18006 # number of SCUpgradeReq MSHR misses 1036system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18006 # number of SCUpgradeReq MSHR misses 1037system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses 1038system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 1039system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40817 # number of ReadExReq MSHR misses 1040system.cpu0.l2cache.ReadExReq_mshr_misses::total 40817 # number of ReadExReq MSHR misses 1041system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 854 # number of demand (read+write) MSHR misses 1042system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 112 # number of demand (read+write) MSHR misses 1043system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 72818 # number of demand (read+write) MSHR misses 1044system.cpu0.l2cache.demand_mshr_misses::cpu0.data 110015 # number of demand (read+write) MSHR misses 1045system.cpu0.l2cache.demand_mshr_misses::total 183799 # number of demand (read+write) MSHR misses 1046system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 854 # number of overall MSHR misses 1047system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 112 # number of overall MSHR misses 1048system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 72818 # number of overall MSHR misses 1049system.cpu0.l2cache.overall_mshr_misses::cpu0.data 110015 # number of overall MSHR misses 1050system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 280772 # number of overall MSHR misses 1051system.cpu0.l2cache.overall_mshr_misses::total 464571 # number of overall MSHR misses 1052system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 24090000 # number of ReadReq MSHR miss cycles 1053system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1685499 # number of ReadReq MSHR miss cycles 1054system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2677133771 # number of ReadReq MSHR miss cycles 1055system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1602381204 # number of ReadReq MSHR miss cycles 1056system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4305290474 # number of ReadReq MSHR miss cycles 1057system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15488924735 # number of HardPFReq MSHR miss cycles 1058system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15488924735 # number of HardPFReq MSHR miss cycles 1059system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 449600763 # number of UpgradeReq MSHR miss cycles 1060system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 449600763 # number of UpgradeReq MSHR miss cycles 1061system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 240569359 # number of SCUpgradeReq MSHR miss cycles 1062system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 240569359 # number of SCUpgradeReq MSHR miss cycles 1063system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 219000 # number of SCUpgradeFailReq MSHR miss cycles 1064system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 219000 # number of SCUpgradeFailReq MSHR miss cycles 1065system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1467254248 # number of ReadExReq MSHR miss cycles 1066system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1467254248 # number of ReadExReq MSHR miss cycles 1067system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 24090000 # number of demand (read+write) MSHR miss cycles 1068system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1685499 # number of demand (read+write) MSHR miss cycles 1069system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2677133771 # number of demand (read+write) MSHR miss cycles 1070system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3069635452 # number of demand (read+write) MSHR miss cycles 1071system.cpu0.l2cache.demand_mshr_miss_latency::total 5772544722 # number of demand (read+write) MSHR miss cycles 1072system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 24090000 # number of overall MSHR miss cycles 1073system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1685499 # number of overall MSHR miss cycles 1074system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2677133771 # number of overall MSHR miss cycles 1075system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3069635452 # number of overall MSHR miss cycles 1076system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15488924735 # number of overall MSHR miss cycles 1077system.cpu0.l2cache.overall_mshr_miss_latency::total 21261469457 # number of overall MSHR miss cycles 1078system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 242870500 # number of ReadReq MSHR uncacheable cycles 1079system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5934206491 # number of ReadReq MSHR uncacheable cycles 1080system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6177076991 # number of ReadReq MSHR uncacheable cycles 1081system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4588309497 # number of WriteReq MSHR uncacheable cycles 1082system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4588309497 # number of WriteReq MSHR uncacheable cycles 1083system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 242870500 # number of overall MSHR uncacheable cycles 1084system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10522515988 # number of overall MSHR uncacheable cycles 1085system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10765386488 # number of overall MSHR uncacheable cycles 1086system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for ReadReq accesses 1087system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for ReadReq accesses 1088system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.036722 # mshr miss rate for ReadReq accesses 1089system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.137324 # mshr miss rate for ReadReq accesses 1090system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.055577 # mshr miss rate for ReadReq accesses | 1016system.cpu0.l2cache.writebacks::writebacks 200203 # number of writebacks 1017system.cpu0.l2cache.writebacks::total 200203 # number of writebacks 1018system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 78 # number of ReadReq MSHR hits 1019system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 437 # number of ReadReq MSHR hits 1020system.cpu0.l2cache.ReadReq_mshr_hits::total 515 # number of ReadReq MSHR hits 1021system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 2951 # number of ReadExReq MSHR hits 1022system.cpu0.l2cache.ReadExReq_mshr_hits::total 2951 # number of ReadExReq MSHR hits 1023system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 78 # number of demand (read+write) MSHR hits 1024system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3388 # number of demand (read+write) MSHR hits 1025system.cpu0.l2cache.demand_mshr_hits::total 3466 # number of demand (read+write) MSHR hits 1026system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 78 # number of overall MSHR hits 1027system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3388 # number of overall MSHR hits 1028system.cpu0.l2cache.overall_mshr_hits::total 3466 # number of overall MSHR hits 1029system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 849 # number of ReadReq MSHR misses 1030system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 121 # number of ReadReq MSHR misses 1031system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 70813 # number of ReadReq MSHR misses 1032system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 69738 # number of ReadReq MSHR misses 1033system.cpu0.l2cache.ReadReq_mshr_misses::total 141521 # number of ReadReq MSHR misses 1034system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 280214 # number of HardPFReq MSHR misses 1035system.cpu0.l2cache.HardPFReq_mshr_misses::total 280214 # number of HardPFReq MSHR misses 1036system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27075 # number of UpgradeReq MSHR misses 1037system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27075 # number of UpgradeReq MSHR misses 1038system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18442 # number of SCUpgradeReq MSHR misses 1039system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18442 # number of SCUpgradeReq MSHR misses 1040system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses 1041system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 1042system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42015 # number of ReadExReq MSHR misses 1043system.cpu0.l2cache.ReadExReq_mshr_misses::total 42015 # number of ReadExReq MSHR misses 1044system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 849 # number of demand (read+write) MSHR misses 1045system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 121 # number of demand (read+write) MSHR misses 1046system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 70813 # number of demand (read+write) MSHR misses 1047system.cpu0.l2cache.demand_mshr_misses::cpu0.data 111753 # number of demand (read+write) MSHR misses 1048system.cpu0.l2cache.demand_mshr_misses::total 183536 # number of demand (read+write) MSHR misses 1049system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 849 # number of overall MSHR misses 1050system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 121 # number of overall MSHR misses 1051system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 70813 # number of overall MSHR misses 1052system.cpu0.l2cache.overall_mshr_misses::cpu0.data 111753 # number of overall MSHR misses 1053system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 280214 # number of overall MSHR misses 1054system.cpu0.l2cache.overall_mshr_misses::total 463750 # number of overall MSHR misses 1055system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 25343250 # number of ReadReq MSHR miss cycles 1056system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1944500 # number of ReadReq MSHR miss cycles 1057system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2803376051 # number of ReadReq MSHR miss cycles 1058system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1710921798 # number of ReadReq MSHR miss cycles 1059system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4541585599 # number of ReadReq MSHR miss cycles 1060system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14990911200 # number of HardPFReq MSHR miss cycles 1061system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 14990911200 # number of HardPFReq MSHR miss cycles 1062system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 547256396 # number of UpgradeReq MSHR miss cycles 1063system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 547256396 # number of UpgradeReq MSHR miss cycles 1064system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 271139812 # number of SCUpgradeReq MSHR miss cycles 1065system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 271139812 # number of SCUpgradeReq MSHR miss cycles 1066system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 116499 # number of SCUpgradeFailReq MSHR miss cycles 1067system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 116499 # number of SCUpgradeFailReq MSHR miss cycles 1068system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1628836464 # number of ReadExReq MSHR miss cycles 1069system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1628836464 # number of ReadExReq MSHR miss cycles 1070system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 25343250 # number of demand (read+write) MSHR miss cycles 1071system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1944500 # number of demand (read+write) MSHR miss cycles 1072system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2803376051 # number of demand (read+write) MSHR miss cycles 1073system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3339758262 # number of demand (read+write) MSHR miss cycles 1074system.cpu0.l2cache.demand_mshr_miss_latency::total 6170422063 # number of demand (read+write) MSHR miss cycles 1075system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 25343250 # number of overall MSHR miss cycles 1076system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1944500 # number of overall MSHR miss cycles 1077system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2803376051 # number of overall MSHR miss cycles 1078system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3339758262 # number of overall MSHR miss cycles 1079system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14990911200 # number of overall MSHR miss cycles 1080system.cpu0.l2cache.overall_mshr_miss_latency::total 21161333263 # number of overall MSHR miss cycles 1081system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 283700250 # number of ReadReq MSHR uncacheable cycles 1082system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4113316250 # number of ReadReq MSHR uncacheable cycles 1083system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4397016500 # number of ReadReq MSHR uncacheable cycles 1084system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3118122000 # number of WriteReq MSHR uncacheable cycles 1085system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3118122000 # number of WriteReq MSHR uncacheable cycles 1086system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 283700250 # number of overall MSHR uncacheable cycles 1087system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7231438250 # number of overall MSHR uncacheable cycles 1088system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7515138500 # number of overall MSHR uncacheable cycles 1089system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010429 # mshr miss rate for ReadReq accesses 1090system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.027456 # mshr miss rate for ReadReq accesses 1091system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.035934 # mshr miss rate for ReadReq accesses 1092system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.139055 # mshr miss rate for ReadReq accesses 1093system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.055325 # mshr miss rate for ReadReq accesses |
| 1091system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1092system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1094system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1095system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1093system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.846699 # mshr miss rate for UpgradeReq accesses 1094system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.846699 # mshr miss rate for UpgradeReq accesses 1095system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.905006 # mshr miss rate for SCUpgradeReq accesses 1096system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.905006 # mshr miss rate for SCUpgradeReq accesses | 1096system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.851603 # mshr miss rate for UpgradeReq accesses 1097system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.851603 # mshr miss rate for UpgradeReq accesses 1098system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.910132 # mshr miss rate for SCUpgradeReq accesses 1099system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.910132 # mshr miss rate for SCUpgradeReq accesses |
| 1097system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1098system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 1100system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1101system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 1099system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150831 # mshr miss rate for ReadExReq accesses 1100system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150831 # mshr miss rate for ReadExReq accesses 1101system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for demand accesses 1102system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for demand accesses 1103system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036722 # mshr miss rate for demand accesses 1104system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.142043 # mshr miss rate for demand accesses 1105system.cpu0.l2cache.demand_mshr_miss_rate::total 0.064643 # mshr miss rate for demand accesses 1106system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for overall accesses 1107system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for overall accesses 1108system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036722 # mshr miss rate for overall accesses 1109system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.142043 # mshr miss rate for overall accesses | 1102system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.156281 # mshr miss rate for ReadExReq accesses 1103system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.156281 # mshr miss rate for ReadExReq accesses 1104system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010429 # mshr miss rate for demand accesses 1105system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.027456 # mshr miss rate for demand accesses 1106system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.035934 # mshr miss rate for demand accesses 1107system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.145067 # mshr miss rate for demand accesses 1108system.cpu0.l2cache.demand_mshr_miss_rate::total 0.064926 # mshr miss rate for demand accesses 1109system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010429 # mshr miss rate for overall accesses 1110system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.027456 # mshr miss rate for overall accesses 1111system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.035934 # mshr miss rate for overall accesses 1112system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.145067 # mshr miss rate for overall accesses |
| 1110system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1113system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1111system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163393 # mshr miss rate for overall accesses 1112system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average ReadReq mshr miss latency 1113system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average ReadReq mshr miss latency 1114system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36764.725356 # average ReadReq mshr miss latency 1115system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23156.467008 # average ReadReq mshr miss latency 1116system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30110.716552 # average ReadReq mshr miss latency 1117system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205 # average HardPFReq mshr miss latency 1118system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55165.489205 # average HardPFReq mshr miss latency 1119system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17026.462281 # average UpgradeReq mshr miss latency 1120system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17026.462281 # average UpgradeReq mshr miss latency 1121system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13360.510885 # average SCUpgradeReq mshr miss latency 1122system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13360.510885 # average SCUpgradeReq mshr miss latency 1123system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 109500 # average SCUpgradeFailReq mshr miss latency 1124system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 109500 # average SCUpgradeFailReq mshr miss latency 1125system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 35947.135948 # average ReadExReq mshr miss latency 1126system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 35947.135948 # average ReadExReq mshr miss latency 1127system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average overall mshr miss latency 1128system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average overall mshr miss latency 1129system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36764.725356 # average overall mshr miss latency 1130system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27901.972022 # average overall mshr miss latency 1131system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31406.834216 # average overall mshr miss latency 1132system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average overall mshr miss latency 1133system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average overall mshr miss latency 1134system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36764.725356 # average overall mshr miss latency 1135system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27901.972022 # average overall mshr miss latency 1136system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205 # average overall mshr miss latency 1137system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45765.812883 # average overall mshr miss latency | 1114system.cpu0.l2cache.overall_mshr_miss_rate::total 0.164053 # mshr miss rate for overall accesses 1115system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29850.706714 # average ReadReq mshr miss latency 1116system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16070.247934 # average ReadReq mshr miss latency 1117system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39588.437872 # average ReadReq mshr miss latency 1118system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 24533.565603 # average ReadReq mshr miss latency 1119system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 32091.248642 # average ReadReq mshr miss latency 1120system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53498.080753 # average HardPFReq mshr miss latency 1121system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53498.080753 # average HardPFReq mshr miss latency 1122system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20212.609271 # average UpgradeReq mshr miss latency 1123system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20212.609271 # average UpgradeReq mshr miss latency 1124system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14702.299751 # average SCUpgradeReq mshr miss latency 1125system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14702.299751 # average SCUpgradeReq mshr miss latency 1126system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 116499 # average SCUpgradeFailReq mshr miss latency 1127system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 116499 # average SCUpgradeFailReq mshr miss latency 1128system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38767.974866 # average ReadExReq mshr miss latency 1129system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38767.974866 # average ReadExReq mshr miss latency 1130system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29850.706714 # average overall mshr miss latency 1131system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16070.247934 # average overall mshr miss latency 1132system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39588.437872 # average overall mshr miss latency 1133system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29885.177687 # average overall mshr miss latency 1134system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33619.682585 # average overall mshr miss latency 1135system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29850.706714 # average overall mshr miss latency 1136system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16070.247934 # average overall mshr miss latency 1137system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39588.437872 # average overall mshr miss latency 1138system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29885.177687 # average overall mshr miss latency 1139system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53498.080753 # average overall mshr miss latency 1140system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45630.907306 # average overall mshr miss latency |
| 1138system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1139system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1140system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1141system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1142system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1143system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1144system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1145system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1146system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1141system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1142system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1143system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1144system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1145system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1146system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1147system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1148system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1149system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1147system.cpu0.toL2Bus.trans_dist::ReadReq 2726808 # Transaction distribution 1148system.cpu0.toL2Bus.trans_dist::ReadResp 2669763 # Transaction distribution 1149system.cpu0.toL2Bus.trans_dist::WriteReq 28813 # Transaction distribution 1150system.cpu0.toL2Bus.trans_dist::WriteResp 28813 # Transaction distribution 1151system.cpu0.toL2Bus.trans_dist::Writeback 523100 # Transaction distribution 1152system.cpu0.toL2Bus.trans_dist::HardPFReq 388140 # Transaction distribution 1153system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1154system.cpu0.toL2Bus.trans_dist::UpgradeReq 64720 # Transaction distribution 1155system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42432 # Transaction distribution 1156system.cpu0.toL2Bus.trans_dist::UpgradeResp 88655 # Transaction distribution 1157system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution 1158system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 13 # Transaction distribution 1159system.cpu0.toL2Bus.trans_dist::ReadExReq 299964 # Transaction distribution 1160system.cpu0.toL2Bus.trans_dist::ReadExResp 286773 # Transaction distribution 1161system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3972081 # Packet count per connected master and slave (bytes) 1162system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2399294 # Packet count per connected master and slave (bytes) 1163system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11788 # Packet count per connected master and slave (bytes) 1164system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 172273 # Packet count per connected master and slave (bytes) 1165system.cpu0.toL2Bus.pkt_count::total 6555436 # Packet count per connected master and slave (bytes) 1166system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 127106560 # Cumulative packet size per connected master and slave (bytes) 1167system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 87442327 # Cumulative packet size per connected master and slave (bytes) 1168system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17780 # Cumulative packet size per connected master and slave (bytes) 1169system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 325388 # Cumulative packet size per connected master and slave (bytes) 1170system.cpu0.toL2Bus.pkt_size::total 214892055 # Cumulative packet size per connected master and slave (bytes) 1171system.cpu0.toL2Bus.snoops 732010 # Total snoops (count) 1172system.cpu0.toL2Bus.snoop_fanout::samples 4046250 # Request fanout histogram 1173system.cpu0.toL2Bus.snoop_fanout::mean 5.152317 # Request fanout histogram 1174system.cpu0.toL2Bus.snoop_fanout::stdev 0.359328 # Request fanout histogram | 1150system.cpu0.toL2Bus.trans_dist::ReadReq 2704309 # Transaction distribution 1151system.cpu0.toL2Bus.trans_dist::ReadResp 2644372 # Transaction distribution 1152system.cpu0.toL2Bus.trans_dist::WriteReq 19133 # Transaction distribution 1153system.cpu0.toL2Bus.trans_dist::WriteResp 19133 # Transaction distribution 1154system.cpu0.toL2Bus.trans_dist::Writeback 516061 # Transaction distribution 1155system.cpu0.toL2Bus.trans_dist::HardPFReq 357573 # Transaction distribution 1156system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36265 # Transaction distribution 1157system.cpu0.toL2Bus.trans_dist::UpgradeReq 65952 # Transaction distribution 1158system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43054 # Transaction distribution 1159system.cpu0.toL2Bus.trans_dist::UpgradeResp 89535 # Transaction distribution 1160system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution 1161system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution 1162system.cpu0.toL2Bus.trans_dist::ReadExReq 298181 # Transaction distribution 1163system.cpu0.toL2Bus.trans_dist::ReadExResp 284517 # Transaction distribution 1164system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3948091 # Packet count per connected master and slave (bytes) 1165system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2342949 # Packet count per connected master and slave (bytes) 1166system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11777 # Packet count per connected master and slave (bytes) 1167system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 172611 # Packet count per connected master and slave (bytes) 1168system.cpu0.toL2Bus.pkt_count::total 6475428 # Packet count per connected master and slave (bytes) 1169system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126338880 # Cumulative packet size per connected master and slave (bytes) 1170system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86633336 # Cumulative packet size per connected master and slave (bytes) 1171system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17628 # Cumulative packet size per connected master and slave (bytes) 1172system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 325620 # Cumulative packet size per connected master and slave (bytes) 1173system.cpu0.toL2Bus.pkt_size::total 213315464 # Cumulative packet size per connected master and slave (bytes) 1174system.cpu0.toL2Bus.snoops 705686 # Total snoops (count) 1175system.cpu0.toL2Bus.snoop_fanout::samples 3997625 # Request fanout histogram 1176system.cpu0.toL2Bus.snoop_fanout::mean 3.147566 # Request fanout histogram 1177system.cpu0.toL2Bus.snoop_fanout::stdev 0.354669 # Request fanout histogram |
| 1175system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1176system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1177system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1178system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 1178system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1179system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1180system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1181system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 1179system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1180system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1181system.cpu0.toL2Bus.snoop_fanout::5 3429939 84.77% 84.77% # Request fanout histogram 1182system.cpu0.toL2Bus.snoop_fanout::6 616311 15.23% 100.00% # Request fanout histogram | 1182system.cpu0.toL2Bus.snoop_fanout::3 3407711 85.24% 85.24% # Request fanout histogram 1183system.cpu0.toL2Bus.snoop_fanout::4 589914 14.76% 100.00% # Request fanout histogram |
| 1183system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1184system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1184system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1185system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1186system.cpu0.toL2Bus.snoop_fanout::total 4046250 # Request fanout histogram 1187system.cpu0.toL2Bus.reqLayer0.occupancy 2284841999 # Layer occupancy (ticks) | 1185system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1186system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1187system.cpu0.toL2Bus.snoop_fanout::total 3997625 # Request fanout histogram 1188system.cpu0.toL2Bus.reqLayer0.occupancy 2250942493 # Layer occupancy (ticks) |
| 1188system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1189system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1189system.cpu0.toL2Bus.snoopLayer0.occupancy 117254000 # Layer occupancy (ticks) | 1190system.cpu0.toL2Bus.snoopLayer0.occupancy 117029497 # Layer occupancy (ticks) |
| 1190system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1191system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1191system.cpu0.toL2Bus.respLayer0.occupancy 2984852953 # Layer occupancy (ticks) | 1192system.cpu0.toL2Bus.respLayer0.occupancy 2966538511 # Layer occupancy (ticks) |
| 1192system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1193system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1193system.cpu0.toL2Bus.respLayer1.occupancy 1241569539 # Layer occupancy (ticks) | 1194system.cpu0.toL2Bus.respLayer1.occupancy 1219549045 # Layer occupancy (ticks) |
| 1194system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1195system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1195system.cpu0.toL2Bus.respLayer2.occupancy 7347491 # Layer occupancy (ticks) | 1196system.cpu0.toL2Bus.respLayer2.occupancy 7373994 # Layer occupancy (ticks) |
| 1196system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1197system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1197system.cpu0.toL2Bus.respLayer3.occupancy 90940738 # Layer occupancy (ticks) | 1198system.cpu0.toL2Bus.respLayer3.occupancy 91216246 # Layer occupancy (ticks) |
| 1198system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1199system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1199system.cpu1.branchPred.lookups 4088735 # Number of BP lookups 1200system.cpu1.branchPred.condPredicted 2366310 # Number of conditional branches predicted 1201system.cpu1.branchPred.condIncorrect 253216 # Number of conditional branches incorrect 1202system.cpu1.branchPred.BTBLookups 2663045 # Number of BTB lookups 1203system.cpu1.branchPred.BTBHits 1651600 # Number of BTB hits | 1200system.cpu1.branchPred.lookups 18670420 # Number of BP lookups 1201system.cpu1.branchPred.condPredicted 6078179 # Number of conditional branches predicted 1202system.cpu1.branchPred.condIncorrect 807720 # Number of conditional branches incorrect 1203system.cpu1.branchPred.BTBLookups 9612678 # Number of BTB lookups 1204system.cpu1.branchPred.BTBHits 6998038 # Number of BTB hits |
| 1204system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1205system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1205system.cpu1.branchPred.BTBHitPct 62.019230 # BTB Hit Percentage 1206system.cpu1.branchPred.usedRAS 809555 # Number of times the RAS was used to get a target. 1207system.cpu1.branchPred.RASInCorrect 58673 # Number of incorrect RAS predictions. | 1206system.cpu1.branchPred.BTBHitPct 72.800088 # BTB Hit Percentage 1207system.cpu1.branchPred.usedRAS 8300224 # Number of times the RAS was used to get a target. 1208system.cpu1.branchPred.RASInCorrect 592338 # Number of incorrect RAS predictions. |
| 1208system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1209system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1210system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1211system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1212system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1213system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1214system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1215system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1229system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1230system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1231system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1232system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1233system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1234system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1235system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1236system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1209system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1210system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1211system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1212system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1213system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1214system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1215system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1216system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1230system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1231system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1232system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1233system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1234system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1235system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1236system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1237system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1237system.cpu1.dtb.walker.walks 25571 # Table walker walks requested 1238system.cpu1.dtb.walker.walksShort 25571 # Table walker walks initiated with short descriptors 1239system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18521 # Level at which table walker walks with short descriptors terminate 1240system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7050 # Level at which table walker walks with short descriptors terminate 1241system.cpu1.dtb.walker.walkWaitTime::samples 25571 # Table walker wait (enqueue to first request) latency 1242system.cpu1.dtb.walker.walkWaitTime::0 25571 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1243system.cpu1.dtb.walker.walkWaitTime::total 25571 # Table walker wait (enqueue to first request) latency 1244system.cpu1.dtb.walker.walkCompletionTime::samples 2708 # Table walker service (enqueue to completion) latency 1245system.cpu1.dtb.walker.walkCompletionTime::mean 8701.256278 # Table walker service (enqueue to completion) latency 1246system.cpu1.dtb.walker.walkCompletionTime::gmean 7631.681902 # Table walker service (enqueue to completion) latency 1247system.cpu1.dtb.walker.walkCompletionTime::stdev 5745.938863 # Table walker service (enqueue to completion) latency 1248system.cpu1.dtb.walker.walkCompletionTime::0-8191 2093 77.29% 77.29% # Table walker service (enqueue to completion) latency 1249system.cpu1.dtb.walker.walkCompletionTime::8192-16383 481 17.76% 95.05% # Table walker service (enqueue to completion) latency | 1238system.cpu1.dtb.walker.walks 26198 # Table walker walks requested 1239system.cpu1.dtb.walker.walksShort 26198 # Table walker walks initiated with short descriptors 1240system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19047 # Level at which table walker walks with short descriptors terminate 1241system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7151 # Level at which table walker walks with short descriptors terminate 1242system.cpu1.dtb.walker.walkWaitTime::samples 26198 # Table walker wait (enqueue to first request) latency 1243system.cpu1.dtb.walker.walkWaitTime::0 26198 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1244system.cpu1.dtb.walker.walkWaitTime::total 26198 # Table walker wait (enqueue to first request) latency 1245system.cpu1.dtb.walker.walkCompletionTime::samples 2710 # Table walker service (enqueue to completion) latency 1246system.cpu1.dtb.walker.walkCompletionTime::mean 9322.699631 # Table walker service (enqueue to completion) latency 1247system.cpu1.dtb.walker.walkCompletionTime::gmean 8294.308784 # Table walker service (enqueue to completion) latency 1248system.cpu1.dtb.walker.walkCompletionTime::stdev 5681.860876 # Table walker service (enqueue to completion) latency 1249system.cpu1.dtb.walker.walkCompletionTime::0-8191 1066 39.34% 39.34% # Table walker service (enqueue to completion) latency 1250system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1510 55.72% 95.06% # Table walker service (enqueue to completion) latency |
| 1250system.cpu1.dtb.walker.walkCompletionTime::16384-24575 65 2.40% 97.45% # Table walker service (enqueue to completion) latency | 1251system.cpu1.dtb.walker.walkCompletionTime::16384-24575 65 2.40% 97.45% # Table walker service (enqueue to completion) latency |
| 1251system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.07% 99.52% # Table walker service (enqueue to completion) latency 1252system.cpu1.dtb.walker.walkCompletionTime::40960-49151 9 0.33% 99.85% # Table walker service (enqueue to completion) latency 1253system.cpu1.dtb.walker.walkCompletionTime::81920-90111 4 0.15% 100.00% # Table walker service (enqueue to completion) latency 1254system.cpu1.dtb.walker.walkCompletionTime::total 2708 # Table walker service (enqueue to completion) latency 1255system.cpu1.dtb.walker.walksPending::samples 1108722264 # Table walker pending requests distribution 1256system.cpu1.dtb.walker.walksPending::0 1108722264 100.00% 100.00% # Table walker pending requests distribution 1257system.cpu1.dtb.walker.walksPending::total 1108722264 # Table walker pending requests distribution 1258system.cpu1.dtb.walker.walkPageSizes::4K 1997 73.74% 73.74% # Table walker page sizes translated 1259system.cpu1.dtb.walker.walkPageSizes::1M 711 26.26% 100.00% # Table walker page sizes translated 1260system.cpu1.dtb.walker.walkPageSizes::total 2708 # Table walker page sizes translated 1261system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 25571 # Table walker requests started/completed, data/inst | 1252system.cpu1.dtb.walker.walkCompletionTime::24576-32767 58 2.14% 99.59% # Table walker service (enqueue to completion) latency 1253system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.67% # Table walker service (enqueue to completion) latency 1254system.cpu1.dtb.walker.walkCompletionTime::40960-49151 6 0.22% 99.89% # Table walker service (enqueue to completion) latency 1255system.cpu1.dtb.walker.walkCompletionTime::90112-98303 3 0.11% 100.00% # Table walker service (enqueue to completion) latency 1256system.cpu1.dtb.walker.walkCompletionTime::total 2710 # Table walker service (enqueue to completion) latency 1257system.cpu1.dtb.walker.walksPending::samples 1205143764 # Table walker pending requests distribution 1258system.cpu1.dtb.walker.walksPending::0 1205143764 100.00% 100.00% # Table walker pending requests distribution 1259system.cpu1.dtb.walker.walksPending::total 1205143764 # Table walker pending requests distribution 1260system.cpu1.dtb.walker.walkPageSizes::4K 2001 73.84% 73.84% # Table walker page sizes translated 1261system.cpu1.dtb.walker.walkPageSizes::1M 709 26.16% 100.00% # Table walker page sizes translated 1262system.cpu1.dtb.walker.walkPageSizes::total 2710 # Table walker page sizes translated 1263system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26198 # Table walker requests started/completed, data/inst |
| 1262system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 1264system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 1263system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 25571 # Table walker requests started/completed, data/inst 1264system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2708 # Table walker requests started/completed, data/inst | 1265system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26198 # Table walker requests started/completed, data/inst 1266system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2710 # Table walker requests started/completed, data/inst |
| 1265system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 1267system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 1266system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2708 # Table walker requests started/completed, data/inst 1267system.cpu1.dtb.walker.walkRequestOrigin::total 28279 # Table walker requests started/completed, data/inst | 1268system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2710 # Table walker requests started/completed, data/inst 1269system.cpu1.dtb.walker.walkRequestOrigin::total 28908 # Table walker requests started/completed, data/inst |
| 1268system.cpu1.dtb.inst_hits 0 # ITB inst hits 1269system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1270system.cpu1.dtb.inst_hits 0 # ITB inst hits 1271system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1270system.cpu1.dtb.read_hits 4075725 # DTB read hits 1271system.cpu1.dtb.read_misses 23546 # DTB read misses 1272system.cpu1.dtb.write_hits 3346999 # DTB write hits 1273system.cpu1.dtb.write_misses 2025 # DTB write misses | 1272system.cpu1.dtb.read_hits 10899944 # DTB read hits 1273system.cpu1.dtb.read_misses 24664 # DTB read misses 1274system.cpu1.dtb.write_hits 6857896 # DTB write hits 1275system.cpu1.dtb.write_misses 1534 # DTB write misses |
| 1274system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1275system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1276system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1277system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1276system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1277system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1278system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1279system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1278system.cpu1.dtb.flush_entries 2069 # Number of entries that have been flushed from TLB 1279system.cpu1.dtb.align_faults 121 # Number of TLB faults due to alignment restrictions 1280system.cpu1.dtb.prefetch_faults 325 # Number of TLB faults due to prefetch | 1280system.cpu1.dtb.flush_entries 2060 # Number of entries that have been flushed from TLB 1281system.cpu1.dtb.align_faults 145 # Number of TLB faults due to alignment restrictions 1282system.cpu1.dtb.prefetch_faults 340 # Number of TLB faults due to prefetch |
| 1281system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1282system.cpu1.dtb.perms_faults 279 # Number of TLB faults due to permissions restrictions | 1283system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1284system.cpu1.dtb.perms_faults 279 # Number of TLB faults due to permissions restrictions |
| 1283system.cpu1.dtb.read_accesses 4099271 # DTB read accesses 1284system.cpu1.dtb.write_accesses 3349024 # DTB write accesses | 1285system.cpu1.dtb.read_accesses 10924608 # DTB read accesses 1286system.cpu1.dtb.write_accesses 6859430 # DTB write accesses |
| 1285system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1287system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1286system.cpu1.dtb.hits 7422724 # DTB hits 1287system.cpu1.dtb.misses 25571 # DTB misses 1288system.cpu1.dtb.accesses 7448295 # DTB accesses | 1288system.cpu1.dtb.hits 17757840 # DTB hits 1289system.cpu1.dtb.misses 26198 # DTB misses 1290system.cpu1.dtb.accesses 17784038 # DTB accesses |
| 1289system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1290system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1291system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1292system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1293system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1294system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1295system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1296system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1310system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1311system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1312system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1313system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1314system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1315system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1316system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1317system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1291system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1292system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1293system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1294system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1295system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1296system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1297system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1298system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1312system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1313system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1314system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1315system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1316system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1317system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1318system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1319system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1318system.cpu1.itb.walker.walks 2243 # Table walker walks requested 1319system.cpu1.itb.walker.walksShort 2243 # Table walker walks initiated with short descriptors 1320system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate 1321system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2062 # Level at which table walker walks with short descriptors terminate 1322system.cpu1.itb.walker.walkWaitTime::samples 2243 # Table walker wait (enqueue to first request) latency 1323system.cpu1.itb.walker.walkWaitTime::0 2243 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1324system.cpu1.itb.walker.walkWaitTime::total 2243 # Table walker wait (enqueue to first request) latency 1325system.cpu1.itb.walker.walkCompletionTime::samples 1122 # Table walker service (enqueue to completion) latency 1326system.cpu1.itb.walker.walkCompletionTime::mean 8831.106061 # Table walker service (enqueue to completion) latency 1327system.cpu1.itb.walker.walkCompletionTime::gmean 7825.020839 # Table walker service (enqueue to completion) latency 1328system.cpu1.itb.walker.walkCompletionTime::stdev 4777.823788 # Table walker service (enqueue to completion) latency 1329system.cpu1.itb.walker.walkCompletionTime::0-4095 160 14.26% 14.26% # Table walker service (enqueue to completion) latency 1330system.cpu1.itb.walker.walkCompletionTime::4096-8191 676 60.25% 74.51% # Table walker service (enqueue to completion) latency 1331system.cpu1.itb.walker.walkCompletionTime::8192-12287 3 0.27% 74.78% # Table walker service (enqueue to completion) latency 1332system.cpu1.itb.walker.walkCompletionTime::12288-16383 248 22.10% 96.88% # Table walker service (enqueue to completion) latency 1333system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 96.97% # Table walker service (enqueue to completion) latency 1334system.cpu1.itb.walker.walkCompletionTime::24576-28671 13 1.16% 98.13% # Table walker service (enqueue to completion) latency 1335system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.69% 99.82% # Table walker service (enqueue to completion) latency 1336system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.91% # Table walker service (enqueue to completion) latency 1337system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 100.00% # Table walker service (enqueue to completion) latency 1338system.cpu1.itb.walker.walkCompletionTime::total 1122 # Table walker service (enqueue to completion) latency 1339system.cpu1.itb.walker.walksPending::samples 1108154264 # Table walker pending requests distribution 1340system.cpu1.itb.walker.walksPending::0 1108154264 100.00% 100.00% # Table walker pending requests distribution 1341system.cpu1.itb.walker.walksPending::total 1108154264 # Table walker pending requests distribution 1342system.cpu1.itb.walker.walkPageSizes::4K 954 85.03% 85.03% # Table walker page sizes translated 1343system.cpu1.itb.walker.walkPageSizes::1M 168 14.97% 100.00% # Table walker page sizes translated 1344system.cpu1.itb.walker.walkPageSizes::total 1122 # Table walker page sizes translated | 1320system.cpu1.itb.walker.walks 2253 # Table walker walks requested 1321system.cpu1.itb.walker.walksShort 2253 # Table walker walks initiated with short descriptors 1322system.cpu1.itb.walker.walksShortTerminationLevel::Level1 177 # Level at which table walker walks with short descriptors terminate 1323system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2076 # Level at which table walker walks with short descriptors terminate 1324system.cpu1.itb.walker.walkWaitTime::samples 2253 # Table walker wait (enqueue to first request) latency 1325system.cpu1.itb.walker.walkWaitTime::0 2253 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1326system.cpu1.itb.walker.walkWaitTime::total 2253 # Table walker wait (enqueue to first request) latency 1327system.cpu1.itb.walker.walkCompletionTime::samples 1119 # Table walker service (enqueue to completion) latency 1328system.cpu1.itb.walker.walkCompletionTime::mean 9627.345845 # Table walker service (enqueue to completion) latency 1329system.cpu1.itb.walker.walkCompletionTime::gmean 8644.762201 # Table walker service (enqueue to completion) latency 1330system.cpu1.itb.walker.walkCompletionTime::stdev 4978.900312 # Table walker service (enqueue to completion) latency 1331system.cpu1.itb.walker.walkCompletionTime::0-4095 184 16.44% 16.44% # Table walker service (enqueue to completion) latency 1332system.cpu1.itb.walker.walkCompletionTime::4096-8191 161 14.39% 30.83% # Table walker service (enqueue to completion) latency 1333system.cpu1.itb.walker.walkCompletionTime::8192-12287 501 44.77% 75.60% # Table walker service (enqueue to completion) latency 1334system.cpu1.itb.walker.walkCompletionTime::12288-16383 236 21.09% 96.69% # Table walker service (enqueue to completion) latency 1335system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 96.78% # Table walker service (enqueue to completion) latency 1336system.cpu1.itb.walker.walkCompletionTime::24576-28671 13 1.16% 97.94% # Table walker service (enqueue to completion) latency 1337system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.88% 99.82% # Table walker service (enqueue to completion) latency 1338system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 100.00% # Table walker service (enqueue to completion) latency 1339system.cpu1.itb.walker.walkCompletionTime::total 1119 # Table walker service (enqueue to completion) latency 1340system.cpu1.itb.walker.walksPending::samples 1204569264 # Table walker pending requests distribution 1341system.cpu1.itb.walker.walksPending::0 1204569264 100.00% 100.00% # Table walker pending requests distribution 1342system.cpu1.itb.walker.walksPending::total 1204569264 # Table walker pending requests distribution 1343system.cpu1.itb.walker.walkPageSizes::4K 955 85.34% 85.34% # Table walker page sizes translated 1344system.cpu1.itb.walker.walkPageSizes::1M 164 14.66% 100.00% # Table walker page sizes translated 1345system.cpu1.itb.walker.walkPageSizes::total 1119 # Table walker page sizes translated |
| 1345system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 1346system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 1346system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2243 # Table walker requests started/completed, data/inst 1347system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2243 # Table walker requests started/completed, data/inst | 1347system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2253 # Table walker requests started/completed, data/inst 1348system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2253 # Table walker requests started/completed, data/inst |
| 1348system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 1349system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 1349system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1122 # Table walker requests started/completed, data/inst 1350system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1122 # Table walker requests started/completed, data/inst 1351system.cpu1.itb.walker.walkRequestOrigin::total 3365 # Table walker requests started/completed, data/inst 1352system.cpu1.itb.inst_hits 7772051 # ITB inst hits 1353system.cpu1.itb.inst_misses 2243 # ITB inst misses | 1350system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1119 # Table walker requests started/completed, data/inst 1351system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1119 # Table walker requests started/completed, data/inst 1352system.cpu1.itb.walker.walkRequestOrigin::total 3372 # Table walker requests started/completed, data/inst 1353system.cpu1.itb.inst_hits 39818327 # ITB inst hits 1354system.cpu1.itb.inst_misses 2253 # ITB inst misses |
| 1354system.cpu1.itb.read_hits 0 # DTB read hits 1355system.cpu1.itb.read_misses 0 # DTB read misses 1356system.cpu1.itb.write_hits 0 # DTB write hits 1357system.cpu1.itb.write_misses 0 # DTB write misses 1358system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1359system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1360system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1361system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1355system.cpu1.itb.read_hits 0 # DTB read hits 1356system.cpu1.itb.read_misses 0 # DTB read misses 1357system.cpu1.itb.write_hits 0 # DTB write hits 1358system.cpu1.itb.write_misses 0 # DTB write misses 1359system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1360system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1361system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1362system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1362system.cpu1.itb.flush_entries 1160 # Number of entries that have been flushed from TLB | 1363system.cpu1.itb.flush_entries 1157 # Number of entries that have been flushed from TLB |
| 1363system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1364system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1365system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1364system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1365system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1366system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1366system.cpu1.itb.perms_faults 1845 # Number of TLB faults due to permissions restrictions | 1367system.cpu1.itb.perms_faults 1840 # Number of TLB faults due to permissions restrictions |
| 1367system.cpu1.itb.read_accesses 0 # DTB read accesses 1368system.cpu1.itb.write_accesses 0 # DTB write accesses | 1368system.cpu1.itb.read_accesses 0 # DTB read accesses 1369system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1369system.cpu1.itb.inst_accesses 7774294 # ITB inst accesses 1370system.cpu1.itb.hits 7772051 # DTB hits 1371system.cpu1.itb.misses 2243 # DTB misses 1372system.cpu1.itb.accesses 7774294 # DTB accesses 1373system.cpu1.numCycles 42246986 # number of cpu cycles simulated | 1370system.cpu1.itb.inst_accesses 39820580 # ITB inst accesses 1371system.cpu1.itb.hits 39818327 # DTB hits 1372system.cpu1.itb.misses 2253 # DTB misses 1373system.cpu1.itb.accesses 39820580 # DTB accesses 1374system.cpu1.numCycles 115094455 # number of cpu cycles simulated |
| 1374system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1375system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1375system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1376system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1376system.cpu1.committedInsts 15956294 # Number of instructions committed 1377system.cpu1.committedOps 19510473 # Number of ops (including micro ops) committed 1378system.cpu1.discardedOps 1491389 # Number of ops (including micro ops) which were discarded before commit 1379system.cpu1.numFetchSuspends 2792 # Number of times Execute suspended instruction fetching 1380system.cpu1.quiesceCycles 5648821854 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1381system.cpu1.cpi 2.647669 # CPI: cycles per instruction 1382system.cpu1.ipc 0.377691 # IPC: instructions per cycle | 1377system.cpu1.committedInsts 46307622 # Number of instructions committed 1378system.cpu1.committedOps 56662250 # Number of ops (including micro ops) committed 1379system.cpu1.discardedOps 4905736 # Number of ops (including micro ops) which were discarded before commit 1380system.cpu1.numFetchSuspends 2805 # Number of times Execute suspended instruction fetching 1381system.cpu1.quiesceCycles 5576292649 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1382system.cpu1.cpi 2.485432 # CPI: cycles per instruction 1383system.cpu1.ipc 0.402345 # IPC: instructions per cycle |
| 1383system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1384system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1384system.cpu1.kern.inst.quiesce 2795 # number of quiesce instructions executed 1385system.cpu1.tickCycles 30354295 # Number of cycles that the object actually ticked 1386system.cpu1.idleCycles 11892691 # Total number of cycles that the object has spent stopped 1387system.cpu1.dcache.tags.replacements 187758 # number of replacements 1388system.cpu1.dcache.tags.tagsinuse 478.493571 # Cycle average of tags in use 1389system.cpu1.dcache.tags.total_refs 7034054 # Total number of references to valid blocks. 1390system.cpu1.dcache.tags.sampled_refs 188124 # Sample count of references to valid blocks. 1391system.cpu1.dcache.tags.avg_refs 37.390519 # Average number of references to valid blocks. 1392system.cpu1.dcache.tags.warmup_cycle 108317904000 # Cycle when the warmup percentage was hit. 1393system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.493571 # Average occupied blocks per requestor 1394system.cpu1.dcache.tags.occ_percent::cpu1.data 0.934558 # Average percentage of cache occupancy 1395system.cpu1.dcache.tags.occ_percent::total 0.934558 # Average percentage of cache occupancy 1396system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id 1397system.cpu1.dcache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id 1398system.cpu1.dcache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id 1399system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id 1400system.cpu1.dcache.tags.tag_accesses 14914460 # Number of tag accesses 1401system.cpu1.dcache.tags.data_accesses 14914460 # Number of data accesses 1402system.cpu1.dcache.ReadReq_hits::cpu1.data 3762812 # number of ReadReq hits 1403system.cpu1.dcache.ReadReq_hits::total 3762812 # number of ReadReq hits 1404system.cpu1.dcache.WriteReq_hits::cpu1.data 3070723 # number of WriteReq hits 1405system.cpu1.dcache.WriteReq_hits::total 3070723 # number of WriteReq hits 1406system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 89288 # number of LoadLockedReq hits 1407system.cpu1.dcache.LoadLockedReq_hits::total 89288 # number of LoadLockedReq hits 1408system.cpu1.dcache.StoreCondReq_hits::cpu1.data 69262 # number of StoreCondReq hits 1409system.cpu1.dcache.StoreCondReq_hits::total 69262 # number of StoreCondReq hits 1410system.cpu1.dcache.demand_hits::cpu1.data 6833535 # number of demand (read+write) hits 1411system.cpu1.dcache.demand_hits::total 6833535 # number of demand (read+write) hits 1412system.cpu1.dcache.overall_hits::cpu1.data 6833535 # number of overall hits 1413system.cpu1.dcache.overall_hits::total 6833535 # number of overall hits 1414system.cpu1.dcache.ReadReq_misses::cpu1.data 181434 # number of ReadReq misses 1415system.cpu1.dcache.ReadReq_misses::total 181434 # number of ReadReq misses 1416system.cpu1.dcache.WriteReq_misses::cpu1.data 139542 # number of WriteReq misses 1417system.cpu1.dcache.WriteReq_misses::total 139542 # number of WriteReq misses 1418system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5058 # number of LoadLockedReq misses 1419system.cpu1.dcache.LoadLockedReq_misses::total 5058 # number of LoadLockedReq misses 1420system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23425 # number of StoreCondReq misses 1421system.cpu1.dcache.StoreCondReq_misses::total 23425 # number of StoreCondReq misses 1422system.cpu1.dcache.demand_misses::cpu1.data 320976 # number of demand (read+write) misses 1423system.cpu1.dcache.demand_misses::total 320976 # number of demand (read+write) misses 1424system.cpu1.dcache.overall_misses::cpu1.data 320976 # number of overall misses 1425system.cpu1.dcache.overall_misses::total 320976 # number of overall misses 1426system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2698134351 # number of ReadReq miss cycles 1427system.cpu1.dcache.ReadReq_miss_latency::total 2698134351 # number of ReadReq miss cycles 1428system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3673411367 # number of WriteReq miss cycles 1429system.cpu1.dcache.WriteReq_miss_latency::total 3673411367 # number of WriteReq miss cycles 1430system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 91654251 # number of LoadLockedReq miss cycles 1431system.cpu1.dcache.LoadLockedReq_miss_latency::total 91654251 # number of LoadLockedReq miss cycles 1432system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 540931813 # number of StoreCondReq miss cycles 1433system.cpu1.dcache.StoreCondReq_miss_latency::total 540931813 # number of StoreCondReq miss cycles 1434system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 185500 # number of StoreCondFailReq miss cycles 1435system.cpu1.dcache.StoreCondFailReq_miss_latency::total 185500 # number of StoreCondFailReq miss cycles 1436system.cpu1.dcache.demand_miss_latency::cpu1.data 6371545718 # number of demand (read+write) miss cycles 1437system.cpu1.dcache.demand_miss_latency::total 6371545718 # number of demand (read+write) miss cycles 1438system.cpu1.dcache.overall_miss_latency::cpu1.data 6371545718 # number of overall miss cycles 1439system.cpu1.dcache.overall_miss_latency::total 6371545718 # number of overall miss cycles 1440system.cpu1.dcache.ReadReq_accesses::cpu1.data 3944246 # number of ReadReq accesses(hits+misses) 1441system.cpu1.dcache.ReadReq_accesses::total 3944246 # number of ReadReq accesses(hits+misses) 1442system.cpu1.dcache.WriteReq_accesses::cpu1.data 3210265 # number of WriteReq accesses(hits+misses) 1443system.cpu1.dcache.WriteReq_accesses::total 3210265 # number of WriteReq accesses(hits+misses) 1444system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 94346 # number of LoadLockedReq accesses(hits+misses) 1445system.cpu1.dcache.LoadLockedReq_accesses::total 94346 # number of LoadLockedReq accesses(hits+misses) 1446system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92687 # number of StoreCondReq accesses(hits+misses) 1447system.cpu1.dcache.StoreCondReq_accesses::total 92687 # number of StoreCondReq accesses(hits+misses) 1448system.cpu1.dcache.demand_accesses::cpu1.data 7154511 # number of demand (read+write) accesses 1449system.cpu1.dcache.demand_accesses::total 7154511 # number of demand (read+write) accesses 1450system.cpu1.dcache.overall_accesses::cpu1.data 7154511 # number of overall (read+write) accesses 1451system.cpu1.dcache.overall_accesses::total 7154511 # number of overall (read+write) accesses 1452system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.046000 # miss rate for ReadReq accesses 1453system.cpu1.dcache.ReadReq_miss_rate::total 0.046000 # miss rate for ReadReq accesses 1454system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.043467 # miss rate for WriteReq accesses 1455system.cpu1.dcache.WriteReq_miss_rate::total 0.043467 # miss rate for WriteReq accesses 1456system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.053611 # miss rate for LoadLockedReq accesses 1457system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.053611 # miss rate for LoadLockedReq accesses 1458system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.252732 # miss rate for StoreCondReq accesses 1459system.cpu1.dcache.StoreCondReq_miss_rate::total 0.252732 # miss rate for StoreCondReq accesses 1460system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044863 # miss rate for demand accesses 1461system.cpu1.dcache.demand_miss_rate::total 0.044863 # miss rate for demand accesses 1462system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044863 # miss rate for overall accesses 1463system.cpu1.dcache.overall_miss_rate::total 0.044863 # miss rate for overall accesses 1464system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14871.161695 # average ReadReq miss latency 1465system.cpu1.dcache.ReadReq_avg_miss_latency::total 14871.161695 # average ReadReq miss latency 1466system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26324.772233 # average WriteReq miss latency 1467system.cpu1.dcache.WriteReq_avg_miss_latency::total 26324.772233 # average WriteReq miss latency 1468system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18120.650652 # average LoadLockedReq miss latency 1469system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18120.650652 # average LoadLockedReq miss latency 1470system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23092.073127 # average StoreCondReq miss latency 1471system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23092.073127 # average StoreCondReq miss latency | 1385system.cpu1.kern.inst.quiesce 2806 # number of quiesce instructions executed 1386system.cpu1.tickCycles 98408596 # Number of cycles that the object actually ticked 1387system.cpu1.idleCycles 16685859 # Total number of cycles that the object has spent stopped 1388system.cpu1.dcache.tags.replacements 195662 # number of replacements 1389system.cpu1.dcache.tags.tagsinuse 474.092793 # Cycle average of tags in use 1390system.cpu1.dcache.tags.total_refs 17323078 # Total number of references to valid blocks. 1391system.cpu1.dcache.tags.sampled_refs 195999 # Sample count of references to valid blocks. 1392system.cpu1.dcache.tags.avg_refs 88.383502 # Average number of references to valid blocks. 1393system.cpu1.dcache.tags.warmup_cycle 90082708500 # Cycle when the warmup percentage was hit. 1394system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.092793 # Average occupied blocks per requestor 1395system.cpu1.dcache.tags.occ_percent::cpu1.data 0.925962 # Average percentage of cache occupancy 1396system.cpu1.dcache.tags.occ_percent::total 0.925962 # Average percentage of cache occupancy 1397system.cpu1.dcache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id 1398system.cpu1.dcache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id 1399system.cpu1.dcache.tags.age_task_id_blocks_1024::3 88 # Occupied blocks per task id 1400system.cpu1.dcache.tags.occ_task_id_percent::1024 0.658203 # Percentage of cache occupancy per task id 1401system.cpu1.dcache.tags.tag_accesses 35540406 # Number of tag accesses 1402system.cpu1.dcache.tags.data_accesses 35540406 # Number of data accesses 1403system.cpu1.dcache.ReadReq_hits::cpu1.data 10562839 # number of ReadReq hits 1404system.cpu1.dcache.ReadReq_hits::total 10562839 # number of ReadReq hits 1405system.cpu1.dcache.WriteReq_hits::cpu1.data 6561699 # number of WriteReq hits 1406system.cpu1.dcache.WriteReq_hits::total 6561699 # number of WriteReq hits 1407system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 92378 # number of LoadLockedReq hits 1408system.cpu1.dcache.LoadLockedReq_hits::total 92378 # number of LoadLockedReq hits 1409system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71754 # number of StoreCondReq hits 1410system.cpu1.dcache.StoreCondReq_hits::total 71754 # number of StoreCondReq hits 1411system.cpu1.dcache.demand_hits::cpu1.data 17124538 # number of demand (read+write) hits 1412system.cpu1.dcache.demand_hits::total 17124538 # number of demand (read+write) hits 1413system.cpu1.dcache.overall_hits::cpu1.data 17124538 # number of overall hits 1414system.cpu1.dcache.overall_hits::total 17124538 # number of overall hits 1415system.cpu1.dcache.ReadReq_misses::cpu1.data 188265 # number of ReadReq misses 1416system.cpu1.dcache.ReadReq_misses::total 188265 # number of ReadReq misses 1417system.cpu1.dcache.WriteReq_misses::cpu1.data 144615 # number of WriteReq misses 1418system.cpu1.dcache.WriteReq_misses::total 144615 # number of WriteReq misses 1419system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4906 # number of LoadLockedReq misses 1420system.cpu1.dcache.LoadLockedReq_misses::total 4906 # number of LoadLockedReq misses 1421system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23743 # number of StoreCondReq misses 1422system.cpu1.dcache.StoreCondReq_misses::total 23743 # number of StoreCondReq misses 1423system.cpu1.dcache.demand_misses::cpu1.data 332880 # number of demand (read+write) misses 1424system.cpu1.dcache.demand_misses::total 332880 # number of demand (read+write) misses 1425system.cpu1.dcache.overall_misses::cpu1.data 332880 # number of overall misses 1426system.cpu1.dcache.overall_misses::total 332880 # number of overall misses 1427system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2782453534 # number of ReadReq miss cycles 1428system.cpu1.dcache.ReadReq_miss_latency::total 2782453534 # number of ReadReq miss cycles 1429system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3892497330 # number of WriteReq miss cycles 1430system.cpu1.dcache.WriteReq_miss_latency::total 3892497330 # number of WriteReq miss cycles 1431system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 87637747 # number of LoadLockedReq miss cycles 1432system.cpu1.dcache.LoadLockedReq_miss_latency::total 87637747 # number of LoadLockedReq miss cycles 1433system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 559501111 # number of StoreCondReq miss cycles 1434system.cpu1.dcache.StoreCondReq_miss_latency::total 559501111 # number of StoreCondReq miss cycles 1435system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 370500 # number of StoreCondFailReq miss cycles 1436system.cpu1.dcache.StoreCondFailReq_miss_latency::total 370500 # number of StoreCondFailReq miss cycles 1437system.cpu1.dcache.demand_miss_latency::cpu1.data 6674950864 # number of demand (read+write) miss cycles 1438system.cpu1.dcache.demand_miss_latency::total 6674950864 # number of demand (read+write) miss cycles 1439system.cpu1.dcache.overall_miss_latency::cpu1.data 6674950864 # number of overall miss cycles 1440system.cpu1.dcache.overall_miss_latency::total 6674950864 # number of overall miss cycles 1441system.cpu1.dcache.ReadReq_accesses::cpu1.data 10751104 # number of ReadReq accesses(hits+misses) 1442system.cpu1.dcache.ReadReq_accesses::total 10751104 # number of ReadReq accesses(hits+misses) 1443system.cpu1.dcache.WriteReq_accesses::cpu1.data 6706314 # number of WriteReq accesses(hits+misses) 1444system.cpu1.dcache.WriteReq_accesses::total 6706314 # number of WriteReq accesses(hits+misses) 1445system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97284 # number of LoadLockedReq accesses(hits+misses) 1446system.cpu1.dcache.LoadLockedReq_accesses::total 97284 # number of LoadLockedReq accesses(hits+misses) 1447system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95497 # number of StoreCondReq accesses(hits+misses) 1448system.cpu1.dcache.StoreCondReq_accesses::total 95497 # number of StoreCondReq accesses(hits+misses) 1449system.cpu1.dcache.demand_accesses::cpu1.data 17457418 # number of demand (read+write) accesses 1450system.cpu1.dcache.demand_accesses::total 17457418 # number of demand (read+write) accesses 1451system.cpu1.dcache.overall_accesses::cpu1.data 17457418 # number of overall (read+write) accesses 1452system.cpu1.dcache.overall_accesses::total 17457418 # number of overall (read+write) accesses 1453system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.017511 # miss rate for ReadReq accesses 1454system.cpu1.dcache.ReadReq_miss_rate::total 0.017511 # miss rate for ReadReq accesses 1455system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021564 # miss rate for WriteReq accesses 1456system.cpu1.dcache.WriteReq_miss_rate::total 0.021564 # miss rate for WriteReq accesses 1457system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.050430 # miss rate for LoadLockedReq accesses 1458system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.050430 # miss rate for LoadLockedReq accesses 1459system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248626 # miss rate for StoreCondReq accesses 1460system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248626 # miss rate for StoreCondReq accesses 1461system.cpu1.dcache.demand_miss_rate::cpu1.data 0.019068 # miss rate for demand accesses 1462system.cpu1.dcache.demand_miss_rate::total 0.019068 # miss rate for demand accesses 1463system.cpu1.dcache.overall_miss_rate::cpu1.data 0.019068 # miss rate for overall accesses 1464system.cpu1.dcache.overall_miss_rate::total 0.019068 # miss rate for overall accesses 1465system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14779.452017 # average ReadReq miss latency 1466system.cpu1.dcache.ReadReq_avg_miss_latency::total 14779.452017 # average ReadReq miss latency 1467system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26916.276527 # average WriteReq miss latency 1468system.cpu1.dcache.WriteReq_avg_miss_latency::total 26916.276527 # average WriteReq miss latency 1469system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17863.380962 # average LoadLockedReq miss latency 1470system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17863.380962 # average LoadLockedReq miss latency 1471system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23564.886956 # average StoreCondReq miss latency 1472system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23564.886956 # average StoreCondReq miss latency |
| 1472system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1473system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 1473system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1474system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1474system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19850.536233 # average overall miss latency 1475system.cpu1.dcache.demand_avg_miss_latency::total 19850.536233 # average overall miss latency 1476system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19850.536233 # average overall miss latency 1477system.cpu1.dcache.overall_avg_miss_latency::total 19850.536233 # average overall miss latency | 1475system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20052.123480 # average overall miss latency 1476system.cpu1.dcache.demand_avg_miss_latency::total 20052.123480 # average overall miss latency 1477system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20052.123480 # average overall miss latency 1478system.cpu1.dcache.overall_avg_miss_latency::total 20052.123480 # average overall miss latency |
| 1478system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1479system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1480system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1481system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1482system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1483system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1484system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1485system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1479system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1480system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1481system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1482system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1483system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1484system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1485system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1486system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1486system.cpu1.dcache.writebacks::writebacks 113901 # number of writebacks 1487system.cpu1.dcache.writebacks::total 113901 # number of writebacks 1488system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 15137 # number of ReadReq MSHR hits 1489system.cpu1.dcache.ReadReq_mshr_hits::total 15137 # number of ReadReq MSHR hits 1490system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 49794 # number of WriteReq MSHR hits 1491system.cpu1.dcache.WriteReq_mshr_hits::total 49794 # number of WriteReq MSHR hits 1492system.cpu1.dcache.demand_mshr_hits::cpu1.data 64931 # number of demand (read+write) MSHR hits 1493system.cpu1.dcache.demand_mshr_hits::total 64931 # number of demand (read+write) MSHR hits 1494system.cpu1.dcache.overall_mshr_hits::cpu1.data 64931 # number of overall MSHR hits 1495system.cpu1.dcache.overall_mshr_hits::total 64931 # number of overall MSHR hits 1496system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166297 # number of ReadReq MSHR misses 1497system.cpu1.dcache.ReadReq_mshr_misses::total 166297 # number of ReadReq MSHR misses 1498system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 89748 # number of WriteReq MSHR misses 1499system.cpu1.dcache.WriteReq_mshr_misses::total 89748 # number of WriteReq MSHR misses 1500system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5058 # number of LoadLockedReq MSHR misses 1501system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5058 # number of LoadLockedReq MSHR misses 1502system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23425 # number of StoreCondReq MSHR misses 1503system.cpu1.dcache.StoreCondReq_mshr_misses::total 23425 # number of StoreCondReq MSHR misses 1504system.cpu1.dcache.demand_mshr_misses::cpu1.data 256045 # number of demand (read+write) MSHR misses 1505system.cpu1.dcache.demand_mshr_misses::total 256045 # number of demand (read+write) MSHR misses 1506system.cpu1.dcache.overall_mshr_misses::cpu1.data 256045 # number of overall MSHR misses 1507system.cpu1.dcache.overall_mshr_misses::total 256045 # number of overall MSHR misses 1508system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2162409829 # number of ReadReq MSHR miss cycles 1509system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2162409829 # number of ReadReq MSHR miss cycles 1510system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2163633710 # number of WriteReq MSHR miss cycles 1511system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2163633710 # number of WriteReq MSHR miss cycles 1512system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 81526749 # number of LoadLockedReq MSHR miss cycles 1513system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 81526749 # number of LoadLockedReq MSHR miss cycles 1514system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 492905187 # number of StoreCondReq MSHR miss cycles 1515system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 492905187 # number of StoreCondReq MSHR miss cycles 1516system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 177500 # number of StoreCondFailReq MSHR miss cycles 1517system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 177500 # number of StoreCondFailReq MSHR miss cycles 1518system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4326043539 # number of demand (read+write) MSHR miss cycles 1519system.cpu1.dcache.demand_mshr_miss_latency::total 4326043539 # number of demand (read+write) MSHR miss cycles 1520system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4326043539 # number of overall MSHR miss cycles 1521system.cpu1.dcache.overall_mshr_miss_latency::total 4326043539 # number of overall MSHR miss cycles 1522system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 330271000 # number of ReadReq MSHR uncacheable cycles 1523system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 330271000 # number of ReadReq MSHR uncacheable cycles 1524system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 203208500 # number of WriteReq MSHR uncacheable cycles 1525system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 203208500 # number of WriteReq MSHR uncacheable cycles 1526system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 533479500 # number of overall MSHR uncacheable cycles 1527system.cpu1.dcache.overall_mshr_uncacheable_latency::total 533479500 # number of overall MSHR uncacheable cycles 1528system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042162 # mshr miss rate for ReadReq accesses 1529system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042162 # mshr miss rate for ReadReq accesses 1530system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027957 # mshr miss rate for WriteReq accesses 1531system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027957 # mshr miss rate for WriteReq accesses 1532system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053611 # mshr miss rate for LoadLockedReq accesses 1533system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053611 # mshr miss rate for LoadLockedReq accesses 1534system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.252732 # mshr miss rate for StoreCondReq accesses 1535system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.252732 # mshr miss rate for StoreCondReq accesses 1536system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.035788 # mshr miss rate for demand accesses 1537system.cpu1.dcache.demand_mshr_miss_rate::total 0.035788 # mshr miss rate for demand accesses 1538system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035788 # mshr miss rate for overall accesses 1539system.cpu1.dcache.overall_mshr_miss_rate::total 0.035788 # mshr miss rate for overall accesses 1540system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13003.300294 # average ReadReq mshr miss latency 1541system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13003.300294 # average ReadReq mshr miss latency 1542system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24107.876610 # average WriteReq mshr miss latency 1543system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24107.876610 # average WriteReq mshr miss latency 1544system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16118.376631 # average LoadLockedReq mshr miss latency 1545system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16118.376631 # average LoadLockedReq mshr miss latency 1546system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21041.843629 # average StoreCondReq mshr miss latency 1547system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21041.843629 # average StoreCondReq mshr miss latency | 1487system.cpu1.dcache.writebacks::writebacks 120164 # number of writebacks 1488system.cpu1.dcache.writebacks::total 120164 # number of writebacks 1489system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 15759 # number of ReadReq MSHR hits 1490system.cpu1.dcache.ReadReq_mshr_hits::total 15759 # number of ReadReq MSHR hits 1491system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52033 # number of WriteReq MSHR hits 1492system.cpu1.dcache.WriteReq_mshr_hits::total 52033 # number of WriteReq MSHR hits 1493system.cpu1.dcache.demand_mshr_hits::cpu1.data 67792 # number of demand (read+write) MSHR hits 1494system.cpu1.dcache.demand_mshr_hits::total 67792 # number of demand (read+write) MSHR hits 1495system.cpu1.dcache.overall_mshr_hits::cpu1.data 67792 # number of overall MSHR hits 1496system.cpu1.dcache.overall_mshr_hits::total 67792 # number of overall MSHR hits 1497system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172506 # number of ReadReq MSHR misses 1498system.cpu1.dcache.ReadReq_mshr_misses::total 172506 # number of ReadReq MSHR misses 1499system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92582 # number of WriteReq MSHR misses 1500system.cpu1.dcache.WriteReq_mshr_misses::total 92582 # number of WriteReq MSHR misses 1501system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4906 # number of LoadLockedReq MSHR misses 1502system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4906 # number of LoadLockedReq MSHR misses 1503system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23743 # number of StoreCondReq MSHR misses 1504system.cpu1.dcache.StoreCondReq_mshr_misses::total 23743 # number of StoreCondReq MSHR misses 1505system.cpu1.dcache.demand_mshr_misses::cpu1.data 265088 # number of demand (read+write) MSHR misses 1506system.cpu1.dcache.demand_mshr_misses::total 265088 # number of demand (read+write) MSHR misses 1507system.cpu1.dcache.overall_mshr_misses::cpu1.data 265088 # number of overall MSHR misses 1508system.cpu1.dcache.overall_mshr_misses::total 265088 # number of overall MSHR misses 1509system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2304438945 # number of ReadReq MSHR miss cycles 1510system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2304438945 # number of ReadReq MSHR miss cycles 1511system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2314812844 # number of WriteReq MSHR miss cycles 1512system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2314812844 # number of WriteReq MSHR miss cycles 1513system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 80267253 # number of LoadLockedReq MSHR miss cycles 1514system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 80267253 # number of LoadLockedReq MSHR miss cycles 1515system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 522512389 # number of StoreCondReq MSHR miss cycles 1516system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 522512389 # number of StoreCondReq MSHR miss cycles 1517system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 358500 # number of StoreCondFailReq MSHR miss cycles 1518system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 358500 # number of StoreCondFailReq MSHR miss cycles 1519system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4619251789 # number of demand (read+write) MSHR miss cycles 1520system.cpu1.dcache.demand_mshr_miss_latency::total 4619251789 # number of demand (read+write) MSHR miss cycles 1521system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4619251789 # number of overall MSHR miss cycles 1522system.cpu1.dcache.overall_mshr_miss_latency::total 4619251789 # number of overall MSHR miss cycles 1523system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2322402500 # number of ReadReq MSHR uncacheable cycles 1524system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2322402500 # number of ReadReq MSHR uncacheable cycles 1525system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1844154499 # number of WriteReq MSHR uncacheable cycles 1526system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1844154499 # number of WriteReq MSHR uncacheable cycles 1527system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4166556999 # number of overall MSHR uncacheable cycles 1528system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4166556999 # number of overall MSHR uncacheable cycles 1529system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016045 # mshr miss rate for ReadReq accesses 1530system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.016045 # mshr miss rate for ReadReq accesses 1531system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013805 # mshr miss rate for WriteReq accesses 1532system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013805 # mshr miss rate for WriteReq accesses 1533system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050430 # mshr miss rate for LoadLockedReq accesses 1534system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050430 # mshr miss rate for LoadLockedReq accesses 1535system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248626 # mshr miss rate for StoreCondReq accesses 1536system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248626 # mshr miss rate for StoreCondReq accesses 1537system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.015185 # mshr miss rate for demand accesses 1538system.cpu1.dcache.demand_mshr_miss_rate::total 0.015185 # mshr miss rate for demand accesses 1539system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015185 # mshr miss rate for overall accesses 1540system.cpu1.dcache.overall_mshr_miss_rate::total 0.015185 # mshr miss rate for overall accesses 1541system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13358.601701 # average ReadReq mshr miss latency 1542system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13358.601701 # average ReadReq mshr miss latency 1543system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25002.839040 # average WriteReq mshr miss latency 1544system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25002.839040 # average WriteReq mshr miss latency 1545system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16361.038117 # average LoadLockedReq mshr miss latency 1546system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16361.038117 # average LoadLockedReq mshr miss latency 1547system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22007.007918 # average StoreCondReq mshr miss latency 1548system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22007.007918 # average StoreCondReq mshr miss latency |
| 1548system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1549system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1549system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1550system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1550system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16895.637638 # average overall mshr miss latency 1551system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16895.637638 # average overall mshr miss latency 1552system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16895.637638 # average overall mshr miss latency 1553system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16895.637638 # average overall mshr miss latency | 1551system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17425.352294 # average overall mshr miss latency 1552system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17425.352294 # average overall mshr miss latency 1553system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17425.352294 # average overall mshr miss latency 1554system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17425.352294 # average overall mshr miss latency |
| 1554system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1555system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1556system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1557system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1558system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1559system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1560system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1555system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1556system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1557system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1558system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1559system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1560system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1561system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1561system.cpu1.icache.tags.replacements 908016 # number of replacements 1562system.cpu1.icache.tags.tagsinuse 499.415703 # Cycle average of tags in use 1563system.cpu1.icache.tags.total_refs 6861520 # Total number of references to valid blocks. 1564system.cpu1.icache.tags.sampled_refs 908528 # Sample count of references to valid blocks. 1565system.cpu1.icache.tags.avg_refs 7.552348 # Average number of references to valid blocks. 1566system.cpu1.icache.tags.warmup_cycle 71602668000 # Cycle when the warmup percentage was hit. 1567system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.415703 # Average occupied blocks per requestor 1568system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975421 # Average percentage of cache occupancy 1569system.cpu1.icache.tags.occ_percent::total 0.975421 # Average percentage of cache occupancy | 1562system.cpu1.icache.tags.replacements 948962 # number of replacements 1563system.cpu1.icache.tags.tagsinuse 499.398770 # Cycle average of tags in use 1564system.cpu1.icache.tags.total_refs 38866849 # Total number of references to valid blocks. 1565system.cpu1.icache.tags.sampled_refs 949474 # Sample count of references to valid blocks. 1566system.cpu1.icache.tags.avg_refs 40.935138 # Average number of references to valid blocks. 1567system.cpu1.icache.tags.warmup_cycle 71724827500 # Cycle when the warmup percentage was hit. 1568system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.398770 # Average occupied blocks per requestor 1569system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975388 # Average percentage of cache occupancy 1570system.cpu1.icache.tags.occ_percent::total 0.975388 # Average percentage of cache occupancy |
| 1570system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1571system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1571system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id 1572system.cpu1.icache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id | 1572system.cpu1.icache.tags.age_task_id_blocks_1024::2 459 # Occupied blocks per task id 1573system.cpu1.icache.tags.age_task_id_blocks_1024::3 53 # Occupied blocks per task id |
| 1573system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1574system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1574system.cpu1.icache.tags.tag_accesses 16448624 # Number of tag accesses 1575system.cpu1.icache.tags.data_accesses 16448624 # Number of data accesses 1576system.cpu1.icache.ReadReq_hits::cpu1.inst 6861520 # number of ReadReq hits 1577system.cpu1.icache.ReadReq_hits::total 6861520 # number of ReadReq hits 1578system.cpu1.icache.demand_hits::cpu1.inst 6861520 # number of demand (read+write) hits 1579system.cpu1.icache.demand_hits::total 6861520 # number of demand (read+write) hits 1580system.cpu1.icache.overall_hits::cpu1.inst 6861520 # number of overall hits 1581system.cpu1.icache.overall_hits::total 6861520 # number of overall hits 1582system.cpu1.icache.ReadReq_misses::cpu1.inst 908528 # number of ReadReq misses 1583system.cpu1.icache.ReadReq_misses::total 908528 # number of ReadReq misses 1584system.cpu1.icache.demand_misses::cpu1.inst 908528 # number of demand (read+write) misses 1585system.cpu1.icache.demand_misses::total 908528 # number of demand (read+write) misses 1586system.cpu1.icache.overall_misses::cpu1.inst 908528 # number of overall misses 1587system.cpu1.icache.overall_misses::total 908528 # number of overall misses 1588system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7748571238 # number of ReadReq miss cycles 1589system.cpu1.icache.ReadReq_miss_latency::total 7748571238 # number of ReadReq miss cycles 1590system.cpu1.icache.demand_miss_latency::cpu1.inst 7748571238 # number of demand (read+write) miss cycles 1591system.cpu1.icache.demand_miss_latency::total 7748571238 # number of demand (read+write) miss cycles 1592system.cpu1.icache.overall_miss_latency::cpu1.inst 7748571238 # number of overall miss cycles 1593system.cpu1.icache.overall_miss_latency::total 7748571238 # number of overall miss cycles 1594system.cpu1.icache.ReadReq_accesses::cpu1.inst 7770048 # number of ReadReq accesses(hits+misses) 1595system.cpu1.icache.ReadReq_accesses::total 7770048 # number of ReadReq accesses(hits+misses) 1596system.cpu1.icache.demand_accesses::cpu1.inst 7770048 # number of demand (read+write) accesses 1597system.cpu1.icache.demand_accesses::total 7770048 # number of demand (read+write) accesses 1598system.cpu1.icache.overall_accesses::cpu1.inst 7770048 # number of overall (read+write) accesses 1599system.cpu1.icache.overall_accesses::total 7770048 # number of overall (read+write) accesses 1600system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.116927 # miss rate for ReadReq accesses 1601system.cpu1.icache.ReadReq_miss_rate::total 0.116927 # miss rate for ReadReq accesses 1602system.cpu1.icache.demand_miss_rate::cpu1.inst 0.116927 # miss rate for demand accesses 1603system.cpu1.icache.demand_miss_rate::total 0.116927 # miss rate for demand accesses 1604system.cpu1.icache.overall_miss_rate::cpu1.inst 0.116927 # miss rate for overall accesses 1605system.cpu1.icache.overall_miss_rate::total 0.116927 # miss rate for overall accesses 1606system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8528.709339 # average ReadReq miss latency 1607system.cpu1.icache.ReadReq_avg_miss_latency::total 8528.709339 # average ReadReq miss latency 1608system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8528.709339 # average overall miss latency 1609system.cpu1.icache.demand_avg_miss_latency::total 8528.709339 # average overall miss latency 1610system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8528.709339 # average overall miss latency 1611system.cpu1.icache.overall_avg_miss_latency::total 8528.709339 # average overall miss latency | 1575system.cpu1.icache.tags.tag_accesses 80582120 # Number of tag accesses 1576system.cpu1.icache.tags.data_accesses 80582120 # Number of data accesses 1577system.cpu1.icache.ReadReq_hits::cpu1.inst 38866849 # number of ReadReq hits 1578system.cpu1.icache.ReadReq_hits::total 38866849 # number of ReadReq hits 1579system.cpu1.icache.demand_hits::cpu1.inst 38866849 # number of demand (read+write) hits 1580system.cpu1.icache.demand_hits::total 38866849 # number of demand (read+write) hits 1581system.cpu1.icache.overall_hits::cpu1.inst 38866849 # number of overall hits 1582system.cpu1.icache.overall_hits::total 38866849 # number of overall hits 1583system.cpu1.icache.ReadReq_misses::cpu1.inst 949474 # number of ReadReq misses 1584system.cpu1.icache.ReadReq_misses::total 949474 # number of ReadReq misses 1585system.cpu1.icache.demand_misses::cpu1.inst 949474 # number of demand (read+write) misses 1586system.cpu1.icache.demand_misses::total 949474 # number of demand (read+write) misses 1587system.cpu1.icache.overall_misses::cpu1.inst 949474 # number of overall misses 1588system.cpu1.icache.overall_misses::total 949474 # number of overall misses 1589system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8197479438 # number of ReadReq miss cycles 1590system.cpu1.icache.ReadReq_miss_latency::total 8197479438 # number of ReadReq miss cycles 1591system.cpu1.icache.demand_miss_latency::cpu1.inst 8197479438 # number of demand (read+write) miss cycles 1592system.cpu1.icache.demand_miss_latency::total 8197479438 # number of demand (read+write) miss cycles 1593system.cpu1.icache.overall_miss_latency::cpu1.inst 8197479438 # number of overall miss cycles 1594system.cpu1.icache.overall_miss_latency::total 8197479438 # number of overall miss cycles 1595system.cpu1.icache.ReadReq_accesses::cpu1.inst 39816323 # number of ReadReq accesses(hits+misses) 1596system.cpu1.icache.ReadReq_accesses::total 39816323 # number of ReadReq accesses(hits+misses) 1597system.cpu1.icache.demand_accesses::cpu1.inst 39816323 # number of demand (read+write) accesses 1598system.cpu1.icache.demand_accesses::total 39816323 # number of demand (read+write) accesses 1599system.cpu1.icache.overall_accesses::cpu1.inst 39816323 # number of overall (read+write) accesses 1600system.cpu1.icache.overall_accesses::total 39816323 # number of overall (read+write) accesses 1601system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023846 # miss rate for ReadReq accesses 1602system.cpu1.icache.ReadReq_miss_rate::total 0.023846 # miss rate for ReadReq accesses 1603system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023846 # miss rate for demand accesses 1604system.cpu1.icache.demand_miss_rate::total 0.023846 # miss rate for demand accesses 1605system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023846 # miss rate for overall accesses 1606system.cpu1.icache.overall_miss_rate::total 0.023846 # miss rate for overall accesses 1607system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8633.706071 # average ReadReq miss latency 1608system.cpu1.icache.ReadReq_avg_miss_latency::total 8633.706071 # average ReadReq miss latency 1609system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8633.706071 # average overall miss latency 1610system.cpu1.icache.demand_avg_miss_latency::total 8633.706071 # average overall miss latency 1611system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8633.706071 # average overall miss latency 1612system.cpu1.icache.overall_avg_miss_latency::total 8633.706071 # average overall miss latency |
| 1612system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1613system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1614system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1615system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1616system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1617system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1618system.cpu1.icache.fast_writes 0 # number of fast writes performed 1619system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1613system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1614system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1615system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1616system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1617system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1618system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1619system.cpu1.icache.fast_writes 0 # number of fast writes performed 1620system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1620system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 908528 # number of ReadReq MSHR misses 1621system.cpu1.icache.ReadReq_mshr_misses::total 908528 # number of ReadReq MSHR misses 1622system.cpu1.icache.demand_mshr_misses::cpu1.inst 908528 # number of demand (read+write) MSHR misses 1623system.cpu1.icache.demand_mshr_misses::total 908528 # number of demand (read+write) MSHR misses 1624system.cpu1.icache.overall_mshr_misses::cpu1.inst 908528 # number of overall MSHR misses 1625system.cpu1.icache.overall_mshr_misses::total 908528 # number of overall MSHR misses 1626system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6381932762 # number of ReadReq MSHR miss cycles 1627system.cpu1.icache.ReadReq_mshr_miss_latency::total 6381932762 # number of ReadReq MSHR miss cycles 1628system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6381932762 # number of demand (read+write) MSHR miss cycles 1629system.cpu1.icache.demand_mshr_miss_latency::total 6381932762 # number of demand (read+write) MSHR miss cycles 1630system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6381932762 # number of overall MSHR miss cycles 1631system.cpu1.icache.overall_mshr_miss_latency::total 6381932762 # number of overall MSHR miss cycles 1632system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10331250 # number of ReadReq MSHR uncacheable cycles 1633system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10331250 # number of ReadReq MSHR uncacheable cycles 1634system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10331250 # number of overall MSHR uncacheable cycles 1635system.cpu1.icache.overall_mshr_uncacheable_latency::total 10331250 # number of overall MSHR uncacheable cycles 1636system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.116927 # mshr miss rate for ReadReq accesses 1637system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.116927 # mshr miss rate for ReadReq accesses 1638system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.116927 # mshr miss rate for demand accesses 1639system.cpu1.icache.demand_mshr_miss_rate::total 0.116927 # mshr miss rate for demand accesses 1640system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.116927 # mshr miss rate for overall accesses 1641system.cpu1.icache.overall_mshr_miss_rate::total 0.116927 # mshr miss rate for overall accesses 1642system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7024.475593 # average ReadReq mshr miss latency 1643system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7024.475593 # average ReadReq mshr miss latency 1644system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7024.475593 # average overall mshr miss latency 1645system.cpu1.icache.demand_avg_mshr_miss_latency::total 7024.475593 # average overall mshr miss latency 1646system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7024.475593 # average overall mshr miss latency 1647system.cpu1.icache.overall_avg_mshr_miss_latency::total 7024.475593 # average overall mshr miss latency | 1621system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 949474 # number of ReadReq MSHR misses 1622system.cpu1.icache.ReadReq_mshr_misses::total 949474 # number of ReadReq MSHR misses 1623system.cpu1.icache.demand_mshr_misses::cpu1.inst 949474 # number of demand (read+write) MSHR misses 1624system.cpu1.icache.demand_mshr_misses::total 949474 # number of demand (read+write) MSHR misses 1625system.cpu1.icache.overall_mshr_misses::cpu1.inst 949474 # number of overall MSHR misses 1626system.cpu1.icache.overall_mshr_misses::total 949474 # number of overall MSHR misses 1627system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7246706562 # number of ReadReq MSHR miss cycles 1628system.cpu1.icache.ReadReq_mshr_miss_latency::total 7246706562 # number of ReadReq MSHR miss cycles 1629system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7246706562 # number of demand (read+write) MSHR miss cycles 1630system.cpu1.icache.demand_mshr_miss_latency::total 7246706562 # number of demand (read+write) MSHR miss cycles 1631system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7246706562 # number of overall MSHR miss cycles 1632system.cpu1.icache.overall_mshr_miss_latency::total 7246706562 # number of overall MSHR miss cycles 1633system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10208000 # number of ReadReq MSHR uncacheable cycles 1634system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10208000 # number of ReadReq MSHR uncacheable cycles 1635system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10208000 # number of overall MSHR uncacheable cycles 1636system.cpu1.icache.overall_mshr_uncacheable_latency::total 10208000 # number of overall MSHR uncacheable cycles 1637system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023846 # mshr miss rate for ReadReq accesses 1638system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023846 # mshr miss rate for ReadReq accesses 1639system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023846 # mshr miss rate for demand accesses 1640system.cpu1.icache.demand_mshr_miss_rate::total 0.023846 # mshr miss rate for demand accesses 1641system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023846 # mshr miss rate for overall accesses 1642system.cpu1.icache.overall_mshr_miss_rate::total 0.023846 # mshr miss rate for overall accesses 1643system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7632.338076 # average ReadReq mshr miss latency 1644system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7632.338076 # average ReadReq mshr miss latency 1645system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7632.338076 # average overall mshr miss latency 1646system.cpu1.icache.demand_avg_mshr_miss_latency::total 7632.338076 # average overall mshr miss latency 1647system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7632.338076 # average overall mshr miss latency 1648system.cpu1.icache.overall_avg_mshr_miss_latency::total 7632.338076 # average overall mshr miss latency |
| 1648system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1649system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1650system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1651system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1652system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1649system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1650system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1651system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1652system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1653system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1653system.cpu1.l2cache.prefetcher.num_hwpf_issued 255012 # number of hwpf issued 1654system.cpu1.l2cache.prefetcher.pfIdentified 255045 # number of prefetch candidates identified 1655system.cpu1.l2cache.prefetcher.pfBufferHit 26 # number of redundant prefetches already in prefetch queue | 1654system.cpu1.l2cache.prefetcher.num_hwpf_issued 263000 # number of hwpf issued 1655system.cpu1.l2cache.prefetcher.pfIdentified 263018 # number of prefetch candidates identified 1656system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue |
| 1656system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1657system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 1657system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1658system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 1658system.cpu1.l2cache.prefetcher.pfSpanPage 67427 # number of prefetches not generated due to page crossing 1659system.cpu1.l2cache.tags.replacements 54264 # number of replacements 1660system.cpu1.l2cache.tags.tagsinuse 15327.785502 # Cycle average of tags in use 1661system.cpu1.l2cache.tags.total_refs 1131516 # Total number of references to valid blocks. 1662system.cpu1.l2cache.tags.sampled_refs 69292 # Sample count of references to valid blocks. 1663system.cpu1.l2cache.tags.avg_refs 16.329677 # Average number of references to valid blocks. | 1659system.cpu1.l2cache.prefetcher.pfSpanPage 69926 # number of prefetches not generated due to page crossing 1660system.cpu1.l2cache.tags.replacements 55260 # number of replacements 1661system.cpu1.l2cache.tags.tagsinuse 15340.181807 # Cycle average of tags in use 1662system.cpu1.l2cache.tags.total_refs 1180273 # Total number of references to valid blocks. 1663system.cpu1.l2cache.tags.sampled_refs 70026 # Sample count of references to valid blocks. 1664system.cpu1.l2cache.tags.avg_refs 16.854783 # Average number of references to valid blocks. |
| 1664system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1665system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1665system.cpu1.l2cache.tags.occ_blocks::writebacks 8763.818423 # Average occupied blocks per requestor 1666system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 26.824644 # Average occupied blocks per requestor 1667system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.109281 # Average occupied blocks per requestor 1668system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3126.745417 # Average occupied blocks per requestor 1669system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2197.034801 # Average occupied blocks per requestor 1670system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1213.252936 # Average occupied blocks per requestor 1671system.cpu1.l2cache.tags.occ_percent::writebacks 0.534901 # Average percentage of cache occupancy 1672system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001637 # Average percentage of cache occupancy | 1666system.cpu1.l2cache.tags.occ_blocks::writebacks 7920.573124 # Average occupied blocks per requestor 1667system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 36.864575 # Average occupied blocks per requestor 1668system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.107624 # Average occupied blocks per requestor 1669system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4396.054830 # Average occupied blocks per requestor 1670system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2144.688544 # Average occupied blocks per requestor 1671system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 841.893110 # Average occupied blocks per requestor 1672system.cpu1.l2cache.tags.occ_percent::writebacks 0.483433 # Average percentage of cache occupancy 1673system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002250 # Average percentage of cache occupancy |
| 1673system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000007 # Average percentage of cache occupancy | 1674system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000007 # Average percentage of cache occupancy |
| 1674system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.190841 # Average percentage of cache occupancy 1675system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.134096 # Average percentage of cache occupancy 1676system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.074051 # Average percentage of cache occupancy 1677system.cpu1.l2cache.tags.occ_percent::total 0.935534 # Average percentage of cache occupancy 1678system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2056 # Occupied blocks per task id 1679system.cpu1.l2cache.tags.occ_task_id_blocks::1023 45 # Occupied blocks per task id 1680system.cpu1.l2cache.tags.occ_task_id_blocks::1024 12927 # Occupied blocks per task id 1681system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 84 # Occupied blocks per task id 1682system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 880 # Occupied blocks per task id 1683system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1092 # Occupied blocks per task id | 1675system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.268314 # Average percentage of cache occupancy 1676system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.130901 # Average percentage of cache occupancy 1677system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051385 # Average percentage of cache occupancy 1678system.cpu1.l2cache.tags.occ_percent::total 0.936290 # Average percentage of cache occupancy 1679system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2047 # Occupied blocks per task id 1680system.cpu1.l2cache.tags.occ_task_id_blocks::1023 49 # Occupied blocks per task id 1681system.cpu1.l2cache.tags.occ_task_id_blocks::1024 12670 # Occupied blocks per task id 1682system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 77 # Occupied blocks per task id 1683system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 853 # Occupied blocks per task id 1684system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1117 # Occupied blocks per task id |
| 1684system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id | 1685system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id |
| 1685system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id 1686system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id 1687system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 271 # Occupied blocks per task id 1688system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5756 # Occupied blocks per task id 1689system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 6900 # Occupied blocks per task id 1690system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.125488 # Percentage of cache occupancy per task id 1691system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002747 # Percentage of cache occupancy per task id 1692system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.789001 # Percentage of cache occupancy per task id 1693system.cpu1.l2cache.tags.tag_accesses 21629208 # Number of tag accesses 1694system.cpu1.l2cache.tags.data_accesses 21629208 # Number of data accesses 1695system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28145 # number of ReadReq hits 1696system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2626 # number of ReadReq hits 1697system.cpu1.l2cache.ReadReq_hits::cpu1.inst 889570 # number of ReadReq hits 1698system.cpu1.l2cache.ReadReq_hits::cpu1.data 104349 # number of ReadReq hits 1699system.cpu1.l2cache.ReadReq_hits::total 1024690 # number of ReadReq hits 1700system.cpu1.l2cache.Writeback_hits::writebacks 113900 # number of Writeback hits 1701system.cpu1.l2cache.Writeback_hits::total 113900 # number of Writeback hits 1702system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1602 # number of UpgradeReq hits 1703system.cpu1.l2cache.UpgradeReq_hits::total 1602 # number of UpgradeReq hits 1704system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 885 # number of SCUpgradeReq hits 1705system.cpu1.l2cache.SCUpgradeReq_hits::total 885 # number of SCUpgradeReq hits 1706system.cpu1.l2cache.ReadExReq_hits::cpu1.data 24979 # number of ReadExReq hits 1707system.cpu1.l2cache.ReadExReq_hits::total 24979 # number of ReadExReq hits 1708system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28145 # number of demand (read+write) hits 1709system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2626 # number of demand (read+write) hits 1710system.cpu1.l2cache.demand_hits::cpu1.inst 889570 # number of demand (read+write) hits 1711system.cpu1.l2cache.demand_hits::cpu1.data 129328 # number of demand (read+write) hits 1712system.cpu1.l2cache.demand_hits::total 1049669 # number of demand (read+write) hits 1713system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 28145 # number of overall hits 1714system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2626 # number of overall hits 1715system.cpu1.l2cache.overall_hits::cpu1.inst 889570 # number of overall hits 1716system.cpu1.l2cache.overall_hits::cpu1.data 129328 # number of overall hits 1717system.cpu1.l2cache.overall_hits::total 1049669 # number of overall hits 1718system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 614 # number of ReadReq misses 1719system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 219 # number of ReadReq misses 1720system.cpu1.l2cache.ReadReq_misses::cpu1.inst 18958 # number of ReadReq misses 1721system.cpu1.l2cache.ReadReq_misses::cpu1.data 67006 # number of ReadReq misses 1722system.cpu1.l2cache.ReadReq_misses::total 86797 # number of ReadReq misses 1723system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28133 # number of UpgradeReq misses 1724system.cpu1.l2cache.UpgradeReq_misses::total 28133 # number of UpgradeReq misses 1725system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22540 # number of SCUpgradeReq misses 1726system.cpu1.l2cache.SCUpgradeReq_misses::total 22540 # number of SCUpgradeReq misses 1727system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35034 # number of ReadExReq misses 1728system.cpu1.l2cache.ReadExReq_misses::total 35034 # number of ReadExReq misses 1729system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 614 # number of demand (read+write) misses 1730system.cpu1.l2cache.demand_misses::cpu1.itb.walker 219 # number of demand (read+write) misses 1731system.cpu1.l2cache.demand_misses::cpu1.inst 18958 # number of demand (read+write) misses 1732system.cpu1.l2cache.demand_misses::cpu1.data 102040 # number of demand (read+write) misses 1733system.cpu1.l2cache.demand_misses::total 121831 # number of demand (read+write) misses 1734system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 614 # number of overall misses 1735system.cpu1.l2cache.overall_misses::cpu1.itb.walker 219 # number of overall misses 1736system.cpu1.l2cache.overall_misses::cpu1.inst 18958 # number of overall misses 1737system.cpu1.l2cache.overall_misses::cpu1.data 102040 # number of overall misses 1738system.cpu1.l2cache.overall_misses::total 121831 # number of overall misses 1739system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 13117250 # number of ReadReq miss cycles 1740system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4335498 # number of ReadReq miss cycles 1741system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 588499240 # number of ReadReq miss cycles 1742system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1440160422 # number of ReadReq miss cycles 1743system.cpu1.l2cache.ReadReq_miss_latency::total 2046112410 # number of ReadReq miss cycles 1744system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 524558345 # number of UpgradeReq miss cycles 1745system.cpu1.l2cache.UpgradeReq_miss_latency::total 524558345 # number of UpgradeReq miss cycles 1746system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 440871540 # number of SCUpgradeReq miss cycles 1747system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 440871540 # number of SCUpgradeReq miss cycles 1748system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 173000 # number of SCUpgradeFailReq miss cycles 1749system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 173000 # number of SCUpgradeFailReq miss cycles 1750system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1316941950 # number of ReadExReq miss cycles 1751system.cpu1.l2cache.ReadExReq_miss_latency::total 1316941950 # number of ReadExReq miss cycles 1752system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 13117250 # number of demand (read+write) miss cycles 1753system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4335498 # number of demand (read+write) miss cycles 1754system.cpu1.l2cache.demand_miss_latency::cpu1.inst 588499240 # number of demand (read+write) miss cycles 1755system.cpu1.l2cache.demand_miss_latency::cpu1.data 2757102372 # number of demand (read+write) miss cycles 1756system.cpu1.l2cache.demand_miss_latency::total 3363054360 # number of demand (read+write) miss cycles 1757system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 13117250 # number of overall miss cycles 1758system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4335498 # number of overall miss cycles 1759system.cpu1.l2cache.overall_miss_latency::cpu1.inst 588499240 # number of overall miss cycles 1760system.cpu1.l2cache.overall_miss_latency::cpu1.data 2757102372 # number of overall miss cycles 1761system.cpu1.l2cache.overall_miss_latency::total 3363054360 # number of overall miss cycles 1762system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 28759 # number of ReadReq accesses(hits+misses) 1763system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2845 # number of ReadReq accesses(hits+misses) 1764system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 908528 # number of ReadReq accesses(hits+misses) 1765system.cpu1.l2cache.ReadReq_accesses::cpu1.data 171355 # number of ReadReq accesses(hits+misses) 1766system.cpu1.l2cache.ReadReq_accesses::total 1111487 # number of ReadReq accesses(hits+misses) 1767system.cpu1.l2cache.Writeback_accesses::writebacks 113900 # number of Writeback accesses(hits+misses) 1768system.cpu1.l2cache.Writeback_accesses::total 113900 # number of Writeback accesses(hits+misses) 1769system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29735 # number of UpgradeReq accesses(hits+misses) 1770system.cpu1.l2cache.UpgradeReq_accesses::total 29735 # number of UpgradeReq accesses(hits+misses) 1771system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23425 # number of SCUpgradeReq accesses(hits+misses) 1772system.cpu1.l2cache.SCUpgradeReq_accesses::total 23425 # number of SCUpgradeReq accesses(hits+misses) 1773system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 60013 # number of ReadExReq accesses(hits+misses) 1774system.cpu1.l2cache.ReadExReq_accesses::total 60013 # number of ReadExReq accesses(hits+misses) 1775system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 28759 # number of demand (read+write) accesses 1776system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2845 # number of demand (read+write) accesses 1777system.cpu1.l2cache.demand_accesses::cpu1.inst 908528 # number of demand (read+write) accesses 1778system.cpu1.l2cache.demand_accesses::cpu1.data 231368 # number of demand (read+write) accesses 1779system.cpu1.l2cache.demand_accesses::total 1171500 # number of demand (read+write) accesses 1780system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 28759 # number of overall (read+write) accesses 1781system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2845 # number of overall (read+write) accesses 1782system.cpu1.l2cache.overall_accesses::cpu1.inst 908528 # number of overall (read+write) accesses 1783system.cpu1.l2cache.overall_accesses::cpu1.data 231368 # number of overall (read+write) accesses 1784system.cpu1.l2cache.overall_accesses::total 1171500 # number of overall (read+write) accesses 1785system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021350 # miss rate for ReadReq accesses 1786system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.076977 # miss rate for ReadReq accesses 1787system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.020867 # miss rate for ReadReq accesses 1788system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.391036 # miss rate for ReadReq accesses 1789system.cpu1.l2cache.ReadReq_miss_rate::total 0.078091 # miss rate for ReadReq accesses 1790system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.946124 # miss rate for UpgradeReq accesses 1791system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.946124 # miss rate for UpgradeReq accesses 1792system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.962220 # miss rate for SCUpgradeReq accesses 1793system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.962220 # miss rate for SCUpgradeReq accesses 1794system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.583774 # miss rate for ReadExReq accesses 1795system.cpu1.l2cache.ReadExReq_miss_rate::total 0.583774 # miss rate for ReadExReq accesses 1796system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021350 # miss rate for demand accesses 1797system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.076977 # miss rate for demand accesses 1798system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.020867 # miss rate for demand accesses 1799system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.441029 # miss rate for demand accesses 1800system.cpu1.l2cache.demand_miss_rate::total 0.103996 # miss rate for demand accesses 1801system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021350 # miss rate for overall accesses 1802system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.076977 # miss rate for overall accesses 1803system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.020867 # miss rate for overall accesses 1804system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.441029 # miss rate for overall accesses 1805system.cpu1.l2cache.overall_miss_rate::total 0.103996 # miss rate for overall accesses 1806system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21363.599349 # average ReadReq miss latency 1807system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19796.794521 # average ReadReq miss latency 1808system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 31042.263952 # average ReadReq miss latency 1809system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21493.006925 # average ReadReq miss latency 1810system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23573.538371 # average ReadReq miss latency 1811system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18645.659723 # average UpgradeReq miss latency 1812system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18645.659723 # average UpgradeReq miss latency 1813system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19559.518190 # average SCUpgradeReq miss latency 1814system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19559.518190 # average SCUpgradeReq miss latency | 1686system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id 1687system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id 1688system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id 1689system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5605 # Occupied blocks per task id 1690system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 6801 # Occupied blocks per task id 1691system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.124939 # Percentage of cache occupancy per task id 1692system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002991 # Percentage of cache occupancy per task id 1693system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.773315 # Percentage of cache occupancy per task id 1694system.cpu1.l2cache.tags.tag_accesses 22538505 # Number of tag accesses 1695system.cpu1.l2cache.tags.data_accesses 22538505 # Number of data accesses 1696system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28252 # number of ReadReq hits 1697system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2535 # number of ReadReq hits 1698system.cpu1.l2cache.ReadReq_hits::cpu1.inst 928580 # number of ReadReq hits 1699system.cpu1.l2cache.ReadReq_hits::cpu1.data 109415 # number of ReadReq hits 1700system.cpu1.l2cache.ReadReq_hits::total 1068782 # number of ReadReq hits 1701system.cpu1.l2cache.Writeback_hits::writebacks 120163 # number of Writeback hits 1702system.cpu1.l2cache.Writeback_hits::total 120163 # number of Writeback hits 1703system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1523 # number of UpgradeReq hits 1704system.cpu1.l2cache.UpgradeReq_hits::total 1523 # number of UpgradeReq hits 1705system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 944 # number of SCUpgradeReq hits 1706system.cpu1.l2cache.SCUpgradeReq_hits::total 944 # number of SCUpgradeReq hits 1707system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27335 # number of ReadExReq hits 1708system.cpu1.l2cache.ReadExReq_hits::total 27335 # number of ReadExReq hits 1709system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28252 # number of demand (read+write) hits 1710system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2535 # number of demand (read+write) hits 1711system.cpu1.l2cache.demand_hits::cpu1.inst 928580 # number of demand (read+write) hits 1712system.cpu1.l2cache.demand_hits::cpu1.data 136750 # number of demand (read+write) hits 1713system.cpu1.l2cache.demand_hits::total 1096117 # number of demand (read+write) hits 1714system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 28252 # number of overall hits 1715system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2535 # number of overall hits 1716system.cpu1.l2cache.overall_hits::cpu1.inst 928580 # number of overall hits 1717system.cpu1.l2cache.overall_hits::cpu1.data 136750 # number of overall hits 1718system.cpu1.l2cache.overall_hits::total 1096117 # number of overall hits 1719system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 647 # number of ReadReq misses 1720system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 218 # number of ReadReq misses 1721system.cpu1.l2cache.ReadReq_misses::cpu1.inst 20894 # number of ReadReq misses 1722system.cpu1.l2cache.ReadReq_misses::cpu1.data 67997 # number of ReadReq misses 1723system.cpu1.l2cache.ReadReq_misses::total 89756 # number of ReadReq misses 1724system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28472 # number of UpgradeReq misses 1725system.cpu1.l2cache.UpgradeReq_misses::total 28472 # number of UpgradeReq misses 1726system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22799 # number of SCUpgradeReq misses 1727system.cpu1.l2cache.SCUpgradeReq_misses::total 22799 # number of SCUpgradeReq misses 1728system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35252 # number of ReadExReq misses 1729system.cpu1.l2cache.ReadExReq_misses::total 35252 # number of ReadExReq misses 1730system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 647 # number of demand (read+write) misses 1731system.cpu1.l2cache.demand_misses::cpu1.itb.walker 218 # number of demand (read+write) misses 1732system.cpu1.l2cache.demand_misses::cpu1.inst 20894 # number of demand (read+write) misses 1733system.cpu1.l2cache.demand_misses::cpu1.data 103249 # number of demand (read+write) misses 1734system.cpu1.l2cache.demand_misses::total 125008 # number of demand (read+write) misses 1735system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 647 # number of overall misses 1736system.cpu1.l2cache.overall_misses::cpu1.itb.walker 218 # number of overall misses 1737system.cpu1.l2cache.overall_misses::cpu1.inst 20894 # number of overall misses 1738system.cpu1.l2cache.overall_misses::cpu1.data 103249 # number of overall misses 1739system.cpu1.l2cache.overall_misses::total 125008 # number of overall misses 1740system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 15366481 # number of ReadReq miss cycles 1741system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4392000 # number of ReadReq miss cycles 1742system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 733956985 # number of ReadReq miss cycles 1743system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1489534989 # number of ReadReq miss cycles 1744system.cpu1.l2cache.ReadReq_miss_latency::total 2243250455 # number of ReadReq miss cycles 1745system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 540730906 # number of UpgradeReq miss cycles 1746system.cpu1.l2cache.UpgradeReq_miss_latency::total 540730906 # number of UpgradeReq miss cycles 1747system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 460330587 # number of SCUpgradeReq miss cycles 1748system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 460330587 # number of SCUpgradeReq miss cycles 1749system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 350500 # number of SCUpgradeFailReq miss cycles 1750system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 350500 # number of SCUpgradeFailReq miss cycles 1751system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1393602664 # number of ReadExReq miss cycles 1752system.cpu1.l2cache.ReadExReq_miss_latency::total 1393602664 # number of ReadExReq miss cycles 1753system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 15366481 # number of demand (read+write) miss cycles 1754system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4392000 # number of demand (read+write) miss cycles 1755system.cpu1.l2cache.demand_miss_latency::cpu1.inst 733956985 # number of demand (read+write) miss cycles 1756system.cpu1.l2cache.demand_miss_latency::cpu1.data 2883137653 # number of demand (read+write) miss cycles 1757system.cpu1.l2cache.demand_miss_latency::total 3636853119 # number of demand (read+write) miss cycles 1758system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 15366481 # number of overall miss cycles 1759system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4392000 # number of overall miss cycles 1760system.cpu1.l2cache.overall_miss_latency::cpu1.inst 733956985 # number of overall miss cycles 1761system.cpu1.l2cache.overall_miss_latency::cpu1.data 2883137653 # number of overall miss cycles 1762system.cpu1.l2cache.overall_miss_latency::total 3636853119 # number of overall miss cycles 1763system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 28899 # number of ReadReq accesses(hits+misses) 1764system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2753 # number of ReadReq accesses(hits+misses) 1765system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 949474 # number of ReadReq accesses(hits+misses) 1766system.cpu1.l2cache.ReadReq_accesses::cpu1.data 177412 # number of ReadReq accesses(hits+misses) 1767system.cpu1.l2cache.ReadReq_accesses::total 1158538 # number of ReadReq accesses(hits+misses) 1768system.cpu1.l2cache.Writeback_accesses::writebacks 120163 # number of Writeback accesses(hits+misses) 1769system.cpu1.l2cache.Writeback_accesses::total 120163 # number of Writeback accesses(hits+misses) 1770system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29995 # number of UpgradeReq accesses(hits+misses) 1771system.cpu1.l2cache.UpgradeReq_accesses::total 29995 # number of UpgradeReq accesses(hits+misses) 1772system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23743 # number of SCUpgradeReq accesses(hits+misses) 1773system.cpu1.l2cache.SCUpgradeReq_accesses::total 23743 # number of SCUpgradeReq accesses(hits+misses) 1774system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62587 # number of ReadExReq accesses(hits+misses) 1775system.cpu1.l2cache.ReadExReq_accesses::total 62587 # number of ReadExReq accesses(hits+misses) 1776system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 28899 # number of demand (read+write) accesses 1777system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2753 # number of demand (read+write) accesses 1778system.cpu1.l2cache.demand_accesses::cpu1.inst 949474 # number of demand (read+write) accesses 1779system.cpu1.l2cache.demand_accesses::cpu1.data 239999 # number of demand (read+write) accesses 1780system.cpu1.l2cache.demand_accesses::total 1221125 # number of demand (read+write) accesses 1781system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 28899 # number of overall (read+write) accesses 1782system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2753 # number of overall (read+write) accesses 1783system.cpu1.l2cache.overall_accesses::cpu1.inst 949474 # number of overall (read+write) accesses 1784system.cpu1.l2cache.overall_accesses::cpu1.data 239999 # number of overall (read+write) accesses 1785system.cpu1.l2cache.overall_accesses::total 1221125 # number of overall (read+write) accesses 1786system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022388 # miss rate for ReadReq accesses 1787system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.079186 # miss rate for ReadReq accesses 1788system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.022006 # miss rate for ReadReq accesses 1789system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.383272 # miss rate for ReadReq accesses 1790system.cpu1.l2cache.ReadReq_miss_rate::total 0.077474 # miss rate for ReadReq accesses 1791system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.949225 # miss rate for UpgradeReq accesses 1792system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.949225 # miss rate for UpgradeReq accesses 1793system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.960241 # miss rate for SCUpgradeReq accesses 1794system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.960241 # miss rate for SCUpgradeReq accesses 1795system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.563248 # miss rate for ReadExReq accesses 1796system.cpu1.l2cache.ReadExReq_miss_rate::total 0.563248 # miss rate for ReadExReq accesses 1797system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022388 # miss rate for demand accesses 1798system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.079186 # miss rate for demand accesses 1799system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.022006 # miss rate for demand accesses 1800system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.430206 # miss rate for demand accesses 1801system.cpu1.l2cache.demand_miss_rate::total 0.102371 # miss rate for demand accesses 1802system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022388 # miss rate for overall accesses 1803system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.079186 # miss rate for overall accesses 1804system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.022006 # miss rate for overall accesses 1805system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.430206 # miss rate for overall accesses 1806system.cpu1.l2cache.overall_miss_rate::total 0.102371 # miss rate for overall accesses 1807system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23750.357032 # average ReadReq miss latency 1808system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20146.788991 # average ReadReq miss latency 1809system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 35127.643582 # average ReadReq miss latency 1810system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21905.892745 # average ReadReq miss latency 1811system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24992.763214 # average ReadReq miss latency 1812system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18991.672731 # average UpgradeReq miss latency 1813system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18991.672731 # average UpgradeReq miss latency 1814system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20190.823589 # average SCUpgradeReq miss latency 1815system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20190.823589 # average SCUpgradeReq miss latency |
| 1815system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency 1816system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency | 1816system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency 1817system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency |
| 1817system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 37590.396472 # average ReadExReq miss latency 1818system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 37590.396472 # average ReadExReq miss latency 1819system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21363.599349 # average overall miss latency 1820system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19796.794521 # average overall miss latency 1821system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 31042.263952 # average overall miss latency 1822system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27019.819404 # average overall miss latency 1823system.cpu1.l2cache.demand_avg_miss_latency::total 27604.258030 # average overall miss latency 1824system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21363.599349 # average overall miss latency 1825system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19796.794521 # average overall miss latency 1826system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 31042.263952 # average overall miss latency 1827system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27019.819404 # average overall miss latency 1828system.cpu1.l2cache.overall_avg_miss_latency::total 27604.258030 # average overall miss latency | 1818system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39532.584364 # average ReadExReq miss latency 1819system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39532.584364 # average ReadExReq miss latency 1820system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23750.357032 # average overall miss latency 1821system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20146.788991 # average overall miss latency 1822system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35127.643582 # average overall miss latency 1823system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27924.121812 # average overall miss latency 1824system.cpu1.l2cache.demand_avg_miss_latency::total 29092.963002 # average overall miss latency 1825system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23750.357032 # average overall miss latency 1826system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20146.788991 # average overall miss latency 1827system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35127.643582 # average overall miss latency 1828system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27924.121812 # average overall miss latency 1829system.cpu1.l2cache.overall_avg_miss_latency::total 29092.963002 # average overall miss latency |
| 1829system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1830system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1831system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1832system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1833system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1834system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1835system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1836system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 1830system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1831system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1832system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1833system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1834system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1835system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1836system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1837system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 1837system.cpu1.l2cache.writebacks::writebacks 33019 # number of writebacks 1838system.cpu1.l2cache.writebacks::total 33019 # number of writebacks 1839system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 18 # number of ReadReq MSHR hits 1840system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 88 # number of ReadReq MSHR hits 1841system.cpu1.l2cache.ReadReq_mshr_hits::total 106 # number of ReadReq MSHR hits 1842system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 284 # number of ReadExReq MSHR hits 1843system.cpu1.l2cache.ReadExReq_mshr_hits::total 284 # number of ReadExReq MSHR hits 1844system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 18 # number of demand (read+write) MSHR hits 1845system.cpu1.l2cache.demand_mshr_hits::cpu1.data 372 # number of demand (read+write) MSHR hits 1846system.cpu1.l2cache.demand_mshr_hits::total 390 # number of demand (read+write) MSHR hits 1847system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 18 # number of overall MSHR hits 1848system.cpu1.l2cache.overall_mshr_hits::cpu1.data 372 # number of overall MSHR hits 1849system.cpu1.l2cache.overall_mshr_hits::total 390 # number of overall MSHR hits 1850system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 614 # number of ReadReq MSHR misses 1851system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 219 # number of ReadReq MSHR misses 1852system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 18940 # number of ReadReq MSHR misses 1853system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 66918 # number of ReadReq MSHR misses 1854system.cpu1.l2cache.ReadReq_mshr_misses::total 86691 # number of ReadReq MSHR misses 1855system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25785 # number of HardPFReq MSHR misses 1856system.cpu1.l2cache.HardPFReq_mshr_misses::total 25785 # number of HardPFReq MSHR misses 1857system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28133 # number of UpgradeReq MSHR misses 1858system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28133 # number of UpgradeReq MSHR misses 1859system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22540 # number of SCUpgradeReq MSHR misses 1860system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22540 # number of SCUpgradeReq MSHR misses 1861system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34750 # number of ReadExReq MSHR misses 1862system.cpu1.l2cache.ReadExReq_mshr_misses::total 34750 # number of ReadExReq MSHR misses 1863system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 614 # number of demand (read+write) MSHR misses 1864system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 219 # number of demand (read+write) MSHR misses 1865system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 18940 # number of demand (read+write) MSHR misses 1866system.cpu1.l2cache.demand_mshr_misses::cpu1.data 101668 # number of demand (read+write) MSHR misses 1867system.cpu1.l2cache.demand_mshr_misses::total 121441 # number of demand (read+write) MSHR misses 1868system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 614 # number of overall MSHR misses 1869system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 219 # number of overall MSHR misses 1870system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 18940 # number of overall MSHR misses 1871system.cpu1.l2cache.overall_mshr_misses::cpu1.data 101668 # number of overall MSHR misses 1872system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25785 # number of overall MSHR misses 1873system.cpu1.l2cache.overall_mshr_misses::total 147226 # number of overall MSHR misses 1874system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 8818750 # number of ReadReq MSHR miss cycles 1875system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2802498 # number of ReadReq MSHR miss cycles 1876system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 454726510 # number of ReadReq MSHR miss cycles 1877system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 969167182 # number of ReadReq MSHR miss cycles 1878system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1435514940 # number of ReadReq MSHR miss cycles 1879system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1025770621 # number of HardPFReq MSHR miss cycles 1880system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1025770621 # number of HardPFReq MSHR miss cycles 1881system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 399929245 # number of UpgradeReq MSHR miss cycles 1882system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 399929245 # number of UpgradeReq MSHR miss cycles 1883system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306606785 # number of SCUpgradeReq MSHR miss cycles 1884system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306606785 # number of SCUpgradeReq MSHR miss cycles 1885system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 145000 # number of SCUpgradeFailReq MSHR miss cycles 1886system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 145000 # number of SCUpgradeFailReq MSHR miss cycles 1887system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1042779776 # number of ReadExReq MSHR miss cycles 1888system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1042779776 # number of ReadExReq MSHR miss cycles 1889system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 8818750 # number of demand (read+write) MSHR miss cycles 1890system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2802498 # number of demand (read+write) MSHR miss cycles 1891system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 454726510 # number of demand (read+write) MSHR miss cycles 1892system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2011946958 # number of demand (read+write) MSHR miss cycles 1893system.cpu1.l2cache.demand_mshr_miss_latency::total 2478294716 # number of demand (read+write) MSHR miss cycles 1894system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 8818750 # number of overall MSHR miss cycles 1895system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2802498 # number of overall MSHR miss cycles 1896system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 454726510 # number of overall MSHR miss cycles 1897system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2011946958 # number of overall MSHR miss cycles 1898system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1025770621 # number of overall MSHR miss cycles 1899system.cpu1.l2cache.overall_mshr_miss_latency::total 3504065337 # number of overall MSHR miss cycles 1900system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9029750 # number of ReadReq MSHR uncacheable cycles 1901system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 307917500 # number of ReadReq MSHR uncacheable cycles 1902system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 316947250 # number of ReadReq MSHR uncacheable cycles 1903system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 187186000 # number of WriteReq MSHR uncacheable cycles 1904system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 187186000 # number of WriteReq MSHR uncacheable cycles 1905system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9029750 # number of overall MSHR uncacheable cycles 1906system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 495103500 # number of overall MSHR uncacheable cycles 1907system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 504133250 # number of overall MSHR uncacheable cycles 1908system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for ReadReq accesses 1909system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for ReadReq accesses 1910system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.020847 # mshr miss rate for ReadReq accesses 1911system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.390523 # mshr miss rate for ReadReq accesses 1912system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.077996 # mshr miss rate for ReadReq accesses | 1838system.cpu1.l2cache.writebacks::writebacks 32039 # number of writebacks 1839system.cpu1.l2cache.writebacks::total 32039 # number of writebacks 1840system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 17 # number of ReadReq MSHR hits 1841system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 99 # number of ReadReq MSHR hits 1842system.cpu1.l2cache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits 1843system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 227 # number of ReadExReq MSHR hits 1844system.cpu1.l2cache.ReadExReq_mshr_hits::total 227 # number of ReadExReq MSHR hits 1845system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits 1846system.cpu1.l2cache.demand_mshr_hits::cpu1.data 326 # number of demand (read+write) MSHR hits 1847system.cpu1.l2cache.demand_mshr_hits::total 343 # number of demand (read+write) MSHR hits 1848system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits 1849system.cpu1.l2cache.overall_mshr_hits::cpu1.data 326 # number of overall MSHR hits 1850system.cpu1.l2cache.overall_mshr_hits::total 343 # number of overall MSHR hits 1851system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 647 # number of ReadReq MSHR misses 1852system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 218 # number of ReadReq MSHR misses 1853system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 20877 # number of ReadReq MSHR misses 1854system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 67898 # number of ReadReq MSHR misses 1855system.cpu1.l2cache.ReadReq_mshr_misses::total 89640 # number of ReadReq MSHR misses 1856system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 27323 # number of HardPFReq MSHR misses 1857system.cpu1.l2cache.HardPFReq_mshr_misses::total 27323 # number of HardPFReq MSHR misses 1858system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28472 # number of UpgradeReq MSHR misses 1859system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28472 # number of UpgradeReq MSHR misses 1860system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22799 # number of SCUpgradeReq MSHR misses 1861system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22799 # number of SCUpgradeReq MSHR misses 1862system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35025 # number of ReadExReq MSHR misses 1863system.cpu1.l2cache.ReadExReq_mshr_misses::total 35025 # number of ReadExReq MSHR misses 1864system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 647 # number of demand (read+write) MSHR misses 1865system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 218 # number of demand (read+write) MSHR misses 1866system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 20877 # number of demand (read+write) MSHR misses 1867system.cpu1.l2cache.demand_mshr_misses::cpu1.data 102923 # number of demand (read+write) MSHR misses 1868system.cpu1.l2cache.demand_mshr_misses::total 124665 # number of demand (read+write) MSHR misses 1869system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 647 # number of overall MSHR misses 1870system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 218 # number of overall MSHR misses 1871system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 20877 # number of overall MSHR misses 1872system.cpu1.l2cache.overall_mshr_misses::cpu1.data 102923 # number of overall MSHR misses 1873system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 27323 # number of overall MSHR misses 1874system.cpu1.l2cache.overall_mshr_misses::total 151988 # number of overall MSHR misses 1875system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 11152993 # number of ReadReq MSHR miss cycles 1876system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2975000 # number of ReadReq MSHR miss cycles 1877system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 596579765 # number of ReadReq MSHR miss cycles 1878system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1045445755 # number of ReadReq MSHR miss cycles 1879system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1656153513 # number of ReadReq MSHR miss cycles 1880system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 967597598 # number of HardPFReq MSHR miss cycles 1881system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 967597598 # number of HardPFReq MSHR miss cycles 1882system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 454341493 # number of UpgradeReq MSHR miss cycles 1883system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 454341493 # number of UpgradeReq MSHR miss cycles 1884system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 344269721 # number of SCUpgradeReq MSHR miss cycles 1885system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 344269721 # number of SCUpgradeReq MSHR miss cycles 1886system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 298500 # number of SCUpgradeFailReq MSHR miss cycles 1887system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 298500 # number of SCUpgradeFailReq MSHR miss cycles 1888system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1133512279 # number of ReadExReq MSHR miss cycles 1889system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1133512279 # number of ReadExReq MSHR miss cycles 1890system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 11152993 # number of demand (read+write) MSHR miss cycles 1891system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2975000 # number of demand (read+write) MSHR miss cycles 1892system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 596579765 # number of demand (read+write) MSHR miss cycles 1893system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2178958034 # number of demand (read+write) MSHR miss cycles 1894system.cpu1.l2cache.demand_mshr_miss_latency::total 2789665792 # number of demand (read+write) MSHR miss cycles 1895system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 11152993 # number of overall MSHR miss cycles 1896system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2975000 # number of overall MSHR miss cycles 1897system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 596579765 # number of overall MSHR miss cycles 1898system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2178958034 # number of overall MSHR miss cycles 1899system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 967597598 # number of overall MSHR miss cycles 1900system.cpu1.l2cache.overall_mshr_miss_latency::total 3757263390 # number of overall MSHR miss cycles 1901system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9248000 # number of ReadReq MSHR uncacheable cycles 1902system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2205503500 # number of ReadReq MSHR uncacheable cycles 1903system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2214751500 # number of ReadReq MSHR uncacheable cycles 1904system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1754476501 # number of WriteReq MSHR uncacheable cycles 1905system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1754476501 # number of WriteReq MSHR uncacheable cycles 1906system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9248000 # number of overall MSHR uncacheable cycles 1907system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3959980001 # number of overall MSHR uncacheable cycles 1908system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3969228001 # number of overall MSHR uncacheable cycles 1909system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022388 # mshr miss rate for ReadReq accesses 1910system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.079186 # mshr miss rate for ReadReq accesses 1911system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.021988 # mshr miss rate for ReadReq accesses 1912system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.382714 # mshr miss rate for ReadReq accesses 1913system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.077373 # mshr miss rate for ReadReq accesses |
| 1913system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1914system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1914system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1915system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1915system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.946124 # mshr miss rate for UpgradeReq accesses 1916system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.946124 # mshr miss rate for UpgradeReq accesses 1917system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962220 # mshr miss rate for SCUpgradeReq accesses 1918system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962220 # mshr miss rate for SCUpgradeReq accesses 1919system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.579041 # mshr miss rate for ReadExReq accesses 1920system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.579041 # mshr miss rate for ReadExReq accesses 1921system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for demand accesses 1922system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for demand accesses 1923system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.020847 # mshr miss rate for demand accesses 1924system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.439421 # mshr miss rate for demand accesses 1925system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103663 # mshr miss rate for demand accesses 1926system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for overall accesses 1927system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for overall accesses 1928system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.020847 # mshr miss rate for overall accesses 1929system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.439421 # mshr miss rate for overall accesses | 1916system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.949225 # mshr miss rate for UpgradeReq accesses 1917system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.949225 # mshr miss rate for UpgradeReq accesses 1918system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.960241 # mshr miss rate for SCUpgradeReq accesses 1919system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.960241 # mshr miss rate for SCUpgradeReq accesses 1920system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.559621 # mshr miss rate for ReadExReq accesses 1921system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.559621 # mshr miss rate for ReadExReq accesses 1922system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022388 # mshr miss rate for demand accesses 1923system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.079186 # mshr miss rate for demand accesses 1924system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.021988 # mshr miss rate for demand accesses 1925system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.428848 # mshr miss rate for demand accesses 1926system.cpu1.l2cache.demand_mshr_miss_rate::total 0.102090 # mshr miss rate for demand accesses 1927system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022388 # mshr miss rate for overall accesses 1928system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.079186 # mshr miss rate for overall accesses 1929system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.021988 # mshr miss rate for overall accesses 1930system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.428848 # mshr miss rate for overall accesses |
| 1930system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1931system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1931system.cpu1.l2cache.overall_mshr_miss_rate::total 0.125673 # mshr miss rate for overall accesses 1932system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average ReadReq mshr miss latency 1933system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average ReadReq mshr miss latency 1934system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 24008.791447 # average ReadReq mshr miss latency 1935system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14482.907170 # average ReadReq mshr miss latency 1936system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16558.984670 # average ReadReq mshr miss latency 1937system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085 # average HardPFReq mshr miss latency 1938system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39781.680085 # average HardPFReq mshr miss latency 1939system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14215.662923 # average UpgradeReq mshr miss latency 1940system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14215.662923 # average UpgradeReq mshr miss latency 1941system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13602.785492 # average SCUpgradeReq mshr miss latency 1942system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13602.785492 # average SCUpgradeReq mshr miss latency | 1932system.cpu1.l2cache.overall_mshr_miss_rate::total 0.124466 # mshr miss rate for overall accesses 1933system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17238.010819 # average ReadReq mshr miss latency 1934system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13646.788991 # average ReadReq mshr miss latency 1935system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28575.933563 # average ReadReq mshr miss latency 1936system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15397.298227 # average ReadReq mshr miss latency 1937system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18475.608133 # average ReadReq mshr miss latency 1938system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35413.300077 # average HardPFReq mshr miss latency 1939system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35413.300077 # average HardPFReq mshr miss latency 1940system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15957.484300 # average UpgradeReq mshr miss latency 1941system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15957.484300 # average UpgradeReq mshr miss latency 1942system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15100.211457 # average SCUpgradeReq mshr miss latency 1943system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15100.211457 # average SCUpgradeReq mshr miss latency |
| 1943system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency 1944system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency | 1944system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency 1945system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency |
| 1945system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30008.051108 # average ReadExReq mshr miss latency 1946system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30008.051108 # average ReadExReq mshr miss latency 1947system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average overall mshr miss latency 1948system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average overall mshr miss latency 1949system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 24008.791447 # average overall mshr miss latency 1950system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19789.382677 # average overall mshr miss latency 1951system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20407.397139 # average overall mshr miss latency 1952system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average overall mshr miss latency 1953system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average overall mshr miss latency 1954system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 24008.791447 # average overall mshr miss latency 1955system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19789.382677 # average overall mshr miss latency 1956system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085 # average overall mshr miss latency 1957system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23800.587783 # average overall mshr miss latency | 1946system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32362.948722 # average ReadExReq mshr miss latency 1947system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32362.948722 # average ReadExReq mshr miss latency 1948system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17238.010819 # average overall mshr miss latency 1949system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13646.788991 # average overall mshr miss latency 1950system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28575.933563 # average overall mshr miss latency 1951system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21170.759053 # average overall mshr miss latency 1952system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22377.297493 # average overall mshr miss latency 1953system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17238.010819 # average overall mshr miss latency 1954system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13646.788991 # average overall mshr miss latency 1955system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28575.933563 # average overall mshr miss latency 1956system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21170.759053 # average overall mshr miss latency 1957system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35413.300077 # average overall mshr miss latency 1958system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24720.789733 # average overall mshr miss latency |
| 1958system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1959system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1960system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1961system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1962system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1963system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1964system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1965system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1966system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1959system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1960system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1961system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1962system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1963system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1964system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1965system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1966system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1967system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1967system.cpu1.toL2Bus.trans_dist::ReadReq 1492249 # Transaction distribution 1968system.cpu1.toL2Bus.trans_dist::ReadResp 1157222 # Transaction distribution 1969system.cpu1.toL2Bus.trans_dist::WriteReq 2126 # Transaction distribution 1970system.cpu1.toL2Bus.trans_dist::WriteResp 2126 # Transaction distribution 1971system.cpu1.toL2Bus.trans_dist::Writeback 113900 # Transaction distribution 1972system.cpu1.toL2Bus.trans_dist::HardPFReq 36842 # Transaction distribution 1973system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1974system.cpu1.toL2Bus.trans_dist::UpgradeReq 74786 # Transaction distribution 1975system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41424 # Transaction distribution 1976system.cpu1.toL2Bus.trans_dist::UpgradeResp 85596 # Transaction distribution 1977system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution 1978system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 13 # Transaction distribution 1979system.cpu1.toL2Bus.trans_dist::ReadExReq 82199 # Transaction distribution 1980system.cpu1.toL2Bus.trans_dist::ReadExResp 64364 # Transaction distribution 1981system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1817284 # Packet count per connected master and slave (bytes) 1982system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 767101 # Packet count per connected master and slave (bytes) 1983system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7150 # Packet count per connected master and slave (bytes) 1984system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 61380 # Packet count per connected master and slave (bytes) 1985system.cpu1.toL2Bus.pkt_count::total 2652915 # Packet count per connected master and slave (bytes) 1986system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 58153088 # Cumulative packet size per connected master and slave (bytes) 1987system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24793955 # Cumulative packet size per connected master and slave (bytes) 1988system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11380 # Cumulative packet size per connected master and slave (bytes) 1989system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 115036 # Cumulative packet size per connected master and slave (bytes) 1990system.cpu1.toL2Bus.pkt_size::total 83073459 # Cumulative packet size per connected master and slave (bytes) 1991system.cpu1.toL2Bus.snoops 610470 # Total snoops (count) 1992system.cpu1.toL2Bus.snoop_fanout::samples 1874725 # Request fanout histogram 1993system.cpu1.toL2Bus.snoop_fanout::mean 5.283158 # Request fanout histogram 1994system.cpu1.toL2Bus.snoop_fanout::stdev 0.450533 # Request fanout histogram | 1968system.cpu1.toL2Bus.trans_dist::ReadReq 1549513 # Transaction distribution 1969system.cpu1.toL2Bus.trans_dist::ReadResp 1217389 # Transaction distribution 1970system.cpu1.toL2Bus.trans_dist::WriteReq 11941 # Transaction distribution 1971system.cpu1.toL2Bus.trans_dist::WriteResp 11941 # Transaction distribution 1972system.cpu1.toL2Bus.trans_dist::Writeback 120163 # Transaction distribution 1973system.cpu1.toL2Bus.trans_dist::HardPFReq 34752 # Transaction distribution 1974system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36265 # Transaction distribution 1975system.cpu1.toL2Bus.trans_dist::UpgradeReq 76638 # Transaction distribution 1976system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42182 # Transaction distribution 1977system.cpu1.toL2Bus.trans_dist::UpgradeResp 86369 # Transaction distribution 1978system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution 1979system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution 1980system.cpu1.toL2Bus.trans_dist::ReadExReq 85047 # Transaction distribution 1981system.cpu1.toL2Bus.trans_dist::ReadExResp 67036 # Transaction distribution 1982system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1899176 # Packet count per connected master and slave (bytes) 1983system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 835933 # Packet count per connected master and slave (bytes) 1984system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7082 # Packet count per connected master and slave (bytes) 1985system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62248 # Packet count per connected master and slave (bytes) 1986system.cpu1.toL2Bus.pkt_count::total 2804439 # Packet count per connected master and slave (bytes) 1987system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60773632 # Cumulative packet size per connected master and slave (bytes) 1988system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25876936 # Cumulative packet size per connected master and slave (bytes) 1989system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11012 # Cumulative packet size per connected master and slave (bytes) 1990system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 115596 # Cumulative packet size per connected master and slave (bytes) 1991system.cpu1.toL2Bus.pkt_size::total 86777176 # Cumulative packet size per connected master and slave (bytes) 1992system.cpu1.toL2Bus.snoops 610005 # Total snoops (count) 1993system.cpu1.toL2Bus.snoop_fanout::samples 1929839 # Request fanout histogram 1994system.cpu1.toL2Bus.snoop_fanout::mean 3.274006 # Request fanout histogram 1995system.cpu1.toL2Bus.snoop_fanout::stdev 0.446012 # Request fanout histogram |
| 1995system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1996system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1997system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1998system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 1996system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1997system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1998system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1999system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 1999system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2000system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 2001system.cpu1.toL2Bus.snoop_fanout::5 1343882 71.68% 71.68% # Request fanout histogram 2002system.cpu1.toL2Bus.snoop_fanout::6 530843 28.32% 100.00% # Request fanout histogram | 2000system.cpu1.toL2Bus.snoop_fanout::3 1401052 72.60% 72.60% # Request fanout histogram 2001system.cpu1.toL2Bus.snoop_fanout::4 528787 27.40% 100.00% # Request fanout histogram |
| 2003system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 2002system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 2004system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2005system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 2006system.cpu1.toL2Bus.snoop_fanout::total 1874725 # Request fanout histogram 2007system.cpu1.toL2Bus.reqLayer0.occupancy 789561722 # Layer occupancy (ticks) | 2003system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 2004system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 2005system.cpu1.toL2Bus.snoop_fanout::total 1929839 # Request fanout histogram 2006system.cpu1.toL2Bus.reqLayer0.occupancy 840003478 # Layer occupancy (ticks) |
| 2008system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 2007system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 2009system.cpu1.toL2Bus.snoopLayer0.occupancy 79017500 # Layer occupancy (ticks) | 2008system.cpu1.toL2Bus.snoopLayer0.occupancy 80148998 # Layer occupancy (ticks) |
| 2010system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2009system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2011system.cpu1.toL2Bus.respLayer0.occupancy 1364909988 # Layer occupancy (ticks) 2012system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2013system.cpu1.toL2Bus.respLayer1.occupancy 381206023 # Layer occupancy (ticks) | 2010system.cpu1.toL2Bus.respLayer0.occupancy 1425055438 # Layer occupancy (ticks) 2011system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 2012system.cpu1.toL2Bus.respLayer1.occupancy 412471555 # Layer occupancy (ticks) |
| 2014system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 2013system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 2015system.cpu1.toL2Bus.respLayer2.occupancy 4307495 # Layer occupancy (ticks) | 2014system.cpu1.toL2Bus.respLayer2.occupancy 4329500 # Layer occupancy (ticks) |
| 2016system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 2015system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2017system.cpu1.toL2Bus.respLayer3.occupancy 32623745 # Layer occupancy (ticks) | 2016system.cpu1.toL2Bus.respLayer3.occupancy 33365476 # Layer occupancy (ticks) |
| 2018system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2017system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2019system.iobus.trans_dist::ReadReq 31012 # Transaction distribution 2020system.iobus.trans_dist::ReadResp 31012 # Transaction distribution 2021system.iobus.trans_dist::WriteReq 59440 # Transaction distribution 2022system.iobus.trans_dist::WriteResp 23216 # Transaction distribution | 2018system.iobus.trans_dist::ReadReq 31015 # Transaction distribution 2019system.iobus.trans_dist::ReadResp 31015 # Transaction distribution 2020system.iobus.trans_dist::WriteReq 59422 # Transaction distribution 2021system.iobus.trans_dist::WriteResp 23198 # Transaction distribution |
| 2023system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution | 2022system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 2024system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) | 2023system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) |
| 2025system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2026system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2027system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2028system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2029system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2030system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2031system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2032system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 2037system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2038system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2039system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2040system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2041system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2042system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2043system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2044system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 2024system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2025system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2026system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2027system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2028system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2029system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2030system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2031system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 2036system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2037system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2038system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2039system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2040system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2041system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2042system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2043system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 2045system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) 2046system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) 2047system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) 2048system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) 2049system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) | 2044system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) 2045system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) 2046system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) 2047system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) 2048system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) |
| 2050system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2051system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2052system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2053system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2054system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2055system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2056system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2057system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 2062system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2063system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2064system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2065system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2066system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 2067system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2068system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 2069system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | 2049system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2050system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2051system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2052system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2053system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2054system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2055system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2056system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 2061system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2062system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2063system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2064system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2065system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 2066system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2067system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 2068system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 2070system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) 2071system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) 2072system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) 2073system.iobus.pkt_size::total 2484026 # Cumulative packet size per connected master and slave (bytes) 2074system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) | 2069system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) 2070system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) 2071system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) 2072system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) 2073system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) |
| 2075system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2076system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 2077system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2078system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 2079system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2080system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 2081system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2082system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) --- 23 unchanged lines hidden (view full) --- 2106system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2107system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2108system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2109system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2110system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2111system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2112system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2113system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 2074system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2075system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 2076system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2077system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 2078system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2079system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 2080system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2081system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) --- 23 unchanged lines hidden (view full) --- 2105system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2106system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2107system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2108system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2109system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2110system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2111system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2112system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 2114system.iobus.reqLayer27.occupancy 347036169 # Layer occupancy (ticks) | 2113system.iobus.reqLayer27.occupancy 199065929 # Layer occupancy (ticks) |
| 2115system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2116system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2117system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 2114system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2115system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2116system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 2118system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) | 2117system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) |
| 2119system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 2118system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2120system.iobus.respLayer3.occupancy 36822569 # Layer occupancy (ticks) | 2119system.iobus.respLayer3.occupancy 36796533 # Layer occupancy (ticks) |
| 2121system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 2120system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2122system.iocache.tags.replacements 36417 # number of replacements 2123system.iocache.tags.tagsinuse 0.997930 # Cycle average of tags in use | 2121system.iocache.tags.replacements 36445 # number of replacements 2122system.iocache.tags.tagsinuse 14.480362 # Cycle average of tags in use |
| 2124system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 2123system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 2125system.iocache.tags.sampled_refs 36433 # Sample count of references to valid blocks. | 2124system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. |
| 2126system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 2125system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 2127system.iocache.tags.warmup_cycle 269849823000 # Cycle when the warmup percentage was hit. 2128system.iocache.tags.occ_blocks::realview.ide 0.997930 # Average occupied blocks per requestor 2129system.iocache.tags.occ_percent::realview.ide 0.062371 # Average percentage of cache occupancy 2130system.iocache.tags.occ_percent::total 0.062371 # Average percentage of cache occupancy | 2126system.iocache.tags.warmup_cycle 270133806000 # Cycle when the warmup percentage was hit. 2127system.iocache.tags.occ_blocks::realview.ide 14.480362 # Average occupied blocks per requestor 2128system.iocache.tags.occ_percent::realview.ide 0.905023 # Average percentage of cache occupancy 2129system.iocache.tags.occ_percent::total 0.905023 # Average percentage of cache occupancy |
| 2131system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2132system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2133system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 2130system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2131system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2132system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 2134system.iocache.tags.tag_accesses 328203 # Number of tag accesses 2135system.iocache.tags.data_accesses 328203 # Number of data accesses 2136system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses 2137system.iocache.ReadReq_misses::total 243 # number of ReadReq misses | 2133system.iocache.tags.tag_accesses 328311 # Number of tag accesses 2134system.iocache.tags.data_accesses 328311 # Number of data accesses 2135system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses 2136system.iocache.ReadReq_misses::total 255 # number of ReadReq misses |
| 2138system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 2139system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses | 2137system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 2138system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses |
| 2140system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses 2141system.iocache.demand_misses::total 243 # number of demand (read+write) misses 2142system.iocache.overall_misses::realview.ide 243 # number of overall misses 2143system.iocache.overall_misses::total 243 # number of overall misses 2144system.iocache.ReadReq_miss_latency::realview.ide 30354377 # number of ReadReq miss cycles 2145system.iocache.ReadReq_miss_latency::total 30354377 # number of ReadReq miss cycles 2146system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9625347223 # number of WriteInvalidateReq miss cycles 2147system.iocache.WriteInvalidateReq_miss_latency::total 9625347223 # number of WriteInvalidateReq miss cycles 2148system.iocache.demand_miss_latency::realview.ide 30354377 # number of demand (read+write) miss cycles 2149system.iocache.demand_miss_latency::total 30354377 # number of demand (read+write) miss cycles 2150system.iocache.overall_miss_latency::realview.ide 30354377 # number of overall miss cycles 2151system.iocache.overall_miss_latency::total 30354377 # number of overall miss cycles 2152system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) 2153system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) | 2139system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses 2140system.iocache.demand_misses::total 255 # number of demand (read+write) misses 2141system.iocache.overall_misses::realview.ide 255 # number of overall misses 2142system.iocache.overall_misses::total 255 # number of overall misses 2143system.iocache.ReadReq_miss_latency::realview.ide 32660377 # number of ReadReq miss cycles 2144system.iocache.ReadReq_miss_latency::total 32660377 # number of ReadReq miss cycles 2145system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6669320019 # number of WriteInvalidateReq miss cycles 2146system.iocache.WriteInvalidateReq_miss_latency::total 6669320019 # number of WriteInvalidateReq miss cycles 2147system.iocache.demand_miss_latency::realview.ide 32660377 # number of demand (read+write) miss cycles 2148system.iocache.demand_miss_latency::total 32660377 # number of demand (read+write) miss cycles 2149system.iocache.overall_miss_latency::realview.ide 32660377 # number of overall miss cycles 2150system.iocache.overall_miss_latency::total 32660377 # number of overall miss cycles 2151system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) 2152system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) |
| 2154system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 2155system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) | 2153system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 2154system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) |
| 2156system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses 2157system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses 2158system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses 2159system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses | 2155system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses 2156system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses 2157system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses 2158system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses |
| 2160system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2161system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2162system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2163system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2164system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2165system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2166system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2167system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 2159system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2160system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2161system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2162system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2163system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2164system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2165system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2166system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 2168system.iocache.ReadReq_avg_miss_latency::realview.ide 124915.131687 # average ReadReq miss latency 2169system.iocache.ReadReq_avg_miss_latency::total 124915.131687 # average ReadReq miss latency 2170system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265717.403462 # average WriteInvalidateReq miss latency 2171system.iocache.WriteInvalidateReq_avg_miss_latency::total 265717.403462 # average WriteInvalidateReq miss latency 2172system.iocache.demand_avg_miss_latency::realview.ide 124915.131687 # average overall miss latency 2173system.iocache.demand_avg_miss_latency::total 124915.131687 # average overall miss latency 2174system.iocache.overall_avg_miss_latency::realview.ide 124915.131687 # average overall miss latency 2175system.iocache.overall_avg_miss_latency::total 124915.131687 # average overall miss latency 2176system.iocache.blocked_cycles::no_mshrs 56938 # number of cycles access was blocked | 2167system.iocache.ReadReq_avg_miss_latency::realview.ide 128079.909804 # average ReadReq miss latency 2168system.iocache.ReadReq_avg_miss_latency::total 128079.909804 # average ReadReq miss latency 2169system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 184113.295578 # average WriteInvalidateReq miss latency 2170system.iocache.WriteInvalidateReq_avg_miss_latency::total 184113.295578 # average WriteInvalidateReq miss latency 2171system.iocache.demand_avg_miss_latency::realview.ide 128079.909804 # average overall miss latency 2172system.iocache.demand_avg_miss_latency::total 128079.909804 # average overall miss latency 2173system.iocache.overall_avg_miss_latency::realview.ide 128079.909804 # average overall miss latency 2174system.iocache.overall_avg_miss_latency::total 128079.909804 # average overall miss latency 2175system.iocache.blocked_cycles::no_mshrs 23275 # number of cycles access was blocked |
| 2177system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2176system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2178system.iocache.blocked::no_mshrs 7266 # number of cycles access was blocked | 2177system.iocache.blocked::no_mshrs 3594 # number of cycles access was blocked |
| 2179system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 2178system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 2180system.iocache.avg_blocked_cycles::no_mshrs 7.836224 # average number of cycles each access was blocked | 2179system.iocache.avg_blocked_cycles::no_mshrs 6.476071 # average number of cycles each access was blocked |
| 2181system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2182system.iocache.fast_writes 0 # number of fast writes performed 2183system.iocache.cache_copies 0 # number of cache copies performed | 2180system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2181system.iocache.fast_writes 0 # number of fast writes performed 2182system.iocache.cache_copies 0 # number of cache copies performed |
| 2184system.iocache.writebacks::writebacks 36174 # number of writebacks 2185system.iocache.writebacks::total 36174 # number of writebacks 2186system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses 2187system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses | 2183system.iocache.writebacks::writebacks 36190 # number of writebacks 2184system.iocache.writebacks::total 36190 # number of writebacks 2185system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses 2186system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses |
| 2188system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 2189system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses | 2187system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 2188system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses |
| 2190system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses 2191system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses 2192system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses 2193system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses 2194system.iocache.ReadReq_mshr_miss_latency::realview.ide 17717377 # number of ReadReq MSHR miss cycles 2195system.iocache.ReadReq_mshr_miss_latency::total 17717377 # number of ReadReq MSHR miss cycles 2196system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7741561361 # number of WriteInvalidateReq MSHR miss cycles 2197system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7741561361 # number of WriteInvalidateReq MSHR miss cycles 2198system.iocache.demand_mshr_miss_latency::realview.ide 17717377 # number of demand (read+write) MSHR miss cycles 2199system.iocache.demand_mshr_miss_latency::total 17717377 # number of demand (read+write) MSHR miss cycles 2200system.iocache.overall_mshr_miss_latency::realview.ide 17717377 # number of overall MSHR miss cycles 2201system.iocache.overall_mshr_miss_latency::total 17717377 # number of overall MSHR miss cycles | 2189system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses 2190system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses 2191system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses 2192system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses 2193system.iocache.ReadReq_mshr_miss_latency::realview.ide 19371377 # number of ReadReq MSHR miss cycles 2194system.iocache.ReadReq_mshr_miss_latency::total 19371377 # number of ReadReq MSHR miss cycles 2195system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4785606085 # number of WriteInvalidateReq MSHR miss cycles 2196system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4785606085 # number of WriteInvalidateReq MSHR miss cycles 2197system.iocache.demand_mshr_miss_latency::realview.ide 19371377 # number of demand (read+write) MSHR miss cycles 2198system.iocache.demand_mshr_miss_latency::total 19371377 # number of demand (read+write) MSHR miss cycles 2199system.iocache.overall_mshr_miss_latency::realview.ide 19371377 # number of overall MSHR miss cycles 2200system.iocache.overall_mshr_miss_latency::total 19371377 # number of overall MSHR miss cycles |
| 2202system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2203system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2204system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2205system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 2206system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2207system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2208system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2209system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 2201system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2202system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2203system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2204system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 2205system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2206system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2207system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2208system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 2210system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72911.016461 # average ReadReq mshr miss latency 2211system.iocache.ReadReq_avg_mshr_miss_latency::total 72911.016461 # average ReadReq mshr miss latency 2212system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213713.597642 # average WriteInvalidateReq mshr miss latency 2213system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213713.597642 # average WriteInvalidateReq mshr miss latency 2214system.iocache.demand_avg_mshr_miss_latency::realview.ide 72911.016461 # average overall mshr miss latency 2215system.iocache.demand_avg_mshr_miss_latency::total 72911.016461 # average overall mshr miss latency 2216system.iocache.overall_avg_mshr_miss_latency::realview.ide 72911.016461 # average overall mshr miss latency 2217system.iocache.overall_avg_mshr_miss_latency::total 72911.016461 # average overall mshr miss latency | 2209system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75966.184314 # average ReadReq mshr miss latency 2210system.iocache.ReadReq_avg_mshr_miss_latency::total 75966.184314 # average ReadReq mshr miss latency 2211system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 132111.475403 # average WriteInvalidateReq mshr miss latency 2212system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 132111.475403 # average WriteInvalidateReq mshr miss latency 2213system.iocache.demand_avg_mshr_miss_latency::realview.ide 75966.184314 # average overall mshr miss latency 2214system.iocache.demand_avg_mshr_miss_latency::total 75966.184314 # average overall mshr miss latency 2215system.iocache.overall_avg_mshr_miss_latency::realview.ide 75966.184314 # average overall mshr miss latency 2216system.iocache.overall_avg_mshr_miss_latency::total 75966.184314 # average overall mshr miss latency |
| 2218system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 2217system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2219system.l2c.tags.replacements 139153 # number of replacements 2220system.l2c.tags.tagsinuse 64176.379405 # Cycle average of tags in use 2221system.l2c.tags.total_refs 380612 # Total number of references to valid blocks. 2222system.l2c.tags.sampled_refs 203608 # Sample count of references to valid blocks. 2223system.l2c.tags.avg_refs 1.869337 # Average number of references to valid blocks. | 2218system.l2c.tags.replacements 135784 # number of replacements 2219system.l2c.tags.tagsinuse 63989.836026 # Cycle average of tags in use 2220system.l2c.tags.total_refs 379813 # Total number of references to valid blocks. 2221system.l2c.tags.sampled_refs 200303 # Sample count of references to valid blocks. 2222system.l2c.tags.avg_refs 1.896192 # Average number of references to valid blocks. |
| 2224system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2223system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2225system.l2c.tags.occ_blocks::writebacks 11502.485032 # Average occupied blocks per requestor 2226system.l2c.tags.occ_blocks::cpu0.dtb.walker 90.401142 # Average occupied blocks per requestor 2227system.l2c.tags.occ_blocks::cpu0.itb.walker 0.038214 # Average occupied blocks per requestor 2228system.l2c.tags.occ_blocks::cpu0.inst 9505.348435 # Average occupied blocks per requestor 2229system.l2c.tags.occ_blocks::cpu0.data 2919.846446 # Average occupied blocks per requestor 2230system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 36413.661117 # Average occupied blocks per requestor 2231system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.683124 # Average occupied blocks per requestor 2232system.l2c.tags.occ_blocks::cpu1.inst 1274.245745 # Average occupied blocks per requestor 2233system.l2c.tags.occ_blocks::cpu1.data 582.633884 # Average occupied blocks per requestor 2234system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1880.036266 # Average occupied blocks per requestor 2235system.l2c.tags.occ_percent::writebacks 0.175514 # Average percentage of cache occupancy 2236system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001379 # Average percentage of cache occupancy 2237system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 2238system.l2c.tags.occ_percent::cpu0.inst 0.145040 # Average percentage of cache occupancy 2239system.l2c.tags.occ_percent::cpu0.data 0.044553 # Average percentage of cache occupancy 2240system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.555628 # Average percentage of cache occupancy 2241system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000117 # Average percentage of cache occupancy 2242system.l2c.tags.occ_percent::cpu1.inst 0.019443 # Average percentage of cache occupancy 2243system.l2c.tags.occ_percent::cpu1.data 0.008890 # Average percentage of cache occupancy 2244system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.028687 # Average percentage of cache occupancy 2245system.l2c.tags.occ_percent::total 0.979254 # Average percentage of cache occupancy 2246system.l2c.tags.occ_task_id_blocks::1022 31795 # Occupied blocks per task id 2247system.l2c.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id 2248system.l2c.tags.occ_task_id_blocks::1024 32593 # Occupied blocks per task id 2249system.l2c.tags.age_task_id_blocks_1022::2 145 # Occupied blocks per task id 2250system.l2c.tags.age_task_id_blocks_1022::3 5678 # Occupied blocks per task id 2251system.l2c.tags.age_task_id_blocks_1022::4 25972 # Occupied blocks per task id | 2224system.l2c.tags.occ_blocks::writebacks 12166.183008 # Average occupied blocks per requestor 2225system.l2c.tags.occ_blocks::cpu0.dtb.walker 73.341692 # Average occupied blocks per requestor 2226system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030170 # Average occupied blocks per requestor 2227system.l2c.tags.occ_blocks::cpu0.inst 8672.913636 # Average occupied blocks per requestor 2228system.l2c.tags.occ_blocks::cpu0.data 2762.328324 # Average occupied blocks per requestor 2229system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35676.457886 # Average occupied blocks per requestor 2230system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.004073 # Average occupied blocks per requestor 2231system.l2c.tags.occ_blocks::cpu1.inst 2139.434191 # Average occupied blocks per requestor 2232system.l2c.tags.occ_blocks::cpu1.data 561.920463 # Average occupied blocks per requestor 2233system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1923.222583 # Average occupied blocks per requestor 2234system.l2c.tags.occ_percent::writebacks 0.185641 # Average percentage of cache occupancy 2235system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001119 # Average percentage of cache occupancy 2236system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 2237system.l2c.tags.occ_percent::cpu0.inst 0.132338 # Average percentage of cache occupancy 2238system.l2c.tags.occ_percent::cpu0.data 0.042150 # Average percentage of cache occupancy 2239system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.544380 # Average percentage of cache occupancy 2240system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000214 # Average percentage of cache occupancy 2241system.l2c.tags.occ_percent::cpu1.inst 0.032645 # Average percentage of cache occupancy 2242system.l2c.tags.occ_percent::cpu1.data 0.008574 # Average percentage of cache occupancy 2243system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.029346 # Average percentage of cache occupancy 2244system.l2c.tags.occ_percent::total 0.976407 # Average percentage of cache occupancy 2245system.l2c.tags.occ_task_id_blocks::1022 31538 # Occupied blocks per task id 2246system.l2c.tags.occ_task_id_blocks::1023 56 # Occupied blocks per task id 2247system.l2c.tags.occ_task_id_blocks::1024 32925 # Occupied blocks per task id 2248system.l2c.tags.age_task_id_blocks_1022::2 124 # Occupied blocks per task id 2249system.l2c.tags.age_task_id_blocks_1022::3 5437 # Occupied blocks per task id 2250system.l2c.tags.age_task_id_blocks_1022::4 25977 # Occupied blocks per task id |
| 2252system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id | 2251system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id |
| 2253system.l2c.tags.age_task_id_blocks_1023::4 66 # Occupied blocks per task id 2254system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 2255system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id 2256system.l2c.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id 2257system.l2c.tags.age_task_id_blocks_1024::3 3295 # Occupied blocks per task id 2258system.l2c.tags.age_task_id_blocks_1024::4 28977 # Occupied blocks per task id 2259system.l2c.tags.occ_task_id_percent::1022 0.485153 # Percentage of cache occupancy per task id 2260system.l2c.tags.occ_task_id_percent::1023 0.001022 # Percentage of cache occupancy per task id 2261system.l2c.tags.occ_task_id_percent::1024 0.497330 # Percentage of cache occupancy per task id 2262system.l2c.tags.tag_accesses 5313847 # Number of tag accesses 2263system.l2c.tags.data_accesses 5313847 # Number of data accesses 2264system.l2c.ReadReq_hits::cpu0.dtb.walker 426 # number of ReadReq hits 2265system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits 2266system.l2c.ReadReq_hits::cpu0.inst 48963 # number of ReadReq hits 2267system.l2c.ReadReq_hits::cpu0.data 21691 # number of ReadReq hits 2268system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 75814 # number of ReadReq hits 2269system.l2c.ReadReq_hits::cpu1.dtb.walker 118 # number of ReadReq hits 2270system.l2c.ReadReq_hits::cpu1.itb.walker 32 # number of ReadReq hits 2271system.l2c.ReadReq_hits::cpu1.inst 16648 # number of ReadReq hits 2272system.l2c.ReadReq_hits::cpu1.data 7359 # number of ReadReq hits 2273system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7439 # number of ReadReq hits 2274system.l2c.ReadReq_hits::total 178553 # number of ReadReq hits 2275system.l2c.Writeback_hits::writebacks 234152 # number of Writeback hits 2276system.l2c.Writeback_hits::total 234152 # number of Writeback hits 2277system.l2c.UpgradeReq_hits::cpu0.data 2938 # number of UpgradeReq hits 2278system.l2c.UpgradeReq_hits::cpu1.data 658 # number of UpgradeReq hits 2279system.l2c.UpgradeReq_hits::total 3596 # number of UpgradeReq hits 2280system.l2c.SCUpgradeReq_hits::cpu0.data 142 # number of SCUpgradeReq hits 2281system.l2c.SCUpgradeReq_hits::cpu1.data 176 # number of SCUpgradeReq hits 2282system.l2c.SCUpgradeReq_hits::total 318 # number of SCUpgradeReq hits 2283system.l2c.ReadExReq_hits::cpu0.data 3842 # number of ReadExReq hits 2284system.l2c.ReadExReq_hits::cpu1.data 1332 # number of ReadExReq hits 2285system.l2c.ReadExReq_hits::total 5174 # number of ReadExReq hits 2286system.l2c.demand_hits::cpu0.dtb.walker 426 # number of demand (read+write) hits 2287system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits 2288system.l2c.demand_hits::cpu0.inst 48963 # number of demand (read+write) hits 2289system.l2c.demand_hits::cpu0.data 25533 # number of demand (read+write) hits 2290system.l2c.demand_hits::cpu0.l2cache.prefetcher 75814 # number of demand (read+write) hits 2291system.l2c.demand_hits::cpu1.dtb.walker 118 # number of demand (read+write) hits 2292system.l2c.demand_hits::cpu1.itb.walker 32 # number of demand (read+write) hits 2293system.l2c.demand_hits::cpu1.inst 16648 # number of demand (read+write) hits 2294system.l2c.demand_hits::cpu1.data 8691 # number of demand (read+write) hits 2295system.l2c.demand_hits::cpu1.l2cache.prefetcher 7439 # number of demand (read+write) hits 2296system.l2c.demand_hits::total 183727 # number of demand (read+write) hits 2297system.l2c.overall_hits::cpu0.dtb.walker 426 # number of overall hits 2298system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits 2299system.l2c.overall_hits::cpu0.inst 48963 # number of overall hits 2300system.l2c.overall_hits::cpu0.data 25533 # number of overall hits 2301system.l2c.overall_hits::cpu0.l2cache.prefetcher 75814 # number of overall hits 2302system.l2c.overall_hits::cpu1.dtb.walker 118 # number of overall hits 2303system.l2c.overall_hits::cpu1.itb.walker 32 # number of overall hits 2304system.l2c.overall_hits::cpu1.inst 16648 # number of overall hits 2305system.l2c.overall_hits::cpu1.data 8691 # number of overall hits 2306system.l2c.overall_hits::cpu1.l2cache.prefetcher 7439 # number of overall hits 2307system.l2c.overall_hits::total 183727 # number of overall hits 2308system.l2c.ReadReq_misses::cpu0.dtb.walker 162 # number of ReadReq misses | 2252system.l2c.tags.age_task_id_blocks_1023::4 55 # Occupied blocks per task id 2253system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 2254system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id 2255system.l2c.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id 2256system.l2c.tags.age_task_id_blocks_1024::3 3182 # Occupied blocks per task id 2257system.l2c.tags.age_task_id_blocks_1024::4 29429 # Occupied blocks per task id 2258system.l2c.tags.occ_task_id_percent::1022 0.481232 # Percentage of cache occupancy per task id 2259system.l2c.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id 2260system.l2c.tags.occ_task_id_percent::1024 0.502396 # Percentage of cache occupancy per task id 2261system.l2c.tags.tag_accesses 5287676 # Number of tag accesses 2262system.l2c.tags.data_accesses 5287676 # Number of data accesses 2263system.l2c.ReadReq_hits::cpu0.dtb.walker 420 # number of ReadReq hits 2264system.l2c.ReadReq_hits::cpu0.itb.walker 71 # number of ReadReq hits 2265system.l2c.ReadReq_hits::cpu0.inst 47985 # number of ReadReq hits 2266system.l2c.ReadReq_hits::cpu0.data 21581 # number of ReadReq hits 2267system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 76019 # number of ReadReq hits 2268system.l2c.ReadReq_hits::cpu1.dtb.walker 126 # number of ReadReq hits 2269system.l2c.ReadReq_hits::cpu1.itb.walker 31 # number of ReadReq hits 2270system.l2c.ReadReq_hits::cpu1.inst 17578 # number of ReadReq hits 2271system.l2c.ReadReq_hits::cpu1.data 7426 # number of ReadReq hits 2272system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7556 # number of ReadReq hits 2273system.l2c.ReadReq_hits::total 178793 # number of ReadReq hits 2274system.l2c.Writeback_hits::writebacks 232242 # number of Writeback hits 2275system.l2c.Writeback_hits::total 232242 # number of Writeback hits 2276system.l2c.UpgradeReq_hits::cpu0.data 3124 # number of UpgradeReq hits 2277system.l2c.UpgradeReq_hits::cpu1.data 764 # number of UpgradeReq hits 2278system.l2c.UpgradeReq_hits::total 3888 # number of UpgradeReq hits 2279system.l2c.SCUpgradeReq_hits::cpu0.data 164 # number of SCUpgradeReq hits 2280system.l2c.SCUpgradeReq_hits::cpu1.data 156 # number of SCUpgradeReq hits 2281system.l2c.SCUpgradeReq_hits::total 320 # number of SCUpgradeReq hits 2282system.l2c.ReadExReq_hits::cpu0.data 4039 # number of ReadExReq hits 2283system.l2c.ReadExReq_hits::cpu1.data 1693 # number of ReadExReq hits 2284system.l2c.ReadExReq_hits::total 5732 # number of ReadExReq hits 2285system.l2c.demand_hits::cpu0.dtb.walker 420 # number of demand (read+write) hits 2286system.l2c.demand_hits::cpu0.itb.walker 71 # number of demand (read+write) hits 2287system.l2c.demand_hits::cpu0.inst 47985 # number of demand (read+write) hits 2288system.l2c.demand_hits::cpu0.data 25620 # number of demand (read+write) hits 2289system.l2c.demand_hits::cpu0.l2cache.prefetcher 76019 # number of demand (read+write) hits 2290system.l2c.demand_hits::cpu1.dtb.walker 126 # number of demand (read+write) hits 2291system.l2c.demand_hits::cpu1.itb.walker 31 # number of demand (read+write) hits 2292system.l2c.demand_hits::cpu1.inst 17578 # number of demand (read+write) hits 2293system.l2c.demand_hits::cpu1.data 9119 # number of demand (read+write) hits 2294system.l2c.demand_hits::cpu1.l2cache.prefetcher 7556 # number of demand (read+write) hits 2295system.l2c.demand_hits::total 184525 # number of demand (read+write) hits 2296system.l2c.overall_hits::cpu0.dtb.walker 420 # number of overall hits 2297system.l2c.overall_hits::cpu0.itb.walker 71 # number of overall hits 2298system.l2c.overall_hits::cpu0.inst 47985 # number of overall hits 2299system.l2c.overall_hits::cpu0.data 25620 # number of overall hits 2300system.l2c.overall_hits::cpu0.l2cache.prefetcher 76019 # number of overall hits 2301system.l2c.overall_hits::cpu1.dtb.walker 126 # number of overall hits 2302system.l2c.overall_hits::cpu1.itb.walker 31 # number of overall hits 2303system.l2c.overall_hits::cpu1.inst 17578 # number of overall hits 2304system.l2c.overall_hits::cpu1.data 9119 # number of overall hits 2305system.l2c.overall_hits::cpu1.l2cache.prefetcher 7556 # number of overall hits 2306system.l2c.overall_hits::total 184525 # number of overall hits 2307system.l2c.ReadReq_misses::cpu0.dtb.walker 151 # number of ReadReq misses |
| 2309system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses | 2308system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses |
| 2310system.l2c.ReadReq_misses::cpu0.inst 23855 # number of ReadReq misses 2311system.l2c.ReadReq_misses::cpu0.data 8693 # number of ReadReq misses 2312system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 136690 # number of ReadReq misses 2313system.l2c.ReadReq_misses::cpu1.dtb.walker 12 # number of ReadReq misses 2314system.l2c.ReadReq_misses::cpu1.inst 2292 # number of ReadReq misses 2315system.l2c.ReadReq_misses::cpu1.data 1041 # number of ReadReq misses 2316system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 6249 # number of ReadReq misses 2317system.l2c.ReadReq_misses::total 178995 # number of ReadReq misses 2318system.l2c.UpgradeReq_misses::cpu0.data 8970 # number of UpgradeReq misses 2319system.l2c.UpgradeReq_misses::cpu1.data 2734 # number of UpgradeReq misses 2320system.l2c.UpgradeReq_misses::total 11704 # number of UpgradeReq misses 2321system.l2c.SCUpgradeReq_misses::cpu0.data 618 # number of SCUpgradeReq misses 2322system.l2c.SCUpgradeReq_misses::cpu1.data 1189 # number of SCUpgradeReq misses 2323system.l2c.SCUpgradeReq_misses::total 1807 # number of SCUpgradeReq misses 2324system.l2c.ReadExReq_misses::cpu0.data 11575 # number of ReadExReq misses 2325system.l2c.ReadExReq_misses::cpu1.data 8676 # number of ReadExReq misses 2326system.l2c.ReadExReq_misses::total 20251 # number of ReadExReq misses 2327system.l2c.demand_misses::cpu0.dtb.walker 162 # number of demand (read+write) misses | 2309system.l2c.ReadReq_misses::cpu0.inst 22827 # number of ReadReq misses 2310system.l2c.ReadReq_misses::cpu0.data 8447 # number of ReadReq misses 2311system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 134637 # number of ReadReq misses 2312system.l2c.ReadReq_misses::cpu1.dtb.walker 21 # number of ReadReq misses 2313system.l2c.ReadReq_misses::cpu1.inst 3299 # number of ReadReq misses 2314system.l2c.ReadReq_misses::cpu1.data 1023 # number of ReadReq misses 2315system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 6207 # number of ReadReq misses 2316system.l2c.ReadReq_misses::total 176613 # number of ReadReq misses 2317system.l2c.UpgradeReq_misses::cpu0.data 9362 # number of UpgradeReq misses 2318system.l2c.UpgradeReq_misses::cpu1.data 2973 # number of UpgradeReq misses 2319system.l2c.UpgradeReq_misses::total 12335 # number of UpgradeReq misses 2320system.l2c.SCUpgradeReq_misses::cpu0.data 691 # number of SCUpgradeReq misses 2321system.l2c.SCUpgradeReq_misses::cpu1.data 1280 # number of SCUpgradeReq misses 2322system.l2c.SCUpgradeReq_misses::total 1971 # number of SCUpgradeReq misses 2323system.l2c.ReadExReq_misses::cpu0.data 11331 # number of ReadExReq misses 2324system.l2c.ReadExReq_misses::cpu1.data 8391 # number of ReadExReq misses 2325system.l2c.ReadExReq_misses::total 19722 # number of ReadExReq misses 2326system.l2c.demand_misses::cpu0.dtb.walker 151 # number of demand (read+write) misses |
| 2328system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses | 2327system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses |
| 2329system.l2c.demand_misses::cpu0.inst 23855 # number of demand (read+write) misses 2330system.l2c.demand_misses::cpu0.data 20268 # number of demand (read+write) misses 2331system.l2c.demand_misses::cpu0.l2cache.prefetcher 136690 # number of demand (read+write) misses 2332system.l2c.demand_misses::cpu1.dtb.walker 12 # number of demand (read+write) misses 2333system.l2c.demand_misses::cpu1.inst 2292 # number of demand (read+write) misses 2334system.l2c.demand_misses::cpu1.data 9717 # number of demand (read+write) misses 2335system.l2c.demand_misses::cpu1.l2cache.prefetcher 6249 # number of demand (read+write) misses 2336system.l2c.demand_misses::total 199246 # number of demand (read+write) misses 2337system.l2c.overall_misses::cpu0.dtb.walker 162 # number of overall misses | 2328system.l2c.demand_misses::cpu0.inst 22827 # number of demand (read+write) misses 2329system.l2c.demand_misses::cpu0.data 19778 # number of demand (read+write) misses 2330system.l2c.demand_misses::cpu0.l2cache.prefetcher 134637 # number of demand (read+write) misses 2331system.l2c.demand_misses::cpu1.dtb.walker 21 # number of demand (read+write) misses 2332system.l2c.demand_misses::cpu1.inst 3299 # number of demand (read+write) misses 2333system.l2c.demand_misses::cpu1.data 9414 # number of demand (read+write) misses 2334system.l2c.demand_misses::cpu1.l2cache.prefetcher 6207 # number of demand (read+write) misses 2335system.l2c.demand_misses::total 196335 # number of demand (read+write) misses 2336system.l2c.overall_misses::cpu0.dtb.walker 151 # number of overall misses |
| 2338system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses | 2337system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses |
| 2339system.l2c.overall_misses::cpu0.inst 23855 # number of overall misses 2340system.l2c.overall_misses::cpu0.data 20268 # number of overall misses 2341system.l2c.overall_misses::cpu0.l2cache.prefetcher 136690 # number of overall misses 2342system.l2c.overall_misses::cpu1.dtb.walker 12 # number of overall misses 2343system.l2c.overall_misses::cpu1.inst 2292 # number of overall misses 2344system.l2c.overall_misses::cpu1.data 9717 # number of overall misses 2345system.l2c.overall_misses::cpu1.l2cache.prefetcher 6249 # number of overall misses 2346system.l2c.overall_misses::total 199246 # number of overall misses 2347system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 12996250 # number of ReadReq miss cycles 2348system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles 2349system.l2c.ReadReq_miss_latency::cpu0.inst 1747991991 # number of ReadReq miss cycles 2350system.l2c.ReadReq_miss_latency::cpu0.data 697325498 # number of ReadReq miss cycles 2351system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 14069068891 # number of ReadReq miss cycles 2352system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 960250 # number of ReadReq miss cycles 2353system.l2c.ReadReq_miss_latency::cpu1.inst 172995499 # number of ReadReq miss cycles 2354system.l2c.ReadReq_miss_latency::cpu1.data 85266750 # number of ReadReq miss cycles 2355system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 826051791 # number of ReadReq miss cycles 2356system.l2c.ReadReq_miss_latency::total 17612731920 # number of ReadReq miss cycles 2357system.l2c.UpgradeReq_miss_latency::cpu0.data 7054791 # number of UpgradeReq miss cycles 2358system.l2c.UpgradeReq_miss_latency::cpu1.data 1587933 # number of UpgradeReq miss cycles 2359system.l2c.UpgradeReq_miss_latency::total 8642724 # number of UpgradeReq miss cycles 2360system.l2c.SCUpgradeReq_miss_latency::cpu0.data 937466 # number of SCUpgradeReq miss cycles 2361system.l2c.SCUpgradeReq_miss_latency::cpu1.data 512978 # number of SCUpgradeReq miss cycles 2362system.l2c.SCUpgradeReq_miss_latency::total 1450444 # number of SCUpgradeReq miss cycles 2363system.l2c.ReadExReq_miss_latency::cpu0.data 952737665 # number of ReadExReq miss cycles 2364system.l2c.ReadExReq_miss_latency::cpu1.data 639334486 # number of ReadExReq miss cycles 2365system.l2c.ReadExReq_miss_latency::total 1592072151 # number of ReadExReq miss cycles 2366system.l2c.demand_miss_latency::cpu0.dtb.walker 12996250 # number of demand (read+write) miss cycles 2367system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles 2368system.l2c.demand_miss_latency::cpu0.inst 1747991991 # number of demand (read+write) miss cycles 2369system.l2c.demand_miss_latency::cpu0.data 1650063163 # number of demand (read+write) miss cycles 2370system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14069068891 # number of demand (read+write) miss cycles 2371system.l2c.demand_miss_latency::cpu1.dtb.walker 960250 # number of demand (read+write) miss cycles 2372system.l2c.demand_miss_latency::cpu1.inst 172995499 # number of demand (read+write) miss cycles 2373system.l2c.demand_miss_latency::cpu1.data 724601236 # number of demand (read+write) miss cycles 2374system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 826051791 # number of demand (read+write) miss cycles 2375system.l2c.demand_miss_latency::total 19204804071 # number of demand (read+write) miss cycles 2376system.l2c.overall_miss_latency::cpu0.dtb.walker 12996250 # number of overall miss cycles 2377system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles 2378system.l2c.overall_miss_latency::cpu0.inst 1747991991 # number of overall miss cycles 2379system.l2c.overall_miss_latency::cpu0.data 1650063163 # number of overall miss cycles 2380system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14069068891 # number of overall miss cycles 2381system.l2c.overall_miss_latency::cpu1.dtb.walker 960250 # number of overall miss cycles 2382system.l2c.overall_miss_latency::cpu1.inst 172995499 # number of overall miss cycles 2383system.l2c.overall_miss_latency::cpu1.data 724601236 # number of overall miss cycles 2384system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 826051791 # number of overall miss cycles 2385system.l2c.overall_miss_latency::total 19204804071 # number of overall miss cycles 2386system.l2c.ReadReq_accesses::cpu0.dtb.walker 588 # number of ReadReq accesses(hits+misses) 2387system.l2c.ReadReq_accesses::cpu0.itb.walker 64 # number of ReadReq accesses(hits+misses) 2388system.l2c.ReadReq_accesses::cpu0.inst 72818 # number of ReadReq accesses(hits+misses) 2389system.l2c.ReadReq_accesses::cpu0.data 30384 # number of ReadReq accesses(hits+misses) 2390system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 212504 # number of ReadReq accesses(hits+misses) 2391system.l2c.ReadReq_accesses::cpu1.dtb.walker 130 # number of ReadReq accesses(hits+misses) 2392system.l2c.ReadReq_accesses::cpu1.itb.walker 32 # number of ReadReq accesses(hits+misses) 2393system.l2c.ReadReq_accesses::cpu1.inst 18940 # number of ReadReq accesses(hits+misses) 2394system.l2c.ReadReq_accesses::cpu1.data 8400 # number of ReadReq accesses(hits+misses) 2395system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 13688 # number of ReadReq accesses(hits+misses) 2396system.l2c.ReadReq_accesses::total 357548 # number of ReadReq accesses(hits+misses) 2397system.l2c.Writeback_accesses::writebacks 234152 # number of Writeback accesses(hits+misses) 2398system.l2c.Writeback_accesses::total 234152 # number of Writeback accesses(hits+misses) 2399system.l2c.UpgradeReq_accesses::cpu0.data 11908 # number of UpgradeReq accesses(hits+misses) 2400system.l2c.UpgradeReq_accesses::cpu1.data 3392 # number of UpgradeReq accesses(hits+misses) 2401system.l2c.UpgradeReq_accesses::total 15300 # number of UpgradeReq accesses(hits+misses) 2402system.l2c.SCUpgradeReq_accesses::cpu0.data 760 # number of SCUpgradeReq accesses(hits+misses) 2403system.l2c.SCUpgradeReq_accesses::cpu1.data 1365 # number of SCUpgradeReq accesses(hits+misses) 2404system.l2c.SCUpgradeReq_accesses::total 2125 # number of SCUpgradeReq accesses(hits+misses) 2405system.l2c.ReadExReq_accesses::cpu0.data 15417 # number of ReadExReq accesses(hits+misses) 2406system.l2c.ReadExReq_accesses::cpu1.data 10008 # number of ReadExReq accesses(hits+misses) 2407system.l2c.ReadExReq_accesses::total 25425 # number of ReadExReq accesses(hits+misses) 2408system.l2c.demand_accesses::cpu0.dtb.walker 588 # number of demand (read+write) accesses 2409system.l2c.demand_accesses::cpu0.itb.walker 64 # number of demand (read+write) accesses 2410system.l2c.demand_accesses::cpu0.inst 72818 # number of demand (read+write) accesses 2411system.l2c.demand_accesses::cpu0.data 45801 # number of demand (read+write) accesses 2412system.l2c.demand_accesses::cpu0.l2cache.prefetcher 212504 # number of demand (read+write) accesses 2413system.l2c.demand_accesses::cpu1.dtb.walker 130 # number of demand (read+write) accesses 2414system.l2c.demand_accesses::cpu1.itb.walker 32 # number of demand (read+write) accesses 2415system.l2c.demand_accesses::cpu1.inst 18940 # number of demand (read+write) accesses 2416system.l2c.demand_accesses::cpu1.data 18408 # number of demand (read+write) accesses 2417system.l2c.demand_accesses::cpu1.l2cache.prefetcher 13688 # number of demand (read+write) accesses 2418system.l2c.demand_accesses::total 382973 # number of demand (read+write) accesses 2419system.l2c.overall_accesses::cpu0.dtb.walker 588 # number of overall (read+write) accesses 2420system.l2c.overall_accesses::cpu0.itb.walker 64 # number of overall (read+write) accesses 2421system.l2c.overall_accesses::cpu0.inst 72818 # number of overall (read+write) accesses 2422system.l2c.overall_accesses::cpu0.data 45801 # number of overall (read+write) accesses 2423system.l2c.overall_accesses::cpu0.l2cache.prefetcher 212504 # number of overall (read+write) accesses 2424system.l2c.overall_accesses::cpu1.dtb.walker 130 # number of overall (read+write) accesses 2425system.l2c.overall_accesses::cpu1.itb.walker 32 # number of overall (read+write) accesses 2426system.l2c.overall_accesses::cpu1.inst 18940 # number of overall (read+write) accesses 2427system.l2c.overall_accesses::cpu1.data 18408 # number of overall (read+write) accesses 2428system.l2c.overall_accesses::cpu1.l2cache.prefetcher 13688 # number of overall (read+write) accesses 2429system.l2c.overall_accesses::total 382973 # number of overall (read+write) accesses 2430system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.275510 # miss rate for ReadReq accesses 2431system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.015625 # miss rate for ReadReq accesses 2432system.l2c.ReadReq_miss_rate::cpu0.inst 0.327598 # miss rate for ReadReq accesses 2433system.l2c.ReadReq_miss_rate::cpu0.data 0.286105 # miss rate for ReadReq accesses 2434system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.643235 # miss rate for ReadReq accesses 2435system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.092308 # miss rate for ReadReq accesses 2436system.l2c.ReadReq_miss_rate::cpu1.inst 0.121014 # miss rate for ReadReq accesses 2437system.l2c.ReadReq_miss_rate::cpu1.data 0.123929 # miss rate for ReadReq accesses 2438system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.456531 # miss rate for ReadReq accesses 2439system.l2c.ReadReq_miss_rate::total 0.500618 # miss rate for ReadReq accesses 2440system.l2c.UpgradeReq_miss_rate::cpu0.data 0.753275 # miss rate for UpgradeReq accesses 2441system.l2c.UpgradeReq_miss_rate::cpu1.data 0.806014 # miss rate for UpgradeReq accesses 2442system.l2c.UpgradeReq_miss_rate::total 0.764967 # miss rate for UpgradeReq accesses 2443system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.813158 # miss rate for SCUpgradeReq accesses 2444system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.871062 # miss rate for SCUpgradeReq accesses 2445system.l2c.SCUpgradeReq_miss_rate::total 0.850353 # miss rate for SCUpgradeReq accesses 2446system.l2c.ReadExReq_miss_rate::cpu0.data 0.750795 # miss rate for ReadExReq accesses 2447system.l2c.ReadExReq_miss_rate::cpu1.data 0.866906 # miss rate for ReadExReq accesses 2448system.l2c.ReadExReq_miss_rate::total 0.796500 # miss rate for ReadExReq accesses 2449system.l2c.demand_miss_rate::cpu0.dtb.walker 0.275510 # miss rate for demand accesses 2450system.l2c.demand_miss_rate::cpu0.itb.walker 0.015625 # miss rate for demand accesses 2451system.l2c.demand_miss_rate::cpu0.inst 0.327598 # miss rate for demand accesses 2452system.l2c.demand_miss_rate::cpu0.data 0.442523 # miss rate for demand accesses 2453system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.643235 # miss rate for demand accesses 2454system.l2c.demand_miss_rate::cpu1.dtb.walker 0.092308 # miss rate for demand accesses 2455system.l2c.demand_miss_rate::cpu1.inst 0.121014 # miss rate for demand accesses 2456system.l2c.demand_miss_rate::cpu1.data 0.527868 # miss rate for demand accesses 2457system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.456531 # miss rate for demand accesses 2458system.l2c.demand_miss_rate::total 0.520261 # miss rate for demand accesses 2459system.l2c.overall_miss_rate::cpu0.dtb.walker 0.275510 # miss rate for overall accesses 2460system.l2c.overall_miss_rate::cpu0.itb.walker 0.015625 # miss rate for overall accesses 2461system.l2c.overall_miss_rate::cpu0.inst 0.327598 # miss rate for overall accesses 2462system.l2c.overall_miss_rate::cpu0.data 0.442523 # miss rate for overall accesses 2463system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.643235 # miss rate for overall accesses 2464system.l2c.overall_miss_rate::cpu1.dtb.walker 0.092308 # miss rate for overall accesses 2465system.l2c.overall_miss_rate::cpu1.inst 0.121014 # miss rate for overall accesses 2466system.l2c.overall_miss_rate::cpu1.data 0.527868 # miss rate for overall accesses 2467system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.456531 # miss rate for overall accesses 2468system.l2c.overall_miss_rate::total 0.520261 # miss rate for overall accesses 2469system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80223.765432 # average ReadReq miss latency 2470system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency 2471system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73275.707022 # average ReadReq miss latency 2472system.l2c.ReadReq_avg_miss_latency::cpu0.data 80216.898424 # average ReadReq miss latency 2473system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 102926.833645 # average ReadReq miss latency 2474system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 80020.833333 # average ReadReq miss latency 2475system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75477.966405 # average ReadReq miss latency 2476system.l2c.ReadReq_avg_miss_latency::cpu1.data 81908.501441 # average ReadReq miss latency 2477system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 132189.436870 # average ReadReq miss latency 2478system.l2c.ReadReq_avg_miss_latency::total 98397.898936 # average ReadReq miss latency 2479system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 786.487291 # average UpgradeReq miss latency 2480system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 580.809437 # average UpgradeReq miss latency 2481system.l2c.UpgradeReq_avg_miss_latency::total 738.441900 # average UpgradeReq miss latency 2482system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1516.935275 # average SCUpgradeReq miss latency 2483system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 431.436501 # average SCUpgradeReq miss latency 2484system.l2c.SCUpgradeReq_avg_miss_latency::total 802.680686 # average SCUpgradeReq miss latency 2485system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82309.949460 # average ReadExReq miss latency 2486system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73690.005302 # average ReadExReq miss latency 2487system.l2c.ReadExReq_avg_miss_latency::total 78616.964644 # average ReadExReq miss latency 2488system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80223.765432 # average overall miss latency 2489system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency 2490system.l2c.demand_avg_miss_latency::cpu0.inst 73275.707022 # average overall miss latency 2491system.l2c.demand_avg_miss_latency::cpu0.data 81412.234212 # average overall miss latency 2492system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 102926.833645 # average overall miss latency 2493system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80020.833333 # average overall miss latency 2494system.l2c.demand_avg_miss_latency::cpu1.inst 75477.966405 # average overall miss latency 2495system.l2c.demand_avg_miss_latency::cpu1.data 74570.467840 # average overall miss latency 2496system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132189.436870 # average overall miss latency 2497system.l2c.demand_avg_miss_latency::total 96387.400856 # average overall miss latency 2498system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80223.765432 # average overall miss latency 2499system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency 2500system.l2c.overall_avg_miss_latency::cpu0.inst 73275.707022 # average overall miss latency 2501system.l2c.overall_avg_miss_latency::cpu0.data 81412.234212 # average overall miss latency 2502system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 102926.833645 # average overall miss latency 2503system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80020.833333 # average overall miss latency 2504system.l2c.overall_avg_miss_latency::cpu1.inst 75477.966405 # average overall miss latency 2505system.l2c.overall_avg_miss_latency::cpu1.data 74570.467840 # average overall miss latency 2506system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132189.436870 # average overall miss latency 2507system.l2c.overall_avg_miss_latency::total 96387.400856 # average overall miss latency | 2338system.l2c.overall_misses::cpu0.inst 22827 # number of overall misses 2339system.l2c.overall_misses::cpu0.data 19778 # number of overall misses 2340system.l2c.overall_misses::cpu0.l2cache.prefetcher 134637 # number of overall misses 2341system.l2c.overall_misses::cpu1.dtb.walker 21 # number of overall misses 2342system.l2c.overall_misses::cpu1.inst 3299 # number of overall misses 2343system.l2c.overall_misses::cpu1.data 9414 # number of overall misses 2344system.l2c.overall_misses::cpu1.l2cache.prefetcher 6207 # number of overall misses 2345system.l2c.overall_misses::total 196335 # number of overall misses 2346system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 13524750 # number of ReadReq miss cycles 2347system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82500 # number of ReadReq miss cycles 2348system.l2c.ReadReq_miss_latency::cpu0.inst 1838995046 # number of ReadReq miss cycles 2349system.l2c.ReadReq_miss_latency::cpu0.data 735224800 # number of ReadReq miss cycles 2350system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 13878942092 # number of ReadReq miss cycles 2351system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 2299500 # number of ReadReq miss cycles 2352system.l2c.ReadReq_miss_latency::cpu1.inst 276071257 # number of ReadReq miss cycles 2353system.l2c.ReadReq_miss_latency::cpu1.data 88476763 # number of ReadReq miss cycles 2354system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 819085145 # number of ReadReq miss cycles 2355system.l2c.ReadReq_miss_latency::total 17652701853 # number of ReadReq miss cycles 2356system.l2c.UpgradeReq_miss_latency::cpu0.data 8759261 # number of UpgradeReq miss cycles 2357system.l2c.UpgradeReq_miss_latency::cpu1.data 2783911 # number of UpgradeReq miss cycles 2358system.l2c.UpgradeReq_miss_latency::total 11543172 # number of UpgradeReq miss cycles 2359system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1313463 # number of SCUpgradeReq miss cycles 2360system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1279959 # number of SCUpgradeReq miss cycles 2361system.l2c.SCUpgradeReq_miss_latency::total 2593422 # number of SCUpgradeReq miss cycles 2362system.l2c.ReadExReq_miss_latency::cpu0.data 1048895931 # number of ReadExReq miss cycles 2363system.l2c.ReadExReq_miss_latency::cpu1.data 690519981 # number of ReadExReq miss cycles 2364system.l2c.ReadExReq_miss_latency::total 1739415912 # number of ReadExReq miss cycles 2365system.l2c.demand_miss_latency::cpu0.dtb.walker 13524750 # number of demand (read+write) miss cycles 2366system.l2c.demand_miss_latency::cpu0.itb.walker 82500 # number of demand (read+write) miss cycles 2367system.l2c.demand_miss_latency::cpu0.inst 1838995046 # number of demand (read+write) miss cycles 2368system.l2c.demand_miss_latency::cpu0.data 1784120731 # number of demand (read+write) miss cycles 2369system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13878942092 # number of demand (read+write) miss cycles 2370system.l2c.demand_miss_latency::cpu1.dtb.walker 2299500 # number of demand (read+write) miss cycles 2371system.l2c.demand_miss_latency::cpu1.inst 276071257 # number of demand (read+write) miss cycles 2372system.l2c.demand_miss_latency::cpu1.data 778996744 # number of demand (read+write) miss cycles 2373system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 819085145 # number of demand (read+write) miss cycles 2374system.l2c.demand_miss_latency::total 19392117765 # number of demand (read+write) miss cycles 2375system.l2c.overall_miss_latency::cpu0.dtb.walker 13524750 # number of overall miss cycles 2376system.l2c.overall_miss_latency::cpu0.itb.walker 82500 # number of overall miss cycles 2377system.l2c.overall_miss_latency::cpu0.inst 1838995046 # number of overall miss cycles 2378system.l2c.overall_miss_latency::cpu0.data 1784120731 # number of overall miss cycles 2379system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13878942092 # number of overall miss cycles 2380system.l2c.overall_miss_latency::cpu1.dtb.walker 2299500 # number of overall miss cycles 2381system.l2c.overall_miss_latency::cpu1.inst 276071257 # number of overall miss cycles 2382system.l2c.overall_miss_latency::cpu1.data 778996744 # number of overall miss cycles 2383system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 819085145 # number of overall miss cycles 2384system.l2c.overall_miss_latency::total 19392117765 # number of overall miss cycles 2385system.l2c.ReadReq_accesses::cpu0.dtb.walker 571 # number of ReadReq accesses(hits+misses) 2386system.l2c.ReadReq_accesses::cpu0.itb.walker 72 # number of ReadReq accesses(hits+misses) 2387system.l2c.ReadReq_accesses::cpu0.inst 70812 # number of ReadReq accesses(hits+misses) 2388system.l2c.ReadReq_accesses::cpu0.data 30028 # number of ReadReq accesses(hits+misses) 2389system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 210656 # number of ReadReq accesses(hits+misses) 2390system.l2c.ReadReq_accesses::cpu1.dtb.walker 147 # number of ReadReq accesses(hits+misses) 2391system.l2c.ReadReq_accesses::cpu1.itb.walker 31 # number of ReadReq accesses(hits+misses) 2392system.l2c.ReadReq_accesses::cpu1.inst 20877 # number of ReadReq accesses(hits+misses) 2393system.l2c.ReadReq_accesses::cpu1.data 8449 # number of ReadReq accesses(hits+misses) 2394system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 13763 # number of ReadReq accesses(hits+misses) 2395system.l2c.ReadReq_accesses::total 355406 # number of ReadReq accesses(hits+misses) 2396system.l2c.Writeback_accesses::writebacks 232242 # number of Writeback accesses(hits+misses) 2397system.l2c.Writeback_accesses::total 232242 # number of Writeback accesses(hits+misses) 2398system.l2c.UpgradeReq_accesses::cpu0.data 12486 # number of UpgradeReq accesses(hits+misses) 2399system.l2c.UpgradeReq_accesses::cpu1.data 3737 # number of UpgradeReq accesses(hits+misses) 2400system.l2c.UpgradeReq_accesses::total 16223 # number of UpgradeReq accesses(hits+misses) 2401system.l2c.SCUpgradeReq_accesses::cpu0.data 855 # number of SCUpgradeReq accesses(hits+misses) 2402system.l2c.SCUpgradeReq_accesses::cpu1.data 1436 # number of SCUpgradeReq accesses(hits+misses) 2403system.l2c.SCUpgradeReq_accesses::total 2291 # number of SCUpgradeReq accesses(hits+misses) 2404system.l2c.ReadExReq_accesses::cpu0.data 15370 # number of ReadExReq accesses(hits+misses) 2405system.l2c.ReadExReq_accesses::cpu1.data 10084 # number of ReadExReq accesses(hits+misses) 2406system.l2c.ReadExReq_accesses::total 25454 # number of ReadExReq accesses(hits+misses) 2407system.l2c.demand_accesses::cpu0.dtb.walker 571 # number of demand (read+write) accesses 2408system.l2c.demand_accesses::cpu0.itb.walker 72 # number of demand (read+write) accesses 2409system.l2c.demand_accesses::cpu0.inst 70812 # number of demand (read+write) accesses 2410system.l2c.demand_accesses::cpu0.data 45398 # number of demand (read+write) accesses 2411system.l2c.demand_accesses::cpu0.l2cache.prefetcher 210656 # number of demand (read+write) accesses 2412system.l2c.demand_accesses::cpu1.dtb.walker 147 # number of demand (read+write) accesses 2413system.l2c.demand_accesses::cpu1.itb.walker 31 # number of demand (read+write) accesses 2414system.l2c.demand_accesses::cpu1.inst 20877 # number of demand (read+write) accesses 2415system.l2c.demand_accesses::cpu1.data 18533 # number of demand (read+write) accesses 2416system.l2c.demand_accesses::cpu1.l2cache.prefetcher 13763 # number of demand (read+write) accesses 2417system.l2c.demand_accesses::total 380860 # number of demand (read+write) accesses 2418system.l2c.overall_accesses::cpu0.dtb.walker 571 # number of overall (read+write) accesses 2419system.l2c.overall_accesses::cpu0.itb.walker 72 # number of overall (read+write) accesses 2420system.l2c.overall_accesses::cpu0.inst 70812 # number of overall (read+write) accesses 2421system.l2c.overall_accesses::cpu0.data 45398 # number of overall (read+write) accesses 2422system.l2c.overall_accesses::cpu0.l2cache.prefetcher 210656 # number of overall (read+write) accesses 2423system.l2c.overall_accesses::cpu1.dtb.walker 147 # number of overall (read+write) accesses 2424system.l2c.overall_accesses::cpu1.itb.walker 31 # number of overall (read+write) accesses 2425system.l2c.overall_accesses::cpu1.inst 20877 # number of overall (read+write) accesses 2426system.l2c.overall_accesses::cpu1.data 18533 # number of overall (read+write) accesses 2427system.l2c.overall_accesses::cpu1.l2cache.prefetcher 13763 # number of overall (read+write) accesses 2428system.l2c.overall_accesses::total 380860 # number of overall (read+write) accesses 2429system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.264448 # miss rate for ReadReq accesses 2430system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.013889 # miss rate for ReadReq accesses 2431system.l2c.ReadReq_miss_rate::cpu0.inst 0.322361 # miss rate for ReadReq accesses 2432system.l2c.ReadReq_miss_rate::cpu0.data 0.281304 # miss rate for ReadReq accesses 2433system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.639132 # miss rate for ReadReq accesses 2434system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.142857 # miss rate for ReadReq accesses 2435system.l2c.ReadReq_miss_rate::cpu1.inst 0.158021 # miss rate for ReadReq accesses 2436system.l2c.ReadReq_miss_rate::cpu1.data 0.121079 # miss rate for ReadReq accesses 2437system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.450992 # miss rate for ReadReq accesses 2438system.l2c.ReadReq_miss_rate::total 0.496933 # miss rate for ReadReq accesses 2439system.l2c.UpgradeReq_miss_rate::cpu0.data 0.749800 # miss rate for UpgradeReq accesses 2440system.l2c.UpgradeReq_miss_rate::cpu1.data 0.795558 # miss rate for UpgradeReq accesses 2441system.l2c.UpgradeReq_miss_rate::total 0.760340 # miss rate for UpgradeReq accesses 2442system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.808187 # miss rate for SCUpgradeReq accesses 2443system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.891365 # miss rate for SCUpgradeReq accesses 2444system.l2c.SCUpgradeReq_miss_rate::total 0.860323 # miss rate for SCUpgradeReq accesses 2445system.l2c.ReadExReq_miss_rate::cpu0.data 0.737215 # miss rate for ReadExReq accesses 2446system.l2c.ReadExReq_miss_rate::cpu1.data 0.832110 # miss rate for ReadExReq accesses 2447system.l2c.ReadExReq_miss_rate::total 0.774809 # miss rate for ReadExReq accesses 2448system.l2c.demand_miss_rate::cpu0.dtb.walker 0.264448 # miss rate for demand accesses 2449system.l2c.demand_miss_rate::cpu0.itb.walker 0.013889 # miss rate for demand accesses 2450system.l2c.demand_miss_rate::cpu0.inst 0.322361 # miss rate for demand accesses 2451system.l2c.demand_miss_rate::cpu0.data 0.435658 # miss rate for demand accesses 2452system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.639132 # miss rate for demand accesses 2453system.l2c.demand_miss_rate::cpu1.dtb.walker 0.142857 # miss rate for demand accesses 2454system.l2c.demand_miss_rate::cpu1.inst 0.158021 # miss rate for demand accesses 2455system.l2c.demand_miss_rate::cpu1.data 0.507959 # miss rate for demand accesses 2456system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.450992 # miss rate for demand accesses 2457system.l2c.demand_miss_rate::total 0.515504 # miss rate for demand accesses 2458system.l2c.overall_miss_rate::cpu0.dtb.walker 0.264448 # miss rate for overall accesses 2459system.l2c.overall_miss_rate::cpu0.itb.walker 0.013889 # miss rate for overall accesses 2460system.l2c.overall_miss_rate::cpu0.inst 0.322361 # miss rate for overall accesses 2461system.l2c.overall_miss_rate::cpu0.data 0.435658 # miss rate for overall accesses 2462system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.639132 # miss rate for overall accesses 2463system.l2c.overall_miss_rate::cpu1.dtb.walker 0.142857 # miss rate for overall accesses 2464system.l2c.overall_miss_rate::cpu1.inst 0.158021 # miss rate for overall accesses 2465system.l2c.overall_miss_rate::cpu1.data 0.507959 # miss rate for overall accesses 2466system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.450992 # miss rate for overall accesses 2467system.l2c.overall_miss_rate::total 0.515504 # miss rate for overall accesses 2468system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 89567.880795 # average ReadReq miss latency 2469system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82500 # average ReadReq miss latency 2470system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80562.274762 # average ReadReq miss latency 2471system.l2c.ReadReq_avg_miss_latency::cpu0.data 87039.753759 # average ReadReq miss latency 2472system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 103084.160313 # average ReadReq miss latency 2473system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 109500 # average ReadReq miss latency 2474system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83683.315247 # average ReadReq miss latency 2475system.l2c.ReadReq_avg_miss_latency::cpu1.data 86487.549365 # average ReadReq miss latency 2476system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 131961.518447 # average ReadReq miss latency 2477system.l2c.ReadReq_avg_miss_latency::total 99951.316455 # average ReadReq miss latency 2478system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 935.618564 # average UpgradeReq miss latency 2479system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 936.397915 # average UpgradeReq miss latency 2480system.l2c.UpgradeReq_avg_miss_latency::total 935.806405 # average UpgradeReq miss latency 2481system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1900.814761 # average SCUpgradeReq miss latency 2482system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 999.967969 # average SCUpgradeReq miss latency 2483system.l2c.SCUpgradeReq_avg_miss_latency::total 1315.789954 # average SCUpgradeReq miss latency 2484system.l2c.ReadExReq_avg_miss_latency::cpu0.data 92568.699232 # average ReadExReq miss latency 2485system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82292.930640 # average ReadExReq miss latency 2486system.l2c.ReadExReq_avg_miss_latency::total 88196.730149 # average ReadExReq miss latency 2487system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 89567.880795 # average overall miss latency 2488system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency 2489system.l2c.demand_avg_miss_latency::cpu0.inst 80562.274762 # average overall miss latency 2490system.l2c.demand_avg_miss_latency::cpu0.data 90207.338002 # average overall miss latency 2491system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 103084.160313 # average overall miss latency 2492system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 109500 # average overall miss latency 2493system.l2c.demand_avg_miss_latency::cpu1.inst 83683.315247 # average overall miss latency 2494system.l2c.demand_avg_miss_latency::cpu1.data 82748.751222 # average overall miss latency 2495system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 131961.518447 # average overall miss latency 2496system.l2c.demand_avg_miss_latency::total 98770.559325 # average overall miss latency 2497system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 89567.880795 # average overall miss latency 2498system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency 2499system.l2c.overall_avg_miss_latency::cpu0.inst 80562.274762 # average overall miss latency 2500system.l2c.overall_avg_miss_latency::cpu0.data 90207.338002 # average overall miss latency 2501system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 103084.160313 # average overall miss latency 2502system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 109500 # average overall miss latency 2503system.l2c.overall_avg_miss_latency::cpu1.inst 83683.315247 # average overall miss latency 2504system.l2c.overall_avg_miss_latency::cpu1.data 82748.751222 # average overall miss latency 2505system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 131961.518447 # average overall miss latency 2506system.l2c.overall_avg_miss_latency::total 98770.559325 # average overall miss latency |
| 2508system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2509system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2510system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2511system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2512system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2513system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2514system.l2c.fast_writes 0 # number of fast writes performed 2515system.l2c.cache_copies 0 # number of cache copies performed | 2507system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2508system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2509system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2510system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2511system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2512system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2513system.l2c.fast_writes 0 # number of fast writes performed 2514system.l2c.cache_copies 0 # number of cache copies performed |
| 2516system.l2c.writebacks::writebacks 104097 # number of writebacks 2517system.l2c.writebacks::total 104097 # number of writebacks 2518system.l2c.ReadReq_mshr_hits::cpu0.inst 8 # number of ReadReq MSHR hits 2519system.l2c.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits 2520system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 2521system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits 2522system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits 2523system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 2524system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits 2525system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits 2526system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits 2527system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 162 # number of ReadReq MSHR misses | 2515system.l2c.writebacks::writebacks 101714 # number of writebacks 2516system.l2c.writebacks::total 101714 # number of writebacks 2517system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 2518system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits 2519system.l2c.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 2520system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 2521system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits 2522system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits 2523system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 2524system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits 2525system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits 2526system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 151 # number of ReadReq MSHR misses |
| 2528system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses | 2527system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses |
| 2529system.l2c.ReadReq_mshr_misses::cpu0.inst 23847 # number of ReadReq MSHR misses 2530system.l2c.ReadReq_mshr_misses::cpu0.data 8693 # number of ReadReq MSHR misses 2531system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 136690 # number of ReadReq MSHR misses 2532system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 12 # number of ReadReq MSHR misses 2533system.l2c.ReadReq_mshr_misses::cpu1.inst 2289 # number of ReadReq MSHR misses 2534system.l2c.ReadReq_mshr_misses::cpu1.data 1041 # number of ReadReq MSHR misses 2535system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of ReadReq MSHR misses 2536system.l2c.ReadReq_mshr_misses::total 178984 # number of ReadReq MSHR misses 2537system.l2c.UpgradeReq_mshr_misses::cpu0.data 8970 # number of UpgradeReq MSHR misses 2538system.l2c.UpgradeReq_mshr_misses::cpu1.data 2734 # number of UpgradeReq MSHR misses 2539system.l2c.UpgradeReq_mshr_misses::total 11704 # number of UpgradeReq MSHR misses 2540system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 618 # number of SCUpgradeReq MSHR misses 2541system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1189 # number of SCUpgradeReq MSHR misses 2542system.l2c.SCUpgradeReq_mshr_misses::total 1807 # number of SCUpgradeReq MSHR misses 2543system.l2c.ReadExReq_mshr_misses::cpu0.data 11575 # number of ReadExReq MSHR misses 2544system.l2c.ReadExReq_mshr_misses::cpu1.data 8676 # number of ReadExReq MSHR misses 2545system.l2c.ReadExReq_mshr_misses::total 20251 # number of ReadExReq MSHR misses 2546system.l2c.demand_mshr_misses::cpu0.dtb.walker 162 # number of demand (read+write) MSHR misses | 2528system.l2c.ReadReq_mshr_misses::cpu0.inst 22826 # number of ReadReq MSHR misses 2529system.l2c.ReadReq_mshr_misses::cpu0.data 8447 # number of ReadReq MSHR misses 2530system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 134637 # number of ReadReq MSHR misses 2531system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 21 # number of ReadReq MSHR misses 2532system.l2c.ReadReq_mshr_misses::cpu1.inst 3297 # number of ReadReq MSHR misses 2533system.l2c.ReadReq_mshr_misses::cpu1.data 1023 # number of ReadReq MSHR misses 2534system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 6207 # number of ReadReq MSHR misses 2535system.l2c.ReadReq_mshr_misses::total 176610 # number of ReadReq MSHR misses 2536system.l2c.UpgradeReq_mshr_misses::cpu0.data 9362 # number of UpgradeReq MSHR misses 2537system.l2c.UpgradeReq_mshr_misses::cpu1.data 2973 # number of UpgradeReq MSHR misses 2538system.l2c.UpgradeReq_mshr_misses::total 12335 # number of UpgradeReq MSHR misses 2539system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 691 # number of SCUpgradeReq MSHR misses 2540system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1280 # number of SCUpgradeReq MSHR misses 2541system.l2c.SCUpgradeReq_mshr_misses::total 1971 # number of SCUpgradeReq MSHR misses 2542system.l2c.ReadExReq_mshr_misses::cpu0.data 11331 # number of ReadExReq MSHR misses 2543system.l2c.ReadExReq_mshr_misses::cpu1.data 8391 # number of ReadExReq MSHR misses 2544system.l2c.ReadExReq_mshr_misses::total 19722 # number of ReadExReq MSHR misses 2545system.l2c.demand_mshr_misses::cpu0.dtb.walker 151 # number of demand (read+write) MSHR misses |
| 2547system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses | 2546system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses |
| 2548system.l2c.demand_mshr_misses::cpu0.inst 23847 # number of demand (read+write) MSHR misses 2549system.l2c.demand_mshr_misses::cpu0.data 20268 # number of demand (read+write) MSHR misses 2550system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 136690 # number of demand (read+write) MSHR misses 2551system.l2c.demand_mshr_misses::cpu1.dtb.walker 12 # number of demand (read+write) MSHR misses 2552system.l2c.demand_mshr_misses::cpu1.inst 2289 # number of demand (read+write) MSHR misses 2553system.l2c.demand_mshr_misses::cpu1.data 9717 # number of demand (read+write) MSHR misses 2554system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of demand (read+write) MSHR misses 2555system.l2c.demand_mshr_misses::total 199235 # number of demand (read+write) MSHR misses 2556system.l2c.overall_mshr_misses::cpu0.dtb.walker 162 # number of overall MSHR misses | 2547system.l2c.demand_mshr_misses::cpu0.inst 22826 # number of demand (read+write) MSHR misses 2548system.l2c.demand_mshr_misses::cpu0.data 19778 # number of demand (read+write) MSHR misses 2549system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134637 # number of demand (read+write) MSHR misses 2550system.l2c.demand_mshr_misses::cpu1.dtb.walker 21 # number of demand (read+write) MSHR misses 2551system.l2c.demand_mshr_misses::cpu1.inst 3297 # number of demand (read+write) MSHR misses 2552system.l2c.demand_mshr_misses::cpu1.data 9414 # number of demand (read+write) MSHR misses 2553system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6207 # number of demand (read+write) MSHR misses 2554system.l2c.demand_mshr_misses::total 196332 # number of demand (read+write) MSHR misses 2555system.l2c.overall_mshr_misses::cpu0.dtb.walker 151 # number of overall MSHR misses |
| 2557system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses | 2556system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses |
| 2558system.l2c.overall_mshr_misses::cpu0.inst 23847 # number of overall MSHR misses 2559system.l2c.overall_mshr_misses::cpu0.data 20268 # number of overall MSHR misses 2560system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 136690 # number of overall MSHR misses 2561system.l2c.overall_mshr_misses::cpu1.dtb.walker 12 # number of overall MSHR misses 2562system.l2c.overall_mshr_misses::cpu1.inst 2289 # number of overall MSHR misses 2563system.l2c.overall_mshr_misses::cpu1.data 9717 # number of overall MSHR misses 2564system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of overall MSHR misses 2565system.l2c.overall_mshr_misses::total 199235 # number of overall MSHR misses 2566system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10991250 # number of ReadReq MSHR miss cycles 2567system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles 2568system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1445321741 # number of ReadReq MSHR miss cycles 2569system.l2c.ReadReq_mshr_miss_latency::cpu0.data 589131498 # number of ReadReq MSHR miss cycles 2570system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12379828891 # number of ReadReq MSHR miss cycles 2571system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 810750 # number of ReadReq MSHR miss cycles 2572system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 143882249 # number of ReadReq MSHR miss cycles 2573system.l2c.ReadReq_mshr_miss_latency::cpu1.data 72327750 # number of ReadReq MSHR miss cycles 2574system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 749741791 # number of ReadReq MSHR miss cycles 2575system.l2c.ReadReq_mshr_miss_latency::total 15392098420 # number of ReadReq MSHR miss cycles 2576system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 91762404 # number of UpgradeReq MSHR miss cycles 2577system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 27532715 # number of UpgradeReq MSHR miss cycles 2578system.l2c.UpgradeReq_mshr_miss_latency::total 119295119 # number of UpgradeReq MSHR miss cycles 2579system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6310115 # number of SCUpgradeReq MSHR miss cycles 2580system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 11917186 # number of SCUpgradeReq MSHR miss cycles 2581system.l2c.SCUpgradeReq_mshr_miss_latency::total 18227301 # number of SCUpgradeReq MSHR miss cycles 2582system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 807808323 # number of ReadExReq MSHR miss cycles 2583system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 530171012 # number of ReadExReq MSHR miss cycles 2584system.l2c.ReadExReq_mshr_miss_latency::total 1337979335 # number of ReadExReq MSHR miss cycles 2585system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10991250 # number of demand (read+write) MSHR miss cycles 2586system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles 2587system.l2c.demand_mshr_miss_latency::cpu0.inst 1445321741 # number of demand (read+write) MSHR miss cycles 2588system.l2c.demand_mshr_miss_latency::cpu0.data 1396939821 # number of demand (read+write) MSHR miss cycles 2589system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12379828891 # number of demand (read+write) MSHR miss cycles 2590system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 810750 # number of demand (read+write) MSHR miss cycles 2591system.l2c.demand_mshr_miss_latency::cpu1.inst 143882249 # number of demand (read+write) MSHR miss cycles 2592system.l2c.demand_mshr_miss_latency::cpu1.data 602498762 # number of demand (read+write) MSHR miss cycles 2593system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 749741791 # number of demand (read+write) MSHR miss cycles 2594system.l2c.demand_mshr_miss_latency::total 16730077755 # number of demand (read+write) MSHR miss cycles 2595system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10991250 # number of overall MSHR miss cycles 2596system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles 2597system.l2c.overall_mshr_miss_latency::cpu0.inst 1445321741 # number of overall MSHR miss cycles 2598system.l2c.overall_mshr_miss_latency::cpu0.data 1396939821 # number of overall MSHR miss cycles 2599system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12379828891 # number of overall MSHR miss cycles 2600system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 810750 # number of overall MSHR miss cycles 2601system.l2c.overall_mshr_miss_latency::cpu1.inst 143882249 # number of overall MSHR miss cycles 2602system.l2c.overall_mshr_miss_latency::cpu1.data 602498762 # number of overall MSHR miss cycles 2603system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 749741791 # number of overall MSHR miss cycles 2604system.l2c.overall_mshr_miss_latency::total 16730077755 # number of overall MSHR miss cycles 2605system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 163590000 # number of ReadReq MSHR uncacheable cycles 2606system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5355654498 # number of ReadReq MSHR uncacheable cycles 2607system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6093250 # number of ReadReq MSHR uncacheable cycles 2608system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 257169500 # number of ReadReq MSHR uncacheable cycles 2609system.l2c.ReadReq_mshr_uncacheable_latency::total 5782507248 # number of ReadReq MSHR uncacheable cycles 2610system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4096891000 # number of WriteReq MSHR uncacheable cycles 2611system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 150604000 # number of WriteReq MSHR uncacheable cycles 2612system.l2c.WriteReq_mshr_uncacheable_latency::total 4247495000 # number of WriteReq MSHR uncacheable cycles 2613system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 163590000 # number of overall MSHR uncacheable cycles 2614system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9452545498 # number of overall MSHR uncacheable cycles 2615system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6093250 # number of overall MSHR uncacheable cycles 2616system.l2c.overall_mshr_uncacheable_latency::cpu1.data 407773500 # number of overall MSHR uncacheable cycles 2617system.l2c.overall_mshr_uncacheable_latency::total 10030002248 # number of overall MSHR uncacheable cycles 2618system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for ReadReq accesses 2619system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for ReadReq accesses 2620system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.327488 # mshr miss rate for ReadReq accesses 2621system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.286105 # mshr miss rate for ReadReq accesses 2622system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for ReadReq accesses 2623system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for ReadReq accesses 2624system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.120855 # mshr miss rate for ReadReq accesses 2625system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.123929 # mshr miss rate for ReadReq accesses 2626system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for ReadReq accesses 2627system.l2c.ReadReq_mshr_miss_rate::total 0.500587 # mshr miss rate for ReadReq accesses 2628system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.753275 # mshr miss rate for UpgradeReq accesses 2629system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.806014 # mshr miss rate for UpgradeReq accesses 2630system.l2c.UpgradeReq_mshr_miss_rate::total 0.764967 # mshr miss rate for UpgradeReq accesses 2631system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.813158 # mshr miss rate for SCUpgradeReq accesses 2632system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.871062 # mshr miss rate for SCUpgradeReq accesses 2633system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.850353 # mshr miss rate for SCUpgradeReq accesses 2634system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.750795 # mshr miss rate for ReadExReq accesses 2635system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.866906 # mshr miss rate for ReadExReq accesses 2636system.l2c.ReadExReq_mshr_miss_rate::total 0.796500 # mshr miss rate for ReadExReq accesses 2637system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for demand accesses 2638system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for demand accesses 2639system.l2c.demand_mshr_miss_rate::cpu0.inst 0.327488 # mshr miss rate for demand accesses 2640system.l2c.demand_mshr_miss_rate::cpu0.data 0.442523 # mshr miss rate for demand accesses 2641system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for demand accesses 2642system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for demand accesses 2643system.l2c.demand_mshr_miss_rate::cpu1.inst 0.120855 # mshr miss rate for demand accesses 2644system.l2c.demand_mshr_miss_rate::cpu1.data 0.527868 # mshr miss rate for demand accesses 2645system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for demand accesses 2646system.l2c.demand_mshr_miss_rate::total 0.520232 # mshr miss rate for demand accesses 2647system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for overall accesses 2648system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for overall accesses 2649system.l2c.overall_mshr_miss_rate::cpu0.inst 0.327488 # mshr miss rate for overall accesses 2650system.l2c.overall_mshr_miss_rate::cpu0.data 0.442523 # mshr miss rate for overall accesses 2651system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for overall accesses 2652system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for overall accesses 2653system.l2c.overall_mshr_miss_rate::cpu1.inst 0.120855 # mshr miss rate for overall accesses 2654system.l2c.overall_mshr_miss_rate::cpu1.data 0.527868 # mshr miss rate for overall accesses 2655system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for overall accesses 2656system.l2c.overall_mshr_miss_rate::total 0.520232 # mshr miss rate for overall accesses 2657system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average ReadReq mshr miss latency 2658system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency 2659system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60608.115947 # average ReadReq mshr miss latency 2660system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67770.792362 # average ReadReq mshr miss latency 2661system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average ReadReq mshr miss latency 2662system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average ReadReq mshr miss latency 2663system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62858.125382 # average ReadReq mshr miss latency 2664system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 69479.106628 # average ReadReq mshr miss latency 2665system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average ReadReq mshr miss latency 2666system.l2c.ReadReq_avg_mshr_miss_latency::total 85997.063536 # average ReadReq mshr miss latency 2667system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10229.922408 # average UpgradeReq mshr miss latency 2668system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10070.488296 # average UpgradeReq mshr miss latency 2669system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10192.679340 # average UpgradeReq mshr miss latency 2670system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10210.542071 # average SCUpgradeReq mshr miss latency 2671system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10022.864592 # average SCUpgradeReq mshr miss latency 2672system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10087.050913 # average SCUpgradeReq mshr miss latency 2673system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69789.055983 # average ReadExReq mshr miss latency 2674system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61107.769940 # average ReadExReq mshr miss latency 2675system.l2c.ReadExReq_avg_mshr_miss_latency::total 66069.790875 # average ReadExReq mshr miss latency 2676system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average overall mshr miss latency 2677system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 2678system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60608.115947 # average overall mshr miss latency 2679system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68923.417259 # average overall mshr miss latency 2680system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average overall mshr miss latency 2681system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average overall mshr miss latency 2682system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62858.125382 # average overall mshr miss latency 2683system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62004.606566 # average overall mshr miss latency 2684system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average overall mshr miss latency 2685system.l2c.demand_avg_mshr_miss_latency::total 83971.580069 # average overall mshr miss latency 2686system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average overall mshr miss latency 2687system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 2688system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60608.115947 # average overall mshr miss latency 2689system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68923.417259 # average overall mshr miss latency 2690system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average overall mshr miss latency 2691system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average overall mshr miss latency 2692system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62858.125382 # average overall mshr miss latency 2693system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62004.606566 # average overall mshr miss latency 2694system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average overall mshr miss latency 2695system.l2c.overall_avg_mshr_miss_latency::total 83971.580069 # average overall mshr miss latency | 2557system.l2c.overall_mshr_misses::cpu0.inst 22826 # number of overall MSHR misses 2558system.l2c.overall_mshr_misses::cpu0.data 19778 # number of overall MSHR misses 2559system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134637 # number of overall MSHR misses 2560system.l2c.overall_mshr_misses::cpu1.dtb.walker 21 # number of overall MSHR misses 2561system.l2c.overall_mshr_misses::cpu1.inst 3297 # number of overall MSHR misses 2562system.l2c.overall_mshr_misses::cpu1.data 9414 # number of overall MSHR misses 2563system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6207 # number of overall MSHR misses 2564system.l2c.overall_mshr_misses::total 196332 # number of overall MSHR misses 2565system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 11628250 # number of ReadReq MSHR miss cycles 2566system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 70000 # number of ReadReq MSHR miss cycles 2567system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1553014454 # number of ReadReq MSHR miss cycles 2568system.l2c.ReadReq_mshr_miss_latency::cpu0.data 629441200 # number of ReadReq MSHR miss cycles 2569system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12219469940 # number of ReadReq MSHR miss cycles 2570system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 2036500 # number of ReadReq MSHR miss cycles 2571system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 234611993 # number of ReadReq MSHR miss cycles 2572system.l2c.ReadReq_mshr_miss_latency::cpu1.data 75645237 # number of ReadReq MSHR miss cycles 2573system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 743074583 # number of ReadReq MSHR miss cycles 2574system.l2c.ReadReq_mshr_miss_latency::total 15468992157 # number of ReadReq MSHR miss cycles 2575system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 166983326 # number of UpgradeReq MSHR miss cycles 2576system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 52806462 # number of UpgradeReq MSHR miss cycles 2577system.l2c.UpgradeReq_mshr_miss_latency::total 219789788 # number of UpgradeReq MSHR miss cycles 2578system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12384188 # number of SCUpgradeReq MSHR miss cycles 2579system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22755279 # number of SCUpgradeReq MSHR miss cycles 2580system.l2c.SCUpgradeReq_mshr_miss_latency::total 35139467 # number of SCUpgradeReq MSHR miss cycles 2581system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 908785069 # number of ReadExReq MSHR miss cycles 2582system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 585566519 # number of ReadExReq MSHR miss cycles 2583system.l2c.ReadExReq_mshr_miss_latency::total 1494351588 # number of ReadExReq MSHR miss cycles 2584system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 11628250 # number of demand (read+write) MSHR miss cycles 2585system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 70000 # number of demand (read+write) MSHR miss cycles 2586system.l2c.demand_mshr_miss_latency::cpu0.inst 1553014454 # number of demand (read+write) MSHR miss cycles 2587system.l2c.demand_mshr_miss_latency::cpu0.data 1538226269 # number of demand (read+write) MSHR miss cycles 2588system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12219469940 # number of demand (read+write) MSHR miss cycles 2589system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 2036500 # number of demand (read+write) MSHR miss cycles 2590system.l2c.demand_mshr_miss_latency::cpu1.inst 234611993 # number of demand (read+write) MSHR miss cycles 2591system.l2c.demand_mshr_miss_latency::cpu1.data 661211756 # number of demand (read+write) MSHR miss cycles 2592system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 743074583 # number of demand (read+write) MSHR miss cycles 2593system.l2c.demand_mshr_miss_latency::total 16963343745 # number of demand (read+write) MSHR miss cycles 2594system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 11628250 # number of overall MSHR miss cycles 2595system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 70000 # number of overall MSHR miss cycles 2596system.l2c.overall_mshr_miss_latency::cpu0.inst 1553014454 # number of overall MSHR miss cycles 2597system.l2c.overall_mshr_miss_latency::cpu0.data 1538226269 # number of overall MSHR miss cycles 2598system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12219469940 # number of overall MSHR miss cycles 2599system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2036500 # number of overall MSHR miss cycles 2600system.l2c.overall_mshr_miss_latency::cpu1.inst 234611993 # number of overall MSHR miss cycles 2601system.l2c.overall_mshr_miss_latency::cpu1.data 661211756 # number of overall MSHR miss cycles 2602system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 743074583 # number of overall MSHR miss cycles 2603system.l2c.overall_mshr_miss_latency::total 16963343745 # number of overall MSHR miss cycles 2604system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 205849250 # number of ReadReq MSHR uncacheable cycles 2605system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3714789750 # number of ReadReq MSHR uncacheable cycles 2606system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6630000 # number of ReadReq MSHR uncacheable cycles 2607system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1920029500 # number of ReadReq MSHR uncacheable cycles 2608system.l2c.ReadReq_mshr_uncacheable_latency::total 5847298500 # number of ReadReq MSHR uncacheable cycles 2609system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2763619000 # number of WriteReq MSHR uncacheable cycles 2610system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1533180000 # number of WriteReq MSHR uncacheable cycles 2611system.l2c.WriteReq_mshr_uncacheable_latency::total 4296799000 # number of WriteReq MSHR uncacheable cycles 2612system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 205849250 # number of overall MSHR uncacheable cycles 2613system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6478408750 # number of overall MSHR uncacheable cycles 2614system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6630000 # number of overall MSHR uncacheable cycles 2615system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3453209500 # number of overall MSHR uncacheable cycles 2616system.l2c.overall_mshr_uncacheable_latency::total 10144097500 # number of overall MSHR uncacheable cycles 2617system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.264448 # mshr miss rate for ReadReq accesses 2618system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013889 # mshr miss rate for ReadReq accesses 2619system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.322346 # mshr miss rate for ReadReq accesses 2620system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.281304 # mshr miss rate for ReadReq accesses 2621system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.639132 # mshr miss rate for ReadReq accesses 2622system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for ReadReq accesses 2623system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.157925 # mshr miss rate for ReadReq accesses 2624system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.121079 # mshr miss rate for ReadReq accesses 2625system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.450992 # mshr miss rate for ReadReq accesses 2626system.l2c.ReadReq_mshr_miss_rate::total 0.496925 # mshr miss rate for ReadReq accesses 2627system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.749800 # mshr miss rate for UpgradeReq accesses 2628system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.795558 # mshr miss rate for UpgradeReq accesses 2629system.l2c.UpgradeReq_mshr_miss_rate::total 0.760340 # mshr miss rate for UpgradeReq accesses 2630system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.808187 # mshr miss rate for SCUpgradeReq accesses 2631system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.891365 # mshr miss rate for SCUpgradeReq accesses 2632system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.860323 # mshr miss rate for SCUpgradeReq accesses 2633system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.737215 # mshr miss rate for ReadExReq accesses 2634system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.832110 # mshr miss rate for ReadExReq accesses 2635system.l2c.ReadExReq_mshr_miss_rate::total 0.774809 # mshr miss rate for ReadExReq accesses 2636system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.264448 # mshr miss rate for demand accesses 2637system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.013889 # mshr miss rate for demand accesses 2638system.l2c.demand_mshr_miss_rate::cpu0.inst 0.322346 # mshr miss rate for demand accesses 2639system.l2c.demand_mshr_miss_rate::cpu0.data 0.435658 # mshr miss rate for demand accesses 2640system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.639132 # mshr miss rate for demand accesses 2641system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for demand accesses 2642system.l2c.demand_mshr_miss_rate::cpu1.inst 0.157925 # mshr miss rate for demand accesses 2643system.l2c.demand_mshr_miss_rate::cpu1.data 0.507959 # mshr miss rate for demand accesses 2644system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.450992 # mshr miss rate for demand accesses 2645system.l2c.demand_mshr_miss_rate::total 0.515497 # mshr miss rate for demand accesses 2646system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.264448 # mshr miss rate for overall accesses 2647system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.013889 # mshr miss rate for overall accesses 2648system.l2c.overall_mshr_miss_rate::cpu0.inst 0.322346 # mshr miss rate for overall accesses 2649system.l2c.overall_mshr_miss_rate::cpu0.data 0.435658 # mshr miss rate for overall accesses 2650system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.639132 # mshr miss rate for overall accesses 2651system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for overall accesses 2652system.l2c.overall_mshr_miss_rate::cpu1.inst 0.157925 # mshr miss rate for overall accesses 2653system.l2c.overall_mshr_miss_rate::cpu1.data 0.507959 # mshr miss rate for overall accesses 2654system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.450992 # mshr miss rate for overall accesses 2655system.l2c.overall_mshr_miss_rate::total 0.515497 # mshr miss rate for overall accesses 2656system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77008.278146 # average ReadReq mshr miss latency 2657system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency 2658system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68037.082888 # average ReadReq mshr miss latency 2659system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74516.538416 # average ReadReq mshr miss latency 2660system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90758.632025 # average ReadReq mshr miss latency 2661system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 96976.190476 # average ReadReq mshr miss latency 2662system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71159.233546 # average ReadReq mshr miss latency 2663system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73944.513196 # average ReadReq mshr miss latency 2664system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119715.576446 # average ReadReq mshr miss latency 2665system.l2c.ReadReq_avg_mshr_miss_latency::total 87588.427365 # average ReadReq mshr miss latency 2666system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17836.287759 # average UpgradeReq mshr miss latency 2667system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17762.012109 # average UpgradeReq mshr miss latency 2668system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17818.385732 # average UpgradeReq mshr miss latency 2669system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17922.124457 # average SCUpgradeReq mshr miss latency 2670system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17777.561719 # average SCUpgradeReq mshr miss latency 2671system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17828.243024 # average SCUpgradeReq mshr miss latency 2672system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80203.430324 # average ReadExReq mshr miss latency 2673system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69785.069598 # average ReadExReq mshr miss latency 2674system.l2c.ReadExReq_avg_mshr_miss_latency::total 75770.793429 # average ReadExReq mshr miss latency 2675system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77008.278146 # average overall mshr miss latency 2676system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency 2677system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68037.082888 # average overall mshr miss latency 2678system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77774.611639 # average overall mshr miss latency 2679system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90758.632025 # average overall mshr miss latency 2680system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 96976.190476 # average overall mshr miss latency 2681system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71159.233546 # average overall mshr miss latency 2682system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70237.067771 # average overall mshr miss latency 2683system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119715.576446 # average overall mshr miss latency 2684system.l2c.demand_avg_mshr_miss_latency::total 86401.318914 # average overall mshr miss latency 2685system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77008.278146 # average overall mshr miss latency 2686system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency 2687system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68037.082888 # average overall mshr miss latency 2688system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77774.611639 # average overall mshr miss latency 2689system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90758.632025 # average overall mshr miss latency 2690system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 96976.190476 # average overall mshr miss latency 2691system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71159.233546 # average overall mshr miss latency 2692system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70237.067771 # average overall mshr miss latency 2693system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119715.576446 # average overall mshr miss latency 2694system.l2c.overall_avg_mshr_miss_latency::total 86401.318914 # average overall mshr miss latency |
| 2696system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 2697system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 2698system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2699system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2700system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2701system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 2702system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2703system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2704system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 2705system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 2706system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2707system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2708system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2709system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 2695system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 2696system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 2697system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2698system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2699system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2700system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 2701system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2702system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2703system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 2704system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 2705system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2706system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2707system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2708system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2710system.membus.trans_dist::ReadReq 217279 # Transaction distribution 2711system.membus.trans_dist::ReadResp 217279 # Transaction distribution 2712system.membus.trans_dist::WriteReq 30939 # Transaction distribution 2713system.membus.trans_dist::WriteResp 30939 # Transaction distribution 2714system.membus.trans_dist::Writeback 140271 # Transaction distribution | 2709system.membus.trans_dist::ReadReq 215369 # Transaction distribution 2710system.membus.trans_dist::ReadResp 215369 # Transaction distribution 2711system.membus.trans_dist::WriteReq 31074 # Transaction distribution 2712system.membus.trans_dist::WriteResp 31074 # Transaction distribution 2713system.membus.trans_dist::Writeback 137904 # Transaction distribution |
| 2715system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2716system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution | 2714system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2715system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 2717system.membus.trans_dist::UpgradeReq 75080 # Transaction distribution 2718system.membus.trans_dist::SCUpgradeReq 40217 # Transaction distribution 2719system.membus.trans_dist::UpgradeResp 13603 # Transaction distribution 2720system.membus.trans_dist::ReadExReq 40948 # Transaction distribution 2721system.membus.trans_dist::ReadExResp 20159 # Transaction distribution 2722system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) | 2716system.membus.trans_dist::UpgradeReq 77019 # Transaction distribution 2717system.membus.trans_dist::SCUpgradeReq 40910 # Transaction distribution 2718system.membus.trans_dist::UpgradeResp 14411 # Transaction distribution 2719system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution 2720system.membus.trans_dist::ReadExReq 39992 # Transaction distribution 2721system.membus.trans_dist::ReadExResp 19617 # Transaction distribution 2722system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) |
| 2723system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) | 2723system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) |
| 2724system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13590 # Packet count per connected master and slave (bytes) 2725system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 668031 # Packet count per connected master and slave (bytes) 2726system.membus.pkt_count_system.l2c.mem_side::total 789629 # Packet count per connected master and slave (bytes) 2727system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108880 # Packet count per connected master and slave (bytes) 2728system.membus.pkt_count_system.iocache.mem_side::total 108880 # Packet count per connected master and slave (bytes) 2729system.membus.pkt_count::total 898509 # Packet count per connected master and slave (bytes) 2730system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) | 2724system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14196 # Packet count per connected master and slave (bytes) 2725system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 663493 # Packet count per connected master and slave (bytes) 2726system.membus.pkt_count_system.l2c.mem_side::total 785643 # Packet count per connected master and slave (bytes) 2727system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes) 2728system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes) 2729system.membus.pkt_count::total 894551 # Packet count per connected master and slave (bytes) 2730system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) |
| 2731system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) | 2731system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) |
| 2732system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27180 # Cumulative packet size per connected master and slave (bytes) 2733system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19605228 # Cumulative packet size per connected master and slave (bytes) 2734system.membus.pkt_size_system.l2c.mem_side::total 19796474 # Cumulative packet size per connected master and slave (bytes) 2735system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4634432 # Cumulative packet size per connected master and slave (bytes) 2736system.membus.pkt_size_system.iocache.mem_side::total 4634432 # Cumulative packet size per connected master and slave (bytes) 2737system.membus.pkt_size::total 24430906 # Cumulative packet size per connected master and slave (bytes) 2738system.membus.snoops 123136 # Total snoops (count) 2739system.membus.snoop_fanout::samples 511969 # Request fanout histogram | 2732system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28392 # Cumulative packet size per connected master and slave (bytes) 2733system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19286572 # Cumulative packet size per connected master and slave (bytes) 2734system.membus.pkt_size_system.l2c.mem_side::total 19478976 # Cumulative packet size per connected master and slave (bytes) 2735system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 2736system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) 2737system.membus.pkt_size::total 24114432 # Cumulative packet size per connected master and slave (bytes) 2738system.membus.snoops 124537 # Total snoops (count) 2739system.membus.snoop_fanout::samples 508980 # Request fanout histogram |
| 2740system.membus.snoop_fanout::mean 1 # Request fanout histogram 2741system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2742system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2743system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 2740system.membus.snoop_fanout::mean 1 # Request fanout histogram 2741system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2742system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2743system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 2744system.membus.snoop_fanout::1 511969 100.00% 100.00% # Request fanout histogram | 2744system.membus.snoop_fanout::1 508980 100.00% 100.00% # Request fanout histogram |
| 2745system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2746system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2747system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2748system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 2745system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2746system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2747system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2748system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 2749system.membus.snoop_fanout::total 511969 # Request fanout histogram 2750system.membus.reqLayer0.occupancy 88887000 # Layer occupancy (ticks) | 2749system.membus.snoop_fanout::total 508980 # Request fanout histogram 2750system.membus.reqLayer0.occupancy 88720999 # Layer occupancy (ticks) |
| 2751system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 2751system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 2752system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) | 2752system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) |
| 2753system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 2753system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 2754system.membus.reqLayer2.occupancy 11855500 # Layer occupancy (ticks) | 2754system.membus.reqLayer2.occupancy 12492999 # Layer occupancy (ticks) |
| 2755system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 2755system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 2756system.membus.reqLayer5.occupancy 1869891749 # Layer occupancy (ticks) 2757system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) 2758system.membus.respLayer2.occupancy 2005520473 # Layer occupancy (ticks) 2759system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 2760system.membus.respLayer3.occupancy 38480431 # Layer occupancy (ticks) | 2756system.membus.reqLayer5.occupancy 1167594605 # Layer occupancy (ticks) 2757system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 2758system.membus.respLayer2.occupancy 1174957130 # Layer occupancy (ticks) 2759system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2760system.membus.respLayer3.occupancy 37546467 # Layer occupancy (ticks) |
| 2761system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2762system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2763system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2764system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2765system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2766system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2767system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2768system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 2785system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2786system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2787system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2788system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2789system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2790system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2791system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2792system.realview.ethernet.droppedPackets 0 # number of packets dropped | 2761system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2762system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2763system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2764system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2765system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2766system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2767system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2768system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 2785system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2786system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2787system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2788system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2789system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2790system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2791system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2792system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 2793system.toL2Bus.trans_dist::ReadReq 516876 # Transaction distribution 2794system.toL2Bus.trans_dist::ReadResp 516861 # Transaction distribution 2795system.toL2Bus.trans_dist::WriteReq 30939 # Transaction distribution 2796system.toL2Bus.trans_dist::WriteResp 30939 # Transaction distribution 2797system.toL2Bus.trans_dist::Writeback 234152 # Transaction distribution 2798system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2799system.toL2Bus.trans_dist::UpgradeReq 78584 # Transaction distribution 2800system.toL2Bus.trans_dist::SCUpgradeReq 40535 # Transaction distribution 2801system.toL2Bus.trans_dist::UpgradeResp 119119 # Transaction distribution 2802system.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution 2803system.toL2Bus.trans_dist::UpgradeFailResp 13 # Transaction distribution 2804system.toL2Bus.trans_dist::ReadExReq 51536 # Transaction distribution 2805system.toL2Bus.trans_dist::ReadExResp 51536 # Transaction distribution 2806system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1131248 # Packet count per connected master and slave (bytes) 2807system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 290761 # Packet count per connected master and slave (bytes) 2808system.toL2Bus.pkt_count::total 1422009 # Packet count per connected master and slave (bytes) 2809system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34509719 # Cumulative packet size per connected master and slave (bytes) 2810system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5415139 # Cumulative packet size per connected master and slave (bytes) 2811system.toL2Bus.pkt_size::total 39924858 # Cumulative packet size per connected master and slave (bytes) 2812system.toL2Bus.snoops 285546 # Total snoops (count) 2813system.toL2Bus.snoop_fanout::samples 919868 # Request fanout histogram 2814system.toL2Bus.snoop_fanout::mean 1.039644 # Request fanout histogram 2815system.toL2Bus.snoop_fanout::stdev 0.195121 # Request fanout histogram | 2793system.toL2Bus.trans_dist::ReadReq 518257 # Transaction distribution 2794system.toL2Bus.trans_dist::ReadResp 518242 # Transaction distribution 2795system.toL2Bus.trans_dist::WriteReq 31074 # Transaction distribution 2796system.toL2Bus.trans_dist::WriteResp 31074 # Transaction distribution 2797system.toL2Bus.trans_dist::Writeback 232242 # Transaction distribution 2798system.toL2Bus.trans_dist::WriteInvalidateReq 36265 # Transaction distribution 2799system.toL2Bus.trans_dist::UpgradeReq 80802 # Transaction distribution 2800system.toL2Bus.trans_dist::SCUpgradeReq 41230 # Transaction distribution 2801system.toL2Bus.trans_dist::UpgradeResp 122032 # Transaction distribution 2802system.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution 2803system.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution 2804system.toL2Bus.trans_dist::ReadExReq 51798 # Transaction distribution 2805system.toL2Bus.trans_dist::ReadExResp 51798 # Transaction distribution 2806system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1084621 # Packet count per connected master and slave (bytes) 2807system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 339731 # Packet count per connected master and slave (bytes) 2808system.toL2Bus.pkt_count::total 1424352 # Packet count per connected master and slave (bytes) 2809system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34113464 # Cumulative packet size per connected master and slave (bytes) 2810system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5575752 # Cumulative packet size per connected master and slave (bytes) 2811system.toL2Bus.pkt_size::total 39689216 # Cumulative packet size per connected master and slave (bytes) 2812system.toL2Bus.snoops 290726 # Total snoops (count) 2813system.toL2Bus.snoop_fanout::samples 922102 # Request fanout histogram 2814system.toL2Bus.snoop_fanout::mean 1.039605 # Request fanout histogram 2815system.toL2Bus.snoop_fanout::stdev 0.195030 # Request fanout histogram |
| 2816system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2817system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 2816system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2817system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 2818system.toL2Bus.snoop_fanout::1 883401 96.04% 96.04% # Request fanout histogram 2819system.toL2Bus.snoop_fanout::2 36467 3.96% 100.00% # Request fanout histogram | 2818system.toL2Bus.snoop_fanout::1 885582 96.04% 96.04% # Request fanout histogram 2819system.toL2Bus.snoop_fanout::2 36520 3.96% 100.00% # Request fanout histogram |
| 2820system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2821system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2822system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 2820system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2821system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2822system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 2823system.toL2Bus.snoop_fanout::total 919868 # Request fanout histogram 2824system.toL2Bus.reqLayer0.occupancy 1489301846 # Layer occupancy (ticks) 2825system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2826system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks) | 2823system.toL2Bus.snoop_fanout::total 922102 # Request fanout histogram 2824system.toL2Bus.reqLayer0.occupancy 794355306 # Layer occupancy (ticks) 2825system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2826system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks) |
| 2827system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2827system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2828system.toL2Bus.respLayer0.occupancy 1891845782 # Layer occupancy (ticks) 2829system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 2830system.toL2Bus.respLayer1.occupancy 645358377 # Layer occupancy (ticks) | 2828system.toL2Bus.respLayer0.occupancy 683518313 # Layer occupancy (ticks) 2829system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2830system.toL2Bus.respLayer1.occupancy 260405210 # Layer occupancy (ticks) |
| 2831system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2832 2833---------- End Simulation Statistics ---------- | 2831system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2832 2833---------- End Simulation Statistics ---------- |