| stats.txt (10585:1c9d5d9417b3) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.844427 # Number of seconds simulated 4sim_ticks 2844427140500 # Number of ticks simulated 5final_tick 2844427140500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.845843 # Number of seconds simulated 4sim_ticks 2845842660500 # Number of ticks simulated 5final_tick 2845842660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 150296 # Simulator instruction rate (inst/s) 8host_op_rate 181972 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3416553864 # Simulator tick rate (ticks/s) 10host_mem_usage 612172 # Number of bytes of host memory used 11host_seconds 832.54 # Real time elapsed on the host 12sim_insts 125127935 # Number of instructions simulated 13sim_ops 151499394 # Number of ops (including micro ops) simulated | 7host_inst_rate 164712 # Simulator instruction rate (inst/s) 8host_op_rate 199442 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3743328799 # Simulator tick rate (ticks/s) 10host_mem_usage 646452 # Number of bytes of host memory used 11host_seconds 760.24 # Real time elapsed on the host 12sim_insts 125221621 # Number of instructions simulated 13sim_ops 151624712 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu0.dtb.walker 10304 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu0.dtb.walker 10368 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu0.inst 1349820 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.l2cache.prefetcher 10836800 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 503456 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.l2cache.prefetcher 1120064 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu0.inst 3007420 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.l2cache.prefetcher 8732480 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 774240 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.l2cache.prefetcher 399936 # Number of bytes read from this memory |
| 23system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 23system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 24system.physmem.bytes_read::total 13821980 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 416640 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 27264 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 443904 # Number of instructions bytes read from this memory 28system.physmem.bytes_written::writebacks 9404288 # Number of bytes written to this memory | 24system.physmem.bytes_read::total 12926236 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 1722304 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 153024 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 1875328 # Number of instructions bytes read from this memory 28system.physmem.bytes_written::writebacks 8977344 # Number of bytes written to this memory |
| 29system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory | 29system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory |
| 31system.physmem.bytes_written::total 9422032 # Number of bytes written to this memory 32system.physmem.num_reads::cpu0.dtb.walker 161 # Number of read requests responded to by this memory | 31system.physmem.bytes_written::total 8995088 # Number of bytes written to this memory 32system.physmem.num_reads::cpu0.dtb.walker 162 # Number of read requests responded to by this memory |
| 33system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory | 33system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory |
| 34system.physmem.num_reads::cpu0.inst 21616 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.l2cache.prefetcher 169325 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.inst 7890 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.l2cache.prefetcher 17501 # Number of read requests responded to by this memory | 34system.physmem.num_reads::cpu0.inst 47516 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.l2cache.prefetcher 136445 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.inst 12121 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.l2cache.prefetcher 6249 # Number of read requests responded to by this memory |
| 39system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 39system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 40system.physmem.num_reads::total 216517 # Number of read requests responded to by this memory 41system.physmem.num_writes::writebacks 146942 # Number of write requests responded to by this memory | 40system.physmem.num_reads::total 202521 # Number of read requests responded to by this memory 41system.physmem.num_writes::writebacks 140271 # Number of write requests responded to by this memory |
| 42system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory 43system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory | 42system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory 43system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory |
| 44system.physmem.num_writes::total 151378 # Number of write requests responded to by this memory 45system.physmem.bw_read::cpu0.dtb.walker 3623 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.inst 474549 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.l2cache.prefetcher 3809836 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.dtb.walker 180 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.inst 176997 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.l2cache.prefetcher 393775 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::total 4859319 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::cpu0.inst 146476 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::cpu1.inst 9585 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::total 156061 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_write::writebacks 3306215 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::cpu0.inst 6224 # Write bandwidth from this memory (bytes/s) | 44system.physmem.num_writes::total 144707 # Number of write requests responded to by this memory 45system.physmem.bw_read::cpu0.dtb.walker 3643 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.inst 1056777 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.l2cache.prefetcher 3068504 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.dtb.walker 270 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.inst 272060 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.l2cache.prefetcher 140533 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::total 4542147 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::cpu0.inst 605200 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::cpu1.inst 53771 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::total 658971 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_write::writebacks 3154547 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::cpu0.inst 6221 # Write bandwidth from this memory (bytes/s) |
| 59system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s) | 59system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s) |
| 60system.physmem.bw_write::total 3312453 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_total::writebacks 3306215 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.dtb.walker 3623 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.inst 480773 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.l2cache.prefetcher 3809836 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.dtb.walker 180 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.inst 177011 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu1.l2cache.prefetcher 393775 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::realview.ide 338 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::total 8171773 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.readReqs 216517 # Number of read requests accepted 72system.physmem.writeReqs 187602 # Number of write requests accepted 73system.physmem.readBursts 216517 # Number of DRAM read bursts, including those serviced by the write queue 74system.physmem.writeBursts 187602 # Number of DRAM write bursts, including those merged in the write queue 75system.physmem.bytesReadDRAM 13846784 # Total number of bytes read from DRAM 76system.physmem.bytesReadWrQ 10304 # Total number of bytes read from write queue 77system.physmem.bytesWritten 11642944 # Total number of bytes written to DRAM 78system.physmem.bytesReadSys 13821980 # Total read bytes from the system interface side 79system.physmem.bytesWrittenSys 11740368 # Total written bytes from the system interface side 80system.physmem.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue 81system.physmem.mergedWrBursts 5664 # Number of DRAM write bursts merged with an existing one 82system.physmem.neitherReadNorWriteReqs 13644 # Number of requests that are neither read nor write 83system.physmem.perBankRdBursts::0 13513 # Per bank write bursts 84system.physmem.perBankRdBursts::1 13311 # Per bank write bursts 85system.physmem.perBankRdBursts::2 14548 # Per bank write bursts 86system.physmem.perBankRdBursts::3 14027 # Per bank write bursts 87system.physmem.perBankRdBursts::4 15548 # Per bank write bursts 88system.physmem.perBankRdBursts::5 13123 # Per bank write bursts 89system.physmem.perBankRdBursts::6 13508 # Per bank write bursts 90system.physmem.perBankRdBursts::7 14039 # Per bank write bursts 91system.physmem.perBankRdBursts::8 13183 # Per bank write bursts 92system.physmem.perBankRdBursts::9 13181 # Per bank write bursts 93system.physmem.perBankRdBursts::10 13142 # Per bank write bursts 94system.physmem.perBankRdBursts::11 11743 # Per bank write bursts 95system.physmem.perBankRdBursts::12 13238 # Per bank write bursts 96system.physmem.perBankRdBursts::13 14181 # Per bank write bursts 97system.physmem.perBankRdBursts::14 13272 # Per bank write bursts 98system.physmem.perBankRdBursts::15 12799 # Per bank write bursts 99system.physmem.perBankWrBursts::0 11429 # Per bank write bursts 100system.physmem.perBankWrBursts::1 11725 # Per bank write bursts 101system.physmem.perBankWrBursts::2 12190 # Per bank write bursts 102system.physmem.perBankWrBursts::3 11854 # Per bank write bursts 103system.physmem.perBankWrBursts::4 10909 # Per bank write bursts 104system.physmem.perBankWrBursts::5 11199 # Per bank write bursts 105system.physmem.perBankWrBursts::6 11528 # Per bank write bursts 106system.physmem.perBankWrBursts::7 11643 # Per bank write bursts 107system.physmem.perBankWrBursts::8 11026 # Per bank write bursts 108system.physmem.perBankWrBursts::9 11436 # Per bank write bursts 109system.physmem.perBankWrBursts::10 11468 # Per bank write bursts 110system.physmem.perBankWrBursts::11 11022 # Per bank write bursts 111system.physmem.perBankWrBursts::12 11525 # Per bank write bursts 112system.physmem.perBankWrBursts::13 11398 # Per bank write bursts 113system.physmem.perBankWrBursts::14 10974 # Per bank write bursts 114system.physmem.perBankWrBursts::15 10595 # Per bank write bursts | 60system.physmem.bw_write::total 3160782 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_total::writebacks 3154547 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.dtb.walker 3643 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.inst 1062998 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.l2cache.prefetcher 3068504 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.dtb.walker 270 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.inst 272074 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu1.l2cache.prefetcher 140533 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::total 7702929 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.readReqs 202521 # Number of read requests accepted 72system.physmem.writeReqs 180931 # Number of write requests accepted 73system.physmem.readBursts 202521 # Number of DRAM read bursts, including those serviced by the write queue 74system.physmem.writeBursts 180931 # Number of DRAM write bursts, including those merged in the write queue 75system.physmem.bytesReadDRAM 12951936 # Total number of bytes read from DRAM 76system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue 77system.physmem.bytesWritten 11206784 # Total number of bytes written to DRAM 78system.physmem.bytesReadSys 12926236 # Total read bytes from the system interface side 79system.physmem.bytesWrittenSys 11313424 # Total written bytes from the system interface side 80system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue 81system.physmem.mergedWrBursts 5797 # Number of DRAM write bursts merged with an existing one 82system.physmem.neitherReadNorWriteReqs 13571 # Number of requests that are neither read nor write 83system.physmem.perBankRdBursts::0 12806 # Per bank write bursts 84system.physmem.perBankRdBursts::1 12696 # Per bank write bursts 85system.physmem.perBankRdBursts::2 13455 # Per bank write bursts 86system.physmem.perBankRdBursts::3 13223 # Per bank write bursts 87system.physmem.perBankRdBursts::4 15141 # Per bank write bursts 88system.physmem.perBankRdBursts::5 12251 # Per bank write bursts 89system.physmem.perBankRdBursts::6 12720 # Per bank write bursts 90system.physmem.perBankRdBursts::7 12666 # Per bank write bursts 91system.physmem.perBankRdBursts::8 12396 # Per bank write bursts 92system.physmem.perBankRdBursts::9 12410 # Per bank write bursts 93system.physmem.perBankRdBursts::10 12030 # Per bank write bursts 94system.physmem.perBankRdBursts::11 11077 # Per bank write bursts 95system.physmem.perBankRdBursts::12 12224 # Per bank write bursts 96system.physmem.perBankRdBursts::13 12978 # Per bank write bursts 97system.physmem.perBankRdBursts::14 12239 # Per bank write bursts 98system.physmem.perBankRdBursts::15 12062 # Per bank write bursts 99system.physmem.perBankWrBursts::0 11243 # Per bank write bursts 100system.physmem.perBankWrBursts::1 11520 # Per bank write bursts 101system.physmem.perBankWrBursts::2 11868 # Per bank write bursts 102system.physmem.perBankWrBursts::3 11342 # Per bank write bursts 103system.physmem.perBankWrBursts::4 10753 # Per bank write bursts 104system.physmem.perBankWrBursts::5 10659 # Per bank write bursts 105system.physmem.perBankWrBursts::6 11197 # Per bank write bursts 106system.physmem.perBankWrBursts::7 10854 # Per bank write bursts 107system.physmem.perBankWrBursts::8 10720 # Per bank write bursts 108system.physmem.perBankWrBursts::9 10780 # Per bank write bursts 109system.physmem.perBankWrBursts::10 10917 # Per bank write bursts 110system.physmem.perBankWrBursts::11 10553 # Per bank write bursts 111system.physmem.perBankWrBursts::12 10892 # Per bank write bursts 112system.physmem.perBankWrBursts::13 10850 # Per bank write bursts 113system.physmem.perBankWrBursts::14 10512 # Per bank write bursts 114system.physmem.perBankWrBursts::15 10446 # Per bank write bursts |
| 115system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 115system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 116system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 117system.physmem.totGap 2844424796500 # Total gap between requests | 116system.physmem.numWrRetry 2 # Number of times write queue was full causing retry 117system.physmem.totGap 2845842079500 # Total gap between requests |
| 118system.physmem.readPktSize::0 0 # Read request sizes (log2) 119system.physmem.readPktSize::1 0 # Read request sizes (log2) 120system.physmem.readPktSize::2 559 # Read request sizes (log2) 121system.physmem.readPktSize::3 28 # Read request sizes (log2) 122system.physmem.readPktSize::4 0 # Read request sizes (log2) 123system.physmem.readPktSize::5 0 # Read request sizes (log2) | 118system.physmem.readPktSize::0 0 # Read request sizes (log2) 119system.physmem.readPktSize::1 0 # Read request sizes (log2) 120system.physmem.readPktSize::2 559 # Read request sizes (log2) 121system.physmem.readPktSize::3 28 # Read request sizes (log2) 122system.physmem.readPktSize::4 0 # Read request sizes (log2) 123system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 124system.physmem.readPktSize::6 215930 # Read request sizes (log2) | 124system.physmem.readPktSize::6 201934 # Read request sizes (log2) |
| 125system.physmem.writePktSize::0 0 # Write request sizes (log2) 126system.physmem.writePktSize::1 0 # Write request sizes (log2) 127system.physmem.writePktSize::2 4436 # Write request sizes (log2) 128system.physmem.writePktSize::3 0 # Write request sizes (log2) 129system.physmem.writePktSize::4 0 # Write request sizes (log2) 130system.physmem.writePktSize::5 0 # Write request sizes (log2) | 125system.physmem.writePktSize::0 0 # Write request sizes (log2) 126system.physmem.writePktSize::1 0 # Write request sizes (log2) 127system.physmem.writePktSize::2 4436 # Write request sizes (log2) 128system.physmem.writePktSize::3 0 # Write request sizes (log2) 129system.physmem.writePktSize::4 0 # Write request sizes (log2) 130system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 131system.physmem.writePktSize::6 183166 # Write request sizes (log2) 132system.physmem.rdQLenPdf::0 79055 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::1 63481 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::2 16932 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::3 12216 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::4 10702 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::5 9369 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::6 8301 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::7 7427 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::8 6415 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::9 1133 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::10 442 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::11 303 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::12 206 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::13 155 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::15 92 # What read queue length does an incoming req see | 131system.physmem.writePktSize::6 176495 # Write request sizes (log2) 132system.physmem.rdQLenPdf::0 98520 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::1 50579 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::2 12267 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::3 9843 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::4 8294 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::5 6337 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::6 5553 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::7 4965 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::8 4352 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::9 735 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::10 300 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::11 250 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::12 218 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::13 156 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see |
| 148system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see | 148system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see |
| 149system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see | 149system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see |
| 150system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see --- 13 unchanged lines hidden (view full) --- 171system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 150system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see --- 13 unchanged lines hidden (view full) --- 171system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 179system.physmem.wrQLenPdf::15 3120 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::16 4786 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::17 5952 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::18 7602 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::19 8745 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::20 10117 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::21 11015 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::22 12070 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::23 12267 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::24 13080 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::25 12741 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::26 12428 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::27 11920 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::28 12228 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::29 10042 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::30 9631 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::31 9531 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::32 8901 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::33 927 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::34 714 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::35 577 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::36 448 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::37 387 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::38 326 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::39 266 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::40 238 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::41 206 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::42 189 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::43 184 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::44 159 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::48 125 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::49 132 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::53 48 # What write queue length does an incoming req see | 179system.physmem.wrQLenPdf::15 2878 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::16 4586 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::17 6172 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::18 7768 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::19 8767 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::20 10076 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::21 10729 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::22 11682 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::23 11838 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::24 12804 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::25 12238 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::26 12014 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::27 11495 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::28 11369 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::29 9447 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::30 9041 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::31 8809 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::32 8307 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::33 693 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::34 570 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::35 469 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::36 381 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::37 332 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::38 285 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::39 233 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::40 218 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::41 204 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::42 186 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::43 200 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::44 181 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::45 147 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::46 135 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::49 128 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::50 115 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see |
| 218system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see | 218system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see |
| 219system.physmem.wrQLenPdf::55 21 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see | 219system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see |
| 221system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see | 221system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see |
| 223system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::60 7 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see | 223system.physmem.wrQLenPdf::59 8 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::60 5 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see |
| 226system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see | 226system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see |
| 227system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see 228system.physmem.bytesPerActivate::samples 93322 # Bytes accessed per row activation 229system.physmem.bytesPerActivate::mean 273.137395 # Bytes accessed per row activation 230system.physmem.bytesPerActivate::gmean 151.655882 # Bytes accessed per row activation 231system.physmem.bytesPerActivate::stdev 326.256113 # Bytes accessed per row activation 232system.physmem.bytesPerActivate::0-127 45588 48.85% 48.85% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::128-255 18736 20.08% 68.93% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::256-383 6915 7.41% 76.34% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::384-511 3558 3.81% 80.15% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::512-639 3108 3.33% 83.48% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::640-767 2062 2.21% 85.69% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::768-895 1352 1.45% 87.14% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::896-1023 1057 1.13% 88.27% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::1024-1151 10946 11.73% 100.00% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::total 93322 # Bytes accessed per row activation 242system.physmem.rdPerTurnAround::samples 7762 # Reads before turning the bus around for writes 243system.physmem.rdPerTurnAround::mean 27.873744 # Reads before turning the bus around for writes 244system.physmem.rdPerTurnAround::stdev 521.384620 # Reads before turning the bus around for writes 245system.physmem.rdPerTurnAround::0-2047 7761 99.99% 99.99% # Reads before turning the bus around for writes 246system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 247system.physmem.rdPerTurnAround::total 7762 # Reads before turning the bus around for writes 248system.physmem.wrPerTurnAround::samples 7762 # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::mean 23.437387 # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::gmean 19.920909 # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::stdev 21.626862 # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::16-19 6141 79.12% 79.12% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::20-23 490 6.31% 85.43% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::24-27 77 0.99% 86.42% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::28-31 208 2.68% 89.10% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::32-35 144 1.86% 90.96% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::36-39 54 0.70% 91.65% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::40-43 53 0.68% 92.33% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::44-47 34 0.44% 92.77% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::48-51 115 1.48% 94.25% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::52-55 15 0.19% 94.45% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::56-59 16 0.21% 94.65% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::60-63 14 0.18% 94.83% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::64-67 31 0.40% 95.23% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::68-71 17 0.22% 95.45% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::72-75 9 0.12% 95.57% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::76-79 24 0.31% 95.88% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::80-83 61 0.79% 96.66% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::84-87 9 0.12% 96.78% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::88-91 4 0.05% 96.83% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::92-95 7 0.09% 96.92% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::96-99 74 0.95% 97.87% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::100-103 2 0.03% 97.90% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::104-107 12 0.15% 98.05% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::108-111 8 0.10% 98.16% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::112-115 21 0.27% 98.43% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::116-119 7 0.09% 98.52% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::120-123 12 0.15% 98.67% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::124-127 7 0.09% 98.76% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::128-131 28 0.36% 99.12% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::132-135 9 0.12% 99.24% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::136-139 3 0.04% 99.28% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::140-143 2 0.03% 99.30% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::144-147 9 0.12% 99.42% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::148-151 8 0.10% 99.52% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::152-155 1 0.01% 99.54% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::156-159 3 0.04% 99.57% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::160-163 7 0.09% 99.67% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::164-167 3 0.04% 99.70% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::168-171 1 0.01% 99.72% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::176-179 5 0.06% 99.78% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::180-183 3 0.04% 99.82% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::184-187 3 0.04% 99.86% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::188-191 3 0.04% 99.90% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::200-203 1 0.01% 99.91% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::208-211 2 0.03% 99.94% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::220-223 3 0.04% 99.97% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::224-227 1 0.01% 99.99% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::240-243 1 0.01% 100.00% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::total 7762 # Writes before turning the bus around for reads 301system.physmem.totQLat 7644398000 # Total ticks spent queuing 302system.physmem.totMemAccLat 11701073000 # Total ticks spent from burst creation until serviced by the DRAM 303system.physmem.totBusLat 1081780000 # Total ticks spent in databus transfers 304system.physmem.avgQLat 35332.50 # Average queueing delay per DRAM burst | 227system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see 228system.physmem.bytesPerActivate::samples 94139 # Bytes accessed per row activation 229system.physmem.bytesPerActivate::mean 256.627498 # Bytes accessed per row activation 230system.physmem.bytesPerActivate::gmean 142.457232 # Bytes accessed per row activation 231system.physmem.bytesPerActivate::stdev 317.924062 # Bytes accessed per row activation 232system.physmem.bytesPerActivate::0-127 48795 51.83% 51.83% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::128-255 18347 19.49% 71.32% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::256-383 6488 6.89% 78.21% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::384-511 3770 4.00% 82.22% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::512-639 2738 2.91% 85.13% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::640-767 1619 1.72% 86.85% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::768-895 964 1.02% 87.87% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::896-1023 1076 1.14% 89.01% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::1024-1151 10342 10.99% 100.00% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::total 94139 # Bytes accessed per row activation 242system.physmem.rdPerTurnAround::samples 7479 # Reads before turning the bus around for writes 243system.physmem.rdPerTurnAround::mean 27.058430 # Reads before turning the bus around for writes 244system.physmem.rdPerTurnAround::stdev 520.327968 # Reads before turning the bus around for writes 245system.physmem.rdPerTurnAround::0-2047 7478 99.99% 99.99% # Reads before turning the bus around for writes 246system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes 247system.physmem.rdPerTurnAround::total 7479 # Reads before turning the bus around for writes 248system.physmem.wrPerTurnAround::samples 7479 # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::mean 23.413023 # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::gmean 19.870843 # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::stdev 21.578889 # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::16-23 6390 85.44% 85.44% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::24-31 248 3.32% 88.76% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::32-39 198 2.65% 91.40% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::40-47 77 1.03% 92.43% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::48-55 144 1.93% 94.36% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::56-63 30 0.40% 94.76% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::64-71 35 0.47% 95.23% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::72-79 33 0.44% 95.67% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::80-87 72 0.96% 96.63% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::88-95 21 0.28% 96.91% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::96-103 96 1.28% 98.19% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::104-111 18 0.24% 98.44% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::112-119 22 0.29% 98.73% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::120-127 12 0.16% 98.89% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::128-135 35 0.47% 99.36% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::136-143 4 0.05% 99.41% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::144-151 12 0.16% 99.57% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::152-159 4 0.05% 99.63% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::160-167 8 0.11% 99.73% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::168-175 2 0.03% 99.76% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::176-183 4 0.05% 99.81% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::184-191 3 0.04% 99.85% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::200-207 2 0.03% 99.88% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::208-215 2 0.03% 99.91% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::216-223 2 0.03% 99.93% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::224-231 1 0.01% 99.95% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::232-239 1 0.01% 99.96% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::248-255 2 0.03% 99.99% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::264-271 1 0.01% 100.00% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::total 7479 # Writes before turning the bus around for reads 282system.physmem.totQLat 5783977250 # Total ticks spent queuing 283system.physmem.totMemAccLat 9578489750 # Total ticks spent from burst creation until serviced by the DRAM 284system.physmem.totBusLat 1011870000 # Total ticks spent in databus transfers 285system.physmem.avgQLat 28580.63 # Average queueing delay per DRAM burst |
| 305system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 286system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 306system.physmem.avgMemAccLat 54082.50 # Average memory access latency per DRAM burst 307system.physmem.avgRdBW 4.87 # Average DRAM read bandwidth in MiByte/s 308system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MiByte/s 309system.physmem.avgRdBWSys 4.86 # Average system read bandwidth in MiByte/s 310system.physmem.avgWrBWSys 4.13 # Average system write bandwidth in MiByte/s | 287system.physmem.avgMemAccLat 47330.63 # Average memory access latency per DRAM burst 288system.physmem.avgRdBW 4.55 # Average DRAM read bandwidth in MiByte/s 289system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MiByte/s 290system.physmem.avgRdBWSys 4.54 # Average system read bandwidth in MiByte/s 291system.physmem.avgWrBWSys 3.98 # Average system write bandwidth in MiByte/s |
| 311system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 312system.physmem.busUtil 0.07 # Data bus utilization in percentage 313system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 314system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 292system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 293system.physmem.busUtil 0.07 # Data bus utilization in percentage 294system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 295system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| 315system.physmem.avgRdQLen 1.94 # Average read queue length when enqueuing 316system.physmem.avgWrQLen 21.48 # Average write queue length when enqueuing 317system.physmem.readRowHits 183280 # Number of row buffer hits during reads 318system.physmem.writeRowHits 121675 # Number of row buffer hits during writes 319system.physmem.readRowHitRate 84.71 # Row buffer hit rate for reads 320system.physmem.writeRowHitRate 66.88 # Row buffer hit rate for writes 321system.physmem.avgGap 7038582.19 # Average gap between requests 322system.physmem.pageHitRate 76.57 # Row buffer hit rate, read and write combined 323system.physmem.memoryStateTime::IDLE 2710525028500 # Time in different power states 324system.physmem.memoryStateTime::REF 94981640000 # Time in different power states 325system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 326system.physmem.memoryStateTime::ACT 38919724000 # Time in different power states 327system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 328system.physmem.actEnergy::0 365533560 # Energy for activate commands per rank (pJ) 329system.physmem.actEnergy::1 339980760 # Energy for activate commands per rank (pJ) 330system.physmem.preEnergy::0 199447875 # Energy for precharge commands per rank (pJ) 331system.physmem.preEnergy::1 185505375 # Energy for precharge commands per rank (pJ) 332system.physmem.readEnergy::0 870612600 # Energy for read commands per rank (pJ) 333system.physmem.readEnergy::1 816964200 # Energy for read commands per rank (pJ) 334system.physmem.writeEnergy::0 599250960 # Energy for write commands per rank (pJ) 335system.physmem.writeEnergy::1 579597120 # Energy for write commands per rank (pJ) 336system.physmem.refreshEnergy::0 185784087840 # Energy for refresh commands per rank (pJ) 337system.physmem.refreshEnergy::1 185784087840 # Energy for refresh commands per rank (pJ) 338system.physmem.actBackEnergy::0 82151193285 # Energy for active background per rank (pJ) 339system.physmem.actBackEnergy::1 81119552850 # Energy for active background per rank (pJ) 340system.physmem.preBackEnergy::0 1634593377000 # Energy for precharge background per rank (pJ) 341system.physmem.preBackEnergy::1 1635498324750 # Energy for precharge background per rank (pJ) 342system.physmem.totalEnergy::0 1904563503120 # Total energy per rank (pJ) 343system.physmem.totalEnergy::1 1904324012895 # Total energy per rank (pJ) 344system.physmem.averagePower::0 669.577359 # Core power per rank (mW) 345system.physmem.averagePower::1 669.493163 # Core power per rank (mW) | 296system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing 297system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing 298system.physmem.readRowHits 168404 # Number of row buffer hits during reads 299system.physmem.writeRowHits 114936 # Number of row buffer hits during writes 300system.physmem.readRowHitRate 83.21 # Row buffer hit rate for reads 301system.physmem.writeRowHitRate 65.63 # Row buffer hit rate for writes 302system.physmem.avgGap 7421638.38 # Average gap between requests 303system.physmem.pageHitRate 75.06 # Row buffer hit rate, read and write combined 304system.physmem_0.actEnergy 372813840 # Energy for activate commands per rank (pJ) 305system.physmem_0.preEnergy 203420250 # Energy for precharge commands per rank (pJ) 306system.physmem_0.readEnergy 818672400 # Energy for read commands per rank (pJ) 307system.physmem_0.writeEnergy 579545280 # Energy for write commands per rank (pJ) 308system.physmem_0.refreshEnergy 185876137200 # Energy for refresh commands per rank (pJ) 309system.physmem_0.actBackEnergy 83421293220 # Energy for active background per rank (pJ) 310system.physmem_0.preBackEnergy 1634324841000 # Energy for precharge background per rank (pJ) 311system.physmem_0.totalEnergy 1905596723190 # Total energy per rank (pJ) 312system.physmem_0.averagePower 669.608836 # Core power per rank (mW) 313system.physmem_0.memoryStateTime::IDLE 2718714861000 # Time in different power states 314system.physmem_0.memoryStateTime::REF 95028700000 # Time in different power states 315system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 316system.physmem_0.memoryStateTime::ACT 32092142750 # Time in different power states 317system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 318system.physmem_1.actEnergy 338877000 # Energy for activate commands per rank (pJ) 319system.physmem_1.preEnergy 184903125 # Energy for precharge commands per rank (pJ) 320system.physmem_1.readEnergy 759837000 # Energy for read commands per rank (pJ) 321system.physmem_1.writeEnergy 555141600 # Energy for write commands per rank (pJ) 322system.physmem_1.refreshEnergy 185876137200 # Energy for refresh commands per rank (pJ) 323system.physmem_1.actBackEnergy 82372109895 # Energy for active background per rank (pJ) 324system.physmem_1.preBackEnergy 1635245177250 # Energy for precharge background per rank (pJ) 325system.physmem_1.totalEnergy 1905332183070 # Total energy per rank (pJ) 326system.physmem_1.averagePower 669.515879 # Core power per rank (mW) 327system.physmem_1.memoryStateTime::IDLE 2720254769500 # Time in different power states 328system.physmem_1.memoryStateTime::REF 95028700000 # Time in different power states 329system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 330system.physmem_1.memoryStateTime::ACT 30559102000 # Time in different power states 331system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 346system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory 347system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory 348system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory 349system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory 350system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory 351system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory 352system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory 353system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 354system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory | 332system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory 333system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory 334system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory 335system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory 336system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory 337system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory 338system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory 339system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 340system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory |
| 355system.realview.nvmem.bw_read::cpu0.inst 158 # Total read bandwidth from this memory (bytes/s) | 341system.realview.nvmem.bw_read::cpu0.inst 157 # Total read bandwidth from this memory (bytes/s) |
| 356system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s) | 342system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s) |
| 357system.realview.nvmem.bw_read::total 428 # Total read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_inst_read::cpu0.inst 158 # Instruction read bandwidth from this memory (bytes/s) | 343system.realview.nvmem.bw_read::total 427 # Total read bandwidth from this memory (bytes/s) 344system.realview.nvmem.bw_inst_read::cpu0.inst 157 # Instruction read bandwidth from this memory (bytes/s) |
| 359system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s) | 345system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s) |
| 360system.realview.nvmem.bw_inst_read::total 428 # Instruction read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_total::cpu0.inst 158 # Total bandwidth to/from this memory (bytes/s) | 346system.realview.nvmem.bw_inst_read::total 427 # Instruction read bandwidth from this memory (bytes/s) 347system.realview.nvmem.bw_total::cpu0.inst 157 # Total bandwidth to/from this memory (bytes/s) |
| 362system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) | 348system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) |
| 363system.realview.nvmem.bw_total::total 428 # Total bandwidth to/from this memory (bytes/s) | 349system.realview.nvmem.bw_total::total 427 # Total bandwidth to/from this memory (bytes/s) |
| 364system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 365system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 366system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 367system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 368system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 369system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 350system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 351system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 352system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 353system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 354system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 355system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 370system.cpu0.branchPred.lookups 35736686 # Number of BP lookups 371system.cpu0.branchPred.condPredicted 17706973 # Number of conditional branches predicted 372system.cpu0.branchPred.condIncorrect 1707657 # Number of conditional branches incorrect 373system.cpu0.branchPred.BTBLookups 20554340 # Number of BTB lookups 374system.cpu0.branchPred.BTBHits 14845557 # Number of BTB hits | 356system.cpu0.branchPred.lookups 35059389 # Number of BP lookups 357system.cpu0.branchPred.condPredicted 17250705 # Number of conditional branches predicted 358system.cpu0.branchPred.condIncorrect 1579435 # Number of conditional branches incorrect 359system.cpu0.branchPred.BTBLookups 20094508 # Number of BTB lookups 360system.cpu0.branchPred.BTBHits 14609065 # Number of BTB hits |
| 375system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 361system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 376system.cpu0.branchPred.BTBHitPct 72.225900 # BTB Hit Percentage 377system.cpu0.branchPred.usedRAS 10924417 # Number of times the RAS was used to get a target. 378system.cpu0.branchPred.RASInCorrect 815226 # Number of incorrect RAS predictions. | 362system.cpu0.branchPred.BTBHitPct 72.701780 # BTB Hit Percentage 363system.cpu0.branchPred.usedRAS 10810171 # Number of times the RAS was used to get a target. 364system.cpu0.branchPred.RASInCorrect 733013 # Number of incorrect RAS predictions. |
| 379system.cpu_clk_domain.clock 500 # Clock period in ticks | 365system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 366system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 367system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 368system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 369system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 370system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 371system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 372system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 373system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 380system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 381system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 382system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 383system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 384system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 385system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 386system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 387system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 393system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 394system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 395system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 396system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 397system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 398system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 399system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 400system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 374system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 375system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 376system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 377system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 378system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 379system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 380system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 381system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 387system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 388system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 389system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 390system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 391system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 392system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 393system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 394system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 395system.cpu0.dtb.walker.walks 67889 # Table walker walks requested 396system.cpu0.dtb.walker.walksShort 67889 # Table walker walks initiated with short descriptors 397system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44852 # Level at which table walker walks with short descriptors terminate 398system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23037 # Level at which table walker walks with short descriptors terminate 399system.cpu0.dtb.walker.walkWaitTime::samples 67889 # Table walker wait (enqueue to first request) latency 400system.cpu0.dtb.walker.walkWaitTime::0 67889 100.00% 100.00% # Table walker wait (enqueue to first request) latency 401system.cpu0.dtb.walker.walkWaitTime::total 67889 # Table walker wait (enqueue to first request) latency 402system.cpu0.dtb.walker.walkCompletionTime::samples 6673 # Table walker service (enqueue to completion) latency 403system.cpu0.dtb.walker.walkCompletionTime::mean 8598.195564 # Table walker service (enqueue to completion) latency 404system.cpu0.dtb.walker.walkCompletionTime::gmean 7320.525431 # Table walker service (enqueue to completion) latency 405system.cpu0.dtb.walker.walkCompletionTime::stdev 6106.619536 # Table walker service (enqueue to completion) latency 406system.cpu0.dtb.walker.walkCompletionTime::0-16383 6491 97.27% 97.27% # Table walker service (enqueue to completion) latency 407system.cpu0.dtb.walker.walkCompletionTime::16384-32767 168 2.52% 99.79% # Table walker service (enqueue to completion) latency 408system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.88% # Table walker service (enqueue to completion) latency 409system.cpu0.dtb.walker.walkCompletionTime::81920-98303 6 0.09% 99.97% # Table walker service (enqueue to completion) latency 410system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 411system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 412system.cpu0.dtb.walker.walkCompletionTime::total 6673 # Table walker service (enqueue to completion) latency 413system.cpu0.dtb.walker.walksPending::samples 287368000 # Table walker pending requests distribution 414system.cpu0.dtb.walker.walksPending::0 287368000 100.00% 100.00% # Table walker pending requests distribution 415system.cpu0.dtb.walker.walksPending::total 287368000 # Table walker pending requests distribution 416system.cpu0.dtb.walker.walkPageSizes::4K 5164 77.39% 77.39% # Table walker page sizes translated 417system.cpu0.dtb.walker.walkPageSizes::1M 1509 22.61% 100.00% # Table walker page sizes translated 418system.cpu0.dtb.walker.walkPageSizes::total 6673 # Table walker page sizes translated 419system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67889 # Table walker requests started/completed, data/inst 420system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 421system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67889 # Table walker requests started/completed, data/inst 422system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6673 # Table walker requests started/completed, data/inst 423system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 424system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6673 # Table walker requests started/completed, data/inst 425system.cpu0.dtb.walker.walkRequestOrigin::total 74562 # Table walker requests started/completed, data/inst |
|
| 401system.cpu0.dtb.inst_hits 0 # ITB inst hits 402system.cpu0.dtb.inst_misses 0 # ITB inst misses | 426system.cpu0.dtb.inst_hits 0 # ITB inst hits 427system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 403system.cpu0.dtb.read_hits 24607000 # DTB read hits 404system.cpu0.dtb.read_misses 66402 # DTB read misses 405system.cpu0.dtb.write_hits 18455953 # DTB write hits 406system.cpu0.dtb.write_misses 6655 # DTB write misses | 428system.cpu0.dtb.read_hits 23969568 # DTB read hits 429system.cpu0.dtb.read_misses 61820 # DTB read misses 430system.cpu0.dtb.write_hits 17946825 # DTB write hits 431system.cpu0.dtb.write_misses 6069 # DTB write misses |
| 407system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 408system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 409system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 410system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 432system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 433system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 434system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 435system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 411system.cpu0.dtb.flush_entries 3808 # Number of entries that have been flushed from TLB 412system.cpu0.dtb.align_faults 1234 # Number of TLB faults due to alignment restrictions 413system.cpu0.dtb.prefetch_faults 2108 # Number of TLB faults due to prefetch | 436system.cpu0.dtb.flush_entries 3496 # Number of entries that have been flushed from TLB 437system.cpu0.dtb.align_faults 1251 # Number of TLB faults due to alignment restrictions 438system.cpu0.dtb.prefetch_faults 2004 # Number of TLB faults due to prefetch |
| 414system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 439system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 415system.cpu0.dtb.perms_faults 615 # Number of TLB faults due to permissions restrictions 416system.cpu0.dtb.read_accesses 24673402 # DTB read accesses 417system.cpu0.dtb.write_accesses 18462608 # DTB write accesses | 440system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions 441system.cpu0.dtb.read_accesses 24031388 # DTB read accesses 442system.cpu0.dtb.write_accesses 17952894 # DTB write accesses |
| 418system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 443system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 419system.cpu0.dtb.hits 43062953 # DTB hits 420system.cpu0.dtb.misses 73057 # DTB misses 421system.cpu0.dtb.accesses 43136010 # DTB accesses | 444system.cpu0.dtb.hits 41916393 # DTB hits 445system.cpu0.dtb.misses 67889 # DTB misses 446system.cpu0.dtb.accesses 41984282 # DTB accesses 447system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 448system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 449system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 450system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 451system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 452system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 453system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 454system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| 422system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 423system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 424system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 425system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 426system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 427system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 428system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 429system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 435system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 436system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 437system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 438system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 439system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 440system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 441system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 442system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 455system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 456system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 457system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 458system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 459system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 460system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 461system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 462system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 468system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 469system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 470system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 471system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 472system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 473system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 474system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 475system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 443system.cpu0.itb.inst_hits 71661808 # ITB inst hits 444system.cpu0.itb.inst_misses 4142 # ITB inst misses | 476system.cpu0.itb.walker.walks 3825 # Table walker walks requested 477system.cpu0.itb.walker.walksShort 3825 # Table walker walks initiated with short descriptors 478system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate 479system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3518 # Level at which table walker walks with short descriptors terminate 480system.cpu0.itb.walker.walkWaitTime::samples 3825 # Table walker wait (enqueue to first request) latency 481system.cpu0.itb.walker.walkWaitTime::0 3825 100.00% 100.00% # Table walker wait (enqueue to first request) latency 482system.cpu0.itb.walker.walkWaitTime::total 3825 # Table walker wait (enqueue to first request) latency 483system.cpu0.itb.walker.walkCompletionTime::samples 2419 # Table walker service (enqueue to completion) latency 484system.cpu0.itb.walker.walkCompletionTime::mean 8874.535345 # Table walker service (enqueue to completion) latency 485system.cpu0.itb.walker.walkCompletionTime::gmean 7628.532351 # Table walker service (enqueue to completion) latency 486system.cpu0.itb.walker.walkCompletionTime::stdev 4888.994435 # Table walker service (enqueue to completion) latency 487system.cpu0.itb.walker.walkCompletionTime::0-8191 1491 61.64% 61.64% # Table walker service (enqueue to completion) latency 488system.cpu0.itb.walker.walkCompletionTime::8192-16383 888 36.71% 98.35% # Table walker service (enqueue to completion) latency 489system.cpu0.itb.walker.walkCompletionTime::16384-24575 4 0.17% 98.51% # Table walker service (enqueue to completion) latency 490system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 99.96% # Table walker service (enqueue to completion) latency 491system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 492system.cpu0.itb.walker.walkCompletionTime::total 2419 # Table walker service (enqueue to completion) latency 493system.cpu0.itb.walker.walksPending::samples 286941000 # Table walker pending requests distribution 494system.cpu0.itb.walker.walksPending::0 286941000 100.00% 100.00% # Table walker pending requests distribution 495system.cpu0.itb.walker.walksPending::total 286941000 # Table walker pending requests distribution 496system.cpu0.itb.walker.walkPageSizes::4K 2119 87.60% 87.60% # Table walker page sizes translated 497system.cpu0.itb.walker.walkPageSizes::1M 300 12.40% 100.00% # Table walker page sizes translated 498system.cpu0.itb.walker.walkPageSizes::total 2419 # Table walker page sizes translated 499system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 500system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3825 # Table walker requests started/completed, data/inst 501system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3825 # Table walker requests started/completed, data/inst 502system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 503system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2419 # Table walker requests started/completed, data/inst 504system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2419 # Table walker requests started/completed, data/inst 505system.cpu0.itb.walker.walkRequestOrigin::total 6244 # Table walker requests started/completed, data/inst 506system.cpu0.itb.inst_hits 70462798 # ITB inst hits 507system.cpu0.itb.inst_misses 3825 # ITB inst misses |
| 445system.cpu0.itb.read_hits 0 # DTB read hits 446system.cpu0.itb.read_misses 0 # DTB read misses 447system.cpu0.itb.write_hits 0 # DTB write hits 448system.cpu0.itb.write_misses 0 # DTB write misses 449system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 450system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 451system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 452system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 508system.cpu0.itb.read_hits 0 # DTB read hits 509system.cpu0.itb.read_misses 0 # DTB read misses 510system.cpu0.itb.write_hits 0 # DTB write hits 511system.cpu0.itb.write_misses 0 # DTB write misses 512system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 513system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 514system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 515system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 453system.cpu0.itb.flush_entries 2456 # Number of entries that have been flushed from TLB | 516system.cpu0.itb.flush_entries 2222 # Number of entries that have been flushed from TLB |
| 454system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 455system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 456system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 517system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 518system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 519system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 457system.cpu0.itb.perms_faults 8241 # Number of TLB faults due to permissions restrictions | 520system.cpu0.itb.perms_faults 7291 # Number of TLB faults due to permissions restrictions |
| 458system.cpu0.itb.read_accesses 0 # DTB read accesses 459system.cpu0.itb.write_accesses 0 # DTB write accesses | 521system.cpu0.itb.read_accesses 0 # DTB read accesses 522system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 460system.cpu0.itb.inst_accesses 71665950 # ITB inst accesses 461system.cpu0.itb.hits 71661808 # DTB hits 462system.cpu0.itb.misses 4142 # DTB misses 463system.cpu0.itb.accesses 71665950 # DTB accesses 464system.cpu0.numCycles 235973632 # number of cpu cycles simulated | 523system.cpu0.itb.inst_accesses 70466623 # ITB inst accesses 524system.cpu0.itb.hits 70462798 # DTB hits 525system.cpu0.itb.misses 3825 # DTB misses 526system.cpu0.itb.accesses 70466623 # DTB accesses 527system.cpu0.numCycles 234985394 # number of cpu cycles simulated |
| 465system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 466system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 528system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 529system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 467system.cpu0.committedInsts 111703770 # Number of instructions committed 468system.cpu0.committedOps 135097839 # Number of ops (including micro ops) committed 469system.cpu0.discardedOps 8562554 # Number of ops (including micro ops) which were discarded before commit 470system.cpu0.numFetchSuspends 1855 # Number of times Execute suspended instruction fetching 471system.cpu0.quiesceCycles 5452894525 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 472system.cpu0.cpi 2.112495 # CPI: cycles per instruction 473system.cpu0.ipc 0.473374 # IPC: instructions per cycle | 530system.cpu0.committedInsts 109265327 # Number of instructions committed 531system.cpu0.committedOps 132114239 # Number of ops (including micro ops) committed 532system.cpu0.discardedOps 8364757 # Number of ops (including micro ops) which were discarded before commit 533system.cpu0.numFetchSuspends 1821 # Number of times Execute suspended instruction fetching 534system.cpu0.quiesceCycles 5456715361 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 535system.cpu0.cpi 2.150594 # CPI: cycles per instruction 536system.cpu0.ipc 0.464988 # IPC: instructions per cycle |
| 474system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 537system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 475system.cpu0.kern.inst.quiesce 1855 # number of quiesce instructions executed 476system.cpu0.tickCycles 199544848 # Number of cycles that the object actually ticked 477system.cpu0.idleCycles 36428784 # Total number of cycles that the object has spent stopped 478system.cpu0.dcache.tags.replacements 751860 # number of replacements 479system.cpu0.dcache.tags.tagsinuse 494.262864 # Cycle average of tags in use 480system.cpu0.dcache.tags.total_refs 41566353 # Total number of references to valid blocks. 481system.cpu0.dcache.tags.sampled_refs 752372 # Sample count of references to valid blocks. 482system.cpu0.dcache.tags.avg_refs 55.247076 # Average number of references to valid blocks. 483system.cpu0.dcache.tags.warmup_cycle 306713000 # Cycle when the warmup percentage was hit. 484system.cpu0.dcache.tags.occ_blocks::cpu0.inst 494.262864 # Average occupied blocks per requestor 485system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.965357 # Average percentage of cache occupancy 486system.cpu0.dcache.tags.occ_percent::total 0.965357 # Average percentage of cache occupancy | 538system.cpu0.kern.inst.quiesce 1824 # number of quiesce instructions executed 539system.cpu0.tickCycles 195318282 # Number of cycles that the object actually ticked 540system.cpu0.idleCycles 39667112 # Total number of cycles that the object has spent stopped 541system.cpu0.dcache.tags.replacements 718541 # number of replacements 542system.cpu0.dcache.tags.tagsinuse 494.305697 # Cycle average of tags in use 543system.cpu0.dcache.tags.total_refs 40476936 # Total number of references to valid blocks. 544system.cpu0.dcache.tags.sampled_refs 719053 # Sample count of references to valid blocks. 545system.cpu0.dcache.tags.avg_refs 56.292006 # Average number of references to valid blocks. 546system.cpu0.dcache.tags.warmup_cycle 306903000 # Cycle when the warmup percentage was hit. 547system.cpu0.dcache.tags.occ_blocks::cpu0.inst 494.305697 # Average occupied blocks per requestor 548system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.965441 # Average percentage of cache occupancy 549system.cpu0.dcache.tags.occ_percent::total 0.965441 # Average percentage of cache occupancy |
| 487system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 550system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 488system.cpu0.dcache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id 489system.cpu0.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id 490system.cpu0.dcache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id | 551system.cpu0.dcache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id 552system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id 553system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id |
| 491system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 554system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 492system.cpu0.dcache.tags.tag_accesses 86104149 # Number of tag accesses 493system.cpu0.dcache.tags.data_accesses 86104149 # Number of data accesses 494system.cpu0.dcache.ReadReq_hits::cpu0.inst 23403701 # number of ReadReq hits 495system.cpu0.dcache.ReadReq_hits::total 23403701 # number of ReadReq hits 496system.cpu0.dcache.WriteReq_hits::cpu0.inst 17336391 # number of WriteReq hits 497system.cpu0.dcache.WriteReq_hits::total 17336391 # number of WriteReq hits 498system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 390425 # number of LoadLockedReq hits 499system.cpu0.dcache.LoadLockedReq_hits::total 390425 # number of LoadLockedReq hits 500system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 371566 # number of StoreCondReq hits 501system.cpu0.dcache.StoreCondReq_hits::total 371566 # number of StoreCondReq hits 502system.cpu0.dcache.demand_hits::cpu0.inst 40740092 # number of demand (read+write) hits 503system.cpu0.dcache.demand_hits::total 40740092 # number of demand (read+write) hits 504system.cpu0.dcache.overall_hits::cpu0.inst 40740092 # number of overall hits 505system.cpu0.dcache.overall_hits::total 40740092 # number of overall hits 506system.cpu0.dcache.ReadReq_misses::cpu0.inst 564897 # number of ReadReq misses 507system.cpu0.dcache.ReadReq_misses::total 564897 # number of ReadReq misses 508system.cpu0.dcache.WriteReq_misses::cpu0.inst 554409 # number of WriteReq misses 509system.cpu0.dcache.WriteReq_misses::total 554409 # number of WriteReq misses 510system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6644 # number of LoadLockedReq misses 511system.cpu0.dcache.LoadLockedReq_misses::total 6644 # number of LoadLockedReq misses 512system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20340 # number of StoreCondReq misses 513system.cpu0.dcache.StoreCondReq_misses::total 20340 # number of StoreCondReq misses 514system.cpu0.dcache.demand_misses::cpu0.inst 1119306 # number of demand (read+write) misses 515system.cpu0.dcache.demand_misses::total 1119306 # number of demand (read+write) misses 516system.cpu0.dcache.overall_misses::cpu0.inst 1119306 # number of overall misses 517system.cpu0.dcache.overall_misses::total 1119306 # number of overall misses 518system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6887885459 # number of ReadReq miss cycles 519system.cpu0.dcache.ReadReq_miss_latency::total 6887885459 # number of ReadReq miss cycles 520system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8219762503 # number of WriteReq miss cycles 521system.cpu0.dcache.WriteReq_miss_latency::total 8219762503 # number of WriteReq miss cycles 522system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 108110000 # number of LoadLockedReq miss cycles 523system.cpu0.dcache.LoadLockedReq_miss_latency::total 108110000 # number of LoadLockedReq miss cycles 524system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 440070983 # number of StoreCondReq miss cycles 525system.cpu0.dcache.StoreCondReq_miss_latency::total 440070983 # number of StoreCondReq miss cycles 526system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 121000 # number of StoreCondFailReq miss cycles 527system.cpu0.dcache.StoreCondFailReq_miss_latency::total 121000 # number of StoreCondFailReq miss cycles 528system.cpu0.dcache.demand_miss_latency::cpu0.inst 15107647962 # number of demand (read+write) miss cycles 529system.cpu0.dcache.demand_miss_latency::total 15107647962 # number of demand (read+write) miss cycles 530system.cpu0.dcache.overall_miss_latency::cpu0.inst 15107647962 # number of overall miss cycles 531system.cpu0.dcache.overall_miss_latency::total 15107647962 # number of overall miss cycles 532system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23968598 # number of ReadReq accesses(hits+misses) 533system.cpu0.dcache.ReadReq_accesses::total 23968598 # number of ReadReq accesses(hits+misses) 534system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17890800 # number of WriteReq accesses(hits+misses) 535system.cpu0.dcache.WriteReq_accesses::total 17890800 # number of WriteReq accesses(hits+misses) 536system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 397069 # number of LoadLockedReq accesses(hits+misses) 537system.cpu0.dcache.LoadLockedReq_accesses::total 397069 # number of LoadLockedReq accesses(hits+misses) 538system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 391906 # number of StoreCondReq accesses(hits+misses) 539system.cpu0.dcache.StoreCondReq_accesses::total 391906 # number of StoreCondReq accesses(hits+misses) 540system.cpu0.dcache.demand_accesses::cpu0.inst 41859398 # number of demand (read+write) accesses 541system.cpu0.dcache.demand_accesses::total 41859398 # number of demand (read+write) accesses 542system.cpu0.dcache.overall_accesses::cpu0.inst 41859398 # number of overall (read+write) accesses 543system.cpu0.dcache.overall_accesses::total 41859398 # number of overall (read+write) accesses 544system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023568 # miss rate for ReadReq accesses 545system.cpu0.dcache.ReadReq_miss_rate::total 0.023568 # miss rate for ReadReq accesses 546system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030988 # miss rate for WriteReq accesses 547system.cpu0.dcache.WriteReq_miss_rate::total 0.030988 # miss rate for WriteReq accesses 548system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016733 # miss rate for LoadLockedReq accesses 549system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016733 # miss rate for LoadLockedReq accesses 550system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.051900 # miss rate for StoreCondReq accesses 551system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051900 # miss rate for StoreCondReq accesses 552system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026740 # miss rate for demand accesses 553system.cpu0.dcache.demand_miss_rate::total 0.026740 # miss rate for demand accesses 554system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026740 # miss rate for overall accesses 555system.cpu0.dcache.overall_miss_rate::total 0.026740 # miss rate for overall accesses 556system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12193.170541 # average ReadReq miss latency 557system.cpu0.dcache.ReadReq_avg_miss_latency::total 12193.170541 # average ReadReq miss latency 558system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 14826.170757 # average WriteReq miss latency 559system.cpu0.dcache.WriteReq_avg_miss_latency::total 14826.170757 # average WriteReq miss latency 560system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16271.824202 # average LoadLockedReq miss latency 561system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16271.824202 # average LoadLockedReq miss latency 562system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21635.741544 # average StoreCondReq miss latency 563system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21635.741544 # average StoreCondReq miss latency | 555system.cpu0.dcache.tags.tag_accesses 83802985 # Number of tag accesses 556system.cpu0.dcache.tags.data_accesses 83802985 # Number of data accesses 557system.cpu0.dcache.ReadReq_hits::cpu0.inst 22808347 # number of ReadReq hits 558system.cpu0.dcache.ReadReq_hits::total 22808347 # number of ReadReq hits 559system.cpu0.dcache.WriteReq_hits::cpu0.inst 16863099 # number of WriteReq hits 560system.cpu0.dcache.WriteReq_hits::total 16863099 # number of WriteReq hits 561system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 381264 # number of LoadLockedReq hits 562system.cpu0.dcache.LoadLockedReq_hits::total 381264 # number of LoadLockedReq hits 563system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 362825 # number of StoreCondReq hits 564system.cpu0.dcache.StoreCondReq_hits::total 362825 # number of StoreCondReq hits 565system.cpu0.dcache.demand_hits::cpu0.inst 39671446 # number of demand (read+write) hits 566system.cpu0.dcache.demand_hits::total 39671446 # number of demand (read+write) hits 567system.cpu0.dcache.overall_hits::cpu0.inst 39671446 # number of overall hits 568system.cpu0.dcache.overall_hits::total 39671446 # number of overall hits 569system.cpu0.dcache.ReadReq_misses::cpu0.inst 540080 # number of ReadReq misses 570system.cpu0.dcache.ReadReq_misses::total 540080 # number of ReadReq misses 571system.cpu0.dcache.WriteReq_misses::cpu0.inst 532227 # number of WriteReq misses 572system.cpu0.dcache.WriteReq_misses::total 532227 # number of WriteReq misses 573system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6489 # number of LoadLockedReq misses 574system.cpu0.dcache.LoadLockedReq_misses::total 6489 # number of LoadLockedReq misses 575system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 19898 # number of StoreCondReq misses 576system.cpu0.dcache.StoreCondReq_misses::total 19898 # number of StoreCondReq misses 577system.cpu0.dcache.demand_misses::cpu0.inst 1072307 # number of demand (read+write) misses 578system.cpu0.dcache.demand_misses::total 1072307 # number of demand (read+write) misses 579system.cpu0.dcache.overall_misses::cpu0.inst 1072307 # number of overall misses 580system.cpu0.dcache.overall_misses::total 1072307 # number of overall misses 581system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6648434719 # number of ReadReq miss cycles 582system.cpu0.dcache.ReadReq_miss_latency::total 6648434719 # number of ReadReq miss cycles 583system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8319872197 # number of WriteReq miss cycles 584system.cpu0.dcache.WriteReq_miss_latency::total 8319872197 # number of WriteReq miss cycles 585system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 104923750 # number of LoadLockedReq miss cycles 586system.cpu0.dcache.LoadLockedReq_miss_latency::total 104923750 # number of LoadLockedReq miss cycles 587system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 438142885 # number of StoreCondReq miss cycles 588system.cpu0.dcache.StoreCondReq_miss_latency::total 438142885 # number of StoreCondReq miss cycles 589system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 309000 # number of StoreCondFailReq miss cycles 590system.cpu0.dcache.StoreCondFailReq_miss_latency::total 309000 # number of StoreCondFailReq miss cycles 591system.cpu0.dcache.demand_miss_latency::cpu0.inst 14968306916 # number of demand (read+write) miss cycles 592system.cpu0.dcache.demand_miss_latency::total 14968306916 # number of demand (read+write) miss cycles 593system.cpu0.dcache.overall_miss_latency::cpu0.inst 14968306916 # number of overall miss cycles 594system.cpu0.dcache.overall_miss_latency::total 14968306916 # number of overall miss cycles 595system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23348427 # number of ReadReq accesses(hits+misses) 596system.cpu0.dcache.ReadReq_accesses::total 23348427 # number of ReadReq accesses(hits+misses) 597system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17395326 # number of WriteReq accesses(hits+misses) 598system.cpu0.dcache.WriteReq_accesses::total 17395326 # number of WriteReq accesses(hits+misses) 599system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 387753 # number of LoadLockedReq accesses(hits+misses) 600system.cpu0.dcache.LoadLockedReq_accesses::total 387753 # number of LoadLockedReq accesses(hits+misses) 601system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 382723 # number of StoreCondReq accesses(hits+misses) 602system.cpu0.dcache.StoreCondReq_accesses::total 382723 # number of StoreCondReq accesses(hits+misses) 603system.cpu0.dcache.demand_accesses::cpu0.inst 40743753 # number of demand (read+write) accesses 604system.cpu0.dcache.demand_accesses::total 40743753 # number of demand (read+write) accesses 605system.cpu0.dcache.overall_accesses::cpu0.inst 40743753 # number of overall (read+write) accesses 606system.cpu0.dcache.overall_accesses::total 40743753 # number of overall (read+write) accesses 607system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023131 # miss rate for ReadReq accesses 608system.cpu0.dcache.ReadReq_miss_rate::total 0.023131 # miss rate for ReadReq accesses 609system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030596 # miss rate for WriteReq accesses 610system.cpu0.dcache.WriteReq_miss_rate::total 0.030596 # miss rate for WriteReq accesses 611system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016735 # miss rate for LoadLockedReq accesses 612system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016735 # miss rate for LoadLockedReq accesses 613system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.051991 # miss rate for StoreCondReq accesses 614system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051991 # miss rate for StoreCondReq accesses 615system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026318 # miss rate for demand accesses 616system.cpu0.dcache.demand_miss_rate::total 0.026318 # miss rate for demand accesses 617system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026318 # miss rate for overall accesses 618system.cpu0.dcache.overall_miss_rate::total 0.026318 # miss rate for overall accesses 619system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12310.092429 # average ReadReq miss latency 620system.cpu0.dcache.ReadReq_avg_miss_latency::total 12310.092429 # average ReadReq miss latency 621system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15632.187388 # average WriteReq miss latency 622system.cpu0.dcache.WriteReq_avg_miss_latency::total 15632.187388 # average WriteReq miss latency 623system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16169.479119 # average LoadLockedReq miss latency 624system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16169.479119 # average LoadLockedReq miss latency 625system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 22019.443411 # average StoreCondReq miss latency 626system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22019.443411 # average StoreCondReq miss latency |
| 564system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency 565system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 627system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency 628system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 566system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13497.334922 # average overall miss latency 567system.cpu0.dcache.demand_avg_miss_latency::total 13497.334922 # average overall miss latency 568system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13497.334922 # average overall miss latency 569system.cpu0.dcache.overall_avg_miss_latency::total 13497.334922 # average overall miss latency | 629system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13958.975290 # average overall miss latency 630system.cpu0.dcache.demand_avg_miss_latency::total 13958.975290 # average overall miss latency 631system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13958.975290 # average overall miss latency 632system.cpu0.dcache.overall_avg_miss_latency::total 13958.975290 # average overall miss latency |
| 570system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 571system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 572system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 573system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 574system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 575system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 576system.cpu0.dcache.fast_writes 0 # number of fast writes performed 577system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 633system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 634system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 635system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 636system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 637system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 638system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 639system.cpu0.dcache.fast_writes 0 # number of fast writes performed 640system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 578system.cpu0.dcache.writebacks::writebacks 541643 # number of writebacks 579system.cpu0.dcache.writebacks::total 541643 # number of writebacks 580system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 45094 # number of ReadReq MSHR hits 581system.cpu0.dcache.ReadReq_mshr_hits::total 45094 # number of ReadReq MSHR hits 582system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 240822 # number of WriteReq MSHR hits 583system.cpu0.dcache.WriteReq_mshr_hits::total 240822 # number of WriteReq MSHR hits 584system.cpu0.dcache.demand_mshr_hits::cpu0.inst 285916 # number of demand (read+write) MSHR hits 585system.cpu0.dcache.demand_mshr_hits::total 285916 # number of demand (read+write) MSHR hits 586system.cpu0.dcache.overall_mshr_hits::cpu0.inst 285916 # number of overall MSHR hits 587system.cpu0.dcache.overall_mshr_hits::total 285916 # number of overall MSHR hits 588system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 519803 # number of ReadReq MSHR misses 589system.cpu0.dcache.ReadReq_mshr_misses::total 519803 # number of ReadReq MSHR misses 590system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 313587 # number of WriteReq MSHR misses 591system.cpu0.dcache.WriteReq_mshr_misses::total 313587 # number of WriteReq MSHR misses 592system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6644 # number of LoadLockedReq MSHR misses 593system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6644 # number of LoadLockedReq MSHR misses 594system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 20340 # number of StoreCondReq MSHR misses 595system.cpu0.dcache.StoreCondReq_mshr_misses::total 20340 # number of StoreCondReq MSHR misses 596system.cpu0.dcache.demand_mshr_misses::cpu0.inst 833390 # number of demand (read+write) MSHR misses 597system.cpu0.dcache.demand_mshr_misses::total 833390 # number of demand (read+write) MSHR misses 598system.cpu0.dcache.overall_mshr_misses::cpu0.inst 833390 # number of overall MSHR misses 599system.cpu0.dcache.overall_mshr_misses::total 833390 # number of overall MSHR misses 600system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5323715430 # number of ReadReq MSHR miss cycles 601system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5323715430 # number of ReadReq MSHR miss cycles 602system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4366940170 # number of WriteReq MSHR miss cycles 603system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4366940170 # number of WriteReq MSHR miss cycles 604system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 94806000 # number of LoadLockedReq MSHR miss cycles 605system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94806000 # number of LoadLockedReq MSHR miss cycles 606system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 398879017 # number of StoreCondReq MSHR miss cycles 607system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 398879017 # number of StoreCondReq MSHR miss cycles 608system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 115000 # number of StoreCondFailReq MSHR miss cycles 609system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 115000 # number of StoreCondFailReq MSHR miss cycles 610system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9690655600 # number of demand (read+write) MSHR miss cycles 611system.cpu0.dcache.demand_mshr_miss_latency::total 9690655600 # number of demand (read+write) MSHR miss cycles 612system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9690655600 # number of overall MSHR miss cycles 613system.cpu0.dcache.overall_mshr_miss_latency::total 9690655600 # number of overall MSHR miss cycles 614system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6196262496 # number of ReadReq MSHR uncacheable cycles 615system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6196262496 # number of ReadReq MSHR uncacheable cycles 616system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4811489492 # number of WriteReq MSHR uncacheable cycles 617system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4811489492 # number of WriteReq MSHR uncacheable cycles 618system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 11007751988 # number of overall MSHR uncacheable cycles 619system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11007751988 # number of overall MSHR uncacheable cycles 620system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021687 # mshr miss rate for ReadReq accesses 621system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021687 # mshr miss rate for ReadReq accesses 622system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017528 # mshr miss rate for WriteReq accesses 623system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017528 # mshr miss rate for WriteReq accesses 624system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016733 # mshr miss rate for LoadLockedReq accesses 625system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016733 # mshr miss rate for LoadLockedReq accesses 626system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.051900 # mshr miss rate for StoreCondReq accesses 627system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051900 # mshr miss rate for StoreCondReq accesses 628system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019909 # mshr miss rate for demand accesses 629system.cpu0.dcache.demand_mshr_miss_rate::total 0.019909 # mshr miss rate for demand accesses 630system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019909 # mshr miss rate for overall accesses 631system.cpu0.dcache.overall_mshr_miss_rate::total 0.019909 # mshr miss rate for overall accesses 632system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10241.794353 # average ReadReq mshr miss latency 633system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10241.794353 # average ReadReq mshr miss latency 634system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 13925.769149 # average WriteReq mshr miss latency 635system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13925.769149 # average WriteReq mshr miss latency 636system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14269.416014 # average LoadLockedReq mshr miss latency 637system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14269.416014 # average LoadLockedReq mshr miss latency 638system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19610.571141 # average StoreCondReq mshr miss latency 639system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19610.571141 # average StoreCondReq mshr miss latency | 641system.cpu0.dcache.writebacks::writebacks 523102 # number of writebacks 642system.cpu0.dcache.writebacks::total 523102 # number of writebacks 643system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 42658 # number of ReadReq MSHR hits 644system.cpu0.dcache.ReadReq_mshr_hits::total 42658 # number of ReadReq MSHR hits 645system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 230433 # number of WriteReq MSHR hits 646system.cpu0.dcache.WriteReq_mshr_hits::total 230433 # number of WriteReq MSHR hits 647system.cpu0.dcache.demand_mshr_hits::cpu0.inst 273091 # number of demand (read+write) MSHR hits 648system.cpu0.dcache.demand_mshr_hits::total 273091 # number of demand (read+write) MSHR hits 649system.cpu0.dcache.overall_mshr_hits::cpu0.inst 273091 # number of overall MSHR hits 650system.cpu0.dcache.overall_mshr_hits::total 273091 # number of overall MSHR hits 651system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 497422 # number of ReadReq MSHR misses 652system.cpu0.dcache.ReadReq_mshr_misses::total 497422 # number of ReadReq MSHR misses 653system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 301794 # number of WriteReq MSHR misses 654system.cpu0.dcache.WriteReq_mshr_misses::total 301794 # number of WriteReq MSHR misses 655system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6489 # number of LoadLockedReq MSHR misses 656system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6489 # number of LoadLockedReq MSHR misses 657system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 19898 # number of StoreCondReq MSHR misses 658system.cpu0.dcache.StoreCondReq_mshr_misses::total 19898 # number of StoreCondReq MSHR misses 659system.cpu0.dcache.demand_mshr_misses::cpu0.inst 799216 # number of demand (read+write) MSHR misses 660system.cpu0.dcache.demand_mshr_misses::total 799216 # number of demand (read+write) MSHR misses 661system.cpu0.dcache.overall_mshr_misses::cpu0.inst 799216 # number of overall MSHR misses 662system.cpu0.dcache.overall_mshr_misses::total 799216 # number of overall MSHR misses 663system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5149793898 # number of ReadReq MSHR miss cycles 664system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5149793898 # number of ReadReq MSHR miss cycles 665system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4423706193 # number of WriteReq MSHR miss cycles 666system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4423706193 # number of WriteReq MSHR miss cycles 667system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 91926250 # number of LoadLockedReq MSHR miss cycles 668system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 91926250 # number of LoadLockedReq MSHR miss cycles 669system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 397751115 # number of StoreCondReq MSHR miss cycles 670system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 397751115 # number of StoreCondReq MSHR miss cycles 671system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 291000 # number of StoreCondFailReq MSHR miss cycles 672system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 291000 # number of StoreCondFailReq MSHR miss cycles 673system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9573500091 # number of demand (read+write) MSHR miss cycles 674system.cpu0.dcache.demand_mshr_miss_latency::total 9573500091 # number of demand (read+write) MSHR miss cycles 675system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9573500091 # number of overall MSHR miss cycles 676system.cpu0.dcache.overall_mshr_miss_latency::total 9573500091 # number of overall MSHR miss cycles 677system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6190990749 # number of ReadReq MSHR uncacheable cycles 678system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6190990749 # number of ReadReq MSHR uncacheable cycles 679system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4804555500 # number of WriteReq MSHR uncacheable cycles 680system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4804555500 # number of WriteReq MSHR uncacheable cycles 681system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 10995546249 # number of overall MSHR uncacheable cycles 682system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10995546249 # number of overall MSHR uncacheable cycles 683system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021304 # mshr miss rate for ReadReq accesses 684system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021304 # mshr miss rate for ReadReq accesses 685system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017349 # mshr miss rate for WriteReq accesses 686system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017349 # mshr miss rate for WriteReq accesses 687system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016735 # mshr miss rate for LoadLockedReq accesses 688system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016735 # mshr miss rate for LoadLockedReq accesses 689system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.051991 # mshr miss rate for StoreCondReq accesses 690system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051991 # mshr miss rate for StoreCondReq accesses 691system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019616 # mshr miss rate for demand accesses 692system.cpu0.dcache.demand_mshr_miss_rate::total 0.019616 # mshr miss rate for demand accesses 693system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019616 # mshr miss rate for overall accesses 694system.cpu0.dcache.overall_mshr_miss_rate::total 0.019616 # mshr miss rate for overall accesses 695system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10352.967697 # average ReadReq mshr miss latency 696system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10352.967697 # average ReadReq mshr miss latency 697system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14658.032277 # average WriteReq mshr miss latency 698system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14658.032277 # average WriteReq mshr miss latency 699system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14166.474033 # average LoadLockedReq mshr miss latency 700system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14166.474033 # average LoadLockedReq mshr miss latency 701system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19989.502211 # average StoreCondReq mshr miss latency 702system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19989.502211 # average StoreCondReq mshr miss latency |
| 640system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency 641system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 703system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency 704system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 642system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11627.996016 # average overall mshr miss latency 643system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11627.996016 # average overall mshr miss latency 644system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11627.996016 # average overall mshr miss latency 645system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11627.996016 # average overall mshr miss latency | 705system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11978.614156 # average overall mshr miss latency 706system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11978.614156 # average overall mshr miss latency 707system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11978.614156 # average overall mshr miss latency 708system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11978.614156 # average overall mshr miss latency |
| 646system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 647system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 648system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 649system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 650system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 651system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 652system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 709system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 710system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 711system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 712system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 713system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 714system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 715system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 653system.cpu0.icache.tags.replacements 2070442 # number of replacements 654system.cpu0.icache.tags.tagsinuse 511.797171 # Cycle average of tags in use 655system.cpu0.icache.tags.total_refs 69582233 # Total number of references to valid blocks. 656system.cpu0.icache.tags.sampled_refs 2070954 # Sample count of references to valid blocks. 657system.cpu0.icache.tags.avg_refs 33.599121 # Average number of references to valid blocks. 658system.cpu0.icache.tags.warmup_cycle 6297775000 # Cycle when the warmup percentage was hit. 659system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.797171 # Average occupied blocks per requestor 660system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999604 # Average percentage of cache occupancy 661system.cpu0.icache.tags.occ_percent::total 0.999604 # Average percentage of cache occupancy | 716system.cpu0.icache.tags.replacements 1982441 # number of replacements 717system.cpu0.icache.tags.tagsinuse 511.792915 # Cycle average of tags in use 718system.cpu0.icache.tags.total_refs 68472197 # Total number of references to valid blocks. 719system.cpu0.icache.tags.sampled_refs 1982953 # Sample count of references to valid blocks. 720system.cpu0.icache.tags.avg_refs 34.530419 # Average number of references to valid blocks. 721system.cpu0.icache.tags.warmup_cycle 6378447750 # Cycle when the warmup percentage was hit. 722system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.792915 # Average occupied blocks per requestor 723system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999596 # Average percentage of cache occupancy 724system.cpu0.icache.tags.occ_percent::total 0.999596 # Average percentage of cache occupancy |
| 662system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 725system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 663system.cpu0.icache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id | 726system.cpu0.icache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id |
| 664system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id | 727system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id |
| 665system.cpu0.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id | 728system.cpu0.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id |
| 666system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 729system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 667system.cpu0.icache.tags.tag_accesses 145377375 # Number of tag accesses 668system.cpu0.icache.tags.data_accesses 145377375 # Number of data accesses 669system.cpu0.icache.ReadReq_hits::cpu0.inst 69582233 # number of ReadReq hits 670system.cpu0.icache.ReadReq_hits::total 69582233 # number of ReadReq hits 671system.cpu0.icache.demand_hits::cpu0.inst 69582233 # number of demand (read+write) hits 672system.cpu0.icache.demand_hits::total 69582233 # number of demand (read+write) hits 673system.cpu0.icache.overall_hits::cpu0.inst 69582233 # number of overall hits 674system.cpu0.icache.overall_hits::total 69582233 # number of overall hits 675system.cpu0.icache.ReadReq_misses::cpu0.inst 2070970 # number of ReadReq misses 676system.cpu0.icache.ReadReq_misses::total 2070970 # number of ReadReq misses 677system.cpu0.icache.demand_misses::cpu0.inst 2070970 # number of demand (read+write) misses 678system.cpu0.icache.demand_misses::total 2070970 # number of demand (read+write) misses 679system.cpu0.icache.overall_misses::cpu0.inst 2070970 # number of overall misses 680system.cpu0.icache.overall_misses::total 2070970 # number of overall misses 681system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17258012980 # number of ReadReq miss cycles 682system.cpu0.icache.ReadReq_miss_latency::total 17258012980 # number of ReadReq miss cycles 683system.cpu0.icache.demand_miss_latency::cpu0.inst 17258012980 # number of demand (read+write) miss cycles 684system.cpu0.icache.demand_miss_latency::total 17258012980 # number of demand (read+write) miss cycles 685system.cpu0.icache.overall_miss_latency::cpu0.inst 17258012980 # number of overall miss cycles 686system.cpu0.icache.overall_miss_latency::total 17258012980 # number of overall miss cycles 687system.cpu0.icache.ReadReq_accesses::cpu0.inst 71653203 # number of ReadReq accesses(hits+misses) 688system.cpu0.icache.ReadReq_accesses::total 71653203 # number of ReadReq accesses(hits+misses) 689system.cpu0.icache.demand_accesses::cpu0.inst 71653203 # number of demand (read+write) accesses 690system.cpu0.icache.demand_accesses::total 71653203 # number of demand (read+write) accesses 691system.cpu0.icache.overall_accesses::cpu0.inst 71653203 # number of overall (read+write) accesses 692system.cpu0.icache.overall_accesses::total 71653203 # number of overall (read+write) accesses 693system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028903 # miss rate for ReadReq accesses 694system.cpu0.icache.ReadReq_miss_rate::total 0.028903 # miss rate for ReadReq accesses 695system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028903 # miss rate for demand accesses 696system.cpu0.icache.demand_miss_rate::total 0.028903 # miss rate for demand accesses 697system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028903 # miss rate for overall accesses 698system.cpu0.icache.overall_miss_rate::total 0.028903 # miss rate for overall accesses 699system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8333.299362 # average ReadReq miss latency 700system.cpu0.icache.ReadReq_avg_miss_latency::total 8333.299362 # average ReadReq miss latency 701system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8333.299362 # average overall miss latency 702system.cpu0.icache.demand_avg_miss_latency::total 8333.299362 # average overall miss latency 703system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8333.299362 # average overall miss latency 704system.cpu0.icache.overall_avg_miss_latency::total 8333.299362 # average overall miss latency | 730system.cpu0.icache.tags.tag_accesses 142893294 # Number of tag accesses 731system.cpu0.icache.tags.data_accesses 142893294 # Number of data accesses 732system.cpu0.icache.ReadReq_hits::cpu0.inst 68472197 # number of ReadReq hits 733system.cpu0.icache.ReadReq_hits::total 68472197 # number of ReadReq hits 734system.cpu0.icache.demand_hits::cpu0.inst 68472197 # number of demand (read+write) hits 735system.cpu0.icache.demand_hits::total 68472197 # number of demand (read+write) hits 736system.cpu0.icache.overall_hits::cpu0.inst 68472197 # number of overall hits 737system.cpu0.icache.overall_hits::total 68472197 # number of overall hits 738system.cpu0.icache.ReadReq_misses::cpu0.inst 1982967 # number of ReadReq misses 739system.cpu0.icache.ReadReq_misses::total 1982967 # number of ReadReq misses 740system.cpu0.icache.demand_misses::cpu0.inst 1982967 # number of demand (read+write) misses 741system.cpu0.icache.demand_misses::total 1982967 # number of demand (read+write) misses 742system.cpu0.icache.overall_misses::cpu0.inst 1982967 # number of overall misses 743system.cpu0.icache.overall_misses::total 1982967 # number of overall misses 744system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18641895952 # number of ReadReq miss cycles 745system.cpu0.icache.ReadReq_miss_latency::total 18641895952 # number of ReadReq miss cycles 746system.cpu0.icache.demand_miss_latency::cpu0.inst 18641895952 # number of demand (read+write) miss cycles 747system.cpu0.icache.demand_miss_latency::total 18641895952 # number of demand (read+write) miss cycles 748system.cpu0.icache.overall_miss_latency::cpu0.inst 18641895952 # number of overall miss cycles 749system.cpu0.icache.overall_miss_latency::total 18641895952 # number of overall miss cycles 750system.cpu0.icache.ReadReq_accesses::cpu0.inst 70455164 # number of ReadReq accesses(hits+misses) 751system.cpu0.icache.ReadReq_accesses::total 70455164 # number of ReadReq accesses(hits+misses) 752system.cpu0.icache.demand_accesses::cpu0.inst 70455164 # number of demand (read+write) accesses 753system.cpu0.icache.demand_accesses::total 70455164 # number of demand (read+write) accesses 754system.cpu0.icache.overall_accesses::cpu0.inst 70455164 # number of overall (read+write) accesses 755system.cpu0.icache.overall_accesses::total 70455164 # number of overall (read+write) accesses 756system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028145 # miss rate for ReadReq accesses 757system.cpu0.icache.ReadReq_miss_rate::total 0.028145 # miss rate for ReadReq accesses 758system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028145 # miss rate for demand accesses 759system.cpu0.icache.demand_miss_rate::total 0.028145 # miss rate for demand accesses 760system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028145 # miss rate for overall accesses 761system.cpu0.icache.overall_miss_rate::total 0.028145 # miss rate for overall accesses 762system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9401.011692 # average ReadReq miss latency 763system.cpu0.icache.ReadReq_avg_miss_latency::total 9401.011692 # average ReadReq miss latency 764system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9401.011692 # average overall miss latency 765system.cpu0.icache.demand_avg_miss_latency::total 9401.011692 # average overall miss latency 766system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9401.011692 # average overall miss latency 767system.cpu0.icache.overall_avg_miss_latency::total 9401.011692 # average overall miss latency |
| 705system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 706system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 707system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 708system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 709system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 710system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 711system.cpu0.icache.fast_writes 0 # number of fast writes performed 712system.cpu0.icache.cache_copies 0 # number of cache copies performed | 768system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 769system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 770system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 771system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 772system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 773system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 774system.cpu0.icache.fast_writes 0 # number of fast writes performed 775system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 713system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2070970 # number of ReadReq MSHR misses 714system.cpu0.icache.ReadReq_mshr_misses::total 2070970 # number of ReadReq MSHR misses 715system.cpu0.icache.demand_mshr_misses::cpu0.inst 2070970 # number of demand (read+write) MSHR misses 716system.cpu0.icache.demand_mshr_misses::total 2070970 # number of demand (read+write) MSHR misses 717system.cpu0.icache.overall_mshr_misses::cpu0.inst 2070970 # number of overall MSHR misses 718system.cpu0.icache.overall_mshr_misses::total 2070970 # number of overall MSHR misses 719system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 14149699520 # number of ReadReq MSHR miss cycles 720system.cpu0.icache.ReadReq_mshr_miss_latency::total 14149699520 # number of ReadReq MSHR miss cycles 721system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 14149699520 # number of demand (read+write) MSHR miss cycles 722system.cpu0.icache.demand_mshr_miss_latency::total 14149699520 # number of demand (read+write) MSHR miss cycles 723system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 14149699520 # number of overall MSHR miss cycles 724system.cpu0.icache.overall_mshr_miss_latency::total 14149699520 # number of overall MSHR miss cycles 725system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 276493750 # number of ReadReq MSHR uncacheable cycles 726system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 276493750 # number of ReadReq MSHR uncacheable cycles 727system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 276493750 # number of overall MSHR uncacheable cycles 728system.cpu0.icache.overall_mshr_uncacheable_latency::total 276493750 # number of overall MSHR uncacheable cycles 729system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028903 # mshr miss rate for ReadReq accesses 730system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028903 # mshr miss rate for ReadReq accesses 731system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028903 # mshr miss rate for demand accesses 732system.cpu0.icache.demand_mshr_miss_rate::total 0.028903 # mshr miss rate for demand accesses 733system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028903 # mshr miss rate for overall accesses 734system.cpu0.icache.overall_mshr_miss_rate::total 0.028903 # mshr miss rate for overall accesses 735system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6832.401976 # average ReadReq mshr miss latency 736system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6832.401976 # average ReadReq mshr miss latency 737system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6832.401976 # average overall mshr miss latency 738system.cpu0.icache.demand_avg_mshr_miss_latency::total 6832.401976 # average overall mshr miss latency 739system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6832.401976 # average overall mshr miss latency 740system.cpu0.icache.overall_avg_mshr_miss_latency::total 6832.401976 # average overall mshr miss latency | 776system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1982967 # number of ReadReq MSHR misses 777system.cpu0.icache.ReadReq_mshr_misses::total 1982967 # number of ReadReq MSHR misses 778system.cpu0.icache.demand_mshr_misses::cpu0.inst 1982967 # number of demand (read+write) MSHR misses 779system.cpu0.icache.demand_mshr_misses::total 1982967 # number of demand (read+write) MSHR misses 780system.cpu0.icache.overall_mshr_misses::cpu0.inst 1982967 # number of overall MSHR misses 781system.cpu0.icache.overall_mshr_misses::total 1982967 # number of overall MSHR misses 782system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 15657207046 # number of ReadReq MSHR miss cycles 783system.cpu0.icache.ReadReq_mshr_miss_latency::total 15657207046 # number of ReadReq MSHR miss cycles 784system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 15657207046 # number of demand (read+write) MSHR miss cycles 785system.cpu0.icache.demand_mshr_miss_latency::total 15657207046 # number of demand (read+write) MSHR miss cycles 786system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 15657207046 # number of overall MSHR miss cycles 787system.cpu0.icache.overall_mshr_miss_latency::total 15657207046 # number of overall MSHR miss cycles 788system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 278031000 # number of ReadReq MSHR uncacheable cycles 789system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 278031000 # number of ReadReq MSHR uncacheable cycles 790system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 278031000 # number of overall MSHR uncacheable cycles 791system.cpu0.icache.overall_mshr_uncacheable_latency::total 278031000 # number of overall MSHR uncacheable cycles 792system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028145 # mshr miss rate for ReadReq accesses 793system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028145 # mshr miss rate for ReadReq accesses 794system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028145 # mshr miss rate for demand accesses 795system.cpu0.icache.demand_mshr_miss_rate::total 0.028145 # mshr miss rate for demand accesses 796system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028145 # mshr miss rate for overall accesses 797system.cpu0.icache.overall_mshr_miss_rate::total 0.028145 # mshr miss rate for overall accesses 798system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7895.848517 # average ReadReq mshr miss latency 799system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7895.848517 # average ReadReq mshr miss latency 800system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7895.848517 # average overall mshr miss latency 801system.cpu0.icache.demand_avg_mshr_miss_latency::total 7895.848517 # average overall mshr miss latency 802system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7895.848517 # average overall mshr miss latency 803system.cpu0.icache.overall_avg_mshr_miss_latency::total 7895.848517 # average overall mshr miss latency |
| 741system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 742system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 743system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 744system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 745system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 804system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 805system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 806system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 807system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 808system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 746system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 18115074 # number of hwpf identified 747system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 431506 # number of hwpf that were already in mshr 748system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 17132776 # number of hwpf that were already in the cache 749system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9283 # number of hwpf that were already in the prefetch queue 750system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 751system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6596 # number of hwpf removed because MSHR allocated 752system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 534910 # number of hwpf issued 753system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1383846 # number of hwpf spanning a virtual page 754system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 755system.cpu0.l2cache.tags.replacements 428439 # number of replacements 756system.cpu0.l2cache.tags.tagsinuse 16212.256950 # Cycle average of tags in use 757system.cpu0.l2cache.tags.total_refs 3152645 # Total number of references to valid blocks. 758system.cpu0.l2cache.tags.sampled_refs 444682 # Sample count of references to valid blocks. 759system.cpu0.l2cache.tags.avg_refs 7.089662 # Average number of references to valid blocks. 760system.cpu0.l2cache.tags.warmup_cycle 2824980212500 # Cycle when the warmup percentage was hit. 761system.cpu0.l2cache.tags.occ_blocks::writebacks 4226.197620 # Average occupied blocks per requestor 762system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 50.775812 # Average occupied blocks per requestor 763system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.065487 # Average occupied blocks per requestor 764system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2187.555983 # Average occupied blocks per requestor 765system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.662049 # Average occupied blocks per requestor 766system.cpu0.l2cache.tags.occ_percent::writebacks 0.257947 # Average percentage of cache occupancy 767system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003099 # Average percentage of cache occupancy | 809system.cpu0.l2cache.prefetcher.num_hwpf_issued 2292717 # number of hwpf issued 810system.cpu0.l2cache.prefetcher.pfIdentified 2293221 # number of prefetch candidates identified 811system.cpu0.l2cache.prefetcher.pfBufferHit 436 # number of redundant prefetches already in prefetch queue 812system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 813system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 814system.cpu0.l2cache.prefetcher.pfSpanPage 284211 # number of prefetches not generated due to page crossing 815system.cpu0.l2cache.tags.replacements 303376 # number of replacements 816system.cpu0.l2cache.tags.tagsinuse 16141.726832 # Cycle average of tags in use 817system.cpu0.l2cache.tags.total_refs 2969035 # Total number of references to valid blocks. 818system.cpu0.l2cache.tags.sampled_refs 319611 # Sample count of references to valid blocks. 819system.cpu0.l2cache.tags.avg_refs 9.289527 # Average number of references to valid blocks. 820system.cpu0.l2cache.tags.warmup_cycle 2825848630000 # Cycle when the warmup percentage was hit. 821system.cpu0.l2cache.tags.occ_blocks::writebacks 6310.295058 # Average occupied blocks per requestor 822system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.412646 # Average occupied blocks per requestor 823system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.063392 # Average occupied blocks per requestor 824system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 7791.524761 # Average occupied blocks per requestor 825system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1981.430976 # Average occupied blocks per requestor 826system.cpu0.l2cache.tags.occ_percent::writebacks 0.385150 # Average percentage of cache occupancy 827system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003565 # Average percentage of cache occupancy |
| 768system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy | 828system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy |
| 769system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.133518 # Average percentage of cache occupancy 770system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.594950 # Average percentage of cache occupancy 771system.cpu0.l2cache.tags.occ_percent::total 0.989518 # Average percentage of cache occupancy 772system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8981 # Occupied blocks per task id 773system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 774system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7254 # Occupied blocks per task id 775system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 61 # Occupied blocks per task id 776system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 111 # Occupied blocks per task id 777system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2870 # Occupied blocks per task id 778system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5529 # Occupied blocks per task id 779system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 410 # Occupied blocks per task id | 829system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.475557 # Average percentage of cache occupancy 830system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.120937 # Average percentage of cache occupancy 831system.cpu0.l2cache.tags.occ_percent::total 0.985213 # Average percentage of cache occupancy 832system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1941 # Occupied blocks per task id 833system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id 834system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14280 # Occupied blocks per task id 835system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id 836system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 509 # Occupied blocks per task id 837system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 923 # Occupied blocks per task id 838system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 497 # Occupied blocks per task id |
| 780system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id | 839system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id |
| 781system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 782system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 783system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 272 # Occupied blocks per task id 784system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3049 # Occupied blocks per task id 785system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3651 # Occupied blocks per task id 786system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 230 # Occupied blocks per task id 787system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.548157 # Percentage of cache occupancy per task id 788system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id 789system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.442749 # Percentage of cache occupancy per task id 790system.cpu0.l2cache.tags.tag_accesses 57799798 # Number of tag accesses 791system.cpu0.l2cache.tags.data_accesses 57799798 # Number of data accesses 792system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 84149 # number of ReadReq hits 793system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4243 # number of ReadReq hits 794system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2500411 # number of ReadReq hits 795system.cpu0.l2cache.ReadReq_hits::total 2588803 # number of ReadReq hits 796system.cpu0.l2cache.Writeback_hits::writebacks 541643 # number of Writeback hits 797system.cpu0.l2cache.Writeback_hits::total 541643 # number of Writeback hits 798system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4674 # number of UpgradeReq hits 799system.cpu0.l2cache.UpgradeReq_hits::total 4674 # number of UpgradeReq hits 800system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 2411 # number of SCUpgradeReq hits 801system.cpu0.l2cache.SCUpgradeReq_hits::total 2411 # number of SCUpgradeReq hits 802system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 234433 # number of ReadExReq hits 803system.cpu0.l2cache.ReadExReq_hits::total 234433 # number of ReadExReq hits 804system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 84149 # number of demand (read+write) hits 805system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4243 # number of demand (read+write) hits 806system.cpu0.l2cache.demand_hits::cpu0.inst 2734844 # number of demand (read+write) hits 807system.cpu0.l2cache.demand_hits::total 2823236 # number of demand (read+write) hits 808system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 84149 # number of overall hits 809system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4243 # number of overall hits 810system.cpu0.l2cache.overall_hits::cpu0.inst 2734844 # number of overall hits 811system.cpu0.l2cache.overall_hits::total 2823236 # number of overall hits 812system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 906 # number of ReadReq misses 813system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 138 # number of ReadReq misses 814system.cpu0.l2cache.ReadReq_misses::cpu0.inst 97001 # number of ReadReq misses 815system.cpu0.l2cache.ReadReq_misses::total 98045 # number of ReadReq misses 816system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 27960 # number of UpgradeReq misses 817system.cpu0.l2cache.UpgradeReq_misses::total 27960 # number of UpgradeReq misses 818system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 17929 # number of SCUpgradeReq misses 819system.cpu0.l2cache.SCUpgradeReq_misses::total 17929 # number of SCUpgradeReq misses 820system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 46525 # number of ReadExReq misses 821system.cpu0.l2cache.ReadExReq_misses::total 46525 # number of ReadExReq misses 822system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 906 # number of demand (read+write) misses 823system.cpu0.l2cache.demand_misses::cpu0.itb.walker 138 # number of demand (read+write) misses 824system.cpu0.l2cache.demand_misses::cpu0.inst 143526 # number of demand (read+write) misses 825system.cpu0.l2cache.demand_misses::total 144570 # number of demand (read+write) misses 826system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 906 # number of overall misses 827system.cpu0.l2cache.overall_misses::cpu0.itb.walker 138 # number of overall misses 828system.cpu0.l2cache.overall_misses::cpu0.inst 143526 # number of overall misses 829system.cpu0.l2cache.overall_misses::total 144570 # number of overall misses 830system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 31530500 # number of ReadReq miss cycles 831system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3231999 # number of ReadReq miss cycles 832system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2954004148 # number of ReadReq miss cycles 833system.cpu0.l2cache.ReadReq_miss_latency::total 2988766647 # number of ReadReq miss cycles 834system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 497244183 # number of UpgradeReq miss cycles 835system.cpu0.l2cache.UpgradeReq_miss_latency::total 497244183 # number of UpgradeReq miss cycles 836system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 356127296 # number of SCUpgradeReq miss cycles 837system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 356127296 # number of SCUpgradeReq miss cycles 838system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 112000 # number of SCUpgradeFailReq miss cycles 839system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 112000 # number of SCUpgradeFailReq miss cycles 840system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 1936152477 # number of ReadExReq miss cycles 841system.cpu0.l2cache.ReadExReq_miss_latency::total 1936152477 # number of ReadExReq miss cycles 842system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 31530500 # number of demand (read+write) miss cycles 843system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3231999 # number of demand (read+write) miss cycles 844system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4890156625 # number of demand (read+write) miss cycles 845system.cpu0.l2cache.demand_miss_latency::total 4924919124 # number of demand (read+write) miss cycles 846system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 31530500 # number of overall miss cycles 847system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3231999 # number of overall miss cycles 848system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4890156625 # number of overall miss cycles 849system.cpu0.l2cache.overall_miss_latency::total 4924919124 # number of overall miss cycles 850system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 85055 # number of ReadReq accesses(hits+misses) 851system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4381 # number of ReadReq accesses(hits+misses) 852system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 2597412 # number of ReadReq accesses(hits+misses) 853system.cpu0.l2cache.ReadReq_accesses::total 2686848 # number of ReadReq accesses(hits+misses) 854system.cpu0.l2cache.Writeback_accesses::writebacks 541643 # number of Writeback accesses(hits+misses) 855system.cpu0.l2cache.Writeback_accesses::total 541643 # number of Writeback accesses(hits+misses) 856system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 32634 # number of UpgradeReq accesses(hits+misses) 857system.cpu0.l2cache.UpgradeReq_accesses::total 32634 # number of UpgradeReq accesses(hits+misses) 858system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 20340 # number of SCUpgradeReq accesses(hits+misses) 859system.cpu0.l2cache.SCUpgradeReq_accesses::total 20340 # number of SCUpgradeReq accesses(hits+misses) 860system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 280958 # number of ReadExReq accesses(hits+misses) 861system.cpu0.l2cache.ReadExReq_accesses::total 280958 # number of ReadExReq accesses(hits+misses) 862system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 85055 # number of demand (read+write) accesses 863system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4381 # number of demand (read+write) accesses 864system.cpu0.l2cache.demand_accesses::cpu0.inst 2878370 # number of demand (read+write) accesses 865system.cpu0.l2cache.demand_accesses::total 2967806 # number of demand (read+write) accesses 866system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 85055 # number of overall (read+write) accesses 867system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4381 # number of overall (read+write) accesses 868system.cpu0.l2cache.overall_accesses::cpu0.inst 2878370 # number of overall (read+write) accesses 869system.cpu0.l2cache.overall_accesses::total 2967806 # number of overall (read+write) accesses 870system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010652 # miss rate for ReadReq accesses 871system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031500 # miss rate for ReadReq accesses 872system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.037345 # miss rate for ReadReq accesses 873system.cpu0.l2cache.ReadReq_miss_rate::total 0.036491 # miss rate for ReadReq accesses 874system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.856775 # miss rate for UpgradeReq accesses 875system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.856775 # miss rate for UpgradeReq accesses 876system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.881465 # miss rate for SCUpgradeReq accesses 877system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.881465 # miss rate for SCUpgradeReq accesses 878system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.165594 # miss rate for ReadExReq accesses 879system.cpu0.l2cache.ReadExReq_miss_rate::total 0.165594 # miss rate for ReadExReq accesses 880system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010652 # miss rate for demand accesses 881system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.031500 # miss rate for demand accesses 882system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.049864 # miss rate for demand accesses 883system.cpu0.l2cache.demand_miss_rate::total 0.048713 # miss rate for demand accesses 884system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010652 # miss rate for overall accesses 885system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.031500 # miss rate for overall accesses 886system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.049864 # miss rate for overall accesses 887system.cpu0.l2cache.overall_miss_rate::total 0.048713 # miss rate for overall accesses 888system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34801.876380 # average ReadReq miss latency 889system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23420.282609 # average ReadReq miss latency 890system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30453.337058 # average ReadReq miss latency 891system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30483.621266 # average ReadReq miss latency 892system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17784.126717 # average UpgradeReq miss latency 893system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17784.126717 # average UpgradeReq miss latency 894system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19863.199063 # average SCUpgradeReq miss latency 895system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19863.199063 # average SCUpgradeReq miss latency 896system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst inf # average SCUpgradeFailReq miss latency 897system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 898system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 41615.313853 # average ReadExReq miss latency 899system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 41615.313853 # average ReadExReq miss latency 900system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34801.876380 # average overall miss latency 901system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23420.282609 # average overall miss latency 902system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34071.573269 # average overall miss latency 903system.cpu0.l2cache.demand_avg_miss_latency::total 34065.982735 # average overall miss latency 904system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34801.876380 # average overall miss latency 905system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23420.282609 # average overall miss latency 906system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34071.573269 # average overall miss latency 907system.cpu0.l2cache.overall_avg_miss_latency::total 34065.982735 # average overall miss latency 908system.cpu0.l2cache.blocked_cycles::no_mshrs 25119 # number of cycles access was blocked | 840system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 841system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 842system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id 843system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id 844system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4022 # Occupied blocks per task id 845system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7455 # Occupied blocks per task id 846system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2494 # Occupied blocks per task id 847system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.118469 # Percentage of cache occupancy per task id 848system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id 849system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.871582 # Percentage of cache occupancy per task id 850system.cpu0.l2cache.tags.tag_accesses 55347065 # Number of tag accesses 851system.cpu0.l2cache.tags.data_accesses 55347065 # Number of data accesses 852system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 80493 # number of ReadReq hits 853system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4332 # number of ReadReq hits 854system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2344344 # number of ReadReq hits 855system.cpu0.l2cache.ReadReq_hits::total 2429169 # number of ReadReq hits 856system.cpu0.l2cache.Writeback_hits::writebacks 523100 # number of Writeback hits 857system.cpu0.l2cache.Writeback_hits::total 523100 # number of Writeback hits 858system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4781 # number of UpgradeReq hits 859system.cpu0.l2cache.UpgradeReq_hits::total 4781 # number of UpgradeReq hits 860system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 1890 # number of SCUpgradeReq hits 861system.cpu0.l2cache.SCUpgradeReq_hits::total 1890 # number of SCUpgradeReq hits 862system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 226532 # number of ReadExReq hits 863system.cpu0.l2cache.ReadExReq_hits::total 226532 # number of ReadExReq hits 864system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 80493 # number of demand (read+write) hits 865system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4332 # number of demand (read+write) hits 866system.cpu0.l2cache.demand_hits::cpu0.inst 2570876 # number of demand (read+write) hits 867system.cpu0.l2cache.demand_hits::total 2655701 # number of demand (read+write) hits 868system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 80493 # number of overall hits 869system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4332 # number of overall hits 870system.cpu0.l2cache.overall_hits::cpu0.inst 2570876 # number of overall hits 871system.cpu0.l2cache.overall_hits::total 2655701 # number of overall hits 872system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 854 # number of ReadReq misses 873system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 113 # number of ReadReq misses 874system.cpu0.l2cache.ReadReq_misses::cpu0.inst 142527 # number of ReadReq misses 875system.cpu0.l2cache.ReadReq_misses::total 143494 # number of ReadReq misses 876system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 26406 # number of UpgradeReq misses 877system.cpu0.l2cache.UpgradeReq_misses::total 26406 # number of UpgradeReq misses 878system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 18006 # number of SCUpgradeReq misses 879system.cpu0.l2cache.SCUpgradeReq_misses::total 18006 # number of SCUpgradeReq misses 880system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 2 # number of SCUpgradeFailReq misses 881system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 882system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 44082 # number of ReadExReq misses 883system.cpu0.l2cache.ReadExReq_misses::total 44082 # number of ReadExReq misses 884system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 854 # number of demand (read+write) misses 885system.cpu0.l2cache.demand_misses::cpu0.itb.walker 113 # number of demand (read+write) misses 886system.cpu0.l2cache.demand_misses::cpu0.inst 186609 # number of demand (read+write) misses 887system.cpu0.l2cache.demand_misses::total 187576 # number of demand (read+write) misses 888system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 854 # number of overall misses 889system.cpu0.l2cache.overall_misses::cpu0.itb.walker 113 # number of overall misses 890system.cpu0.l2cache.overall_misses::cpu0.inst 186609 # number of overall misses 891system.cpu0.l2cache.overall_misses::total 187576 # number of overall misses 892system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 30085500 # number of ReadReq miss cycles 893system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2495499 # number of ReadReq miss cycles 894system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 5310554679 # number of ReadReq miss cycles 895system.cpu0.l2cache.ReadReq_miss_latency::total 5343135678 # number of ReadReq miss cycles 896system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 462181513 # number of UpgradeReq miss cycles 897system.cpu0.l2cache.UpgradeReq_miss_latency::total 462181513 # number of UpgradeReq miss cycles 898system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 354964789 # number of SCUpgradeReq miss cycles 899system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 354964789 # number of SCUpgradeReq miss cycles 900system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 282000 # number of SCUpgradeFailReq miss cycles 901system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 282000 # number of SCUpgradeFailReq miss cycles 902system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 2099231484 # number of ReadExReq miss cycles 903system.cpu0.l2cache.ReadExReq_miss_latency::total 2099231484 # number of ReadExReq miss cycles 904system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 30085500 # number of demand (read+write) miss cycles 905system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2495499 # number of demand (read+write) miss cycles 906system.cpu0.l2cache.demand_miss_latency::cpu0.inst 7409786163 # number of demand (read+write) miss cycles 907system.cpu0.l2cache.demand_miss_latency::total 7442367162 # number of demand (read+write) miss cycles 908system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 30085500 # number of overall miss cycles 909system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2495499 # number of overall miss cycles 910system.cpu0.l2cache.overall_miss_latency::cpu0.inst 7409786163 # number of overall miss cycles 911system.cpu0.l2cache.overall_miss_latency::total 7442367162 # number of overall miss cycles 912system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 81347 # number of ReadReq accesses(hits+misses) 913system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4445 # number of ReadReq accesses(hits+misses) 914system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 2486871 # number of ReadReq accesses(hits+misses) 915system.cpu0.l2cache.ReadReq_accesses::total 2572663 # number of ReadReq accesses(hits+misses) 916system.cpu0.l2cache.Writeback_accesses::writebacks 523100 # number of Writeback accesses(hits+misses) 917system.cpu0.l2cache.Writeback_accesses::total 523100 # number of Writeback accesses(hits+misses) 918system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 31187 # number of UpgradeReq accesses(hits+misses) 919system.cpu0.l2cache.UpgradeReq_accesses::total 31187 # number of UpgradeReq accesses(hits+misses) 920system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 19896 # number of SCUpgradeReq accesses(hits+misses) 921system.cpu0.l2cache.SCUpgradeReq_accesses::total 19896 # number of SCUpgradeReq accesses(hits+misses) 922system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 2 # number of SCUpgradeFailReq accesses(hits+misses) 923system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 924system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 270614 # number of ReadExReq accesses(hits+misses) 925system.cpu0.l2cache.ReadExReq_accesses::total 270614 # number of ReadExReq accesses(hits+misses) 926system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 81347 # number of demand (read+write) accesses 927system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4445 # number of demand (read+write) accesses 928system.cpu0.l2cache.demand_accesses::cpu0.inst 2757485 # number of demand (read+write) accesses 929system.cpu0.l2cache.demand_accesses::total 2843277 # number of demand (read+write) accesses 930system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 81347 # number of overall (read+write) accesses 931system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4445 # number of overall (read+write) accesses 932system.cpu0.l2cache.overall_accesses::cpu0.inst 2757485 # number of overall (read+write) accesses 933system.cpu0.l2cache.overall_accesses::total 2843277 # number of overall (read+write) accesses 934system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010498 # miss rate for ReadReq accesses 935system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025422 # miss rate for ReadReq accesses 936system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.057312 # miss rate for ReadReq accesses 937system.cpu0.l2cache.ReadReq_miss_rate::total 0.055776 # miss rate for ReadReq accesses 938system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.846699 # miss rate for UpgradeReq accesses 939system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.846699 # miss rate for UpgradeReq accesses 940system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.905006 # miss rate for SCUpgradeReq accesses 941system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.905006 # miss rate for SCUpgradeReq accesses 942system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses 943system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 944system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.162896 # miss rate for ReadExReq accesses 945system.cpu0.l2cache.ReadExReq_miss_rate::total 0.162896 # miss rate for ReadExReq accesses 946system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010498 # miss rate for demand accesses 947system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025422 # miss rate for demand accesses 948system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.067674 # miss rate for demand accesses 949system.cpu0.l2cache.demand_miss_rate::total 0.065972 # miss rate for demand accesses 950system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010498 # miss rate for overall accesses 951system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025422 # miss rate for overall accesses 952system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.067674 # miss rate for overall accesses 953system.cpu0.l2cache.overall_miss_rate::total 0.065972 # miss rate for overall accesses 954system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35228.922717 # average ReadReq miss latency 955system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22084.061947 # average ReadReq miss latency 956system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37259.990591 # average ReadReq miss latency 957system.cpu0.l2cache.ReadReq_avg_miss_latency::total 37235.951873 # average ReadReq miss latency 958system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17502.897561 # average UpgradeReq miss latency 959system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17502.897561 # average UpgradeReq miss latency 960system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19713.694824 # average SCUpgradeReq miss latency 961system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19713.694824 # average SCUpgradeReq miss latency 962system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 141000 # average SCUpgradeFailReq miss latency 963system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 141000 # average SCUpgradeFailReq miss latency 964system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 47621.058119 # average ReadExReq miss latency 965system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47621.058119 # average ReadExReq miss latency 966system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35228.922717 # average overall miss latency 967system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22084.061947 # average overall miss latency 968system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39707.549813 # average overall miss latency 969system.cpu0.l2cache.demand_avg_miss_latency::total 39676.542639 # average overall miss latency 970system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35228.922717 # average overall miss latency 971system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22084.061947 # average overall miss latency 972system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39707.549813 # average overall miss latency 973system.cpu0.l2cache.overall_avg_miss_latency::total 39676.542639 # average overall miss latency 974system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 909system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 975system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 910system.cpu0.l2cache.blocked::no_mshrs 346 # number of cycles access was blocked | 976system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 911system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 977system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 912system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 72.598266 # average number of cycles each access was blocked | 978system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 913system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 914system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 915system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 979system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 980system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 981system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 916system.cpu0.l2cache.writebacks::writebacks 220063 # number of writebacks 917system.cpu0.l2cache.writebacks::total 220063 # number of writebacks 918system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 8315 # number of ReadReq MSHR hits 919system.cpu0.l2cache.ReadReq_mshr_hits::total 8315 # number of ReadReq MSHR hits 920system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 3034 # number of ReadExReq MSHR hits 921system.cpu0.l2cache.ReadExReq_mshr_hits::total 3034 # number of ReadExReq MSHR hits 922system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 11349 # number of demand (read+write) MSHR hits 923system.cpu0.l2cache.demand_mshr_hits::total 11349 # number of demand (read+write) MSHR hits 924system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 11349 # number of overall MSHR hits 925system.cpu0.l2cache.overall_mshr_hits::total 11349 # number of overall MSHR hits 926system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 906 # number of ReadReq MSHR misses 927system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 138 # number of ReadReq MSHR misses 928system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 88686 # number of ReadReq MSHR misses 929system.cpu0.l2cache.ReadReq_mshr_misses::total 89730 # number of ReadReq MSHR misses 930system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 534906 # number of HardPFReq MSHR misses 931system.cpu0.l2cache.HardPFReq_mshr_misses::total 534906 # number of HardPFReq MSHR misses 932system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 27960 # number of UpgradeReq MSHR misses 933system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27960 # number of UpgradeReq MSHR misses 934system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 17929 # number of SCUpgradeReq MSHR misses 935system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17929 # number of SCUpgradeReq MSHR misses 936system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 43491 # number of ReadExReq MSHR misses 937system.cpu0.l2cache.ReadExReq_mshr_misses::total 43491 # number of ReadExReq MSHR misses 938system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 906 # number of demand (read+write) MSHR misses 939system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 138 # number of demand (read+write) MSHR misses 940system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 132177 # number of demand (read+write) MSHR misses 941system.cpu0.l2cache.demand_mshr_misses::total 133221 # number of demand (read+write) MSHR misses 942system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 906 # number of overall MSHR misses 943system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 138 # number of overall MSHR misses 944system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 132177 # number of overall MSHR misses 945system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 534906 # number of overall MSHR misses 946system.cpu0.l2cache.overall_mshr_misses::total 668127 # number of overall MSHR misses 947system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 25168500 # number of ReadReq MSHR miss cycles 948system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2265999 # number of ReadReq MSHR miss cycles 949system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2160848492 # number of ReadReq MSHR miss cycles 950system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2188282991 # number of ReadReq MSHR miss cycles 951system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21648732719 # number of HardPFReq MSHR miss cycles 952system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21648732719 # number of HardPFReq MSHR miss cycles 953system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 481473058 # number of UpgradeReq MSHR miss cycles 954system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 481473058 # number of UpgradeReq MSHR miss cycles 955system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 238593946 # number of SCUpgradeReq MSHR miss cycles 956system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 238593946 # number of SCUpgradeReq MSHR miss cycles 957system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 91000 # number of SCUpgradeFailReq MSHR miss cycles 958system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 91000 # number of SCUpgradeFailReq MSHR miss cycles 959system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 1198815233 # number of ReadExReq MSHR miss cycles 960system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1198815233 # number of ReadExReq MSHR miss cycles 961system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 25168500 # number of demand (read+write) MSHR miss cycles 962system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2265999 # number of demand (read+write) MSHR miss cycles 963system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3359663725 # number of demand (read+write) MSHR miss cycles 964system.cpu0.l2cache.demand_mshr_miss_latency::total 3387098224 # number of demand (read+write) MSHR miss cycles 965system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 25168500 # number of overall MSHR miss cycles 966system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2265999 # number of overall MSHR miss cycles 967system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3359663725 # number of overall MSHR miss cycles 968system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21648732719 # number of overall MSHR miss cycles 969system.cpu0.l2cache.overall_mshr_miss_latency::total 25035830943 # number of overall MSHR miss cycles 970system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6180670251 # number of ReadReq MSHR uncacheable cycles 971system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6180670251 # number of ReadReq MSHR uncacheable cycles 972system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4594924508 # number of WriteReq MSHR uncacheable cycles 973system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4594924508 # number of WriteReq MSHR uncacheable cycles 974system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10775594759 # number of overall MSHR uncacheable cycles 975system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10775594759 # number of overall MSHR uncacheable cycles 976system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010652 # mshr miss rate for ReadReq accesses 977system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031500 # mshr miss rate for ReadReq accesses 978system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.034144 # mshr miss rate for ReadReq accesses 979system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.033396 # mshr miss rate for ReadReq accesses | 982system.cpu0.l2cache.writebacks::writebacks 201133 # number of writebacks 983system.cpu0.l2cache.writebacks::total 201133 # number of writebacks 984system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits 985system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 511 # number of ReadReq MSHR hits 986system.cpu0.l2cache.ReadReq_mshr_hits::total 512 # number of ReadReq MSHR hits 987system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 3265 # number of ReadExReq MSHR hits 988system.cpu0.l2cache.ReadExReq_mshr_hits::total 3265 # number of ReadExReq MSHR hits 989system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits 990system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3776 # number of demand (read+write) MSHR hits 991system.cpu0.l2cache.demand_mshr_hits::total 3777 # number of demand (read+write) MSHR hits 992system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits 993system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3776 # number of overall MSHR hits 994system.cpu0.l2cache.overall_mshr_hits::total 3777 # number of overall MSHR hits 995system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 854 # number of ReadReq MSHR misses 996system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 112 # number of ReadReq MSHR misses 997system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 142016 # number of ReadReq MSHR misses 998system.cpu0.l2cache.ReadReq_mshr_misses::total 142982 # number of ReadReq MSHR misses 999system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 280772 # number of HardPFReq MSHR misses 1000system.cpu0.l2cache.HardPFReq_mshr_misses::total 280772 # number of HardPFReq MSHR misses 1001system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 26406 # number of UpgradeReq MSHR misses 1002system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26406 # number of UpgradeReq MSHR misses 1003system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 18006 # number of SCUpgradeReq MSHR misses 1004system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18006 # number of SCUpgradeReq MSHR misses 1005system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 2 # number of SCUpgradeFailReq MSHR misses 1006system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 1007system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 40817 # number of ReadExReq MSHR misses 1008system.cpu0.l2cache.ReadExReq_mshr_misses::total 40817 # number of ReadExReq MSHR misses 1009system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 854 # number of demand (read+write) MSHR misses 1010system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 112 # number of demand (read+write) MSHR misses 1011system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 182833 # number of demand (read+write) MSHR misses 1012system.cpu0.l2cache.demand_mshr_misses::total 183799 # number of demand (read+write) MSHR misses 1013system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 854 # number of overall MSHR misses 1014system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 112 # number of overall MSHR misses 1015system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 182833 # number of overall MSHR misses 1016system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 280772 # number of overall MSHR misses 1017system.cpu0.l2cache.overall_mshr_misses::total 464571 # number of overall MSHR misses 1018system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 24090000 # number of ReadReq MSHR miss cycles 1019system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1685499 # number of ReadReq MSHR miss cycles 1020system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 4279514975 # number of ReadReq MSHR miss cycles 1021system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4305290474 # number of ReadReq MSHR miss cycles 1022system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15488924735 # number of HardPFReq MSHR miss cycles 1023system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15488924735 # number of HardPFReq MSHR miss cycles 1024system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 449600763 # number of UpgradeReq MSHR miss cycles 1025system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 449600763 # number of UpgradeReq MSHR miss cycles 1026system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 240569359 # number of SCUpgradeReq MSHR miss cycles 1027system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 240569359 # number of SCUpgradeReq MSHR miss cycles 1028system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 219000 # number of SCUpgradeFailReq MSHR miss cycles 1029system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 219000 # number of SCUpgradeFailReq MSHR miss cycles 1030system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 1467254248 # number of ReadExReq MSHR miss cycles 1031system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1467254248 # number of ReadExReq MSHR miss cycles 1032system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 24090000 # number of demand (read+write) MSHR miss cycles 1033system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1685499 # number of demand (read+write) MSHR miss cycles 1034system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 5746769223 # number of demand (read+write) MSHR miss cycles 1035system.cpu0.l2cache.demand_mshr_miss_latency::total 5772544722 # number of demand (read+write) MSHR miss cycles 1036system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 24090000 # number of overall MSHR miss cycles 1037system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1685499 # number of overall MSHR miss cycles 1038system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 5746769223 # number of overall MSHR miss cycles 1039system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15488924735 # number of overall MSHR miss cycles 1040system.cpu0.l2cache.overall_mshr_miss_latency::total 21261469457 # number of overall MSHR miss cycles 1041system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6177076991 # number of ReadReq MSHR uncacheable cycles 1042system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6177076991 # number of ReadReq MSHR uncacheable cycles 1043system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4588309497 # number of WriteReq MSHR uncacheable cycles 1044system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4588309497 # number of WriteReq MSHR uncacheable cycles 1045system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10765386488 # number of overall MSHR uncacheable cycles 1046system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10765386488 # number of overall MSHR uncacheable cycles 1047system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for ReadReq accesses 1048system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for ReadReq accesses 1049system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.057106 # mshr miss rate for ReadReq accesses 1050system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.055577 # mshr miss rate for ReadReq accesses |
| 980system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 981system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1051system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1052system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 982system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.856775 # mshr miss rate for UpgradeReq accesses 983system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.856775 # mshr miss rate for UpgradeReq accesses 984system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.881465 # mshr miss rate for SCUpgradeReq accesses 985system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.881465 # mshr miss rate for SCUpgradeReq accesses 986system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.154795 # mshr miss rate for ReadExReq accesses 987system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154795 # mshr miss rate for ReadExReq accesses 988system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010652 # mshr miss rate for demand accesses 989system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031500 # mshr miss rate for demand accesses 990system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.045921 # mshr miss rate for demand accesses 991system.cpu0.l2cache.demand_mshr_miss_rate::total 0.044889 # mshr miss rate for demand accesses 992system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010652 # mshr miss rate for overall accesses 993system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031500 # mshr miss rate for overall accesses 994system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.045921 # mshr miss rate for overall accesses | 1053system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.846699 # mshr miss rate for UpgradeReq accesses 1054system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.846699 # mshr miss rate for UpgradeReq accesses 1055system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.905006 # mshr miss rate for SCUpgradeReq accesses 1056system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.905006 # mshr miss rate for SCUpgradeReq accesses 1057system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses 1058system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1059system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.150831 # mshr miss rate for ReadExReq accesses 1060system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150831 # mshr miss rate for ReadExReq accesses 1061system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for demand accesses 1062system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for demand accesses 1063system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.066304 # mshr miss rate for demand accesses 1064system.cpu0.l2cache.demand_mshr_miss_rate::total 0.064643 # mshr miss rate for demand accesses 1065system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for overall accesses 1066system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for overall accesses 1067system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.066304 # mshr miss rate for overall accesses |
| 995system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1068system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 996system.cpu0.l2cache.overall_mshr_miss_rate::total 0.225125 # mshr miss rate for overall accesses 997system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average ReadReq mshr miss latency 998system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average ReadReq mshr miss latency 999system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24365.159010 # average ReadReq mshr miss latency 1000system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24387.417709 # average ReadReq mshr miss latency 1001system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40472.031944 # average HardPFReq mshr miss latency 1002system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40472.031944 # average HardPFReq mshr miss latency 1003system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17220.066452 # average UpgradeReq mshr miss latency 1004system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17220.066452 # average UpgradeReq mshr miss latency 1005system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13307.710748 # average SCUpgradeReq mshr miss latency 1006system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13307.710748 # average SCUpgradeReq mshr miss latency 1007system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst inf # average SCUpgradeFailReq mshr miss latency 1008system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 1009system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27564.673910 # average ReadExReq mshr miss latency 1010system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27564.673910 # average ReadExReq mshr miss latency 1011system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average overall mshr miss latency 1012system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average overall mshr miss latency 1013system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25417.914804 # average overall mshr miss latency 1014system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25424.656953 # average overall mshr miss latency 1015system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average overall mshr miss latency 1016system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average overall mshr miss latency 1017system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25417.914804 # average overall mshr miss latency 1018system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40472.031944 # average overall mshr miss latency 1019system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37471.664733 # average overall mshr miss latency | 1069system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163393 # mshr miss rate for overall accesses 1070system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average ReadReq mshr miss latency 1071system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average ReadReq mshr miss latency 1072system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30134.034017 # average ReadReq mshr miss latency 1073system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30110.716552 # average ReadReq mshr miss latency 1074system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205 # average HardPFReq mshr miss latency 1075system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55165.489205 # average HardPFReq mshr miss latency 1076system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17026.462281 # average UpgradeReq mshr miss latency 1077system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17026.462281 # average UpgradeReq mshr miss latency 1078system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13360.510885 # average SCUpgradeReq mshr miss latency 1079system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13360.510885 # average SCUpgradeReq mshr miss latency 1080system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 109500 # average SCUpgradeFailReq mshr miss latency 1081system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 109500 # average SCUpgradeFailReq mshr miss latency 1082system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 35947.135948 # average ReadExReq mshr miss latency 1083system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 35947.135948 # average ReadExReq mshr miss latency 1084system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average overall mshr miss latency 1085system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average overall mshr miss latency 1086system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31431.794167 # average overall mshr miss latency 1087system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31406.834216 # average overall mshr miss latency 1088system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average overall mshr miss latency 1089system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average overall mshr miss latency 1090system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31431.794167 # average overall mshr miss latency 1091system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205 # average overall mshr miss latency 1092system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45765.812883 # average overall mshr miss latency |
| 1020system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1021system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1022system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 1023system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1024system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1025system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1026system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1093system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1094system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1095system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 1096system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1097system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1098system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1099system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1027system.cpu0.toL2Bus.trans_dist::ReadReq 2861093 # Transaction distribution 1028system.cpu0.toL2Bus.trans_dist::ReadResp 2792980 # Transaction distribution 1029system.cpu0.toL2Bus.trans_dist::WriteReq 28855 # Transaction distribution 1030system.cpu0.toL2Bus.trans_dist::WriteResp 28855 # Transaction distribution 1031system.cpu0.toL2Bus.trans_dist::Writeback 541643 # Transaction distribution 1032system.cpu0.toL2Bus.trans_dist::HardPFReq 731101 # Transaction distribution | 1100system.cpu0.toL2Bus.trans_dist::ReadReq 2726808 # Transaction distribution 1101system.cpu0.toL2Bus.trans_dist::ReadResp 2669763 # Transaction distribution 1102system.cpu0.toL2Bus.trans_dist::WriteReq 28813 # Transaction distribution 1103system.cpu0.toL2Bus.trans_dist::WriteResp 28813 # Transaction distribution 1104system.cpu0.toL2Bus.trans_dist::Writeback 523100 # Transaction distribution 1105system.cpu0.toL2Bus.trans_dist::HardPFReq 388140 # Transaction distribution |
| 1033system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution | 1106system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution |
| 1034system.cpu0.toL2Bus.trans_dist::UpgradeReq 68486 # Transaction distribution 1035system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42622 # Transaction distribution 1036system.cpu0.toL2Bus.trans_dist::UpgradeResp 93982 # Transaction distribution 1037system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 1038system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution 1039system.cpu0.toL2Bus.trans_dist::ReadExReq 302729 # Transaction distribution 1040system.cpu0.toL2Bus.trans_dist::ReadExResp 293421 # Transaction distribution 1041system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 4148051 # Packet count per connected master and slave (bytes) 1042system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2491359 # Packet count per connected master and slave (bytes) 1043system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12339 # Packet count per connected master and slave (bytes) 1044system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 183942 # Packet count per connected master and slave (bytes) 1045system.cpu0.toL2Bus.pkt_count::total 6835691 # Packet count per connected master and slave (bytes) 1046system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 132737600 # Cumulative packet size per connected master and slave (bytes) 1047system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 90757533 # Cumulative packet size per connected master and slave (bytes) 1048system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17524 # Cumulative packet size per connected master and slave (bytes) 1049system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 340220 # Cumulative packet size per connected master and slave (bytes) 1050system.cpu0.toL2Bus.pkt_size::total 223852877 # Cumulative packet size per connected master and slave (bytes) 1051system.cpu0.toL2Bus.snoops 1093341 # Total snoops (count) 1052system.cpu0.toL2Bus.snoop_fanout::samples 4548807 # Request fanout histogram 1053system.cpu0.toL2Bus.snoop_fanout::mean 5.213001 # Request fanout histogram 1054system.cpu0.toL2Bus.snoop_fanout::stdev 0.409428 # Request fanout histogram | 1107system.cpu0.toL2Bus.trans_dist::UpgradeReq 64720 # Transaction distribution 1108system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42432 # Transaction distribution 1109system.cpu0.toL2Bus.trans_dist::UpgradeResp 88655 # Transaction distribution 1110system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution 1111system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 13 # Transaction distribution 1112system.cpu0.toL2Bus.trans_dist::ReadExReq 299964 # Transaction distribution 1113system.cpu0.toL2Bus.trans_dist::ReadExResp 286773 # Transaction distribution 1114system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3972081 # Packet count per connected master and slave (bytes) 1115system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2399294 # Packet count per connected master and slave (bytes) 1116system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11788 # Packet count per connected master and slave (bytes) 1117system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 172273 # Packet count per connected master and slave (bytes) 1118system.cpu0.toL2Bus.pkt_count::total 6555436 # Packet count per connected master and slave (bytes) 1119system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 127106560 # Cumulative packet size per connected master and slave (bytes) 1120system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 87442327 # Cumulative packet size per connected master and slave (bytes) 1121system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17780 # Cumulative packet size per connected master and slave (bytes) 1122system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 325388 # Cumulative packet size per connected master and slave (bytes) 1123system.cpu0.toL2Bus.pkt_size::total 214892055 # Cumulative packet size per connected master and slave (bytes) 1124system.cpu0.toL2Bus.snoops 732010 # Total snoops (count) 1125system.cpu0.toL2Bus.snoop_fanout::samples 4046250 # Request fanout histogram 1126system.cpu0.toL2Bus.snoop_fanout::mean 5.152317 # Request fanout histogram 1127system.cpu0.toL2Bus.snoop_fanout::stdev 0.359328 # Request fanout histogram |
| 1055system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1056system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1057system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1058system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1059system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1060system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1128system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1129system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1130system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1131system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1132system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1133system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 1061system.cpu0.toL2Bus.snoop_fanout::5 3579907 78.70% 78.70% # Request fanout histogram 1062system.cpu0.toL2Bus.snoop_fanout::6 968900 21.30% 100.00% # Request fanout histogram | 1134system.cpu0.toL2Bus.snoop_fanout::5 3429939 84.77% 84.77% # Request fanout histogram 1135system.cpu0.toL2Bus.snoop_fanout::6 616311 15.23% 100.00% # Request fanout histogram |
| 1063system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1064system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1065system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 1136system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1137system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1138system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 1066system.cpu0.toL2Bus.snoop_fanout::total 4548807 # Request fanout histogram 1067system.cpu0.toL2Bus.reqLayer0.occupancy 2378574445 # Layer occupancy (ticks) | 1139system.cpu0.toL2Bus.snoop_fanout::total 4046250 # Request fanout histogram 1140system.cpu0.toL2Bus.reqLayer0.occupancy 2284841999 # Layer occupancy (ticks) |
| 1068system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1141system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1069system.cpu0.toL2Bus.snoopLayer0.occupancy 119537998 # Layer occupancy (ticks) | 1142system.cpu0.toL2Bus.snoopLayer0.occupancy 117254000 # Layer occupancy (ticks) |
| 1070system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1143system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1071system.cpu0.toL2Bus.respLayer0.occupancy 3112636730 # Layer occupancy (ticks) | 1144system.cpu0.toL2Bus.respLayer0.occupancy 2984852953 # Layer occupancy (ticks) |
| 1072system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1145system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1073system.cpu0.toL2Bus.respLayer1.occupancy 1291088389 # Layer occupancy (ticks) | 1146system.cpu0.toL2Bus.respLayer1.occupancy 1241569539 # Layer occupancy (ticks) |
| 1074system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1147system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1075system.cpu0.toL2Bus.respLayer2.occupancy 7963988 # Layer occupancy (ticks) | 1148system.cpu0.toL2Bus.respLayer2.occupancy 7347491 # Layer occupancy (ticks) |
| 1076system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1149system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1077system.cpu0.toL2Bus.respLayer3.occupancy 98908477 # Layer occupancy (ticks) | 1150system.cpu0.toL2Bus.respLayer3.occupancy 90940738 # Layer occupancy (ticks) |
| 1078system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1151system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1079system.cpu1.branchPred.lookups 3448752 # Number of BP lookups 1080system.cpu1.branchPred.condPredicted 1941981 # Number of conditional branches predicted 1081system.cpu1.branchPred.condIncorrect 196391 # Number of conditional branches incorrect 1082system.cpu1.branchPred.BTBLookups 2221819 # Number of BTB lookups 1083system.cpu1.branchPred.BTBHits 1396869 # Number of BTB hits | 1152system.cpu1.branchPred.lookups 4088735 # Number of BP lookups 1153system.cpu1.branchPred.condPredicted 2366310 # Number of conditional branches predicted 1154system.cpu1.branchPred.condIncorrect 253216 # Number of conditional branches incorrect 1155system.cpu1.branchPred.BTBLookups 2663045 # Number of BTB lookups 1156system.cpu1.branchPred.BTBHits 1651600 # Number of BTB hits |
| 1084system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1157system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1085system.cpu1.branchPred.BTBHitPct 62.870513 # BTB Hit Percentage 1086system.cpu1.branchPred.usedRAS 715789 # Number of times the RAS was used to get a target. 1087system.cpu1.branchPred.RASInCorrect 52420 # Number of incorrect RAS predictions. | 1158system.cpu1.branchPred.BTBHitPct 62.019230 # BTB Hit Percentage 1159system.cpu1.branchPred.usedRAS 809555 # Number of times the RAS was used to get a target. 1160system.cpu1.branchPred.RASInCorrect 58673 # Number of incorrect RAS predictions. 1161system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1162system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1163system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1164system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1165system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1166system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1167system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1168system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| 1088system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1089system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1090system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1091system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1092system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1093system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1094system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1095system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1101system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1102system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1103system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1104system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1105system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1106system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1107system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1108system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1169system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1170system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1171system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1172system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1173system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1174system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1175system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1176system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1182system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1183system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1184system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1185system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1186system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1187system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1188system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1189system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1190system.cpu1.dtb.walker.walks 25571 # Table walker walks requested 1191system.cpu1.dtb.walker.walksShort 25571 # Table walker walks initiated with short descriptors 1192system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18521 # Level at which table walker walks with short descriptors terminate 1193system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7050 # Level at which table walker walks with short descriptors terminate 1194system.cpu1.dtb.walker.walkWaitTime::samples 25571 # Table walker wait (enqueue to first request) latency 1195system.cpu1.dtb.walker.walkWaitTime::0 25571 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1196system.cpu1.dtb.walker.walkWaitTime::total 25571 # Table walker wait (enqueue to first request) latency 1197system.cpu1.dtb.walker.walkCompletionTime::samples 2708 # Table walker service (enqueue to completion) latency 1198system.cpu1.dtb.walker.walkCompletionTime::mean 8701.256278 # Table walker service (enqueue to completion) latency 1199system.cpu1.dtb.walker.walkCompletionTime::gmean 7631.681902 # Table walker service (enqueue to completion) latency 1200system.cpu1.dtb.walker.walkCompletionTime::stdev 5745.938863 # Table walker service (enqueue to completion) latency 1201system.cpu1.dtb.walker.walkCompletionTime::0-8191 2093 77.29% 77.29% # Table walker service (enqueue to completion) latency 1202system.cpu1.dtb.walker.walkCompletionTime::8192-16383 481 17.76% 95.05% # Table walker service (enqueue to completion) latency 1203system.cpu1.dtb.walker.walkCompletionTime::16384-24575 65 2.40% 97.45% # Table walker service (enqueue to completion) latency 1204system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.07% 99.52% # Table walker service (enqueue to completion) latency 1205system.cpu1.dtb.walker.walkCompletionTime::40960-49151 9 0.33% 99.85% # Table walker service (enqueue to completion) latency 1206system.cpu1.dtb.walker.walkCompletionTime::81920-90111 4 0.15% 100.00% # Table walker service (enqueue to completion) latency 1207system.cpu1.dtb.walker.walkCompletionTime::total 2708 # Table walker service (enqueue to completion) latency 1208system.cpu1.dtb.walker.walksPending::samples 1108722264 # Table walker pending requests distribution 1209system.cpu1.dtb.walker.walksPending::0 1108722264 100.00% 100.00% # Table walker pending requests distribution 1210system.cpu1.dtb.walker.walksPending::total 1108722264 # Table walker pending requests distribution 1211system.cpu1.dtb.walker.walkPageSizes::4K 1997 73.74% 73.74% # Table walker page sizes translated 1212system.cpu1.dtb.walker.walkPageSizes::1M 711 26.26% 100.00% # Table walker page sizes translated 1213system.cpu1.dtb.walker.walkPageSizes::total 2708 # Table walker page sizes translated 1214system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 25571 # Table walker requests started/completed, data/inst 1215system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1216system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 25571 # Table walker requests started/completed, data/inst 1217system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2708 # Table walker requests started/completed, data/inst 1218system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1219system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2708 # Table walker requests started/completed, data/inst 1220system.cpu1.dtb.walker.walkRequestOrigin::total 28279 # Table walker requests started/completed, data/inst |
|
| 1109system.cpu1.dtb.inst_hits 0 # ITB inst hits 1110system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1221system.cpu1.dtb.inst_hits 0 # ITB inst hits 1222system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1111system.cpu1.dtb.read_hits 3432223 # DTB read hits 1112system.cpu1.dtb.read_misses 19764 # DTB read misses 1113system.cpu1.dtb.write_hits 2826731 # DTB write hits 1114system.cpu1.dtb.write_misses 1392 # DTB write misses | 1223system.cpu1.dtb.read_hits 4075725 # DTB read hits 1224system.cpu1.dtb.read_misses 23546 # DTB read misses 1225system.cpu1.dtb.write_hits 3346999 # DTB write hits 1226system.cpu1.dtb.write_misses 2025 # DTB write misses |
| 1115system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1116system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1117system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1118system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1227system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1228system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1229system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1230system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1119system.cpu1.dtb.flush_entries 1674 # Number of entries that have been flushed from TLB 1120system.cpu1.dtb.align_faults 101 # Number of TLB faults due to alignment restrictions 1121system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch | 1231system.cpu1.dtb.flush_entries 2069 # Number of entries that have been flushed from TLB 1232system.cpu1.dtb.align_faults 121 # Number of TLB faults due to alignment restrictions 1233system.cpu1.dtb.prefetch_faults 325 # Number of TLB faults due to prefetch |
| 1122system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1234system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1123system.cpu1.dtb.perms_faults 209 # Number of TLB faults due to permissions restrictions 1124system.cpu1.dtb.read_accesses 3451987 # DTB read accesses 1125system.cpu1.dtb.write_accesses 2828123 # DTB write accesses | 1235system.cpu1.dtb.perms_faults 279 # Number of TLB faults due to permissions restrictions 1236system.cpu1.dtb.read_accesses 4099271 # DTB read accesses 1237system.cpu1.dtb.write_accesses 3349024 # DTB write accesses |
| 1126system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1238system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1127system.cpu1.dtb.hits 6258954 # DTB hits 1128system.cpu1.dtb.misses 21156 # DTB misses 1129system.cpu1.dtb.accesses 6280110 # DTB accesses | 1239system.cpu1.dtb.hits 7422724 # DTB hits 1240system.cpu1.dtb.misses 25571 # DTB misses 1241system.cpu1.dtb.accesses 7448295 # DTB accesses 1242system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1243system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1244system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1245system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1246system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1247system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1248system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1249system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| 1130system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1131system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1132system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1133system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1134system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1135system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1136system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1137system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1143system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1144system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1145system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1146system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1147system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1148system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1149system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1150system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1250system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1251system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1252system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1253system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1254system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1255system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1256system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1257system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1263system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1264system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1265system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1266system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1267system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1268system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1269system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1270system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1151system.cpu1.itb.inst_hits 6653879 # ITB inst hits 1152system.cpu1.itb.inst_misses 1856 # ITB inst misses | 1271system.cpu1.itb.walker.walks 2243 # Table walker walks requested 1272system.cpu1.itb.walker.walksShort 2243 # Table walker walks initiated with short descriptors 1273system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate 1274system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2062 # Level at which table walker walks with short descriptors terminate 1275system.cpu1.itb.walker.walkWaitTime::samples 2243 # Table walker wait (enqueue to first request) latency 1276system.cpu1.itb.walker.walkWaitTime::0 2243 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1277system.cpu1.itb.walker.walkWaitTime::total 2243 # Table walker wait (enqueue to first request) latency 1278system.cpu1.itb.walker.walkCompletionTime::samples 1122 # Table walker service (enqueue to completion) latency 1279system.cpu1.itb.walker.walkCompletionTime::mean 8831.106061 # Table walker service (enqueue to completion) latency 1280system.cpu1.itb.walker.walkCompletionTime::gmean 7825.020839 # Table walker service (enqueue to completion) latency 1281system.cpu1.itb.walker.walkCompletionTime::stdev 4777.823788 # Table walker service (enqueue to completion) latency 1282system.cpu1.itb.walker.walkCompletionTime::0-4095 160 14.26% 14.26% # Table walker service (enqueue to completion) latency 1283system.cpu1.itb.walker.walkCompletionTime::4096-8191 676 60.25% 74.51% # Table walker service (enqueue to completion) latency 1284system.cpu1.itb.walker.walkCompletionTime::8192-12287 3 0.27% 74.78% # Table walker service (enqueue to completion) latency 1285system.cpu1.itb.walker.walkCompletionTime::12288-16383 248 22.10% 96.88% # Table walker service (enqueue to completion) latency 1286system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 96.97% # Table walker service (enqueue to completion) latency 1287system.cpu1.itb.walker.walkCompletionTime::24576-28671 13 1.16% 98.13% # Table walker service (enqueue to completion) latency 1288system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.69% 99.82% # Table walker service (enqueue to completion) latency 1289system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.91% # Table walker service (enqueue to completion) latency 1290system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 100.00% # Table walker service (enqueue to completion) latency 1291system.cpu1.itb.walker.walkCompletionTime::total 1122 # Table walker service (enqueue to completion) latency 1292system.cpu1.itb.walker.walksPending::samples 1108154264 # Table walker pending requests distribution 1293system.cpu1.itb.walker.walksPending::0 1108154264 100.00% 100.00% # Table walker pending requests distribution 1294system.cpu1.itb.walker.walksPending::total 1108154264 # Table walker pending requests distribution 1295system.cpu1.itb.walker.walkPageSizes::4K 954 85.03% 85.03% # Table walker page sizes translated 1296system.cpu1.itb.walker.walkPageSizes::1M 168 14.97% 100.00% # Table walker page sizes translated 1297system.cpu1.itb.walker.walkPageSizes::total 1122 # Table walker page sizes translated 1298system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1299system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2243 # Table walker requests started/completed, data/inst 1300system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2243 # Table walker requests started/completed, data/inst 1301system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1302system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1122 # Table walker requests started/completed, data/inst 1303system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1122 # Table walker requests started/completed, data/inst 1304system.cpu1.itb.walker.walkRequestOrigin::total 3365 # Table walker requests started/completed, data/inst 1305system.cpu1.itb.inst_hits 7772051 # ITB inst hits 1306system.cpu1.itb.inst_misses 2243 # ITB inst misses |
| 1153system.cpu1.itb.read_hits 0 # DTB read hits 1154system.cpu1.itb.read_misses 0 # DTB read misses 1155system.cpu1.itb.write_hits 0 # DTB write hits 1156system.cpu1.itb.write_misses 0 # DTB write misses 1157system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1158system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1159system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1160system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1307system.cpu1.itb.read_hits 0 # DTB read hits 1308system.cpu1.itb.read_misses 0 # DTB read misses 1309system.cpu1.itb.write_hits 0 # DTB write hits 1310system.cpu1.itb.write_misses 0 # DTB write misses 1311system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1312system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1313system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1314system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1161system.cpu1.itb.flush_entries 882 # Number of entries that have been flushed from TLB | 1315system.cpu1.itb.flush_entries 1160 # Number of entries that have been flushed from TLB |
| 1162system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1163system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1164system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1316system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1317system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1318system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1165system.cpu1.itb.perms_faults 1128 # Number of TLB faults due to permissions restrictions | 1319system.cpu1.itb.perms_faults 1845 # Number of TLB faults due to permissions restrictions |
| 1166system.cpu1.itb.read_accesses 0 # DTB read accesses 1167system.cpu1.itb.write_accesses 0 # DTB write accesses | 1320system.cpu1.itb.read_accesses 0 # DTB read accesses 1321system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1168system.cpu1.itb.inst_accesses 6655735 # ITB inst accesses 1169system.cpu1.itb.hits 6653879 # DTB hits 1170system.cpu1.itb.misses 1856 # DTB misses 1171system.cpu1.itb.accesses 6655735 # DTB accesses 1172system.cpu1.numCycles 36145472 # number of cpu cycles simulated | 1322system.cpu1.itb.inst_accesses 7774294 # ITB inst accesses 1323system.cpu1.itb.hits 7772051 # DTB hits 1324system.cpu1.itb.misses 2243 # DTB misses 1325system.cpu1.itb.accesses 7774294 # DTB accesses 1326system.cpu1.numCycles 42246986 # number of cpu cycles simulated |
| 1173system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1174system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1327system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1328system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1175system.cpu1.committedInsts 13424165 # Number of instructions committed 1176system.cpu1.committedOps 16401555 # Number of ops (including micro ops) committed 1177system.cpu1.discardedOps 1287407 # Number of ops (including micro ops) which were discarded before commit 1178system.cpu1.numFetchSuspends 2767 # Number of times Execute suspended instruction fetching 1179system.cpu1.quiesceCycles 5652095397 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1180system.cpu1.cpi 2.692568 # CPI: cycles per instruction 1181system.cpu1.ipc 0.371393 # IPC: instructions per cycle | 1329system.cpu1.committedInsts 15956294 # Number of instructions committed 1330system.cpu1.committedOps 19510473 # Number of ops (including micro ops) committed 1331system.cpu1.discardedOps 1491389 # Number of ops (including micro ops) which were discarded before commit 1332system.cpu1.numFetchSuspends 2792 # Number of times Execute suspended instruction fetching 1333system.cpu1.quiesceCycles 5648821854 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1334system.cpu1.cpi 2.647669 # CPI: cycles per instruction 1335system.cpu1.ipc 0.377691 # IPC: instructions per cycle |
| 1182system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1336system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1183system.cpu1.kern.inst.quiesce 2770 # number of quiesce instructions executed 1184system.cpu1.tickCycles 26236459 # Number of cycles that the object actually ticked 1185system.cpu1.idleCycles 9909013 # Total number of cycles that the object has spent stopped 1186system.cpu1.dcache.tags.replacements 149765 # number of replacements 1187system.cpu1.dcache.tags.tagsinuse 476.829408 # Cycle average of tags in use 1188system.cpu1.dcache.tags.total_refs 5935391 # Total number of references to valid blocks. 1189system.cpu1.dcache.tags.sampled_refs 150124 # Sample count of references to valid blocks. 1190system.cpu1.dcache.tags.avg_refs 39.536590 # Average number of references to valid blocks. 1191system.cpu1.dcache.tags.warmup_cycle 107725830000 # Cycle when the warmup percentage was hit. 1192system.cpu1.dcache.tags.occ_blocks::cpu1.inst 476.829408 # Average occupied blocks per requestor 1193system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.931307 # Average percentage of cache occupancy 1194system.cpu1.dcache.tags.occ_percent::total 0.931307 # Average percentage of cache occupancy 1195system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id 1196system.cpu1.dcache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id 1197system.cpu1.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id 1198system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id 1199system.cpu1.dcache.tags.tag_accesses 12574886 # Number of tag accesses 1200system.cpu1.dcache.tags.data_accesses 12574886 # Number of data accesses 1201system.cpu1.dcache.ReadReq_hits::cpu1.inst 3167382 # number of ReadReq hits 1202system.cpu1.dcache.ReadReq_hits::total 3167382 # number of ReadReq hits 1203system.cpu1.dcache.WriteReq_hits::cpu1.inst 2587127 # number of WriteReq hits 1204system.cpu1.dcache.WriteReq_hits::total 2587127 # number of WriteReq hits 1205system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 79870 # number of LoadLockedReq hits 1206system.cpu1.dcache.LoadLockedReq_hits::total 79870 # number of LoadLockedReq hits 1207system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 60510 # number of StoreCondReq hits 1208system.cpu1.dcache.StoreCondReq_hits::total 60510 # number of StoreCondReq hits 1209system.cpu1.dcache.demand_hits::cpu1.inst 5754509 # number of demand (read+write) hits 1210system.cpu1.dcache.demand_hits::total 5754509 # number of demand (read+write) hits 1211system.cpu1.dcache.overall_hits::cpu1.inst 5754509 # number of overall hits 1212system.cpu1.dcache.overall_hits::total 5754509 # number of overall hits 1213system.cpu1.dcache.ReadReq_misses::cpu1.inst 151161 # number of ReadReq misses 1214system.cpu1.dcache.ReadReq_misses::total 151161 # number of ReadReq misses 1215system.cpu1.dcache.WriteReq_misses::cpu1.inst 116953 # number of WriteReq misses 1216system.cpu1.dcache.WriteReq_misses::total 116953 # number of WriteReq misses 1217system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5079 # number of LoadLockedReq misses 1218system.cpu1.dcache.LoadLockedReq_misses::total 5079 # number of LoadLockedReq misses 1219system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 22818 # number of StoreCondReq misses 1220system.cpu1.dcache.StoreCondReq_misses::total 22818 # number of StoreCondReq misses 1221system.cpu1.dcache.demand_misses::cpu1.inst 268114 # number of demand (read+write) misses 1222system.cpu1.dcache.demand_misses::total 268114 # number of demand (read+write) misses 1223system.cpu1.dcache.overall_misses::cpu1.inst 268114 # number of overall misses 1224system.cpu1.dcache.overall_misses::total 268114 # number of overall misses 1225system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2359046468 # number of ReadReq miss cycles 1226system.cpu1.dcache.ReadReq_miss_latency::total 2359046468 # number of ReadReq miss cycles 1227system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3063915205 # number of WriteReq miss cycles 1228system.cpu1.dcache.WriteReq_miss_latency::total 3063915205 # number of WriteReq miss cycles 1229system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 93260000 # number of LoadLockedReq miss cycles 1230system.cpu1.dcache.LoadLockedReq_miss_latency::total 93260000 # number of LoadLockedReq miss cycles 1231system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 534664798 # number of StoreCondReq miss cycles 1232system.cpu1.dcache.StoreCondReq_miss_latency::total 534664798 # number of StoreCondReq miss cycles 1233system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 106500 # number of StoreCondFailReq miss cycles 1234system.cpu1.dcache.StoreCondFailReq_miss_latency::total 106500 # number of StoreCondFailReq miss cycles 1235system.cpu1.dcache.demand_miss_latency::cpu1.inst 5422961673 # number of demand (read+write) miss cycles 1236system.cpu1.dcache.demand_miss_latency::total 5422961673 # number of demand (read+write) miss cycles 1237system.cpu1.dcache.overall_miss_latency::cpu1.inst 5422961673 # number of overall miss cycles 1238system.cpu1.dcache.overall_miss_latency::total 5422961673 # number of overall miss cycles 1239system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3318543 # number of ReadReq accesses(hits+misses) 1240system.cpu1.dcache.ReadReq_accesses::total 3318543 # number of ReadReq accesses(hits+misses) 1241system.cpu1.dcache.WriteReq_accesses::cpu1.inst 2704080 # number of WriteReq accesses(hits+misses) 1242system.cpu1.dcache.WriteReq_accesses::total 2704080 # number of WriteReq accesses(hits+misses) 1243system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 84949 # number of LoadLockedReq accesses(hits+misses) 1244system.cpu1.dcache.LoadLockedReq_accesses::total 84949 # number of LoadLockedReq accesses(hits+misses) 1245system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 83328 # number of StoreCondReq accesses(hits+misses) 1246system.cpu1.dcache.StoreCondReq_accesses::total 83328 # number of StoreCondReq accesses(hits+misses) 1247system.cpu1.dcache.demand_accesses::cpu1.inst 6022623 # number of demand (read+write) accesses 1248system.cpu1.dcache.demand_accesses::total 6022623 # number of demand (read+write) accesses 1249system.cpu1.dcache.overall_accesses::cpu1.inst 6022623 # number of overall (read+write) accesses 1250system.cpu1.dcache.overall_accesses::total 6022623 # number of overall (read+write) accesses 1251system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.045550 # miss rate for ReadReq accesses 1252system.cpu1.dcache.ReadReq_miss_rate::total 0.045550 # miss rate for ReadReq accesses 1253system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043251 # miss rate for WriteReq accesses 1254system.cpu1.dcache.WriteReq_miss_rate::total 0.043251 # miss rate for WriteReq accesses 1255system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.059789 # miss rate for LoadLockedReq accesses 1256system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.059789 # miss rate for LoadLockedReq accesses 1257system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.273834 # miss rate for StoreCondReq accesses 1258system.cpu1.dcache.StoreCondReq_miss_rate::total 0.273834 # miss rate for StoreCondReq accesses 1259system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044518 # miss rate for demand accesses 1260system.cpu1.dcache.demand_miss_rate::total 0.044518 # miss rate for demand accesses 1261system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044518 # miss rate for overall accesses 1262system.cpu1.dcache.overall_miss_rate::total 0.044518 # miss rate for overall accesses 1263system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15606.184585 # average ReadReq miss latency 1264system.cpu1.dcache.ReadReq_avg_miss_latency::total 15606.184585 # average ReadReq miss latency 1265system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 26197.833360 # average WriteReq miss latency 1266system.cpu1.dcache.WriteReq_avg_miss_latency::total 26197.833360 # average WriteReq miss latency 1267system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18361.882260 # average LoadLockedReq miss latency 1268system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18361.882260 # average LoadLockedReq miss latency 1269system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23431.711719 # average StoreCondReq miss latency 1270system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23431.711719 # average StoreCondReq miss latency | 1337system.cpu1.kern.inst.quiesce 2795 # number of quiesce instructions executed 1338system.cpu1.tickCycles 30354295 # Number of cycles that the object actually ticked 1339system.cpu1.idleCycles 11892691 # Total number of cycles that the object has spent stopped 1340system.cpu1.dcache.tags.replacements 187758 # number of replacements 1341system.cpu1.dcache.tags.tagsinuse 478.493571 # Cycle average of tags in use 1342system.cpu1.dcache.tags.total_refs 7034054 # Total number of references to valid blocks. 1343system.cpu1.dcache.tags.sampled_refs 188124 # Sample count of references to valid blocks. 1344system.cpu1.dcache.tags.avg_refs 37.390519 # Average number of references to valid blocks. 1345system.cpu1.dcache.tags.warmup_cycle 108317904000 # Cycle when the warmup percentage was hit. 1346system.cpu1.dcache.tags.occ_blocks::cpu1.inst 478.493571 # Average occupied blocks per requestor 1347system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.934558 # Average percentage of cache occupancy 1348system.cpu1.dcache.tags.occ_percent::total 0.934558 # Average percentage of cache occupancy 1349system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id 1350system.cpu1.dcache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id 1351system.cpu1.dcache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id 1352system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id 1353system.cpu1.dcache.tags.tag_accesses 14914460 # Number of tag accesses 1354system.cpu1.dcache.tags.data_accesses 14914460 # Number of data accesses 1355system.cpu1.dcache.ReadReq_hits::cpu1.inst 3762812 # number of ReadReq hits 1356system.cpu1.dcache.ReadReq_hits::total 3762812 # number of ReadReq hits 1357system.cpu1.dcache.WriteReq_hits::cpu1.inst 3070723 # number of WriteReq hits 1358system.cpu1.dcache.WriteReq_hits::total 3070723 # number of WriteReq hits 1359system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 89288 # number of LoadLockedReq hits 1360system.cpu1.dcache.LoadLockedReq_hits::total 89288 # number of LoadLockedReq hits 1361system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 69262 # number of StoreCondReq hits 1362system.cpu1.dcache.StoreCondReq_hits::total 69262 # number of StoreCondReq hits 1363system.cpu1.dcache.demand_hits::cpu1.inst 6833535 # number of demand (read+write) hits 1364system.cpu1.dcache.demand_hits::total 6833535 # number of demand (read+write) hits 1365system.cpu1.dcache.overall_hits::cpu1.inst 6833535 # number of overall hits 1366system.cpu1.dcache.overall_hits::total 6833535 # number of overall hits 1367system.cpu1.dcache.ReadReq_misses::cpu1.inst 181434 # number of ReadReq misses 1368system.cpu1.dcache.ReadReq_misses::total 181434 # number of ReadReq misses 1369system.cpu1.dcache.WriteReq_misses::cpu1.inst 139542 # number of WriteReq misses 1370system.cpu1.dcache.WriteReq_misses::total 139542 # number of WriteReq misses 1371system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5058 # number of LoadLockedReq misses 1372system.cpu1.dcache.LoadLockedReq_misses::total 5058 # number of LoadLockedReq misses 1373system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23425 # number of StoreCondReq misses 1374system.cpu1.dcache.StoreCondReq_misses::total 23425 # number of StoreCondReq misses 1375system.cpu1.dcache.demand_misses::cpu1.inst 320976 # number of demand (read+write) misses 1376system.cpu1.dcache.demand_misses::total 320976 # number of demand (read+write) misses 1377system.cpu1.dcache.overall_misses::cpu1.inst 320976 # number of overall misses 1378system.cpu1.dcache.overall_misses::total 320976 # number of overall misses 1379system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2698134351 # number of ReadReq miss cycles 1380system.cpu1.dcache.ReadReq_miss_latency::total 2698134351 # number of ReadReq miss cycles 1381system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3673411367 # number of WriteReq miss cycles 1382system.cpu1.dcache.WriteReq_miss_latency::total 3673411367 # number of WriteReq miss cycles 1383system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 91654251 # number of LoadLockedReq miss cycles 1384system.cpu1.dcache.LoadLockedReq_miss_latency::total 91654251 # number of LoadLockedReq miss cycles 1385system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 540931813 # number of StoreCondReq miss cycles 1386system.cpu1.dcache.StoreCondReq_miss_latency::total 540931813 # number of StoreCondReq miss cycles 1387system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 185500 # number of StoreCondFailReq miss cycles 1388system.cpu1.dcache.StoreCondFailReq_miss_latency::total 185500 # number of StoreCondFailReq miss cycles 1389system.cpu1.dcache.demand_miss_latency::cpu1.inst 6371545718 # number of demand (read+write) miss cycles 1390system.cpu1.dcache.demand_miss_latency::total 6371545718 # number of demand (read+write) miss cycles 1391system.cpu1.dcache.overall_miss_latency::cpu1.inst 6371545718 # number of overall miss cycles 1392system.cpu1.dcache.overall_miss_latency::total 6371545718 # number of overall miss cycles 1393system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3944246 # number of ReadReq accesses(hits+misses) 1394system.cpu1.dcache.ReadReq_accesses::total 3944246 # number of ReadReq accesses(hits+misses) 1395system.cpu1.dcache.WriteReq_accesses::cpu1.inst 3210265 # number of WriteReq accesses(hits+misses) 1396system.cpu1.dcache.WriteReq_accesses::total 3210265 # number of WriteReq accesses(hits+misses) 1397system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 94346 # number of LoadLockedReq accesses(hits+misses) 1398system.cpu1.dcache.LoadLockedReq_accesses::total 94346 # number of LoadLockedReq accesses(hits+misses) 1399system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 92687 # number of StoreCondReq accesses(hits+misses) 1400system.cpu1.dcache.StoreCondReq_accesses::total 92687 # number of StoreCondReq accesses(hits+misses) 1401system.cpu1.dcache.demand_accesses::cpu1.inst 7154511 # number of demand (read+write) accesses 1402system.cpu1.dcache.demand_accesses::total 7154511 # number of demand (read+write) accesses 1403system.cpu1.dcache.overall_accesses::cpu1.inst 7154511 # number of overall (read+write) accesses 1404system.cpu1.dcache.overall_accesses::total 7154511 # number of overall (read+write) accesses 1405system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046000 # miss rate for ReadReq accesses 1406system.cpu1.dcache.ReadReq_miss_rate::total 0.046000 # miss rate for ReadReq accesses 1407system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043467 # miss rate for WriteReq accesses 1408system.cpu1.dcache.WriteReq_miss_rate::total 0.043467 # miss rate for WriteReq accesses 1409system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.053611 # miss rate for LoadLockedReq accesses 1410system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.053611 # miss rate for LoadLockedReq accesses 1411system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.252732 # miss rate for StoreCondReq accesses 1412system.cpu1.dcache.StoreCondReq_miss_rate::total 0.252732 # miss rate for StoreCondReq accesses 1413system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044863 # miss rate for demand accesses 1414system.cpu1.dcache.demand_miss_rate::total 0.044863 # miss rate for demand accesses 1415system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044863 # miss rate for overall accesses 1416system.cpu1.dcache.overall_miss_rate::total 0.044863 # miss rate for overall accesses 1417system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14871.161695 # average ReadReq miss latency 1418system.cpu1.dcache.ReadReq_avg_miss_latency::total 14871.161695 # average ReadReq miss latency 1419system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 26324.772233 # average WriteReq miss latency 1420system.cpu1.dcache.WriteReq_avg_miss_latency::total 26324.772233 # average WriteReq miss latency 1421system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18120.650652 # average LoadLockedReq miss latency 1422system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18120.650652 # average LoadLockedReq miss latency 1423system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23092.073127 # average StoreCondReq miss latency 1424system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23092.073127 # average StoreCondReq miss latency |
| 1271system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency 1272system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 1425system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency 1426system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1273system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 20226.327879 # average overall miss latency 1274system.cpu1.dcache.demand_avg_miss_latency::total 20226.327879 # average overall miss latency 1275system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 20226.327879 # average overall miss latency 1276system.cpu1.dcache.overall_avg_miss_latency::total 20226.327879 # average overall miss latency | 1427system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 19850.536233 # average overall miss latency 1428system.cpu1.dcache.demand_avg_miss_latency::total 19850.536233 # average overall miss latency 1429system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 19850.536233 # average overall miss latency 1430system.cpu1.dcache.overall_avg_miss_latency::total 19850.536233 # average overall miss latency |
| 1277system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1278system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1279system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1280system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1281system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1282system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1283system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1284system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1431system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1432system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1433system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1434system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1435system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1436system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1437system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1438system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1285system.cpu1.dcache.writebacks::writebacks 93707 # number of writebacks 1286system.cpu1.dcache.writebacks::total 93707 # number of writebacks 1287system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 11593 # number of ReadReq MSHR hits 1288system.cpu1.dcache.ReadReq_mshr_hits::total 11593 # number of ReadReq MSHR hits 1289system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 39187 # number of WriteReq MSHR hits 1290system.cpu1.dcache.WriteReq_mshr_hits::total 39187 # number of WriteReq MSHR hits 1291system.cpu1.dcache.demand_mshr_hits::cpu1.inst 50780 # number of demand (read+write) MSHR hits 1292system.cpu1.dcache.demand_mshr_hits::total 50780 # number of demand (read+write) MSHR hits 1293system.cpu1.dcache.overall_mshr_hits::cpu1.inst 50780 # number of overall MSHR hits 1294system.cpu1.dcache.overall_mshr_hits::total 50780 # number of overall MSHR hits 1295system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 139568 # number of ReadReq MSHR misses 1296system.cpu1.dcache.ReadReq_mshr_misses::total 139568 # number of ReadReq MSHR misses 1297system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 77766 # number of WriteReq MSHR misses 1298system.cpu1.dcache.WriteReq_mshr_misses::total 77766 # number of WriteReq MSHR misses 1299system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5079 # number of LoadLockedReq MSHR misses 1300system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5079 # number of LoadLockedReq MSHR misses 1301system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 22818 # number of StoreCondReq MSHR misses 1302system.cpu1.dcache.StoreCondReq_mshr_misses::total 22818 # number of StoreCondReq MSHR misses 1303system.cpu1.dcache.demand_mshr_misses::cpu1.inst 217334 # number of demand (read+write) MSHR misses 1304system.cpu1.dcache.demand_mshr_misses::total 217334 # number of demand (read+write) MSHR misses 1305system.cpu1.dcache.overall_mshr_misses::cpu1.inst 217334 # number of overall MSHR misses 1306system.cpu1.dcache.overall_mshr_misses::total 217334 # number of overall MSHR misses 1307system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 1914681986 # number of ReadReq MSHR miss cycles 1308system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1914681986 # number of ReadReq MSHR miss cycles 1309system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 1867013423 # number of WriteReq MSHR miss cycles 1310system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1867013423 # number of WriteReq MSHR miss cycles 1311system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 83091000 # number of LoadLockedReq MSHR miss cycles 1312system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83091000 # number of LoadLockedReq MSHR miss cycles 1313system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 487833202 # number of StoreCondReq MSHR miss cycles 1314system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 487833202 # number of StoreCondReq MSHR miss cycles 1315system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 100500 # number of StoreCondFailReq MSHR miss cycles 1316system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 100500 # number of StoreCondFailReq MSHR miss cycles 1317system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 3781695409 # number of demand (read+write) MSHR miss cycles 1318system.cpu1.dcache.demand_mshr_miss_latency::total 3781695409 # number of demand (read+write) MSHR miss cycles 1319system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 3781695409 # number of overall MSHR miss cycles 1320system.cpu1.dcache.overall_mshr_miss_latency::total 3781695409 # number of overall MSHR miss cycles 1321system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 327471996 # number of ReadReq MSHR uncacheable cycles 1322system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 327471996 # number of ReadReq MSHR uncacheable cycles 1323system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 198424999 # number of WriteReq MSHR uncacheable cycles 1324system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 198424999 # number of WriteReq MSHR uncacheable cycles 1325system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 525896995 # number of overall MSHR uncacheable cycles 1326system.cpu1.dcache.overall_mshr_uncacheable_latency::total 525896995 # number of overall MSHR uncacheable cycles 1327system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042057 # mshr miss rate for ReadReq accesses 1328system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042057 # mshr miss rate for ReadReq accesses 1329system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.028759 # mshr miss rate for WriteReq accesses 1330system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028759 # mshr miss rate for WriteReq accesses 1331system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.059789 # mshr miss rate for LoadLockedReq accesses 1332system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.059789 # mshr miss rate for LoadLockedReq accesses 1333system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.273834 # mshr miss rate for StoreCondReq accesses 1334system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.273834 # mshr miss rate for StoreCondReq accesses 1335system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.036086 # mshr miss rate for demand accesses 1336system.cpu1.dcache.demand_mshr_miss_rate::total 0.036086 # mshr miss rate for demand accesses 1337system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.036086 # mshr miss rate for overall accesses 1338system.cpu1.dcache.overall_mshr_miss_rate::total 0.036086 # mshr miss rate for overall accesses 1339system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13718.631678 # average ReadReq mshr miss latency 1340system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13718.631678 # average ReadReq mshr miss latency 1341system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 24008.093807 # average WriteReq mshr miss latency 1342system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24008.093807 # average WriteReq mshr miss latency 1343system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16359.716480 # average LoadLockedReq mshr miss latency 1344system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16359.716480 # average LoadLockedReq mshr miss latency 1345system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21379.314664 # average StoreCondReq mshr miss latency 1346system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21379.314664 # average StoreCondReq mshr miss latency | 1439system.cpu1.dcache.writebacks::writebacks 113901 # number of writebacks 1440system.cpu1.dcache.writebacks::total 113901 # number of writebacks 1441system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15137 # number of ReadReq MSHR hits 1442system.cpu1.dcache.ReadReq_mshr_hits::total 15137 # number of ReadReq MSHR hits 1443system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 49794 # number of WriteReq MSHR hits 1444system.cpu1.dcache.WriteReq_mshr_hits::total 49794 # number of WriteReq MSHR hits 1445system.cpu1.dcache.demand_mshr_hits::cpu1.inst 64931 # number of demand (read+write) MSHR hits 1446system.cpu1.dcache.demand_mshr_hits::total 64931 # number of demand (read+write) MSHR hits 1447system.cpu1.dcache.overall_mshr_hits::cpu1.inst 64931 # number of overall MSHR hits 1448system.cpu1.dcache.overall_mshr_hits::total 64931 # number of overall MSHR hits 1449system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 166297 # number of ReadReq MSHR misses 1450system.cpu1.dcache.ReadReq_mshr_misses::total 166297 # number of ReadReq MSHR misses 1451system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 89748 # number of WriteReq MSHR misses 1452system.cpu1.dcache.WriteReq_mshr_misses::total 89748 # number of WriteReq MSHR misses 1453system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5058 # number of LoadLockedReq MSHR misses 1454system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5058 # number of LoadLockedReq MSHR misses 1455system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23425 # number of StoreCondReq MSHR misses 1456system.cpu1.dcache.StoreCondReq_mshr_misses::total 23425 # number of StoreCondReq MSHR misses 1457system.cpu1.dcache.demand_mshr_misses::cpu1.inst 256045 # number of demand (read+write) MSHR misses 1458system.cpu1.dcache.demand_mshr_misses::total 256045 # number of demand (read+write) MSHR misses 1459system.cpu1.dcache.overall_mshr_misses::cpu1.inst 256045 # number of overall MSHR misses 1460system.cpu1.dcache.overall_mshr_misses::total 256045 # number of overall MSHR misses 1461system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2162409829 # number of ReadReq MSHR miss cycles 1462system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2162409829 # number of ReadReq MSHR miss cycles 1463system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2163633710 # number of WriteReq MSHR miss cycles 1464system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2163633710 # number of WriteReq MSHR miss cycles 1465system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 81526749 # number of LoadLockedReq MSHR miss cycles 1466system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 81526749 # number of LoadLockedReq MSHR miss cycles 1467system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 492905187 # number of StoreCondReq MSHR miss cycles 1468system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 492905187 # number of StoreCondReq MSHR miss cycles 1469system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 177500 # number of StoreCondFailReq MSHR miss cycles 1470system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 177500 # number of StoreCondFailReq MSHR miss cycles 1471system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4326043539 # number of demand (read+write) MSHR miss cycles 1472system.cpu1.dcache.demand_mshr_miss_latency::total 4326043539 # number of demand (read+write) MSHR miss cycles 1473system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4326043539 # number of overall MSHR miss cycles 1474system.cpu1.dcache.overall_mshr_miss_latency::total 4326043539 # number of overall MSHR miss cycles 1475system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 330271000 # number of ReadReq MSHR uncacheable cycles 1476system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 330271000 # number of ReadReq MSHR uncacheable cycles 1477system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 203208500 # number of WriteReq MSHR uncacheable cycles 1478system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 203208500 # number of WriteReq MSHR uncacheable cycles 1479system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 533479500 # number of overall MSHR uncacheable cycles 1480system.cpu1.dcache.overall_mshr_uncacheable_latency::total 533479500 # number of overall MSHR uncacheable cycles 1481system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042162 # mshr miss rate for ReadReq accesses 1482system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042162 # mshr miss rate for ReadReq accesses 1483system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027957 # mshr miss rate for WriteReq accesses 1484system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027957 # mshr miss rate for WriteReq accesses 1485system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.053611 # mshr miss rate for LoadLockedReq accesses 1486system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053611 # mshr miss rate for LoadLockedReq accesses 1487system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.252732 # mshr miss rate for StoreCondReq accesses 1488system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.252732 # mshr miss rate for StoreCondReq accesses 1489system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.035788 # mshr miss rate for demand accesses 1490system.cpu1.dcache.demand_mshr_miss_rate::total 0.035788 # mshr miss rate for demand accesses 1491system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.035788 # mshr miss rate for overall accesses 1492system.cpu1.dcache.overall_mshr_miss_rate::total 0.035788 # mshr miss rate for overall accesses 1493system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13003.300294 # average ReadReq mshr miss latency 1494system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13003.300294 # average ReadReq mshr miss latency 1495system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 24107.876610 # average WriteReq mshr miss latency 1496system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24107.876610 # average WriteReq mshr miss latency 1497system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16118.376631 # average LoadLockedReq mshr miss latency 1498system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16118.376631 # average LoadLockedReq mshr miss latency 1499system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21041.843629 # average StoreCondReq mshr miss latency 1500system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21041.843629 # average StoreCondReq mshr miss latency |
| 1347system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency 1348system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1501system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency 1502system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1349system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 17400.385623 # average overall mshr miss latency 1350system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17400.385623 # average overall mshr miss latency 1351system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 17400.385623 # average overall mshr miss latency 1352system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17400.385623 # average overall mshr miss latency | 1503system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16895.637638 # average overall mshr miss latency 1504system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16895.637638 # average overall mshr miss latency 1505system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16895.637638 # average overall mshr miss latency 1506system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16895.637638 # average overall mshr miss latency |
| 1353system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1354system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1355system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 1356system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1357system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1358system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1359system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1507system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1508system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1509system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 1510system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1511system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1512system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1513system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1360system.cpu1.icache.tags.replacements 827152 # number of replacements 1361system.cpu1.icache.tags.tagsinuse 499.447245 # Cycle average of tags in use 1362system.cpu1.icache.tags.total_refs 5824947 # Total number of references to valid blocks. 1363system.cpu1.icache.tags.sampled_refs 827664 # Sample count of references to valid blocks. 1364system.cpu1.icache.tags.avg_refs 7.037816 # Average number of references to valid blocks. 1365system.cpu1.icache.tags.warmup_cycle 71343314500 # Cycle when the warmup percentage was hit. 1366system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.447245 # Average occupied blocks per requestor 1367system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975483 # Average percentage of cache occupancy 1368system.cpu1.icache.tags.occ_percent::total 0.975483 # Average percentage of cache occupancy | 1514system.cpu1.icache.tags.replacements 908016 # number of replacements 1515system.cpu1.icache.tags.tagsinuse 499.415703 # Cycle average of tags in use 1516system.cpu1.icache.tags.total_refs 6861520 # Total number of references to valid blocks. 1517system.cpu1.icache.tags.sampled_refs 908528 # Sample count of references to valid blocks. 1518system.cpu1.icache.tags.avg_refs 7.552348 # Average number of references to valid blocks. 1519system.cpu1.icache.tags.warmup_cycle 71602668000 # Cycle when the warmup percentage was hit. 1520system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.415703 # Average occupied blocks per requestor 1521system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975421 # Average percentage of cache occupancy 1522system.cpu1.icache.tags.occ_percent::total 0.975421 # Average percentage of cache occupancy |
| 1369system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1523system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1370system.cpu1.icache.tags.age_task_id_blocks_1024::2 469 # Occupied blocks per task id 1371system.cpu1.icache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id 1372system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id | 1524system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id 1525system.cpu1.icache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id |
| 1373system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1526system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1374system.cpu1.icache.tags.tag_accesses 14132886 # Number of tag accesses 1375system.cpu1.icache.tags.data_accesses 14132886 # Number of data accesses 1376system.cpu1.icache.ReadReq_hits::cpu1.inst 5824947 # number of ReadReq hits 1377system.cpu1.icache.ReadReq_hits::total 5824947 # number of ReadReq hits 1378system.cpu1.icache.demand_hits::cpu1.inst 5824947 # number of demand (read+write) hits 1379system.cpu1.icache.demand_hits::total 5824947 # number of demand (read+write) hits 1380system.cpu1.icache.overall_hits::cpu1.inst 5824947 # number of overall hits 1381system.cpu1.icache.overall_hits::total 5824947 # number of overall hits 1382system.cpu1.icache.ReadReq_misses::cpu1.inst 827664 # number of ReadReq misses 1383system.cpu1.icache.ReadReq_misses::total 827664 # number of ReadReq misses 1384system.cpu1.icache.demand_misses::cpu1.inst 827664 # number of demand (read+write) misses 1385system.cpu1.icache.demand_misses::total 827664 # number of demand (read+write) misses 1386system.cpu1.icache.overall_misses::cpu1.inst 827664 # number of overall misses 1387system.cpu1.icache.overall_misses::total 827664 # number of overall misses 1388system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6712177482 # number of ReadReq miss cycles 1389system.cpu1.icache.ReadReq_miss_latency::total 6712177482 # number of ReadReq miss cycles 1390system.cpu1.icache.demand_miss_latency::cpu1.inst 6712177482 # number of demand (read+write) miss cycles 1391system.cpu1.icache.demand_miss_latency::total 6712177482 # number of demand (read+write) miss cycles 1392system.cpu1.icache.overall_miss_latency::cpu1.inst 6712177482 # number of overall miss cycles 1393system.cpu1.icache.overall_miss_latency::total 6712177482 # number of overall miss cycles 1394system.cpu1.icache.ReadReq_accesses::cpu1.inst 6652611 # number of ReadReq accesses(hits+misses) 1395system.cpu1.icache.ReadReq_accesses::total 6652611 # number of ReadReq accesses(hits+misses) 1396system.cpu1.icache.demand_accesses::cpu1.inst 6652611 # number of demand (read+write) accesses 1397system.cpu1.icache.demand_accesses::total 6652611 # number of demand (read+write) accesses 1398system.cpu1.icache.overall_accesses::cpu1.inst 6652611 # number of overall (read+write) accesses 1399system.cpu1.icache.overall_accesses::total 6652611 # number of overall (read+write) accesses 1400system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.124412 # miss rate for ReadReq accesses 1401system.cpu1.icache.ReadReq_miss_rate::total 0.124412 # miss rate for ReadReq accesses 1402system.cpu1.icache.demand_miss_rate::cpu1.inst 0.124412 # miss rate for demand accesses 1403system.cpu1.icache.demand_miss_rate::total 0.124412 # miss rate for demand accesses 1404system.cpu1.icache.overall_miss_rate::cpu1.inst 0.124412 # miss rate for overall accesses 1405system.cpu1.icache.overall_miss_rate::total 0.124412 # miss rate for overall accesses 1406system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8109.785471 # average ReadReq miss latency 1407system.cpu1.icache.ReadReq_avg_miss_latency::total 8109.785471 # average ReadReq miss latency 1408system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8109.785471 # average overall miss latency 1409system.cpu1.icache.demand_avg_miss_latency::total 8109.785471 # average overall miss latency 1410system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8109.785471 # average overall miss latency 1411system.cpu1.icache.overall_avg_miss_latency::total 8109.785471 # average overall miss latency | 1527system.cpu1.icache.tags.tag_accesses 16448624 # Number of tag accesses 1528system.cpu1.icache.tags.data_accesses 16448624 # Number of data accesses 1529system.cpu1.icache.ReadReq_hits::cpu1.inst 6861520 # number of ReadReq hits 1530system.cpu1.icache.ReadReq_hits::total 6861520 # number of ReadReq hits 1531system.cpu1.icache.demand_hits::cpu1.inst 6861520 # number of demand (read+write) hits 1532system.cpu1.icache.demand_hits::total 6861520 # number of demand (read+write) hits 1533system.cpu1.icache.overall_hits::cpu1.inst 6861520 # number of overall hits 1534system.cpu1.icache.overall_hits::total 6861520 # number of overall hits 1535system.cpu1.icache.ReadReq_misses::cpu1.inst 908528 # number of ReadReq misses 1536system.cpu1.icache.ReadReq_misses::total 908528 # number of ReadReq misses 1537system.cpu1.icache.demand_misses::cpu1.inst 908528 # number of demand (read+write) misses 1538system.cpu1.icache.demand_misses::total 908528 # number of demand (read+write) misses 1539system.cpu1.icache.overall_misses::cpu1.inst 908528 # number of overall misses 1540system.cpu1.icache.overall_misses::total 908528 # number of overall misses 1541system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7748571238 # number of ReadReq miss cycles 1542system.cpu1.icache.ReadReq_miss_latency::total 7748571238 # number of ReadReq miss cycles 1543system.cpu1.icache.demand_miss_latency::cpu1.inst 7748571238 # number of demand (read+write) miss cycles 1544system.cpu1.icache.demand_miss_latency::total 7748571238 # number of demand (read+write) miss cycles 1545system.cpu1.icache.overall_miss_latency::cpu1.inst 7748571238 # number of overall miss cycles 1546system.cpu1.icache.overall_miss_latency::total 7748571238 # number of overall miss cycles 1547system.cpu1.icache.ReadReq_accesses::cpu1.inst 7770048 # number of ReadReq accesses(hits+misses) 1548system.cpu1.icache.ReadReq_accesses::total 7770048 # number of ReadReq accesses(hits+misses) 1549system.cpu1.icache.demand_accesses::cpu1.inst 7770048 # number of demand (read+write) accesses 1550system.cpu1.icache.demand_accesses::total 7770048 # number of demand (read+write) accesses 1551system.cpu1.icache.overall_accesses::cpu1.inst 7770048 # number of overall (read+write) accesses 1552system.cpu1.icache.overall_accesses::total 7770048 # number of overall (read+write) accesses 1553system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.116927 # miss rate for ReadReq accesses 1554system.cpu1.icache.ReadReq_miss_rate::total 0.116927 # miss rate for ReadReq accesses 1555system.cpu1.icache.demand_miss_rate::cpu1.inst 0.116927 # miss rate for demand accesses 1556system.cpu1.icache.demand_miss_rate::total 0.116927 # miss rate for demand accesses 1557system.cpu1.icache.overall_miss_rate::cpu1.inst 0.116927 # miss rate for overall accesses 1558system.cpu1.icache.overall_miss_rate::total 0.116927 # miss rate for overall accesses 1559system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8528.709339 # average ReadReq miss latency 1560system.cpu1.icache.ReadReq_avg_miss_latency::total 8528.709339 # average ReadReq miss latency 1561system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8528.709339 # average overall miss latency 1562system.cpu1.icache.demand_avg_miss_latency::total 8528.709339 # average overall miss latency 1563system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8528.709339 # average overall miss latency 1564system.cpu1.icache.overall_avg_miss_latency::total 8528.709339 # average overall miss latency |
| 1412system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1413system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1414system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1415system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1416system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1417system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1418system.cpu1.icache.fast_writes 0 # number of fast writes performed 1419system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1565system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1566system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1567system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1568system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1569system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1570system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1571system.cpu1.icache.fast_writes 0 # number of fast writes performed 1572system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1420system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 827664 # number of ReadReq MSHR misses 1421system.cpu1.icache.ReadReq_mshr_misses::total 827664 # number of ReadReq MSHR misses 1422system.cpu1.icache.demand_mshr_misses::cpu1.inst 827664 # number of demand (read+write) MSHR misses 1423system.cpu1.icache.demand_mshr_misses::total 827664 # number of demand (read+write) MSHR misses 1424system.cpu1.icache.overall_mshr_misses::cpu1.inst 827664 # number of overall MSHR misses 1425system.cpu1.icache.overall_mshr_misses::total 827664 # number of overall MSHR misses 1426system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5467532518 # number of ReadReq MSHR miss cycles 1427system.cpu1.icache.ReadReq_mshr_miss_latency::total 5467532518 # number of ReadReq MSHR miss cycles 1428system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5467532518 # number of demand (read+write) MSHR miss cycles 1429system.cpu1.icache.demand_mshr_miss_latency::total 5467532518 # number of demand (read+write) MSHR miss cycles 1430system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5467532518 # number of overall MSHR miss cycles 1431system.cpu1.icache.overall_mshr_miss_latency::total 5467532518 # number of overall MSHR miss cycles 1432system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10038000 # number of ReadReq MSHR uncacheable cycles 1433system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10038000 # number of ReadReq MSHR uncacheable cycles 1434system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10038000 # number of overall MSHR uncacheable cycles 1435system.cpu1.icache.overall_mshr_uncacheable_latency::total 10038000 # number of overall MSHR uncacheable cycles 1436system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for ReadReq accesses 1437system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.124412 # mshr miss rate for ReadReq accesses 1438system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for demand accesses 1439system.cpu1.icache.demand_mshr_miss_rate::total 0.124412 # mshr miss rate for demand accesses 1440system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for overall accesses 1441system.cpu1.icache.overall_mshr_miss_rate::total 0.124412 # mshr miss rate for overall accesses 1442system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average ReadReq mshr miss latency 1443system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6605.980830 # average ReadReq mshr miss latency 1444system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average overall mshr miss latency 1445system.cpu1.icache.demand_avg_mshr_miss_latency::total 6605.980830 # average overall mshr miss latency 1446system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average overall mshr miss latency 1447system.cpu1.icache.overall_avg_mshr_miss_latency::total 6605.980830 # average overall mshr miss latency | 1573system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 908528 # number of ReadReq MSHR misses 1574system.cpu1.icache.ReadReq_mshr_misses::total 908528 # number of ReadReq MSHR misses 1575system.cpu1.icache.demand_mshr_misses::cpu1.inst 908528 # number of demand (read+write) MSHR misses 1576system.cpu1.icache.demand_mshr_misses::total 908528 # number of demand (read+write) MSHR misses 1577system.cpu1.icache.overall_mshr_misses::cpu1.inst 908528 # number of overall MSHR misses 1578system.cpu1.icache.overall_mshr_misses::total 908528 # number of overall MSHR misses 1579system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6381932762 # number of ReadReq MSHR miss cycles 1580system.cpu1.icache.ReadReq_mshr_miss_latency::total 6381932762 # number of ReadReq MSHR miss cycles 1581system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6381932762 # number of demand (read+write) MSHR miss cycles 1582system.cpu1.icache.demand_mshr_miss_latency::total 6381932762 # number of demand (read+write) MSHR miss cycles 1583system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6381932762 # number of overall MSHR miss cycles 1584system.cpu1.icache.overall_mshr_miss_latency::total 6381932762 # number of overall MSHR miss cycles 1585system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10331250 # number of ReadReq MSHR uncacheable cycles 1586system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10331250 # number of ReadReq MSHR uncacheable cycles 1587system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10331250 # number of overall MSHR uncacheable cycles 1588system.cpu1.icache.overall_mshr_uncacheable_latency::total 10331250 # number of overall MSHR uncacheable cycles 1589system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.116927 # mshr miss rate for ReadReq accesses 1590system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.116927 # mshr miss rate for ReadReq accesses 1591system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.116927 # mshr miss rate for demand accesses 1592system.cpu1.icache.demand_mshr_miss_rate::total 0.116927 # mshr miss rate for demand accesses 1593system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.116927 # mshr miss rate for overall accesses 1594system.cpu1.icache.overall_mshr_miss_rate::total 0.116927 # mshr miss rate for overall accesses 1595system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7024.475593 # average ReadReq mshr miss latency 1596system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7024.475593 # average ReadReq mshr miss latency 1597system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7024.475593 # average overall mshr miss latency 1598system.cpu1.icache.demand_avg_mshr_miss_latency::total 7024.475593 # average overall mshr miss latency 1599system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7024.475593 # average overall mshr miss latency 1600system.cpu1.icache.overall_avg_mshr_miss_latency::total 7024.475593 # average overall mshr miss latency |
| 1448system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1449system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1450system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1451system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1452system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1601system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1602system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1603system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1604system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1605system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1453system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 6453687 # number of hwpf identified 1454system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 29592 # number of hwpf that were already in mshr 1455system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6340817 # number of hwpf that were already in the cache 1456system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 898 # number of hwpf that were already in the prefetch queue 1457system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 1458system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2376 # number of hwpf removed because MSHR allocated 1459system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 80004 # number of hwpf issued 1460system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 668025 # number of hwpf spanning a virtual page 1461system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 1462system.cpu1.l2cache.tags.replacements 52740 # number of replacements 1463system.cpu1.l2cache.tags.tagsinuse 15520.178150 # Cycle average of tags in use 1464system.cpu1.l2cache.tags.total_refs 1029232 # Total number of references to valid blocks. 1465system.cpu1.l2cache.tags.sampled_refs 68128 # Sample count of references to valid blocks. 1466system.cpu1.l2cache.tags.avg_refs 15.107327 # Average number of references to valid blocks. | 1606system.cpu1.l2cache.prefetcher.num_hwpf_issued 255012 # number of hwpf issued 1607system.cpu1.l2cache.prefetcher.pfIdentified 255045 # number of prefetch candidates identified 1608system.cpu1.l2cache.prefetcher.pfBufferHit 26 # number of redundant prefetches already in prefetch queue 1609system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1610system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1611system.cpu1.l2cache.prefetcher.pfSpanPage 67427 # number of prefetches not generated due to page crossing 1612system.cpu1.l2cache.tags.replacements 54264 # number of replacements 1613system.cpu1.l2cache.tags.tagsinuse 15327.785502 # Cycle average of tags in use 1614system.cpu1.l2cache.tags.total_refs 1131516 # Total number of references to valid blocks. 1615system.cpu1.l2cache.tags.sampled_refs 69292 # Sample count of references to valid blocks. 1616system.cpu1.l2cache.tags.avg_refs 16.329677 # Average number of references to valid blocks. |
| 1467system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1617system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1468system.cpu1.l2cache.tags.occ_blocks::writebacks 6901.586978 # Average occupied blocks per requestor 1469system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 27.255538 # Average occupied blocks per requestor 1470system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.084140 # Average occupied blocks per requestor 1471system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2337.993929 # Average occupied blocks per requestor 1472system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6253.257565 # Average occupied blocks per requestor 1473system.cpu1.l2cache.tags.occ_percent::writebacks 0.421239 # Average percentage of cache occupancy 1474system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001664 # Average percentage of cache occupancy 1475system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000005 # Average percentage of cache occupancy 1476system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.142700 # Average percentage of cache occupancy 1477system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.381669 # Average percentage of cache occupancy 1478system.cpu1.l2cache.tags.occ_percent::total 0.947276 # Average percentage of cache occupancy 1479system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8859 # Occupied blocks per task id 1480system.cpu1.l2cache.tags.occ_task_id_blocks::1023 87 # Occupied blocks per task id 1481system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6442 # Occupied blocks per task id 1482system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 153 # Occupied blocks per task id 1483system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1624 # Occupied blocks per task id 1484system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 7082 # Occupied blocks per task id 1485system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 18 # Occupied blocks per task id | 1618system.cpu1.l2cache.tags.occ_blocks::writebacks 8763.818423 # Average occupied blocks per requestor 1619system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 26.824644 # Average occupied blocks per requestor 1620system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.109281 # Average occupied blocks per requestor 1621system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5323.780218 # Average occupied blocks per requestor 1622system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1213.252936 # Average occupied blocks per requestor 1623system.cpu1.l2cache.tags.occ_percent::writebacks 0.534901 # Average percentage of cache occupancy 1624system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001637 # Average percentage of cache occupancy 1625system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000007 # Average percentage of cache occupancy 1626system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.324938 # Average percentage of cache occupancy 1627system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.074051 # Average percentage of cache occupancy 1628system.cpu1.l2cache.tags.occ_percent::total 0.935534 # Average percentage of cache occupancy 1629system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2056 # Occupied blocks per task id 1630system.cpu1.l2cache.tags.occ_task_id_blocks::1023 45 # Occupied blocks per task id 1631system.cpu1.l2cache.tags.occ_task_id_blocks::1024 12927 # Occupied blocks per task id 1632system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 84 # Occupied blocks per task id 1633system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 880 # Occupied blocks per task id 1634system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1092 # Occupied blocks per task id 1635system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id |
| 1486system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id | 1636system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id |
| 1487system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 51 # Occupied blocks per task id 1488system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 256 # Occupied blocks per task id 1489system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1161 # Occupied blocks per task id 1490system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5025 # Occupied blocks per task id 1491system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.540710 # Percentage of cache occupancy per task id 1492system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005310 # Percentage of cache occupancy per task id 1493system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.393188 # Percentage of cache occupancy per task id 1494system.cpu1.l2cache.tags.tag_accesses 19285639 # Number of tag accesses 1495system.cpu1.l2cache.tags.data_accesses 19285639 # Number of data accesses 1496system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 22569 # number of ReadReq hits 1497system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2289 # number of ReadReq hits 1498system.cpu1.l2cache.ReadReq_hits::cpu1.inst 905837 # number of ReadReq hits 1499system.cpu1.l2cache.ReadReq_hits::total 930695 # number of ReadReq hits 1500system.cpu1.l2cache.Writeback_hits::writebacks 93707 # number of Writeback hits 1501system.cpu1.l2cache.Writeback_hits::total 93707 # number of Writeback hits 1502system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1549 # number of UpgradeReq hits 1503system.cpu1.l2cache.UpgradeReq_hits::total 1549 # number of UpgradeReq hits 1504system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 533 # number of SCUpgradeReq hits 1505system.cpu1.l2cache.SCUpgradeReq_hits::total 533 # number of SCUpgradeReq hits 1506system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 18299 # number of ReadExReq hits 1507system.cpu1.l2cache.ReadExReq_hits::total 18299 # number of ReadExReq hits 1508system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 22569 # number of demand (read+write) hits 1509system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2289 # number of demand (read+write) hits 1510system.cpu1.l2cache.demand_hits::cpu1.inst 924136 # number of demand (read+write) hits 1511system.cpu1.l2cache.demand_hits::total 948994 # number of demand (read+write) hits 1512system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 22569 # number of overall hits 1513system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2289 # number of overall hits 1514system.cpu1.l2cache.overall_hits::cpu1.inst 924136 # number of overall hits 1515system.cpu1.l2cache.overall_hits::total 948994 # number of overall hits 1516system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 704 # number of ReadReq misses 1517system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 245 # number of ReadReq misses 1518system.cpu1.l2cache.ReadReq_misses::cpu1.inst 66474 # number of ReadReq misses 1519system.cpu1.l2cache.ReadReq_misses::total 67423 # number of ReadReq misses 1520system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 27781 # number of UpgradeReq misses 1521system.cpu1.l2cache.UpgradeReq_misses::total 27781 # number of UpgradeReq misses 1522system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22285 # number of SCUpgradeReq misses 1523system.cpu1.l2cache.SCUpgradeReq_misses::total 22285 # number of SCUpgradeReq misses 1524system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 30137 # number of ReadExReq misses 1525system.cpu1.l2cache.ReadExReq_misses::total 30137 # number of ReadExReq misses 1526system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 704 # number of demand (read+write) misses 1527system.cpu1.l2cache.demand_misses::cpu1.itb.walker 245 # number of demand (read+write) misses 1528system.cpu1.l2cache.demand_misses::cpu1.inst 96611 # number of demand (read+write) misses 1529system.cpu1.l2cache.demand_misses::total 97560 # number of demand (read+write) misses 1530system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 704 # number of overall misses 1531system.cpu1.l2cache.overall_misses::cpu1.itb.walker 245 # number of overall misses 1532system.cpu1.l2cache.overall_misses::cpu1.inst 96611 # number of overall misses 1533system.cpu1.l2cache.overall_misses::total 97560 # number of overall misses 1534system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 14471499 # number of ReadReq miss cycles 1535system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4810998 # number of ReadReq miss cycles 1536system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1464118881 # number of ReadReq miss cycles 1537system.cpu1.l2cache.ReadReq_miss_latency::total 1483401378 # number of ReadReq miss cycles 1538system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 523592810 # number of UpgradeReq miss cycles 1539system.cpu1.l2cache.UpgradeReq_miss_latency::total 523592810 # number of UpgradeReq miss cycles 1540system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 437167020 # number of SCUpgradeReq miss cycles 1541system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 437167020 # number of SCUpgradeReq miss cycles 1542system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 97500 # number of SCUpgradeFailReq miss cycles 1543system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 97500 # number of SCUpgradeFailReq miss cycles 1544system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1078871611 # number of ReadExReq miss cycles 1545system.cpu1.l2cache.ReadExReq_miss_latency::total 1078871611 # number of ReadExReq miss cycles 1546system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 14471499 # number of demand (read+write) miss cycles 1547system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4810998 # number of demand (read+write) miss cycles 1548system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2542990492 # number of demand (read+write) miss cycles 1549system.cpu1.l2cache.demand_miss_latency::total 2562272989 # number of demand (read+write) miss cycles 1550system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 14471499 # number of overall miss cycles 1551system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4810998 # number of overall miss cycles 1552system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2542990492 # number of overall miss cycles 1553system.cpu1.l2cache.overall_miss_latency::total 2562272989 # number of overall miss cycles 1554system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 23273 # number of ReadReq accesses(hits+misses) 1555system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2534 # number of ReadReq accesses(hits+misses) 1556system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 972311 # number of ReadReq accesses(hits+misses) 1557system.cpu1.l2cache.ReadReq_accesses::total 998118 # number of ReadReq accesses(hits+misses) 1558system.cpu1.l2cache.Writeback_accesses::writebacks 93707 # number of Writeback accesses(hits+misses) 1559system.cpu1.l2cache.Writeback_accesses::total 93707 # number of Writeback accesses(hits+misses) 1560system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 29330 # number of UpgradeReq accesses(hits+misses) 1561system.cpu1.l2cache.UpgradeReq_accesses::total 29330 # number of UpgradeReq accesses(hits+misses) 1562system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 22818 # number of SCUpgradeReq accesses(hits+misses) 1563system.cpu1.l2cache.SCUpgradeReq_accesses::total 22818 # number of SCUpgradeReq accesses(hits+misses) 1564system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 48436 # number of ReadExReq accesses(hits+misses) 1565system.cpu1.l2cache.ReadExReq_accesses::total 48436 # number of ReadExReq accesses(hits+misses) 1566system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 23273 # number of demand (read+write) accesses 1567system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2534 # number of demand (read+write) accesses 1568system.cpu1.l2cache.demand_accesses::cpu1.inst 1020747 # number of demand (read+write) accesses 1569system.cpu1.l2cache.demand_accesses::total 1046554 # number of demand (read+write) accesses 1570system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 23273 # number of overall (read+write) accesses 1571system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2534 # number of overall (read+write) accesses 1572system.cpu1.l2cache.overall_accesses::cpu1.inst 1020747 # number of overall (read+write) accesses 1573system.cpu1.l2cache.overall_accesses::total 1046554 # number of overall (read+write) accesses 1574system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.030250 # miss rate for ReadReq accesses 1575system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.096685 # miss rate for ReadReq accesses 1576system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.068367 # miss rate for ReadReq accesses 1577system.cpu1.l2cache.ReadReq_miss_rate::total 0.067550 # miss rate for ReadReq accesses 1578system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.947187 # miss rate for UpgradeReq accesses 1579system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.947187 # miss rate for UpgradeReq accesses 1580system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.976641 # miss rate for SCUpgradeReq accesses 1581system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.976641 # miss rate for SCUpgradeReq accesses 1582system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.622202 # miss rate for ReadExReq accesses 1583system.cpu1.l2cache.ReadExReq_miss_rate::total 0.622202 # miss rate for ReadExReq accesses 1584system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.030250 # miss rate for demand accesses 1585system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.096685 # miss rate for demand accesses 1586system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.094647 # miss rate for demand accesses 1587system.cpu1.l2cache.demand_miss_rate::total 0.093220 # miss rate for demand accesses 1588system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.030250 # miss rate for overall accesses 1589system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.096685 # miss rate for overall accesses 1590system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.094647 # miss rate for overall accesses 1591system.cpu1.l2cache.overall_miss_rate::total 0.093220 # miss rate for overall accesses 1592system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20556.106534 # average ReadReq miss latency 1593system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19636.726531 # average ReadReq miss latency 1594system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22025.436727 # average ReadReq miss latency 1595system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22001.414621 # average ReadReq miss latency 1596system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18847.154890 # average UpgradeReq miss latency 1597system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18847.154890 # average UpgradeReq miss latency 1598system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19617.097599 # average SCUpgradeReq miss latency 1599system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19617.097599 # average SCUpgradeReq miss latency | 1637system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id 1638system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 271 # Occupied blocks per task id 1639system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5756 # Occupied blocks per task id 1640system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 6900 # Occupied blocks per task id 1641system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.125488 # Percentage of cache occupancy per task id 1642system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002747 # Percentage of cache occupancy per task id 1643system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.789001 # Percentage of cache occupancy per task id 1644system.cpu1.l2cache.tags.tag_accesses 21629208 # Number of tag accesses 1645system.cpu1.l2cache.tags.data_accesses 21629208 # Number of data accesses 1646system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28145 # number of ReadReq hits 1647system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2626 # number of ReadReq hits 1648system.cpu1.l2cache.ReadReq_hits::cpu1.inst 993919 # number of ReadReq hits 1649system.cpu1.l2cache.ReadReq_hits::total 1024690 # number of ReadReq hits 1650system.cpu1.l2cache.Writeback_hits::writebacks 113900 # number of Writeback hits 1651system.cpu1.l2cache.Writeback_hits::total 113900 # number of Writeback hits 1652system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1602 # number of UpgradeReq hits 1653system.cpu1.l2cache.UpgradeReq_hits::total 1602 # number of UpgradeReq hits 1654system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 885 # number of SCUpgradeReq hits 1655system.cpu1.l2cache.SCUpgradeReq_hits::total 885 # number of SCUpgradeReq hits 1656system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 24979 # number of ReadExReq hits 1657system.cpu1.l2cache.ReadExReq_hits::total 24979 # number of ReadExReq hits 1658system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28145 # number of demand (read+write) hits 1659system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2626 # number of demand (read+write) hits 1660system.cpu1.l2cache.demand_hits::cpu1.inst 1018898 # number of demand (read+write) hits 1661system.cpu1.l2cache.demand_hits::total 1049669 # number of demand (read+write) hits 1662system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 28145 # number of overall hits 1663system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2626 # number of overall hits 1664system.cpu1.l2cache.overall_hits::cpu1.inst 1018898 # number of overall hits 1665system.cpu1.l2cache.overall_hits::total 1049669 # number of overall hits 1666system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 614 # number of ReadReq misses 1667system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 219 # number of ReadReq misses 1668system.cpu1.l2cache.ReadReq_misses::cpu1.inst 85964 # number of ReadReq misses 1669system.cpu1.l2cache.ReadReq_misses::total 86797 # number of ReadReq misses 1670system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 28133 # number of UpgradeReq misses 1671system.cpu1.l2cache.UpgradeReq_misses::total 28133 # number of UpgradeReq misses 1672system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22540 # number of SCUpgradeReq misses 1673system.cpu1.l2cache.SCUpgradeReq_misses::total 22540 # number of SCUpgradeReq misses 1674system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 35034 # number of ReadExReq misses 1675system.cpu1.l2cache.ReadExReq_misses::total 35034 # number of ReadExReq misses 1676system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 614 # number of demand (read+write) misses 1677system.cpu1.l2cache.demand_misses::cpu1.itb.walker 219 # number of demand (read+write) misses 1678system.cpu1.l2cache.demand_misses::cpu1.inst 120998 # number of demand (read+write) misses 1679system.cpu1.l2cache.demand_misses::total 121831 # number of demand (read+write) misses 1680system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 614 # number of overall misses 1681system.cpu1.l2cache.overall_misses::cpu1.itb.walker 219 # number of overall misses 1682system.cpu1.l2cache.overall_misses::cpu1.inst 120998 # number of overall misses 1683system.cpu1.l2cache.overall_misses::total 121831 # number of overall misses 1684system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 13117250 # number of ReadReq miss cycles 1685system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4335498 # number of ReadReq miss cycles 1686system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 2028659662 # number of ReadReq miss cycles 1687system.cpu1.l2cache.ReadReq_miss_latency::total 2046112410 # number of ReadReq miss cycles 1688system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 524558345 # number of UpgradeReq miss cycles 1689system.cpu1.l2cache.UpgradeReq_miss_latency::total 524558345 # number of UpgradeReq miss cycles 1690system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 440871540 # number of SCUpgradeReq miss cycles 1691system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 440871540 # number of SCUpgradeReq miss cycles 1692system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 173000 # number of SCUpgradeFailReq miss cycles 1693system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 173000 # number of SCUpgradeFailReq miss cycles 1694system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1316941950 # number of ReadExReq miss cycles 1695system.cpu1.l2cache.ReadExReq_miss_latency::total 1316941950 # number of ReadExReq miss cycles 1696system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 13117250 # number of demand (read+write) miss cycles 1697system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4335498 # number of demand (read+write) miss cycles 1698system.cpu1.l2cache.demand_miss_latency::cpu1.inst 3345601612 # number of demand (read+write) miss cycles 1699system.cpu1.l2cache.demand_miss_latency::total 3363054360 # number of demand (read+write) miss cycles 1700system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 13117250 # number of overall miss cycles 1701system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4335498 # number of overall miss cycles 1702system.cpu1.l2cache.overall_miss_latency::cpu1.inst 3345601612 # number of overall miss cycles 1703system.cpu1.l2cache.overall_miss_latency::total 3363054360 # number of overall miss cycles 1704system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 28759 # number of ReadReq accesses(hits+misses) 1705system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2845 # number of ReadReq accesses(hits+misses) 1706system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 1079883 # number of ReadReq accesses(hits+misses) 1707system.cpu1.l2cache.ReadReq_accesses::total 1111487 # number of ReadReq accesses(hits+misses) 1708system.cpu1.l2cache.Writeback_accesses::writebacks 113900 # number of Writeback accesses(hits+misses) 1709system.cpu1.l2cache.Writeback_accesses::total 113900 # number of Writeback accesses(hits+misses) 1710system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 29735 # number of UpgradeReq accesses(hits+misses) 1711system.cpu1.l2cache.UpgradeReq_accesses::total 29735 # number of UpgradeReq accesses(hits+misses) 1712system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 23425 # number of SCUpgradeReq accesses(hits+misses) 1713system.cpu1.l2cache.SCUpgradeReq_accesses::total 23425 # number of SCUpgradeReq accesses(hits+misses) 1714system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 60013 # number of ReadExReq accesses(hits+misses) 1715system.cpu1.l2cache.ReadExReq_accesses::total 60013 # number of ReadExReq accesses(hits+misses) 1716system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 28759 # number of demand (read+write) accesses 1717system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2845 # number of demand (read+write) accesses 1718system.cpu1.l2cache.demand_accesses::cpu1.inst 1139896 # number of demand (read+write) accesses 1719system.cpu1.l2cache.demand_accesses::total 1171500 # number of demand (read+write) accesses 1720system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 28759 # number of overall (read+write) accesses 1721system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2845 # number of overall (read+write) accesses 1722system.cpu1.l2cache.overall_accesses::cpu1.inst 1139896 # number of overall (read+write) accesses 1723system.cpu1.l2cache.overall_accesses::total 1171500 # number of overall (read+write) accesses 1724system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021350 # miss rate for ReadReq accesses 1725system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.076977 # miss rate for ReadReq accesses 1726system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.079605 # miss rate for ReadReq accesses 1727system.cpu1.l2cache.ReadReq_miss_rate::total 0.078091 # miss rate for ReadReq accesses 1728system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.946124 # miss rate for UpgradeReq accesses 1729system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.946124 # miss rate for UpgradeReq accesses 1730system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.962220 # miss rate for SCUpgradeReq accesses 1731system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.962220 # miss rate for SCUpgradeReq accesses 1732system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.583774 # miss rate for ReadExReq accesses 1733system.cpu1.l2cache.ReadExReq_miss_rate::total 0.583774 # miss rate for ReadExReq accesses 1734system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021350 # miss rate for demand accesses 1735system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.076977 # miss rate for demand accesses 1736system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.106148 # miss rate for demand accesses 1737system.cpu1.l2cache.demand_miss_rate::total 0.103996 # miss rate for demand accesses 1738system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021350 # miss rate for overall accesses 1739system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.076977 # miss rate for overall accesses 1740system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.106148 # miss rate for overall accesses 1741system.cpu1.l2cache.overall_miss_rate::total 0.103996 # miss rate for overall accesses 1742system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21363.599349 # average ReadReq miss latency 1743system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19796.794521 # average ReadReq miss latency 1744system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 23598.944465 # average ReadReq miss latency 1745system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23573.538371 # average ReadReq miss latency 1746system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18645.659723 # average UpgradeReq miss latency 1747system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18645.659723 # average UpgradeReq miss latency 1748system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19559.518190 # average SCUpgradeReq miss latency 1749system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19559.518190 # average SCUpgradeReq miss latency |
| 1600system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst inf # average SCUpgradeFailReq miss latency 1601system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency | 1750system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst inf # average SCUpgradeFailReq miss latency 1751system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency |
| 1602system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 35798.905365 # average ReadExReq miss latency 1603system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 35798.905365 # average ReadExReq miss latency 1604system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20556.106534 # average overall miss latency 1605system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19636.726531 # average overall miss latency 1606system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26321.956009 # average overall miss latency 1607system.cpu1.l2cache.demand_avg_miss_latency::total 26263.560773 # average overall miss latency 1608system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20556.106534 # average overall miss latency 1609system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19636.726531 # average overall miss latency 1610system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26321.956009 # average overall miss latency 1611system.cpu1.l2cache.overall_avg_miss_latency::total 26263.560773 # average overall miss latency 1612system.cpu1.l2cache.blocked_cycles::no_mshrs 2801 # number of cycles access was blocked | 1752system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 37590.396472 # average ReadExReq miss latency 1753system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 37590.396472 # average ReadExReq miss latency 1754system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21363.599349 # average overall miss latency 1755system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19796.794521 # average overall miss latency 1756system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 27650.057125 # average overall miss latency 1757system.cpu1.l2cache.demand_avg_miss_latency::total 27604.258030 # average overall miss latency 1758system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21363.599349 # average overall miss latency 1759system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19796.794521 # average overall miss latency 1760system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 27650.057125 # average overall miss latency 1761system.cpu1.l2cache.overall_avg_miss_latency::total 27604.258030 # average overall miss latency 1762system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 1613system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1763system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1614system.cpu1.l2cache.blocked::no_mshrs 79 # number of cycles access was blocked | 1764system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 1615system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1765system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1616system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 35.455696 # average number of cycles each access was blocked | 1766system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 1617system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1618system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1619system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 1767system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1768system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1769system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 1620system.cpu1.l2cache.writebacks::writebacks 30368 # number of writebacks 1621system.cpu1.l2cache.writebacks::total 30368 # number of writebacks 1622system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 950 # number of ReadReq MSHR hits 1623system.cpu1.l2cache.ReadReq_mshr_hits::total 950 # number of ReadReq MSHR hits 1624system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 295 # number of ReadExReq MSHR hits 1625system.cpu1.l2cache.ReadExReq_mshr_hits::total 295 # number of ReadExReq MSHR hits 1626system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1245 # number of demand (read+write) MSHR hits 1627system.cpu1.l2cache.demand_mshr_hits::total 1245 # number of demand (read+write) MSHR hits 1628system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1245 # number of overall MSHR hits 1629system.cpu1.l2cache.overall_mshr_hits::total 1245 # number of overall MSHR hits 1630system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 704 # number of ReadReq MSHR misses 1631system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 245 # number of ReadReq MSHR misses 1632system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 65524 # number of ReadReq MSHR misses 1633system.cpu1.l2cache.ReadReq_mshr_misses::total 66473 # number of ReadReq MSHR misses 1634system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 80004 # number of HardPFReq MSHR misses 1635system.cpu1.l2cache.HardPFReq_mshr_misses::total 80004 # number of HardPFReq MSHR misses 1636system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 27781 # number of UpgradeReq MSHR misses 1637system.cpu1.l2cache.UpgradeReq_mshr_misses::total 27781 # number of UpgradeReq MSHR misses 1638system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22285 # number of SCUpgradeReq MSHR misses 1639system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22285 # number of SCUpgradeReq MSHR misses 1640system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 29842 # number of ReadExReq MSHR misses 1641system.cpu1.l2cache.ReadExReq_mshr_misses::total 29842 # number of ReadExReq MSHR misses 1642system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 704 # number of demand (read+write) MSHR misses 1643system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 245 # number of demand (read+write) MSHR misses 1644system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 95366 # number of demand (read+write) MSHR misses 1645system.cpu1.l2cache.demand_mshr_misses::total 96315 # number of demand (read+write) MSHR misses 1646system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 704 # number of overall MSHR misses 1647system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 245 # number of overall MSHR misses 1648system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 95366 # number of overall MSHR misses 1649system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 80004 # number of overall MSHR misses 1650system.cpu1.l2cache.overall_mshr_misses::total 176319 # number of overall MSHR misses 1651system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 9542501 # number of ReadReq MSHR miss cycles 1652system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3095998 # number of ReadReq MSHR miss cycles 1653system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 981688737 # number of ReadReq MSHR miss cycles 1654system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 994327236 # number of ReadReq MSHR miss cycles 1655system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2522312930 # number of HardPFReq MSHR miss cycles 1656system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 2522312930 # number of HardPFReq MSHR miss cycles 1657system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 396174942 # number of UpgradeReq MSHR miss cycles 1658system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 396174942 # number of UpgradeReq MSHR miss cycles 1659system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 306073762 # number of SCUpgradeReq MSHR miss cycles 1660system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306073762 # number of SCUpgradeReq MSHR miss cycles 1661system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 76500 # number of SCUpgradeFailReq MSHR miss cycles 1662system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 76500 # number of SCUpgradeFailReq MSHR miss cycles 1663system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 831450098 # number of ReadExReq MSHR miss cycles 1664system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 831450098 # number of ReadExReq MSHR miss cycles 1665system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 9542501 # number of demand (read+write) MSHR miss cycles 1666system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3095998 # number of demand (read+write) MSHR miss cycles 1667system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1813138835 # number of demand (read+write) MSHR miss cycles 1668system.cpu1.l2cache.demand_mshr_miss_latency::total 1825777334 # number of demand (read+write) MSHR miss cycles 1669system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 9542501 # number of overall MSHR miss cycles 1670system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3095998 # number of overall MSHR miss cycles 1671system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1813138835 # number of overall MSHR miss cycles 1672system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2522312930 # number of overall MSHR miss cycles 1673system.cpu1.l2cache.overall_mshr_miss_latency::total 4348090264 # number of overall MSHR miss cycles 1674system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 313994504 # number of ReadReq MSHR uncacheable cycles 1675system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 313994504 # number of ReadReq MSHR uncacheable cycles 1676system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 182561501 # number of WriteReq MSHR uncacheable cycles 1677system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 182561501 # number of WriteReq MSHR uncacheable cycles 1678system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 496556005 # number of overall MSHR uncacheable cycles 1679system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 496556005 # number of overall MSHR uncacheable cycles 1680system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.030250 # mshr miss rate for ReadReq accesses 1681system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.096685 # mshr miss rate for ReadReq accesses 1682system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.067390 # mshr miss rate for ReadReq accesses 1683system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.066598 # mshr miss rate for ReadReq accesses | 1770system.cpu1.l2cache.writebacks::writebacks 33019 # number of writebacks 1771system.cpu1.l2cache.writebacks::total 33019 # number of writebacks 1772system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 106 # number of ReadReq MSHR hits 1773system.cpu1.l2cache.ReadReq_mshr_hits::total 106 # number of ReadReq MSHR hits 1774system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 284 # number of ReadExReq MSHR hits 1775system.cpu1.l2cache.ReadExReq_mshr_hits::total 284 # number of ReadExReq MSHR hits 1776system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 390 # number of demand (read+write) MSHR hits 1777system.cpu1.l2cache.demand_mshr_hits::total 390 # number of demand (read+write) MSHR hits 1778system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 390 # number of overall MSHR hits 1779system.cpu1.l2cache.overall_mshr_hits::total 390 # number of overall MSHR hits 1780system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 614 # number of ReadReq MSHR misses 1781system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 219 # number of ReadReq MSHR misses 1782system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 85858 # number of ReadReq MSHR misses 1783system.cpu1.l2cache.ReadReq_mshr_misses::total 86691 # number of ReadReq MSHR misses 1784system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25785 # number of HardPFReq MSHR misses 1785system.cpu1.l2cache.HardPFReq_mshr_misses::total 25785 # number of HardPFReq MSHR misses 1786system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 28133 # number of UpgradeReq MSHR misses 1787system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28133 # number of UpgradeReq MSHR misses 1788system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22540 # number of SCUpgradeReq MSHR misses 1789system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22540 # number of SCUpgradeReq MSHR misses 1790system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 34750 # number of ReadExReq MSHR misses 1791system.cpu1.l2cache.ReadExReq_mshr_misses::total 34750 # number of ReadExReq MSHR misses 1792system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 614 # number of demand (read+write) MSHR misses 1793system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 219 # number of demand (read+write) MSHR misses 1794system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 120608 # number of demand (read+write) MSHR misses 1795system.cpu1.l2cache.demand_mshr_misses::total 121441 # number of demand (read+write) MSHR misses 1796system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 614 # number of overall MSHR misses 1797system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 219 # number of overall MSHR misses 1798system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 120608 # number of overall MSHR misses 1799system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25785 # number of overall MSHR misses 1800system.cpu1.l2cache.overall_mshr_misses::total 147226 # number of overall MSHR misses 1801system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 8818750 # number of ReadReq MSHR miss cycles 1802system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2802498 # number of ReadReq MSHR miss cycles 1803system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1423893692 # number of ReadReq MSHR miss cycles 1804system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1435514940 # number of ReadReq MSHR miss cycles 1805system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1025770621 # number of HardPFReq MSHR miss cycles 1806system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1025770621 # number of HardPFReq MSHR miss cycles 1807system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 399929245 # number of UpgradeReq MSHR miss cycles 1808system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 399929245 # number of UpgradeReq MSHR miss cycles 1809system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 306606785 # number of SCUpgradeReq MSHR miss cycles 1810system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306606785 # number of SCUpgradeReq MSHR miss cycles 1811system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 145000 # number of SCUpgradeFailReq MSHR miss cycles 1812system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 145000 # number of SCUpgradeFailReq MSHR miss cycles 1813system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 1042779776 # number of ReadExReq MSHR miss cycles 1814system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1042779776 # number of ReadExReq MSHR miss cycles 1815system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 8818750 # number of demand (read+write) MSHR miss cycles 1816system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2802498 # number of demand (read+write) MSHR miss cycles 1817system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 2466673468 # number of demand (read+write) MSHR miss cycles 1818system.cpu1.l2cache.demand_mshr_miss_latency::total 2478294716 # number of demand (read+write) MSHR miss cycles 1819system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 8818750 # number of overall MSHR miss cycles 1820system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2802498 # number of overall MSHR miss cycles 1821system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 2466673468 # number of overall MSHR miss cycles 1822system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1025770621 # number of overall MSHR miss cycles 1823system.cpu1.l2cache.overall_mshr_miss_latency::total 3504065337 # number of overall MSHR miss cycles 1824system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 316947250 # number of ReadReq MSHR uncacheable cycles 1825system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 316947250 # number of ReadReq MSHR uncacheable cycles 1826system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 187186000 # number of WriteReq MSHR uncacheable cycles 1827system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 187186000 # number of WriteReq MSHR uncacheable cycles 1828system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 504133250 # number of overall MSHR uncacheable cycles 1829system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 504133250 # number of overall MSHR uncacheable cycles 1830system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for ReadReq accesses 1831system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for ReadReq accesses 1832system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.079507 # mshr miss rate for ReadReq accesses 1833system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.077996 # mshr miss rate for ReadReq accesses |
| 1684system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1685system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1834system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1835system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1686system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.947187 # mshr miss rate for UpgradeReq accesses 1687system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.947187 # mshr miss rate for UpgradeReq accesses 1688system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.976641 # mshr miss rate for SCUpgradeReq accesses 1689system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.976641 # mshr miss rate for SCUpgradeReq accesses 1690system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.616112 # mshr miss rate for ReadExReq accesses 1691system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.616112 # mshr miss rate for ReadExReq accesses 1692system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.030250 # mshr miss rate for demand accesses 1693system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.096685 # mshr miss rate for demand accesses 1694system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.093428 # mshr miss rate for demand accesses 1695system.cpu1.l2cache.demand_mshr_miss_rate::total 0.092031 # mshr miss rate for demand accesses 1696system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.030250 # mshr miss rate for overall accesses 1697system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.096685 # mshr miss rate for overall accesses 1698system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.093428 # mshr miss rate for overall accesses | 1836system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.946124 # mshr miss rate for UpgradeReq accesses 1837system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.946124 # mshr miss rate for UpgradeReq accesses 1838system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.962220 # mshr miss rate for SCUpgradeReq accesses 1839system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962220 # mshr miss rate for SCUpgradeReq accesses 1840system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.579041 # mshr miss rate for ReadExReq accesses 1841system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.579041 # mshr miss rate for ReadExReq accesses 1842system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for demand accesses 1843system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for demand accesses 1844system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.105806 # mshr miss rate for demand accesses 1845system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103663 # mshr miss rate for demand accesses 1846system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for overall accesses 1847system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for overall accesses 1848system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.105806 # mshr miss rate for overall accesses |
| 1699system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1849system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1700system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168476 # mshr miss rate for overall accesses 1701system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average ReadReq mshr miss latency 1702system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average ReadReq mshr miss latency 1703system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14982.124672 # average ReadReq mshr miss latency 1704system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14958.362583 # average ReadReq mshr miss latency 1705system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31527.335258 # average HardPFReq mshr miss latency 1706system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31527.335258 # average HardPFReq mshr miss latency 1707system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14260.643677 # average UpgradeReq mshr miss latency 1708system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14260.643677 # average UpgradeReq mshr miss latency 1709system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13734.519273 # average SCUpgradeReq mshr miss latency 1710system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13734.519273 # average SCUpgradeReq mshr miss latency | 1850system.cpu1.l2cache.overall_mshr_miss_rate::total 0.125673 # mshr miss rate for overall accesses 1851system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average ReadReq mshr miss latency 1852system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average ReadReq mshr miss latency 1853system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 16584.286753 # average ReadReq mshr miss latency 1854system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16558.984670 # average ReadReq mshr miss latency 1855system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085 # average HardPFReq mshr miss latency 1856system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39781.680085 # average HardPFReq mshr miss latency 1857system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14215.662923 # average UpgradeReq mshr miss latency 1858system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14215.662923 # average UpgradeReq mshr miss latency 1859system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13602.785492 # average SCUpgradeReq mshr miss latency 1860system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13602.785492 # average SCUpgradeReq mshr miss latency |
| 1711system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst inf # average SCUpgradeFailReq mshr miss latency 1712system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency | 1861system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst inf # average SCUpgradeFailReq mshr miss latency 1862system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency |
| 1713system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27861.741773 # average ReadExReq mshr miss latency 1714system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27861.741773 # average ReadExReq mshr miss latency 1715system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average overall mshr miss latency 1716system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average overall mshr miss latency 1717system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19012.424082 # average overall mshr miss latency 1718system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18956.313492 # average overall mshr miss latency 1719system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average overall mshr miss latency 1720system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average overall mshr miss latency 1721system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19012.424082 # average overall mshr miss latency 1722system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31527.335258 # average overall mshr miss latency 1723system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24660.361413 # average overall mshr miss latency | 1863system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30008.051108 # average ReadExReq mshr miss latency 1864system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30008.051108 # average ReadExReq mshr miss latency 1865system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average overall mshr miss latency 1866system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average overall mshr miss latency 1867system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20451.988823 # average overall mshr miss latency 1868system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20407.397139 # average overall mshr miss latency 1869system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average overall mshr miss latency 1870system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average overall mshr miss latency 1871system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20451.988823 # average overall mshr miss latency 1872system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085 # average overall mshr miss latency 1873system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23800.587783 # average overall mshr miss latency |
| 1724system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1725system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1726system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 1727system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1728system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1729system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1730system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1874system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1875system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1876system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 1877system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1878system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1879system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1880system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1731system.cpu1.toL2Bus.trans_dist::ReadReq 1502965 # Transaction distribution 1732system.cpu1.toL2Bus.trans_dist::ReadResp 1041469 # Transaction distribution 1733system.cpu1.toL2Bus.trans_dist::WriteReq 2098 # Transaction distribution 1734system.cpu1.toL2Bus.trans_dist::WriteResp 2098 # Transaction distribution 1735system.cpu1.toL2Bus.trans_dist::Writeback 93707 # Transaction distribution 1736system.cpu1.toL2Bus.trans_dist::HardPFReq 114724 # Transaction distribution | 1881system.cpu1.toL2Bus.trans_dist::ReadReq 1492249 # Transaction distribution 1882system.cpu1.toL2Bus.trans_dist::ReadResp 1157222 # Transaction distribution 1883system.cpu1.toL2Bus.trans_dist::WriteReq 2126 # Transaction distribution 1884system.cpu1.toL2Bus.trans_dist::WriteResp 2126 # Transaction distribution 1885system.cpu1.toL2Bus.trans_dist::Writeback 113900 # Transaction distribution 1886system.cpu1.toL2Bus.trans_dist::HardPFReq 36842 # Transaction distribution |
| 1737system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution | 1887system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution |
| 1738system.cpu1.toL2Bus.trans_dist::UpgradeReq 83933 # Transaction distribution 1739system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40744 # Transaction distribution 1740system.cpu1.toL2Bus.trans_dist::UpgradeResp 84523 # Transaction distribution 1741system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 1742system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution 1743system.cpu1.toL2Bus.trans_dist::ReadExReq 65298 # Transaction distribution 1744system.cpu1.toL2Bus.trans_dist::ReadExResp 52790 # Transaction distribution 1745system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1655558 # Packet count per connected master and slave (bytes) 1746system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 667978 # Packet count per connected master and slave (bytes) 1747system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6105 # Packet count per connected master and slave (bytes) 1748system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 48641 # Packet count per connected master and slave (bytes) 1749system.cpu1.toL2Bus.pkt_count::total 2378282 # Packet count per connected master and slave (bytes) 1750system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 52977856 # Cumulative packet size per connected master and slave (bytes) 1751system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 21039827 # Cumulative packet size per connected master and slave (bytes) 1752system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10136 # Cumulative packet size per connected master and slave (bytes) 1753system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 93092 # Cumulative packet size per connected master and slave (bytes) 1754system.cpu1.toL2Bus.pkt_size::total 74120911 # Cumulative packet size per connected master and slave (bytes) 1755system.cpu1.toL2Bus.snoops 816365 # Total snoops (count) 1756system.cpu1.toL2Bus.snoop_fanout::samples 1934720 # Request fanout histogram 1757system.cpu1.toL2Bus.snoop_fanout::mean 5.382054 # Request fanout histogram 1758system.cpu1.toL2Bus.snoop_fanout::stdev 0.485890 # Request fanout histogram | 1888system.cpu1.toL2Bus.trans_dist::UpgradeReq 74786 # Transaction distribution 1889system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41424 # Transaction distribution 1890system.cpu1.toL2Bus.trans_dist::UpgradeResp 85596 # Transaction distribution 1891system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution 1892system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 13 # Transaction distribution 1893system.cpu1.toL2Bus.trans_dist::ReadExReq 82199 # Transaction distribution 1894system.cpu1.toL2Bus.trans_dist::ReadExResp 64364 # Transaction distribution 1895system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1817284 # Packet count per connected master and slave (bytes) 1896system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 767101 # Packet count per connected master and slave (bytes) 1897system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7150 # Packet count per connected master and slave (bytes) 1898system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 61380 # Packet count per connected master and slave (bytes) 1899system.cpu1.toL2Bus.pkt_count::total 2652915 # Packet count per connected master and slave (bytes) 1900system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 58153088 # Cumulative packet size per connected master and slave (bytes) 1901system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24793955 # Cumulative packet size per connected master and slave (bytes) 1902system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11380 # Cumulative packet size per connected master and slave (bytes) 1903system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 115036 # Cumulative packet size per connected master and slave (bytes) 1904system.cpu1.toL2Bus.pkt_size::total 83073459 # Cumulative packet size per connected master and slave (bytes) 1905system.cpu1.toL2Bus.snoops 610470 # Total snoops (count) 1906system.cpu1.toL2Bus.snoop_fanout::samples 1874725 # Request fanout histogram 1907system.cpu1.toL2Bus.snoop_fanout::mean 5.283158 # Request fanout histogram 1908system.cpu1.toL2Bus.snoop_fanout::stdev 0.450533 # Request fanout histogram |
| 1759system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1760system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1761system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1762system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1763system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1764system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1909system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1910system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1911system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1912system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1913system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1914system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 1765system.cpu1.toL2Bus.snoop_fanout::5 1195552 61.79% 61.79% # Request fanout histogram 1766system.cpu1.toL2Bus.snoop_fanout::6 739168 38.21% 100.00% # Request fanout histogram | 1915system.cpu1.toL2Bus.snoop_fanout::5 1343882 71.68% 71.68% # Request fanout histogram 1916system.cpu1.toL2Bus.snoop_fanout::6 530843 28.32% 100.00% # Request fanout histogram |
| 1767system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1768system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1769system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 1917system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1918system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1919system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 1770system.cpu1.toL2Bus.snoop_fanout::total 1934720 # Request fanout histogram 1771system.cpu1.toL2Bus.reqLayer0.occupancy 695166718 # Layer occupancy (ticks) | 1920system.cpu1.toL2Bus.snoop_fanout::total 1874725 # Request fanout histogram 1921system.cpu1.toL2Bus.reqLayer0.occupancy 789561722 # Layer occupancy (ticks) |
| 1772system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1922system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1773system.cpu1.toL2Bus.snoopLayer0.occupancy 78719500 # Layer occupancy (ticks) | 1923system.cpu1.toL2Bus.snoopLayer0.occupancy 79017500 # Layer occupancy (ticks) |
| 1774system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1924system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1775system.cpu1.toL2Bus.respLayer0.occupancy 1243267482 # Layer occupancy (ticks) | 1925system.cpu1.toL2Bus.respLayer0.occupancy 1364909988 # Layer occupancy (ticks) |
| 1776system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1926system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1777system.cpu1.toL2Bus.respLayer1.occupancy 322631890 # Layer occupancy (ticks) | 1927system.cpu1.toL2Bus.respLayer1.occupancy 381206023 # Layer occupancy (ticks) |
| 1778system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1928system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1779system.cpu1.toL2Bus.respLayer2.occupancy 3571998 # Layer occupancy (ticks) | 1929system.cpu1.toL2Bus.respLayer2.occupancy 4307495 # Layer occupancy (ticks) |
| 1780system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1930system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1781system.cpu1.toL2Bus.respLayer3.occupancy 25370995 # Layer occupancy (ticks) | 1931system.cpu1.toL2Bus.respLayer3.occupancy 32623745 # Layer occupancy (ticks) |
| 1782system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1932system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1783system.iobus.trans_dist::ReadReq 31020 # Transaction distribution 1784system.iobus.trans_dist::ReadResp 31020 # Transaction distribution 1785system.iobus.trans_dist::WriteReq 59447 # Transaction distribution 1786system.iobus.trans_dist::WriteResp 23223 # Transaction distribution | 1933system.iobus.trans_dist::ReadReq 31012 # Transaction distribution 1934system.iobus.trans_dist::ReadResp 31012 # Transaction distribution 1935system.iobus.trans_dist::WriteReq 59440 # Transaction distribution 1936system.iobus.trans_dist::WriteResp 23216 # Transaction distribution |
| 1787system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution | 1937system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 1788system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56686 # Packet count per connected master and slave (bytes) | 1938system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) |
| 1789system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1790system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1791system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1792system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1793system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1794system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1795system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1796system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1801system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1802system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1803system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1804system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1805system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1806system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1807system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1808system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 1939system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1940system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1941system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1942system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1943system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1944system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1945system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1946system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1951system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1952system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1953system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1954system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1955system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1956system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1957system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1958system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 1809system.iobus.pkt_count_system.bridge.master::total 108000 # Packet count per connected master and slave (bytes) | 1959system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) |
| 1810system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) 1811system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) | 1960system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) 1961system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) |
| 1812system.iobus.pkt_count::total 180934 # Packet count per connected master and slave (bytes) 1813system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71630 # Cumulative packet size per connected master and slave (bytes) | 1962system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) 1963system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) |
| 1814system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 1815system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1816system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1817system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1818system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1819system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1820system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1821system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1826system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1827system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1828system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1829system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1830system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1831system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1832system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1833system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | 1964system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 1965system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1966system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1967system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1968system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1969system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1970system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1971system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1976system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1977system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1978system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1979system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1980system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1981system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1982system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1983system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 1834system.iobus.pkt_size_system.bridge.master::total 162880 # Cumulative packet size per connected master and slave (bytes) | 1984system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) |
| 1835system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) 1836system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) | 1985system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) 1986system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) |
| 1837system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) 1838system.iobus.reqLayer0.occupancy 40158000 # Layer occupancy (ticks) | 1987system.iobus.pkt_size::total 2484026 # Cumulative packet size per connected master and slave (bytes) 1988system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) |
| 1839system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1840system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 1841system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1842system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 1843system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1844system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 1845system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1846system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) --- 23 unchanged lines hidden (view full) --- 1870system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1871system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1872system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1873system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1874system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1875system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1876system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1877system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 1989system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1990system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 1991system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1992system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 1993system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1994system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 1995system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1996system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) --- 23 unchanged lines hidden (view full) --- 2020system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2021system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2022system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2023system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2024system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2025system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2026system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2027system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 1878system.iobus.reqLayer27.occupancy 347075142 # Layer occupancy (ticks) | 2028system.iobus.reqLayer27.occupancy 347036169 # Layer occupancy (ticks) |
| 1879system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1880system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1881system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 2029system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2030system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2031system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 1882system.iobus.respLayer0.occupancy 84777000 # Layer occupancy (ticks) | 2032system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) |
| 1883system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 2033system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1884system.iobus.respLayer3.occupancy 36822606 # Layer occupancy (ticks) | 2034system.iobus.respLayer3.occupancy 36822569 # Layer occupancy (ticks) |
| 1885system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 2035system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1886system.iocache.tags.replacements 36433 # number of replacements 1887system.iocache.tags.tagsinuse 0.995239 # Cycle average of tags in use | 2036system.iocache.tags.replacements 36417 # number of replacements 2037system.iocache.tags.tagsinuse 0.997930 # Cycle average of tags in use |
| 1888system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 2038system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 1889system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. | 2039system.iocache.tags.sampled_refs 36433 # Sample count of references to valid blocks. |
| 1890system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 2040system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1891system.iocache.tags.warmup_cycle 269184120000 # Cycle when the warmup percentage was hit. 1892system.iocache.tags.occ_blocks::realview.ide 0.995239 # Average occupied blocks per requestor 1893system.iocache.tags.occ_percent::realview.ide 0.062202 # Average percentage of cache occupancy 1894system.iocache.tags.occ_percent::total 0.062202 # Average percentage of cache occupancy | 2041system.iocache.tags.warmup_cycle 269849823000 # Cycle when the warmup percentage was hit. 2042system.iocache.tags.occ_blocks::realview.ide 0.997930 # Average occupied blocks per requestor 2043system.iocache.tags.occ_percent::realview.ide 0.062371 # Average percentage of cache occupancy 2044system.iocache.tags.occ_percent::total 0.062371 # Average percentage of cache occupancy |
| 1895system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1896system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1897system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1898system.iocache.tags.tag_accesses 328203 # Number of tag accesses 1899system.iocache.tags.data_accesses 328203 # Number of data accesses 1900system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses 1901system.iocache.ReadReq_misses::total 243 # number of ReadReq misses 1902system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 1903system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses 1904system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses 1905system.iocache.demand_misses::total 243 # number of demand (read+write) misses 1906system.iocache.overall_misses::realview.ide 243 # number of overall misses 1907system.iocache.overall_misses::total 243 # number of overall misses | 2045system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2046system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2047system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2048system.iocache.tags.tag_accesses 328203 # Number of tag accesses 2049system.iocache.tags.data_accesses 328203 # Number of data accesses 2050system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses 2051system.iocache.ReadReq_misses::total 243 # number of ReadReq misses 2052system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 2053system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses 2054system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses 2055system.iocache.demand_misses::total 243 # number of demand (read+write) misses 2056system.iocache.overall_misses::realview.ide 243 # number of overall misses 2057system.iocache.overall_misses::total 243 # number of overall misses |
| 1908system.iocache.ReadReq_miss_latency::realview.ide 30315377 # number of ReadReq miss cycles 1909system.iocache.ReadReq_miss_latency::total 30315377 # number of ReadReq miss cycles 1910system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9644186159 # number of WriteInvalidateReq miss cycles 1911system.iocache.WriteInvalidateReq_miss_latency::total 9644186159 # number of WriteInvalidateReq miss cycles 1912system.iocache.demand_miss_latency::realview.ide 30315377 # number of demand (read+write) miss cycles 1913system.iocache.demand_miss_latency::total 30315377 # number of demand (read+write) miss cycles 1914system.iocache.overall_miss_latency::realview.ide 30315377 # number of overall miss cycles 1915system.iocache.overall_miss_latency::total 30315377 # number of overall miss cycles | 2058system.iocache.ReadReq_miss_latency::realview.ide 30354377 # number of ReadReq miss cycles 2059system.iocache.ReadReq_miss_latency::total 30354377 # number of ReadReq miss cycles 2060system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9625347223 # number of WriteInvalidateReq miss cycles 2061system.iocache.WriteInvalidateReq_miss_latency::total 9625347223 # number of WriteInvalidateReq miss cycles 2062system.iocache.demand_miss_latency::realview.ide 30354377 # number of demand (read+write) miss cycles 2063system.iocache.demand_miss_latency::total 30354377 # number of demand (read+write) miss cycles 2064system.iocache.overall_miss_latency::realview.ide 30354377 # number of overall miss cycles 2065system.iocache.overall_miss_latency::total 30354377 # number of overall miss cycles |
| 1916system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) 1917system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) 1918system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1919system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 1920system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses 1921system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses 1922system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses 1923system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses 1924system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1925system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1926system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 1927system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1928system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1929system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1930system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1931system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 2066system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) 2067system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) 2068system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 2069system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 2070system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses 2071system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses 2072system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses 2073system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses 2074system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2075system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2076system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2077system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2078system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2079system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2080system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2081system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1932system.iocache.ReadReq_avg_miss_latency::realview.ide 124754.637860 # average ReadReq miss latency 1933system.iocache.ReadReq_avg_miss_latency::total 124754.637860 # average ReadReq miss latency 1934system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 266237.471262 # average WriteInvalidateReq miss latency 1935system.iocache.WriteInvalidateReq_avg_miss_latency::total 266237.471262 # average WriteInvalidateReq miss latency 1936system.iocache.demand_avg_miss_latency::realview.ide 124754.637860 # average overall miss latency 1937system.iocache.demand_avg_miss_latency::total 124754.637860 # average overall miss latency 1938system.iocache.overall_avg_miss_latency::realview.ide 124754.637860 # average overall miss latency 1939system.iocache.overall_avg_miss_latency::total 124754.637860 # average overall miss latency 1940system.iocache.blocked_cycles::no_mshrs 57278 # number of cycles access was blocked | 2082system.iocache.ReadReq_avg_miss_latency::realview.ide 124915.131687 # average ReadReq miss latency 2083system.iocache.ReadReq_avg_miss_latency::total 124915.131687 # average ReadReq miss latency 2084system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265717.403462 # average WriteInvalidateReq miss latency 2085system.iocache.WriteInvalidateReq_avg_miss_latency::total 265717.403462 # average WriteInvalidateReq miss latency 2086system.iocache.demand_avg_miss_latency::realview.ide 124915.131687 # average overall miss latency 2087system.iocache.demand_avg_miss_latency::total 124915.131687 # average overall miss latency 2088system.iocache.overall_avg_miss_latency::realview.ide 124915.131687 # average overall miss latency 2089system.iocache.overall_avg_miss_latency::total 124915.131687 # average overall miss latency 2090system.iocache.blocked_cycles::no_mshrs 56938 # number of cycles access was blocked |
| 1941system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2091system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1942system.iocache.blocked::no_mshrs 7269 # number of cycles access was blocked | 2092system.iocache.blocked::no_mshrs 7266 # number of cycles access was blocked |
| 1943system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 2093system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1944system.iocache.avg_blocked_cycles::no_mshrs 7.879763 # average number of cycles each access was blocked | 2094system.iocache.avg_blocked_cycles::no_mshrs 7.836224 # average number of cycles each access was blocked |
| 1945system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1946system.iocache.fast_writes 0 # number of fast writes performed 1947system.iocache.cache_copies 0 # number of cache copies performed | 2095system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2096system.iocache.fast_writes 0 # number of fast writes performed 2097system.iocache.cache_copies 0 # number of cache copies performed |
| 1948system.iocache.writebacks::writebacks 36190 # number of writebacks 1949system.iocache.writebacks::total 36190 # number of writebacks | 2098system.iocache.writebacks::writebacks 36174 # number of writebacks 2099system.iocache.writebacks::total 36174 # number of writebacks |
| 1950system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses 1951system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses 1952system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 1953system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses 1954system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses 1955system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses 1956system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses 1957system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses | 2100system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses 2101system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses 2102system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 2103system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses 2104system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses 2105system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses 2106system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses 2107system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses |
| 1958system.iocache.ReadReq_mshr_miss_latency::realview.ide 17678377 # number of ReadReq MSHR miss cycles 1959system.iocache.ReadReq_mshr_miss_latency::total 17678377 # number of ReadReq MSHR miss cycles 1960system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7760326371 # number of WriteInvalidateReq MSHR miss cycles 1961system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7760326371 # number of WriteInvalidateReq MSHR miss cycles 1962system.iocache.demand_mshr_miss_latency::realview.ide 17678377 # number of demand (read+write) MSHR miss cycles 1963system.iocache.demand_mshr_miss_latency::total 17678377 # number of demand (read+write) MSHR miss cycles 1964system.iocache.overall_mshr_miss_latency::realview.ide 17678377 # number of overall MSHR miss cycles 1965system.iocache.overall_mshr_miss_latency::total 17678377 # number of overall MSHR miss cycles | 2108system.iocache.ReadReq_mshr_miss_latency::realview.ide 17717377 # number of ReadReq MSHR miss cycles 2109system.iocache.ReadReq_mshr_miss_latency::total 17717377 # number of ReadReq MSHR miss cycles 2110system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7741561361 # number of WriteInvalidateReq MSHR miss cycles 2111system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7741561361 # number of WriteInvalidateReq MSHR miss cycles 2112system.iocache.demand_mshr_miss_latency::realview.ide 17717377 # number of demand (read+write) MSHR miss cycles 2113system.iocache.demand_mshr_miss_latency::total 17717377 # number of demand (read+write) MSHR miss cycles 2114system.iocache.overall_mshr_miss_latency::realview.ide 17717377 # number of overall MSHR miss cycles 2115system.iocache.overall_mshr_miss_latency::total 17717377 # number of overall MSHR miss cycles |
| 1966system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1967system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1968system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1969system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1970system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1971system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1972system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1973system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 2116system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2117system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2118system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2119system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 2120system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2121system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2122system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2123system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1974system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72750.522634 # average ReadReq mshr miss latency 1975system.iocache.ReadReq_avg_mshr_miss_latency::total 72750.522634 # average ReadReq mshr miss latency 1976system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 214231.624641 # average WriteInvalidateReq mshr miss latency 1977system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 214231.624641 # average WriteInvalidateReq mshr miss latency 1978system.iocache.demand_avg_mshr_miss_latency::realview.ide 72750.522634 # average overall mshr miss latency 1979system.iocache.demand_avg_mshr_miss_latency::total 72750.522634 # average overall mshr miss latency 1980system.iocache.overall_avg_mshr_miss_latency::realview.ide 72750.522634 # average overall mshr miss latency 1981system.iocache.overall_avg_mshr_miss_latency::total 72750.522634 # average overall mshr miss latency | 2124system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72911.016461 # average ReadReq mshr miss latency 2125system.iocache.ReadReq_avg_mshr_miss_latency::total 72911.016461 # average ReadReq mshr miss latency 2126system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213713.597642 # average WriteInvalidateReq mshr miss latency 2127system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213713.597642 # average WriteInvalidateReq mshr miss latency 2128system.iocache.demand_avg_mshr_miss_latency::realview.ide 72911.016461 # average overall mshr miss latency 2129system.iocache.demand_avg_mshr_miss_latency::total 72911.016461 # average overall mshr miss latency 2130system.iocache.overall_avg_mshr_miss_latency::realview.ide 72911.016461 # average overall mshr miss latency 2131system.iocache.overall_avg_mshr_miss_latency::total 72911.016461 # average overall mshr miss latency |
| 1982system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 2132system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1983system.l2c.tags.replacements 150396 # number of replacements 1984system.l2c.tags.tagsinuse 64479.883220 # Cycle average of tags in use 1985system.l2c.tags.total_refs 522727 # Total number of references to valid blocks. 1986system.l2c.tags.sampled_refs 215317 # Sample count of references to valid blocks. 1987system.l2c.tags.avg_refs 2.427709 # Average number of references to valid blocks. | 2133system.l2c.tags.replacements 139153 # number of replacements 2134system.l2c.tags.tagsinuse 64176.379405 # Cycle average of tags in use 2135system.l2c.tags.total_refs 380612 # Total number of references to valid blocks. 2136system.l2c.tags.sampled_refs 203608 # Sample count of references to valid blocks. 2137system.l2c.tags.avg_refs 1.869337 # Average number of references to valid blocks. |
| 1988system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2138system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1989system.l2c.tags.occ_blocks::writebacks 12469.492368 # Average occupied blocks per requestor 1990system.l2c.tags.occ_blocks::cpu0.dtb.walker 93.733463 # Average occupied blocks per requestor 1991system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999899 # Average occupied blocks per requestor 1992system.l2c.tags.occ_blocks::cpu0.inst 3818.005633 # Average occupied blocks per requestor 1993system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42810.602787 # Average occupied blocks per requestor 1994system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.718540 # Average occupied blocks per requestor 1995system.l2c.tags.occ_blocks::cpu1.inst 732.215158 # Average occupied blocks per requestor 1996system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4549.115372 # Average occupied blocks per requestor 1997system.l2c.tags.occ_percent::writebacks 0.190269 # Average percentage of cache occupancy 1998system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001430 # Average percentage of cache occupancy 1999system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy 2000system.l2c.tags.occ_percent::cpu0.inst 0.058258 # Average percentage of cache occupancy 2001system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.653238 # Average percentage of cache occupancy 2002system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000087 # Average percentage of cache occupancy 2003system.l2c.tags.occ_percent::cpu1.inst 0.011173 # Average percentage of cache occupancy 2004system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.069414 # Average percentage of cache occupancy 2005system.l2c.tags.occ_percent::total 0.983885 # Average percentage of cache occupancy 2006system.l2c.tags.occ_task_id_blocks::1022 47457 # Occupied blocks per task id 2007system.l2c.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id 2008system.l2c.tags.occ_task_id_blocks::1024 17396 # Occupied blocks per task id 2009system.l2c.tags.age_task_id_blocks_1022::2 475 # Occupied blocks per task id 2010system.l2c.tags.age_task_id_blocks_1022::3 6086 # Occupied blocks per task id 2011system.l2c.tags.age_task_id_blocks_1022::4 40896 # Occupied blocks per task id | 2139system.l2c.tags.occ_blocks::writebacks 11502.485032 # Average occupied blocks per requestor 2140system.l2c.tags.occ_blocks::cpu0.dtb.walker 90.401142 # Average occupied blocks per requestor 2141system.l2c.tags.occ_blocks::cpu0.itb.walker 0.038214 # Average occupied blocks per requestor 2142system.l2c.tags.occ_blocks::cpu0.inst 12425.194881 # Average occupied blocks per requestor 2143system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 36413.661117 # Average occupied blocks per requestor 2144system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.683124 # Average occupied blocks per requestor 2145system.l2c.tags.occ_blocks::cpu1.inst 1856.879628 # Average occupied blocks per requestor 2146system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1880.036266 # Average occupied blocks per requestor 2147system.l2c.tags.occ_percent::writebacks 0.175514 # Average percentage of cache occupancy 2148system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001379 # Average percentage of cache occupancy 2149system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 2150system.l2c.tags.occ_percent::cpu0.inst 0.189593 # Average percentage of cache occupancy 2151system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.555628 # Average percentage of cache occupancy 2152system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000117 # Average percentage of cache occupancy 2153system.l2c.tags.occ_percent::cpu1.inst 0.028334 # Average percentage of cache occupancy 2154system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.028687 # Average percentage of cache occupancy 2155system.l2c.tags.occ_percent::total 0.979254 # Average percentage of cache occupancy 2156system.l2c.tags.occ_task_id_blocks::1022 31795 # Occupied blocks per task id 2157system.l2c.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id 2158system.l2c.tags.occ_task_id_blocks::1024 32593 # Occupied blocks per task id 2159system.l2c.tags.age_task_id_blocks_1022::2 145 # Occupied blocks per task id 2160system.l2c.tags.age_task_id_blocks_1022::3 5678 # Occupied blocks per task id 2161system.l2c.tags.age_task_id_blocks_1022::4 25972 # Occupied blocks per task id |
| 2012system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id | 2162system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id |
| 2013system.l2c.tags.age_task_id_blocks_1023::4 67 # Occupied blocks per task id | 2163system.l2c.tags.age_task_id_blocks_1023::4 66 # Occupied blocks per task id |
| 2014system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id | 2164system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id |
| 2015system.l2c.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id 2016system.l2c.tags.age_task_id_blocks_1024::2 270 # Occupied blocks per task id 2017system.l2c.tags.age_task_id_blocks_1024::3 2310 # Occupied blocks per task id 2018system.l2c.tags.age_task_id_blocks_1024::4 14797 # Occupied blocks per task id 2019system.l2c.tags.occ_task_id_percent::1022 0.724136 # Percentage of cache occupancy per task id 2020system.l2c.tags.occ_task_id_percent::1023 0.001038 # Percentage of cache occupancy per task id 2021system.l2c.tags.occ_task_id_percent::1024 0.265442 # Percentage of cache occupancy per task id 2022system.l2c.tags.tag_accesses 6561930 # Number of tag accesses 2023system.l2c.tags.data_accesses 6561930 # Number of data accesses 2024system.l2c.ReadReq_hits::cpu0.dtb.walker 576 # number of ReadReq hits 2025system.l2c.ReadReq_hits::cpu0.itb.walker 131 # number of ReadReq hits 2026system.l2c.ReadReq_hits::cpu0.inst 39519 # number of ReadReq hits 2027system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 221242 # number of ReadReq hits 2028system.l2c.ReadReq_hits::cpu1.dtb.walker 94 # number of ReadReq hits 2029system.l2c.ReadReq_hits::cpu1.itb.walker 19 # number of ReadReq hits 2030system.l2c.ReadReq_hits::cpu1.inst 6900 # number of ReadReq hits 2031system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 25945 # number of ReadReq hits 2032system.l2c.ReadReq_hits::total 294426 # number of ReadReq hits 2033system.l2c.Writeback_hits::writebacks 250431 # number of Writeback hits 2034system.l2c.Writeback_hits::total 250431 # number of Writeback hits 2035system.l2c.UpgradeReq_hits::cpu0.inst 11782 # number of UpgradeReq hits 2036system.l2c.UpgradeReq_hits::cpu1.inst 481 # number of UpgradeReq hits 2037system.l2c.UpgradeReq_hits::total 12263 # number of UpgradeReq hits 2038system.l2c.SCUpgradeReq_hits::cpu0.inst 184 # number of SCUpgradeReq hits 2039system.l2c.SCUpgradeReq_hits::cpu1.inst 192 # number of SCUpgradeReq hits 2040system.l2c.SCUpgradeReq_hits::total 376 # number of SCUpgradeReq hits 2041system.l2c.ReadExReq_hits::cpu0.inst 3646 # number of ReadExReq hits 2042system.l2c.ReadExReq_hits::cpu1.inst 908 # number of ReadExReq hits 2043system.l2c.ReadExReq_hits::total 4554 # number of ReadExReq hits 2044system.l2c.demand_hits::cpu0.dtb.walker 576 # number of demand (read+write) hits 2045system.l2c.demand_hits::cpu0.itb.walker 131 # number of demand (read+write) hits 2046system.l2c.demand_hits::cpu0.inst 43165 # number of demand (read+write) hits 2047system.l2c.demand_hits::cpu0.l2cache.prefetcher 221242 # number of demand (read+write) hits 2048system.l2c.demand_hits::cpu1.dtb.walker 94 # number of demand (read+write) hits 2049system.l2c.demand_hits::cpu1.itb.walker 19 # number of demand (read+write) hits 2050system.l2c.demand_hits::cpu1.inst 7808 # number of demand (read+write) hits 2051system.l2c.demand_hits::cpu1.l2cache.prefetcher 25945 # number of demand (read+write) hits 2052system.l2c.demand_hits::total 298980 # number of demand (read+write) hits 2053system.l2c.overall_hits::cpu0.dtb.walker 576 # number of overall hits 2054system.l2c.overall_hits::cpu0.itb.walker 131 # number of overall hits 2055system.l2c.overall_hits::cpu0.inst 43165 # number of overall hits 2056system.l2c.overall_hits::cpu0.l2cache.prefetcher 221242 # number of overall hits 2057system.l2c.overall_hits::cpu1.dtb.walker 94 # number of overall hits 2058system.l2c.overall_hits::cpu1.itb.walker 19 # number of overall hits 2059system.l2c.overall_hits::cpu1.inst 7808 # number of overall hits 2060system.l2c.overall_hits::cpu1.l2cache.prefetcher 25945 # number of overall hits 2061system.l2c.overall_hits::total 298980 # number of overall hits 2062system.l2c.ReadReq_misses::cpu0.dtb.walker 161 # number of ReadReq misses | 2165system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id 2166system.l2c.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id 2167system.l2c.tags.age_task_id_blocks_1024::3 3295 # Occupied blocks per task id 2168system.l2c.tags.age_task_id_blocks_1024::4 28977 # Occupied blocks per task id 2169system.l2c.tags.occ_task_id_percent::1022 0.485153 # Percentage of cache occupancy per task id 2170system.l2c.tags.occ_task_id_percent::1023 0.001022 # Percentage of cache occupancy per task id 2171system.l2c.tags.occ_task_id_percent::1024 0.497330 # Percentage of cache occupancy per task id 2172system.l2c.tags.tag_accesses 5313847 # Number of tag accesses 2173system.l2c.tags.data_accesses 5313847 # Number of data accesses 2174system.l2c.ReadReq_hits::cpu0.dtb.walker 426 # number of ReadReq hits 2175system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits 2176system.l2c.ReadReq_hits::cpu0.inst 70654 # number of ReadReq hits 2177system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 75814 # number of ReadReq hits 2178system.l2c.ReadReq_hits::cpu1.dtb.walker 118 # number of ReadReq hits 2179system.l2c.ReadReq_hits::cpu1.itb.walker 32 # number of ReadReq hits 2180system.l2c.ReadReq_hits::cpu1.inst 24007 # number of ReadReq hits 2181system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7439 # number of ReadReq hits 2182system.l2c.ReadReq_hits::total 178553 # number of ReadReq hits 2183system.l2c.Writeback_hits::writebacks 234152 # number of Writeback hits 2184system.l2c.Writeback_hits::total 234152 # number of Writeback hits 2185system.l2c.UpgradeReq_hits::cpu0.inst 2938 # number of UpgradeReq hits 2186system.l2c.UpgradeReq_hits::cpu1.inst 658 # number of UpgradeReq hits 2187system.l2c.UpgradeReq_hits::total 3596 # number of UpgradeReq hits 2188system.l2c.SCUpgradeReq_hits::cpu0.inst 142 # number of SCUpgradeReq hits 2189system.l2c.SCUpgradeReq_hits::cpu1.inst 176 # number of SCUpgradeReq hits 2190system.l2c.SCUpgradeReq_hits::total 318 # number of SCUpgradeReq hits 2191system.l2c.ReadExReq_hits::cpu0.inst 3842 # number of ReadExReq hits 2192system.l2c.ReadExReq_hits::cpu1.inst 1332 # number of ReadExReq hits 2193system.l2c.ReadExReq_hits::total 5174 # number of ReadExReq hits 2194system.l2c.demand_hits::cpu0.dtb.walker 426 # number of demand (read+write) hits 2195system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits 2196system.l2c.demand_hits::cpu0.inst 74496 # number of demand (read+write) hits 2197system.l2c.demand_hits::cpu0.l2cache.prefetcher 75814 # number of demand (read+write) hits 2198system.l2c.demand_hits::cpu1.dtb.walker 118 # number of demand (read+write) hits 2199system.l2c.demand_hits::cpu1.itb.walker 32 # number of demand (read+write) hits 2200system.l2c.demand_hits::cpu1.inst 25339 # number of demand (read+write) hits 2201system.l2c.demand_hits::cpu1.l2cache.prefetcher 7439 # number of demand (read+write) hits 2202system.l2c.demand_hits::total 183727 # number of demand (read+write) hits 2203system.l2c.overall_hits::cpu0.dtb.walker 426 # number of overall hits 2204system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits 2205system.l2c.overall_hits::cpu0.inst 74496 # number of overall hits 2206system.l2c.overall_hits::cpu0.l2cache.prefetcher 75814 # number of overall hits 2207system.l2c.overall_hits::cpu1.dtb.walker 118 # number of overall hits 2208system.l2c.overall_hits::cpu1.itb.walker 32 # number of overall hits 2209system.l2c.overall_hits::cpu1.inst 25339 # number of overall hits 2210system.l2c.overall_hits::cpu1.l2cache.prefetcher 7439 # number of overall hits 2211system.l2c.overall_hits::total 183727 # number of overall hits 2212system.l2c.ReadReq_misses::cpu0.dtb.walker 162 # number of ReadReq misses |
| 2063system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses | 2213system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses |
| 2064system.l2c.ReadReq_misses::cpu0.inst 11256 # number of ReadReq misses 2065system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 169617 # number of ReadReq misses 2066system.l2c.ReadReq_misses::cpu1.dtb.walker 8 # number of ReadReq misses 2067system.l2c.ReadReq_misses::cpu1.inst 1341 # number of ReadReq misses 2068system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 17501 # number of ReadReq misses 2069system.l2c.ReadReq_misses::total 199885 # number of ReadReq misses 2070system.l2c.UpgradeReq_misses::cpu0.inst 9580 # number of UpgradeReq misses 2071system.l2c.UpgradeReq_misses::cpu1.inst 2241 # number of UpgradeReq misses 2072system.l2c.UpgradeReq_misses::total 11821 # number of UpgradeReq misses 2073system.l2c.SCUpgradeReq_misses::cpu0.inst 527 # number of SCUpgradeReq misses 2074system.l2c.SCUpgradeReq_misses::cpu1.inst 1214 # number of SCUpgradeReq misses 2075system.l2c.SCUpgradeReq_misses::total 1741 # number of SCUpgradeReq misses 2076system.l2c.ReadExReq_misses::cpu0.inst 6969 # number of ReadExReq misses 2077system.l2c.ReadExReq_misses::cpu1.inst 6429 # number of ReadExReq misses 2078system.l2c.ReadExReq_misses::total 13398 # number of ReadExReq misses 2079system.l2c.demand_misses::cpu0.dtb.walker 161 # number of demand (read+write) misses | 2214system.l2c.ReadReq_misses::cpu0.inst 32548 # number of ReadReq misses 2215system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 136690 # number of ReadReq misses 2216system.l2c.ReadReq_misses::cpu1.dtb.walker 12 # number of ReadReq misses 2217system.l2c.ReadReq_misses::cpu1.inst 3333 # number of ReadReq misses 2218system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 6249 # number of ReadReq misses 2219system.l2c.ReadReq_misses::total 178995 # number of ReadReq misses 2220system.l2c.UpgradeReq_misses::cpu0.inst 8970 # number of UpgradeReq misses 2221system.l2c.UpgradeReq_misses::cpu1.inst 2734 # number of UpgradeReq misses 2222system.l2c.UpgradeReq_misses::total 11704 # number of UpgradeReq misses 2223system.l2c.SCUpgradeReq_misses::cpu0.inst 618 # number of SCUpgradeReq misses 2224system.l2c.SCUpgradeReq_misses::cpu1.inst 1189 # number of SCUpgradeReq misses 2225system.l2c.SCUpgradeReq_misses::total 1807 # number of SCUpgradeReq misses 2226system.l2c.ReadExReq_misses::cpu0.inst 11575 # number of ReadExReq misses 2227system.l2c.ReadExReq_misses::cpu1.inst 8676 # number of ReadExReq misses 2228system.l2c.ReadExReq_misses::total 20251 # number of ReadExReq misses 2229system.l2c.demand_misses::cpu0.dtb.walker 162 # number of demand (read+write) misses |
| 2080system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses | 2230system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses |
| 2081system.l2c.demand_misses::cpu0.inst 18225 # number of demand (read+write) misses 2082system.l2c.demand_misses::cpu0.l2cache.prefetcher 169617 # number of demand (read+write) misses 2083system.l2c.demand_misses::cpu1.dtb.walker 8 # number of demand (read+write) misses 2084system.l2c.demand_misses::cpu1.inst 7770 # number of demand (read+write) misses 2085system.l2c.demand_misses::cpu1.l2cache.prefetcher 17501 # number of demand (read+write) misses 2086system.l2c.demand_misses::total 213283 # number of demand (read+write) misses 2087system.l2c.overall_misses::cpu0.dtb.walker 161 # number of overall misses | 2231system.l2c.demand_misses::cpu0.inst 44123 # number of demand (read+write) misses 2232system.l2c.demand_misses::cpu0.l2cache.prefetcher 136690 # number of demand (read+write) misses 2233system.l2c.demand_misses::cpu1.dtb.walker 12 # number of demand (read+write) misses 2234system.l2c.demand_misses::cpu1.inst 12009 # number of demand (read+write) misses 2235system.l2c.demand_misses::cpu1.l2cache.prefetcher 6249 # number of demand (read+write) misses 2236system.l2c.demand_misses::total 199246 # number of demand (read+write) misses 2237system.l2c.overall_misses::cpu0.dtb.walker 162 # number of overall misses |
| 2088system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses | 2238system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses |
| 2089system.l2c.overall_misses::cpu0.inst 18225 # number of overall misses 2090system.l2c.overall_misses::cpu0.l2cache.prefetcher 169617 # number of overall misses 2091system.l2c.overall_misses::cpu1.dtb.walker 8 # number of overall misses 2092system.l2c.overall_misses::cpu1.inst 7770 # number of overall misses 2093system.l2c.overall_misses::cpu1.l2cache.prefetcher 17501 # number of overall misses 2094system.l2c.overall_misses::total 213283 # number of overall misses 2095system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 12824000 # number of ReadReq miss cycles | 2239system.l2c.overall_misses::cpu0.inst 44123 # number of overall misses 2240system.l2c.overall_misses::cpu0.l2cache.prefetcher 136690 # number of overall misses 2241system.l2c.overall_misses::cpu1.dtb.walker 12 # number of overall misses 2242system.l2c.overall_misses::cpu1.inst 12009 # number of overall misses 2243system.l2c.overall_misses::cpu1.l2cache.prefetcher 6249 # number of overall misses 2244system.l2c.overall_misses::total 199246 # number of overall misses 2245system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 12996250 # number of ReadReq miss cycles |
| 2096system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles | 2246system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles |
| 2097system.l2c.ReadReq_miss_latency::cpu0.inst 957656246 # number of ReadReq miss cycles 2098system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18265787207 # number of ReadReq miss cycles 2099system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 597000 # number of ReadReq miss cycles 2100system.l2c.ReadReq_miss_latency::cpu1.inst 113197750 # number of ReadReq miss cycles 2101system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 1914570464 # number of ReadReq miss cycles 2102system.l2c.ReadReq_miss_latency::total 21264707667 # number of ReadReq miss cycles 2103system.l2c.UpgradeReq_miss_latency::cpu0.inst 10249624 # number of UpgradeReq miss cycles 2104system.l2c.UpgradeReq_miss_latency::cpu1.inst 2389898 # number of UpgradeReq miss cycles 2105system.l2c.UpgradeReq_miss_latency::total 12639522 # number of UpgradeReq miss cycles 2106system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 1315451 # number of SCUpgradeReq miss cycles 2107system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 1074955 # number of SCUpgradeReq miss cycles 2108system.l2c.SCUpgradeReq_miss_latency::total 2390406 # number of SCUpgradeReq miss cycles 2109system.l2c.ReadExReq_miss_latency::cpu0.inst 593841904 # number of ReadExReq miss cycles 2110system.l2c.ReadExReq_miss_latency::cpu1.inst 477642745 # number of ReadExReq miss cycles 2111system.l2c.ReadExReq_miss_latency::total 1071484649 # number of ReadExReq miss cycles 2112system.l2c.demand_miss_latency::cpu0.dtb.walker 12824000 # number of demand (read+write) miss cycles | 2247system.l2c.ReadReq_miss_latency::cpu0.inst 2445317489 # number of ReadReq miss cycles 2248system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 14069068891 # number of ReadReq miss cycles 2249system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 960250 # number of ReadReq miss cycles 2250system.l2c.ReadReq_miss_latency::cpu1.inst 258262249 # number of ReadReq miss cycles 2251system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 826051791 # number of ReadReq miss cycles 2252system.l2c.ReadReq_miss_latency::total 17612731920 # number of ReadReq miss cycles 2253system.l2c.UpgradeReq_miss_latency::cpu0.inst 7054791 # number of UpgradeReq miss cycles 2254system.l2c.UpgradeReq_miss_latency::cpu1.inst 1587933 # number of UpgradeReq miss cycles 2255system.l2c.UpgradeReq_miss_latency::total 8642724 # number of UpgradeReq miss cycles 2256system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 937466 # number of SCUpgradeReq miss cycles 2257system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 512978 # number of SCUpgradeReq miss cycles 2258system.l2c.SCUpgradeReq_miss_latency::total 1450444 # number of SCUpgradeReq miss cycles 2259system.l2c.ReadExReq_miss_latency::cpu0.inst 952737665 # number of ReadExReq miss cycles 2260system.l2c.ReadExReq_miss_latency::cpu1.inst 639334486 # number of ReadExReq miss cycles 2261system.l2c.ReadExReq_miss_latency::total 1592072151 # number of ReadExReq miss cycles 2262system.l2c.demand_miss_latency::cpu0.dtb.walker 12996250 # number of demand (read+write) miss cycles |
| 2113system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles | 2263system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles |
| 2114system.l2c.demand_miss_latency::cpu0.inst 1551498150 # number of demand (read+write) miss cycles 2115system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18265787207 # number of demand (read+write) miss cycles 2116system.l2c.demand_miss_latency::cpu1.dtb.walker 597000 # number of demand (read+write) miss cycles 2117system.l2c.demand_miss_latency::cpu1.inst 590840495 # number of demand (read+write) miss cycles 2118system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1914570464 # number of demand (read+write) miss cycles 2119system.l2c.demand_miss_latency::total 22336192316 # number of demand (read+write) miss cycles 2120system.l2c.overall_miss_latency::cpu0.dtb.walker 12824000 # number of overall miss cycles | 2264system.l2c.demand_miss_latency::cpu0.inst 3398055154 # number of demand (read+write) miss cycles 2265system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14069068891 # number of demand (read+write) miss cycles 2266system.l2c.demand_miss_latency::cpu1.dtb.walker 960250 # number of demand (read+write) miss cycles 2267system.l2c.demand_miss_latency::cpu1.inst 897596735 # number of demand (read+write) miss cycles 2268system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 826051791 # number of demand (read+write) miss cycles 2269system.l2c.demand_miss_latency::total 19204804071 # number of demand (read+write) miss cycles 2270system.l2c.overall_miss_latency::cpu0.dtb.walker 12996250 # number of overall miss cycles |
| 2121system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles | 2271system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles |
| 2122system.l2c.overall_miss_latency::cpu0.inst 1551498150 # number of overall miss cycles 2123system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18265787207 # number of overall miss cycles 2124system.l2c.overall_miss_latency::cpu1.dtb.walker 597000 # number of overall miss cycles 2125system.l2c.overall_miss_latency::cpu1.inst 590840495 # number of overall miss cycles 2126system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1914570464 # number of overall miss cycles 2127system.l2c.overall_miss_latency::total 22336192316 # number of overall miss cycles 2128system.l2c.ReadReq_accesses::cpu0.dtb.walker 737 # number of ReadReq accesses(hits+misses) 2129system.l2c.ReadReq_accesses::cpu0.itb.walker 132 # number of ReadReq accesses(hits+misses) 2130system.l2c.ReadReq_accesses::cpu0.inst 50775 # number of ReadReq accesses(hits+misses) 2131system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 390859 # number of ReadReq accesses(hits+misses) 2132system.l2c.ReadReq_accesses::cpu1.dtb.walker 102 # number of ReadReq accesses(hits+misses) 2133system.l2c.ReadReq_accesses::cpu1.itb.walker 19 # number of ReadReq accesses(hits+misses) 2134system.l2c.ReadReq_accesses::cpu1.inst 8241 # number of ReadReq accesses(hits+misses) 2135system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 43446 # number of ReadReq accesses(hits+misses) 2136system.l2c.ReadReq_accesses::total 494311 # number of ReadReq accesses(hits+misses) 2137system.l2c.Writeback_accesses::writebacks 250431 # number of Writeback accesses(hits+misses) 2138system.l2c.Writeback_accesses::total 250431 # number of Writeback accesses(hits+misses) 2139system.l2c.UpgradeReq_accesses::cpu0.inst 21362 # number of UpgradeReq accesses(hits+misses) 2140system.l2c.UpgradeReq_accesses::cpu1.inst 2722 # number of UpgradeReq accesses(hits+misses) 2141system.l2c.UpgradeReq_accesses::total 24084 # number of UpgradeReq accesses(hits+misses) 2142system.l2c.SCUpgradeReq_accesses::cpu0.inst 711 # number of SCUpgradeReq accesses(hits+misses) 2143system.l2c.SCUpgradeReq_accesses::cpu1.inst 1406 # number of SCUpgradeReq accesses(hits+misses) 2144system.l2c.SCUpgradeReq_accesses::total 2117 # number of SCUpgradeReq accesses(hits+misses) 2145system.l2c.ReadExReq_accesses::cpu0.inst 10615 # number of ReadExReq accesses(hits+misses) 2146system.l2c.ReadExReq_accesses::cpu1.inst 7337 # number of ReadExReq accesses(hits+misses) 2147system.l2c.ReadExReq_accesses::total 17952 # number of ReadExReq accesses(hits+misses) 2148system.l2c.demand_accesses::cpu0.dtb.walker 737 # number of demand (read+write) accesses 2149system.l2c.demand_accesses::cpu0.itb.walker 132 # number of demand (read+write) accesses 2150system.l2c.demand_accesses::cpu0.inst 61390 # number of demand (read+write) accesses 2151system.l2c.demand_accesses::cpu0.l2cache.prefetcher 390859 # number of demand (read+write) accesses 2152system.l2c.demand_accesses::cpu1.dtb.walker 102 # number of demand (read+write) accesses 2153system.l2c.demand_accesses::cpu1.itb.walker 19 # number of demand (read+write) accesses 2154system.l2c.demand_accesses::cpu1.inst 15578 # number of demand (read+write) accesses 2155system.l2c.demand_accesses::cpu1.l2cache.prefetcher 43446 # number of demand (read+write) accesses 2156system.l2c.demand_accesses::total 512263 # number of demand (read+write) accesses 2157system.l2c.overall_accesses::cpu0.dtb.walker 737 # number of overall (read+write) accesses 2158system.l2c.overall_accesses::cpu0.itb.walker 132 # number of overall (read+write) accesses 2159system.l2c.overall_accesses::cpu0.inst 61390 # number of overall (read+write) accesses 2160system.l2c.overall_accesses::cpu0.l2cache.prefetcher 390859 # number of overall (read+write) accesses 2161system.l2c.overall_accesses::cpu1.dtb.walker 102 # number of overall (read+write) accesses 2162system.l2c.overall_accesses::cpu1.itb.walker 19 # number of overall (read+write) accesses 2163system.l2c.overall_accesses::cpu1.inst 15578 # number of overall (read+write) accesses 2164system.l2c.overall_accesses::cpu1.l2cache.prefetcher 43446 # number of overall (read+write) accesses 2165system.l2c.overall_accesses::total 512263 # number of overall (read+write) accesses 2166system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.218453 # miss rate for ReadReq accesses 2167system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.007576 # miss rate for ReadReq accesses 2168system.l2c.ReadReq_miss_rate::cpu0.inst 0.221684 # miss rate for ReadReq accesses 2169system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.433960 # miss rate for ReadReq accesses 2170system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.078431 # miss rate for ReadReq accesses 2171system.l2c.ReadReq_miss_rate::cpu1.inst 0.162723 # miss rate for ReadReq accesses 2172system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.402822 # miss rate for ReadReq accesses 2173system.l2c.ReadReq_miss_rate::total 0.404371 # miss rate for ReadReq accesses 2174system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.448460 # miss rate for UpgradeReq accesses 2175system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.823292 # miss rate for UpgradeReq accesses 2176system.l2c.UpgradeReq_miss_rate::total 0.490824 # miss rate for UpgradeReq accesses 2177system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.741210 # miss rate for SCUpgradeReq accesses 2178system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.863442 # miss rate for SCUpgradeReq accesses 2179system.l2c.SCUpgradeReq_miss_rate::total 0.822390 # miss rate for SCUpgradeReq accesses 2180system.l2c.ReadExReq_miss_rate::cpu0.inst 0.656524 # miss rate for ReadExReq accesses 2181system.l2c.ReadExReq_miss_rate::cpu1.inst 0.876244 # miss rate for ReadExReq accesses 2182system.l2c.ReadExReq_miss_rate::total 0.746324 # miss rate for ReadExReq accesses 2183system.l2c.demand_miss_rate::cpu0.dtb.walker 0.218453 # miss rate for demand accesses 2184system.l2c.demand_miss_rate::cpu0.itb.walker 0.007576 # miss rate for demand accesses 2185system.l2c.demand_miss_rate::cpu0.inst 0.296872 # miss rate for demand accesses 2186system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.433960 # miss rate for demand accesses 2187system.l2c.demand_miss_rate::cpu1.dtb.walker 0.078431 # miss rate for demand accesses 2188system.l2c.demand_miss_rate::cpu1.inst 0.498780 # miss rate for demand accesses 2189system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.402822 # miss rate for demand accesses 2190system.l2c.demand_miss_rate::total 0.416354 # miss rate for demand accesses 2191system.l2c.overall_miss_rate::cpu0.dtb.walker 0.218453 # miss rate for overall accesses 2192system.l2c.overall_miss_rate::cpu0.itb.walker 0.007576 # miss rate for overall accesses 2193system.l2c.overall_miss_rate::cpu0.inst 0.296872 # miss rate for overall accesses 2194system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.433960 # miss rate for overall accesses 2195system.l2c.overall_miss_rate::cpu1.dtb.walker 0.078431 # miss rate for overall accesses 2196system.l2c.overall_miss_rate::cpu1.inst 0.498780 # miss rate for overall accesses 2197system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.402822 # miss rate for overall accesses 2198system.l2c.overall_miss_rate::total 0.416354 # miss rate for overall accesses 2199system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79652.173913 # average ReadReq miss latency | 2272system.l2c.overall_miss_latency::cpu0.inst 3398055154 # number of overall miss cycles 2273system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14069068891 # number of overall miss cycles 2274system.l2c.overall_miss_latency::cpu1.dtb.walker 960250 # number of overall miss cycles 2275system.l2c.overall_miss_latency::cpu1.inst 897596735 # number of overall miss cycles 2276system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 826051791 # number of overall miss cycles 2277system.l2c.overall_miss_latency::total 19204804071 # number of overall miss cycles 2278system.l2c.ReadReq_accesses::cpu0.dtb.walker 588 # number of ReadReq accesses(hits+misses) 2279system.l2c.ReadReq_accesses::cpu0.itb.walker 64 # number of ReadReq accesses(hits+misses) 2280system.l2c.ReadReq_accesses::cpu0.inst 103202 # number of ReadReq accesses(hits+misses) 2281system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 212504 # number of ReadReq accesses(hits+misses) 2282system.l2c.ReadReq_accesses::cpu1.dtb.walker 130 # number of ReadReq accesses(hits+misses) 2283system.l2c.ReadReq_accesses::cpu1.itb.walker 32 # number of ReadReq accesses(hits+misses) 2284system.l2c.ReadReq_accesses::cpu1.inst 27340 # number of ReadReq accesses(hits+misses) 2285system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 13688 # number of ReadReq accesses(hits+misses) 2286system.l2c.ReadReq_accesses::total 357548 # number of ReadReq accesses(hits+misses) 2287system.l2c.Writeback_accesses::writebacks 234152 # number of Writeback accesses(hits+misses) 2288system.l2c.Writeback_accesses::total 234152 # number of Writeback accesses(hits+misses) 2289system.l2c.UpgradeReq_accesses::cpu0.inst 11908 # number of UpgradeReq accesses(hits+misses) 2290system.l2c.UpgradeReq_accesses::cpu1.inst 3392 # number of UpgradeReq accesses(hits+misses) 2291system.l2c.UpgradeReq_accesses::total 15300 # number of UpgradeReq accesses(hits+misses) 2292system.l2c.SCUpgradeReq_accesses::cpu0.inst 760 # number of SCUpgradeReq accesses(hits+misses) 2293system.l2c.SCUpgradeReq_accesses::cpu1.inst 1365 # number of SCUpgradeReq accesses(hits+misses) 2294system.l2c.SCUpgradeReq_accesses::total 2125 # number of SCUpgradeReq accesses(hits+misses) 2295system.l2c.ReadExReq_accesses::cpu0.inst 15417 # number of ReadExReq accesses(hits+misses) 2296system.l2c.ReadExReq_accesses::cpu1.inst 10008 # number of ReadExReq accesses(hits+misses) 2297system.l2c.ReadExReq_accesses::total 25425 # number of ReadExReq accesses(hits+misses) 2298system.l2c.demand_accesses::cpu0.dtb.walker 588 # number of demand (read+write) accesses 2299system.l2c.demand_accesses::cpu0.itb.walker 64 # number of demand (read+write) accesses 2300system.l2c.demand_accesses::cpu0.inst 118619 # number of demand (read+write) accesses 2301system.l2c.demand_accesses::cpu0.l2cache.prefetcher 212504 # number of demand (read+write) accesses 2302system.l2c.demand_accesses::cpu1.dtb.walker 130 # number of demand (read+write) accesses 2303system.l2c.demand_accesses::cpu1.itb.walker 32 # number of demand (read+write) accesses 2304system.l2c.demand_accesses::cpu1.inst 37348 # number of demand (read+write) accesses 2305system.l2c.demand_accesses::cpu1.l2cache.prefetcher 13688 # number of demand (read+write) accesses 2306system.l2c.demand_accesses::total 382973 # number of demand (read+write) accesses 2307system.l2c.overall_accesses::cpu0.dtb.walker 588 # number of overall (read+write) accesses 2308system.l2c.overall_accesses::cpu0.itb.walker 64 # number of overall (read+write) accesses 2309system.l2c.overall_accesses::cpu0.inst 118619 # number of overall (read+write) accesses 2310system.l2c.overall_accesses::cpu0.l2cache.prefetcher 212504 # number of overall (read+write) accesses 2311system.l2c.overall_accesses::cpu1.dtb.walker 130 # number of overall (read+write) accesses 2312system.l2c.overall_accesses::cpu1.itb.walker 32 # number of overall (read+write) accesses 2313system.l2c.overall_accesses::cpu1.inst 37348 # number of overall (read+write) accesses 2314system.l2c.overall_accesses::cpu1.l2cache.prefetcher 13688 # number of overall (read+write) accesses 2315system.l2c.overall_accesses::total 382973 # number of overall (read+write) accesses 2316system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.275510 # miss rate for ReadReq accesses 2317system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.015625 # miss rate for ReadReq accesses 2318system.l2c.ReadReq_miss_rate::cpu0.inst 0.315381 # miss rate for ReadReq accesses 2319system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.643235 # miss rate for ReadReq accesses 2320system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.092308 # miss rate for ReadReq accesses 2321system.l2c.ReadReq_miss_rate::cpu1.inst 0.121909 # miss rate for ReadReq accesses 2322system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.456531 # miss rate for ReadReq accesses 2323system.l2c.ReadReq_miss_rate::total 0.500618 # miss rate for ReadReq accesses 2324system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.753275 # miss rate for UpgradeReq accesses 2325system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.806014 # miss rate for UpgradeReq accesses 2326system.l2c.UpgradeReq_miss_rate::total 0.764967 # miss rate for UpgradeReq accesses 2327system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.813158 # miss rate for SCUpgradeReq accesses 2328system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.871062 # miss rate for SCUpgradeReq accesses 2329system.l2c.SCUpgradeReq_miss_rate::total 0.850353 # miss rate for SCUpgradeReq accesses 2330system.l2c.ReadExReq_miss_rate::cpu0.inst 0.750795 # miss rate for ReadExReq accesses 2331system.l2c.ReadExReq_miss_rate::cpu1.inst 0.866906 # miss rate for ReadExReq accesses 2332system.l2c.ReadExReq_miss_rate::total 0.796500 # miss rate for ReadExReq accesses 2333system.l2c.demand_miss_rate::cpu0.dtb.walker 0.275510 # miss rate for demand accesses 2334system.l2c.demand_miss_rate::cpu0.itb.walker 0.015625 # miss rate for demand accesses 2335system.l2c.demand_miss_rate::cpu0.inst 0.371972 # miss rate for demand accesses 2336system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.643235 # miss rate for demand accesses 2337system.l2c.demand_miss_rate::cpu1.dtb.walker 0.092308 # miss rate for demand accesses 2338system.l2c.demand_miss_rate::cpu1.inst 0.321543 # miss rate for demand accesses 2339system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.456531 # miss rate for demand accesses 2340system.l2c.demand_miss_rate::total 0.520261 # miss rate for demand accesses 2341system.l2c.overall_miss_rate::cpu0.dtb.walker 0.275510 # miss rate for overall accesses 2342system.l2c.overall_miss_rate::cpu0.itb.walker 0.015625 # miss rate for overall accesses 2343system.l2c.overall_miss_rate::cpu0.inst 0.371972 # miss rate for overall accesses 2344system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.643235 # miss rate for overall accesses 2345system.l2c.overall_miss_rate::cpu1.dtb.walker 0.092308 # miss rate for overall accesses 2346system.l2c.overall_miss_rate::cpu1.inst 0.321543 # miss rate for overall accesses 2347system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.456531 # miss rate for overall accesses 2348system.l2c.overall_miss_rate::total 0.520261 # miss rate for overall accesses 2349system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80223.765432 # average ReadReq miss latency |
| 2200system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency | 2350system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency |
| 2201system.l2c.ReadReq_avg_miss_latency::cpu0.inst 85079.623845 # average ReadReq miss latency 2202system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107688.422782 # average ReadReq miss latency 2203system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74625 # average ReadReq miss latency 2204system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84412.938106 # average ReadReq miss latency 2205system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 109397.775213 # average ReadReq miss latency 2206system.l2c.ReadReq_avg_miss_latency::total 106384.709543 # average ReadReq miss latency 2207system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1069.898121 # average UpgradeReq miss latency 2208system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1066.442660 # average UpgradeReq miss latency 2209system.l2c.UpgradeReq_avg_miss_latency::total 1069.243042 # average UpgradeReq miss latency 2210system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 2496.111954 # average SCUpgradeReq miss latency 2211system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 885.465404 # average SCUpgradeReq miss latency 2212system.l2c.SCUpgradeReq_avg_miss_latency::total 1373.007467 # average SCUpgradeReq miss latency 2213system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 85211.924810 # average ReadExReq miss latency 2214system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74295.029554 # average ReadExReq miss latency 2215system.l2c.ReadExReq_avg_miss_latency::total 79973.477310 # average ReadExReq miss latency 2216system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79652.173913 # average overall miss latency | 2351system.l2c.ReadReq_avg_miss_latency::cpu0.inst 75129.577516 # average ReadReq miss latency 2352system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 102926.833645 # average ReadReq miss latency 2353system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 80020.833333 # average ReadReq miss latency 2354system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77486.423342 # average ReadReq miss latency 2355system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 132189.436870 # average ReadReq miss latency 2356system.l2c.ReadReq_avg_miss_latency::total 98397.898936 # average ReadReq miss latency 2357system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 786.487291 # average UpgradeReq miss latency 2358system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 580.809437 # average UpgradeReq miss latency 2359system.l2c.UpgradeReq_avg_miss_latency::total 738.441900 # average UpgradeReq miss latency 2360system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 1516.935275 # average SCUpgradeReq miss latency 2361system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 431.436501 # average SCUpgradeReq miss latency 2362system.l2c.SCUpgradeReq_avg_miss_latency::total 802.680686 # average SCUpgradeReq miss latency 2363system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 82309.949460 # average ReadExReq miss latency 2364system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 73690.005302 # average ReadExReq miss latency 2365system.l2c.ReadExReq_avg_miss_latency::total 78616.964644 # average ReadExReq miss latency 2366system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80223.765432 # average overall miss latency |
| 2217system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency | 2367system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency |
| 2218system.l2c.demand_avg_miss_latency::cpu0.inst 85130.213992 # average overall miss latency 2219system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107688.422782 # average overall miss latency 2220system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74625 # average overall miss latency 2221system.l2c.demand_avg_miss_latency::cpu1.inst 76041.247748 # average overall miss latency 2222system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109397.775213 # average overall miss latency 2223system.l2c.demand_avg_miss_latency::total 104725.610180 # average overall miss latency 2224system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79652.173913 # average overall miss latency | 2368system.l2c.demand_avg_miss_latency::cpu0.inst 77013.239218 # average overall miss latency 2369system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 102926.833645 # average overall miss latency 2370system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80020.833333 # average overall miss latency 2371system.l2c.demand_avg_miss_latency::cpu1.inst 74743.670164 # average overall miss latency 2372system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132189.436870 # average overall miss latency 2373system.l2c.demand_avg_miss_latency::total 96387.400856 # average overall miss latency 2374system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80223.765432 # average overall miss latency |
| 2225system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency | 2375system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency |
| 2226system.l2c.overall_avg_miss_latency::cpu0.inst 85130.213992 # average overall miss latency 2227system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107688.422782 # average overall miss latency 2228system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74625 # average overall miss latency 2229system.l2c.overall_avg_miss_latency::cpu1.inst 76041.247748 # average overall miss latency 2230system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109397.775213 # average overall miss latency 2231system.l2c.overall_avg_miss_latency::total 104725.610180 # average overall miss latency | 2376system.l2c.overall_avg_miss_latency::cpu0.inst 77013.239218 # average overall miss latency 2377system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 102926.833645 # average overall miss latency 2378system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80020.833333 # average overall miss latency 2379system.l2c.overall_avg_miss_latency::cpu1.inst 74743.670164 # average overall miss latency 2380system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132189.436870 # average overall miss latency 2381system.l2c.overall_avg_miss_latency::total 96387.400856 # average overall miss latency |
| 2232system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2233system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2234system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2235system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2236system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2237system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2238system.l2c.fast_writes 0 # number of fast writes performed 2239system.l2c.cache_copies 0 # number of cache copies performed | 2382system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2383system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2384system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2385system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2386system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2387system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2388system.l2c.fast_writes 0 # number of fast writes performed 2389system.l2c.cache_copies 0 # number of cache copies performed |
| 2240system.l2c.writebacks::writebacks 110752 # number of writebacks 2241system.l2c.writebacks::total 110752 # number of writebacks 2242system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadReq MSHR hits 2243system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 2244system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits 2245system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 2246system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits 2247system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 2248system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 161 # number of ReadReq MSHR misses | 2390system.l2c.writebacks::writebacks 104097 # number of writebacks 2391system.l2c.writebacks::total 104097 # number of writebacks 2392system.l2c.ReadReq_mshr_hits::cpu0.inst 8 # number of ReadReq MSHR hits 2393system.l2c.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits 2394system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 2395system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits 2396system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits 2397system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 2398system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits 2399system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits 2400system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits 2401system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 162 # number of ReadReq MSHR misses |
| 2249system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses | 2402system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses |
| 2250system.l2c.ReadReq_mshr_misses::cpu0.inst 11256 # number of ReadReq MSHR misses 2251system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 169616 # number of ReadReq MSHR misses 2252system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 8 # number of ReadReq MSHR misses 2253system.l2c.ReadReq_mshr_misses::cpu1.inst 1341 # number of ReadReq MSHR misses 2254system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 17501 # number of ReadReq MSHR misses 2255system.l2c.ReadReq_mshr_misses::total 199884 # number of ReadReq MSHR misses 2256system.l2c.UpgradeReq_mshr_misses::cpu0.inst 9580 # number of UpgradeReq MSHR misses 2257system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2241 # number of UpgradeReq MSHR misses 2258system.l2c.UpgradeReq_mshr_misses::total 11821 # number of UpgradeReq MSHR misses 2259system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 527 # number of SCUpgradeReq MSHR misses 2260system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1214 # number of SCUpgradeReq MSHR misses 2261system.l2c.SCUpgradeReq_mshr_misses::total 1741 # number of SCUpgradeReq MSHR misses 2262system.l2c.ReadExReq_mshr_misses::cpu0.inst 6969 # number of ReadExReq MSHR misses 2263system.l2c.ReadExReq_mshr_misses::cpu1.inst 6429 # number of ReadExReq MSHR misses 2264system.l2c.ReadExReq_mshr_misses::total 13398 # number of ReadExReq MSHR misses 2265system.l2c.demand_mshr_misses::cpu0.dtb.walker 161 # number of demand (read+write) MSHR misses | 2403system.l2c.ReadReq_mshr_misses::cpu0.inst 32540 # number of ReadReq MSHR misses 2404system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 136690 # number of ReadReq MSHR misses 2405system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 12 # number of ReadReq MSHR misses 2406system.l2c.ReadReq_mshr_misses::cpu1.inst 3330 # number of ReadReq MSHR misses 2407system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of ReadReq MSHR misses 2408system.l2c.ReadReq_mshr_misses::total 178984 # number of ReadReq MSHR misses 2409system.l2c.UpgradeReq_mshr_misses::cpu0.inst 8970 # number of UpgradeReq MSHR misses 2410system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2734 # number of UpgradeReq MSHR misses 2411system.l2c.UpgradeReq_mshr_misses::total 11704 # number of UpgradeReq MSHR misses 2412system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 618 # number of SCUpgradeReq MSHR misses 2413system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1189 # number of SCUpgradeReq MSHR misses 2414system.l2c.SCUpgradeReq_mshr_misses::total 1807 # number of SCUpgradeReq MSHR misses 2415system.l2c.ReadExReq_mshr_misses::cpu0.inst 11575 # number of ReadExReq MSHR misses 2416system.l2c.ReadExReq_mshr_misses::cpu1.inst 8676 # number of ReadExReq MSHR misses 2417system.l2c.ReadExReq_mshr_misses::total 20251 # number of ReadExReq MSHR misses 2418system.l2c.demand_mshr_misses::cpu0.dtb.walker 162 # number of demand (read+write) MSHR misses |
| 2266system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses | 2419system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses |
| 2267system.l2c.demand_mshr_misses::cpu0.inst 18225 # number of demand (read+write) MSHR misses 2268system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 169616 # number of demand (read+write) MSHR misses 2269system.l2c.demand_mshr_misses::cpu1.dtb.walker 8 # number of demand (read+write) MSHR misses 2270system.l2c.demand_mshr_misses::cpu1.inst 7770 # number of demand (read+write) MSHR misses 2271system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 17501 # number of demand (read+write) MSHR misses 2272system.l2c.demand_mshr_misses::total 213282 # number of demand (read+write) MSHR misses 2273system.l2c.overall_mshr_misses::cpu0.dtb.walker 161 # number of overall MSHR misses | 2420system.l2c.demand_mshr_misses::cpu0.inst 44115 # number of demand (read+write) MSHR misses 2421system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 136690 # number of demand (read+write) MSHR misses 2422system.l2c.demand_mshr_misses::cpu1.dtb.walker 12 # number of demand (read+write) MSHR misses 2423system.l2c.demand_mshr_misses::cpu1.inst 12006 # number of demand (read+write) MSHR misses 2424system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of demand (read+write) MSHR misses 2425system.l2c.demand_mshr_misses::total 199235 # number of demand (read+write) MSHR misses 2426system.l2c.overall_mshr_misses::cpu0.dtb.walker 162 # number of overall MSHR misses |
| 2274system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses | 2427system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses |
| 2275system.l2c.overall_mshr_misses::cpu0.inst 18225 # number of overall MSHR misses 2276system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 169616 # number of overall MSHR misses 2277system.l2c.overall_mshr_misses::cpu1.dtb.walker 8 # number of overall MSHR misses 2278system.l2c.overall_mshr_misses::cpu1.inst 7770 # number of overall MSHR misses 2279system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 17501 # number of overall MSHR misses 2280system.l2c.overall_mshr_misses::total 213282 # number of overall MSHR misses 2281system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10828000 # number of ReadReq MSHR miss cycles | 2428system.l2c.overall_mshr_misses::cpu0.inst 44115 # number of overall MSHR misses 2429system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 136690 # number of overall MSHR misses 2430system.l2c.overall_mshr_misses::cpu1.dtb.walker 12 # number of overall MSHR misses 2431system.l2c.overall_mshr_misses::cpu1.inst 12006 # number of overall MSHR misses 2432system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of overall MSHR misses 2433system.l2c.overall_mshr_misses::total 199235 # number of overall MSHR misses 2434system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10991250 # number of ReadReq MSHR miss cycles |
| 2282system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles | 2435system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles |
| 2283system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 817788246 # number of ReadReq MSHR miss cycles 2284system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16174111957 # number of ReadReq MSHR miss cycles 2285system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 500000 # number of ReadReq MSHR miss cycles 2286system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 96492250 # number of ReadReq MSHR miss cycles 2287system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1701029964 # number of ReadReq MSHR miss cycles 2288system.l2c.ReadReq_mshr_miss_latency::total 18800812917 # number of ReadReq MSHR miss cycles 2289system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 97817994 # number of UpgradeReq MSHR miss cycles 2290system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 22626723 # number of UpgradeReq MSHR miss cycles 2291system.l2c.UpgradeReq_mshr_miss_latency::total 120444717 # number of UpgradeReq MSHR miss cycles 2292system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 5423023 # number of SCUpgradeReq MSHR miss cycles 2293system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 12163710 # number of SCUpgradeReq MSHR miss cycles 2294system.l2c.SCUpgradeReq_mshr_miss_latency::total 17586733 # number of SCUpgradeReq MSHR miss cycles 2295system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 506879094 # number of ReadExReq MSHR miss cycles 2296system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 396754755 # number of ReadExReq MSHR miss cycles 2297system.l2c.ReadExReq_mshr_miss_latency::total 903633849 # number of ReadExReq MSHR miss cycles 2298system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10828000 # number of demand (read+write) MSHR miss cycles | 2436system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 2034453239 # number of ReadReq MSHR miss cycles 2437system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12379828891 # number of ReadReq MSHR miss cycles 2438system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 810750 # number of ReadReq MSHR miss cycles 2439system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 216209999 # number of ReadReq MSHR miss cycles 2440system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 749741791 # number of ReadReq MSHR miss cycles 2441system.l2c.ReadReq_mshr_miss_latency::total 15392098420 # number of ReadReq MSHR miss cycles 2442system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 91762404 # number of UpgradeReq MSHR miss cycles 2443system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 27532715 # number of UpgradeReq MSHR miss cycles 2444system.l2c.UpgradeReq_mshr_miss_latency::total 119295119 # number of UpgradeReq MSHR miss cycles 2445system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 6310115 # number of SCUpgradeReq MSHR miss cycles 2446system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 11917186 # number of SCUpgradeReq MSHR miss cycles 2447system.l2c.SCUpgradeReq_mshr_miss_latency::total 18227301 # number of SCUpgradeReq MSHR miss cycles 2448system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 807808323 # number of ReadExReq MSHR miss cycles 2449system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 530171012 # number of ReadExReq MSHR miss cycles 2450system.l2c.ReadExReq_mshr_miss_latency::total 1337979335 # number of ReadExReq MSHR miss cycles 2451system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10991250 # number of demand (read+write) MSHR miss cycles |
| 2299system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles | 2452system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles |
| 2300system.l2c.demand_mshr_miss_latency::cpu0.inst 1324667340 # number of demand (read+write) MSHR miss cycles 2301system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16174111957 # number of demand (read+write) MSHR miss cycles 2302system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 500000 # number of demand (read+write) MSHR miss cycles 2303system.l2c.demand_mshr_miss_latency::cpu1.inst 493247005 # number of demand (read+write) MSHR miss cycles 2304system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1701029964 # number of demand (read+write) MSHR miss cycles 2305system.l2c.demand_mshr_miss_latency::total 19704446766 # number of demand (read+write) MSHR miss cycles 2306system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10828000 # number of overall MSHR miss cycles | 2453system.l2c.demand_mshr_miss_latency::cpu0.inst 2842261562 # number of demand (read+write) MSHR miss cycles 2454system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12379828891 # number of demand (read+write) MSHR miss cycles 2455system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 810750 # number of demand (read+write) MSHR miss cycles 2456system.l2c.demand_mshr_miss_latency::cpu1.inst 746381011 # number of demand (read+write) MSHR miss cycles 2457system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 749741791 # number of demand (read+write) MSHR miss cycles 2458system.l2c.demand_mshr_miss_latency::total 16730077755 # number of demand (read+write) MSHR miss cycles 2459system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10991250 # number of overall MSHR miss cycles |
| 2307system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles | 2460system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles |
| 2308system.l2c.overall_mshr_miss_latency::cpu0.inst 1324667340 # number of overall MSHR miss cycles 2309system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16174111957 # number of overall MSHR miss cycles 2310system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 500000 # number of overall MSHR miss cycles 2311system.l2c.overall_mshr_miss_latency::cpu1.inst 493247005 # number of overall MSHR miss cycles 2312system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1701029964 # number of overall MSHR miss cycles 2313system.l2c.overall_mshr_miss_latency::total 19704446766 # number of overall MSHR miss cycles 2314system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5522428749 # number of ReadReq MSHR uncacheable cycles 2315system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 260648000 # number of ReadReq MSHR uncacheable cycles 2316system.l2c.ReadReq_mshr_uncacheable_latency::total 5783076749 # number of ReadReq MSHR uncacheable cycles 2317system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4102579499 # number of WriteReq MSHR uncacheable cycles 2318system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 146450000 # number of WriteReq MSHR uncacheable cycles 2319system.l2c.WriteReq_mshr_uncacheable_latency::total 4249029499 # number of WriteReq MSHR uncacheable cycles 2320system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9625008248 # number of overall MSHR uncacheable cycles 2321system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 407098000 # number of overall MSHR uncacheable cycles 2322system.l2c.overall_mshr_uncacheable_latency::total 10032106248 # number of overall MSHR uncacheable cycles 2323system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.218453 # mshr miss rate for ReadReq accesses 2324system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.007576 # mshr miss rate for ReadReq accesses 2325system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.221684 # mshr miss rate for ReadReq accesses 2326system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.433957 # mshr miss rate for ReadReq accesses 2327system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.078431 # mshr miss rate for ReadReq accesses 2328system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.162723 # mshr miss rate for ReadReq accesses 2329system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402822 # mshr miss rate for ReadReq accesses 2330system.l2c.ReadReq_mshr_miss_rate::total 0.404369 # mshr miss rate for ReadReq accesses 2331system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.448460 # mshr miss rate for UpgradeReq accesses 2332system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.823292 # mshr miss rate for UpgradeReq accesses 2333system.l2c.UpgradeReq_mshr_miss_rate::total 0.490824 # mshr miss rate for UpgradeReq accesses 2334system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.741210 # mshr miss rate for SCUpgradeReq accesses 2335system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.863442 # mshr miss rate for SCUpgradeReq accesses 2336system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.822390 # mshr miss rate for SCUpgradeReq accesses 2337system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.656524 # mshr miss rate for ReadExReq accesses 2338system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.876244 # mshr miss rate for ReadExReq accesses 2339system.l2c.ReadExReq_mshr_miss_rate::total 0.746324 # mshr miss rate for ReadExReq accesses 2340system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.218453 # mshr miss rate for demand accesses 2341system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.007576 # mshr miss rate for demand accesses 2342system.l2c.demand_mshr_miss_rate::cpu0.inst 0.296872 # mshr miss rate for demand accesses 2343system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.433957 # mshr miss rate for demand accesses 2344system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.078431 # mshr miss rate for demand accesses 2345system.l2c.demand_mshr_miss_rate::cpu1.inst 0.498780 # mshr miss rate for demand accesses 2346system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402822 # mshr miss rate for demand accesses 2347system.l2c.demand_mshr_miss_rate::total 0.416353 # mshr miss rate for demand accesses 2348system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.218453 # mshr miss rate for overall accesses 2349system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.007576 # mshr miss rate for overall accesses 2350system.l2c.overall_mshr_miss_rate::cpu0.inst 0.296872 # mshr miss rate for overall accesses 2351system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.433957 # mshr miss rate for overall accesses 2352system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.078431 # mshr miss rate for overall accesses 2353system.l2c.overall_mshr_miss_rate::cpu1.inst 0.498780 # mshr miss rate for overall accesses 2354system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402822 # mshr miss rate for overall accesses 2355system.l2c.overall_mshr_miss_rate::total 0.416353 # mshr miss rate for overall accesses 2356system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385 # average ReadReq mshr miss latency | 2461system.l2c.overall_mshr_miss_latency::cpu0.inst 2842261562 # number of overall MSHR miss cycles 2462system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12379828891 # number of overall MSHR miss cycles 2463system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 810750 # number of overall MSHR miss cycles 2464system.l2c.overall_mshr_miss_latency::cpu1.inst 746381011 # number of overall MSHR miss cycles 2465system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 749741791 # number of overall MSHR miss cycles 2466system.l2c.overall_mshr_miss_latency::total 16730077755 # number of overall MSHR miss cycles 2467system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5519244498 # number of ReadReq MSHR uncacheable cycles 2468system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 263262750 # number of ReadReq MSHR uncacheable cycles 2469system.l2c.ReadReq_mshr_uncacheable_latency::total 5782507248 # number of ReadReq MSHR uncacheable cycles 2470system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4096891000 # number of WriteReq MSHR uncacheable cycles 2471system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 150604000 # number of WriteReq MSHR uncacheable cycles 2472system.l2c.WriteReq_mshr_uncacheable_latency::total 4247495000 # number of WriteReq MSHR uncacheable cycles 2473system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9616135498 # number of overall MSHR uncacheable cycles 2474system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 413866750 # number of overall MSHR uncacheable cycles 2475system.l2c.overall_mshr_uncacheable_latency::total 10030002248 # number of overall MSHR uncacheable cycles 2476system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for ReadReq accesses 2477system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for ReadReq accesses 2478system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.315304 # mshr miss rate for ReadReq accesses 2479system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for ReadReq accesses 2480system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for ReadReq accesses 2481system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.121800 # mshr miss rate for ReadReq accesses 2482system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for ReadReq accesses 2483system.l2c.ReadReq_mshr_miss_rate::total 0.500587 # mshr miss rate for ReadReq accesses 2484system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.753275 # mshr miss rate for UpgradeReq accesses 2485system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.806014 # mshr miss rate for UpgradeReq accesses 2486system.l2c.UpgradeReq_mshr_miss_rate::total 0.764967 # mshr miss rate for UpgradeReq accesses 2487system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.813158 # mshr miss rate for SCUpgradeReq accesses 2488system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.871062 # mshr miss rate for SCUpgradeReq accesses 2489system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.850353 # mshr miss rate for SCUpgradeReq accesses 2490system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.750795 # mshr miss rate for ReadExReq accesses 2491system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.866906 # mshr miss rate for ReadExReq accesses 2492system.l2c.ReadExReq_mshr_miss_rate::total 0.796500 # mshr miss rate for ReadExReq accesses 2493system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for demand accesses 2494system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for demand accesses 2495system.l2c.demand_mshr_miss_rate::cpu0.inst 0.371905 # mshr miss rate for demand accesses 2496system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for demand accesses 2497system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for demand accesses 2498system.l2c.demand_mshr_miss_rate::cpu1.inst 0.321463 # mshr miss rate for demand accesses 2499system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for demand accesses 2500system.l2c.demand_mshr_miss_rate::total 0.520232 # mshr miss rate for demand accesses 2501system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for overall accesses 2502system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for overall accesses 2503system.l2c.overall_mshr_miss_rate::cpu0.inst 0.371905 # mshr miss rate for overall accesses 2504system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for overall accesses 2505system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for overall accesses 2506system.l2c.overall_mshr_miss_rate::cpu1.inst 0.321463 # mshr miss rate for overall accesses 2507system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for overall accesses 2508system.l2c.overall_mshr_miss_rate::total 0.520232 # mshr miss rate for overall accesses 2509system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average ReadReq mshr miss latency |
| 2357system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency | 2510system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency |
| 2358system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72653.539979 # average ReadReq mshr miss latency 2359system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average ReadReq mshr miss latency 2360system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency 2361system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71955.443699 # average ReadReq mshr miss latency 2362system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average ReadReq mshr miss latency 2363system.l2c.ReadReq_avg_mshr_miss_latency::total 94058.618584 # average ReadReq mshr miss latency 2364system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10210.646555 # average UpgradeReq mshr miss latency 2365system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10096.708166 # average UpgradeReq mshr miss latency 2366system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10189.046358 # average UpgradeReq mshr miss latency 2367system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10290.366224 # average SCUpgradeReq mshr miss latency 2368system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10019.530478 # average SCUpgradeReq mshr miss latency 2369system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10101.512349 # average SCUpgradeReq mshr miss latency 2370system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72733.404219 # average ReadExReq mshr miss latency 2371system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61713.292114 # average ReadExReq mshr miss latency 2372system.l2c.ReadExReq_avg_mshr_miss_latency::total 67445.428348 # average ReadExReq mshr miss latency 2373system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385 # average overall mshr miss latency | 2511system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 62521.611524 # average ReadReq mshr miss latency 2512system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average ReadReq mshr miss latency 2513system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average ReadReq mshr miss latency 2514system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64927.927628 # average ReadReq mshr miss latency 2515system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average ReadReq mshr miss latency 2516system.l2c.ReadReq_avg_mshr_miss_latency::total 85997.063536 # average ReadReq mshr miss latency 2517system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10229.922408 # average UpgradeReq mshr miss latency 2518system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10070.488296 # average UpgradeReq mshr miss latency 2519system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10192.679340 # average UpgradeReq mshr miss latency 2520system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10210.542071 # average SCUpgradeReq mshr miss latency 2521system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10022.864592 # average SCUpgradeReq mshr miss latency 2522system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10087.050913 # average SCUpgradeReq mshr miss latency 2523system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 69789.055983 # average ReadExReq mshr miss latency 2524system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61107.769940 # average ReadExReq mshr miss latency 2525system.l2c.ReadExReq_avg_mshr_miss_latency::total 66069.790875 # average ReadExReq mshr miss latency 2526system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average overall mshr miss latency |
| 2374system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 2527system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 2375system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72684.079012 # average overall mshr miss latency 2376system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average overall mshr miss latency 2377system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency 2378system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63480.953024 # average overall mshr miss latency 2379system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average overall mshr miss latency 2380system.l2c.demand_avg_mshr_miss_latency::total 92386.824795 # average overall mshr miss latency 2381system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385 # average overall mshr miss latency | 2528system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64428.461113 # average overall mshr miss latency 2529system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average overall mshr miss latency 2530system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average overall mshr miss latency 2531system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62167.333916 # average overall mshr miss latency 2532system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average overall mshr miss latency 2533system.l2c.demand_avg_mshr_miss_latency::total 83971.580069 # average overall mshr miss latency 2534system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average overall mshr miss latency |
| 2382system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 2535system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 2383system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72684.079012 # average overall mshr miss latency 2384system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average overall mshr miss latency 2385system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency 2386system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63480.953024 # average overall mshr miss latency 2387system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average overall mshr miss latency 2388system.l2c.overall_avg_mshr_miss_latency::total 92386.824795 # average overall mshr miss latency | 2536system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64428.461113 # average overall mshr miss latency 2537system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average overall mshr miss latency 2538system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average overall mshr miss latency 2539system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62167.333916 # average overall mshr miss latency 2540system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average overall mshr miss latency 2541system.l2c.overall_avg_mshr_miss_latency::total 83971.580069 # average overall mshr miss latency |
| 2389system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 2390system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2391system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2392system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 2393system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 2394system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2395system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 2396system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2397system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2398system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 2542system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 2543system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2544system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2545system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency 2546system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency 2547system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2548system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 2549system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2550system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2551system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2399system.membus.trans_dist::ReadReq 238185 # Transaction distribution 2400system.membus.trans_dist::ReadResp 238185 # Transaction distribution 2401system.membus.trans_dist::WriteReq 30953 # Transaction distribution 2402system.membus.trans_dist::WriteResp 30953 # Transaction distribution 2403system.membus.trans_dist::Writeback 146942 # Transaction distribution | 2552system.membus.trans_dist::ReadReq 217279 # Transaction distribution 2553system.membus.trans_dist::ReadResp 217279 # Transaction distribution 2554system.membus.trans_dist::WriteReq 30939 # Transaction distribution 2555system.membus.trans_dist::WriteResp 30939 # Transaction distribution 2556system.membus.trans_dist::Writeback 140271 # Transaction distribution |
| 2404system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2405system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution | 2557system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2558system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 2406system.membus.trans_dist::UpgradeReq 78292 # Transaction distribution 2407system.membus.trans_dist::SCUpgradeReq 39832 # Transaction distribution 2408system.membus.trans_dist::UpgradeResp 13662 # Transaction distribution 2409system.membus.trans_dist::ReadExReq 30241 # Transaction distribution 2410system.membus.trans_dist::ReadExResp 13298 # Transaction distribution 2411system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 108000 # Packet count per connected master and slave (bytes) | 2559system.membus.trans_dist::UpgradeReq 75080 # Transaction distribution 2560system.membus.trans_dist::SCUpgradeReq 40217 # Transaction distribution 2561system.membus.trans_dist::UpgradeResp 13603 # Transaction distribution 2562system.membus.trans_dist::ReadExReq 40948 # Transaction distribution 2563system.membus.trans_dist::ReadExResp 20159 # Transaction distribution 2564system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) |
| 2412system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) | 2565system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) |
| 2413system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13634 # Packet count per connected master and slave (bytes) 2414system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 701758 # Packet count per connected master and slave (bytes) 2415system.membus.pkt_count_system.l2c.mem_side::total 823430 # Packet count per connected master and slave (bytes) 2416system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108896 # Packet count per connected master and slave (bytes) 2417system.membus.pkt_count_system.iocache.mem_side::total 108896 # Packet count per connected master and slave (bytes) 2418system.membus.pkt_count::total 932326 # Packet count per connected master and slave (bytes) 2419system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162880 # Cumulative packet size per connected master and slave (bytes) | 2566system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13590 # Packet count per connected master and slave (bytes) 2567system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 668031 # Packet count per connected master and slave (bytes) 2568system.membus.pkt_count_system.l2c.mem_side::total 789629 # Packet count per connected master and slave (bytes) 2569system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108880 # Packet count per connected master and slave (bytes) 2570system.membus.pkt_count_system.iocache.mem_side::total 108880 # Packet count per connected master and slave (bytes) 2571system.membus.pkt_count::total 898509 # Packet count per connected master and slave (bytes) 2572system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) |
| 2420system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) | 2573system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) |
| 2421system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27268 # Cumulative packet size per connected master and slave (bytes) 2422system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 20926892 # Cumulative packet size per connected master and slave (bytes) 2423system.membus.pkt_size_system.l2c.mem_side::total 21118256 # Cumulative packet size per connected master and slave (bytes) 2424system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 2425system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) 2426system.membus.pkt_size::total 25753712 # Cumulative packet size per connected master and slave (bytes) 2427system.membus.snoops 122070 # Total snoops (count) 2428system.membus.snoop_fanout::samples 531658 # Request fanout histogram | 2574system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27180 # Cumulative packet size per connected master and slave (bytes) 2575system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19605228 # Cumulative packet size per connected master and slave (bytes) 2576system.membus.pkt_size_system.l2c.mem_side::total 19796474 # Cumulative packet size per connected master and slave (bytes) 2577system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4634432 # Cumulative packet size per connected master and slave (bytes) 2578system.membus.pkt_size_system.iocache.mem_side::total 4634432 # Cumulative packet size per connected master and slave (bytes) 2579system.membus.pkt_size::total 24430906 # Cumulative packet size per connected master and slave (bytes) 2580system.membus.snoops 123136 # Total snoops (count) 2581system.membus.snoop_fanout::samples 511969 # Request fanout histogram |
| 2429system.membus.snoop_fanout::mean 1 # Request fanout histogram 2430system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2431system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2432system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 2582system.membus.snoop_fanout::mean 1 # Request fanout histogram 2583system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2584system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2585system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 2433system.membus.snoop_fanout::1 531658 100.00% 100.00% # Request fanout histogram | 2586system.membus.snoop_fanout::1 511969 100.00% 100.00% # Request fanout histogram |
| 2434system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2435system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2436system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2437system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 2587system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2588system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2589system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2590system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 2438system.membus.snoop_fanout::total 531658 # Request fanout histogram 2439system.membus.reqLayer0.occupancy 88755994 # Layer occupancy (ticks) | 2591system.membus.snoop_fanout::total 511969 # Request fanout histogram 2592system.membus.reqLayer0.occupancy 88887000 # Layer occupancy (ticks) |
| 2440system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 2593system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 2441system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) | 2594system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) |
| 2442system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 2595system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 2443system.membus.reqLayer2.occupancy 11894500 # Layer occupancy (ticks) | 2596system.membus.reqLayer2.occupancy 11855500 # Layer occupancy (ticks) |
| 2444system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 2597system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 2445system.membus.reqLayer5.occupancy 1935574499 # Layer occupancy (ticks) | 2598system.membus.reqLayer5.occupancy 1869891749 # Layer occupancy (ticks) |
| 2446system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) | 2599system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) |
| 2447system.membus.respLayer2.occupancy 2123782192 # Layer occupancy (ticks) | 2600system.membus.respLayer2.occupancy 2005520473 # Layer occupancy (ticks) |
| 2448system.membus.respLayer2.utilization 0.1 # Layer utilization (%) | 2601system.membus.respLayer2.utilization 0.1 # Layer utilization (%) |
| 2449system.membus.respLayer3.occupancy 38517394 # Layer occupancy (ticks) | 2602system.membus.respLayer3.occupancy 38480431 # Layer occupancy (ticks) |
| 2450system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2451system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2452system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2453system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2454system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2455system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2456system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2457system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 2474system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2475system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2476system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2477system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2478system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2479system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2480system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2481system.realview.ethernet.droppedPackets 0 # number of packets dropped | 2603system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2604system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2605system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2606system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2607system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2608system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2609system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2610system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 2627system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2628system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2629system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2630system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2631system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2632system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2633system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2634system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 2482system.toL2Bus.trans_dist::ReadReq 658320 # Transaction distribution 2483system.toL2Bus.trans_dist::ReadResp 658305 # Transaction distribution 2484system.toL2Bus.trans_dist::WriteReq 30953 # Transaction distribution 2485system.toL2Bus.trans_dist::WriteResp 30953 # Transaction distribution 2486system.toL2Bus.trans_dist::Writeback 250431 # Transaction distribution | 2635system.toL2Bus.trans_dist::ReadReq 516876 # Transaction distribution 2636system.toL2Bus.trans_dist::ReadResp 516861 # Transaction distribution 2637system.toL2Bus.trans_dist::WriteReq 30939 # Transaction distribution 2638system.toL2Bus.trans_dist::WriteResp 30939 # Transaction distribution 2639system.toL2Bus.trans_dist::Writeback 234152 # Transaction distribution |
| 2487system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution | 2640system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution |
| 2488system.toL2Bus.trans_dist::UpgradeReq 90455 # Transaction distribution 2489system.toL2Bus.trans_dist::SCUpgradeReq 40208 # Transaction distribution 2490system.toL2Bus.trans_dist::UpgradeResp 130663 # Transaction distribution 2491system.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution 2492system.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution 2493system.toL2Bus.trans_dist::ReadExReq 38633 # Transaction distribution 2494system.toL2Bus.trans_dist::ReadExResp 38633 # Transaction distribution 2495system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1411505 # Packet count per connected master and slave (bytes) 2496system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 304961 # Packet count per connected master and slave (bytes) 2497system.toL2Bus.pkt_count::total 1716466 # Packet count per connected master and slave (bytes) 2498system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 43486557 # Cumulative packet size per connected master and slave (bytes) 2499system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5753747 # Cumulative packet size per connected master and slave (bytes) 2500system.toL2Bus.pkt_size::total 49240304 # Cumulative packet size per connected master and slave (bytes) 2501system.toL2Bus.snoops 287552 # Total snoops (count) 2502system.toL2Bus.snoop_fanout::samples 1076220 # Request fanout histogram 2503system.toL2Bus.snoop_fanout::mean 1.033884 # Request fanout histogram 2504system.toL2Bus.snoop_fanout::stdev 0.180932 # Request fanout histogram | 2641system.toL2Bus.trans_dist::UpgradeReq 78584 # Transaction distribution 2642system.toL2Bus.trans_dist::SCUpgradeReq 40535 # Transaction distribution 2643system.toL2Bus.trans_dist::UpgradeResp 119119 # Transaction distribution 2644system.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution 2645system.toL2Bus.trans_dist::UpgradeFailResp 13 # Transaction distribution 2646system.toL2Bus.trans_dist::ReadExReq 51536 # Transaction distribution 2647system.toL2Bus.trans_dist::ReadExResp 51536 # Transaction distribution 2648system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1131248 # Packet count per connected master and slave (bytes) 2649system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 290761 # Packet count per connected master and slave (bytes) 2650system.toL2Bus.pkt_count::total 1422009 # Packet count per connected master and slave (bytes) 2651system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34509719 # Cumulative packet size per connected master and slave (bytes) 2652system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5415139 # Cumulative packet size per connected master and slave (bytes) 2653system.toL2Bus.pkt_size::total 39924858 # Cumulative packet size per connected master and slave (bytes) 2654system.toL2Bus.snoops 285546 # Total snoops (count) 2655system.toL2Bus.snoop_fanout::samples 919868 # Request fanout histogram 2656system.toL2Bus.snoop_fanout::mean 1.039644 # Request fanout histogram 2657system.toL2Bus.snoop_fanout::stdev 0.195121 # Request fanout histogram |
| 2505system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2506system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 2658system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2659system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 2507system.toL2Bus.snoop_fanout::1 1039753 96.61% 96.61% # Request fanout histogram 2508system.toL2Bus.snoop_fanout::2 36467 3.39% 100.00% # Request fanout histogram | 2660system.toL2Bus.snoop_fanout::1 883401 96.04% 96.04% # Request fanout histogram 2661system.toL2Bus.snoop_fanout::2 36467 3.96% 100.00% # Request fanout histogram |
| 2509system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2510system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2511system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 2662system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2663system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2664system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 2512system.toL2Bus.snoop_fanout::total 1076220 # Request fanout histogram 2513system.toL2Bus.reqLayer0.occupancy 1573537018 # Layer occupancy (ticks) | 2665system.toL2Bus.snoop_fanout::total 919868 # Request fanout histogram 2666system.toL2Bus.reqLayer0.occupancy 1489301846 # Layer occupancy (ticks) |
| 2514system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2515system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks) 2516system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2667system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2668system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks) 2669system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2517system.toL2Bus.respLayer0.occupancy 2438104006 # Layer occupancy (ticks) | 2670system.toL2Bus.respLayer0.occupancy 1891845782 # Layer occupancy (ticks) |
| 2518system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 2671system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 2519system.toL2Bus.respLayer1.occupancy 680349684 # Layer occupancy (ticks) | 2672system.toL2Bus.respLayer1.occupancy 645358377 # Layer occupancy (ticks) |
| 2520system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2521 2522---------- End Simulation Statistics ---------- | 2673system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2674 2675---------- End Simulation Statistics ---------- |